nature electronics

Perspective https://doi.org/10.1038/s41928-024-01277-y

The development of general-purpose

brain-inspired computing

Received: 5 May 2023 Weihao Zhang 1,2,3,4,5,7, Songchen Ma , Xinglong Ji1,2,3,4,5, Xue Liu1,2,3,4,5,
1,2,3,4,5,7

Yuqing Cong1,6 & Luping Shi 1,2,3,4,5

Accepted: 2 October 2024

Published online: 7 November 2024

Brain-inspired computing uses insights from neuroscience to develop more
Check for updates efficient computing systems. The approach is of use in a broad range of
applications—from neural simulation to intelligent computing—and could
potentially be used to create a general-purpose computing infrastructure.
Here we explore the development of general-purpose brain-inspired
computing. We examine the hardware and software that have so far been
used to create brain-inspired computing systems. We then consider the
potential of combining approaches from neuro­science and computer
science to build general-purpose brain-inspired computing systems,
highlighting three areas: temporal, spatial and spatiotemporal capabilities;
approximate computing and precise computing; and control flow and
data flow. Finally, we discuss initiatives that will be needed to develop
general-purpose brain-inspired computing, highlighting three potential
strategies: application-level pattern generalization, hardware-level
structural generalization and software-level systematic generalization.

Brain-inspired computing1, which is also known as neuromorphic diversity in workloads, to accommodate different resource demands
computing, aims to mimic biological mechanisms to provide new in terms of computation, storage and other computing resources;
approaches to studying the brain and developing artificial intelligent and diversity in performance requirements, to encompass specific
systems. Initially, neuromorphic research primarily sought to replicate requirements for latency, throughput and power consumption.
or validate biological findings on hardware platforms, with insights A practical general-purpose system should also offer programmability
from neuroscience guiding the development of such systems2,3. The that allows convenient deployment of applications and flexible control
recent explosion of big data, along with new technologies such as over computing resources.
artificial intelligence and the Internet of Things, has led to a surge in Modern computing models tend to solve problems through a
demand for high-performance computing, and thus researchers have control-flow mechanism with fast instruction and state switching,
also turned to brain-inspired computing as a potential approach to which leverages temporal processing capabilities. Parallelism of such
deliver more efficient computing systems. Brain-inspired computing a computing model is typically achieved by replicating control-flow
could be of use in a broad range of applications4 and could provide a processes or directing multiple uniform data operations with one
basis for future computing infrastructures5. But what would it take to control-flow process. In contrast, the human brain relies on mas-
develop general-purpose brain-inspired computing (GPBIC)? sively interconnected neurons that transmit information via sparse
A general-purpose system needs to address the diversity of prac- spikes. Dynamic topology and neural dynamics play a crucial role in
tical applications. This includes diversity in functionality, to support intelligence6,7, and the temporal correlation of spikes establishes the
a range of functions and algorithms with acceptable performance; basis for learning. In essence, the brain tends to solve problems by

1
Center for Brain-inspired Computing Research (CBICR), Tsinghua University, Beijing, China. 2Department of Precision Instruments, Tsinghua University,
Beijing, China. 3Optical Memory National Engineering Research Center, Tsinghua University, Beijing, China. 4Tsinghua University- China Electronics
Technology HIK Group Co. Joint Research Center for Brian-inspired Computing, Tsinghua University, Beijing, China. 5IDG/McGovern Institute for Brain
Research at Tsinghua University, Beijing, China. 6Department of Computer Science and Technology, Tsinghua University, Beijing, China. 7These authors
contributed equally: Weihao Zhang, Songchen Ma. e-mail: [email protected]

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Perspective https://doi.org/10.1038/s41928-024-01277-y

Application scope synaptic dynamics, types and numbers of ion channels and compart-
Neuroscience Intelligence General ments), the number of modelling neurons, the density and complexity
of connections, and timing on multiple scales (such as long- and short-
term synaptic plasticity). These factors affect the circuit designs and
Brain Classical
paradigm neuromorphic final performance.
engineering When designing chips, researchers typically address design
Brain-
inspired trade-offs from two perspectives: research goals and biological
computing references (such as spike firing rates, the locality of neuronal con-
Dual-driven
Dual-driven nections and cortex orientation references). This leads to each chip
paradigm
brain-inspired computing
being designed with common metrics, while also having its specific
focus (Fig. 2).
Computer Initially, neuromorphic engineering focused on developing neuro-
paradigm Dedicated Classical
super- morphic sensors such as artificial retinas or cochlea based on relatively
computing computing
established biological principles. Among various neuromorphic sen-
sors, visual sensors have received the most attention (such as DVS10,
Paradigm ATIS11, CeleX12, Vidar13 and Tianmouc14) and have then been designed by
Fig. 1 | Guiding paradigms and applications of brain-inspired computing. drawing from the peripheral perception of motion and the fine texture
Neuromorphic engineering has historically been guided by brain paradigms, and pattern recognition function of the central fovea. These sensors
replicating features or functions of biological nervous systems for exploring serve as effective interfaces between the environment and cognitive
neuroscience and accelerating intelligent tasks. Beyond these, the fusion of systems with sensitivity to dynamic signals and substantially reduce
computational paradigms inherent to both the brain and classical computers signal processing complexity and communication costs.
could lead to the efficient and flexible management of a broader range of general- When modelling a small-scale network of silicon neurons, a hard-
purpose tasks. wired approach usually suffices15. However, a programmable approach
is necessary to model different types of neuron, ion channel and
dynamic connection with growing complexity. To meet this demand,
adopting spatiotemporal processing capabilities, integrating memory different technical approaches are adopted. Analogue circuits are effi-
and computation efficiently in an event-driven data-flow manner. cient at implementing dynamic and differential processes with various
Thus, a promising approach to developing an advanced computing time constants, making them suitable for building spiking neurons with
system—and GPBIC—is to combine features of modern computers and rich spatiotemporal complexity (such as Neurogrid16, BrainScaleS17
the human brain8 (Fig. 1). (formerly known as FACETS18,19) and DYNAPs20). To model more neurons
In this Perspective, we examine the development of brain-inspired within a limited area, various circuit-sharing and parameter-sharing
computing and consider the hardware and software that could pro- techniques have been developed16. Furthermore, many-core architec-
vide a foundation for GPBIC. We explore the potential of combining tures with a hierarchical communication infrastructure21 have been
approaches from neuroscience and computer science to build GPBIC, employed for higher scalability, while digital circuits provide more
highlighting three areas: temporal, spatial and spatiotemporal capabili- reliable and reconfigurable connections.
ties; approximate computing and precise computing; and control flow The inter-chip communication bandwidth is an important factor of
and data flow. Finally, we consider the short-term and long-term initia- neuromorphic chips. Inspired by supercomputers, SpiNNaker22 organ-
tives that will be required to develop GPBIC, highlighting three poten- izes large-scale digital-logic neurons instead of implementing specific
tial strategies: application-level pattern generalization, hardware-level neuron circuits. It consists of optimized advanced RISC machine (ARM)
structural generalization and software-level systematic generalization. processors interconnected through multiple levels of communication
infrastructure. Owing to resource limits, the design of neuromorphic
The development of brain-inspired computing chips with large-scale neurons and synapses involves a careful bal-
The field of brain-inspired computing has undergone considerable ance of various trade-offs, such as circuit complexity, communication
developments along four main routes (Fig. 2). Initially, it centred around bandwidth and energy efficiency, to achieve optimal performance for
neuromorphic sensing engineering, then advanced to brain simula- a specific application.
tion and intelligent computing, and more recently, general-purpose In light of the advancements in big data and artificial intelli-
computing. We highlight here the key hardware and software advances gence, coupled with the end of Moore’s law, the field of intelligent
along each of these routes, as well as the construction of large-scale computing23–25 has garnered considerable attention within the
computing systems. (Note, algorithms are not covered in this article, brain-inspired computing community. Along this route, there has been
and have been documented extensively elsewhere4,9.) a noticeable shift in the emphasis on hardware design objectives. Ini-
tially centred on replicating biological behaviour with complex neuro-
Hardware scientific modelling, the current emphasis is on practical applications
The precise mechanism underlying the brain’s computational power with simplified neuron models26,27. This has led to the development of
remains unclear, but it is believed to arise from the coordinated activity several chips using fully digital circuits to build logic neurons (such as
of numerous neurons and their connections, which undergo dynamic TrueNorth28,29, IMPULSE30, Tianjic31, Darwin32,33, Novena34 and µBrain35).
changes in connection strength and availability to support learning TrueNorth features a hybrid synchro–asynchronous architecture for
and adaptability. increased neuron capacity and multi-chip scalability. Loihi-136 offers
To emulate this process in hardware, researchers aim to replicate a specialized instruction set, facilitating the programming of various
the brain’s structural features to create a computational substrate local learning rules. ODIN37 supports long-term potentiation and 20
as well as to explore neural mechanisms. The primary challenge is to different neuronal models with Izhikevich response behaviours.
construct a functional processor that can organize a large number of Recent advances in network-level hardware and increasing appli-
fine-grained parallel computing units with intrinsic temporal dynam- cation demands have led to the development of hardware designs for
ics. Constraints imposed by manufacturing and limited resources general-purpose computing. To improve the practicality of neuro-
require careful consideration of trade-offs across multiple aspects, morphic computing, heterogeneous hardware has been developed8
such as the granularity of neuron modelling (such as neuron and by acting as a co-processor and accelerating specific workloads under

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central processing unit (CPU) or field-programmable gate array (FPGA) programming frameworks and algorithm abstractions for convenient
control8,38. For example, BrainScaleS utilizes a reduced instruction modelling and hardware-agnostic development of brain-inspired algo-
set computer (RISC) CPU for reward-based learning39, while Loihi-140 rithms; compilers for efficiently deploying algorithms on specific or
directly integrates three embedded x86 processor cores on the chip various hardware with compatibility; runtimes and operating systems
to facilitate communication and encodings between conventional for flexible and dynamic task commitment and resource management;
computing and spike-based neuromorphic computing. SpiNNaker hardware abstractions for decoupling hardware details from other
is a specialized supercomputer based on ARM processors, balancing software and providing low-level control interfaces; and hardware
between general-purpose computing and dedicated parallel design. simulators and design tools for facilitating the engineering of systems.
Fusion with modern computing has also become a widely adopted We examine here the first four types of system software along each
strategy to extend applications of brain-inspired computing hardware. route (Fig. 2).
Tianjic41,42, for instance, achieves efficient support for artificial neural Route I emphasizes the use of hard-wiring neural models, mini-
networks (ANNs), spiking neural networks (SNNs) and hybrid models, mizing the reliance on software, whereas route II prioritizes the pro-
providing a unified computing platform catering to both computer grammability and configurability of deploying diverse neural models.
science and neuroscience research. It establishes a unified algorithmic To enable the rapid construction and analysis of these models, vari-
framework, operator representation and resource-shared circuit archi- ous simulation frameworks, including GENESIS59, NEURON60, NEST61,
tecture that leverages the strengths of both computing paradigms. PyNN62 and Brian63,64, have been developed. Modelling theories, such as
Some chips also incorporate a similar hybrid architecture, includ- NEF50, have also been established for dynamic modelling, leading to the
ing Shenjing43, NEUBULA44, SpiNNaker-245, Loihi-246, BrainScaleS-247 creation of practical modelling frameworks such as Nengo65. In route II,
and TCAS-II202148. Approximating general functions with neural net- toolchains are used to identify appropriate hardware configurations
works is another approach to realizing general computing. One such that match hardware behaviours and simulation expectations66,67. Spe-
example is Braindrop49, a chip designed specifically for the Neural cifically, some research in this area focuses on parameter calibration of
Engineering Framework50 (NEF) to enable neural networks to generi- analogue circuits or analogue–digital mixed circuits49,68, and runtime
cally approximate functions through system dynamics with minimal systems have been developed to accommodate various drivers and
computation cost. These efforts collectively highlight a growing effort interacting modes of the hardware67,69–71.
towards advancing general computing and expanding the applications Route III places greater emphasis on abstraction for improving
of brain-inspired hardware. portability, programmability and performance. Algorithm abstrac-
The deceleration of Moore’s law has made the continued tions enhance the modularity and composability of constructing SNNs.
miniaturization of transistors both physically and economically Hybrid support for ANNs and SNNs is one of the important research
unsustainable. Consequently, various post-complementary metal– topics across all system levels72. For instance, frameworks such as
oxide–semiconductor (CMOS) technologies have emerged51–53, such as Spyketorch73 and SpkingJelly74 integrate SNN modelling and training
redox-based resistive random-access memory, phase-change memo- with established ANN frameworks. Hardware abstractions, ranging
ries, spin-transfer torque magneto resistive random-access memory, from inference to learning instruction set75, play a key role in improving
and memristors. These technologies offer potential solutions to the system functionality. Some abstractions focus on the structural and
demands of brain-inspired computing for high computational density behavioural features of the hardware, such as Corelet25, and establish a
and low power consumption. Optical memristors, alongside their comprehensive low-level programming/execution model. The execu-
electronic counterparts, offer significant benefits, including high tion model provides concrete and operable interfaces that enable the
bandwidth, low crosstalk and fast speeds, paving the way for all-optical runtime and operating system to achieve flexible task scheduling and
brain-inspired computing, such as photonic tensor cores54. Recently, resource allocation42,76. Finally, compilers link high-level representa-
fully parallel on-chip neural networks have been implemented by mem- tions and low-level abstractions to map neural tasks on massive parallel
ristors, making substantial progress in the feasibility and diversity of infrastructures, satisfying diverse resource constraints and achieving
memristor systems55,56. Compared with CMOS technology, memristive load-balancing for high performance29,75,77–79.
circuits show superior power and area efficiency, particularly for matrix Route IV introduces novel abstractions that facilitate general-
multiplication and accumulation tasks. They can serve as independent purpose computing using brain-inspired patterns. Two primary
processors or co-processors to accelerate neural networks, boosting approaches are used: embedding general computer languages into
computing efficiency in in-memory or near-memory computing57. the neural network structure80,81 and utilizing brain-inspired repre-
However, achieving versatility for general-purpose computations sentations to approximate general functions82,83. While compilers
still requires additional CMOS circuitry, which increases power con- and some NEF implementations leverage the general approximation
sumption and area overhead, which, to a certain extent, potentially ability of neuron systems to deploy non-neural network applications84,
diminishes the efficiency advantages of memristors. the main challenge of the approximation approach is to ensure the
quality of computing with limited resources and improve program-
Software mability to support complex control flow. Portability is another key
Effective computing relies heavily on system software. For brain- objective. LAVA81,85 pioneers cross-platform deployment by defining
inspired computing, the system software bridges neural models and a series of protocols, and some studies directly use general-processors
hardware with specific constraints, adapting to changes in algorithms ARM infrastructure80, or extend SNN functionalities from the RISC-V
and hardware, while translating abstract neural models into concrete instruction set architecture (ISA)86. However, more dedicated designs
hardware operations58. System software falls into five main categories: for GPBIC hardware abstractions are still needed.

Fig. 2 | Hardware and software advancements in brain-inspired computing. applications, including ANNs, SNNs and hybrid neural networks (HNNs); and
Top: key contributions to software (SW) development. The location of entries the pathway towards general-purpose applications. The vertical positioning
indicates it belongs to a specific route or crosses multiple routes. Bottom: of each entry indicates the specific route to which it belongs. Due to extensive
trends in hardware (HW) development. Circle sizes represent citation counts, research in brain-inspired computing software and hardware, certain critical
normalized logarithmically. There are four primary routes for brain-inspired contributions may be inadvertently omitted, and some works may span
computing: neuromorphic engineering for intelligent sensory processing, which multiple target routes. SIMD stands for single instruction multiple data parallel
involves minimal software; brain simulation for investigating brain functions mechanism. References 1–118 in the figure, along with their citation counts, are
and mechanisms; intelligent computing to accelerate neural network (NN) listed in Supplementary Information.

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Software stack NEF81 Brian112 SpykeTorch116 Random walk representation89

Nengo 115
Darwin framework 98
Fugu80
GENESIS118 Brian2113
SpikingJelly117 Graph of communicating entities92
Graph of communicating entities94
Programming framework 110
NEST83 99
and algorithm abstraction PyNN HNN programming Communicating sequential process107
Corelet96 NxTF106
NEURON111 NeuCube114 Tree-organized compartments105
Neuromorphic completeness representation101
82 86
Dynamical system guided mapping Cross-SIMD compilation Dynamics approximation38
NN approximates NN108
Neural accelerator for general programs90,91
SNN partition and mapping88
Analogue circuit calibration38,87 Coarse-fine-grained hybrid mapping98
Compiler Minimum communication mapping97 Machine graph generation92
95
Splitting, grouping, mapping Magma107
Homogeneity-aware mapping84 Minimum core mapping105 Generic graph reforming, tuning103
Semi-folded mapping100 Simulation-interactive compilation hierarchy104
Event-driven runtime library94,95 Event-based operating93
85
Batch and hybrid operation mode Time-annotated control flow86
TrueNorth runtime
78 Mutual scheduling69
Runtime and OS 85
Availability and calibration database Neural task operation and resource management98
Neural state machine scheduling102 Magma107
Loihi runtime105
Dimensionless model for mixed analogue–digital34 Extended HW coordinate8
Corelet96 Machine graph9
Hardware Hierarchical coordinate85 Microcode for learning105
abstraction
Darwin modelling98 Spatiotemporal execution model69
Interrupt handler API94 RISC-V SNN ISA109

1988 2
1 Hardware
Brains in silicon Tianjic
3
FACETS\BrainScaleS Darwin
4 SpiNNaker Intel-loihi
IBM ODIN/MorphIC
1995 UZH\ETH Zurich Others
5 16
6

17
2000
7
19
18
8 20
21
9
Year

22
2005 10 24 23
25 26
11
27 39
29 28

2010 40 41
12 72
13 30 31
42 73 74
43 75
14 32
46 45 44
33 76
34 48
2015 49 47 78
15 51 77
35 53 50
52 79
37 54 55 38
36
59 58
38 57 56 60
62
2020 65 64
63 61 67 68
68
66
69 67 66
70 71 69

Route I: Route II: Route III: Route IV:

Neuromorphic engineering Brain simulation Intelligent computing GPBIC
Neuron Diverse Brain Bio-inspired Paradigm
structure Intelligent Bio-inspired Intelligent principles fusing
neurons and mechanisms General
and sensory principles applications +
organizations exploration purpose
properties Neuron Neuron Algorithm–HW advanced SW–HW
modelling programming co-design computing decoupling
• Compact/circuit area • Programmability • AI model support • Versatility
• Power consumption • Scalability • Energy efficiency • Elasticity
• Biologically realistic • Simulation latency/power • Latency • Interactivity
• Biologically plausibility • Programmability

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For systems based on post-CMOS technologies, studies on soft- Recently, neuromorphic completeness has been proposed as
ware mainly include two key aspects: hardware simulators and algo- a more adaptive and broader definition of completeness for brain-
rithm deployment software. When it comes to system software stacks, inspired computing83. It relaxes the completeness requirement for
such as compilers and runtimes, the progress still lags behind tradi- brain-inspired computing hardware, enlarging the design space
tional CMOS-based counterparts, despite some initial efforts87. This lag by introducing a new dimension, the approximation granularity.
is largely attributed to the fact that the hardware has not yet matured Guided by this theory, a system hierarchy can be developed includ-
enough for large-scale systems. As a result, manual compilation and ing Turing-complete software abstractions and versatile hardware.
resource management are still viable for small-scale systems. Achieving Moreover, distinct roles and optimization objectives for different
compatibility with the existing brain-inspired computing ecosystem levels of hardware and software components can be defined with
and developing end-to-end compilation tools are still challenges. greater clarity with enhanced compatibility among different hardware
In the development of system software, three emerging trends and/or software designs.
are noticeable. First, there is an increasing emphasis on decoupling To some extent, the completeness theory addresses fundamental
software stacks through different levels of abstraction. While co-design questions about brain-inspired computing’s capabilities, discussing
or coupling between software and hardware can enhance performance, the problem its systems can solve and delineating their functional
decoupling improves usability and iterative ability, and standardizes boundaries. The performance advantage it offers is rooted in how it
interdisciplinary cooperation. Co-evolution will promote long-term represents and processes information. Modern computers excel in
development. Second, there is an increasing focus on extending the temporal processing capabilities driven by rapid instruction and state
performance benefits to various areas, from domain-specific to gen- switching. The brain, in contrast, is characterized by highly intercon-
eral parallel computing, and the responsibility of general purpose nected connections, dynamics and adaptivity, enabling simultaneous
has shifted partly from hardware to system software. Third, the com- processing of spatial and spatiotemporal capabilities. Furthermore,
munity of software is becoming diverse and richer, from deployment modern computers are engineered for precise processing, whereas
toolchains to middleware for large-scale systems. the brain possesses the attribute of approximate processing. In addi-
tion, modern computers with their von Neumann architecture are
Large-scale computing systems and applications recognized as control-flow architectures with separated storage and
To meet the growing demands for high-performance computing, computation, whereas the brain is typically characterized as a data-flow
large-scale brain-inspired systems have been developed to support event-driven architecture with co-located storage and computation.
expansive neural networks or simulations. Typically, these systems are To advance the computing model of GPBIC, it is important to
constructed hierarchically, starting with smaller components (such as fuse the brain’s spatiotemporal processing capability, approximation
board, reticle) that utilize brain-inspired chips and scaling up to larger computing and data flow with the computer’s temporal processing
systems (Fig. 3) with various methods. The integration and intercon- capability, precise computing and control flow. We explore here the
nection are crucial to ensure high bandwidth and effective cross-mode fusion of these three aspects—temporal, spatial and spatiotemporal
communication. However, current large-scale systems primarily use capabilities; approximate computing and precise computing; and
custom-developed chips and system software. control flow and data flow—providing a model that can be conceptual-
Current large-scale systems primarily use custom-developed ized as brain-inspired automata (Fig. 4). Our primary goal in providing
chips and system software and show heterogeneity of the von this theoretical computing model is to bring together researchers
Neumann-based host and brain-inspired computing slave modules. from diverse disciplines and inspire further research within a cohesive
FPGAs are frequently used for data conversion, interface translation theoretical framework. While these aspects are pivotal, they are not
and control information transmission. Most systems use an ethernet intended to be exhaustive or fixed, and further developments could
link and peripheral component interconnect express (PCIe) as the phys- be made by examining additional features.
ical interface and adopt a hierarchical connection scheme to improve
scalability, including routing topology, communication protocols and Temporal, spatial and spatiotemporal capabilities
schemes. During runtime, general-purpose processors are responsible The formalized descriptions of the concepts of ‘temporal’ and ‘spatial’
for running the operating system and managing data exchange. underpin this computing model, although there are diverse interpre-
Brain-inspired computing chips or systems have been used in tations of these terms at different levels within the research domain.
various applications, including artificial perception, signal processing, To provide a more coherent framework and enhance communication
robotics and neural simulation (Fig. 3f). Applications beyond neural among researchers, we consider a collection of parallel processing units
network or brain simulation88 have also been explored, such as commu- that have topological connections in space (analogous to synapses)
nity detection89, scientific computing90 and agent-based modelling91. and show internal state transitions (comparable to spiking neurons),
By demonstrating their capability to solve non-deterministic polyno- which is referred to as brain-inspired automata. This model is inspired
mial complete problems, these systems have highlighted their poten- by the cellular automaton92 and each unit features finite state machines
tial for complex computations. As system software continues to evolve, and input–output connection patterns. Its effectiveness relies on both
these systems are expected to provide greater high-performance temporal and spatial features in processing and information repre-
computing power, versatility and efficiency. sentation. In subsequent discussions, ‘automata’ specifically denotes
‘brain-inspired automata’.
Combining neuroscience and computer science
The integration of approaches from neuroscience and computer sci- Temporal and spatial processing. The computing capabilities of
ence is key to developing GPBIC. To do this, it is necessary to establish brain-inspired automata rely significantly on some intrinsic attributes,
a theoretical foundation that defines the scientific scope and provides notably temporal richness and spatial richness. Temporal richness
essential guidance, including complete and formalized computing reflects neuron dynamics and measures the processing capabilities
models. Turing completeness lays the theoretical foundation for com- of each processing unit, such as the number of states and the flex-
puters, and the hierarchical system structure decouples modern com- ibility of state transitions of state machines. Spatial richness origi-
puters’ software and hardware to ensure their independent progress as nates from the neuron interconnections and reflects the potential
well as compatibility. However, the lack of guidance in brain-inspired for information exchange, evaluated by the connectivity and het-
systems leads to more tight coupling development of dedicated soft- erogeneity among processing units. While computers prioritize
ware and hardware, hindering the establishment of GPBIC. temporal richness, the brain leverages massive neurons with spatial

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460 billion

100 billion
a Chips f
Neurons

4 billion

4 billion
460 million
Synapses Bio-data (signal)
Cognitive

1 billion
1 billion

100 million
control processing
Perception,
45 million

auditory 9%
5%

16 million
Perception,
4 million 3%

4 million
olfactory
1 million

2%
200,000

Brain simulation

27%
Robotics

7%
29,000
7,000

%
768
384

21
9%
Scientific

100
computing Neural
64

17%
simulation
16

Perception,
vision

FACETS Neurogrid BrainScaleS SpiNNaker TrueNorth Loihi Tianjic

b c e
USB
CPLD Neurocore

N N N FX2 N N N

Brain-inspired computing chip

CPLD
N N N N
4 wafer modules per rack

…
N N N N N N
FPGA
d 24 boards per card frame, 5 card frames 384
C C … C
HICANN B B B
per rack Rack 0–4
chips B … B … Chips C C … C

HICANN
board
S S … S B B B
SpiNNaker

… … … C
48 chips S S … S Rack 0–9
board(0) … … S C C … C
S S … S …
3 Link
Inner-FPGA Link

FPGA
FPGA Link Ethernet board
FPGA

chips Ethernet PCIe/ethernet

FPGA

BMP BM P Switch Switch

Switch
Switch CPU

Host PCIe/ethernet
Switch Switch

CPU
system
Ctrl
CPU

Host system Data IO

Host system

Fig. 3 | Large-scale brain-inspired computing systems. a, The scale of six e, The system architecture of other fully digital projects, including Tianjic,
representative large-scale systems. b, The system architecture of Neurogrid16. Loihi and TrueNorth 38,40,98. C indicates chips. Ctrl, controller: details may be
The input/output (IO) data of the system is sent through the universal serial bus different for these systems. f, Publication statistics on applications deployed on
(USB) and converted by complex programmable logic device (CPLD). FX2 is a brain-inspired computing chips or systems. Here we specifically focused on the
USB controller. c, The system architecture of BrainScaleS-NM-PM-117. B indicates articles about applications deployed on brain-inspired computing chips over the
BrainScaleS dies. HICANN, high input count analogue neural network. d, The past decade. Following this, we categorized the themes and contents of the 157
system architecture of SpiNNaker22. S indicates SpiNNaker chips. Board(0) is the articles obtained.
first board. Each board is controlled by a board management processor (BMP).

parallelism and their connections to process complex information, input processing units and the sequence symbols. Both languages
demonstrating significant spatial richness. Despite advancements can be complete, but the spatial-temporal language is more efficient
such as graphics-processing-unit and neural-network accelerators for handling various information distributions and data structures
that enable high parallelism, these technologies lack the abundant because of its additional dimension. It also offers greater flexibility
spatial richness observed in the human brain. Therefore, a critical in capturing underlying dependencies within algorithms, making it
research topic is exploring effective designs that fuse both temporal promising for leveraging both temporal and spatial richness to achieve
and spatial richness. cost-efficient execution.
The spatial-temporal processing and coding underpin the versatil-
Temporal and spatial coding. In terms of coding, the Turing machine- ity of the automata and determine the adaptivity for diverse resource
based computing model encodes information as a symbol sequence and performance requirements. This adaptivity can be assessed through
(temporal language). In contrast, the automata take a spatial-temporal complexity (cost) metrics of an automaton, including time complexity,
language, where information is represented through the locations of space complexity and transmission complexity, which corresponds to

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Paradigm fusion for GPBIC

Brain paradigm Computer paradigm

• Topology and • Logic based

dynamic based • Precise
• Approximate • Control flow
• Data flow

A theoretical perspective

Features formed
Brain-inspired Design considerations
through fusion
automata model
Time and space TST elasticity

complexity
Time
Processing
unit
Processing
stage Connection Temporal richness
pattern
Spatial richness
Space complexity
Precision and
approximation

pl gy
ity
m er
ex
co En
10
Output Versatility
GPBIC
0 1
Performance

Performance
Scope Scope

0 1 Control flow and Interactivity and programmability

Algorithm: data flow
1 1 Data flow Control flow
Timing
1 0
Processing units

Coding
Schedule

stage 0 0
1 1
Input:
0 1 Functionality
Time

Fig. 4 | Fusing the key features of brains and computers. Hybrid features generates output symbols. During execution, in-processing units interpret the
and design considerations for GPBIC are explored with the brain-inspired corresponding symbol sequences they receive. Processing units that receive
automata formed by a set of processing units. Each processing unit has a finite valid symbols generate corresponding symbols to the output connections and
state machine and is interconnected via specific patterns. These connections undergo state transitions according to predefined rules. Finally, out-processing
include input connections for symbol reception and output connections for units generate output sequences, which are decoded to the final result. The
symbol transmission to other units. A subset of processing units known as in- brain-inspired automata integrate the features of temporal, precise and control-
processing units receive input symbols encoding algorithms and specific input flow processing and representations with spatial, approximate and data-flow
data. Similarly, another subset of processing units, termed out-processing units, patterns to achieve TST elasticity, versatility, interactivity and programmability.

the time required to solve specific problems, the number of process- Temporal richness and spatial richness can be interchangeable.
ing units involved and the volume of data exchange among processing For instance, the computation capability of a biologically detailed
units. These complexity metrics are similar to those in modern com- neuron model is functionally similar to that of a multilayer ANN93. This
puters with certain redefinitions. For automata, a single task can be insight is valuable for designing neuromorphic devices and GPBIC
deployed through different strategies with distinct processing units systems. Ideally, GPBIC hardware should balance between ‘simple’ and
and process orders, resulting in varying time, space and transmission ‘complex’ processing units, coupled with dynamic spatial topological
complexity. Some strategies may use more processing units to reduce connections to handle diverse workloads adaptively and elastically.
time complexity, while others may extend processing time to mini- Consequently, an ‘adaptive’ neuromorphic device should possess
mize transmission complexity. The range of valid strategies defines the capability to switch between ‘high temporal richness with more
a scope of time–space–transmission (TST) elasticity (Fig. 4), allowing available internal states’ and ‘high spatial richness with more exter-
tailored strategies for specific problem requirements. The elasticity is nal connections’. Currently, many neuromorphic devices show the
influenced by spatial-temporal richness and coding, which helps the capacity to mimic complex neuronal or synaptic behaviours, but
computing architecture adapt to different scenarios. Hence, a critical achieving flexible spatial connections remains a significant chal-
challenge of the GPBIC is to leverage spatial and temporal richness and lenge. Inspiration can be drawn from recent innovations, such as IBM
coding to achieve appropriate TST elasticity for target applications. NorthPole94, which adopts four kinds of networks-on-chip to enhance

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Perspective https://doi.org/10.1038/s41928-024-01277-y

Intelligent applications and Applications with more brain-

brain simulation inspired patterns
Versatile
Application applications
ANN, SNN, HNN CG, HPC,
multi-agent simulation, …
Inference, learning

Brain-inspired pattern-inclined programming

Abstraction NN programming framework and representation
language

System
software Compiler Domain-specific compilation stack Domain-agnostic compilation stack

Brain-inspired co-operating Brain-inspired self-operating

Operating system Brain-inspired operating system
system and runtime system

ISA

General-purpose Brain-inspired
processor central processor
Hardware General-purpose
brain-inspired
processor
Brain-inspired Control
co-processor co-processor

Fig. 5 | The development of GPBICs. A full-stack computer system comprises level converts applications with various patterns on brain-inspired hardware
three levels: application, system software and hardware. Efforts aimed at and develops self-organized systems. Structural generalization at the hardware
advancing general-purpose computers can be directed across all levels. level rearranges the architecture and circuit components and eventually gets a
Specifically, the pattern generalization at the application level defines the general-purpose brain-inspired processor. CG, computational graphics; HPC,
scope of applications that can be efficiently supported and enlarges the scope high-performance computing.
by relaxing the supporting patterns. Systematic generalization at the software

spatial computing and improve ANN inference throughput. Future for approximation coding can show increased resilience to minor
developments may involve advanced technologies such as chiplet data variations, leading to fault tolerance during execution95,96. At
and three-dimensional stacking, necessitating close collaboration the processing stage, approximation can be implemented either at
between academia and industry. the hardware level or within operation systems. This differs from the
coding stage, where approximation is achieved through compilers or
Approximate computing and precise computing runtime encoders.
Modern computers typically adhere to precise logic defined by pro- For specific tasks, ongoing efforts are fusing the high precision of
grams to ensure reliable programmability, enabling the construc- digital computing and energy-efficient and/or area-efficient in-memory
tion of complex systems with multilevel abstractions. In contrast, computing. For example, research97 introduced mixed-precision
brain-inspired automata fuse approximate computing, which aligns in-memory computing, which combines the accuracy of the von Neu-
with the inherent nature of approximation in existing brain-inspired mann machine with a low-precision yet computationally powerful
computing and also offers distinct advantages. This can be explained phase-change memory unit, to solve matrix equations by conjugate
from two aspects: the processing stage and the coding stage. gradient method. The phase-change memory unit takes the lead in
At the processing stage, approximation involves executing an handling the bulk of the computational workload, while the von Neu-
algorithm that may not precisely adhere to its exact program logic. mann cores use a backwards method to iteratively enhance accuracy.
In the context of brain-inspired automata, processing can be defined This hybrid system achieves 4× to 20× speed-ups and energy-saving
as y = f(x), where x and y represent input and output. The introduc- compared with conventional approaches.
tion of approximation in processing entails substituting the original From our perspective, the fusion of approximate and precise
algorithm f(·) with an approximate algorithm f′(·). To ensure satis- computing expands the design space between performance and fidelity
factory results, the automata output should be constrained within a for developing GPBIC. It involves fine-grained balancing in the selec-
specific margin of error ε, where |f(x) − f′(x)| ≤ ε. By loosening ε, the tion of precise and approximate components, as well as ε, tailored to
TST complexity would be reduced, providing a design space for trad- the specific requirements of a given program. Various approaches
ing off computing resources and service quality. Allowing a tolerable exist for implementing approximation, and we introduce two exam-
level of error ε can also expand the range of efficiently supported ples for GPBIC. One potential solution is to utilize precise computing
applications, leading to enhanced versatility. Noise during execu- at the critical control locus, constraining the approximation pro-
tion is an inherent approximate feature of some technologies, and cess within a stable trajectory. Second, due to the decentralization,
certain studies utilize this feature to develop unique computing self-organized scheduling strategies can be applied during runtime to
functionalities49. achieve dynamic adaptivity. The scheduling process can be approxi-
Approximation at the coding stage involves employing a less pre- mate as sub-optimal solutions may suffice. Consequently, it becomes
cise data representation for the automata. Specifically, an approximate viable to tailor a specialized scheduling algorithm for approximate
input x′ may be encoded with the constraint |f(x) − f(x′)| ≤ ε. Beyond hardware components, while employing high-precision components
the potential performance enhancements, processing units designed for task-related computation.

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Perspective https://doi.org/10.1038/s41928-024-01277-y

Control flow and data flow control-flow programs as control co-processors. The long-term
In the field of computation, control-flow and data-flow architectures goal is to align control logic into a data-flow manner for a complete
are two frequently adopted schemas. The former relies on sequential brain-inspired hardware solution.
execution of instructions to determine the processing unit’s function, Innovations such as in/near-memory computing and in-sensor
while the latter usually takes an event-driven approach to achieve low computing using technologies such as memristors and non-volatile
latency and low power consumption. Current brain-inspired comput- memories have improved power efficiency and area utilization in some
ing architecture primarily adopts the data-flow architecture16,29,36,41 domain-specific hardware. However, challenges such as immature
due to its high performance and bio-plausibility. Combining data fabrication processes, lack of established design methodologies and
flow with control flow has the potential to increase controllability underdeveloped architectures have limited their use to co-processing
and interactivity while retaining the performance advantages of units at the macro-core level. Future use of these technologies could
event-driven. Control flow can be incorporated in three key aspects, improve memory hierarchy flexibility, promoting the computing
namely, functionality, timing and scheduling. Some architectures ability and power efficiency of GPBIC systems76. Moreover, flexible
establish synchronous groups or barriers to improve controllability memory protocols with reconfigurable storage and computation
in the original data-flow architecture, which typically adopts an asyn- resource ratios are expected to better support various computation
chronous pattern. Moreover, distributed runtime scheduling could operators.
be adopted in the future to enable efficient allocation of computa- Systematic generalization emphasizes creating a complete system
tional resources while retaining flexibility. Decentralized co-located software that works seamlessly with domain/pattern-specific hardware
resources, such as those utilized in in-memory processing, enhance to improve the generality of the entire computing system, wherein
locality and alleviate the data movement bottleneck. However, this general purpose is defined systematically and collectively by hardware
approach can restrict adaptivity when dealing with diverse workloads and software. Current brain-inspired computing software stacks are
with varying proportions of computation, storage and communica- often tailored to specific hardware, including abstractions for decou-
tion. In-memory computing also poses challenges for flexible data pling and modelling, compilers for deploying neural networks or brain
access due to the close coupling of storage and processing. To address simulation tasks, and co-operating systems with drivers and runtimes
these complexities, a hybrid solution can be devised, combining the for hardware interaction, resource allocation and task scheduling. The
strengths of in-memory processing with near-memory processing term co-operating system refers to a program that still executes under
with established memory control protocols. the control of a general operating system, such as Linus and Windows.
As applications diversify, there is potential for domain-agnostic but
Outlook pattern-specific intermediate programming languages and compilers
Unlike domain-specific architectures, GPBIC systems offer versatil- for fusion pattern programs. In addition, a brain-inspired operating
ity across a range of applications, flexibility for various deployment system could directly run on the brain-inspired central processor,
strategies, interactivity for environmental changes and program- leveraging their scheduling ability.
mability for various usage. Successfully developing GPBIC systems Advances such as universal approximation expand software
will though require creating a computing ecosystem that encourages responsibilities. For example, the fusion of approximation and preci-
exploration and innovation at every level. This can be achieved through sion offers a vast exploration space for the compilers to search for
three potential strategies: application-level pattern generalization, appropriate deployment strategies based on performance require-
hardware-level structural generalization and software-level systematic ments, acceptable task error margins and available hardware
generalization (Fig. 5). resources83. Following this direction, a philosophy of ‘efficient spe-
Pattern generalization involves expanding the range of appli- cialized hardware, flexible general-purpose system’ can eventually
cations that a system can support, progressing from domain spe- lead to a general-purpose computer solely based on brain-inspired
cific to pattern specific, and ultimately general purpose. Initially, computing hardware, providing a self-operating system that can adap-
brain-inspired computers were designed to efficiently run specific tively manage the entire computing environment. Such a system could
algorithms, like those used in spike-based intelligence and brain optimize resource allocation and task scheduling, and also dynamically
simulations. Contemporary systems are increasingly optimized to adjust to changing workloads and application demands. By decoupling
support ANNs alongside SNNs41,45–47, which can be achieved with mini- applications and algorithms from hardware through system software,
mal additional costs due to the similarities in the underlying patterns. brain-inspired computing could develop into a viable and practical
Key characteristics of brain-inspired patterns include large-scale solution, potentially serving as the next-generation general-purpose
parallelism, sparse or dense spatial-temporal representation and computing infrastructure.
processing, decentralized resource utilization, and low-precision
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Acknowledgements Correspondence should be addressed to Luping Shi.

This work was supported by the National Key Research and
Development Program of China (number 2021ZD0200300) and the Peer review information Nature Electronics thanks the anonymous
National Nature Science Foundation of China (numbers 62088102 and reviewers for their contribution to the peer review of this work.
61836004).
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