Design of 6T-SRAM array

ECE-611 (Memory Design and Test)

Indrajit Dutta (MT22161)
Pallavi Kapoor (MT22166)
Yanni Gupta (MT22180)
Specifications
✦ Specifications to be met:

▪ SNM, WM 6σ Qualified
▪ Icell >= 80uA at wc, 1.62V, 125C
▪ Ileak < 250pA at nom,1.8V,25C

✦ ICell should be atleast 80uA with worst case PVT of

SS/1.62v/125℃
✦ Ileak should be minimized to less than 250 pA at PVT of
TT/1.8V/25℃
Design Schematic
▪ We have designed the schematic of 6T-SRAM using Xschem in
skywater-130nm technology

Cell Ratio (CR) 1.54

Pull-up Ratio 0.646

(PR)

(W/L)PG 0.65/0.15

(W/L)PD 1/0.15

(W/L)PU 0.42/0.15

Fig. 1 Schematic of 6T-SRAM bitcell

FOM and stimuli given:-
Given below are the stimulis:-
FOM Value( WL BL BLB
Pre-Layout)

Cell current 114.28 uA HIGH HIGH HIGH

(SS/1.62V/125℃)

Leakage Current 18.78 pA LOW HIGH HIGH

(TT/1.8V/25℃)

WL Write Margin 612.41 mV HIGH HIGH LOW

(SF/1.2V/-40℃)

BL Write Margin 979.72 mV HIGH HIGH LOW

(SF/1.2V/-40℃)

Write Time 1.09 ns HIGH HIGH LOW

(SF/1.2V/-40℃)

SNM 345.48 mV HIGH HIGH HIGH

(FS/1.2V/125℃)
Read Operation (SS/1.62V/125℃)
▪ Read operation
is where both
the BLs is
precharged to
VDD

Vbump arrived at Q ▪ WL arrives after

where 0 was stored precharge is off

▪ Cell current
flows through
the pass gate
where 0 is
stored .

Fig 2. Read operation of 6T SRAM bitecll

Write Operation

● In write
operation, BL
is discharged
to 0
● WL is made
ON after the
BL has
1 and 0 discharged.
written after ● So, ‘0’ is
WL arrives written on
Qbar node
where ‘1’ was
stored initially
and ‘1’ is
written on Q
node where
Fig 3. Waveform of Write operation
‘0’ was stored
Figure of Merits (FOMs)-Cell current
✦ ICell obtained
when WL arrives
and BL’s kept
precharged.
✦ Wc PVT taken as
SS/1.62V/125℃
114.28 µA and Icell we got
114.28 uA which
is satisfying the
given
specification.
✦ VWL=VBL/BLB=1.62
V

Fig 4. Waveform of Icell

 Figure of Merits (FOMs)-ILeak
✦ We have calculated bitline leakage and standby leakage keeping
WL at GND at SS/125℃/1.8V.
✦ Bitline leakage current is calculated through the BL and the
standby leakage current through VDD.

✦ Total leakage current we got as 18.78 pA at the given PVT

Parameters Before Pex After Pex

Bitline leakage 1.923 pA 1.922 pA

Standby leakage 16.86 pA 18.67 pA

Total leakage 18.78 pA 20.60 pA

Figure of Merits (FOMs)-Wordline Write Margin

● Lowest level of
WL to ensure cell
flip with BL@GND
● VWM= 612.41 mV
● WL is DC swept
from 0 to 1.62
and ‘0’ is written
on Qbar node
v(Q)-v(Qbar) = 0
measure WL voltage here
where ‘1’ was
stored initially.

Fig. 5 WL Write-margin
Figure of Merits (FOMs)-Bitline Write Margin

▪ Write-Margin: The
highest level of
Bitline to ensure
cell flip with WL @
Vdd

v(Q)-v(Qbar) = 0
▪ VWM= 979.72 mV
measure BLB voltage here
▪ Bitline is DC swept
from 1.62 V and
‘1’ is written on
the Qbar node
where ‘0’ was
stored initially.

Fig. 6 BL Write-margin
 SNM(Static Noise Margin) circuit:-
● Noise injected with
help of two dependent
sources
● To determine SNM,
voltage of noise source
is found when cell
contents are flipped

dependent
noise sources
main noise
source

Fig. 7 Static noise margin circuit

Layout single 6T bitcell:-
Gnd
Bitline

VDD WL

WL M2

BL and BLB M1

diffusion of PG and PU Local interconnect

Vdd M1

Gnd M2
 Layout of 32x32 SRAM Array:-
width= 152.330 µm area=7138.184 µm2
height=46.860 µm
46.680 µm

152.330 µm
Parasitic extraction (PEX)
After extraction from 32x32 array, we obtained
following parasitic capacitances of single bitcell :

WL 1.24fF

BL 0.535fF

BLB 0.4418fF
WL Write Margin Monte Carlo Analysis:-
WL Write Margin WL Write Margin (After
(Before PEX) PEX) 6- sigma qualified
0.6124 volts 0.6134 volts
BL Write Margin Monte Carlo Analysis:-
BL is swept from 1.62v to 0 volts.
BL Write Margin BL Write Margin
(Before PEX) (After PEX) 6- sigma qualified
0.979 volts 1.18 volts
Write Time Monte Carlo Analysis:-
With pex parasitics delay get added so local variations effect becomes
more significant which results in more horizontal spread i.e., more shift
in the mean.
Write Time (Before Write Time(After 6- sigma qualified
PEX) PEX)

1.09 ns 1.18 ns

Write time (Before Write time (After

PEX) PEX)

1.099 ns 1.124 ns
SNM Monte Carlo Analysis:-
SNM (Before PEX) SNM (After PEX)

0.345 V 0.331 V 6- sigma qualified

 Worldline Underdrive as Read Assist
Scheme (1) :-
at FS/1.2v/125℃

Fig. 8 WLUD

SNM SNM
(before (after
WLUD) WLUD)

345.48 449.206
mV mV

Reference : A. Mishra and A. Grover, "A 0.9V 64Mb 6T SRAM cell with Read and Write assist schemes in 65nm LSTP
technology," 2020 24th International Symposium on VLSI Design and Test (VDAT), Bhubaneswar, India, 2020, pp.
1-4, doi: 10.1109/VDAT50263.2020.9190373.
Worldline Underdrive as Read Assist
Scheme (2) :-
We observed that wordline underdrive results in improved SNM.
With the decrease in wordline voltage the bump voltage decreases
and improves the stability.
6- sigma qualified

WL is lowered
to 1.2v
Comparison of Post Layout and Pre
Layout:-
FOM Value Value
( Pre-Layout) (Post-Layout)

Cell current 114.28 uA 109.63uA

(SS/1.62V/125℃)

Leakage Current 18.33 pA 20.60 pA

(TT/1.8V/25℃)

WL Write Margin 612.41 mV 613.4 mV

(SF/1.2V/-40℃)

BL Write Margin 979.72 mV 1180 mV

(SF/1.2V/-40℃)

Write Time 1.09 ns 1.18 ns

(SF/1.2V/-40℃)

SNM 345.48 mV 331 mV

(FS/1.2V/125℃)
Challenges faced & Future Plans
✦ Challenges faced

✤ To attain proper sizing to obtain 6 sigma qualification of

each parameters

✦ Future plans
✤ In depth analysis of different read and write assist schemes
✤ Publication Scope in conferences like IOP Conference Series
Materials Science and Engineering can be explored.
References
▪ E. Seevinck, F. J. List and J. Lohstroh, "Static-noise margin analysis of
MOS SRAM cells," in IEEE Journal of Solid-State Circuits, vol. 22, no. 5, pp.
748-754, Oct. 1987, doi: 10.1109/JSSC.1987.1052809.
▪ A. Bhaskar, "Design and analysis of low power SRAM cells," 2017
Innovations in Power and Advanced Computing Technologies (i-PACT),
Vellore, India, 2017, pp. 1-5, doi: 10.1109/IPACT.2017.8244888.
▪ K. Takeda et al., "A read-static-noise-margin-free SRAM cell for low-VDD
and high-speed applications," in IEEE Journal of Solid-State Circuits, vol.
41, no. 1, pp. 113-121, Jan. 2006, doi: 10.1109/JSSC.2005.859030.
▪ A. Mishra and A. Grover, "A 0.9V 64Mb 6T SRAM cell with Read and
Write assist schemes in 65nm LSTP technology," 2020 24th International
Symposium on VLSI Design and Test (VDAT), Bhubaneswar, India, 2020,
pp. 1-4, doi: 10.1109/VDAT50263.2020.9190373.
▪ B. N. K. Reddy, K. Sarangam, T. Veeraiah and R. Cheruku, "SRAM cell with
better read and write stability with Minimum area," TENCON 2019 - 2019
IEEE Region 10 Conference (TENCON), Kochi, India, 2019, pp. 2164-2167,
doi: 10.1109/TENCON.2019.8929593.
Contribution:-
All the work has been done mutually by team members.

Thank You!