ASICs...

the course

Michael John Sebastian Smith

This course is based on ASICs... the book

Application-Specific Integrated Circuits

Michael J. S. Smith
VLSI Design Series
1,040 pages
ISBN 0-201-50022-1
LOC TK7874.6.S63
Addison Wesley Longman, http://www.awl.com

Additional material (figures, resources, source code) is located at

ASICs... the website

http://spectra.eng.hawaii.edu/~msmith/ASICs/HTML/ASICs.htm
Some material in this work is reprinted from IEEE Std 1149.1-1990, “IEEE Standard Test Access Port and Boundary-Scan Archi-
tecture,” Copyright © 1990; IEEE Std 1076/INT-1991 “IEEE Standards Interpretations: IEEE Std 1076-1987, IEEE Standard
VHDL Language Reference Manual,” Copyright © 1991; IEEE Std 1076-1993 “IEEE Standard VHDL Language Reference
Manual,” Copyright © 1993; IEEE Std 1164-1993 “IEEE Standard Multivalue Logic System for VHDL Model Interoperability
(Std_logic_1164),” Copyright © 1993; IEEE Std 1149.1b-1994 “Supplement to IEEE Std 1149.1-1990, IEEE Standard Test
Access Port and Boundary-Scan Architecture,” Copyright © 1994; IEEE Std 1076.4-1995 “IEEE Standard for VITAL Applica-
tion-Specific Integerated Circuit (ASIC) Modeling Specification,” Copyright © 1995; IEEE 1364-1995 “IEEE Standard Descrip-
tion Language Based on the Verilog® Hardware Description Language,” Copyright © 1995; and IEEE Std 1076.3-1997 “IEEE
Standard for VHDL Synthesis Packages,” Copyright © 1997; by the Institute of Electrical and Electronics Engineers, Inc. The
IEEE disclaims any responsibility or liability resulting from the placement and use in the described manner. Information is
reprinted with the permission of the IEEE. Figures describing Xilinx FPGAs are courtesy of Xilinx, Inc. ©Xilinx, Inc. 1996,
1997, 1998. All rights reserved. Figures describing Altera CPLDs are courtesy of Altera Corporation. Altera is a trademark and
service mark of Altera Corporation in the United States and other countries. Altera products are the intellectual property of Altera
Corporation and are protected by copyright laws and one or more U.S. and foreign patents and patent applications. Figures
describing Actel FPGAs iare courtesy of Actel Corporation.

The programs and applications presented in this work have been included for their instructional value. They have been tested with
care but are not guaranteed for any particular purpose. The author does not offer any warranties, representations, or accept any lia-
bilities with respect to the programs or applications.

Many of the designations used by manufacturers and sellers to distinguish their products are claimed as trademarks. Where those
designations appear in this work, and the author was aware of a trademark claim, the designations have been printed in initial caps or
all caps.

Figures copyright © 1997 by Addison Wesley Longman, Inc. Text copyright © 1997, 1998 by Michael John Sebastian Smith.
ASICs...THE COURSE (1 WEEK)

INTRODUCTION 1
TO ASICs

Key concepts: The difference between full-custom and semicustom ASICs • The difference
between standard-cell, gate-array, and programmable ASICs • ASIC design flow • Design
economics • ASIC cell library

An ASIC (“a-sick”) is an application-specific integrated circuit

A gate equivalent is a NAND gate F = A • B (IBM uses a NOR gate), or four transistors
History of integration: small-scale integration (SSI, ~10 gates per chip, 60’s), medium-
scale integration (MSI, ~100–1000 gates per chip, 70’s), large-scale integration (LSI,
~1000–10,000 gates per chip, 80’s), very large-scale integration (VLSI, ~10,000–100,000
gates per chip, 90’s), ultralarge scale integration (ULSI, ~1M–10M gates per chip)
History of technology: bipolar technology and transistor–transistor logic (TTL) preceded
metal-oxide-silicon (MOS) technology because it was difficult to make metal-gate n-chan-
nel MOS (nMOS or NMOS); the introduction of complementary MOS (CMOS, never cMOS)
greatly reduced power
The feature size is the smallest shape you can make on a chip and is measured in λ or
lambda
Origin of ASICs: the standard parts, initially used to design microelectronic systems,
were gradually replaced with a combination of glue logic, custom ICs, dynamic random-
access memory (DRAM) and static RAM (SRAM)
History of ASICs: The IEEE Custom Integrated Circuits Conference (CICC) and IEEE Inter-
national ASIC Conference document the development of ASICs
Application-specific standard products (ASSPs) are a cross between standard parts and
ASICs

1.1 Types of ASICs

ICs are made on a wafer. Circuits are built up with successive mask layers. The number of
masks used to define the interconnect and other layers is different between full-custom
ICs and programmable ASICs

1
2 SECTION 1 INTRODUCTION TO ASICs ASICS... THE COURSE

silicon
die

A silicon chip or integrated cicuit

(IC) is more properly called a die

0.1 inch
(a) (b)

1.1.1 Full-Custom ASICs

All mask layers are customized in a full-custom ASIC.
It only makes sense to design a full-custom IC if there are no libraries available.
Full-custom offers the highest performance and lowest part cost (smallest die size) with the
disadvantages of increased design time, complexity, design expense, and highest risk.
Microprocessors were exclusively full-custom, but designers are increasingly turning to
semicustom ASIC techniques in this area too.
Other examples of full-custom ICs or ASICs are requirements for high-voltage (automobile),
analog/digital (communications), or sensors and actuators.

1.1.2 Standard-Cell–Based ASICs

A cell-based ASIC (CBIC—“sea-bick”)

• Standard cells
standard-cell 1
• Possibly megacells, megafunctions, full- area
custom blocks, system-level macros (SLMs), 2 3
fixed blocks, cores, or Functional Standard
Blocks (FSBs) fixed
blocks
• All mask layers are customized—transistors and
interconnect
4 5
• Custom blocks can be embedded 0.02in
500 µm
• Manufacturing lead time is about eight weeks.

In datapath (DP) logic we may use a datapath compiler and a datapath library. Cells such
as arithmetic and logical units (ALUs) are pitch-matchedto each other to improve timing
and density.
ASICs... THE COURSE 1.1 Types of ASICs 3

VDD
m1

n-well cell bounding box

(BB)

contact
ndiff
pdiff

Z
A1 B1 via
metal2
poly

ndiff
cell abutment box
(AB)
p-well
pdiff

pdiff
GND

10λ

Looking down on the layout of a standard cell from a standard-cell library

1.1.3 Gate-Array–Based ASICs

A gate array, masked gate array, MGA, or prediffused array uses macros (books) to
reduce turnaround time and comprises a base array made from a base cell or primitive
cell. There are three types:
• Channeled gate arrays
• Channelless gate arrays
• Structured gate arrays
4 SECTION 1 INTRODUCTION TO ASICs ASICS... THE COURSE

1 expanded view
of part of flexible no
block 1 connection
connection metal2
to power to power
250 λ pads metal1 pads
terminal VSS VDD VSS VDD

Z row-end
cells

feedthrough cell A.11

cell A.14 cell A.23

spacer
cell A.132 metal2 cells

I1 power cell metal1

metal2
metal1 rows of standard cells
50 λ

Routing a CBIC (cell-based IC)

• A “wall” of standard cells forms a flexible block
• metal2 may be used in a feedthrough cell to cross over cell rows that use metal1 for wir-
ing
• Other wiring cells: spacer cells, row-end cells, and power cells

A note on the use of hyphens and dashes in the spelling (orthography) of compound nouns: Be
careful to distinguish between a “high-school girl” (a girl of high-school age) and a “high school
girl” (is she on drugs or perhaps very tall?).
We write “channeled gate array,” but “channeled gate-array architecture” because the gate
array is channeled; it is not “channeled-gate array architecture” (which is an array of chan-
neled-gates) or “channeled gate array architecture” (which is ambiguous).
We write gate-array–based ASICs (with a en-dash between array and based) to mean (gate
array)-based ASICs.
ASICs... THE COURSE 1.1 Types of ASICs 5

1.1.4 Channeled Gate Array

A channeled gate array base cell

• Only the interconnect is customized

• The interconnect uses predefined spaces between rows
of base cells
• Manufacturing lead time is between two days and two array of
base cells
weeks (not all
shown)

1.1.5 Channelless Gate Array

A channelless gate array (channel-free gate array, sea- base cell

of-gates array, or SOG array)
• Only some (the top few) mask layers are customized—
the interconnect
• Manufacturing lead time is between two days and two array of
base cells
weeks. (not all
shown)

1.1.6 Structured Gate Array

6 SECTION 1 INTRODUCTION TO ASICs ASICS... THE COURSE

An embedded gate array or structured gate

embedded
array (masterslice or masterimage) block

• Only the interconnect is customized

• Custom blocks (the same for each design)
can be embedded
array of
• Manufacturing lead time is between two days base cells
and two weeks. (not all
shown)

1.1.7 Programmable Logic Devices

Examples and types of PLDs: read-only memory (ROM) • programmable ROM or PROM •
electrically programmable ROM, or EPROM • An erasable PLD (EPLD) • electrically eras-
able PROM, or EEPROM • UV-erasable PROM, or UVPROM • mask-programmable ROM
• A mask-programmed PLD usually uses bipolar technology

Logic arrays may be either a Programmable Array Logic (PAL®, a registered trademark of
AMD) or a programmable logic array (PLA); both have an AND plane and an OR plane

A programmable logic device (PLD)

• No customized mask layers or logic cells
• Fast design turnaround macrocell

• A single large block of programmable intercon-

nect
• A matrix of logic macrocells that usually consist of
programmable array logic followed by a flip-flop or
programmable
latch interconnect
ASICs... THE COURSE 1.2 Design Flow 7

1.1.8 Field-Programmable Gate Arrays

A field-programmable gate array (FPGA) or

complex PLD
• None of the mask layers are customized
programmable
• A method for programming the basic logic basic logic
cell
cells and the interconnect
• The core is a regular array of programmable
basic logic cells that can implement combina-
tional as well as sequential logic (flip-flops)
• A matrix of programmable interconnect sur-
rounds the basic logic cells
programmable
• Programmable I/O cells surround the core interconnect

• Design turnaround is a few hours

1.2 Design Flow

A design flow is a sequence of steps to design an ASIC
1. Design entry. Using a hardware description language (HDL) or schematic entry.
2. Logic synthesis. Produces a netlist—logic cells and their connections.
3. System partitioning. Divide a large system into ASIC-sized pieces.
4. Prelayout simulation. Check to see if the design functions correctly.
5. Floorplanning. Arrange the blocks of the netlist on the chip.
6. Placement. Decide the locations of cells in a block.
7. Routing. Make the connections between cells and blocks.
8. Extraction. Determine the resistance and capacitance of the interconnect.
9. Postlayout simulation. Check to see the design still works with the added loads of the
interconnect.

1.3 Case Study

SPARCstation 1: Better performance at lower cost • Compact size, reduced power, and quiet
operation • Reduced number of parts, easier assembly, and improved reliability
8 SECTION 1 INTRODUCTION TO ASICs ASICS... THE COURSE

start

prelayout design entry logical

simulation design
4 1
VHDL/Verilog

logic synthesis netlist

2

A B
system
partitioning
3

A
postlayout floorplanning
simulation
9 5 chip

placement
block
6

physical
circuit routing design
extraction
8 7
logic cells
back-annotated
netlist finish

ASIC design flow. Steps 1–4 are logical design, and steps 5–9 are physical design

The ASICs in the Sun Microsystems SPARCstation 1

SPARCstation 1 ASIC Gates (k-gates)
1 SPARC integer unit (IU) 20
2 SPARC floating-point unit (FPU) 50
3 Cache controller 9
4 Memory-management unit (MMU) 5
5 Data buffer 3
6 Direct memory access (DMA) controller 9
7 Video controller/data buffer 4
8 RAM controller 1
9 Clock generator 1
ASICs... THE COURSE 1.4 Economics of ASICs 9

The CAD tools used in the design of the Sun Microsystems SPARCstation 1
Design level Function Tool
ASIC design ASIC physical design LSI Logic
ASIC logic synthesis Internal tools and UC Berkeley tools
ASIC simulation LSI Logic
Board design Schematic capture Valid Logic
PCB layout Valid Logic Allegro
Timing verification Quad Design Motive and internal tools
Mechanical design Case and enclosure Autocad
Thermal analysis Pacific Numerix
Structural analysis Cosmos
Management Scheduling Suntrac
Documentation Interleaf and FrameMaker

1.4 Economics of ASICs

We’ll compare the most popular types of ASICs: an FPGA, an MGA, and a CBIC. The fig-
ures in the following sections are approximate and used to illustrate the different compo-
nents of cost.

1.4.1 Comparison Between ASIC Technologies

Example of an ASIC part cost: A 0.5 µm, 20k-gate array might cost 0.01–0.02 cents/gate
(for more than 10,000 parts) or $2–$4 per part, but an equivalent FPGA might be $20.
When does it make sense to use a more expensive part? This is what we shall examine
next.
10 SECTION 1 INTRODUCTION TO ASICs ASICS... THE COURSE

1.4.2 Product Cost

In a product cost there are fixed costs and variable costs (the number of products sold is
the sales volume):

total product cost = fixed product cost + variable product cost × products sold

In a product made from parts the total cost for any part is

total part cost = fixed part cost + variable cost per part × volume of parts

For example, suppose we have the following (imaginary) costs:

• FPGA: $21,800 (fixed) $39 (variable)
• MGA: $86,000 (fixed) $10 (variable)
• CBIC $146,000 (fixed) $8 (variable)
Then we can calculate the following break-even volumes:
• FPGA/MGA ≈ 2000 parts
• FPGA/CBIC ≈ 4000 parts
• MGA/CBIC ≈ 20,000 parts

cost of parts

$1,000,000

break-even
FPGA/CBIC

CBIC
$100,000 MGA

FPGA break-even
MGA/CBIC
break-even
FPGA/MGA
$10,000
10 100 1000 10,000 100,000
number of parts or volume

Break-even graph
ASICs... THE COURSE 1.4 Economics of ASICs 11

1.4.3 ASIC Fixed Costs

Examples of fixed costs: training cost for a new electronic design automation (EDA) sys-
tem • hardware and software cost • productivity • production test and design for test •
programming costs for an FPGA • nonrecurring-engineering (NRE) • test vectors and
test-program development cost • pass (turn or spin) • profit model represents the profit
flow during the product lifetime • product velocity • second source

FPGA MGA CBIC

Training: $800 $2,000 $2,000
Days 2 5 5
Cost/day $400 $400 $400
Hardware $10,000 $10,000 $10,000
Software $1,000 $20,000 $40,000
Design: $8,000 $20,000 $20,000
Size (gates) 10,000 10,000 10,000
Gates/day 500 200 200
Days 20 50 50
Cost/day $400 $400 $400
Design for test: $2,000 $2,000
Days 5 5
Cost/day $400 $400
NRE: $30,000 $70,000
Masks $10,000 $50,000
Simulation $10,000 $10,000
Test program $10,000 $10,000
Second source: $2,000 $2,000 $2,000
Days 5 5 5
Cost/day $400 $400 $400

Total fixed costs $21,800 $86,000 $146,000

Spreadsheet, “Fixed Costs”

12 SECTION 1 INTRODUCTION TO ASICs ASICS... THE COURSE

sales per
quarter, s
peak sales
s1
$20M lost sales
product
introduction

$10M end of
s2 product life

Q1 Q2 Q3 Q4 Q1 Q2
t1 t2 t3 time
delay to market, d

Profit model
ASICs... THE COURSE 1.4 Economics of ASICs 13

1.4.4 ASIC Variable Costs

Factors affecting fixed costs: wafer size • wafer cost • Moore’s Law (Gordon Moore of Intel)
• gate density • gate utilization • die size • die per wafer • defect density • yield • die cost
• profit margin (depends on fab or fabless) • price per gate • part cost

FPGA MGA CBIC Units

Wafer size 6 6 6 inches
Wafer cost 1,400 1,300 1,500 $
Design 10,000 10,000 10,000 gates
Density 10,000 20,000 25,000 gates/sq.cm
Utilization 60 85 100 %
Die size 1.67 0.59 0.40 sq.cm
Die/wafer 88 248 365
Defect density 1.10 0.90 1.00 defects/sq.cm
Yield 65 72 80 %
Die cost 25 7 5 $
Profit margin 60 45 50 %
Price/gate 0.39 0.10 0.08 cents

Part cost $39 $10 $8

Spreadsheet, “Variable Costs”

14 SECTION 1 INTRODUCTION TO ASICs ASICS... THE COURSE

cents/gate
1.00

CBIC 2 µm

CBIC 1.5 µm

CBIC 1 µm
0.10
CBIC 0.6 µm

FPGA 1 µm

FPGA 0.6 µm
–32%/year
0.01
1984 1986 1988 1990 1992 1994 1996

Example price per gate figures

ASICs... THE COURSE 1.5 ASIC Cell Libraries 15

1.5 ASIC Cell Libraries

You can:
(1) use a design kit from the ASIC vendor
(2) buy an ASIC-vendor library from a library vendor
(3) you can build your own cell library

(1) is usually a phantom library—the cells are empty boxes, or phantoms, you hand off your
design to the ASIC vendor and they perform phantom instantiation (Synopsys CBA)

(2) involves a buy-or-build decision. You need a qualified cell library (qualified by the ASIC
foundry) If you own the masks (the tooling) you have a customer-owned tooling (COT, pro-
nounced “see-oh-tee”) solution (which is becoming very popular)

(3) involves a complex library development process: cell layout • behavioral model • Ver-
ilog/VHDL model • timing model • test strategy • characterization • circuit extraction • pro-
cess control monitors (PCMs) or drop-ins • cell schematic • cell icon • layout versus
schematic (LVS) check • cell icon • logic synthesis • retargeting • wire-load model • rout-
ing model • phantom
16 SECTION 1 INTRODUCTION TO ASICs ASICS... THE COURSE

1.6 Summary
Key concepts:
• We could define an ASIC as a design style that uses a cell library
• The difference between full-custom and semicustom ASICs
• The difference between standard-cell, gate-array, and programmable ASICs
• The ASIC design flow
• Design economics including part cost, NRE, and breakeven volume
• The contents and use of an ASIC cell library

Types of ASIC
Custom Custom
ASIC type Family member
mask layers logic cells
Full-custom Analog/digital All Some
Semicustom Cell-based (CBIC) All None
Masked gate array (MGA) Some None
Programmable Field-programmable gate array (FPGA) None None
Programmable logic device (PLD) None None

1.7 Problems
Suggested homework: 1.4, 1.5, 1.9 (from ASICs... the book)

1.8 Bibliography
EE Times (ISSN 0192-1541, http://techweb.cmp.com/eet), EDN (ISSN 0012-7515,
http://www.ednmag.com), EDAC (Electronic Design Automation Companies)
(http://www.edac.org), The Electrical Engineering page on the World Wide Web
(E2W3) (http://www.e2w3.com), SEMATECH (Semiconductor Manufacturing Technol-
ogy) (http://www.sematech.org), The MIT Semiconductor Subway (http://www-
mtl.mit.edu), EDA companies at http://www.yahoo.comunder
Business_and_Economyin Companies/Computers/Software/Graph-
ics/CAD/IC_Design, The MOS Implementation Service (MOSIS)
(http://www.isi.edu), The Microelectronic Systems Newsletter at http://www-
ece.engr.utk.edu/ece, NASA (http://nppp.jpl.nasa.gov/dmg/jpl/loc/asic )
ASICs... THE COURSE 1.9 References 17

1.9 References
Glasser, L. A., and D. W. Dobberpuhl. 1985. The Design and Analysis of VLSI Circuits.
Reading, MA: Addison-Wesley, 473 p. ISBN 0-201-12580-3. TK7874.G573. Detailed anal-
ysis of circuits, but largely nMOS.
Mead, C. A., and L. A. Conway. 1980. Introduction to VLSI Systems. Reading, MA: Addison-
Wesley, 396 p. ISBN 0-201-04358-0. TK7874.M37.
Weste, N. H. E., and K. Eshraghian. 1993. Principles of CMOS VLSI Design: A Systems Per-
spective. 2nd ed. Reading, MA: Addison-Wesley, 713 p. ISBN 0-201-53376-6.
TK7874.W46. Concentrates on full-custom design.
18 SECTION 1 INTRODUCTION TO ASICs ASICS... THE COURSE
ASICs...THE COURSE (1 WEEK)

CMOS LOGIC 2

Key concepts: The use of transistors as switches • The difference between a flip-flop and a
latch • Setup time and hold time • Pipelines and latency • The difference between datapath,
standard-cell, and gate-array logic cells • Strong and weak logic levels • Pushing bubbles •
Ratio of logic • Resistance per square of layers and their relative values in CMOS • Design
rules and λ

• CMOS transistor (or device)

• A transistor has three terminals: gate, source, drain (and a fourth that we ignore for a
moment)
• An MOS transistor looks like a switch (conducting/on, nonconducting/off, not open or
closed)

'1' VDD '1' VDD

n-channel transistor p-channel transistor
drain source '1' = '0' =
gate gate '0' '0' '1' '1'
source drain
'1' = '0' =
GND or GND or
'0' VSS '0' VSS
'1' = on '1' = off
VDD

= = A F = A F
'0' off '0' on

GND or
VSS
(a) (b) (c)

CMOS transistors viewed as switches • a CMOS inverter

1
2 SECTION 2 CMOS LOGIC ASICS... THE COURSE

VDD VDD VDD VDD

on on off on on off off off F=NAND(A, B)
A
F=1 F=1 F=1 F=0 B 0 1
(a)
0 1 1
off on off on
B=0 B=1 B=0 B=1
1 1 0
A=0 A=0 A=1 A=1
off off on on
p-channel
n-channel

VDD VDD VDD VDD

A=0 A=1 A=0 A=1 F=NOR(A, B)
on off on off
A
B=0 B=0 B=1 B=1 B 0 1
(b) on on off off
F =1 F =0 F =0 F =0 0 1 0

1 0 0
off off off on on off on on p-channel
n-channel

CMOS logic • a two-input NAND gate • a two-input NOR gate • Good '1's • Good '0's
ASICs... THE COURSE 2.1 CMOS Transistors 3

2.1 CMOS Transistors

drain

gate bulk
+ + + +
VGS L
VDS VGS source VDS
W

gate T ox

n-type n-type bulk

source electrons drain
GND or
depletion VSS
Ex region
p-type mobile channel charge fixed depletion charge

An n-channel transistor • channel • source • drain • depletion region • gate • bulk

current (amperes) = charge (coulombs) per unit time (second)

• Channel charge = Q (imagine taking a picture and counting the electrons)

• tf is time of flight or transit time

The drain-to-source current IDSn = Q/tf

The (vector) velocity of the electrons v = –µnE

• µn is the electron mobility (µp is the hole mobility)

• E is the electric field (units Vm–1)

L L2
tf = ––– = –––––––
vx µnVDS
4 SECTION 2 CMOS LOGIC ASICS... THE COURSE

Q = C(VGC – Vtn) = C [ (VGS – Vtn) – 0.5 VDS ] = WLCox [ (VGS – Vtn) – 0.5 VDS ]

IDSn = Q/tf
'
= (W/L)µnCox[ (VGS – Vtn) – 0.5 VDS ]VDS = (W/L)k n [ (VGS – Vtn) – 0.5 VDS ]VDS

k'n = µnCox is the process transconductance parameter (or intrinsic transconductance)

βn = k'n(W/L) is the transistor gain factor (or just gain factor)

• The linear region (triode region) extends until VDS = VGS –V tn

• VDS = VGS –V tn = VDS(sat) (saturation voltage)
• VDS > VGS –V tn (the saturation region, or pentode region, of operation)
• saturation current, IDSn(sat)

IDSn(sat) = (βn/2)(VGS – Vtn)2 ; VGS > Vtn

ASICs... THE COURSE 2.1 CMOS Transistors 5

(a) (b)

IDS /mA 1
3 2
n-ch. W/L=60/6 VGS /V
3.0
IDS /mA n-ch.
2 n-ch. W/L=6/0.6
2.5 3 W/L=6/0.6

2.0 3
1
0 2
1.5 VDS /V
3 1
1.0
2
0 0.5, 0.0 1 0
VGS /V 1
0 1 2 3
0
VDS /V

(c)

IDS(sat) /mA 2
3
VDS =3.0 V

2 n-ch. W/L=6/0.6
MOS n-channel transistor characteristics IDS (sat) ∝ VGS –V tn

n-ch. W/L =60/6

IDS (sat) ∝ (VGS –V tn)2
0
0 1 2 3
VGS /V

2.1.1 P-Channel Transistors

IDSp = –k'p(W/L)[ (VGS – Vtp) – 0.5 VDS ]VDS ; VDS > VGS – Vtp
IDSp(sat) = –βp/2 (VGS – Vtp)2 ; VDS < VGS – Vtp .

• Vtp is negative
• VDS and VGS are normally negative (and –3V<–2V)
6 SECTION 2 CMOS LOGIC ASICS... THE COURSE

2.1.2 Velocity Saturation

• vmaxn =10 5 ms–1
• velocity saturation
• tf =L eff/vmaxn
• mobility degradation

IDSn(sat) = WvmaxnCox (VGS – Vtn) ; VDS > VDS(sat) (velocity saturated).

2.1.3 SPICE Models

• KP (in µAV–2) = k'n (k'p)
• VT0 and TOX = Vtn (Vtp) and Tox
• U0 (in cm2V–1s–1) = µn (and µp)

SPICE parameters
.MODEL CMOSN NMOS LEVEL=3 PHI=0.7 TOX=10E-09 XJ=0.2U TPG=1 VTO=0.65
DELTA=0.7
+ LD=5E-08 KP=2E-04 UO=550 THETA=0.27 RSH=2 GAMMA=0.6 NSUB=1.4E+17
NFS=6E+11
+ VMAX=2E+05 ETA=3.7E-02 KAPPA=2.9E-02 CGDO=3.0E-10 CGSO=3.0E-10
CGBO=4.0E-10
+ CJ=5.6E-04 MJ=0.56 CJSW=5E-11 MJSW=0.52 PB=1
.MODEL CMOSP PMOS LEVEL=3 PHI=0.7 TOX=10E-09 XJ=0.2U TPG=-1 VTO=-
0.92 DELTA=0.29
+ LD=3.5E-08 KP=4.9E-05 UO=135 THETA=0.18 RSH=2 GAMMA=0.47
NSUB=8.5E+16 NFS=6.5E+11
+ VMAX=2.5E+05 ETA=2.45E-02 KAPPA=7.96 CGDO=2.4E-10 CGSO=2.4E-10
CGBO=3.8E-10
+ CJ=9.3E-04 MJ=0.47 CJSW=2.9E-10 MJSW=0.505 PB=1
ASICs... THE COURSE 2.1 CMOS Transistors 7

2.1.4 Logic Levels

VGS >V tn '1' VGD >V tn VGS =V tn '1' VGD =0

gate gate
'1' → '0' '0' → '1'–V tn '1'
strong '0' weak '1'
n-type –Q n-type n-type n-type +
'0' source drain source drain
p-type p-type VDD

no channel charge

strong '0' '1'

VC VC
'1' → '0' '0' → '1'–V tn
D '1' D
'1' '1' '1'
G S G S
VC '1' → '0' '0' '0'
t VC weak '1' t
'0'

(a) (b)

VGD =0 '0' VGS = –Vtp VGS <V tp '0' VGD < Vtp

gate gate
'1' → '0'– Vtp '0' → '1' '1'
weak '0' strong '1'
p-type p-type p-type +Q p-type +
'0' drain source drain source
n-type n-type VDD
+ +
VDD no channel charge VDD

weak '0' '1'

VC VC
S '1' → '0'–V tp S '0' → '1'
'0' '1' '0' '1'
G D G D
VC '0' '0'
t VC strong '1' t
'0'

(c) (d)

CMOS logic levels

• VSS is a strong '0' • VDD is a strong '1'
• degraded logic levels: VDD –V tn is a weak '1' ; VSS –V tp (Vtp is negative) is a weak '0'
8 SECTION 2 CMOS LOGIC ASICS... THE COURSE

2.2 The CMOS Process

2 4
1hour 5
3
1 furnace spin
wafer resist

grow crystal saw grow oxide

etch
resist As +
oxide
mask

6 7 8 9 10 11 12

The CMOS manufacturing process

Key words: boule • wafer • boat • silicon dioxide • resist • mask • chemical etch • isotropic •
plasma etch • anisotropic • ion implantation • implant energy and dose • polysilicon • chemical
vapor deposition (CVD) • sputtering • photolithography • submicron and deep-submicron
process • n-well process • p-well process • twin-tub (or twin-well) • triple-well • substrate
contacts (well contacts or tub ties) • active (CAA) • gate oxide • field • field implant or chan-
nel-stop implant • field oxide (FOX) • bloat • dopant • self-aligned process • positive resist •
negative resist • drain engineering • LDD process • lightly doped drain • LDD diffusion or LDD
implant • stipple-pattern
ASICs... THE COURSE 2.2 The CMOS Process 9

Derivation
Mask/layer name from drawn Alternative names for mask/layer Mask label
layers
n-well =nwell bulk, substrate, tub, n-tub, moat CWN
p-well =pwell bulk, substrate, tub, p-tub, moat CWP
active =pdiff+ndiff thin oxide, thinox, island, gate oxide CAA
polysilicon =poly poly, gate CPG
n-diffusion
=grow(ndiff) ndiff, n-select, nplus, n+ CSN
implant
p-diffusion
=grow(pdiff) pdiff, p-select, pplus, p+ CSP
implant
contact cut, poly contact, diffusion con-
contact =contact CCP and CCA
tact
metal1 =m1 first-level metal CMF
metal2 =m2 second-level metal CMS
via2 =via2 metal2/metal3 via, m2/m3 via CVS
metal3 =m3 third-level metal CMT
glass =glass passivation, overglass, pad COG
10 SECTION 2 CMOS LOGIC ASICS... THE COURSE

(a) nwell (b) pwell (c) ndiff (d) pdiff

(e) poly (f) contact (g) m1 (h) via

(i) m2 (j) cell (k) phantom

The mask layers of a standard cell

ASICs... THE COURSE 2.2 The CMOS Process 11

Active mask
CAA (mask) = ndiff (drawn) ∨ pdiff (drawn)

Implant select masks

CSN (mask) = grow (ndiff (drawn)) and
CSP (mask) = grow (pdiff (drawn))

Source and drain diffusion (on the silicon)

n-diffusion (silicon) = (CAA (mask) ∧ CSN (mask)) ∧ (¬CPG (mask)) and
p-diffusion(silicon)=(CAA(mask) ∧ CSP(mask)) ∧ (¬CPG(mask))

Source and drain diffusion (on the silicon) in terms of drawn layers
n-diffusion (silicon) = (ndiff (drawn)) ∧ (¬poly (drawn)) and
p-diffusion (silicon) = (pdiff (drawn)) ∧ (¬poly (drawn))
12 SECTION 2 CMOS LOGIC ASICS... THE COURSE

nwell pwell ndiff pdiff poly contact

Drawn layers and stipple patterns (or solid)

m1 via1 m2 via2 m3 glass

(or solid) (or solid)

nwell
p-diffusion
2λ
pdiff polysilicon
field oxide
field implant
poly
gate oxide
y LDD diffusion z
y
source/drain diffusion
x x
n-well (or substrate)

(a) (b) 2λ

The transistor layers

ASICs... THE COURSE 2.2 The CMOS Process 13

y z m3
(a) y (b)
x x
via2

m2+via2 +m3 m2
The interconnect layers via1 TiW
AlCu
m1 (3000Å)
m2 W plug
contact m3
(4000Å)
+m1 2λ contact
+via1 Pt barrier
+m2 (200Å)

2.2.1 Sheet Resistance

Sheet resistance (1µm ) Sheet resistance (0.35 µm)

Sheet Sheet
Layer Units Layer Units
resistance resistance
n-well 1.15± 0.25 kΩ /square n-well 1± 0.4 kΩ /square
poly 3.5± 2.0 Ω /square poly 10± 4.0 Ω /square
n-diffusion 75± 20 Ω /square n-diffusion 3.5± 2.0 Ω /square
p-diffusion 140± 40 Ω /square p-diffusion 2.5± 1.5 Ω /square
m1/2 70± 6 mΩ /square m1/2/3 60± 6 mΩ /square
m3 30± 3 mΩ /square metal4 30± 3 mΩ /square

Key words: diffusion • Ω /square (ohms per square) • sheet resistance • silicide • self-
aligned silicide (salicide) • LI, white metal, local interconnect, metal0, or m0 • m1 or metal1
• diffusion contacts • polysilicon contacts • barrier metal • contact plugs (via plugs) •
chemical–mechanical polishing (CMP) • intermetal oxide (IMO) • interlevel dielectric
(ILD) • metal vias, cuts, or vias • stacked vias and stacked contacts • two-level metal
(2LM) • 3LM (m3 or metal3) • via1 • via2 • metal pitch • electromigration • contact resis-
tance and via resistance
14 SECTION 2 CMOS LOGIC ASICS... THE COURSE

2.3 CMOS Design Rules

1.
1 well 2.
2 active 3.
3 poly
10 (1.1) 3 (2.1) 5 (2.3) 3 (2.4) nwell 1 (3.5)
nwell 3 0 or 4 pdiff
(2.2) (2.5)
nwell 3 (3.4)
pdiff pdiff ndiff nwell
0 (1.4) 9 (1.2) 2 (3.3)
ndiff 3 ndiff 0 or 4 pdiff
hot 2 (3.2)
pwell (2.2) (2.5)
pwell 0 or 6 (1.3) poly
3 (2.1) 5 (2.3) 3 (2.4) pwell
2 (3.1)
4
4. select
pwell nwell 5.
5 poly 2 (5.3a)
1.5
p-select n-select contact (5.2a)
poly
pdiff
ndiff 2 × 2 (5.1a)
6.
6 active
1 (4.3) 3 (4.1) contact 2 (6.3a) nwell
poly
1.5 (6.2a) 2 (6.4a)
ndiff pdiff
2 (4.2)
n-select p-select
poly
2 × 2 1.5
77. metal1 8.
8 via1 (6.1a) (6.2a)
1 (7.3)
pdiff poly 2 (8.4)
3 (7.1)
poly 2 (8.5) via1
3 1 (8.3)
metal2 contact
(7.2a)
m1 m2
active
contact m1 2 poly 2 (8.5) 2 × 2 (8.1)
(7.2b) 3 (8.2) ndiff
1 (7.4)
99. metal2 15.
15 metal3
10.
10 overglass (microns)
14.
14 via2
30 (10.4)
3 (9.1) m3 6 (10.3)
2 × 2 (14.1) 2 (14.4) m3
m2 6
m2 1 (15.1)
via2 (14.3) m2
via1
4 (15.2)
m3 15
3 1 3 (10.5)
(14.2) via1 glass
(9.2b) 4 (9.3) via2
(9.2a) m3 m1
m2
m1
2 (15.3) 100 × 100 (10.1)

Scalable CMOS design rules

ASICs... THE COURSE 2.4 Combinational Logic Cells 15

2.4 Combinational Logic Cells

The AOI family of cells with three index numbers or less
Cell type1 Cells Number of unique cells
Xa1 X21, X31 2
Xa11 X211, X311 2
Xab X22, X33, X32 3
Xab1 X221, X331, X321 3
Xabc X222, X333, X332, X322 4
Total 14
1Xabc: X={AOI, AO, OAI, OA}; a, b, c = {2, 3}; {} means “choose one.”

AOI221 OAI321

AND OR INVERT OR AND INVERT

A
Naming of complex CMOS com- A B
B Z C Z
binational logic cells C D
D E
E F
AOI221 OAI321
(a) (b)

2.4.1 Pushing Bubbles

2.4.2 Drive Strength

We ratio a cell to adjust its drive strength and make βn = βp to create equal rise and fall
times
16 SECTION 2 CMOS LOGIC ASICS... THE COURSE

OR = parallel
AND = series VDD VDD
A 6/1 6/1
B A B adjust
C Z 3 4 sizes
D C 6/1 6/1
D
1 E
push bubbles to the inputs 6/1 6/(1+1+1) =
E
Z 2/1
OR = parallel
A AND = series
B 1/1 2/1 2/1
C Z E A C
D 2/1 2/1
E 2 B D

(a) (b) (c)

Constructing a CMOS logic cell—an AOI221 • pushing bubbles • de Morgan’s theorem •

network duals

2.4.3 Transmission Gates

S'
strong '1' charge sharing
S=0 S'
A Z A Z
A Z '0'
S=1 VSMALL→VF VBIG→VF
A Z Z
S A
strong '0'
C SMALL '1' C BIG
S

(a) (b) (c)

CMOS transmission gate (TG, TX gate, pass gate, coupler)

Charge sharing: suppose CBIG =0.2pF and CSMALL =0.02pF, VBIG =0V and VSMALL =5V;
then

(0.2 × 10–12) (0) + (0.02 × 10–12) (5)

–––––––––––––––––––––––––––
VF = – = 0.45 V
(0.2 × 10–12) + (0.02 × 10–12)
ASICs... THE COURSE 2.5 Sequential Logic Cells 17

2.5 Sequential Logic Cells

Two choices for sequential logic: multiphase clocks or synchronous design. We choose
the latter.

2.5.1 Latch

CLKN latch is transparent

D Q D Q D Q
I1 I2 I1 I2 I1 I2
CLKP CLKP storage
loop
I3 I3 I3
CLKN
CLK
I4 I5
CLKN CLKP CLK CLK
D D
1D
C1 Q Q

t t
(a) (b) (c)

CMOS latch • enable • transparent • static • sequential logic cell • storage • initial value
18 SECTION 2 CMOS LOGIC ASICS... THE COURSE

2.5.2 Flip-Flop

master slave
CLKN CLKP
D M S Q
(a) I1 I2 I6 I8
CLKP CLKP CLKN CLKN
QN
I3 I7 I9
CLKN CLKP

CLK
I4 I5 1D
CLKN CLKP C1

load master

D M S Q
(b) I1 I2 I6 I8
store
CLK=1 QN
I3 I7 I9

load slave

D M S Q
(c) I1 I2 I6 I8
store
CLK=0
QN
I3 I7 I9

load master load slave load master load slave

CLK 50%
t SU
(d) D
tH
M decision
window
Q
tPD
t

CMOS flip-flop
• master latch • slave latch
• active clock edge • negative-edge–triggered flip-flop
• setup time (tSU) • hold time (tH) • clock-to-Q propagation delay (tPD)
• decision window
ASICs... THE COURSE 2.6 Datapath Logic Cells 19

2.6 Datapath Logic Cells

full adder (FA): SUM = A ⊕ B ⊕ CIN = SUM(A, B, CIN) = PARITY(A, B, CIN) ,
COUT = A · B + A · CIN + B · CIN = MAJ(A, B, CIN).

• parity function ('1' for an odd numbers of '1's)

• majority function ('1' if the majority of the inputs are '1')

S[i] = SUM (A[i], B[i], CIN)

COUT = MAJ (A[i], B[i], CIN)

COUT[2] COUT[3]

A[3] S[3] m2
B[3] m1
A B COUT
A[2] S[2]
CIN S
B[2] COUT[2] COUT[3]
CIN COUT A[1] S[1]
A ADD B[1]
B SUM A[0] S[0] control
B[0] m2 m2
CIN CIN[0]
data
VSS m1 m1 VSS
(a) (b) (c) (d)

A datapath adder
• Ripple-carry adder (RCA)
• Data signals • control signals • datapath • datapath cell or datapath element
• Datapath advantages: predictable and equal delay for each bit • built-in interconnect
• Disadvantages of a datapath: overhead • harder design • software is more complex
20 SECTION 2 CMOS LOGIC ASICS... THE COURSE

2.6.1 Datapath Elements

ASICs... THE COURSE 2.6 Datapath Logic Cells 21

Binary arithmetic
Binary Number Representation
Operation Signed Ones’ Two’s
Unsigned
magnitude complement complement
no change if positive then if negative if negative
MSB=0 then flip bits then {flip bits;
add 1}
else MSB=1
3= 0011 0011 0011 0011
–3= NA 1011 1100 1101
zero= 0000 0000 or 1000 1111 or 0000 0000
max. positive= 1111=15 0111=7 0111=7 0111=7
max. negative= 0000=0 1111=–7 1000=–7 1000=–8
addition= S=A+B if SG(A)=SG(B) S= S=A+B
then S=A+B
S= A+B A+B+COUT[MS
else {if B<A then B]
=addend+auge
S=A–B
nd
else S=B–A}
COUT is carry
out
SG(A)=sign of A
addition result: OR=COUT[M if SG(A)=SG(B) OV= OV=
SB] then
OV=overflow, XOR(COUT[MS XOR(COUT[MS
OV=COUT[MSB]
B], B],
OR=out of range
else OV=0 (impossi- COUT[MSB–1]) COUT[MSB–1]
COUT is carry
ble) )
out
SG(S)=sign of S NA if SG(A)=SG(B) NA NA
then SG(S)=SG(A)
else {if B<A then
S= A+B
SG(S)=SG(A)
else SG(S)=SG(B)}
subtraction= D=A–B SG(B)=NOT(SG(B)); Z=–B (negate); Z=–B (negate);
D= A–B D=A+B D=A+Z D=A+Z
=minuend
–subtrahend
22 SECTION 2 CMOS LOGIC ASICS... THE COURSE

subtraction OR=BOUT[M as in addition as in addition as in addition

result: SB]
OV=overflow, BOUT is bor-
row out
OR=out of range
negation: NA Z=A; Z=NOT(A) Z=NOT(A)+1
Z=–A (negate) SG(Z)=NOT(SG(A))

2.6.2 Adders
Generate, G[i] and propagate, P[i]

method 1 method 2
G[i] = A[i] · B[i] G[i] = A[i] · B[i]
P[i] = A[i] ⊕ B[i P[i] = A[i] + B[i]
C[i] = G[i] + P[i] · C[i–1] C[i] = G[i] + P[i] · C[i–1]
S[i] = P[i] ⊕ C[i–1] S[i] = A[i] ⊕ B[i] ⊕ C[i–1]

Carry signal:

either C[i] = A[i] · B[i] + P[i] · C[i – 1]

or C[i] = (A[i] + B[i]) · (P[i]' + C[i – 1]), where P[i]'=NOT(P[i])

Carry chain using two-input NAND gates, one per cell:

even stages odd stages

C1[i]' = P[i ] · C3[i – 1] · C4[i – 1] C3[i]' = P[i ] · C1[i – 1] · C2[i – 1]
C2[i] = A[i] + B[i ] C4[i]' = A[i] · B[i ]
C[i] = C1[i ] · C2[i ] C[i] = C3[i ]'+ C4[i ]'

Carry-save adder (CSA) cell CSA(A1[i], A2[i], A3[i ], CIN, S1[i], S2[i], COUT) has three out-
puts:

S1[i] = CIN ,
S2[i] = A1[i] ⊕ A2[i] ⊕ A3[i ] = PARITY(A1[i], A2[i], A3[i ])
COUT = A1[i] · A2[i] + [(A1[i] + A2[i]) · A3[i ]] = MAJ(A1[i], A2[i], A3[i ])
ASICs... THE COURSE 2.6 Datapath Logic Cells 23

Carry-propagate adder (CPA)

COUT[MSB] COUT[MSB–1]
COUT[MSB] OV
COUT[MSB–1]
COUT A1[MSB:0] n S1[MSB:0]
+ n
A1 A2[MSB:0] n
A2
CSA S1 + Σ
S2 +
A3 A3[MSB:0] n S2[MSB:0]
n
CIN CIN[0]

(a) (b) (c)

n n CSA1 CSA2 RCA
A1[MSB:0]
+ +
A2[MSB:0] n n MSB
+ Σ Σ S[MSB:0] bit slice
+ + n
n
A3[MSB:0] n + Σ
n +
+ CSA2 LSB
A4[MSB:0] n RCA
CSA1
(d) (e)

CLK CLK
CLK CLK CSA1 CSA2 RCA
n
A1[MSB:0] n 1 4
+ + S[MSB:0]
A2[MSB:0] n 2 + Σ Σ
+ + n n
A3[MSB:0] n + Σ 3 5
+
+ CSA2 RCA 1 23 4 5
A4[MSB:0] n
CSA1 pipeline registers
pipeline registers
(f) (g)

The carry-save adder (CSA) • pipeline • latency • bit slice

carry-bypass adders (CBA):

C[7]=(G[7]+P[7]·C[6])·BYPASS'+C[3]·BYPASS

carry-skip adder:

CSKIP[i] = (G[i] + P[i] · C[i – 1]) · SKIP' + C[i – 2] · SKIP

24 SECTION 2 CMOS LOGIC ASICS... THE COURSE

Carry-lookahead adder (CLA, for example the Brent–Kung adder):

C[1] = G[1] + P[1] · C[0]

= G[1] + P[1] · (G[0] + P[1] · C[–1])
= G[1] + P[1] · G[0]

C[2] = G[2] + P[2] · G[1] + P[2] · P[1] · G[0] ,

C[3] = G[3] + P[2] · G[2] + P[2] · P[1] · G[1] + P[3] · P[2] · P[1] · G[0]

C[3]= G[3]
C[2] =G[2] +P[3]G[2]
C[1] =G[1] +P[2]G[1] + P[3]P[2]G[1]
+P[0] +P[2]P[1]G[0] +P[3]P[2]P[1]G[0]
G[0]
P[0] P[0]P[1] P[0]P[1]P[2] P[0]P[1]P[2]P[3]
CLG CLG CLG
G[1] G[2] G[3]
P[1] L1 P[2] L2 P[3] L3

(a) C[1] C[2]

CLG G[0]
P[0] CLG CLG
G[i ] G[1]
G[i +1]+P[ i ] P[1] L1 L4
P[i ]
C[3]
G[i +1] G[2]
P[2] CLG CLG
P[i +1] P[i ]P[i + 1] G[3]
P[3] L2 L3

(b) Each wire is a bundle of (c)

G[i +1]+P[ i ] and P[i ]P[i +1].
G[i]/P[i ] in C[i ] out Create generate and propagate signals.
0 0
1 Create carry signals.
1
2 2 Create sum signals.
0
1 3 0 3
2 3 1 G[i ] C[i]
4 Sum[i ]
(d) 2 P[i ]
3 5
0
1 A[i ] B[i ] A[i ] B[i ]
4 6
0 2 5 or
1 P[i ]
6 7
2 3 7
3
(e) (f) (g)

The Brent–Kung carry-lookahead adder

Carry-select adder duplicates two small adders for the cases CIN='0' and CIN='1' and then
uses a MUX to select the case that we need
ASICs... THE COURSE 2.6 Datapath Logic Cells 25

(a) A[i ] B[i] (c)

H bit
1 0
A[1] B[1] A[0] B[0]
stage
0 H1 H0

A[i ].B[i ] carry out (carry in=0)

A[i] ⊕ B[i ] sum (carry in =0)
A[i ]+B[ i ] carry out (carry in=1)
(A[ i ] ⊕ B[i ])' sum (carry in =1)
1 Q1_1 Q1_0
(b) C1_0_1 C1_0_0

Si_j_1 or Si_j_0 or
Ci_j_1 Ci_j_0
Qi_j Ci_j_k
Si_j_k or Ci_j_k

Ci_j_k (k =0 or 1)
G1
Si_j_0 or Si_j_k or
Ci_j_0 1 2 Q2_1
1 Ci_j_k C[0]
Si_j_1 or
Ci_j_1 S[1] C[2] S[0]

Ci_j_k =carry in to the i th bit assuming the carry in to the j th bit is k (k =0 or 1)

Si_j_k =sum at the ith bit assuming the carry in to the jth bit is k (k =0 or 1)

The conditional-sum adder

26 SECTION 2 CMOS LOGIC ASICS... THE COURSE

2.6.3 A Simple Example

An 8-bit conditional-sum adder

module m8bitCSum (C0, a, b, s, C8); // Verilog conditional-sum adder
for an FPGA //1
input [7:0] C0, a, b; output [7:0] s; output C8; //2
wire
A7,A6,A5,A4,A3,A2,A1,A0,B7,B6,B5,B4,B3,B2,B1,B0,S8,S7,S6,S5,S4,S3,S2
,S1,S0; //3
wire C0, C2, C4_2_0, C4_2_1, S5_4_0, S5_4_1, C6, C6_4_0, C6_4_1,
C8; //4
assign {A7,A6,A5,A4,A3,A2,A1,A0} = a; assign
{B7,B6,B5,B4,B3,B2,B1,B0} = b; //5
assign s = { S7,S6,S5,S4,S3,S2,S1,S0 }; //6
assign S0 = A0^B0^C0 ; // start of level 1: & = AND, ^ = XOR, | =
OR, ! = NOT //7
assign S1 = A1^B1^(A0&B0|(A0|B0)&C0) ; //8
assign C2 = A1&B1|(A1|B1)&(A0&B0|(A0|B0)&C0) ; //9
assign C4_2_0 = A3&B3|(A3|B3)&(A2&B2) ; assign C4_2_1 =
A3&B3|(A3|B3)&(A2|B2) ; //10
assign S5_4_0 = A5^B5^(A4&B4) ; assign S5_4_1 = A5^B5^(A4|B4) ; //11
assign C6_4_0 = A5&B5|(A5|B5)&(A4&B4) ; assign C6_4_1 =
A5&B5|(A5|B5)&(A4|B4) ; //12
assign S2 = A2^B2^C2 ; // start of level 2 //13
assign S3 = A3^B3^(A2&B2|(A2|B2)&C2) ; //14
assign S4 = A4^B4^(C4_2_0|C4_2_1&C2) ; //15
assign S5 = S5_4_0&
!(C4_2_0|C4_2_1&C2)|S5_4_1&(C4_2_0|C4_2_1&C2) ; //16
assign C6 = C6_4_0|C6_4_1&(C4_2_0|C4_2_1&C2) ; //17
assign S6 = A6^B6^C6 ; // start of level 3 //18
assign S7 = A7^B7^(A6&B6|(A6|B6)&C6) ; //19
assign C8 = A7&B7|(A7|B7s)&(A6&B6|(A6|B6)&C6) ; //20
endmodule //21

2.6.4 Multipliers
• Mental arithmetic: 15 (multiplicand) × 19 (multiplier) = 15 × (20–1) = 15 × 21
• Suppose we want to multiply by B=00010111 (decimal 16+4+2+1=23)
• Use the canonical signed-digit vector (CSD vector) D= 00101001 (decimal 32–8+1=
23)
• B has a weight of 4, but D has a weight of 3 — and saves hardware
ASICs... THE COURSE 2.6 Datapath Logic Cells 27

normalized area/k λ2
delay
120 3000
ripple-carry ripple-carry

carry-select carry-select
80 2000
carry-save carry-save

40 1000

2-input
NAND =1
8 16 32 64 8 16 32 64
bits bits
(a) (b)

Datapath adders

To recode (or encode) any binary number, B, as a CSD vector, D: Di = Bi + Ci – 2Ci + 1 ,

where Ci +1 is the carry from the sum of Bi+1 +B i +C i (we start with C0 =0).

If B=011 (B2 =0, B 1 =1, B 0 =1; decimal 3), then: D0 = B0 + C0 – 2C1 = 1 + 0 – 2 = 1,

D1 = B1 + C1 – 2C2 = 1 + 1 – 2 = 0,
D2 = B2 + C2 – 2C3 = 0 + 1 – 0 = 1,
so that D= 101 (decimal 4–1=3).

We can use a radix other than 2, for example Booth encoding (radix-4):
B=101001 (decimal 9–32=–23) ⇒ E= 1 21 (decimal –16–8+1=–23)
B=01011 (eleven) ⇒ E= 11 1 (16–4–1)
B=101 ⇒ E= 11
28 SECTION 2 CMOS LOGIC ASICS... THE COURSE

Each dot
'0' A B represents
'0' '0' an output of
S50 S40 COUT CIN one stage
redundant FA and an
carry input to the S50 0
a0 b0 '0' full adder S50 S23 next. S41
'0'
S51 S41 S31 Sum S41 S14 S32
S23
S32 S05 S14
a1 b1 c1 5.1 5.2 S05
S42 S32 S22 1
5.1
b2 c2 d2 5.3
5.2
S33 S23 S13 '0' 2
5.3
c3 d3 e3 5.4
5.4 3
S24 S14 S04
half
adder 4
d4 e4 f4
S15 S05
5.5 5
e5 f5 5.5
full
adder P5 6
'0'
f6 (c)

P6 P5 P4 P5

carry-save chain Wallace tree

(a) (b)

Tree-based multiplication – at each stage we have the following three choices:

(1) sum three outputs using a full adder
(2) sum two outputs using a half adder
(3) pass the outputs to the next stage
ASICs... THE COURSE 2.6 Datapath Logic Cells 29

S54S45 S53S44 S52S43 S51S42 S50 S41 S23S14 S22S13 S21S12 S20S11 S10'0' S00
1 S S S S S S S S S
1 35 2 34 3 33 4 32 5 05 6 04 7 03 8 02 9 01

S25 S15
S S31 S30 P1 P0
2
10 11 12 24 13 14 15 16 '0'
'0'
S40 P2
3 17 18 19 20 21 '0'

P3
4 '0' 0
22 23 24 '0'

P4 1
5 25
2
6 P5 3
26
4
S55 A B
7 5
27 28 29 30 P6 COUT CIN
FA 6
full 7
P11 P10 P9 P8 P7 adder
P5
Sum

A Wallace-tree multiplier works forward from the multiplier inputs

• Full adder is a 3:2 compressor or (3, 2) counter
• Half adder is a (2, 2) counter
30 SECTION 2 CMOS LOGIC ASICS... THE COURSE

0
S25 S34 S15 S24 S42 S51 S05 S14 S32 S41 S04S13 S00
1
S43 S33 S23 '0'
1 2 3 '0' 4 5 6 '0'
2
3 S35 S44 S52 S22 S03 S12 P0
4 7 8 9 10 11 S31 12 '0'
S45 S54 S53 S50 S40 S21S02 S11

13 14 15 16 17 18 19 S30 20 S20
S55 '0' S10S01

21 22 23 24 25 26 27 28 29 30 '0'

P10 P9 P8 P7 P6 P5 P4 P3 P2 P1
P11

The Dadda multiplier works backward from the final product

• Each stage has a maximum of 2, 3, 4, 6, 9, 13, 19, ...outputs (each successive stage is
3/2 times larger—rounded down to an integer

The number of stages and thus delay (in units of an FA delay—excluding the CPA) for an n-bit
tree-based multiplier using (3, 2) counters is
log1.5 n = log10 n/log10 1.5 = log10 n/0.176
ASICs... THE COURSE 2.6 Datapath Logic Cells 31

A3
S32 two-input 2-bit A0 Z'0
AND submultiplier B0
B2
A3 A1 A3 A1 A1
A2 A0 A2 A0 B0 Z'1
B0 (3, 2) B0 A0
S32 B1 counter Z0 B1
B2 B1 B1 Z'2
B3
B2
(3, 2) A0
counter B3 B0 Z'4
A1
B1
(a) (b) (c)

Ferrari–Stefanelli architecture “nests” multipliers

32 SECTION 2 CMOS LOGIC ASICS... THE COURSE

2.6.5 Other Arithmetic Systems

binary decimal redundant binary CSD vector

1010111 87 10101001 10101001 addend
+ 1100101 101 + 11100111 + 01100101 augend
01001110 = 11001100 intermediate sum
11000101 11000000 intermediate carry
= 10111100 = 188 111000100 101001100 sum

Redundant binary addition • redundant binary encoding avoids carry propagation

Intermediate Intermediate
A[i] B[i] A[i–1] B[i–1]
sum carry
1 1 x x 0 1
A[i–1]=0/1 and
1 0 B[i–1]=0/1 1 0
0 1 A[i–1]=1 or B[i–1]=1 1 1
1 1 x x 0 0
1 1 x x 0 0
0 0 x x 0 0
A[i–1]=0/1 and
0 1 B[i–1]=0/1 1 1
1 0 A[i–1]=1 or B[i–1]=1 1 0
1 1 x x 0 1

• 101 (decimal) is 1100101 (in binary and CSD vector) or 11100111

• 188 (decimal) is 10111100 (in binary), 111000100, 101001100, or 101000100 (CSD
vector)
• 101 is represented as 010010 (using sign magnitude) — rather wasteful
Residue number system
• 11 (decimal) is represented as [1, 2] residue (5, 3)
• 11R5 =11 mod 5=1 and 11R3 =11 mod 3=2
• The size of this system is 3 × 5=15
• We can now add, subtract, or multiply without using any carry
ASICs... THE COURSE 2.6 Datapath Logic Cells 33

4 [4, 1] 12 [2, 0] 3 [3, 0]

+ 7 + [2, 1] –4 – [4, 1] × 4 × [4, 1]
= 11 = [1, 2] =8 = [3, 2] = 12 = [2, 0]

The 5, 3 residue number system

n residue 5 residue 3 n residue 5 residue 3 n residue 5 residue 3
0 0 0 5 0 2 10 0 1
1 1 1 6 1 0 11 1 2
2 2 2 7 2 1 12 2 0
3 3 0 8 3 2 13 3 1
4 4 1 9 4 0 14 4 2
34 SECTION 2 CMOS LOGIC ASICS... THE COURSE

2.6.6 Other Datapath Operators

Full subtracter DIFF = A ⊕ NOT(B) ⊕ ΝΟΤ(BIN)

= SUM(A, NOT(B), NOT(BIN))
NOT(BOUT
)= A · NOT(B) + A · NOT(BIN) + NOT(B) · NOT(BIN)
= MAJ(NOT(A), B, NOT(BIN))

CLK PRE A
Z[MSB:0]
D[MSB:0] Q[MSB:0]
A[MSB:0] Z[MSB:0] B[MSB:0]

B[MSB:0]
(c)

(a) (b)
A[MSB:0] + S[MSB:0]
S Σ
A[MSB:0] Z[MSB:0] Z[MSB:0] Z Z
0 +/-1 =0 =1 B[MSB:0] +/-
B[MSB:0] 1
(d) (e) (f) (g) (h)

Symbols for datapath elements

Keywords: adder/subtracter • barrel shifter • normalizer • denormalizer • leading-one detector

• priority encoder • exponent correcter • accumulator • multiplier–accumulator (MAC) •
incrementer • decrementer • incrementer/decrementer • all-zeros detector • all-ones detector
• register file • first-in first-out register (FIFO) • last-in first-out register (LIFO)
ASICs... THE COURSE 2.7 I/O Cells 35

2.7 I/O Cells

Keywords:Tri-State® is a registered trademark of National Semiconductor) • drivers • con-

tention • bus keeper or bus-hold cell (TI calls this Bus-Friendly logic) • slew rate • power-
supply bounce • simultaneously switching outputs (SSOs) • quiet-I/O • bidirectional I/O
• open-drain • level shifter • electrostatic discharge, or ESD • electrical overstress (EOS)
• ESD implant • human-body model (HBM) • machine model (MM) • charge-device model
(CDM, also called device charge–discharge) • latch-up • undershoot • overshoot • guard
rings

from core VDD

logic
ND1 M1
OE I/O
output pad
enable I2
A three-state bidirectional output buffer M2
DATAout

NR1
DATAin

to core I1
logic

2.8 Cell Compilers

Keywords: silicon compilers • RAM compiler • multiplier compiler • single-port RAM • dual-port
RAMs • multiport RAMs • asynchronous • synchronous • model compiler • netlist compiler •
correct by construction

2.9 Summary
• The use of transistors as switches
• The difference between a flip-flop and a latch
• The meaning of setup time and hold time
36 SECTION 2 CMOS LOGIC ASICS... THE COURSE

• Pipelines and latency

• The difference between datapath, standard-cell, and gate-array logic cells
• Strong and weak logic levels
• Pushing bubbles
• Ratio of logic
• Resistance per square of layers and their relative values in CMOS
• Design rules and λ

2.10 Problems
Suggested homework: 2.1, 2.2, 2.38, 2.39 (from ASICs... the book)