21 Regulation Vlsi Lab Manual
21 Regulation Vlsi Lab Manual
1 Exp 1: Realization of Combinational and Sequential Circuits using gate level modeling 1
2 Exp 2: Realization of digital circuits using behavioral modeling 2
Soft copy of manual (student’s Copy) will be posted in the Google classroom. Lab
report format should follow the following details
➢Aim
➢Software required
➢Pre-Lab answers
➢Circuit Diagram, Truth table, Boolean Expression for each problem statement
➢Program code
➢Test bench code
➢Simulated output
➢Post-Lab answers
➢Results
Laboratory Report Cover Sheet
Name:
Register No.:
Title of Experiment:
Date of Conduction:
Date of Submission:
Lab Report 05
Total 40
REPORT VERIFICATION
Staff Name :
Signature:
Lab Experiment #1
1.List the types of design methodologies for digital design with an example?
2.Give the difference between module and module instance.
3.What are built in gate primitives?
4.Give the use of net, reg. and wire data types.
5.Declare the following variables in Verilog:
Full adder:
// TEST BENCH
module half_adder_tb_v;
// Inputs
reg x; // reg
y; //Outputs
wire s; wire cout;
// Instantiate the Unit Under Test (UUT)
Half_adder uut (.s(s), .cout(cout), .x(x), .y(y) );
initial begin // Initialize Inputs
x = 0; y = 0;
Wait 100 ns for global reset to finish #100; x=0; y=1;
#100; x=1; y=0; #100; x=1; y=1; Add
stimulus here
end
endmodule
wire c1,c2,c3;
full_adder f1(S[0],c1,A[0],B[0],cin);
full_adder f2(S[1],c2,A[1],B[1],c1);
full_adder f3(S[2],c3,A[2],B[2],c2);
full_adder f4(S[3],cout,A[3],B[3],c3);
endmodule
// TEST BENCH
module ripple_carry_adder_tb_v;
// Inputs
reg [3:0] A; reg [3:0] B; reg cin;
// Outputs wire [3:0] S;
wire cout;
// Instantiate the Unit Under Test (UUT) ripple_carry_adder uut (.S(S),
.cout(cout), .A(A), .B(B), .cin(cin)); initial begin
//Initialize Inputs A = 0; B = 0; cin = 0;
//Wait 100 ns for global reset to finish #100; A=0; B=0; cin=1;
#100; A=0; B=1; cin=0; #100; A=0; B=1; cin=1; #100; A=1; B=0; cin=0; #100; A=1;
B=0; cin=1; #100; A=1; B=1; cin=0; #100; A=1; B=1; cin=1;
//Add stimulus here End
endmodule
Waveforms – Problem 1
1.5 Result:
Thus, the design of combinational and Sequential logic circuits was simulated in Verilog and
synthesized using Xilinx vivado tools.
Lab Experiment #2
Realization of Digital Circuits Using Behavioral Modeling
2.1 Objective: To realize the design of digital circuits in Verilog using behavioral and switch
level modelling then simulating and synthesizing using Xilinx vivado tools.
Logic Diagram
D flip flop
flip flop
T
Verilog
Code - Problem 1
1.(a) POSITIVE EDGE TRIGGERED D FLIPFLOP USING IF STATEMENT
// TEST BENCH
module
dff_tb_v; //
Inputs reg d; reg
clk; reg clear; //
Outputs wire q;
wire qbar;
// TEST BENCH
module tffcase_tb_v;
// Inputs
reg clk; reg clr; reg t; //Outputs
wire q;
//Instantiate the Unit Under Test (UUT) tffcase uut (.q(q),.clk(clk),.clr(clr),.t(t)); initial begin
//Initialize Inputs clk = 0; clr = 1; t = 0;
//Wait 100 ns for global reset to finish #100; clr=0;
#100; clr=0; t=1;
//Add stimulus here
end
always #50
clk=~clk;
endmodule
Waveforms – Problem 1
Mod-N Counter:
SISO Register:
// TEST BENCH
module updowncntr_tb_v;
// Inputs
reg clr; reg clk; reg mod; //Outputs
wire [3:0]q;
//Instantiate the Unit Under Test (UUT) updowncntr uut (.q(q),.clr(clr),.clk(clk),.mod(mod));
initial begin // Initialize Inputs clr = 1; clk = 0; mod = 1;
//Wait 100 ns for global reset to finish #100; clr=0;
#1000; mod=0;
//Add stimulus here
end always #50
clk=~clk;
endmodule
module modN_ctr
# (parameter N = 10,
parameter WIDTH = 4)
( input clk,
input rstn, output
reg[WIDTH-1:0] out);
always @ (posedge clk) begin
if (rstn) begin
out <= 0; end
else begin if
(out == N-1)
out <= 0;
else out <=
out + 1; end
end
endmodule
// TEST BENCH
module modncounter_tb_v;
// Inputs
reg clk;
reg rstn;
// Outputs
wire [3:0] out;
// Inputs reg
shift_in; reg
clk; // Outputs
wire
shift_out;
// Instantiate the Unit Under Test (UUT)
siso_register uut ( .shift_out(shift_out),
.shift_in(shift_in),
.clk(clk)
);
initial begin //
Initialize Inputs
shift_in = 1;
clk = 1;
#100 shift_in = 0;
#100 shift_in = 1;
#100 shift_in = 0;
// Add stimulus here
Waveforms – Problem 2
2.3 Result:
Thus, the design of Digital circuits using behavioral and Switch level modelling is simulated in
Verilog and synthesized using EDA tools.
Lab Experiment #3
Design of Finite State Machine (FSM) and Algorithmic State
Machine
3.1 Objective:
To learn the design of Finite State Machine (FSM) and Algorithmic State Machine
(ASM) for any application in Verilog, the simulating and synthesizing using Xilinx vivado
tools.
3.2 Tools Required:
Software’s: Xilinx vivado
3.3 Pre Lab Questions:
1. Draw the simple model of FSM.
2. What is the basic Algorithm of Sequence Detector?
3. List the difference between Mealy and Moore Model.
4. What is ASM Chart and what are its main components?
3.4.1 Problem:
1. Implement Sequence recognizer for detecting three successive 1’s using Mealy Model
(Behavioural Modelling).
Mealy model for 111 Detector (FSM):
module fsm_mealy_111_tb_v;
// Inputs
reg reset;
reg a; reg
clk; //
Outputs
wire o;
// Instantiate the Unit Under Test (UUT)
fsm_mealy_111 uut (
.o(o),
.reset(reset),
.a(a),
.clk(clk)
); initial begin //
Initialize Inputs
reset = 1; a = 1;
clk = 1;
// Wait 100 ns for global reset to finish
#100;
reset = 0;
a = 1; #100;
reset = 0; a =
1; #100;
reset = 0; a =
1; #100;
reset = 0; a =
0; #100;
reset = 0; a =
1; #100;
// Add stimulus here end
always #50 clk=~clk;
endmodule
Simulation Result:
3.4.2 Consider the following state graph of a sequential network which has both Mealy
and Moore outputs. The outputs Y1 and Y2 are the Mealy outputs and so should be
conditional outputs. The Ya, Yb, and Yc are the Moore outputs so they should be part of
state box. Input X can either be “0” or “1” and hence it should be part of the decision box.
Draw the ASM Chart for the above state graph and implement using Verilog.
ASM Chart:
Verilog Program:
module asm (input clk, input x, output reg ya, output reg yb, output reg yc, output
reg y1, output reg y2);
reg [1:0] state, nextstate;
parameter [1:0] S0=0, S1=1, S2=2;
always @(posedge clk)// always block to update state state <= nextstate;
always @(state or x) // always block to compute both Mealy output & next
state begin y1 = 1'b0; y2 = 1'b0; case (state) S0: if(x) nextstate = S1;
else nextstate = S0;
S1: if(x)
nextstate = S2;
else nextstate
= S0; S2: if(x)
begin
y2 = 1'b1;
nextstate = S1; end
else begin
y1 = 1'b1; nextstate = S0; end default:nextstate
= S0; endcase end always @(state) // always block to
compute Moore output begin ya = 1'b0; yb = 1'b0;
yc = 1'b0; case(state) //begin
S0: ya = 1'b1;
S1: yb = 1'b1;
S2: yc =
1'b1; //end
default: begin
ya = 1'b0; yb
= 1'b0; yc =
1'b0; end
endcase
end
endmodule
Test Bench: module
asm_tb_v;
// Inputs
reg clk;
reg x; //
Outputs
wire ya;
wire yb;
wire yc;
wire y1;
wire y2;
// Instantiate the Unit Under Test (UUT)
asm uut ( .clk(clk),
.x(x),
.ya(ya),
.yb(yb),
.yc(yc),
.y1(y1), .y2(y2)
); initial begin //
Initialize Inputs x
= 1; clk = 1;
// Wait 100 ns for global reset to finish
#100;
x = 1;
#100;
x = 1;
#100;
x = 1;
#100;
x = 0;
#100;
// Add stimulus here
end always #50
clk=~clk;
// Add stimulus
here endmodule
Output:
4.4 Problem: Write a Verilog code to implement the 4-bit Carry Look-ahead adder using
structural model.
Logic Diagram:
Test bench:
module carry_lookahead_adder_tb ();
parameter WIDTH = 3;
reg [WIDTH-1:0] r_ADD_1 = 0;
reg [WIDTH-1:0] r_ADD_2 = 0;
wire [WIDTH:0] w_RESULT;
CLA_4bit #(.WIDTH(WIDTH)) carry_lookahead_inst
( .i_add1(r_ADD_1), .i_add2(r_ADD_2),
.o_result(w_RESULT) );
5.4 Problem: Write a Verilog code to implement the 4-bit Carry Look-ahead adder using
structural model.
Logic Diagram:
module propagate_p(a,b,p,bp);
input [3:0] a,b; output [3:0] p; output
bp; assign p= a^b;//get all propagate
bits assign bp= &p;// and p0p1p2p3
bits
endmodule
TEST BENCH:
module
carry_skip_4bit_addertb; wire
[7:0]Y; wire carryout; reg
[7:0]A,B; reg carryin;
carry_skip_4bit csa1 (Y,carryout,A,B,carryin);
initial begin
$display("RSLT\tA\tB\tCYIN\t\tCYOUT\tSU
M");
//A = 4'b0101; B = 4'b1101; carryin = 0; #50; // Set inputs and add delay
A = 0; B = 0; carryin = 0; #50; // Set inputs and add delay
A = 3; B = 2; carryin = 1; #50; // Set inputs and add delay
A = 7; B = 10; carryin = 0; #50; // Set inputs and add delay
A = 15; B = 15; carryin = 1; #50; // Set inputs and add delay
A = 255; B = 55; carryin = 0; #50; // Set inputs and add delay
A = 255; B = 255; carryin = 1; #50; // Set inputs and add delay
/*
//if ( (carryout == 1 ) && (Y === 4'b0010) )
if ( (carryout == 1 ) && (Y === 2) )
$display("PASS\t%p\t%p\t%d\t=\t%d\p%p",A,B,carryin,carryout,Y); else
$display("FAIL\t%p\t%p\t%d\t=\t%d\t%p",A,B,carryin,carryout,Y);
*/
end
//enabling the wave dump
initial begin
$dumpfile("dump.vcd"); $dumpvars;
end
endmodule
Simulation Waveform:
5.6 Result
Thus, the design of 4-bit carry look-ahead adder circuit was simulated in Verilog and
synthesized using Xilinx vivado tools.
Lab Experiment #6
Realization of Multiplier-1
6.1 Objective: To design and simulate the Braun array multiplier in Verilog and synthesize
using Xilinx vivado tools.
6.4 Problem: Write a Verilog code to implement the 4-bit Braun Array multipliers using
structural model. Logic Diagram
// TEST BENCH
module braun_test_v;
// Inputs
reg [3:0] a;
reg [3:0] b;
// Outputs
wire [7:0]p;
// Instantiate the Unit Under Test (UUT) braun uut (
.a(a),
.b(b),
.p(p));
initial begin
// Initialize
Inputs a =
0; b = 0;
#100;a=1101; b=1001; end
endmodule
Simulation waveforms:
6.6 Result
Thus, the design of 4-bit Braun array multiplier circuit was simulated in Verilog and
synthesized using Xilinx vivado tools.
Lab Experiment #7
Realization of Multiplier-II
7.1 Objective: To design and simulate the Wallace tree multiplier in Verilog and synthesize
using Xilinx vivado tools
7.4 Problem:
Write a Verilog code to implement the 4-bit Wallace tree multipliers using structural model.
Logic Diagram:
Source code:
Thus, the design of 4-bit Wallace tree multiplier circuit was simulated in Verilog and
synthesized using Xilinx vivado tools
Lab Experiment #8
Realization of Memory
8.1 Objective:
Design memory using Verilog and Simulate using Xilinx Tool.
8.3 Prelab:
1.What are the different types of memory? Compare its performance.
2.Write the difference between static and dynamic memory.
3.Define port for 32*64k RAM memory.
Logic Diagram:
Program:
TEST BENCH:
module RAM_Test_v;
// Inputs
reg [3:0] Data; reg RD;
reg WR; reg [3:0]
Address; //
Outputs wire
[3:0] Output;
// Instantiate the Unit Under Test (UUT)
emory_Design uut
(.Data(Data),.RD(RD),.WR(WR),.Address(Address),.Output(Output));
initial begin
Data = 4'b0000; RD = 0; WR = 1; Address = 4'b0000; #30;
Data = 4'b0001; RD = 0; WR = 1; Address = 4'b0001; #30;
Data = 4'b0010; RD = 0; WR = 1; Address = 4'b0010; #30;
Data = 4'b0011; RD = 0; WR = 1; Address = 4'b0011; #30;
Data = 4'b0100; RD = 0; WR = 1; Address = 4'b0100; #30;
Data = 4'b0101; RD = 0; WR = 1; Address = 4'b0101; #30;
Data = 4'b0110; RD = 0; WR = 1; Address = 4'b0110; #30;
Data = 4'b0111; RD = 0; WR = 1; Address = 4'b0111; #30;
Data = 4'b1000; RD = 0; WR = 1; Address = 4'b1000; #30;
Data = 4'b1001; RD = 0; WR = 1; Address = 4'b1001; #30;
Data = 4'b1010; RD = 0; WR = 1; Address = 4'b1010; #30;
Data = 4'b1011; RD = 0; WR = 1; Address = 4'b1011; #30;
Data = 4'b1100; RD = 0; WR = 1; Address = 4'b1100; #30;
#100;
End
endmodule
Simulation Output:
Statement 2:
Block Diagram:
Program:
Module ROM_16x4(Address, RD, Output); input[3:0] Address; input
RD;
output reg[3:0] Output; reg[3:0]
ROM[15:0]; initial begin
ROM[4'b0000]=4'b1111; ROM[4'b0001]=4'b1110;
Test Bench:
module ROM_Test_v;
// Inputs
reg [3:0] Address; reg RD;
// Outputs wire
[3:0] Output;
// Instantiate the Unit Under Test (UUT)
ROM_16x4 uut (.Address(Address),.RD(RD),.Output(Output)); initial begin
// Initialize Inputs
Address = 4'b0000; RD = 1; #50;
Address = 4'b0001; RD = 1; #50;
endmodule
Simulation:
8.6 Result:
Design of a 16x4 ROM in Verilog is Performed and Verified using Xilinx Tool.
Lab Experiment #9
Design and Analysis of CMOS inverter
9.1 Objective: To learn the design of CMOS inverter in circuit level and get the spice netlist using
LTSPICE tool.
LTSPICE tool.
9.4 Problem 1: Design and analyse the CMOS inverter in circuit level, verify the transfer
characteristics and infer the SPICE netlist using LTSPICE.
9.4.1 Logic Diagram
9.4.2 Circuit design of CMOS Inverter in LTSPICE:
9.6 Result:
Thus, the design and analysis of CMOS Inverter has been performed, transfer characteristics have been
verified using LTSPICE tool.
LAB EXPERIMENT # 10
Circuit Diagram:
.option post
.include c:\synopsys\tsmc018.lib
vdd 1 0 dc 1.8v
vin1 4 0 pulse(-5 5 2ns 2ns 2ns 80us 160us) //(input A)
vin2 6 0 pulse(-5 5 2ns 2ns 2ns 50us 100us) //(input B)
vin3 2 0 pulse(-5 5 2ns 2ns 2ns 50us 100us) //(CLOCK)
vin4 8 0 pulse(-5 5 2ns 2ns 2ns 50us 100us) //(CLOCK)
m1 3 2 1 1 cmosp w=4u l=180nm
m2 3 4 5 5 cmosn w=2u l=180nm
m3 5 6 7 7 cmosn w=2u l=180nm
m4 7 8 0 0 cmosn w=2u l=180nm
c1 3 0 100p // (CAPACITOR→
Vary the capacitor value to see the
dynamic performance) .tran 100u
800u
.plot v(3) v(4) V(6)
.end
10.7 Netlist :
.option post
.include c:\synopsys\tsmc018.lib
* t58f spice bsim3 version 3.1 parameters
*
* spice 3f5 level 8, star-hspice level 49, utmost level 8 *
* temperature_parameters=default
*
vdd 1 0 dc 1.8v
vin1 4 0 pulse(-5 5 2ns 2ns 2ns 80us 160us)
vin2 6 0 pulse(-5 5 2ns 2ns 2ns 50us 100us)
vin3 2 0 pulse(-5 5 2ns 2ns 2ns 50us 100us)
vin4 8 0 pulse(-5 5 2ns 2ns 2ns 50us 100us)
m1 3 2 1 1 cmosp w=4u l=180nm
m2 3 4 5 5 cmosn w=2u l=180nm
m3 5 6 7 7 cmosn w=2u l=180nm
m4 7 8 0 0 cmosn w=2u
l=180nm c1 3 0 100p .tran
100u 800u
.plot v(3) v(4) v(6)
.end
******
dynamic nand
****** mos model parameters tnom= 25.000 temp= 25.000
******
*************************************************************************** ***
model parameters model name: 0:cmosn model type:nmos ***
***************************************************************************
Model: 0:cmosn
W = 1.99e-006, L = 1.8e-007
dynamic nand
****** operating point information tnom= 25.000 temp= 25.000
******
***** operating point status is voltage simulation time is 0.
node =voltage node =voltage node =voltage
******
dynamic nand
****** transient analysis tnom= 25.000 temp= 25.000
******
a
legend:
a: v(3)
b: v(4)
c: v(6)
time
v(3)
(abc ) -10.0000 -5.0000 0. 5.0000 10.0000
+ + + + +
0. 1.800 -+------+------2------+------+----a-+------+------+------+-
100.0000u 1.800 + + 2 + + a+ + + +
200.0000u 1.800 + + c + + a+ b + +
300.0000u 1.800 + + 2 + + a+ + + +
400.0000u 1.800 + + c + + a+ b + +
500.0000u 1.800 + + c + + a+ b + +
600.0000u 1.800 + + 2 + + a+ + + +
700.0000u 1.800 + + c + + a+ b + +
800.0000u 1.800 + + 2 + + a+ + + +
+ + + + +
B
dynamic nand
****** job statistics summary tnom= 25.000 temp= 25.000
******
# nodes = 9 # elements= 10
# diodes= 0 # bjts = 0 # jfets = 0 # mosfets = 4
# va device = 0
op point 0.03 1 32
transient 0.05 9 2016 560 rev= 114
readin 0.01 errchk 0.00 setup 0.00
output 0.00
total cpu time 0.14 seconds
job started at 12:36:05 02/26/2020 job
ended at 12:36:05 02/26/2020
10.6 Result:
Thus the design of two input dynamic NAND gate, MOS transistor level using HSPICE was studied
and simulated.