LS1043ARM
Uploaded by
hwtest147LS1043ARM
Uploaded by
hwtest147QorIQ LS1043A Reference Manual
Supports LS1023A
Document Number: LS1043ARM
Rev. 4, 6/2018
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
2 NXP Semiconductors
Contents
Section number Title Page
Chapter 1
Overview
1.1 Introduction...................................................................................................................................................................159
1.2 Features summary......................................................................................................................................................... 160
1.3 Application examples....................................................................................................................................................161
1.3.1 Multi-service branch office router............................................................................................................... 161
1.3.2 Security appliance/UTM.............................................................................................................................. 162
1.4 Module features ........................................................................................................................................................... 163
1.4.1 Arm® Cortex®-A53 core............................................................................................................................ 163
1.4.2 System memory management unit MMU-500.............................................................................................164
1.4.3 Arm CoreLink CCI-400 cache coherent interconnect................................................................................. 165
1.4.4 PreBoot loader (PBL) and nonvolatile memory interfaces.......................................................................... 165
1.4.5 DDR memory controllers.............................................................................................................................166
1.4.6 Enhanced direct memory access (eDMA) and direct memory access multiplexer (DMAMUX)............... 166
1.4.7 DUART........................................................................................................................................................ 167
1.4.8 FlexTimer module (FTM)............................................................................................................................ 167
1.4.9 Integrated flash controller (IFC).................................................................................................................. 167
1.4.9.1 IFC NAND flash controller features........................................................................................ 168
1.4.9.2 IFC NOR flash controller features........................................................................................... 168
1.4.9.3 IFC GPCM controller features................................................................................................. 168
1.4.10 Universal Serial Bus (USB) controllers and PHY....................................................................................... 169
1.4.11 High speed I/O interfaces.............................................................................................................................169
1.4.11.1 Serial ATA (SATA) controller................................................................................................ 169
1.4.11.2 PCI Express..............................................................................................................................170
1.4.11.3 SGMII ..................................................................................................................................... 171
1.4.12 QUICC Engine (QE).................................................................................................................................... 171
1.4.13 Enhanced secure digital host controller and SDIO...................................................................................... 171
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 3
Section number Title Page
1.4.14 Security Engine (SEC)................................................................................................................................. 171
1.4.15 Inter-Integrated Circuit (I2C).......................................................................................................................172
1.4.16 Low Power Universal asynchronous receiver/ transmitter (LPUART)....................................................... 172
1.4.17 Quad Serial Peripheral Interface (QuadSPI)................................................................................................ 173
1.4.18 Queue Direct Memory Access Controller (qDMA).....................................................................................173
1.4.19 Serial Peripheral Interface (SPI).................................................................................................................. 173
1.4.20 Watchdog Timer (WDOG).......................................................................................................................... 174
Chapter 2
Memory Map
2.1 Memory map overview................................................................................................................................................. 175
2.2 Fixed memory map....................................................................................................................................................... 175
2.2.1 DDR remapping........................................................................................................................................... 177
2.3 CCSR address map....................................................................................................................................................... 178
Chapter 3
Signal Descriptions
3.1 Signals introduction...................................................................................................................................................... 185
3.2 Signals overview...........................................................................................................................................................185
3.3 Configuration signals sampled at reset ........................................................................................................................ 216
3.4 Signal multiplexing details........................................................................................................................................... 217
3.4.1 UART, GPIO, FTM, and LPUART signal multiplexing............................................................................. 217
3.4.2 ASLEEP and GPIO1 signal multiplexing.................................................................................................... 218
3.4.3 RTC and GPIO1 signal multiplexing...........................................................................................................219
3.4.4 eSDHC, GPIO2, and GPIO4 signal multiplexing........................................................................................219
3.4.5 External IRQ, QE, and GPIO1 signal multiplexing.....................................................................................220
3.4.6 SPI, eSDHC, USB and GPIO2 signal multiplexing.....................................................................................222
3.4.7 IFC, QuadSPI, FTM and GPIO2 signal multiplexing..................................................................................223
3.4.8 Ethernet controller 1, FTM1, and GPIO3 signal multiplexing.................................................................... 225
3.4.9 Ethernet controller 2, GPIO3, FTM2, and IEEE1588 signal multiplexing..................................................226
3.4.10 Ethernet management interface1 and GPIO3 signal multiplexing...............................................................227
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
4 NXP Semiconductors
Section number Title Page
3.4.11 Ethernet management interface2 and GPIO4 signal multiplexing...............................................................227
3.4.12 I2C2, GPIO4, FTM, QE and eSDHC signal multiplexing...........................................................................228
3.4.13 USB and GPIO4 signal multiplexing...........................................................................................................228
3.5 Output Signal States During Reset............................................................................................................................... 229
Chapter 4
Reset, Clocking, and Initialization
4.1 Reset, clocking, and initialization overview................................................................................................................. 231
4.2 External signal descriptions.......................................................................................................................................... 231
4.2.1 System control signals................................................................................................................................. 232
4.2.2 External clock signals.................................................................................................................................. 233
4.3 Clocking Memory Map.................................................................................................................................................234
4.3.1 Core cluster n clock control/status register (Clocking_CLKCCSR)........................................................... 235
4.3.2 Clock generator n hardware accelerator control/status register (Clocking_CLnKCGHWACSR).............. 236
4.3.3 PLL cluster n general status register (Clocking_PLLCnGSR).................................................................... 238
4.3.4 Platform clock domain control/status register (Clocking_CLKPCSR)....................................................... 240
4.3.5 Platform PLL general status register (Clocking_PLLPGSR)...................................................................... 241
4.3.6 DDR PLL general status register (Clocking_PLLDGSR)........................................................................... 243
4.4 Functional description...................................................................................................................................................244
4.4.1 Power-on reset sequence.............................................................................................................................. 244
4.4.2 Hard reset sequence..................................................................................................................................... 247
4.4.3 Core soft reset.............................................................................................................................................. 248
4.4.4 RCW state timing.........................................................................................................................................248
4.4.5 Power-on reset configuration....................................................................................................................... 249
4.4.5.1 Reset configuration word (RCW) source.................................................................................250
4.4.5.2 General-purpose input..............................................................................................................252
4.4.5.3 DRAM type select....................................................................................................................253
4.4.5.4 Single oscillator source clock select........................................................................................ 253
4.4.5.5 IFC external transceiver enable polarity select........................................................................ 254
4.4.6 Reset configuration word (RCW)................................................................................................................ 254
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 5
Section number Title Page
4.4.6.1 RCW field definitions.............................................................................................................. 255
4.4.6.2 Hard-coded RCW options........................................................................................................ 270
4.4.6.3 RCW settings for hard-coded Options..................................................................................... 271
4.4.7 Clocking....................................................................................................................................................... 273
4.4.7.1 Single source clocking............................................................................................................. 274
4.4.7.1.1 Single oscillator source reference clock mode....................................................274
4.4.7.1.2 Dual reference clock mode................................................................................. 275
4.4.7.1.3 Multiple reference clock mode........................................................................... 276
4.4.7.2 IP logic clock distribution and configuration...........................................................................277
4.4.7.3 CLK_OUT configuration......................................................................................................... 280
Chapter 5
Interrupt Assignments
5.1 Introduction...................................................................................................................................................................281
5.2 Internal interrupt sources.............................................................................................................................................. 281
Chapter 6
Arm Modules
6.1 Introduction...................................................................................................................................................................289
6.2 Arm® Cortex®-A53 core............................................................................................................................................. 290
6.3 Arm generic interrupt controller (GIC-400)................................................................................................................. 291
6.4 System memory management unit (MMU-500)...........................................................................................................292
Chapter 7
CSU, OCRAM, and MSCM
7.1 Central Security Unit.................................................................................................................................................... 295
7.1.1 CSU Memory Map/Register Definition....................................................................................................... 295
7.1.1.1 Config Security Level (CSU_CSL)......................................................................................... 296
7.1.1.2 Secure Access register (CSU_SAn)......................................................................................... 302
7.1.2 Initialization Policy...................................................................................................................................... 306
7.2 On-Chip RAM memory controller (OCRAM)............................................................................................................. 306
7.3 Miscellaneous System Control Module (MSCM)........................................................................................................ 306
7.3.1 MSCM Access Control and TrustZone Security (ACTZS)Memory Map/Register Definition................... 307
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
6 NXP Semiconductors
Section number Title Page
7.3.1.1 ACTZS CSL Interrupt Enable Register (MSCM_ACTZS_CSLIER)..................................... 307
7.3.1.2 ACTZS CSL Interrupt Register (MSCM_ACTZS_CSLIR)....................................................310
7.3.1.3 ACTZS CSL Interrupt Overrun Register (MSCM_ACTZS_CSOVR)................................... 313
7.3.2 ACTZS CSLn Fail Status Capture Registers (Memory Map/Register Definition)..................................... 315
7.3.2.1 ACTZS CSLn Fail Status Address (Low) Register (MSCM_CSFARn)................................. 319
7.3.2.2 ACTZS CSLn Fail Status Control Register (MSCM_CSFCRn)............................................. 320
7.3.2.3 ACTZS CSLn Fail Status Master ID Register (MSCM_CSFIRn).......................................... 321
7.3.2.4 ACTZS CSLn Fail Status Address (Low) Register (MSCM_CSFARn)................................. 322
7.3.2.5 ACTZS CSLn Fail Status Control Register (MSCM_CSFCRn)............................................. 323
7.3.2.6 ACTZS CSLn Fail Status Master ID Register (MSCM_CSFIRn).......................................... 324
7.3.2.7 ACTZS CSLn Fail Status Address (Low) Register (MSCM_CSFARn)................................. 325
7.3.2.8 ACTZS CSLn Fail Status Control Register (MSCM_CSFCRn)............................................. 326
7.3.2.9 ACTZS CSLn Fail Status Master ID Register (MSCM_CSFIRn).......................................... 327
7.3.2.10 ACTZS CSLn Fail Status Address (Low) Register (MSCM_CSFARn)................................. 328
7.3.2.11 ACTZS CSLn Fail Status Master ID Register (MSCM_CSFIRn).......................................... 329
7.3.2.12 ACTZS CSLn Fail Status Control Register (MSCM_CSFCRn)............................................. 329
Chapter 8
System Counter
8.1 System counter..............................................................................................................................................................331
8.1.1 Secure system counter memory map/register definition..............................................................................331
8.1.1.1 Control register (Secure_system_counter_CNTCR)............................................................... 332
8.1.1.2 LSB of counter count value register (Secure_system_counter_CNTCV1)............................. 332
8.1.1.3 MSB of counter count value register (Secure_system_counter_CNTCV2)............................ 333
8.1.1.4 Counter frequency mode table base frequency register
(Secure_system_counter_CNTFID0).......................................................................................333
8.1.1.5 Counter frequency mode table end frequency register (Secure_system_counter_CNTFID1) 334
8.1.2 Non-Secure system counter memory map/register definition......................................................................334
8.1.2.1 LSB of Counter Count Value (Non_Secure_SYS_Counter_CNCTV_RO1).......................... 335
8.1.2.2 MSB of counter count value register (Non_Secure_SYS_Counter_CNCTV2_RO2).............335
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 7
Section number Title Page
Chapter 9
Interconnect Fabric
9.1 Introduction...................................................................................................................................................................337
9.2 QoS generators..............................................................................................................................................................337
9.2.1 Fixed QoS generator.................................................................................................................................... 337
9.2.2 Limiter QoS generator................................................................................................................................. 337
9.2.3 Regulator QoS generator..............................................................................................................................338
9.3 IF Memory Map/Register Definition............................................................................................................................ 338
9.3.1 Priority qdma (IF_prio_qdma_read_only)................................................................................................... 339
9.3.2 Mode qdma (IF_mod_qdma_read_only)..................................................................................................... 340
9.3.3 Bandwidth qdma (IF_bw_qdma_read_only)............................................................................................... 340
9.3.4 Saturation qdma (IF_sat_qdma_read_only).................................................................................................341
9.3.5 ExtControl qdma (IF_ext_cntrl_qdma_read_only)......................................................................................341
9.3.6 Priority qdma (IF_prio_qdma_write_only)..................................................................................................342
9.3.7 Mode qdma (IF_mod_qdma_write_only).................................................................................................... 342
9.3.8 Bandwidth qdma (IF_bw_qdma_write_only).............................................................................................. 343
9.3.9 Saturation qdma (IF_sat_qdma_write_only)............................................................................................... 343
9.3.10 ExtControl qdma (IF_ext_cntrl_qdma_write_only).................................................................................... 344
9.3.11 Priority pex (IF_prio_pex_read_only)......................................................................................................... 344
9.3.12 Mode_pex (IF_mod_pex_read_only).......................................................................................................... 345
9.3.13 Bandwidth_pex (IF_bw_pex_read_only).................................................................................................... 346
9.3.14 Saturation_pex (IF_sat_pex_read_only)...................................................................................................... 346
9.3.15 ExtControl_pex_ro (IF_ext_cntrl_pex_ro).................................................................................................. 347
9.3.16 Priority_pex (IF_prio_pex_write_only)....................................................................................................... 347
9.3.17 Mode_pex (IF_mod_pex_write_only)......................................................................................................... 348
9.3.18 Bandwidth_pex (IF_bw_smmu_pex_write_only)....................................................................................... 349
9.3.19 Saturation_pex (IF_sat_pex_write_only).....................................................................................................349
9.3.20 ExtControl_pex_wo (IF_ext_cntrl_pex_write_only)...................................................................................350
Chapter 10
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
8 NXP Semiconductors
Section number Title Page
Cache Coherent Interconnect (CCI-400)
10.1 The CCI-400 module as implemented on the chip....................................................................................................... 351
10.1.1 LS1043A CCI module integration............................................................................................................... 351
10.1.2 Connections to the CCI-400 interconnect.................................................................................................... 352
10.1.3 Snoop transaction configurations.................................................................................................................353
10.2 Functional Description..................................................................................................................................................354
10.2.1 About the functions...................................................................................................................................... 354
10.2.2 Snoop connectivity and control....................................................................................................................354
10.2.2.1 Removing a master from the coherent domain........................................................................ 355
10.2.3 Speculative fetch.......................................................................................................................................... 356
10.2.4 Security........................................................................................................................................................ 357
10.2.4.1 Internal programmers view...................................................................................................... 357
10.2.4.2 Security of master interfaces....................................................................................................357
10.2.5 Error responses.............................................................................................................................................358
10.2.5.1 Imprecise errors........................................................................................................................358
10.2.6 Barriers.........................................................................................................................................................359
10.2.7 DVM messages............................................................................................................................................ 359
10.2.8 Quality of Service........................................................................................................................................ 360
10.2.8.1 QoS value................................................................................................................................. 360
10.2.8.2 Regulation based on outstanding transactions......................................................................... 362
10.2.8.3 QoS programmable registers....................................................................................................364
10.3 register descriptions...................................................................................................................................................... 365
10.3.1 CCI400 Registers Memory map.................................................................................................................. 365
10.3.2 Control Override Register (Control_Override_Register)............................................................................ 367
10.3.2.1 Offset........................................................................................................................................367
10.3.2.2 Function................................................................................................................................... 367
10.3.2.3 Diagram....................................................................................................................................368
10.3.2.4 Fields........................................................................................................................................ 368
10.3.3 Speculation Control Register (Speculation_Control_Register)................................................................... 369
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 9
Section number Title Page
10.3.3.1 Offset........................................................................................................................................369
10.3.3.2 Function................................................................................................................................... 369
10.3.3.3 Diagram....................................................................................................................................369
10.3.3.4 Fields........................................................................................................................................ 370
10.3.4 Secure Access Register (Secure_Access_Register)..................................................................................... 371
10.3.4.1 Offset........................................................................................................................................371
10.3.4.2 Function................................................................................................................................... 371
10.3.4.3 Diagram....................................................................................................................................371
10.3.4.4 Fields........................................................................................................................................ 372
10.3.5 Status Register (Status_Register).................................................................................................................372
10.3.5.1 Offset........................................................................................................................................372
10.3.5.2 Function................................................................................................................................... 372
10.3.5.3 Diagram....................................................................................................................................373
10.3.5.4 Fields........................................................................................................................................ 373
10.3.6 Imprecise Error Register (Imprecise_Error_Register)................................................................................. 374
10.3.6.1 Offset........................................................................................................................................374
10.3.6.2 Function................................................................................................................................... 374
10.3.6.3 Diagram....................................................................................................................................374
10.3.6.4 Fields........................................................................................................................................ 375
10.3.7 Snoop Control Registers (Snoop_Control_Register_S0 - Snoop_Control_Register_S4)........................... 375
10.3.7.1 Offset........................................................................................................................................375
10.3.7.2 Function................................................................................................................................... 375
10.3.7.3 Diagram....................................................................................................................................376
10.3.7.4 Fields........................................................................................................................................ 376
10.3.8 Shareable Override Registers (Shareable_Override_Register_S0 - Shareable_Override_Register_S4).....377
10.3.8.1 Offset........................................................................................................................................377
10.3.8.2 Function................................................................................................................................... 377
10.3.8.3 Diagram....................................................................................................................................378
10.3.8.4 Fields........................................................................................................................................ 378
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
10 NXP Semiconductors
Section number Title Page
10.3.9 Read Channel QoS Value Override Register (Read_Qos_Override_Register_S0 - Read_Qos_Override_
Register_S4).................................................................................................................................................379
10.3.9.1 Offset........................................................................................................................................379
10.3.9.2 Function................................................................................................................................... 379
10.3.9.3 Diagram....................................................................................................................................379
10.3.9.4 Fields........................................................................................................................................ 380
10.3.10 Write Qos Override Register (Write_Qos_Override_Register_S0 - Write_Qos_Override_Register_S4).. 380
10.3.10.1 Offset........................................................................................................................................380
10.3.10.2 Function................................................................................................................................... 381
10.3.10.3 Diagram....................................................................................................................................381
10.3.10.4 Fields........................................................................................................................................ 381
10.3.11 Qos Control Register (Qos_Control_Register_S0 - Qos_Control_Register_S4)........................................ 382
10.3.11.1 Offset........................................................................................................................................382
10.3.11.2 Function................................................................................................................................... 382
10.3.11.3 Diagram....................................................................................................................................382
10.3.11.4 Fields........................................................................................................................................ 383
10.3.12 Max OT Registers (Max_OT_Register_S0 - Max_OT_Register_S4).........................................................384
10.3.12.1 Offset........................................................................................................................................384
10.3.12.2 Function................................................................................................................................... 384
10.3.12.3 Diagram....................................................................................................................................385
10.3.12.4 Fields........................................................................................................................................ 385
10.3.13 Regulator Target Registers (Target_Latency_Register_S0 - Target_Latency_Register_S4)......................386
10.3.13.1 Offset........................................................................................................................................386
10.3.13.2 Function................................................................................................................................... 386
10.3.13.3 Diagram....................................................................................................................................386
10.3.13.4 Fields........................................................................................................................................ 387
10.3.14 QoS Range Register (Qos_Range_Register_S0 - Qos_Range_Register_S4)..............................................387
10.3.14.1 Offset........................................................................................................................................387
10.3.14.2 Function................................................................................................................................... 387
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 11
Section number Title Page
10.3.14.3 Diagram....................................................................................................................................388
10.3.14.4 Fields........................................................................................................................................ 388
10.3.15 QoS Regulator Scale Factor Registers (Latency_Regulation_Register_S0 - Latency_Regulation_Regis
ter_S4).......................................................................................................................................................... 389
10.3.15.1 Offset........................................................................................................................................389
10.3.15.2 Function................................................................................................................................... 389
10.3.15.3 Diagram....................................................................................................................................390
10.3.15.4 Fields........................................................................................................................................ 390
Chapter 11
Arm CoreLink™ TrustZone Address Space Controller TZC-380
11.1 Introduction...................................................................................................................................................................391
11.1.1 Overview...................................................................................................................................................... 391
11.1.1.1 Features.................................................................................................................................... 392
11.2 Miscellaneous signal descriptions.................................................................................................................................392
11.3 Functional description...................................................................................................................................................393
11.3.1 Functional operation.................................................................................................................................... 393
11.3.1.1 Regions.....................................................................................................................................394
11.3.1.2 Priority..................................................................................................................................... 394
11.3.1.3 Subregions................................................................................................................................395
11.3.1.4 Subregion disable..................................................................................................................... 395
11.3.1.5 Region security permissions.................................................................................................... 397
11.3.1.6 Denied AXI transactions.......................................................................................................... 401
11.3.1.7 Speculative accesses................................................................................................................ 402
11.3.1.8 Preventing writes to registers and using secure_boot_lock..................................................... 402
11.3.1.9 Using locked transaction sequences.........................................................................................403
11.3.1.10 Using exclusive accesses......................................................................................................... 404
11.3.2 Constraints of use.........................................................................................................................................404
11.4 register descriptions...................................................................................................................................................... 405
11.4.1 TZASC Memory map.................................................................................................................................. 406
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
12 NXP Semiconductors
Section number Title Page
11.4.2 Configuration Register (configuration)........................................................................................................407
11.4.2.1 Offset........................................................................................................................................408
11.4.2.2 Function................................................................................................................................... 408
11.4.2.3 Diagram....................................................................................................................................408
11.4.2.4 Fields........................................................................................................................................ 408
11.4.3 Action register (action)................................................................................................................................ 409
11.4.3.1 Offset........................................................................................................................................409
11.4.3.2 Function................................................................................................................................... 409
11.4.3.3 Diagram....................................................................................................................................409
11.4.3.4 Fields........................................................................................................................................ 410
11.4.4 Lockdown Range Register (lockdown_range).............................................................................................410
11.4.4.1 Offset........................................................................................................................................410
11.4.4.2 Function................................................................................................................................... 410
11.4.4.3 Diagram....................................................................................................................................411
11.4.4.4 Fields........................................................................................................................................ 411
11.4.5 Lockdown Select Register (lockdown_select)............................................................................................. 412
11.4.5.1 Offset........................................................................................................................................412
11.4.5.2 Function................................................................................................................................... 412
11.4.5.3 Diagram....................................................................................................................................412
11.4.5.4 Fields........................................................................................................................................ 413
11.4.6 Interrupt Status Register (int_status)............................................................................................................414
11.4.6.1 Offset........................................................................................................................................414
11.4.6.2 Function................................................................................................................................... 414
11.4.6.3 Diagram....................................................................................................................................414
11.4.6.4 Fields........................................................................................................................................ 414
11.4.7 Interrupt Clear Register (int_clear).............................................................................................................. 415
11.4.7.1 Offset........................................................................................................................................415
11.4.7.2 Function................................................................................................................................... 415
11.4.7.3 Diagram....................................................................................................................................415
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 13
Section number Title Page
11.4.7.4 Fields........................................................................................................................................ 415
11.4.8 Fail Address Low Register (fail_address_low)............................................................................................416
11.4.8.1 Offset........................................................................................................................................416
11.4.8.2 Function................................................................................................................................... 416
11.4.8.3 Diagram....................................................................................................................................416
11.4.8.4 Fields........................................................................................................................................ 417
11.4.9 Fail Address High Register (fail_address_high).......................................................................................... 417
11.4.9.1 Offset........................................................................................................................................417
11.4.9.2 Function................................................................................................................................... 417
11.4.9.3 Diagram....................................................................................................................................417
11.4.9.4 Fields........................................................................................................................................ 417
11.4.10 Fail Control Register (fail_control)..............................................................................................................418
11.4.10.1 Offset........................................................................................................................................418
11.4.10.2 Function................................................................................................................................... 418
11.4.10.3 Diagram....................................................................................................................................418
11.4.10.4 Fields........................................................................................................................................ 419
11.4.11 Fail ID Register (fail_id)..............................................................................................................................419
11.4.11.1 Offset........................................................................................................................................419
11.4.11.2 Function................................................................................................................................... 419
11.4.11.3 Diagram....................................................................................................................................420
11.4.11.4 Fields........................................................................................................................................ 420
11.4.12 Speculation Control Register (speculation_control).................................................................................... 420
11.4.12.1 Offset........................................................................................................................................420
11.4.12.2 Function................................................................................................................................... 420
11.4.12.3 Diagram....................................................................................................................................421
11.4.12.4 Fields........................................................................................................................................ 421
11.4.13 Security Inversion Register (security_inversion_en)................................................................................... 422
11.4.13.1 Offset........................................................................................................................................422
11.4.13.2 Function................................................................................................................................... 422
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
14 NXP Semiconductors
Section number Title Page
11.4.13.3 Diagram....................................................................................................................................422
11.4.13.4 Fields........................................................................................................................................ 422
11.4.14 Region Setup Low 0 Register (region_setup_low_0).................................................................................. 423
11.4.14.1 Offset........................................................................................................................................423
11.4.14.2 Diagram....................................................................................................................................423
11.4.14.3 Fields........................................................................................................................................ 424
11.4.15 Region Setup High 0 Register (region_setup_high_0)................................................................................ 424
11.4.15.1 Offset........................................................................................................................................424
11.4.15.2 Function................................................................................................................................... 424
11.4.15.3 Diagram....................................................................................................................................424
11.4.15.4 Fields........................................................................................................................................ 425
11.4.16 Region Attributes 0 Register (region_attributes_0)..................................................................................... 425
11.4.16.1 Offset........................................................................................................................................425
11.4.16.2 Function................................................................................................................................... 425
11.4.16.3 Diagram....................................................................................................................................425
11.4.16.4 Fields........................................................................................................................................ 426
11.4.17 Region Setup Low 1 Register (region_setup_low_1).................................................................................. 426
11.4.17.1 Offset........................................................................................................................................426
11.4.17.2 Diagram....................................................................................................................................426
11.4.17.3 Fields........................................................................................................................................ 427
11.4.18 Region Setup High 1 Register (region_setup_high_1)................................................................................ 427
11.4.18.1 Offset........................................................................................................................................428
11.4.18.2 Function................................................................................................................................... 428
11.4.18.3 Diagram....................................................................................................................................428
11.4.18.4 Fields........................................................................................................................................ 428
11.4.19 Region Attributes 1 Register (region_attributes_1)..................................................................................... 428
11.4.19.1 Offset........................................................................................................................................429
11.4.19.2 Function................................................................................................................................... 429
11.4.19.3 Diagram....................................................................................................................................430
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 15
Section number Title Page
11.4.19.4 Fields........................................................................................................................................ 431
11.4.20 Region Setup Low 2 Register (region_setup_low_2).................................................................................. 432
11.4.20.1 Offset........................................................................................................................................432
11.4.20.2 Diagram....................................................................................................................................432
11.4.20.3 Fields........................................................................................................................................ 432
11.4.21 Region Setup High 2 Register (region_setup_high_2)................................................................................ 433
11.4.21.1 Offset........................................................................................................................................433
11.4.21.2 Function................................................................................................................................... 433
11.4.21.3 Diagram....................................................................................................................................433
11.4.21.4 Fields........................................................................................................................................ 434
11.4.22 Region Attributes 2 Register (region_attributes_2)..................................................................................... 434
11.4.22.1 Offset........................................................................................................................................434
11.4.22.2 Function................................................................................................................................... 434
11.4.22.3 Diagram....................................................................................................................................436
11.4.22.4 Fields........................................................................................................................................ 436
11.4.23 Region Setup Low 3 Register (region_setup_low_3).................................................................................. 437
11.4.23.1 Offset........................................................................................................................................437
11.4.23.2 Diagram....................................................................................................................................437
11.4.23.3 Fields........................................................................................................................................ 438
11.4.24 Region Setup High 3 Register (region_setup_high_3)................................................................................ 438
11.4.24.1 Offset........................................................................................................................................439
11.4.24.2 Function................................................................................................................................... 439
11.4.24.3 Diagram....................................................................................................................................439
11.4.24.4 Fields........................................................................................................................................ 439
11.4.25 Region Attributes 3 Register (region_attributes_3)..................................................................................... 439
11.4.25.1 Offset........................................................................................................................................440
11.4.25.2 Function................................................................................................................................... 440
11.4.25.3 Diagram....................................................................................................................................441
11.4.25.4 Fields........................................................................................................................................ 442
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
16 NXP Semiconductors
Section number Title Page
11.4.26 Region Setup Low 4 Register (region_setup_low_4).................................................................................. 443
11.4.26.1 Offset........................................................................................................................................443
11.4.26.2 Diagram....................................................................................................................................443
11.4.26.3 Fields........................................................................................................................................ 443
11.4.27 Region Setup High 4 Register (region_setup_high_4)................................................................................ 444
11.4.27.1 Offset........................................................................................................................................444
11.4.27.2 Function................................................................................................................................... 444
11.4.27.3 Diagram....................................................................................................................................444
11.4.27.4 Fields........................................................................................................................................ 445
11.4.28 Region Attributes 4 Register (region_attributes_4)..................................................................................... 445
11.4.28.1 Offset........................................................................................................................................445
11.4.28.2 Function................................................................................................................................... 445
11.4.28.3 Diagram....................................................................................................................................447
11.4.28.4 Fields........................................................................................................................................ 447
11.4.29 Region Setup Low 5 Register (region_setup_low_5).................................................................................. 448
11.4.29.1 Offset........................................................................................................................................448
11.4.29.2 Diagram....................................................................................................................................448
11.4.29.3 Fields........................................................................................................................................ 449
11.4.30 Region Setup High 5 Register (region_setup_high_5)................................................................................ 449
11.4.30.1 Offset........................................................................................................................................450
11.4.30.2 Function................................................................................................................................... 450
11.4.30.3 Diagram....................................................................................................................................450
11.4.30.4 Fields........................................................................................................................................ 450
11.4.31 Region Attributes 5 Register (region_attributes_5)..................................................................................... 450
11.4.31.1 Offset........................................................................................................................................451
11.4.31.2 Function................................................................................................................................... 451
11.4.31.3 Diagram....................................................................................................................................452
11.4.31.4 Fields........................................................................................................................................ 453
11.4.32 Region Setup Low 6 Register (region_setup_low_6).................................................................................. 454
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 17
Section number Title Page
11.4.32.1 Offset........................................................................................................................................454
11.4.32.2 Diagram....................................................................................................................................454
11.4.32.3 Fields........................................................................................................................................ 454
11.4.33 Region Setup High 6 Register (region_setup_high_6)................................................................................ 455
11.4.33.1 Offset........................................................................................................................................455
11.4.33.2 Function................................................................................................................................... 455
11.4.33.3 Diagram....................................................................................................................................455
11.4.33.4 Fields........................................................................................................................................ 456
11.4.34 Region Attributes 6 Register (region_attributes_6)..................................................................................... 456
11.4.34.1 Offset........................................................................................................................................456
11.4.34.2 Function................................................................................................................................... 456
11.4.34.3 Diagram....................................................................................................................................458
11.4.34.4 Fields........................................................................................................................................ 458
11.4.35 Region Setup Low 7 Register (region_setup_low_7).................................................................................. 459
11.4.35.1 Offset........................................................................................................................................459
11.4.35.2 Diagram....................................................................................................................................459
11.4.35.3 Fields........................................................................................................................................ 460
11.4.36 Region Setup High 7 Register (region_setup_high_7)................................................................................ 460
11.4.36.1 Offset........................................................................................................................................461
11.4.36.2 Function................................................................................................................................... 461
11.4.36.3 Diagram....................................................................................................................................461
11.4.36.4 Fields........................................................................................................................................ 461
11.4.37 Region Attributes 7 Register (region_attributes_7)..................................................................................... 461
11.4.37.1 Offset........................................................................................................................................462
11.4.37.2 Function................................................................................................................................... 462
11.4.37.3 Diagram....................................................................................................................................463
11.4.37.4 Fields........................................................................................................................................ 464
11.4.38 Region Setup Low 8 Register (region_setup_low_8).................................................................................. 465
11.4.38.1 Offset........................................................................................................................................465
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
18 NXP Semiconductors
Section number Title Page
11.4.38.2 Diagram....................................................................................................................................465
11.4.38.3 Fields........................................................................................................................................ 465
11.4.39 Region Setup High 8 Register (region_setup_high_8)................................................................................ 466
11.4.39.1 Offset........................................................................................................................................466
11.4.39.2 Function................................................................................................................................... 466
11.4.39.3 Diagram....................................................................................................................................466
11.4.39.4 Fields........................................................................................................................................ 467
11.4.40 Region Attributes 8 Register (region_attributes_8)..................................................................................... 467
11.4.40.1 Offset........................................................................................................................................467
11.4.40.2 Function................................................................................................................................... 467
11.4.40.3 Diagram....................................................................................................................................469
11.4.40.4 Fields........................................................................................................................................ 469
11.4.41 Region Setup Low 9 Register (region_setup_low_9).................................................................................. 470
11.4.41.1 Offset........................................................................................................................................470
11.4.41.2 Diagram....................................................................................................................................470
11.4.41.3 Fields........................................................................................................................................ 471
11.4.42 Region Setup High 9 Register (region_setup_high_9)................................................................................ 471
11.4.42.1 Offset........................................................................................................................................472
11.4.42.2 Function................................................................................................................................... 472
11.4.42.3 Diagram....................................................................................................................................472
11.4.42.4 Fields........................................................................................................................................ 472
11.4.43 Region Attributes 9 Register (region_attributes_9)..................................................................................... 472
11.4.43.1 Offset........................................................................................................................................473
11.4.43.2 Function................................................................................................................................... 473
11.4.43.3 Diagram....................................................................................................................................474
11.4.43.4 Fields........................................................................................................................................ 475
11.4.44 Region Setup Low 10 Register (region_setup_low_10).............................................................................. 476
11.4.44.1 Offset........................................................................................................................................476
11.4.44.2 Diagram....................................................................................................................................476
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 19
Section number Title Page
11.4.44.3 Fields........................................................................................................................................ 476
11.4.45 Region Setup High 10 Register (region_setup_high_10)............................................................................ 477
11.4.45.1 Offset........................................................................................................................................477
11.4.45.2 Function................................................................................................................................... 477
11.4.45.3 Diagram....................................................................................................................................477
11.4.45.4 Fields........................................................................................................................................ 478
11.4.46 Region Attributes 10 Register (region_attributes_10)................................................................................. 478
11.4.46.1 Offset........................................................................................................................................478
11.4.46.2 Function................................................................................................................................... 478
11.4.46.3 Diagram....................................................................................................................................480
11.4.46.4 Fields........................................................................................................................................ 480
11.4.47 Region Setup Low 11 Register (region_setup_low_11).............................................................................. 481
11.4.47.1 Offset........................................................................................................................................481
11.4.47.2 Diagram....................................................................................................................................481
11.4.47.3 Fields........................................................................................................................................ 482
11.4.48 Region Setup High 11 Register (region_setup_high_11)............................................................................ 482
11.4.48.1 Offset........................................................................................................................................483
11.4.48.2 Function................................................................................................................................... 483
11.4.48.3 Diagram....................................................................................................................................483
11.4.48.4 Fields........................................................................................................................................ 483
11.4.49 Region Attributes 11 Register (region_attributes_11)................................................................................. 483
11.4.49.1 Offset........................................................................................................................................484
11.4.49.2 Function................................................................................................................................... 484
11.4.49.3 Diagram....................................................................................................................................485
11.4.49.4 Fields........................................................................................................................................ 486
11.4.50 Region Setup Low 12 Register (region_setup_low_12).............................................................................. 487
11.4.50.1 Offset........................................................................................................................................487
11.4.50.2 Diagram....................................................................................................................................487
11.4.50.3 Fields........................................................................................................................................ 487
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
20 NXP Semiconductors
Section number Title Page
11.4.51 Region Setup High 12 Register (region_setup_high_12)............................................................................ 488
11.4.51.1 Offset........................................................................................................................................488
11.4.51.2 Function................................................................................................................................... 488
11.4.51.3 Diagram....................................................................................................................................488
11.4.51.4 Fields........................................................................................................................................ 489
11.4.52 Region Attributes 12 Register (region_attributes_12)................................................................................. 489
11.4.52.1 Offset........................................................................................................................................489
11.4.52.2 Function................................................................................................................................... 489
11.4.52.3 Diagram....................................................................................................................................491
11.4.52.4 Fields........................................................................................................................................ 491
11.4.53 Region Setup Low 13 Register (region_setup_low_13).............................................................................. 492
11.4.53.1 Offset........................................................................................................................................492
11.4.53.2 Diagram....................................................................................................................................492
11.4.53.3 Fields........................................................................................................................................ 493
11.4.54 Region Setup High 13 Register (region_setup_high_13)............................................................................ 493
11.4.54.1 Offset........................................................................................................................................494
11.4.54.2 Function................................................................................................................................... 494
11.4.54.3 Diagram....................................................................................................................................494
11.4.54.4 Fields........................................................................................................................................ 494
11.4.55 Region Attributes 13 Register (region_attributes_13)................................................................................. 494
11.4.55.1 Offset........................................................................................................................................495
11.4.55.2 Function................................................................................................................................... 495
11.4.55.3 Diagram....................................................................................................................................496
11.4.55.4 Fields........................................................................................................................................ 497
11.4.56 Region Setup Low 14 Register (region_setup_low_14).............................................................................. 498
11.4.56.1 Offset........................................................................................................................................498
11.4.56.2 Diagram....................................................................................................................................498
11.4.56.3 Fields........................................................................................................................................ 498
11.4.57 Region Setup High 14 Register (region_setup_high_14)............................................................................ 499
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 21
Section number Title Page
11.4.57.1 Offset........................................................................................................................................499
11.4.57.2 Function................................................................................................................................... 499
11.4.57.3 Diagram....................................................................................................................................499
11.4.57.4 Fields........................................................................................................................................ 500
11.4.58 Region Attributes 14 Register (region_attributes_14)................................................................................. 500
11.4.58.1 Offset........................................................................................................................................500
11.4.58.2 Function................................................................................................................................... 500
11.4.58.3 Diagram....................................................................................................................................502
11.4.58.4 Fields........................................................................................................................................ 502
11.4.59 Region Setup Low 15 Register (region_setup_low_15).............................................................................. 503
11.4.59.1 Offset........................................................................................................................................503
11.4.59.2 Diagram....................................................................................................................................503
11.4.59.3 Fields........................................................................................................................................ 504
11.4.60 Region Setup High 15 Register (region_setup_high_15)............................................................................ 504
11.4.60.1 Offset........................................................................................................................................505
11.4.60.2 Function................................................................................................................................... 505
11.4.60.3 Diagram....................................................................................................................................505
11.4.60.4 Fields........................................................................................................................................ 505
11.4.61 Region Attributes 15 Register (region_attributes_15)................................................................................. 505
11.4.61.1 Offset........................................................................................................................................506
11.4.61.2 Function................................................................................................................................... 506
11.4.61.3 Diagram....................................................................................................................................507
11.4.61.4 Fields........................................................................................................................................ 508
11.4.62 Integration Test Control Register (itcrg)......................................................................................................509
11.4.62.1 Offset........................................................................................................................................509
11.4.62.2 Function................................................................................................................................... 509
11.4.62.3 Diagram....................................................................................................................................509
11.4.62.4 Fields........................................................................................................................................ 510
11.4.63 Integration Test Input Register (itip)........................................................................................................... 510
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
22 NXP Semiconductors
Section number Title Page
11.4.63.1 Offset........................................................................................................................................510
11.4.63.2 Function................................................................................................................................... 510
11.4.63.3 Diagram....................................................................................................................................510
11.4.63.4 Fields........................................................................................................................................ 511
11.4.64 Integration Test Output Register (itop)........................................................................................................ 511
11.4.64.1 Offset........................................................................................................................................511
11.4.64.2 Function................................................................................................................................... 511
11.4.64.3 Diagram....................................................................................................................................512
11.4.64.4 Fields........................................................................................................................................ 512
Chapter 12
Supplemental Configuration Unit
12.1 Introduction ..................................................................................................................................................................513
12.2 Overview ......................................................................................................................................................................513
12.3 SCFG Memory Map/Register Definition......................................................................................................................513
12.3.1 USB1 Parameter 1 Control Register (SCFG_USB1PRM1CR)................................................................... 517
12.3.2 USB1 Parameter 2 Control Register (SCFG_USB1PRM2CR)................................................................... 519
12.3.3 USB1 Parameter 3 Control Register (SCFG_USB1PRM3CR)................................................................... 520
12.3.4 USB2 Parameter 1 Control Register (SCFG_USB2PRM1CR)................................................................... 521
12.3.5 USB2 Parameter 2 Control Register (SCFG_USB2PRM2CR)................................................................... 523
12.3.6 USB2 Parameter3 Control Register (SCFG_USB2PRM3CR).................................................................... 524
12.3.7 USB3 Parameter 1 Control Register (SCFG_USB3PRM1CR)................................................................... 525
12.3.8 USB3 Parameter 2 Control Register (SCFG_USB3PRM2CR)................................................................... 526
12.3.9 USB3 Parameter 3 Control Register (SCFG_USB3PRM3CR)................................................................... 528
12.3.10 USB2 ICID Register (SCFG_USB2_ICID).................................................................................................529
12.3.11 USB3 ICID Register (SCFG_USB3_ICID).................................................................................................530
12.3.12 qDMA ICID Register (SCFG_DMA_ICID)................................................................................................531
12.3.13 SATA ICID Register (SCFG_SATA_ICID)............................................................................................... 532
12.3.14 USB1 ICID Register (SCFG_USB1_ICID).................................................................................................533
12.3.15 QE ICID Register (SCFG_QE_ICID)..........................................................................................................534
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 23
Section number Title Page
12.3.16 eSDHC ICID Register (SCFG_SDHC_ICID)............................................................................................. 535
12.3.17 eDMA ICID Register (SCFG_eDMA_ICID).............................................................................................. 536
12.3.18 ETR ICID Register (SCFG_ETR_ICID)..................................................................................................... 537
12.3.19 Core 0 soft reset Register (SCFG_CORE0_SFT_RST).............................................................................. 538
12.3.20 Core 1 soft reset Register (SCFG_CORE1_SFT_RST).............................................................................. 539
12.3.21 Core 2 soft reset Register (SCFG_CORE2_SFT_RST).............................................................................. 540
12.3.22 Core 3soft reset Register (SCFG_CORE3_SFT_RST)............................................................................... 541
12.3.23 PEX PME control register (SCFG_PEXPMECR).......................................................................................542
12.3.24 FTM chain configuration (SCFG_FTM_CHAIN_CONFIG)......................................................................543
12.3.25 ALTCBAR Register (SCFG_ALTCBAR).................................................................................................. 544
12.3.26 QSPI CONFIG Register (SCFG_QSPI_CFG).............................................................................................544
12.3.27 QOS1 Register (SCFG_QOS1)....................................................................................................................545
12.3.28 QOS2 Register (SCFG_QOS2)....................................................................................................................546
12.3.29 GIC-400 Address 64K Page Alignment Register (SCFG_GIC400_ADDR_ALIGN_64K)....................... 547
12.3.30 Debug ICID Register (SCFG_Debug_ICID)............................................................................................... 548
12.3.31 Snoop Configuration Register (SCFG_SNPCNFGCR)...............................................................................549
12.3.32 Interrupt Polarity Register (SCFG_INTPCR)..............................................................................................551
12.3.33 CORE Soft Reset Enable Register (SCFG_CORESRENCR)..................................................................... 553
12.3.34 Core 0 Reset Vector Base Address0 (SCFG_RVBAR0_0).........................................................................553
12.3.35 Core 0 Reset Vector Base Address1 (SCFG_RVBAR0_1).........................................................................554
12.3.36 Core 1 Reset Vector Base Address0 (SCFG_RVBAR1_0).........................................................................555
12.3.37 Core 1 Reset Vector Base Address1 (SCFG_RVBAR1_1).........................................................................555
12.3.38 Core 2 Reset Vector Base Address0 (SCFG_RVBAR2_0).........................................................................556
12.3.39 Core 2 Reset Vector Base Address1 (SCFG_RVBAR2_1).........................................................................556
12.3.40 Core 3 Reset Vector Base Address0 (SCFG_RVBAR3_0).........................................................................557
12.3.41 Core 3 Reset Vector Base Address1 (SCFG_RVBAR3_1).........................................................................557
12.3.42 Core Low Power Mode Control Status Register (SCFG_LPMCSR).......................................................... 558
12.3.43 ECGTX Clock Mux Control Register (SCFG_ECGTXCMCR)................................................................. 560
12.3.44 SDHC IO VSEL Control Register (SCFG_SDHCIOVSELCR)................................................................. 561
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
24 NXP Semiconductors
Section number Title Page
12.3.45 Extended RCW PinMux Control Register (SCFG_RCWPMUXCR0)....................................................... 562
12.3.46 USB DRVVBUS Control Register (SCFG_USBDRVVBUS_SELCR)..................................................... 564
12.3.47 USB PWRFAULTControl Register (SCFG_USBPWRFAULT_SELCR)................................................. 564
12.3.48 USB PHY1 Reference Clock Select Register (SCFG_USB_REFCLK_SELCR1).....................................565
12.3.49 USB PHY2 Reference Clock Select Register (SCFG_USB_REFCLK_SELCR2).....................................566
12.3.50 USB PHY3 Reference Clock Select Register (SCFG_USB_REFCLK_SELCR3).....................................567
12.3.51 Retention Request Control Register (SCFG_RETREQCR)........................................................................ 568
12.3.52 CORE PM Control Register (SCFG_COREPMCR)................................................................................... 569
12.3.53 SCRATCHRWn - Scratch Read Write Registers (SCFG_SCRATCHRWn)..............................................569
12.3.54 Core Boot Control Register (SCFG_COREBCR)....................................................................................... 570
12.3.55 Shared Message Signaled Interrupt Index Register (SCFG_G0MSIIR)..................................................... 571
12.3.56 Shared Message Signaled Interrupt Register (SCFG_G0MSIR1)............................................................... 573
12.3.57 Shared Message Signaled Interrupt Register (SCFG_G0MSIR2)............................................................... 573
12.3.58 Shared Message Signaled Interrupt Register (SCFG_G0MSIR3)............................................................... 574
12.3.59 Shared Message Signaled Interrupt Register (SCFG_G0MSIR4)............................................................... 574
12.3.60 Shared Message Signaled Interrupt Index Register (SCFG_G1MSIIR)..................................................... 575
12.3.61 Shared Message Signaled Interrupt Register (SCFG_G1MSIR1)............................................................... 577
12.3.62 Shared Message Signaled Interrupt Register (SCFG_G1MSIR2)............................................................... 577
12.3.63 Shared Message Signaled Interrupt Register (SCFG_G1MSIR3)............................................................... 578
12.3.64 Shared Message Signaled Interrupt Register (SCFG_G1MSIR4)............................................................... 578
12.3.65 Shared Message Signaled Interrupt Index Register (SCFG_G2MSIIR)..................................................... 579
12.3.66 Shared Message Signaled Interrupt Register (SCFG_G2MSIR1)............................................................... 581
12.3.67 Shared Message Signaled Interrupt Register (SCFG_G2MSIR2)............................................................... 581
12.3.68 Shared Message Signaled Interrupt Register (SCFG_G2MSIR3)............................................................... 582
12.3.69 Shared Message Signaled Interrupt Register (SCFG_G2MSIR4)............................................................... 582
Chapter 13
Device Configuration and Pin Control
13.1 Device Configuration and Pin Control Introduction.....................................................................................................585
13.2 Features......................................................................................................................................................................... 585
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 25
Section number Title Page
13.3 Device Configuration/Pin Control Memory Map......................................................................................................... 586
13.3.1 POR Status Register 1 (DCFG_CCSR_PORSR1).......................................................................................592
13.3.2 POR Status Register 2 (DCFG_CCSR_PORSR2).......................................................................................593
13.3.3 General-Purpose POR Configuration Register (DCFG_CCSR_GPPORCR1)........................................... 595
13.3.4 Device Disable Register 1 (DCFG_CCSR_DEVDISR1)............................................................................ 595
13.3.5 Device Disable Register 2 (DCFG_CCSR_DEVDISR2)............................................................................ 597
13.3.6 Device Disable Register 3 (DCFG_CCSR_DEVDISR3)............................................................................ 599
13.3.7 Device Disable Register 4 (DCFG_CCSR_DEVDISR4)............................................................................ 600
13.3.8 Device Disable Register 5 (DCFG_CCSR_DEVDISR5)............................................................................ 601
13.3.9 Core Disable Register (DCFG_CCSR_COREDISR).................................................................................. 604
13.3.10 System Version Register (DCFG_CCSR_SVR)..........................................................................................606
13.3.11 Reset Control Register (DCFG_CCSR_RSTCR)........................................................................................ 607
13.3.12 Reset Request Preboot Loader Status Register (DCFG_CCSR_RSTRQPBLSR)...................................... 608
13.3.13 Reset Request Mask Register (DCFG_CCSR_RSTRQMR1)..................................................................... 609
13.3.14 Reset Request Status Register (DCFG_CCSR_RSTRQSR1)..................................................................... 611
13.3.15 Boot Release Register (DCFG_CCSR_BRR)..............................................................................................615
13.3.16 Reset Control Word Status Register n (DCFG_CCSR_RCWSRn).............................................................616
13.3.17 Scratch Read / Write Register n (DCFG_CCSR_SCRATCHRWn)........................................................... 617
13.3.18 Scratch Read Register n (DCFG_CCSR_SCRATCHW1Rn)......................................................................618
13.3.19 Core Reset Status Register n (DCFG_CCSR_CRSTSRn).......................................................................... 618
13.3.20 DMA Control Register (DCFG_CCSR_DMACR1)....................................................................................621
13.3.21 Topology Initiator Type n Register (DCFG_CCSR_TP_ITYPn)................................................................622
13.3.22 Core Cluster n Topology Register (DCFG_CCSR_TP_CLUSTERn)........................................................ 623
13.3.23 DDR Clock Disable Register (DCFG_CCSR_DDRCLKDR).....................................................................624
13.3.24 DDR Clock Disable Register (DCFG_CCSR_DDRCLKDR).....................................................................625
13.3.25 IFC Clock Disable Register (DCFG_CCSR_IFCCLKDR)......................................................................... 626
13.3.26 eSDHC Polarity Configuration Register (DCFG_CCSR_SDHCPCR)....................................................... 627
Chapter 14
Run Control and Power Management (RCPM)
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
26 NXP Semiconductors
Section number Title Page
14.1 Introduction...................................................................................................................................................................629
14.1.1 Overview...................................................................................................................................................... 629
14.1.2 The RCPM module as implemented on the chip......................................................................................... 629
14.1.3 Power Management Features....................................................................................................................... 630
14.1.4 Power Management States........................................................................................................................... 631
14.1.4.1 Power Management State Summary........................................................................................ 631
14.1.5 Modes Entry and Exit for Power Management............................................................................................632
14.1.5.1 SWLPM20 Entry Sequence – System Software...................................................................... 635
14.1.5.2 SWLPM20 Device Specific Entry and Exit Sequence............................................................ 636
14.1.6 Power Management States........................................................................................................................... 639
14.1.6.1 STANDBYWFI (PW15) State.................................................................................................640
14.1.6.2 PH20 State................................................................................................................................640
14.1.6.3 LPM20 State............................................................................................................................ 640
14.1.6.4 SWLPM20 State...................................................................................................................... 641
14.1.7 Reset modes................................................................................................................................................. 641
14.1.7.1 Power-On Reset and Hard Reset States................................................................................... 642
14.2 External Signal Description.......................................................................................................................................... 642
14.3 RCPM Memory Map/Register Definition.................................................................................................................... 642
14.3.1 Thread Wait status Register (RCPM_TWAITSR).......................................................................................643
14.3.2 Physical Core PH20 Status Register (RCPM_PCPH20SR)........................................................................ 644
14.3.3 Physical Core PH20 Set Control Register (RCPM_PCPH20SETR)........................................................... 644
14.3.4 Physical Core PH20 Clear Control Register (RCPM_PCPH20CLRR).......................................................645
14.3.5 Physical Core PH20 Previous Status Register (RCPM_PCPH20PSR)....................................................... 647
14.3.6 Power Management Control and Status Register (RCPM_POWMGTCSR).............................................. 647
14.3.7 IP Powerdown Exception Control Register (RCPM_IPPDEXPCR)........................................................... 649
14.3.8 nIRQOUT interrupt mask register (RCPM_nIRQOUTR)...........................................................................651
14.3.9 nFIQOUT Interrupt Register (RCPM_nFIQOUTR)....................................................................................651
14.4 RCPM functional description....................................................................................................................................... 652
Chapter 15
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 27
Section number Title Page
QUICC Engine Block
15.1 Introduction...................................................................................................................................................................653
15.2 QUICC Engine block....................................................................................................................................................653
15.3 QUICC Engine implementation details........................................................................................................................ 654
15.3.1 System interface........................................................................................................................................... 656
15.3.1.1 System interface-data paths..................................................................................................... 657
15.3.1.2 System interface-interrupt configuration................................................................................. 658
15.3.1.3 System interface-bus arbitration.............................................................................................. 659
15.3.2 Configuration............................................................................................................................................... 659
15.3.2.1 Configuration-parameter RAM................................................................................................659
15.3.3 Multiplexing and timers............................................................................................................................... 660
15.3.3.1 Multiplexing and timers-NMSI configuration......................................................................... 660
15.3.3.2 Multiplexing and timers-baud-rate generators (BRGs), BRG configuration registers 1-4
(BRGCn).................................................................................................................................. 662
15.3.4 Unified communications controllers (UCCs).............................................................................................. 664
15.3.4.1 Unified communications controllers (UCCs)-UCC page base address................................... 664
15.3.5 HDLC controller.......................................................................................................................................... 664
15.3.5.1 HDLC controller-introduction................................................................................................. 665
15.3.6 Transparent controller.................................................................................................................................. 665
15.3.7 UCC for fast protocols................................................................................................................................. 665
15.3.8 UCC for slow protocols............................................................................................................................... 665
15.3.9 UART mode and asynchronous HDLC....................................................................................................... 665
15.3.10 BISYNC mode............................................................................................................................................. 666
15.3.11 Serial interface with time-slot assigner........................................................................................................ 666
15.3.12 Multi-channel controller on UCC (UMCC).................................................................................................666
Chapter 16
Data Path Acceleration Architecture (DPAA) Overview and SoC DPAA Implementation
16.1 DPAA Introduction and Terms.....................................................................................................................................667
16.2 Data Formats Used in the DPAA..................................................................................................................................669
16.2.1 Frame Descriptor (FD).................................................................................................................................670
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
28 NXP Semiconductors
Section number Title Page
16.2.1.1 FD Format................................................................................................................................ 670
16.2.2 Multi-Buffer Frames.................................................................................................................................... 671
16.2.2.1 Scatter/Gather Entry Format.................................................................................................... 671
16.2.2.2 Multi-Buffer Frame Considerations.........................................................................................672
16.2.2.3 Situations Where Multi-Frame Buffering Stops ..................................................................... 673
16.2.3 Single-Buffer Frames................................................................................................................................... 674
16.2.4 Compound Frames....................................................................................................................................... 674
16.2.4.1 When to Use Compound Frames............................................................................................. 674
16.2.4.2 Compound Frame Considerations............................................................................................675
16.2.5 Simple Frames..............................................................................................................................................676
16.2.6 Frame Format Codes.................................................................................................................................... 676
16.2.7 Frame Formats Supported by Accelerators..................................................................................................677
16.2.8 Special Values and Exceptions ................................................................................................................... 678
16.2.9 Releasing Buffers to the BMan.................................................................................................................... 678
16.3 Accessing Memory Using Isolation Context Identifier(ICID)..................................................................................... 678
16.4 Packet Walk-Through Example....................................................................................................................................679
16.5 LS1043A-Specific DPAA Implementation Details...................................................................................................... 681
16.5.1 Queue Manager (QMan) Implementation....................................................................................................681
16.5.2 Buffer Manager (BMan) Implementation.................................................................................................... 682
16.5.3 Frame Manager (FMan) Implementation.....................................................................................................682
16.5.4 Security and Encryption Engine (SEC) Implementation............................................................................. 683
Chapter 17
Secure Boot and Trust Architecture
17.1 Trust architecture objectives......................................................................................................................................... 685
17.2 Characteristics and claims.............................................................................................................................................685
17.3 Non-claims....................................................................................................................................................................687
17.4 Related resources ......................................................................................................................................................... 689
Chapter 18
DDR Memory Controller
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 29
Section number Title Page
18.1 DDR Introduction......................................................................................................................................................... 691
18.2 DDR Features................................................................................................................................................................692
18.2.1 DDR Modes of Operation............................................................................................................................ 693
18.3 DDR External Signal Descriptions............................................................................................................................... 694
18.3.1 DDR Signals Overview................................................................................................................................694
18.3.2 DDR Detailed Signal Descriptions ............................................................................................................. 696
18.3.2.1 Memory Interface Signals ....................................................................................................... 697
18.3.2.2 Clock Interface Signals............................................................................................................ 701
18.4 DDR register descriptions.............................................................................................................................................701
18.4.1 DDR Memory map.......................................................................................................................................702
18.4.2 Chip select a memory bounds (CS0_BNDS - CS3_BNDS)........................................................................ 704
18.4.2.1 Offset........................................................................................................................................704
18.4.2.2 Function................................................................................................................................... 704
18.4.2.3 Diagram....................................................................................................................................704
18.4.2.4 Fields........................................................................................................................................ 705
18.4.3 Chip select a configuration (CS0_CONFIG - CS3_CONFIG).................................................................... 705
18.4.3.1 Offset........................................................................................................................................705
18.4.3.2 Function................................................................................................................................... 705
18.4.3.3 Diagram....................................................................................................................................706
18.4.3.4 Fields........................................................................................................................................ 706
18.4.4 DDR SDRAM timing configuration 3 (TIMING_CFG_3)......................................................................... 708
18.4.4.1 Offset........................................................................................................................................708
18.4.4.2 Function................................................................................................................................... 708
18.4.4.3 Diagram....................................................................................................................................708
18.4.4.4 Fields........................................................................................................................................ 709
18.4.5 DDR SDRAM timing configuration 0 (TIMING_CFG_0)......................................................................... 711
18.4.5.1 Offset........................................................................................................................................711
18.4.5.2 Function................................................................................................................................... 711
18.4.5.3 Diagram....................................................................................................................................711
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
30 NXP Semiconductors
Section number Title Page
18.4.5.4 Fields........................................................................................................................................ 712
18.4.6 DDR SDRAM timing configuration 1 (TIMING_CFG_1)......................................................................... 715
18.4.6.1 Offset........................................................................................................................................715
18.4.6.2 Function................................................................................................................................... 715
18.4.6.3 Diagram....................................................................................................................................715
18.4.6.4 Fields........................................................................................................................................ 715
18.4.7 DDR SDRAM timing configuration 2 (TIMING_CFG_2)......................................................................... 718
18.4.7.1 Offset........................................................................................................................................718
18.4.7.2 Function................................................................................................................................... 718
18.4.7.3 Diagram....................................................................................................................................719
18.4.7.4 Fields........................................................................................................................................ 719
18.4.8 DDR SDRAM control configuration (DDR_SDRAM_CFG)..................................................................... 721
18.4.8.1 Offset........................................................................................................................................721
18.4.8.2 Function................................................................................................................................... 722
18.4.8.3 Diagram....................................................................................................................................722
18.4.8.4 Fields........................................................................................................................................ 722
18.4.9 DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2).............................................................. 725
18.4.9.1 Offset........................................................................................................................................725
18.4.9.2 Function................................................................................................................................... 725
18.4.9.3 Diagram....................................................................................................................................725
18.4.9.4 Fields........................................................................................................................................ 726
18.4.10 DDR SDRAM mode configuration (DDR_SDRAM_MODE)................................................................... 728
18.4.10.1 Offset........................................................................................................................................728
18.4.10.2 Function................................................................................................................................... 728
18.4.10.3 Diagram....................................................................................................................................728
18.4.10.4 Fields........................................................................................................................................ 729
18.4.11 DDR SDRAM mode configuration 2 (DDR_SDRAM_MODE_2)............................................................ 729
18.4.11.1 Offset........................................................................................................................................729
18.4.11.2 Function................................................................................................................................... 730
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 31
Section number Title Page
18.4.11.3 Diagram....................................................................................................................................730
18.4.11.4 Fields........................................................................................................................................ 730
18.4.12 DDR SDRAM mode control (DDR_SDRAM_MD_CNTL).......................................................................731
18.4.12.1 Offset........................................................................................................................................731
18.4.12.2 Function................................................................................................................................... 731
18.4.12.3 Diagram....................................................................................................................................731
18.4.12.4 Fields........................................................................................................................................ 732
18.4.13 DDR SDRAM interval configuration (DDR_SDRAM_INTERVAL)........................................................ 734
18.4.13.1 Offset........................................................................................................................................734
18.4.13.2 Function................................................................................................................................... 734
18.4.13.3 Diagram....................................................................................................................................734
18.4.13.4 Fields........................................................................................................................................ 734
18.4.14 DDR SDRAM data initialization (DDR_DATA_INIT).............................................................................. 735
18.4.14.1 Offset........................................................................................................................................735
18.4.14.2 Function................................................................................................................................... 735
18.4.14.3 Diagram....................................................................................................................................735
18.4.14.4 Fields........................................................................................................................................ 736
18.4.15 DDR SDRAM clock control (DDR_SDRAM_CLK_CNTL)..................................................................... 736
18.4.15.1 Offset........................................................................................................................................736
18.4.15.2 Function................................................................................................................................... 736
18.4.15.3 Diagram....................................................................................................................................736
18.4.15.4 Fields........................................................................................................................................ 736
18.4.16 DDR training initialization address (DDR_INIT_ADDR).......................................................................... 737
18.4.16.1 Offset........................................................................................................................................737
18.4.16.2 Function................................................................................................................................... 737
18.4.16.3 Diagram....................................................................................................................................738
18.4.16.4 Fields........................................................................................................................................ 738
18.4.17 DDR training initialization extended address (DDR_INIT_EXT_ADDRESS).......................................... 739
18.4.17.1 Offset........................................................................................................................................739
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
32 NXP Semiconductors
Section number Title Page
18.4.17.2 Function................................................................................................................................... 739
18.4.17.3 Diagram....................................................................................................................................739
18.4.17.4 Fields........................................................................................................................................ 739
18.4.18 DDR SDRAM timing configuration 4 (TIMING_CFG_4)......................................................................... 740
18.4.18.1 Offset........................................................................................................................................740
18.4.18.2 Function................................................................................................................................... 740
18.4.18.3 Diagram....................................................................................................................................740
18.4.18.4 Fields........................................................................................................................................ 740
18.4.19 DDR SDRAM timing configuration 5 (TIMING_CFG_5)......................................................................... 744
18.4.19.1 Offset........................................................................................................................................744
18.4.19.2 Function................................................................................................................................... 744
18.4.19.3 Diagram....................................................................................................................................744
18.4.19.4 Fields........................................................................................................................................ 744
18.4.20 DDR SDRAM timing configuration 6 (TIMING_CFG_6)......................................................................... 746
18.4.20.1 Offset........................................................................................................................................746
18.4.20.2 Function................................................................................................................................... 746
18.4.20.3 Diagram....................................................................................................................................746
18.4.20.4 Fields........................................................................................................................................ 747
18.4.21 DDR SDRAM timing configuration 7 (TIMING_CFG_7)......................................................................... 749
18.4.21.1 Offset........................................................................................................................................749
18.4.21.2 Function................................................................................................................................... 749
18.4.21.3 Diagram....................................................................................................................................749
18.4.21.4 Fields........................................................................................................................................ 749
18.4.22 DDR ZQ calibration control (DDR_ZQ_CNTL).........................................................................................751
18.4.22.1 Offset........................................................................................................................................751
18.4.22.2 Function................................................................................................................................... 752
18.4.22.3 Diagram....................................................................................................................................752
18.4.22.4 Fields........................................................................................................................................ 752
18.4.23 DDR write leveling control (DDR_WRLVL_CNTL)................................................................................. 754
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 33
Section number Title Page
18.4.23.1 Offset........................................................................................................................................754
18.4.23.2 Function................................................................................................................................... 754
18.4.23.3 Diagram....................................................................................................................................754
18.4.23.4 Fields........................................................................................................................................ 755
18.4.24 DDR Self Refresh Counter (DDR_SR_CNTR)...........................................................................................758
18.4.24.1 Offset........................................................................................................................................758
18.4.24.2 Function................................................................................................................................... 758
18.4.24.3 Diagram....................................................................................................................................758
18.4.24.4 Fields........................................................................................................................................ 758
18.4.25 DDR Register Control Words 1 (DDR_SDRAM_RCW_1)........................................................................759
18.4.25.1 Offset........................................................................................................................................759
18.4.25.2 Function................................................................................................................................... 759
18.4.25.3 Diagram....................................................................................................................................759
18.4.25.4 Fields........................................................................................................................................ 760
18.4.26 DDR Register Control Words 2 (DDR_SDRAM_RCW_2)........................................................................760
18.4.26.1 Offset........................................................................................................................................760
18.4.26.2 Function................................................................................................................................... 761
18.4.26.3 Diagram....................................................................................................................................761
18.4.26.4 Fields........................................................................................................................................ 761
18.4.27 DDR write leveling control 2 (DDR_WRLVL_CNTL_2).......................................................................... 762
18.4.27.1 Offset........................................................................................................................................762
18.4.27.2 Function................................................................................................................................... 762
18.4.27.3 Diagram....................................................................................................................................762
18.4.27.4 Fields........................................................................................................................................ 763
18.4.28 DDR write leveling control 3 (DDR_WRLVL_CNTL_3).......................................................................... 766
18.4.28.1 Offset........................................................................................................................................766
18.4.28.2 Function................................................................................................................................... 766
18.4.28.3 Diagram....................................................................................................................................766
18.4.28.4 Fields........................................................................................................................................ 766
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
34 NXP Semiconductors
Section number Title Page
18.4.29 DDR Register Control Words 3 (DDR_SDRAM_RCW_3)........................................................................769
18.4.29.1 Offset........................................................................................................................................769
18.4.29.2 Function................................................................................................................................... 770
18.4.29.3 Diagram....................................................................................................................................770
18.4.29.4 Fields........................................................................................................................................ 770
18.4.30 DDR Register Control Words 4 (DDR_SDRAM_RCW_4)........................................................................770
18.4.30.1 Offset........................................................................................................................................770
18.4.30.2 Function................................................................................................................................... 771
18.4.30.3 Diagram....................................................................................................................................771
18.4.30.4 Fields........................................................................................................................................ 771
18.4.31 DDR Register Control Words 5 (DDR_SDRAM_RCW_5)........................................................................772
18.4.31.1 Offset........................................................................................................................................772
18.4.31.2 Function................................................................................................................................... 772
18.4.31.3 Diagram....................................................................................................................................772
18.4.31.4 Fields........................................................................................................................................ 772
18.4.32 DDR Register Control Words 6 (DDR_SDRAM_RCW_6)........................................................................773
18.4.32.1 Offset........................................................................................................................................773
18.4.32.2 Function................................................................................................................................... 773
18.4.32.3 Diagram....................................................................................................................................773
18.4.32.4 Fields........................................................................................................................................ 773
18.4.33 DDR SDRAM mode configuration 3 (DDR_SDRAM_MODE_3)............................................................ 774
18.4.33.1 Offset........................................................................................................................................774
18.4.33.2 Function................................................................................................................................... 774
18.4.33.3 Diagram....................................................................................................................................774
18.4.33.4 Fields........................................................................................................................................ 775
18.4.34 DDR SDRAM mode configuration 4 (DDR_SDRAM_MODE_4)............................................................ 775
18.4.34.1 Offset........................................................................................................................................775
18.4.34.2 Function................................................................................................................................... 776
18.4.34.3 Diagram....................................................................................................................................776
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 35
Section number Title Page
18.4.34.4 Fields........................................................................................................................................ 776
18.4.35 DDR SDRAM mode configuration 5 (DDR_SDRAM_MODE_5)............................................................ 777
18.4.35.1 Offset........................................................................................................................................777
18.4.35.2 Function................................................................................................................................... 777
18.4.35.3 Diagram....................................................................................................................................777
18.4.35.4 Fields........................................................................................................................................ 777
18.4.36 DDR SDRAM mode configuration 6 (DDR_SDRAM_MODE_6)............................................................ 778
18.4.36.1 Offset........................................................................................................................................778
18.4.36.2 Function................................................................................................................................... 778
18.4.36.3 Diagram....................................................................................................................................778
18.4.36.4 Fields........................................................................................................................................ 779
18.4.37 DDR SDRAM mode configuration 7 (DDR_SDRAM_MODE_7)............................................................ 779
18.4.37.1 Offset........................................................................................................................................779
18.4.37.2 Function................................................................................................................................... 780
18.4.37.3 Diagram....................................................................................................................................780
18.4.37.4 Fields........................................................................................................................................ 780
18.4.38 DDR SDRAM mode configuration 8 (DDR_SDRAM_MODE_8)............................................................ 781
18.4.38.1 Offset........................................................................................................................................781
18.4.38.2 Function................................................................................................................................... 781
18.4.38.3 Diagram....................................................................................................................................781
18.4.38.4 Fields........................................................................................................................................ 781
18.4.39 DDR SDRAM mode configuration 9 (DDR_SDRAM_MODE_9)............................................................ 782
18.4.39.1 Offset........................................................................................................................................782
18.4.39.2 Function................................................................................................................................... 782
18.4.39.3 Diagram....................................................................................................................................782
18.4.39.4 Fields........................................................................................................................................ 783
18.4.40 DDR SDRAM mode configuration 10 (DDR_SDRAM_MODE_10)........................................................ 783
18.4.40.1 Offset........................................................................................................................................783
18.4.40.2 Function................................................................................................................................... 783
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
36 NXP Semiconductors
Section number Title Page
18.4.40.3 Diagram....................................................................................................................................783
18.4.40.4 Fields........................................................................................................................................ 784
18.4.41 DDR SDRAM mode configuration 11 (DDR_SDRAM_MODE_11)........................................................ 784
18.4.41.1 Offset........................................................................................................................................784
18.4.41.2 Function................................................................................................................................... 784
18.4.41.3 Diagram....................................................................................................................................785
18.4.41.4 Fields........................................................................................................................................ 785
18.4.42 DDR SDRAM mode configuration 12 (DDR_SDRAM_MODE_12)........................................................ 785
18.4.42.1 Offset........................................................................................................................................785
18.4.42.2 Function................................................................................................................................... 786
18.4.42.3 Diagram....................................................................................................................................786
18.4.42.4 Fields........................................................................................................................................ 786
18.4.43 DDR SDRAM mode configuration 13 (DDR_SDRAM_MODE_13)........................................................ 787
18.4.43.1 Offset........................................................................................................................................787
18.4.43.2 Function................................................................................................................................... 787
18.4.43.3 Diagram....................................................................................................................................787
18.4.43.4 Fields........................................................................................................................................ 787
18.4.44 DDR SDRAM mode configuration 14 (DDR_SDRAM_MODE_14)........................................................ 788
18.4.44.1 Offset........................................................................................................................................788
18.4.44.2 Function................................................................................................................................... 788
18.4.44.3 Diagram....................................................................................................................................788
18.4.44.4 Fields........................................................................................................................................ 789
18.4.45 DDR SDRAM mode configuration 15 (DDR_SDRAM_MODE_15)........................................................ 789
18.4.45.1 Offset........................................................................................................................................789
18.4.45.2 Function................................................................................................................................... 790
18.4.45.3 Diagram....................................................................................................................................790
18.4.45.4 Fields........................................................................................................................................ 790
18.4.46 DDR SDRAM mode configuration 16 (DDR_SDRAM_MODE_16)........................................................ 790
18.4.46.1 Offset........................................................................................................................................791
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 37
Section number Title Page
18.4.46.2 Function................................................................................................................................... 791
18.4.46.3 Diagram....................................................................................................................................791
18.4.46.4 Fields........................................................................................................................................ 791
18.4.47 DDR SDRAM timing configuration 8 (TIMING_CFG_8)......................................................................... 792
18.4.47.1 Offset........................................................................................................................................792
18.4.47.2 Function................................................................................................................................... 792
18.4.47.3 Diagram....................................................................................................................................792
18.4.47.4 Fields........................................................................................................................................ 792
18.4.48 DDR SDRAM control configuration 3 (DDR_SDRAM_CFG_3).............................................................. 796
18.4.48.1 Offset........................................................................................................................................796
18.4.48.2 Function................................................................................................................................... 796
18.4.48.3 Diagram....................................................................................................................................796
18.4.48.4 Fields........................................................................................................................................ 797
18.4.49 DQ mapping register 0 (DDR_DQ_MAP0)................................................................................................ 799
18.4.49.1 Offset........................................................................................................................................799
18.4.49.2 Function................................................................................................................................... 800
18.4.49.3 Diagram....................................................................................................................................801
18.4.49.4 Fields........................................................................................................................................ 802
18.4.50 DQ mapping register 1 (DDR_DQ_MAP1)................................................................................................ 802
18.4.50.1 Offset........................................................................................................................................802
18.4.50.2 Function................................................................................................................................... 803
18.4.50.3 Diagram....................................................................................................................................803
18.4.50.4 Fields........................................................................................................................................ 803
18.4.51 DQ mapping register 2 (DDR_DQ_MAP2)................................................................................................ 803
18.4.51.1 Offset........................................................................................................................................804
18.4.51.2 Function................................................................................................................................... 804
18.4.51.3 Diagram....................................................................................................................................804
18.4.51.4 Fields........................................................................................................................................ 804
18.4.52 DQ mapping register 3 (DDR_DQ_MAP3)................................................................................................ 805
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
38 NXP Semiconductors
Section number Title Page
18.4.52.1 Offset........................................................................................................................................805
18.4.52.2 Function................................................................................................................................... 805
18.4.52.3 Diagram....................................................................................................................................805
18.4.52.4 Fields........................................................................................................................................ 805
18.4.53 DDR Debug Status Register 1 (DDRDSR_1)..............................................................................................806
18.4.53.1 Offset........................................................................................................................................806
18.4.53.2 Function................................................................................................................................... 806
18.4.53.3 Diagram....................................................................................................................................806
18.4.53.4 Fields........................................................................................................................................ 807
18.4.54 DDR Debug Status Register 2 (DDRDSR_2)..............................................................................................807
18.4.54.1 Offset........................................................................................................................................807
18.4.54.2 Function................................................................................................................................... 807
18.4.54.3 Diagram....................................................................................................................................808
18.4.54.4 Fields........................................................................................................................................ 808
18.4.55 DDR Control Driver Register 1 (DDRCDR_1)........................................................................................... 809
18.4.55.1 Offset........................................................................................................................................809
18.4.55.2 Function................................................................................................................................... 809
18.4.55.3 Diagram....................................................................................................................................809
18.4.55.4 Fields........................................................................................................................................ 810
18.4.56 DDR Control Driver Register 2 (DDRCDR_2)........................................................................................... 811
18.4.56.1 Offset........................................................................................................................................811
18.4.56.2 Function................................................................................................................................... 811
18.4.56.3 Diagram....................................................................................................................................811
18.4.56.4 Fields........................................................................................................................................ 812
18.4.57 DDR IP block revision 1 (DDR_IP_REV1)................................................................................................ 813
18.4.57.1 Offset........................................................................................................................................813
18.4.57.2 Function................................................................................................................................... 814
18.4.57.3 Diagram....................................................................................................................................814
18.4.57.4 Fields........................................................................................................................................ 814
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 39
Section number Title Page
18.4.58 DDR IP block revision 2 (DDR_IP_REV2)................................................................................................ 814
18.4.58.1 Offset........................................................................................................................................814
18.4.58.2 Function................................................................................................................................... 815
18.4.58.3 Diagram....................................................................................................................................815
18.4.58.4 Fields........................................................................................................................................ 815
18.4.59 DDR Memory Test Control Register (DDR_MTCR)..................................................................................815
18.4.59.1 Offset........................................................................................................................................815
18.4.59.2 Function................................................................................................................................... 816
18.4.59.3 Diagram....................................................................................................................................816
18.4.59.4 Fields........................................................................................................................................ 816
18.4.60 DDR Memory Test Pattern n Register (DDR_MTP1 - DDR_MTP10).......................................................818
18.4.60.1 Offset........................................................................................................................................818
18.4.60.2 Function................................................................................................................................... 818
18.4.60.3 Diagram....................................................................................................................................818
18.4.60.4 Fields........................................................................................................................................ 818
18.4.61 DDR Memory Test Start Extended Address (DDR_MT_ST_EXT_ADDR).............................................. 819
18.4.61.1 Offset........................................................................................................................................819
18.4.61.2 Function................................................................................................................................... 819
18.4.61.3 Diagram....................................................................................................................................819
18.4.61.4 Fields........................................................................................................................................ 819
18.4.62 DDR Memory Test Start Address (DDR_MT_ST_ADDR)........................................................................820
18.4.62.1 Offset........................................................................................................................................820
18.4.62.2 Function................................................................................................................................... 820
18.4.62.3 Diagram....................................................................................................................................820
18.4.62.4 Fields........................................................................................................................................ 821
18.4.63 DDR Memory Test End Extended Address (DDR_MT_END_EXT_ADDR)........................................... 821
18.4.63.1 Offset........................................................................................................................................821
18.4.63.2 Function................................................................................................................................... 821
18.4.63.3 Diagram....................................................................................................................................821
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
40 NXP Semiconductors
Section number Title Page
18.4.63.4 Fields........................................................................................................................................ 822
18.4.64 DDR Memory Test End Address (DDR_MT_END_ADDR)..................................................................... 822
18.4.64.1 Offset........................................................................................................................................822
18.4.64.2 Function................................................................................................................................... 822
18.4.64.3 Diagram....................................................................................................................................822
18.4.64.4 Fields........................................................................................................................................ 823
18.4.65 Memory data path error injection mask high (DATA_ERR_INJECT_HI)................................................. 823
18.4.65.1 Offset........................................................................................................................................823
18.4.65.2 Diagram....................................................................................................................................823
18.4.65.3 Fields........................................................................................................................................ 824
18.4.66 Memory data path error injection mask low (DATA_ERR_INJECT_LO)................................................. 824
18.4.66.1 Offset........................................................................................................................................824
18.4.66.2 Diagram....................................................................................................................................824
18.4.66.3 Fields........................................................................................................................................ 825
18.4.67 Memory data path error injection mask ECC (ECC_ERR_INJECT)..........................................................825
18.4.67.1 Offset........................................................................................................................................825
18.4.67.2 Function................................................................................................................................... 825
18.4.67.3 Diagram....................................................................................................................................825
18.4.67.4 Fields........................................................................................................................................ 826
18.4.68 Memory data path read capture high (CAPTURE_DATA_HI).................................................................. 827
18.4.68.1 Offset........................................................................................................................................827
18.4.68.2 Function................................................................................................................................... 827
18.4.68.3 Diagram....................................................................................................................................827
18.4.68.4 Fields........................................................................................................................................ 827
18.4.69 Memory data path read capture low (CAPTURE_DATA_LO).................................................................. 827
18.4.69.1 Offset........................................................................................................................................828
18.4.69.2 Function................................................................................................................................... 828
18.4.69.3 Diagram....................................................................................................................................828
18.4.69.4 Fields........................................................................................................................................ 828
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 41
Section number Title Page
18.4.70 Memory data path read capture ECC (CAPTURE_ECC)........................................................................... 828
18.4.70.1 Offset........................................................................................................................................828
18.4.70.2 Function................................................................................................................................... 829
18.4.70.3 Diagram....................................................................................................................................829
18.4.70.4 Fields........................................................................................................................................ 829
18.4.71 Memory error detect (ERR_DETECT)........................................................................................................830
18.4.71.1 Offset........................................................................................................................................830
18.4.71.2 Function................................................................................................................................... 830
18.4.71.3 Diagram....................................................................................................................................830
18.4.71.4 Fields........................................................................................................................................ 830
18.4.72 Memory error disable (ERR_DISABLE).................................................................................................... 832
18.4.72.1 Offset........................................................................................................................................832
18.4.72.2 Function................................................................................................................................... 832
18.4.72.3 Diagram....................................................................................................................................832
18.4.72.4 Fields........................................................................................................................................ 833
18.4.73 Memory error interrupt enable (ERR_INT_EN)......................................................................................... 833
18.4.73.1 Offset........................................................................................................................................834
18.4.73.2 Function................................................................................................................................... 834
18.4.73.3 Diagram....................................................................................................................................834
18.4.73.4 Fields........................................................................................................................................ 834
18.4.74 Memory error attributes capture (CAPTURE_ATTRIBUTES).................................................................. 835
18.4.74.1 Offset........................................................................................................................................835
18.4.74.2 Function................................................................................................................................... 835
18.4.74.3 Diagram....................................................................................................................................836
18.4.74.4 Fields........................................................................................................................................ 836
18.4.75 Memory error address capture (CAPTURE_ADDRESS)........................................................................... 837
18.4.75.1 Offset........................................................................................................................................837
18.4.75.2 Function................................................................................................................................... 837
18.4.75.3 Diagram....................................................................................................................................837
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
42 NXP Semiconductors
Section number Title Page
18.4.75.4 Fields........................................................................................................................................ 838
18.4.76 Memory error extended address capture (CAPTURE_EXT_ADDRESS).................................................. 838
18.4.76.1 Offset........................................................................................................................................838
18.4.76.2 Function................................................................................................................................... 838
18.4.76.3 Diagram....................................................................................................................................838
18.4.76.4 Fields........................................................................................................................................ 838
18.4.77 Single-Bit ECC memory error management (ERR_SBE)........................................................................... 839
18.4.77.1 Offset........................................................................................................................................839
18.4.77.2 Function................................................................................................................................... 839
18.4.77.3 Diagram....................................................................................................................................839
18.4.77.4 Fields........................................................................................................................................ 839
18.5 DDR Functional Description........................................................................................................................................ 840
18.5.1 DDR SDRAM Interface Operation..............................................................................................................844
18.5.1.1 Supported DDR SDRAM Organizations................................................................................. 844
18.5.2 DDR SDRAM Address Multiplexing.......................................................................................................... 845
18.5.3 DDR SDRAM Write Timing Adjustments.................................................................................................. 849
18.5.4 DDR SDRAM Refresh.................................................................................................................................850
18.5.4.1 DDR SDRAM Refresh Timing................................................................................................851
18.5.4.2 DDR SDRAM Refresh and Power-Saving Modes.................................................................. 851
18.5.5 DDR Data Beat Ordering............................................................................................................................. 852
18.5.6 Page Mode and Logical Bank Retention......................................................................................................852
18.5.7 Error Checking and Correcting (ECC).........................................................................................................853
18.5.8 Error Management....................................................................................................................................... 855
18.5.9 DDR Rapid Clear of Memory...................................................................................................................... 856
18.6 Initialization/Application Information.......................................................................................................................... 857
18.6.1 Programming Summary .............................................................................................................................. 861
18.6.2 DDR SDRAM Initialization Sequence........................................................................................................ 867
18.6.3 Using Forced Self-Refresh Mode to Implement a Battery-Backed RAM System...................................... 867
18.6.3.1 Software Based Self-Refresh Scheme......................................................................................867
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 43
Section number Title Page
18.6.3.2 Bypassing Re-initialization During Battery-Backed Operation...............................................867
Chapter 19
Direct Memory Access Multiplexer (DMAMUX)
19.1 The DMAMUX module as implemented on the chip...................................................................................................869
19.1.1 LS1043A DMAMUX module integration................................................................................................... 869
19.1.2 LS1043A DMAMUX module special consideration...................................................................................869
19.1.2.1 eDMA and DMAMUX............................................................................................................ 869
19.1.2.1.1 eDMA and DMAMUX channel assignment.......................................................870
19.1.2.1.2 DMAMUX settings.............................................................................................870
19.1.2.1.3 DMAMUX request sources................................................................................ 870
19.2 Introduction...................................................................................................................................................................873
19.2.1 Overview...................................................................................................................................................... 873
19.2.2 Features........................................................................................................................................................ 874
19.2.3 Modes of operation...................................................................................................................................... 874
19.3 External signal description............................................................................................................................................875
19.4 Memory map/register definition................................................................................................................................... 875
19.4.1 Channel Configuration register (DMAMUXx_CHCFGn).......................................................................... 876
19.5 Functional description...................................................................................................................................................877
19.5.1 Always-enabled DMA sources.................................................................................................................... 877
19.6 Initialization/application information........................................................................................................................... 878
19.6.1 Reset.............................................................................................................................................................878
19.6.2 Enabling and configuring sources................................................................................................................879
Chapter 20
DUART
20.1 The DUART module as implemented on the chip........................................................................................................881
20.2 Overview.......................................................................................................................................................................881
20.2.1 Features........................................................................................................................................................ 882
20.2.2 Modes of operation...................................................................................................................................... 883
20.3 DUART external signal descriptions............................................................................................................................ 883
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
44 NXP Semiconductors
Section number Title Page
20.4 DUART register descriptions....................................................................................................................................... 884
20.4.1 DUART Memory map................................................................................................................................. 885
20.4.2 UART divisor least significant byte register (UDLB1 - UDLB2)...............................................................886
20.4.2.1 Offset........................................................................................................................................886
20.4.2.2 Function................................................................................................................................... 886
20.4.2.3 Diagram....................................................................................................................................887
20.4.2.4 Fields........................................................................................................................................ 887
20.4.3 UART receiver buffer register (URBR1 - URBR2).................................................................................... 887
20.4.3.1 Offset........................................................................................................................................888
20.4.3.2 Function................................................................................................................................... 888
20.4.3.3 Diagram....................................................................................................................................888
20.4.3.4 Fields........................................................................................................................................ 888
20.4.4 UART transmitter holding register (UTHR1 - UTHR2)............................................................................. 888
20.4.4.1 Offset........................................................................................................................................889
20.4.4.2 Function................................................................................................................................... 889
20.4.4.3 Diagram....................................................................................................................................889
20.4.4.4 Fields........................................................................................................................................ 889
20.4.5 UART divisor most significant byte register (UDMB1 - UDMB2)............................................................ 889
20.4.5.1 Offset........................................................................................................................................890
20.4.5.2 Function................................................................................................................................... 890
20.4.5.3 Diagram....................................................................................................................................890
20.4.5.4 Fields........................................................................................................................................ 890
20.4.6 UART interrupt enable register (UIER1 - UIER2)...................................................................................... 891
20.4.6.1 Offset........................................................................................................................................891
20.4.6.2 Function................................................................................................................................... 891
20.4.6.3 Diagram....................................................................................................................................891
20.4.6.4 Fields........................................................................................................................................ 891
20.4.7 UART alternate function register (UAFR1 - UAFR2)................................................................................ 892
20.4.7.1 Offset........................................................................................................................................892
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 45
Section number Title Page
20.4.7.2 Function................................................................................................................................... 892
20.4.7.3 Diagram....................................................................................................................................892
20.4.7.4 Fields........................................................................................................................................ 892
20.4.8 UART FIFO control register (UFCR1 - UFCR2)........................................................................................ 893
20.4.8.1 Offset........................................................................................................................................893
20.4.8.2 Function................................................................................................................................... 893
20.4.8.3 Diagram....................................................................................................................................894
20.4.8.4 Fields........................................................................................................................................ 894
20.4.9 UART interrupt ID register (UIIR1 - UIIR2).............................................................................................. 894
20.4.9.1 Offset........................................................................................................................................895
20.4.9.2 Function................................................................................................................................... 895
20.4.9.3 Diagram....................................................................................................................................896
20.4.9.4 Fields........................................................................................................................................ 896
20.4.10 UART line control register (ULCR1 - ULCR2).......................................................................................... 897
20.4.10.1 Offset........................................................................................................................................897
20.4.10.2 Function................................................................................................................................... 897
20.4.10.3 Diagram....................................................................................................................................898
20.4.10.4 Fields........................................................................................................................................ 898
20.4.11 UART modem control register (UMCR1 - UMCR2).................................................................................. 899
20.4.11.1 Offset........................................................................................................................................899
20.4.11.2 Function................................................................................................................................... 899
20.4.11.3 Diagram....................................................................................................................................899
20.4.11.4 Fields........................................................................................................................................ 900
20.4.12 UART line status register (ULSR1 - ULSR2)............................................................................................. 900
20.4.12.1 Offset........................................................................................................................................900
20.4.12.2 Function................................................................................................................................... 900
20.4.12.3 Diagram....................................................................................................................................901
20.4.12.4 Fields........................................................................................................................................ 901
20.4.13 UART modem status register (UMSR1 - UMSR2)..................................................................................... 902
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
46 NXP Semiconductors
Section number Title Page
20.4.13.1 Offset........................................................................................................................................902
20.4.13.2 Function................................................................................................................................... 902
20.4.13.3 Diagram....................................................................................................................................902
20.4.13.4 Fields........................................................................................................................................ 903
20.4.14 UART scratch register (USCR1 - USCR2)..................................................................................................903
20.4.14.1 Offset........................................................................................................................................903
20.4.14.2 Function................................................................................................................................... 903
20.4.14.3 Diagram....................................................................................................................................904
20.4.14.4 Fields........................................................................................................................................ 904
20.4.15 UART DMA status register (UDSR1 - UDSR2)......................................................................................... 904
20.4.15.1 Offset........................................................................................................................................904
20.4.15.2 Function................................................................................................................................... 904
20.4.15.3 Diagram....................................................................................................................................906
20.4.15.4 Fields........................................................................................................................................ 906
20.5 Functional description...................................................................................................................................................906
20.5.1 Serial interface............................................................................................................................................. 906
20.5.1.1 START bit................................................................................................................................907
20.5.1.2 Data transfer............................................................................................................................. 907
20.5.1.3 Parity bit................................................................................................................................... 908
20.5.1.4 STOP bit...................................................................................................................................908
20.5.2 Baud-rate generator logic.............................................................................................................................908
20.5.3 Local loopback mode................................................................................................................................... 909
20.5.4 Errors............................................................................................................................................................909
20.5.4.1 Framing error........................................................................................................................... 909
20.5.4.2 Parity error............................................................................................................................... 910
20.5.4.3 Overrun error............................................................................................................................910
20.5.5 FIFO mode................................................................................................................................................... 910
20.5.5.1 FIFO interrupts.........................................................................................................................910
20.5.5.2 Interrupt control logic.............................................................................................................. 911
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 47
Section number Title Page
20.6 Initialization/Application information.......................................................................................................................... 911
Chapter 21
Enhanced Direct Memory Access (eDMA)
21.1 Overview ......................................................................................................................................................................913
21.2 Introduction...................................................................................................................................................................913
21.2.1 eDMA system block diagram...................................................................................................................... 913
21.2.2 Block parts................................................................................................................................................... 914
21.2.3 Features........................................................................................................................................................ 915
21.3 Modes of operation....................................................................................................................................................... 916
21.4 Memory map/register definition................................................................................................................................... 917
21.4.1 TCD memory............................................................................................................................................... 917
21.4.2 TCD initialization........................................................................................................................................ 917
21.4.3 TCD structure...............................................................................................................................................917
21.4.4 Reserved memory and bit fields...................................................................................................................918
21.4.5 Endianness................................................................................................................................................... 918
21.4.6 Control Register (DMA_CR).......................................................................................................................945
21.4.7 Error Status Register (DMA_ES)................................................................................................................ 948
21.4.8 Enable Request Register (DMA_ERQ)....................................................................................................... 950
21.4.9 Enable Error Interrupt Register (DMA_EEI)...............................................................................................954
21.4.10 Clear Enable Error Interrupt Register (DMA_CEEI).................................................................................. 957
21.4.11 Set Enable Error Interrupt Register (DMA_SEEI)...................................................................................... 958
21.4.12 Clear Enable Request Register (DMA_CERQ)........................................................................................... 959
21.4.13 Set Enable Request Register (DMA_SERQ)............................................................................................... 960
21.4.14 Clear DONE Status Bit Register (DMA_CDNE)........................................................................................ 961
21.4.15 Set START Bit Register (DMA_SSRT)...................................................................................................... 962
21.4.16 Clear Error Register (DMA_CERR)............................................................................................................963
21.4.17 Clear Interrupt Request Register (DMA_CINT)......................................................................................... 964
21.4.18 Interrupt Request Register (DMA_INT)......................................................................................................965
21.4.19 Error Register (DMA_ERR)........................................................................................................................ 968
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
48 NXP Semiconductors
Section number Title Page
21.4.20 Hardware Request Status Register (DMA_HRS)........................................................................................ 972
21.4.21 Channel n Priority Register (DMA_DCHPRIn).......................................................................................... 978
21.4.22 TCD Source Address (DMA_TCDn_SADDR)........................................................................................... 979
21.4.23 TCD Signed Source Address Offset (DMA_TCDn_SOFF)........................................................................980
21.4.24 TCD Transfer Attributes (DMA_TCDn_ATTR).........................................................................................980
21.4.25 TCD Minor Byte Count (Minor Loop Mapping Disabled) (DMA_TCDn_NBYTES_MLNO)................. 981
21.4.26 TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
(DMA_TCDn_NBYTES_MLOFFNO)....................................................................................................... 982
21.4.27 TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
(DMA_TCDn_NBYTES_MLOFFYES)..................................................................................................... 983
21.4.28 TCD Last Source Address Adjustment (DMA_TCDn_SLAST).................................................................985
21.4.29 TCD Destination Address (DMA_TCDn_DADDR)................................................................................... 985
21.4.30 TCD Signed Destination Address Offset (DMA_TCDn_DOFF)................................................................986
21.4.31 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_CITER_ELINKYES)...........................................................................................................986
21.4.32 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_CITER_ELINKNO)............................................................................................................ 987
21.4.33 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCDn_DLASTSGA).......... 988
21.4.34 TCD Control and Status (DMA_TCDn_CSR)............................................................................................ 989
21.4.35 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_BITER_ELINKYES)...........................................................................................................991
21.4.36 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_BITER_ELINKNO)............................................................................................................ 992
21.5 Functional description...................................................................................................................................................993
21.5.1 eDMA basic data flow................................................................................................................................. 993
21.5.2 Fault reporting and handling........................................................................................................................ 996
21.5.3 Channel preemption..................................................................................................................................... 999
21.6 Initialization/application information........................................................................................................................... 999
21.6.1 eDMA initialization..................................................................................................................................... 999
21.6.2 Programming errors..................................................................................................................................... 1001
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 49
Section number Title Page
21.6.3 Arbitration mode considerations.................................................................................................................. 1002
21.6.3.1 Fixed group arbitration, Fixed channel arbitration.................................................................. 1002
21.6.3.2 Fixed group arbitration, Round-robin channel arbitration....................................................... 1003
21.6.4 Performing DMA transfers.......................................................................................................................... 1003
21.6.4.1 Single request........................................................................................................................... 1003
21.6.4.2 Multiple requests......................................................................................................................1005
21.6.4.3 Using the modulo feature......................................................................................................... 1007
21.6.5 Monitoring transfer descriptor status........................................................................................................... 1007
21.6.5.1 Testing for minor loop completion.......................................................................................... 1007
21.6.5.2 Reading the transfer descriptors of active channels.................................................................1008
21.6.5.3 Checking channel preemption status........................................................................................1009
21.6.6 Channel Linking...........................................................................................................................................1009
21.6.7 Dynamic programming................................................................................................................................ 1010
21.6.7.1 Dynamically changing the channel priority............................................................................. 1010
21.6.7.2 Dynamic channel linking......................................................................................................... 1011
21.6.7.3 Dynamic scatter/gather............................................................................................................ 1011
21.6.7.3.1 Method 1 (channel not using major loop channel linking)................................. 1012
21.6.7.3.2 Method 2 (channel using major loop channel linking)....................................... 1013
21.6.8 Suspend/resume a DMA channel with active hardware service requests.................................................... 1014
21.6.8.1 Suspend an active DMA channel............................................................................................. 1014
21.6.8.2 Resume a DMA channel.......................................................................................................... 1014
Chapter 22
Enhanced Secured Digital Host Controller
22.1 Overview.......................................................................................................................................................................1017
22.1.1 eSDHC features summary............................................................................................................................1019
22.1.2 Modes and operations.................................................................................................................................. 1020
22.1.2.1 Data transfer modes................................................................................................................. 1020
22.2 External signals.............................................................................................................................................................1021
22.2.1 External signals overview............................................................................................................................ 1021
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
50 NXP Semiconductors
Section number Title Page
22.2.2 eSDHC signal descriptions.......................................................................................................................... 1022
22.3 eSDHC register descriptions.........................................................................................................................................1023
22.3.1 eSDHC Memory map...................................................................................................................................1023
22.3.2 SDMA system address register/Block attributes 2 (DSADDR_BLKATTR2)............................................ 1024
22.3.2.1 Offset........................................................................................................................................1024
22.3.2.2 Function................................................................................................................................... 1024
22.3.2.3 Diagram....................................................................................................................................1024
22.3.2.4 Fields........................................................................................................................................ 1025
22.3.3 Block attributes register (BLKATTR)......................................................................................................... 1025
22.3.3.1 Offset........................................................................................................................................1025
22.3.3.2 Function................................................................................................................................... 1026
22.3.3.3 Diagram....................................................................................................................................1026
22.3.3.4 Fields........................................................................................................................................ 1026
22.3.4 Command argument register (CMDARG)...................................................................................................1027
22.3.4.1 Offset........................................................................................................................................1027
22.3.4.2 Function................................................................................................................................... 1027
22.3.4.3 Diagram....................................................................................................................................1027
22.3.4.4 Fields........................................................................................................................................ 1028
22.3.5 Transfer type register (XFERTYP)..............................................................................................................1028
22.3.5.1 Offset........................................................................................................................................1028
22.3.5.2 Function................................................................................................................................... 1028
22.3.5.3 Diagram....................................................................................................................................1030
22.3.5.4 Fields........................................................................................................................................ 1030
22.3.6 Command response 0 register (CMDRSP0)................................................................................................ 1032
22.3.6.1 Offset........................................................................................................................................1032
22.3.6.2 Function................................................................................................................................... 1033
22.3.6.3 Diagram....................................................................................................................................1033
22.3.6.4 Fields........................................................................................................................................ 1033
22.3.7 Command response 1 register (CMDRSP1)................................................................................................ 1033
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 51
Section number Title Page
22.3.7.1 Offset........................................................................................................................................1033
22.3.7.2 Function................................................................................................................................... 1034
22.3.7.3 Diagram....................................................................................................................................1034
22.3.7.4 Fields........................................................................................................................................ 1034
22.3.8 Command response 2 register (CMDRSP2)................................................................................................ 1034
22.3.8.1 Offset........................................................................................................................................1034
22.3.8.2 Function................................................................................................................................... 1035
22.3.8.3 Diagram....................................................................................................................................1035
22.3.8.4 Fields........................................................................................................................................ 1035
22.3.9 Command Response 3 register (CMDRSP3)...............................................................................................1035
22.3.9.1 Offset........................................................................................................................................1035
22.3.9.2 Function................................................................................................................................... 1036
22.3.9.3 Diagram....................................................................................................................................1037
22.3.9.4 Fields........................................................................................................................................ 1037
22.3.10 Buffer data port register (DATPORT)......................................................................................................... 1037
22.3.10.1 Offset........................................................................................................................................1037
22.3.10.2 Function................................................................................................................................... 1038
22.3.10.3 Diagram....................................................................................................................................1038
22.3.10.4 Fields........................................................................................................................................ 1038
22.3.11 Present state register (PRSSTAT)................................................................................................................1038
22.3.11.1 Offset........................................................................................................................................1038
22.3.11.2 Function................................................................................................................................... 1039
22.3.11.3 Diagram....................................................................................................................................1039
22.3.11.4 Fields........................................................................................................................................ 1039
22.3.12 Protocol control register (PROCTL)............................................................................................................1043
22.3.12.1 Offset........................................................................................................................................1043
22.3.12.2 Function................................................................................................................................... 1043
22.3.12.3 Diagram....................................................................................................................................1043
22.3.12.4 Fields........................................................................................................................................ 1044
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
52 NXP Semiconductors
Section number Title Page
22.3.13 System Control Register when ESDHCCTL[CRS=0] (SYSCTL_ESDHCCTL_CRS_0)..........................1046
22.3.13.1 Offset........................................................................................................................................1046
22.3.13.2 Function................................................................................................................................... 1047
22.3.13.3 Diagram....................................................................................................................................1047
22.3.13.4 Fields........................................................................................................................................ 1047
22.3.14 System Control Register when ESDHCCTL[CRS=1] (SYSCTL_ESDHCCTL_CRS_1)..........................1050
22.3.14.1 Offset........................................................................................................................................1050
22.3.14.2 Diagram....................................................................................................................................1050
22.3.14.3 Fields........................................................................................................................................ 1050
22.3.15 Interrupt status register (IRQSTAT)............................................................................................................ 1053
22.3.15.1 Offset........................................................................................................................................1053
22.3.15.2 Function................................................................................................................................... 1053
22.3.15.3 Diagram....................................................................................................................................1054
22.3.15.4 Fields........................................................................................................................................ 1054
22.3.16 Interrupt status enable register (IRQSTATEN)........................................................................................... 1058
22.3.16.1 Offset........................................................................................................................................1058
22.3.16.2 Function................................................................................................................................... 1058
22.3.16.3 Diagram....................................................................................................................................1058
22.3.16.4 Fields........................................................................................................................................ 1059
22.3.17 Interrupt signal enable register (IRQSIGEN).............................................................................................. 1060
22.3.17.1 Offset........................................................................................................................................1061
22.3.17.2 Function................................................................................................................................... 1061
22.3.17.3 Diagram....................................................................................................................................1061
22.3.17.4 Fields........................................................................................................................................ 1061
22.3.18 Auto CMD Error Status Register / System Control 2 Register (AUTOCERR_SYSCTL2)....................... 1063
22.3.18.1 Offset........................................................................................................................................1063
22.3.18.2 Function................................................................................................................................... 1063
22.3.18.3 Diagram....................................................................................................................................1064
22.3.18.4 Fields........................................................................................................................................ 1065
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 53
Section number Title Page
22.3.19 Host controller capabilities register (HOSTCAPBLT)................................................................................ 1066
22.3.19.1 Offset........................................................................................................................................1066
22.3.19.2 Function................................................................................................................................... 1067
22.3.19.3 Diagram....................................................................................................................................1067
22.3.19.4 Fields........................................................................................................................................ 1067
22.3.20 Watermark level register (WML)................................................................................................................ 1068
22.3.20.1 Offset........................................................................................................................................1068
22.3.20.2 Function................................................................................................................................... 1069
22.3.20.3 Diagram....................................................................................................................................1069
22.3.20.4 Fields........................................................................................................................................ 1069
22.3.21 Force event register (FEVT)........................................................................................................................ 1070
22.3.21.1 Offset........................................................................................................................................1070
22.3.21.2 Function................................................................................................................................... 1070
22.3.21.3 Diagram....................................................................................................................................1071
22.3.21.4 Fields........................................................................................................................................ 1071
22.3.22 ADMA error status register (ADMAES)..................................................................................................... 1072
22.3.22.1 Offset........................................................................................................................................1073
22.3.22.2 Function................................................................................................................................... 1073
22.3.22.3 Diagram....................................................................................................................................1074
22.3.22.4 Fields........................................................................................................................................ 1074
22.3.23 ADMA system address register (ADSADDR)............................................................................................ 1074
22.3.23.1 Offset........................................................................................................................................1075
22.3.23.2 Function................................................................................................................................... 1075
22.3.23.3 Diagram....................................................................................................................................1075
22.3.23.4 Fields........................................................................................................................................ 1075
22.3.24 Host controller version register (HOSTVER)..............................................................................................1075
22.3.24.1 Offset........................................................................................................................................1076
22.3.24.2 Function................................................................................................................................... 1076
22.3.24.3 Diagram....................................................................................................................................1076
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
54 NXP Semiconductors
Section number Title Page
22.3.24.4 Fields........................................................................................................................................ 1076
22.3.25 DMA error address register (DMAERRADDR)......................................................................................... 1077
22.3.25.1 Offset........................................................................................................................................1077
22.3.25.2 Function................................................................................................................................... 1077
22.3.25.3 Diagram....................................................................................................................................1077
22.3.25.4 Fields........................................................................................................................................ 1077
22.3.26 DMA error attribute register (DMAERRATTR)......................................................................................... 1078
22.3.26.1 Offset........................................................................................................................................1078
22.3.26.2 Function................................................................................................................................... 1078
22.3.26.3 Diagram....................................................................................................................................1078
22.3.26.4 Fields........................................................................................................................................ 1078
22.3.27 Host controller capabilities register 2 (HOSTCAPBLT2)........................................................................... 1079
22.3.27.1 Offset........................................................................................................................................1079
22.3.27.2 Function................................................................................................................................... 1079
22.3.27.3 Diagram....................................................................................................................................1079
22.3.27.4 Fields........................................................................................................................................ 1079
22.3.28 Tuning block control register (TBCTL).......................................................................................................1081
22.3.28.1 Offset........................................................................................................................................1081
22.3.28.2 Function................................................................................................................................... 1081
22.3.28.3 Diagram....................................................................................................................................1081
22.3.28.4 Fields........................................................................................................................................ 1081
22.3.29 Tuning block status register (TBSTAT)...................................................................................................... 1082
22.3.29.1 Offset........................................................................................................................................1082
22.3.29.2 Function................................................................................................................................... 1083
22.3.29.3 Diagram....................................................................................................................................1083
22.3.29.4 Fields........................................................................................................................................ 1083
22.3.30 Tuning block pointer register (TBPTR).......................................................................................................1083
22.3.30.1 Offset........................................................................................................................................1083
22.3.30.2 Function................................................................................................................................... 1084
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 55
Section number Title Page
22.3.30.3 Diagram....................................................................................................................................1084
22.3.30.4 Fields........................................................................................................................................ 1084
22.3.31 SD direction control register (SDDIRCTL).................................................................................................1084
22.3.31.1 Offset........................................................................................................................................1085
22.3.31.2 Function................................................................................................................................... 1085
22.3.31.3 Diagram....................................................................................................................................1085
22.3.31.4 Fields........................................................................................................................................ 1085
22.3.32 SD Clock Control Register (SDCLKCTL).................................................................................................. 1086
22.3.32.1 Offset........................................................................................................................................1086
22.3.32.2 Function................................................................................................................................... 1086
22.3.32.3 Diagram....................................................................................................................................1086
22.3.32.4 Fields........................................................................................................................................ 1086
22.3.33 eSDHC control register (ESDHCCTL)........................................................................................................1087
22.3.33.1 Offset........................................................................................................................................1087
22.3.33.2 Function................................................................................................................................... 1087
22.3.33.3 Diagram....................................................................................................................................1088
22.3.33.4 Fields........................................................................................................................................ 1088
22.4 Functional description...................................................................................................................................................1089
22.4.1 System interface and control unit (SysICU)................................................................................................ 1090
22.4.1.1 Data buffer............................................................................................................................... 1091
22.4.1.1.1 Write operation sequence....................................................................................1092
22.4.1.1.2 Read operation sequence.....................................................................................1092
22.4.1.1.3 Data buffer and block size.................................................................................. 1093
22.4.1.1.4 Dividing large data transfer................................................................................ 1096
22.4.1.1.5 Byte order (endianness) of buffer data port register........................................... 1097
22.4.1.2 DMA system interface............................................................................................................. 1098
22.4.1.2.1 DMA burst length............................................................................................... 1099
22.4.1.2.2 System master interface...................................................................................... 1099
22.4.1.3 Single DMA (SDMA).............................................................................................................. 1100
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
56 NXP Semiconductors
Section number Title Page
22.4.1.3.1 SDMA error........................................................................................................ 1100
22.4.1.4 Advanced DMA (ADMA)....................................................................................................... 1100
22.4.1.4.1 ADMA concept and descriptor format............................................................... 1100
22.4.1.4.2 ADMA interrupt..................................................................................................1105
22.4.1.4.3 ADMA error........................................................................................................1105
22.4.2 SD interface and control unit (SDICU) .......................................................................................................1105
22.4.2.1 Command CRC........................................................................................................................ 1106
22.4.2.2 Data CRC................................................................................................................................. 1106
22.4.2.3 Tuning block (SDICU).............................................................................................................1106
22.4.3 Register bank ...............................................................................................................................................1108
22.4.4 Clock and reset module................................................................................................................................1109
22.4.4.1 Clock generator........................................................................................................................ 1110
22.4.5 SD monitor................................................................................................................................................... 1111
22.4.5.1 SDIO card interrupt..................................................................................................................1112
22.4.5.1.1 Interrupts in 1-bit mode...................................................................................... 1112
22.4.5.1.2 Interrupt in 4-bit mode........................................................................................ 1112
22.4.5.1.3 Card interrupt handling....................................................................................... 1113
22.4.5.2 Card insertion and removal detection...................................................................................... 1114
22.4.5.3 Power management and wake up events..................................................................................1114
22.4.5.3.1 Setting wake up events........................................................................................1115
22.5 Initialization/application of eSDHC............................................................................................................................. 1116
22.5.1 Command send and response receive basic operation................................................................................. 1116
22.5.2 Card identification mode..............................................................................................................................1117
22.5.2.1 Card detect............................................................................................................................... 1117
22.5.2.2 Reset.........................................................................................................................................1118
22.5.2.3 Voltage validation.................................................................................................................... 1119
22.5.2.4 Card registry.............................................................................................................................1121
22.5.3 Card access...................................................................................................................................................1122
22.5.3.1 Block write............................................................................................................................... 1122
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 57
Section number Title Page
22.5.3.1.1 Normal write....................................................................................................... 1122
22.5.3.1.2 Write with pause................................................................................................. 1124
22.5.3.2 Block read................................................................................................................................ 1125
22.5.3.2.1 Normal read........................................................................................................ 1125
22.5.3.2.2 Read with pause.................................................................................................. 1127
22.5.3.3 Suspend resume........................................................................................................................1128
22.5.3.3.1 Suspend............................................................................................................... 1128
22.5.3.3.2 Resume................................................................................................................1129
22.5.3.4 ADMA usage........................................................................................................................... 1129
22.5.3.5 Tuning block procedure........................................................................................................... 1129
22.5.3.5.1 Tuning procedure for hardware tuning modes....................................................1130
22.5.3.5.2 Tuning procedure for software tuning mode...................................................... 1131
22.5.3.6 DDR......................................................................................................................................... 1131
22.5.3.7 Transfer error........................................................................................................................... 1132
22.5.3.7.1 CRC transfer error...............................................................................................1132
22.5.3.7.2 DMA transfer error............................................................................................. 1132
22.5.3.7.3 ADMA transfer error.......................................................................................... 1132
22.5.3.7.4 Auto CMD12 error..............................................................................................1133
22.5.3.8 Card interrupt........................................................................................................................... 1133
22.5.4 Switch function............................................................................................................................................ 1134
22.5.4.1 Query, enable and disable SDIO high speed mode..................................................................1134
22.5.4.2 Query, enable and disable SD high speed mode...................................................................... 1135
22.5.4.3 Query, enable and disable MMC high speed mode................................................................. 1135
22.5.4.4 Set MMC bus width................................................................................................................. 1136
22.5.5 ADMA operation......................................................................................................................................... 1136
22.5.5.1 ADMA1 operation................................................................................................................... 1136
22.5.5.2 ADMA2 operation................................................................................................................... 1136
22.6 Interfacing Card............................................................................................................................................................ 1137
22.7 Commands for MMC/SD/SDIO and ........................................................................................................................... 1138
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
58 NXP Semiconductors
Section number Title Page
22.8 Software restrictions..................................................................................................................................................... 1144
22.8.1 Software polling procedure.......................................................................................................................... 1145
22.8.2 Suspend operation........................................................................................................................................ 1145
22.8.3 Data port access........................................................................................................................................... 1145
22.8.4 Multi-block read...........................................................................................................................................1145
22.8.5 ADMA address............................................................................................................................................ 1146
22.8.6 Allowed operations after stop at block gap..................................................................................................1146
22.8.7 SDIO card interrupt during soft reset...........................................................................................................1146
22.8.8 Soft reset for data not allowed when SD clock is disabled.......................................................................... 1146
22.8.9 Data transfer with Auto CMD12 Enable......................................................................................................1146
Chapter 23
FlexTimer Module (FTM)
23.1 The FlexTimer module as implemented on the chip.................................................................................................... 1149
23.1.1 LS1043A FlexTimer module integration..................................................................................................... 1149
23.1.2 LS1043A FlexTimer signals........................................................................................................................ 1149
23.1.3 LS1043A FlexTimer module special consideration.....................................................................................1150
23.2 Introduction...................................................................................................................................................................1151
23.2.1 FlexTimer philosophy.................................................................................................................................. 1151
23.2.2 Features........................................................................................................................................................ 1152
23.2.3 Modes of operation...................................................................................................................................... 1153
23.2.4 Block diagram.............................................................................................................................................. 1154
23.3 FTM signal descriptions............................................................................................................................................... 1156
23.4 Memory map and register definition.............................................................................................................................1156
23.4.1 Memory map................................................................................................................................................ 1156
23.4.2 Register descriptions.................................................................................................................................... 1157
23.4.3 Status And Control (FTMx_SC).................................................................................................................. 1169
23.4.4 Counter (FTMx_CNT)................................................................................................................................. 1170
23.4.5 Modulo (FTMx_MOD)................................................................................................................................ 1171
23.4.6 Channel (n) Status And Control (FTMx_CnSC)..........................................................................................1172
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 59
Section number Title Page
23.4.7 Channel (n) Value (FTMx_CnV)................................................................................................................. 1174
23.4.8 Counter Initial Value (FTMx_CNTIN)........................................................................................................1175
23.4.9 Capture And Compare Status (FTMx_STATUS)........................................................................................ 1175
23.4.10 Features Mode Selection (FTMx_MODE).................................................................................................. 1177
23.4.11 Synchronization (FTMx_SYNC)................................................................................................................. 1179
23.4.12 Initial State For Channels Output (FTMx_OUTINIT).................................................................................1182
23.4.13 Output Mask (FTMx_OUTMASK)............................................................................................................. 1183
23.4.14 Function For Linked Channels (FTMx_COMBINE)...................................................................................1185
23.4.15 Deadtime Insertion Control (FTMx_DEADTIME)..................................................................................... 1190
23.4.16 FTM External Trigger (FTMx_EXTTRIG)................................................................................................. 1191
23.4.17 Channels Polarity (FTMx_POL).................................................................................................................. 1193
23.4.18 Fault Mode Status (FTMx_FMS).................................................................................................................1195
23.4.19 Input Capture Filter Control (FTMx_FILTER)........................................................................................... 1197
23.4.20 Fault Control (FTMx_FLTCTRL)............................................................................................................... 1198
23.4.21 Quadrature Decoder Control And Status (FTMx_QDCTRL)......................................................................1200
23.4.22 Configuration (FTMx_CONF)..................................................................................................................... 1202
23.4.23 FTM Fault Input Polarity (FTMx_FLTPOL)...............................................................................................1203
23.4.24 Synchronization Configuration (FTMx_SYNCONF)..................................................................................1205
23.4.25 FTM Inverting Control (FTMx_INVCTRL)................................................................................................1207
23.4.26 FTM Software Output Control (FTMx_SWOCTRL).................................................................................. 1208
23.4.27 FTM PWM Load (FTMx_PWMLOAD)..................................................................................................... 1210
23.5 Functional description...................................................................................................................................................1211
23.5.1 Clock source.................................................................................................................................................1212
23.5.1.1 Counter clock source................................................................................................................1212
23.5.2 Prescaler....................................................................................................................................................... 1213
23.5.3 Counter.........................................................................................................................................................1213
23.5.3.1 Up counting..............................................................................................................................1213
23.5.3.2 Up-down counting....................................................................................................................1216
23.5.3.3 Free running counter................................................................................................................ 1217
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
60 NXP Semiconductors
Section number Title Page
23.5.3.4 Counter reset............................................................................................................................ 1218
23.5.3.5 When the TOF bit is set........................................................................................................... 1218
23.5.4 Input Capture mode......................................................................................................................................1219
23.5.4.1 Filter for Input Capture mode.................................................................................................. 1220
23.5.5 Output Compare mode................................................................................................................................. 1222
23.5.6 Edge-Aligned PWM (EPWM) mode........................................................................................................... 1223
23.5.7 Center-Aligned PWM (CPWM) mode........................................................................................................ 1225
23.5.8 Combine mode............................................................................................................................................. 1227
23.5.8.1 Asymmetrical PWM................................................................................................................ 1234
23.5.9 Complementary mode.................................................................................................................................. 1234
23.5.10 Registers updated from write buffers...........................................................................................................1235
23.5.10.1 CNTIN register update.............................................................................................................1235
23.5.10.2 MOD register update................................................................................................................1236
23.5.10.3 CnV register update................................................................................................................. 1236
23.5.11 PWM synchronization..................................................................................................................................1237
23.5.11.1 Hardware trigger...................................................................................................................... 1237
23.5.11.2 Software trigger........................................................................................................................1238
23.5.11.3 Boundary cycle and loading points.......................................................................................... 1239
23.5.11.4 MOD register synchronization.................................................................................................1240
23.5.11.5 CNTIN register synchronization.............................................................................................. 1243
23.5.11.6 C(n)V and C(n+1)V register synchronization..........................................................................1244
23.5.11.7 OUTMASK register synchronization...................................................................................... 1244
23.5.11.8 INVCTRL register synchronization.........................................................................................1247
23.5.11.9 SWOCTRL register synchronization....................................................................................... 1248
23.5.11.10 FTM counter synchronization.................................................................................................. 1250
23.5.12 Inverting....................................................................................................................................................... 1253
23.5.13 Software output control................................................................................................................................1254
23.5.14 Deadtime insertion....................................................................................................................................... 1256
23.5.14.1 Deadtime insertion corner cases.............................................................................................. 1257
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 61
Section number Title Page
23.5.15 Output mask................................................................................................................................................. 1259
23.5.16 Fault control................................................................................................................................................. 1259
23.5.16.1 Automatic fault clearing...........................................................................................................1261
23.5.16.2 Manual fault clearing............................................................................................................... 1262
23.5.16.3 Fault inputs polarity control..................................................................................................... 1263
23.5.17 Polarity control.............................................................................................................................................1263
23.5.18 Initialization................................................................................................................................................. 1264
23.5.19 Features priority........................................................................................................................................... 1264
23.5.20 Channel trigger output................................................................................................................................. 1265
23.5.21 Initialization trigger......................................................................................................................................1266
23.5.22 Capture Test mode....................................................................................................................................... 1268
23.5.23 DMA............................................................................................................................................................ 1269
23.5.24 Dual Edge Capture mode............................................................................................................................. 1270
23.5.24.1 One-Shot Capture mode...........................................................................................................1271
23.5.24.2 Continuous Capture mode........................................................................................................1272
23.5.24.3 Pulse width measurement.........................................................................................................1272
23.5.24.4 Period measurement................................................................................................................. 1274
23.5.24.5 Read coherency mechanism.....................................................................................................1276
23.5.25 Quadrature Decoder mode........................................................................................................................... 1277
23.5.25.1 Quadrature Decoder boundary conditions............................................................................... 1281
23.5.26 Intermediate load..........................................................................................................................................1282
23.5.27 Global time base (GTB)............................................................................................................................... 1284
23.5.27.1 Enabling the global time base (GTB)...................................................................................... 1285
23.6 Reset overview..............................................................................................................................................................1285
23.7 FTM Interrupts..............................................................................................................................................................1287
23.7.1 Timer Overflow Interrupt.............................................................................................................................1287
23.7.2 Channel (n) Interrupt....................................................................................................................................1287
23.7.3 Fault Interrupt.............................................................................................................................................. 1287
23.8 Initialization Procedure.................................................................................................................................................1287
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
62 NXP Semiconductors
Section number Title Page
Chapter 24
General Purpose I/O (GPIO)
24.1 The GPIO module as implemented on the chip............................................................................................................ 1291
24.2 GPIO overview............................................................................................................................................................. 1291
24.3 GPIO features summary................................................................................................................................................1292
24.4 GPIO signal descriptions.............................................................................................................................................. 1293
24.5 GPIO register descriptions............................................................................................................................................1293
24.5.1 GPIO Memory map......................................................................................................................................1293
24.5.2 GPIO direction register (GPDIR)................................................................................................................ 1294
24.5.2.1 Offset........................................................................................................................................1294
24.5.2.2 Function................................................................................................................................... 1294
24.5.2.3 Diagram....................................................................................................................................1294
24.5.2.4 Fields........................................................................................................................................ 1294
24.5.3 GPIO open drain register (GPODR)............................................................................................................ 1295
24.5.3.1 Offset........................................................................................................................................1295
24.5.3.2 Function................................................................................................................................... 1295
24.5.3.3 Diagram....................................................................................................................................1295
24.5.3.4 Fields........................................................................................................................................ 1295
24.5.4 GPIO data register (GPDAT).......................................................................................................................1296
24.5.4.1 Offset........................................................................................................................................1296
24.5.4.2 Function................................................................................................................................... 1296
24.5.4.3 Diagram....................................................................................................................................1296
24.5.4.4 Fields........................................................................................................................................ 1296
24.5.5 GPIO interrupt event register (GPIER)........................................................................................................1297
24.5.5.1 Offset........................................................................................................................................1297
24.5.5.2 Function................................................................................................................................... 1297
24.5.5.3 Diagram....................................................................................................................................1297
24.5.5.4 Fields........................................................................................................................................ 1298
24.5.6 GPIO interrupt mask register (GPIMR).......................................................................................................1298
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 63
Section number Title Page
24.5.6.1 Offset........................................................................................................................................1298
24.5.6.2 Function................................................................................................................................... 1298
24.5.6.3 Diagram....................................................................................................................................1299
24.5.6.4 Fields........................................................................................................................................ 1299
24.5.7 GPIO interrupt control register (GPICR).....................................................................................................1299
24.5.7.1 Offset........................................................................................................................................1299
24.5.7.2 Function................................................................................................................................... 1299
24.5.7.3 Diagram....................................................................................................................................1299
24.5.7.4 Fields........................................................................................................................................ 1300
Chapter 25
Integrated Flash Controller (IFC)
25.1 IFC overview................................................................................................................................................................ 1301
25.1.1 IFC features summary.................................................................................................................................. 1302
25.1.1.1 NAND flash features................................................................................................................1303
25.1.1.2 NOR flash features...................................................................................................................1304
25.1.1.3 GPCM and GASIC features..................................................................................................... 1304
25.1.2 IFC modes of operation................................................................................................................................1305
25.2 External signal descriptions.......................................................................................................................................... 1305
25.2.1 Internal connectivity of WP/RB signal........................................................................................................ 1309
25.2.1.1 Internal connectivity of WP signal...........................................................................................1310
25.2.1.2 Internal connectivity of RB signal........................................................................................... 1311
25.3 IFC memory map/register definition............................................................................................................................ 1312
25.3.1 IFC Revision Control register (IFC_REV).................................................................................................. 1322
25.3.2 Extended Chip Select Property registers (IFC_CSPRn_EXT).................................................................... 1323
25.3.3 Chip-select Property register n (IFC_CSPRn)............................................................................................. 1323
25.3.4 Address Mask register (IFC_AMASnK)..................................................................................................... 1325
25.3.5 Chip-Select Option register - NAND Flash Mode (IFC_CSORn_NAND)................................................. 1327
25.3.6 Chip-Select Option register - NOR Flash Mode (IFC_CSORn_NOR)....................................................... 1330
25.3.7 Chip-Select Option register - GPCM (IFC_CSORn_GPCM)..................................................................... 1332
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
64 NXP Semiconductors
Section number Title Page
25.3.8 Extended Chip-Select Option register - NAND Flash Mode (IFC_CSORn_EXT).....................................1336
25.3.9 Flash Timing register 0 for Chip Select n - NAND flash asyncNVDDR mode
(IFC_FTIM0_CSn_NAND).........................................................................................................................1338
25.3.10 Flash Timing register 0 for Chip Select n - NAND flash Asynchronous Mode
(IFC_FTIM0_CS_NAND_ASYNC_MODE)............................................................................................. 1340
25.3.11 Flash Timing register 0 for CSn - NOR Flash Mode (IFC_FTIM0_CSn_NOR)........................................ 1341
25.3.12 Flash Timing register 0 for CSn - Normal GPCM Mode (IFC_FTIM0_CSn_GPCM)...............................1343
25.3.13 Flash Timing register 1 for Chip-Select n - NAND Flash NVDDR Mode (IFC_FTIM1_CSn_NAND)....1344
25.3.14 Flash Timing register 1 for Chip Select n - Asynchronous Mode
(IFC_FTIM1_CSn_NAND_ASYNC_MODE)........................................................................................... 1345
25.3.15 Flash Timing register 1 for CSn - NOR Flash Mode (IFC_FTIM1_CSn_NOR)........................................ 1346
25.3.16 Flash Timing register 1 for CSn - Normal GPCM Mode (IFC_FTIM1_CSn_GPCM)...............................1347
25.3.17 Flash Timing register 2 for Chip Select n - NAND Flash NVDDR Mode (IFC_FTIM2_CSn_NAND).... 1348
25.3.18 Flash Timing register 2 for Chip Select n - NAND Flash Asynchronous Mode
(IFC_FTIM2_CSn_NAND_ASYNC_MODE)........................................................................................... 1348
25.3.19 Flash Timing register 2 for CSn - NOR Flash Mode (IFC_FTIM2_CSn_NOR)........................................ 1349
25.3.20 Flash Timing register 2 for CSn - Normal GPCM Mode (IFC_FTIM2_CSn_GPCM)...............................1351
25.3.21 Flash Timing register 3 for Chip Select n - NAND Flash Mode (IFC_FTIM3_CSn_NAND)................... 1352
25.3.22 Flash Timing register 3 for Chip Select n - NAND Flash Asynchronous Mode
(IFC_IFC_FTIMn3_CS_NAND_ASYNC_MODE)................................................................................... 1352
25.3.23 Flash Timing register 3 for CSn - NOR Flash Mode (IFC_FTIM3_CS_NOR).......................................... 1353
25.3.24 Flash Timing register 3 for CSn - Normal GPCM Mode (IFC_FTIM3_CSn_GPCM)...............................1353
25.3.25 Ready Busy Status for each Chip Select (IFC_RB_STAT).........................................................................1354
25.3.26 General Control register (IFC_GCR)...........................................................................................................1356
25.3.27 Common Event and Error Status register (IFC_CM_EVTER_STAT)....................................................... 1357
25.3.28 Common Event and Error Enable register (IFC_CM_EVTER_EN)...........................................................1358
25.3.29 Common Event and Error Interrupt Enable register (IFC_CM_EVTER_INTR_EN)................................ 1359
25.3.30 Common Transfer Error Attributes register 0 (IFC_CM_ERATTR0)........................................................ 1359
25.3.31 Common Transfer Error Attributes register 1 (IFC_CM_ERATTR1)........................................................ 1361
25.3.32 Clock Control register (IFC_CCR).............................................................................................................. 1361
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 65
Section number Title Page
25.3.33 Clock Status register (IFC_CSR)................................................................................................................. 1363
25.3.34 DDR Clock Control register (IFC_DDR_CCR).......................................................................................... 1364
25.3.35 NAND Configuration register (IFC_NCFGR)............................................................................................ 1366
25.3.36 NAND Flash Command register 0 (IFC_NAND_FCR0)............................................................................1368
25.3.37 NAND Flash Command register 1 (IFC_NAND_FCR1)............................................................................1369
25.3.38 Flash Row Address register n (IFC_ROWn)............................................................................................... 1369
25.3.39 Flash COL Address register n (IFC_COLn)................................................................................................ 1370
25.3.40 Flash COL Address register for 2 KB Large-Page Device (IFC_COLn_2KB)...........................................1371
25.3.41 Flash COL Address register for 4 KB Large-Page Device (IFC_COLn_4KB)...........................................1372
25.3.42 Flash COL Address register for 8 KB Large-Page Device (IFC_COLn_8KB)...........................................1373
25.3.43 Flash Byte Count register for NAND Flash (IFC_NAND_BC).................................................................. 1374
25.3.44 NAND Flash Instruction register 0 (IFC_NAND_FIR0)............................................................................ 1375
25.3.45 NAND Flash Instruction register 1 (IFC_NAND_FIR1)............................................................................ 1377
25.3.46 NAND Flash Instruction register 2 (IFC_NAND_FIR2)............................................................................ 1378
25.3.47 NAND Chip-Select register (IFC_NAND_CSEL)...................................................................................... 1379
25.3.48 NAND Operation Sequence Start (IFC_NANDSEQ_STRT)..................................................................... 1379
25.3.49 NAND Event and Error Status register (IFC_NAND_EVTER_STAT)..................................................... 1381
25.3.50 NAND Page Read Completion Event Status register (IFC_PGRDCMPL_EVT_STAT)........................... 1383
25.3.51 NAND Event and Error Enable register (IFC_NAND_EVTER_EN).........................................................1385
25.3.52 NAND Event and Error Interrupt Enable register (IFC_NAND_EVTER_INTR_EN)...............................1387
25.3.53 NAND Transfer Error Attributes register 0 (IFC_NAND_ERATTR0)...................................................... 1388
25.3.54 NAND Transfer Error Attributes register 1 (IFC_NAND_ERATTR1)...................................................... 1389
25.3.55 NAND Flash Status register (IFC_NAND_FSR)........................................................................................ 1390
25.3.56 ECC Status and Result of Flash Operation register 0 (IFC_ECCSTAT0).................................................. 1390
25.3.57 ECC Status and Result of Flash Operation register 1 (IFC_ECCSTAT1).................................................. 1392
25.3.58 ECC Status and Result of Flash Operation register 2 (IFC_ECCSTAT2).................................................. 1393
25.3.59 ECC Status and Result of Flash Operation register 3 (IFC_ECCSTAT3).................................................. 1394
25.3.60 NAND Control register (IFC_NANDCR)................................................................................................... 1395
25.3.61 NAND Autoboot Trigger register (IFC_NAND_AUTOBOOT_TRGR).................................................... 1395
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
66 NXP Semiconductors
Section number Title Page
25.3.62 NAND Flash Memory Data register (IFC_NAND_MDR)..........................................................................1397
25.3.63 Nand DLL Low Config 0 Register (IFC_NAND_DLL_LOW_CFG0)...................................................... 1398
25.3.64 Nand DLL Low Config 1 Register (IFC_NAND_DLL_LOW_CFG1)...................................................... 1399
25.3.65 NAND DLL Low Status Register (IFC_NAND_DLL_LOW_STAT)........................................................1401
25.3.66 NOR Event and Error Status register (IFC_NOR_EVTER_STAT)............................................................1402
25.3.67 NOR Event and Error Enable register (IFC_NOR_EVTER_EN)............................................................... 1404
25.3.68 NOR Event and Error Interrupt enable register (IFC_NOR_EVTER_INTR_EN)..................................... 1406
25.3.69 NOR Transfer Error Attributes register 0 (IFC_NOR_ERATTR0)............................................................ 1407
25.3.70 NOR Transfer Error Attribute register 1 (IFC_NOR_ERATTR1).............................................................. 1408
25.3.71 NOR Transfer Error Attribute register 2 (IFC_NOR_ERATTR2).............................................................. 1409
25.3.72 NOR Control register (IFC_NORCR)......................................................................................................... 1409
25.3.73 GPCM Event and Error Status register (IFC_GPCM_EVTER_STAT)...................................................... 1411
25.3.74 GPCM Event and Error Enable register (IFC_GPCM_EVTER_EN)......................................................... 1413
25.3.75 GPCM Event and Error Interrupt enable register (IFC_GPCM_EVTER_INTR_EN)................................1414
25.3.76 GPCM Transfer Error Attributes register 0 (IFC_GPCM_ERATTR0).......................................................1416
25.3.77 GPCM Transfer Error Attributes register 1 (IFC_GPCM_ERATTR1).......................................................1417
25.3.78 GPCM Transfer Error Attributes register 2 (IFC_GPCM_ERATTR2).......................................................1418
25.3.79 GPCM Status register (IFC_GPCM_STAT)............................................................................................... 1420
25.4 IFC functional description............................................................................................................................................ 1421
25.4.1 General architecture..................................................................................................................................... 1423
25.4.1.1 Bank selection through address decoding................................................................................ 1423
25.4.1.2 Address/Data pin muxing for external address latch............................................................... 1423
25.4.1.2.1 Mode 0 pin muxing (CSORn[ADM_SHFT_MODE] = 0) ................................ 1424
25.4.1.2.2 Mode 1 pin muxing (CSORn[ADM_SHFT_MODE] = 1)................................. 1426
25.4.2 Programming model for flash interface timing ...........................................................................................1431
25.4.3 Booting methods.......................................................................................................................................... 1431
25.4.4 Software reset handling................................................................................................................................1431
25.4.4.1 System bus handling................................................................................................................ 1432
25.4.4.2 Flash interface handling........................................................................................................... 1432
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 67
Section number Title Page
25.4.5 Data buffer control (BCTL)......................................................................................................................... 1432
25.4.6 External transceiver enable (TE)..................................................................................................................1434
25.4.6.1 Transceiver enable during boot................................................................................................1434
25.4.6.2 Transceiver enable post-boot................................................................................................... 1435
25.4.6.3 Transceiver enable example.....................................................................................................1436
25.5 NAND flash control machine....................................................................................................................................... 1436
25.5.1 NAND flash synchronous mode.................................................................................................................. 1436
25.5.2 NAND flash asynchronous mode................................................................................................................ 1437
25.5.3 NV-DDR Mode............................................................................................................................................1437
25.5.4 Write protect................................................................................................................................................ 1437
25.5.5 SRAM buffer................................................................................................................................................1439
25.5.5.1 Guidelines for SRAM buffer for NAND access...................................................................... 1439
25.5.5.2 Buffer layout and page mapping for 512-byte page NAND flash........................................... 1440
25.5.5.3 Buffer layout and page mapping for 2-KB page NAND flash.................................................1441
25.5.5.4 Buffer layout and page mapping for 4 KB page NAND flash.................................................1442
25.5.5.5 Buffer layout and page mapping for 8 KB page NAND flash.................................................1443
25.5.5.6 SRAM buffer initialization requirement.................................................................................. 1444
25.5.6 Use of ECC algorithms................................................................................................................................ 1444
25.5.6.1 Generating Galois field elements............................................................................................. 1444
25.5.6.2 BCH encoding..........................................................................................................................1445
25.5.7 Programming the NAND FCM....................................................................................................................1452
25.5.7.1 FCM command instructions.....................................................................................................1453
25.5.7.2 FCM address instructions.........................................................................................................1454
25.5.7.3 FCM data read instructions...................................................................................................... 1454
25.5.7.4 FCM data write instructions.....................................................................................................1456
25.5.8 Looping FIR sequences................................................................................................................................1456
25.5.9 NAND DLL................................................................................................................................................. 1456
25.5.10 NAND asynchronous mode timings............................................................................................................ 1457
25.5.10.1 NAND asynchronous mode program data timing....................................................................1458
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
68 NXP Semiconductors
Section number Title Page
25.5.10.2 NAND asynchronous mode read data timing.......................................................................... 1458
25.5.10.3 NAND asynchronous mode calculating read data window width........................................... 1459
25.5.10.4 NAND asynchronous mode read data sampling approach...................................................... 1460
25.5.10.5 NAND asynchronous mode read status timing........................................................................1460
25.5.11 NV-DDR mode timings............................................................................................................................... 1461
25.5.11.1 NAND synchronous mode program operation........................................................................ 1461
25.5.11.2 NAND synchronous mode program with clock stopped......................................................... 1462
25.5.11.3 NAND synchronous page read operation................................................................................ 1463
25.6 NOR flash control machine.......................................................................................................................................... 1463
25.6.1 NOR boot..................................................................................................................................................... 1463
25.6.2 Unmuxed (parallel) asynchronous NOR read timings................................................................................. 1463
25.6.3 Simple asynchronous NOR write timings....................................................................................................1464
25.6.4 Muxed (ADM) asynchronous NOR read timings........................................................................................ 1465
25.6.5 Muxed (ADM) asynchronous NOR write timings.......................................................................................1466
25.7 General purpose chip-select machine (GPCM)............................................................................................................ 1467
25.7.1 Normal GPCM mode of operation...............................................................................................................1467
25.7.1.1 Normal GPCM program operation.......................................................................................... 1467
25.7.1.1.1 Normal GPCM internal counter-based program operation.................................1467
25.7.1.1.2 Normal GPCM external termination-based program operation..........................1471
25.7.1.2 Normal GPCM read operation................................................................................................. 1472
25.7.1.2.1 Normal GPCM internal counter-based read operation....................................... 1473
25.7.1.2.2 Normal GPCM external termination-based read operation................................ 1477
25.7.2 Generic ASIC mode of operation.................................................................................................................1479
25.7.2.1 General ASIC program operation............................................................................................ 1480
25.7.2.2 Generic ASIC read data sampling............................................................................................1481
25.8 Clock generation module.............................................................................................................................................. 1483
25.9 Initialization/Application information.......................................................................................................................... 1483
25.9.1 Switching Interfaces in ONFi NAND.......................................................................................................... 1483
25.9.1.1 Activating the NVDDR Interface............................................................................................ 1483
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 69
Section number Title Page
25.9.1.2 Switching to the asynchronous interface................................................................................. 1484
25.9.1.3 Switching timing modes when configured in NVDDR mode................................................. 1485
25.9.2 ONFI mode timing parameters.................................................................................................................... 1486
25.9.3 DLL configuration guideline (valid when IFC is in NVDDR Mode)..........................................................1486
25.9.4 IFC flash connections...................................................................................................................................1487
25.9.4.1 NAND flash connections......................................................................................................... 1487
25.9.4.1.1 Switching to the synchronous interface.............................................................. 1488
25.9.4.1.2 Switching to the asynchronous interface............................................................ 1489
25.9.4.2 NOR flash connections............................................................................................................ 1490
25.9.5 Bus turnaround............................................................................................................................................. 1491
25.9.5.1 Address phase after previous read........................................................................................... 1491
25.9.5.2 Read-data phase after address phase........................................................................................ 1492
25.9.5.3 Read-modify-write cycle for parity protected memory banks................................................. 1492
25.9.6 Interfacing to different port sizes................................................................................................................. 1492
25.9.7 Command sequence examples for NAND flash EEPROM......................................................................... 1493
25.9.7.1 NAND flash soft reset command sequence example...............................................................1494
25.9.7.2 NAND flash read status command sequence example............................................................ 1494
25.9.7.3 NAND flash read identification command sequence example................................................ 1495
25.9.7.4 NAND flash page read command sequence example.............................................................. 1495
25.9.7.5 NAND flash program command sequence example................................................................1496
25.9.7.6 Read status command during busy period of program/erase operation................................... 1497
25.9.7.7 Valid opcode transitions in the IFC......................................................................................... 1498
Chapter 26
Inter-Integrated Circuit (I2C)
26.1 The I2C module as implemented on the chip............................................................................................................... 1499
26.1.1 LS1043A I2C module integration................................................................................................................1499
26.1.2 LS1043A I2C module special consideration............................................................................................... 1499
26.2 Overview.......................................................................................................................................................................1500
26.3 Introduction to I2C........................................................................................................................................................1500
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
70 NXP Semiconductors
Section number Title Page
26.3.1 Definition: I2C module................................................................................................................................ 1501
26.3.2 Advantages of the I2C bus........................................................................................................................... 1501
26.3.3 Module block diagram................................................................................................................................. 1501
26.3.4 Features........................................................................................................................................................ 1502
26.3.5 Modes of operation...................................................................................................................................... 1503
26.3.6 Definition: I2C conditions........................................................................................................................... 1504
26.4 External signal descriptions.......................................................................................................................................... 1505
26.4.1 Signal overview............................................................................................................................................1505
26.4.2 Detailed external signal descriptions........................................................................................................... 1505
26.5 Memory map and register definition.............................................................................................................................1505
26.5.1 Register accessibility....................................................................................................................................1506
26.5.2 Register figure conventions......................................................................................................................... 1506
26.5.3 I2C Bus Address Register (I2Cx_IBAD).....................................................................................................1507
26.5.4 I2C Bus Frequency Divider Register (I2Cx_IBFD).................................................................................... 1508
26.5.5 I2C Bus Control Register (I2Cx_IBCR)...................................................................................................... 1508
26.5.6 I2C Bus Status Register (I2Cx_IBSR)......................................................................................................... 1510
26.5.7 I2C Bus Data I/O Register (I2Cx_IBDR).................................................................................................... 1511
26.5.8 I2C Bus Interrupt Config Register (I2Cx_IBIC)..........................................................................................1512
26.6 Functional description...................................................................................................................................................1513
26.6.1 Notes about module operation..................................................................................................................... 1513
26.6.2 Transactions................................................................................................................................................. 1513
26.6.2.1 Protocol overview.................................................................................................................... 1514
26.6.2.2 Transaction protocol definitions.............................................................................................. 1514
26.6.2.3 I2C calling address requirements............................................................................................. 1515
26.6.2.4 High-level protocol steps......................................................................................................... 1515
26.6.2.5 START condition..................................................................................................................... 1516
26.6.2.6 Slave address transmission.......................................................................................................1516
26.6.2.7 Data transmission..................................................................................................................... 1516
26.6.2.8 STOP condition........................................................................................................................1517
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 71
Section number Title Page
26.6.2.9 Repeated START condition..................................................................................................... 1517
26.6.3 Arbitration procedure................................................................................................................................... 1517
26.6.4 Clock behavior............................................................................................................................................. 1518
26.6.4.1 Clock synchronization..............................................................................................................1518
26.6.4.2 Clock stretching....................................................................................................................... 1519
26.6.4.3 Handshaking.............................................................................................................................1519
26.6.4.4 Clock rate and IBFD settings................................................................................................... 1519
26.6.4.4.1 Timing definitions...............................................................................................1519
26.6.4.4.2 Divider and hold values...................................................................................... 1520
26.6.5 Interrupts...................................................................................................................................................... 1525
26.6.5.1 Interrupt vector.........................................................................................................................1526
26.6.5.2 Interrupt description................................................................................................................. 1526
26.6.6 STOP mode.................................................................................................................................................. 1526
26.6.7 DMA interface............................................................................................................................................. 1527
26.7 Initialization/application information........................................................................................................................... 1528
26.7.1 Recommended interrupt service flow.......................................................................................................... 1528
26.7.2 General programming guidelines (for both master and slave mode)...........................................................1529
26.7.2.1 Initializing the I2C module...................................................................................................... 1530
26.7.2.2 Software response after a transfer............................................................................................ 1530
26.7.3 Programming guidelines specific to master mode....................................................................................... 1531
26.7.3.1 Generating START.................................................................................................................. 1531
26.7.3.2 Transmit/receive sequence....................................................................................................... 1532
26.7.3.3 Generating STOP..................................................................................................................... 1534
26.7.3.4 Generating repeated START....................................................................................................1534
26.7.3.5 Loss of arbitration.................................................................................................................... 1535
26.7.4 Programming guidelines specific to slave mode..........................................................................................1535
26.7.5 DMA application information......................................................................................................................1535
26.7.5.1 DMA mode, master transmit....................................................................................................1536
26.7.5.2 DMA mode, master reception.................................................................................................. 1537
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
72 NXP Semiconductors
Section number Title Page
26.7.5.3 Exiting DMA mode, system requirement considerations........................................................ 1539
Chapter 27
Low Power Universal asynchronous receiver/transmitter (LPUART)
27.1 LPUART module integration........................................................................................................................................1543
27.2 Chip LPUART signals.................................................................................................................................................. 1544
27.3 Chip LPUART module special consideration...............................................................................................................1544
27.4 Introduction...................................................................................................................................................................1545
27.4.1 Features........................................................................................................................................................ 1545
27.4.2 Modes of operation...................................................................................................................................... 1546
27.4.2.1 Stop mode................................................................................................................................ 1546
27.4.2.2 Wait mode................................................................................................................................ 1546
27.4.3 Signal Descriptions...................................................................................................................................... 1546
27.4.4 Block diagram.............................................................................................................................................. 1546
27.5 Register definition.........................................................................................................................................................1548
27.5.1 LPUART Baud Rate Register (LPUARTx_BAUD)....................................................................................1550
27.5.2 LPUART Status Register (LPUARTx_STAT)............................................................................................ 1552
27.5.3 LPUART Control Register (LPUARTx_CTRL)......................................................................................... 1556
27.5.4 LPUART Data Register (LPUARTx_DATA)............................................................................................. 1560
27.5.5 LPUART Match Address Register (LPUARTx_MATCH)......................................................................... 1561
27.5.6 LPUART Modem IrDA Register (LPUARTx_MODIR).............................................................................1562
27.5.7 LPUART FIFO Register (LPUARTx_FIFO).............................................................................................. 1564
27.5.8 LPUART Watermark Register (LPUARTx_WATER)................................................................................1566
27.6 Functional description...................................................................................................................................................1567
27.6.1 Baud rate generation.................................................................................................................................... 1567
27.6.2 Transmitter functional description............................................................................................................... 1568
27.6.2.1 Send break and queued idle..................................................................................................... 1569
27.6.2.2 Hardware flow control............................................................................................................. 1570
27.6.2.3 Transceiver driver enable.........................................................................................................1570
27.6.2.4 Transceiver driver enable using LPUART_RTS..................................................................... 1571
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 73
Section number Title Page
27.6.3 Receiver functional description................................................................................................................... 1571
27.6.3.1 Data sampling technique.......................................................................................................... 1572
27.6.3.2 Receiver wakeup operation...................................................................................................... 1573
27.6.3.2.1 Idle-line wakeup..................................................................................................1574
27.6.3.2.2 Address-mark wakeup........................................................................................ 1574
27.6.3.2.3 Address Match operation.................................................................................... 1574
27.6.3.3 Hardware flow control............................................................................................................. 1575
27.6.3.4 Infrared decoder....................................................................................................................... 1575
27.6.3.4.1 Start bit detection................................................................................................ 1576
27.6.3.4.2 Noise filtering..................................................................................................... 1576
27.6.3.4.3 Low-bit detection................................................................................................ 1576
27.6.3.4.4 High-bit detection............................................................................................... 1576
27.6.4 Additional LPUART functions.................................................................................................................... 1576
27.6.4.1 8-bit, 9-bit and 10-bit data modes............................................................................................ 1576
27.6.4.2 Idle length................................................................................................................................ 1577
27.6.4.3 Loop mode............................................................................................................................... 1577
27.6.4.4 Single-wire operation............................................................................................................... 1578
27.6.5 Infrared interface..........................................................................................................................................1578
27.6.5.1 Infrared transmit encoder......................................................................................................... 1579
27.6.5.2 Infrared receive decoder...........................................................................................................1579
27.6.6 Interrupts and status flags............................................................................................................................ 1579
27.7 LPUART changes......................................................................................................................................................... 1580
Chapter 28
PCI Express Interface Controller
28.1 The PCI Express controller as implemented on the chip..............................................................................................1581
28.1.1 PCI Express MSI implementation................................................................................................................1581
28.1.2 PCI Express soft reset support..................................................................................................................... 1583
28.1.3 PCI Express PM turnoff message support................................................................................................... 1583
28.1.4 Additional PCI Express events connected to GIC-400 interrupt................................................................. 1583
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
74 NXP Semiconductors
Section number Title Page
28.2 Introduction...................................................................................................................................................................1584
28.2.1 Overview...................................................................................................................................................... 1584
28.2.1.1 Outbound Transactions............................................................................................................ 1586
28.2.1.2 Inbound Transactions............................................................................................................... 1586
28.2.2 Features........................................................................................................................................................ 1587
28.2.3 Modes of Operation..................................................................................................................................... 1587
28.2.3.1 Link Width............................................................................................................................... 1588
28.2.3.2 Link Speed............................................................................................................................... 1588
28.3 External Signal Descriptions.........................................................................................................................................1588
28.4 Memory map/register overview....................................................................................................................................1589
28.4.1 PCI Express configuration registers.............................................................................................................1589
28.4.2 PEX register descriptions.............................................................................................................................1590
28.4.2.1 PCI_Express_Configuration_Registers Memory map.............................................................1590
28.4.2.2 PCI Express Vendor ID Register (Vendor_ID_Register)........................................................ 1593
28.4.2.2.1 Offset...................................................................................................................1593
28.4.2.2.2 Function.............................................................................................................. 1593
28.4.2.2.3 Diagram...............................................................................................................1594
28.4.2.2.4 Fields...................................................................................................................1594
28.4.2.3 PCI Express Device ID Register (Device_ID_Register)......................................................... 1594
28.4.2.3.1 Offset...................................................................................................................1594
28.4.2.3.2 Function.............................................................................................................. 1594
28.4.2.3.3 Diagram...............................................................................................................1594
28.4.2.3.4 Fields...................................................................................................................1595
28.4.2.4 PCI Express Command Register (Command_Register).......................................................... 1595
28.4.2.4.1 Offset...................................................................................................................1595
28.4.2.4.2 Function.............................................................................................................. 1595
28.4.2.4.3 Diagram...............................................................................................................1595
28.4.2.4.4 Fields...................................................................................................................1596
28.4.2.5 PCI Express Status Register (Status_Register)........................................................................ 1597
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 75
Section number Title Page
28.4.2.5.1 Offset...................................................................................................................1597
28.4.2.5.2 Function.............................................................................................................. 1597
28.4.2.5.3 Diagram...............................................................................................................1597
28.4.2.5.4 Fields...................................................................................................................1598
28.4.2.6 PCI Express Revision ID Register (Revision_ID_Register)....................................................1599
28.4.2.6.1 Offset...................................................................................................................1599
28.4.2.6.2 Function.............................................................................................................. 1599
28.4.2.6.3 Diagram...............................................................................................................1599
28.4.2.6.4 Fields...................................................................................................................1600
28.4.2.7 PCI Express Class Code Register (Class_Code_Register)...................................................... 1600
28.4.2.7.1 Offset...................................................................................................................1600
28.4.2.7.2 Function.............................................................................................................. 1600
28.4.2.7.3 Diagram...............................................................................................................1600
28.4.2.7.4 Fields...................................................................................................................1600
28.4.2.8 PCI Express Cache Line Size Register (Cache_Line_Size_Register)..................................... 1601
28.4.2.8.1 Offset...................................................................................................................1601
28.4.2.8.2 Function.............................................................................................................. 1601
28.4.2.8.3 Diagram...............................................................................................................1601
28.4.2.8.4 Fields...................................................................................................................1601
28.4.2.9 PCI Express Latency Timer Register (Latency_Timer_Register)........................................... 1602
28.4.2.9.1 Offset...................................................................................................................1602
28.4.2.9.2 Function.............................................................................................................. 1602
28.4.2.9.3 Diagram...............................................................................................................1602
28.4.2.9.4 Fields...................................................................................................................1602
28.4.2.10 PCI Express Header Type Register (Header_Type_Register)................................................. 1602
28.4.2.10.1 Offset...................................................................................................................1602
28.4.2.10.2 Function.............................................................................................................. 1603
28.4.2.10.3 Diagram...............................................................................................................1603
28.4.2.10.4 Fields...................................................................................................................1603
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
76 NXP Semiconductors
Section number Title Page
28.4.2.11 PCI Express Base Address Register 0 (BAR0)........................................................................1603
28.4.2.11.1 Offset...................................................................................................................1603
28.4.2.11.2 Function.............................................................................................................. 1604
28.4.2.11.3 Diagram...............................................................................................................1604
28.4.2.11.4 Fields...................................................................................................................1604
28.4.2.12 PCI Express Primary Bus Number Register (Primary_Bus_Number_Register)..................... 1605
28.4.2.12.1 Offset...................................................................................................................1605
28.4.2.12.2 Function.............................................................................................................. 1605
28.4.2.12.3 Diagram...............................................................................................................1605
28.4.2.12.4 Fields...................................................................................................................1605
28.4.2.13 PCI Express Secondary Bus Number Register (Secondary_Bus_Number_Register)............. 1605
28.4.2.13.1 Offset...................................................................................................................1605
28.4.2.13.2 Function.............................................................................................................. 1606
28.4.2.13.3 Diagram...............................................................................................................1606
28.4.2.13.4 Fields...................................................................................................................1606
28.4.2.14 PCI Express Subordinate Bus Number Register (Subordinate_Bus_Number_Register)........ 1606
28.4.2.14.1 Offset...................................................................................................................1606
28.4.2.14.2 Function.............................................................................................................. 1606
28.4.2.14.3 Diagram...............................................................................................................1606
28.4.2.14.4 Fields...................................................................................................................1607
28.4.2.15 PCI Express I/O Base Register (IO_Base_Register)............................................................... 1607
28.4.2.15.1 Offset...................................................................................................................1607
28.4.2.15.2 Function.............................................................................................................. 1607
28.4.2.15.3 Diagram...............................................................................................................1607
28.4.2.15.4 Fields...................................................................................................................1607
28.4.2.16 PCI Express I/O Limit Register (IO_Limit_Register)............................................................. 1608
28.4.2.16.1 Offset...................................................................................................................1608
28.4.2.16.2 Function.............................................................................................................. 1608
28.4.2.16.3 Diagram...............................................................................................................1608
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 77
Section number Title Page
28.4.2.16.4 Fields...................................................................................................................1609
28.4.2.17 PCI Express Secondary Status Register (Secondary_Status_Register)................................... 1609
28.4.2.17.1 Offset...................................................................................................................1609
28.4.2.17.2 Function.............................................................................................................. 1609
28.4.2.17.3 Diagram...............................................................................................................1609
28.4.2.17.4 Fields...................................................................................................................1609
28.4.2.18 PCI Express Memory Base Register (Memory_Base_Register)............................................. 1610
28.4.2.18.1 Offset...................................................................................................................1610
28.4.2.18.2 Function.............................................................................................................. 1610
28.4.2.18.3 Diagram...............................................................................................................1610
28.4.2.18.4 Fields...................................................................................................................1611
28.4.2.19 PCI Express Memory Limit Register (Memory_Limit_Register)........................................... 1611
28.4.2.19.1 Offset...................................................................................................................1611
28.4.2.19.2 Function.............................................................................................................. 1611
28.4.2.19.3 Diagram...............................................................................................................1611
28.4.2.19.4 Fields...................................................................................................................1612
28.4.2.20 PCI Express Prefetchable Memory Base Register (Prefetchable_Memory_Base_Register).. 1612
28.4.2.20.1 Offset...................................................................................................................1612
28.4.2.20.2 Function.............................................................................................................. 1612
28.4.2.20.3 Diagram...............................................................................................................1612
28.4.2.20.4 Fields...................................................................................................................1613
28.4.2.21 PCI Express Prefetchable Memory Limit Register (Prefetchable_Memory_Limit_Register) 1613
28.4.2.21.1 Offset...................................................................................................................1613
28.4.2.21.2 Function.............................................................................................................. 1613
28.4.2.21.3 Diagram...............................................................................................................1613
28.4.2.21.4 Fields...................................................................................................................1614
28.4.2.22 PCI Express Prefetchable Base Upper 32 Bits Register (Prefetchable_Base_Upper_32_B
its_Register)............................................................................................................................. 1614
28.4.2.22.1 Offset...................................................................................................................1614
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
78 NXP Semiconductors
Section number Title Page
28.4.2.22.2 Function.............................................................................................................. 1614
28.4.2.22.3 Diagram...............................................................................................................1614
28.4.2.22.4 Fields...................................................................................................................1614
28.4.2.23 PCI Express Prefetchable Limit Upper 32 Bits Register (Prefetchable_Limit_Upper_32_
Bits_Register)...........................................................................................................................1615
28.4.2.23.1 Offset...................................................................................................................1615
28.4.2.23.2 Function.............................................................................................................. 1615
28.4.2.23.3 Diagram...............................................................................................................1615
28.4.2.23.4 Fields...................................................................................................................1615
28.4.2.24 PCI Express I/O Base Upper 16 Bits Register (IO_Base_Upper_16_Bits_Register)............. 1616
28.4.2.24.1 Offset...................................................................................................................1616
28.4.2.24.2 Function.............................................................................................................. 1616
28.4.2.24.3 Diagram...............................................................................................................1616
28.4.2.24.4 Fields...................................................................................................................1616
28.4.2.25 PCI Express I/O Limit Upper 16 Bits Register (IO_Limit_Upper_16_Bits_Register)........... 1616
28.4.2.25.1 Offset...................................................................................................................1616
28.4.2.25.2 Function.............................................................................................................. 1617
28.4.2.25.3 Diagram...............................................................................................................1617
28.4.2.25.4 Fields...................................................................................................................1617
28.4.2.26 Capabilities Pointer Register (Capabilities_Pointer_Register)................................................ 1617
28.4.2.26.1 Offset...................................................................................................................1617
28.4.2.26.2 Function.............................................................................................................. 1617
28.4.2.26.3 Diagram...............................................................................................................1618
28.4.2.26.4 Fields...................................................................................................................1618
28.4.2.27 PCI Express Expansion ROM Base Address Register (RC-Mode) (Expansion_ROM_BA
R_Type1)................................................................................................................................. 1618
28.4.2.27.1 Offset...................................................................................................................1618
28.4.2.27.2 Function.............................................................................................................. 1618
28.4.2.27.3 Diagram...............................................................................................................1618
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 79
Section number Title Page
28.4.2.27.4 Fields...................................................................................................................1619
28.4.2.28 PCI Express Interrupt Line Register (Interrupt_Line_Register)..............................................1619
28.4.2.28.1 Offset...................................................................................................................1619
28.4.2.28.2 Function.............................................................................................................. 1619
28.4.2.28.3 Diagram...............................................................................................................1620
28.4.2.28.4 Fields...................................................................................................................1620
28.4.2.29 PCI Express Interrupt Pin Register (Interrupt_Pin_Register)..................................................1620
28.4.2.29.1 Offset...................................................................................................................1620
28.4.2.29.2 Function.............................................................................................................. 1620
28.4.2.29.3 Diagram...............................................................................................................1620
28.4.2.29.4 Fields...................................................................................................................1621
28.4.2.30 PCI Express Bridge Control Register (Bridge_Control_Register).......................................... 1621
28.4.2.30.1 Offset...................................................................................................................1621
28.4.2.30.2 Function.............................................................................................................. 1621
28.4.2.30.3 Diagram...............................................................................................................1621
28.4.2.30.4 Fields...................................................................................................................1621
28.4.2.31 PCI Express Power Management Capability ID Register (Power_Management_Capabil
ity_ID_Register).......................................................................................................................1622
28.4.2.31.1 Offset...................................................................................................................1622
28.4.2.31.2 Diagram...............................................................................................................1622
28.4.2.31.3 Fields...................................................................................................................1622
28.4.2.32 PCI Express Power Management Capabilities Register (Power_Management_Capabilities_
Register)................................................................................................................................... 1623
28.4.2.32.1 Offset...................................................................................................................1623
28.4.2.32.2 Diagram...............................................................................................................1623
28.4.2.32.3 Fields...................................................................................................................1623
28.4.2.33 PCI Express Power Management Status and Control Register (Power_Management_Sta
tus_and_Control_Register)...................................................................................................... 1624
28.4.2.33.1 Offset...................................................................................................................1624
28.4.2.33.2 Diagram...............................................................................................................1624
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
80 NXP Semiconductors
Section number Title Page
28.4.2.33.3 Fields...................................................................................................................1624
28.4.2.34 PCI Express Power Management Data Register (Power_Management_Data_Register)........ 1625
28.4.2.34.1 Offset...................................................................................................................1625
28.4.2.34.2 Diagram...............................................................................................................1625
28.4.2.34.3 Fields...................................................................................................................1625
28.4.2.35 PCI Express Capability ID Register (Capability_ID_Register)...............................................1625
28.4.2.35.1 Offset...................................................................................................................1625
28.4.2.35.2 Diagram...............................................................................................................1626
28.4.2.35.3 Fields...................................................................................................................1626
28.4.2.36 PCI Express Capabilities Register (Capabilities_Register)..................................................... 1626
28.4.2.36.1 Offset...................................................................................................................1626
28.4.2.36.2 Diagram...............................................................................................................1626
28.4.2.36.3 Fields...................................................................................................................1627
28.4.2.37 PCI Express Device Capabilities Register (Device_Capabilities_Register)............................1627
28.4.2.37.1 Offset...................................................................................................................1627
28.4.2.37.2 Diagram...............................................................................................................1628
28.4.2.37.3 Fields...................................................................................................................1628
28.4.2.38 PCI Express Device Control Register (Device_Control_Register)......................................... 1629
28.4.2.38.1 Offset...................................................................................................................1629
28.4.2.38.2 Diagram...............................................................................................................1629
28.4.2.38.3 Fields...................................................................................................................1629
28.4.2.39 PCI Express Device Status Register (Device_Status_Register).............................................. 1630
28.4.2.39.1 Offset...................................................................................................................1630
28.4.2.39.2 Diagram...............................................................................................................1630
28.4.2.39.3 Fields...................................................................................................................1631
28.4.2.40 PCI Express Link Capabilities Register (Link_Capabilities_Register)................................... 1631
28.4.2.40.1 Offset...................................................................................................................1631
28.4.2.40.2 Diagram...............................................................................................................1631
28.4.2.40.3 Fields...................................................................................................................1632
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 81
Section number Title Page
28.4.2.41 PCI Express Link Control Register (Link_Control_Register)................................................. 1633
28.4.2.41.1 Offset...................................................................................................................1633
28.4.2.41.2 Diagram...............................................................................................................1633
28.4.2.41.3 Fields...................................................................................................................1633
28.4.2.42 PCI Express Link Status Register (Link_Status_Register)......................................................1634
28.4.2.42.1 Offset...................................................................................................................1634
28.4.2.42.2 Diagram...............................................................................................................1634
28.4.2.42.3 Fields...................................................................................................................1635
28.4.2.43 PCI Express Slot Capabilities Register (Slot_Capabilities_Register)..................................... 1635
28.4.2.43.1 Offset...................................................................................................................1635
28.4.2.43.2 Function.............................................................................................................. 1636
28.4.2.43.3 Diagram...............................................................................................................1636
28.4.2.43.4 Fields...................................................................................................................1636
28.4.2.44 PCI Express Slot Control Register (Slot_Control_Register)................................................... 1637
28.4.2.44.1 Offset...................................................................................................................1637
28.4.2.44.2 Function.............................................................................................................. 1637
28.4.2.44.3 Diagram...............................................................................................................1637
28.4.2.44.4 Fields...................................................................................................................1638
28.4.2.45 PCI Express Slot Status Register (Slot_Status_Register)........................................................ 1638
28.4.2.45.1 Offset...................................................................................................................1639
28.4.2.45.2 Function.............................................................................................................. 1639
28.4.2.45.3 Diagram...............................................................................................................1639
28.4.2.45.4 Fields...................................................................................................................1639
28.4.2.46 PCI Express Root Control Register (Root_Control_Register)................................................ 1640
28.4.2.46.1 Offset...................................................................................................................1640
28.4.2.46.2 Function.............................................................................................................. 1640
28.4.2.46.3 Diagram...............................................................................................................1640
28.4.2.46.4 Fields...................................................................................................................1640
28.4.2.47 PCI Express Root Capabilities Register (Root_Capabilities_Register)...................................1641
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
82 NXP Semiconductors
Section number Title Page
28.4.2.47.1 Offset...................................................................................................................1641
28.4.2.47.2 Function.............................................................................................................. 1641
28.4.2.47.3 Diagram...............................................................................................................1641
28.4.2.47.4 Fields...................................................................................................................1641
28.4.2.48 PCI Express Root Status Register (Root_Status_Register)..................................................... 1642
28.4.2.48.1 Offset...................................................................................................................1642
28.4.2.48.2 Function.............................................................................................................. 1642
28.4.2.48.3 Diagram...............................................................................................................1642
28.4.2.48.4 Fields...................................................................................................................1642
28.4.2.49 PCI Express Device Capabilities 2 Register (Device_Capabilities_2_Register).....................1643
28.4.2.49.1 Offset...................................................................................................................1643
28.4.2.49.2 Diagram...............................................................................................................1643
28.4.2.49.3 Fields...................................................................................................................1643
28.4.2.50 PCI Express Device Control 2 Register (Device_Control_2_Register).................................. 1644
28.4.2.50.1 Offset...................................................................................................................1644
28.4.2.50.2 Diagram...............................................................................................................1644
28.4.2.50.3 Fields...................................................................................................................1644
28.4.2.51 PCI Express Link Capabilities 2 Register (Link_Capabilities_2_Register)............................ 1645
28.4.2.51.1 Offset...................................................................................................................1645
28.4.2.51.2 Function.............................................................................................................. 1645
28.4.2.51.3 Diagram...............................................................................................................1645
28.4.2.51.4 Fields...................................................................................................................1646
28.4.2.52 PCI Express Link Control 2 Register (Link_Control_2_Register).......................................... 1646
28.4.2.52.1 Offset...................................................................................................................1647
28.4.2.52.2 Diagram...............................................................................................................1647
28.4.2.52.3 Fields...................................................................................................................1647
28.4.2.53 PCI Express Link Status 2 Register (Link_Status_2_Register)...............................................1647
28.4.2.53.1 Offset...................................................................................................................1648
28.4.2.53.2 Diagram...............................................................................................................1648
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 83
Section number Title Page
28.4.2.53.3 Fields...................................................................................................................1648
28.4.2.54 PCI Express Advanced Error Reporting Capability ID Register (Advanced_Error_Repor
ting_Capability_ID_Register).................................................................................................. 1648
28.4.2.54.1 Offset...................................................................................................................1649
28.4.2.54.2 Diagram...............................................................................................................1649
28.4.2.54.3 Fields...................................................................................................................1649
28.4.2.55 PCI Express Uncorrectable Error Status Register (Uncorrectable_Error_Status_Register)....1649
28.4.2.55.1 Offset...................................................................................................................1649
28.4.2.55.2 Diagram...............................................................................................................1649
28.4.2.55.3 Fields...................................................................................................................1650
28.4.2.56 PCI Express Uncorrectable Error Mask Register (Uncorrectable_Error_Mask_Register)......1651
28.4.2.56.1 Offset...................................................................................................................1651
28.4.2.56.2 Diagram...............................................................................................................1651
28.4.2.56.3 Fields...................................................................................................................1651
28.4.2.57 PCI Express Uncorrectable Error Severity Register (Uncorrectable_Error_Severity_Reg
ister)......................................................................................................................................... 1652
28.4.2.57.1 Offset...................................................................................................................1652
28.4.2.57.2 Diagram...............................................................................................................1652
28.4.2.57.3 Fields...................................................................................................................1653
28.4.2.58 PCI Express Correctable Error Status Register (Correctable_Error_Status_Register)............1654
28.4.2.58.1 Offset...................................................................................................................1654
28.4.2.58.2 Diagram...............................................................................................................1654
28.4.2.58.3 Fields...................................................................................................................1654
28.4.2.59 PCI Express Correctable Error Mask Register (Correctable_Error_Mask_Register)..............1655
28.4.2.59.1 Offset...................................................................................................................1655
28.4.2.59.2 Diagram...............................................................................................................1655
28.4.2.59.3 Fields...................................................................................................................1655
28.4.2.60 PCI Express Advanced Error Capabilities and Control Register (Advanced_Error_Capab
ilities_and_Control_Register).................................................................................................. 1656
28.4.2.60.1 Offset...................................................................................................................1656
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
84 NXP Semiconductors
Section number Title Page
28.4.2.60.2 Diagram...............................................................................................................1656
28.4.2.60.3 Fields...................................................................................................................1657
28.4.2.61 PCI Express Header Log Register 1 (Header_Log_Register_DWORD1).............................. 1657
28.4.2.61.1 Offset...................................................................................................................1657
28.4.2.61.2 Function.............................................................................................................. 1658
28.4.2.61.3 Diagram...............................................................................................................1658
28.4.2.61.4 Fields...................................................................................................................1658
28.4.2.62 PCI Express Header Log Register 2 (Header_Log_Register_DWORD2).............................. 1658
28.4.2.62.1 Offset...................................................................................................................1658
28.4.2.62.2 Function.............................................................................................................. 1659
28.4.2.62.3 Diagram...............................................................................................................1659
28.4.2.62.4 Fields...................................................................................................................1659
28.4.2.63 PCI Express Header Log Register 3 (Header_Log_Register_DWORD3).............................. 1659
28.4.2.63.1 Offset...................................................................................................................1659
28.4.2.63.2 Function.............................................................................................................. 1660
28.4.2.63.3 Diagram...............................................................................................................1660
28.4.2.63.4 Fields...................................................................................................................1660
28.4.2.64 PCI Express Header Log Register 4 (Header_Log_Register_DWORD4).............................. 1660
28.4.2.64.1 Offset...................................................................................................................1660
28.4.2.64.2 Function.............................................................................................................. 1661
28.4.2.64.3 Diagram...............................................................................................................1661
28.4.2.64.4 Fields...................................................................................................................1661
28.4.2.65 PCI Express Root Error Command Register (Root_Error_Command_Register)....................1661
28.4.2.65.1 Offset...................................................................................................................1661
28.4.2.65.2 Function.............................................................................................................. 1662
28.4.2.65.3 Diagram...............................................................................................................1662
28.4.2.65.4 Fields...................................................................................................................1662
28.4.2.66 PCI Express Root Error Status Register (Root_Error_Status_Register)................................. 1662
28.4.2.66.1 Offset...................................................................................................................1663
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 85
Section number Title Page
28.4.2.66.2 Function.............................................................................................................. 1663
28.4.2.66.3 Diagram...............................................................................................................1663
28.4.2.66.4 Fields...................................................................................................................1663
28.4.2.67 PCI Express Correctable Error Source ID Register (Correctable_Error_Source_ID_Regi
ster)...........................................................................................................................................1664
28.4.2.67.1 Offset...................................................................................................................1664
28.4.2.67.2 Diagram...............................................................................................................1664
28.4.2.67.3 Fields...................................................................................................................1664
28.4.2.68 PCI Express Error Source ID Register (Error_Source_ID_Register)...................................... 1665
28.4.2.68.1 Offset...................................................................................................................1665
28.4.2.68.2 Diagram...............................................................................................................1665
28.4.2.68.3 Fields...................................................................................................................1665
28.4.2.69 Secondary PCI Express Extended Capability Header (SPCIE_CAP_HEADER_REG)......... 1665
28.4.2.69.1 Offset...................................................................................................................1665
28.4.2.69.2 Diagram...............................................................................................................1665
28.4.2.69.3 Fields...................................................................................................................1666
28.4.2.70 Link Control 3 Register (LINK_CONTROL3_REG)............................................................. 1666
28.4.2.70.1 Offset...................................................................................................................1666
28.4.2.70.2 Diagram...............................................................................................................1666
28.4.2.70.3 Fields...................................................................................................................1667
28.4.2.71 Lane Error Status Register (LANE_ERR_STATUS_REG).................................................... 1667
28.4.2.71.1 Offset...................................................................................................................1667
28.4.2.71.2 Diagram...............................................................................................................1667
28.4.2.71.3 Fields...................................................................................................................1668
28.4.2.72 Lane Equalization Control Register (LANE0_EQUALIZATION_CONTROL - LANE3_
EQUALIZATION_CONTROL)..............................................................................................1668
28.4.2.72.1 Offset...................................................................................................................1668
28.4.2.72.2 Diagram...............................................................................................................1670
28.4.2.72.3 Register reset values........................................................................................... 1670
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
86 NXP Semiconductors
Section number Title Page
28.4.2.72.4 Fields...................................................................................................................1670
28.4.2.73 Symbol Timer Register and Filter Mask 1 Register (SYMBOL_TIMER_FILTER_1_OFF).1671
28.4.2.73.1 Offset...................................................................................................................1671
28.4.2.73.2 Function.............................................................................................................. 1671
28.4.2.73.3 Diagram...............................................................................................................1671
28.4.2.73.4 Fields...................................................................................................................1672
28.4.2.74 DBI Read-only Write Enable Register (MISC_CONTROL_1_OFF)..................................... 1674
28.4.2.74.1 Offset...................................................................................................................1674
28.4.2.74.2 Diagram...............................................................................................................1674
28.4.2.74.3 Fields...................................................................................................................1675
28.4.2.75 Coherency Control Register 1 (COHERENCY_CONTROL_1_OFF)................................... 1675
28.4.2.75.1 Offset...................................................................................................................1675
28.4.2.75.2 Diagram...............................................................................................................1675
28.4.2.75.3 Fields...................................................................................................................1676
28.4.2.76 Coherency Control Register 2 (COHERENCY_CONTROL_2_OFF)................................... 1676
28.4.2.76.1 Offset...................................................................................................................1677
28.4.2.76.2 Diagram...............................................................................................................1677
28.4.2.76.3 Fields...................................................................................................................1677
28.4.2.77 Coherency Control Register 3 (COHERENCY_CONTROL_3_OFF)................................... 1677
28.4.2.77.1 Offset...................................................................................................................1677
28.4.2.77.2 Diagram...............................................................................................................1678
28.4.2.77.3 Fields...................................................................................................................1678
28.4.2.78 iATU Index Register (IATU_VIEWPORT_OFF)...................................................................1678
28.4.2.78.1 Offset...................................................................................................................1678
28.4.2.78.2 Function.............................................................................................................. 1678
28.4.2.78.3 Diagram...............................................................................................................1678
28.4.2.78.4 Fields...................................................................................................................1679
28.4.2.79 iATU Region Control 1 Register (IATU_REGION_CTRL_1_OFF_INBOUND_0)............. 1679
28.4.2.79.1 Offset...................................................................................................................1679
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 87
Section number Title Page
28.4.2.79.2 Diagram...............................................................................................................1679
28.4.2.79.3 Fields...................................................................................................................1680
28.4.2.80 iATU Region Control 1 Register (IATU_REGION_CTRL_1_OFF_OUTBOUND_0)......... 1680
28.4.2.80.1 Offset...................................................................................................................1681
28.4.2.80.2 Diagram...............................................................................................................1681
28.4.2.80.3 Fields...................................................................................................................1681
28.4.2.81 iATU Region Control 2 Register (IATU_REGION_CTRL_2_OFF_INBOUND_0)............. 1682
28.4.2.81.1 Offset...................................................................................................................1682
28.4.2.81.2 Diagram...............................................................................................................1682
28.4.2.81.3 Fields...................................................................................................................1682
28.4.2.82 iATU Region Control 2 Register (IATU_REGION_CTRL_2_OFF_OUTBOUND_0)......... 1684
28.4.2.82.1 Offset...................................................................................................................1684
28.4.2.82.2 Diagram...............................................................................................................1684
28.4.2.82.3 Fields...................................................................................................................1685
28.4.2.83 iATU Lower Base Address Register (IATU_LWR_BASE_ADDR_OFF_INBOUND_0).... 1686
28.4.2.83.1 Offset...................................................................................................................1686
28.4.2.83.2 Diagram...............................................................................................................1686
28.4.2.83.3 Fields...................................................................................................................1686
28.4.2.84 iATU Lower Base Address Register (IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0) 1686
28.4.2.84.1 Offset...................................................................................................................1686
28.4.2.84.2 Diagram...............................................................................................................1687
28.4.2.84.3 Fields...................................................................................................................1687
28.4.2.85 iATU Upper Base Address Register (IATU_UPPER_BASE_ADDR_OFF_INBOUND_0). 1687
28.4.2.85.1 Offset...................................................................................................................1687
28.4.2.85.2 Diagram...............................................................................................................1688
28.4.2.85.3 Fields...................................................................................................................1688
28.4.2.86 iATU Upper Base Address Register (IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_
0).............................................................................................................................................. 1688
28.4.2.86.1 Offset...................................................................................................................1688
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
88 NXP Semiconductors
Section number Title Page
28.4.2.86.2 Diagram...............................................................................................................1688
28.4.2.86.3 Fields...................................................................................................................1689
28.4.2.87 iATU Limit Address Register (IATU_LIMIT_ADDR_OFF_INBOUND_0).........................1689
28.4.2.87.1 Offset...................................................................................................................1689
28.4.2.87.2 Diagram...............................................................................................................1689
28.4.2.87.3 Fields...................................................................................................................1690
28.4.2.88 iATU Limit Address Register (IATU_LIMIT_ADDR_OFF_OUTBOUND_0).....................1690
28.4.2.88.1 Offset...................................................................................................................1690
28.4.2.88.2 Diagram...............................................................................................................1690
28.4.2.88.3 Fields...................................................................................................................1691
28.4.2.89 iATU Region#N Lower Offset Address Register (IATU_LWR_TARGET_ADDR_OFF_
INBOUND_0).......................................................................................................................... 1691
28.4.2.89.1 Offset...................................................................................................................1691
28.4.2.89.2 Diagram...............................................................................................................1691
28.4.2.89.3 Fields...................................................................................................................1692
28.4.2.90 iATU Outbound Region#N Lower Offset Address Register (IATU_LWR_TARGET_
ADDR_OFF_OUTBOUND_0)............................................................................................... 1692
28.4.2.90.1 Offset...................................................................................................................1692
28.4.2.90.2 Diagram...............................................................................................................1693
28.4.2.90.3 Fields...................................................................................................................1693
28.4.2.91 iATU Upper Target Address Register (IATU_UPPER_TARGET_ADDR_OFF_INBOU
ND_0).......................................................................................................................................1693
28.4.2.91.1 Offset...................................................................................................................1693
28.4.2.91.2 Diagram...............................................................................................................1693
28.4.2.91.3 Fields...................................................................................................................1694
28.4.2.92 iATU Upper Target Address Register (IATU_UPPER_TARGET_ADDR_OFF_OUTBO
UND_0)....................................................................................................................................1694
28.4.2.92.1 Offset...................................................................................................................1694
28.4.2.92.2 Diagram...............................................................................................................1694
28.4.2.92.3 Fields...................................................................................................................1695
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 89
Section number Title Page
28.4.2.93 Base Address Register 0 Mask (BAR0_MASK)..................................................................... 1695
28.4.2.93.1 Offset...................................................................................................................1695
28.4.2.93.2 Function.............................................................................................................. 1695
28.4.2.93.3 Diagram...............................................................................................................1696
28.4.2.93.4 Fields...................................................................................................................1696
28.4.2.94 Base Address Register 1 Mask (BAR1_MASK)..................................................................... 1696
28.4.2.94.1 Offset...................................................................................................................1696
28.4.2.94.2 Function.............................................................................................................. 1696
28.4.2.94.3 Diagram...............................................................................................................1697
28.4.2.94.4 Fields...................................................................................................................1697
28.4.2.95 Expansion ROM Base Address Register Mask (RC mode) (EXP_ROM_BAR_MASK_
RC)........................................................................................................................................... 1697
28.4.2.95.1 Offset...................................................................................................................1697
28.4.2.95.2 Function.............................................................................................................. 1697
28.4.2.95.3 Diagram...............................................................................................................1698
28.4.2.95.4 Fields...................................................................................................................1698
28.5 PEX_LUT memory map/registers overview................................................................................................................ 1698
28.5.1 PEX_LUT register descriptions................................................................................................................... 1699
28.5.1.1 PEX_LUT Memory map..........................................................................................................1699
28.5.1.2 PEX LUT Status Register (PEXLSR)......................................................................................1701
28.5.1.2.1 Offset...................................................................................................................1701
28.5.1.2.2 Function.............................................................................................................. 1701
28.5.1.2.3 Diagram...............................................................................................................1701
28.5.1.2.4 Fields...................................................................................................................1701
28.5.1.3 PEX LUT Control Register (PEXLCR)...................................................................................1702
28.5.1.3.1 Offset...................................................................................................................1702
28.5.1.3.2 Function.............................................................................................................. 1702
28.5.1.3.3 Diagram...............................................................................................................1702
28.5.1.3.4 Fields...................................................................................................................1703
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
90 NXP Semiconductors
Section number Title Page
28.5.1.4 PEX LUT Debug Register (PEXLDBG)................................................................................. 1703
28.5.1.4.1 Offset...................................................................................................................1703
28.5.1.4.2 Function.............................................................................................................. 1703
28.5.1.4.3 Diagram...............................................................................................................1704
28.5.1.4.4 Fields...................................................................................................................1704
28.5.1.5 PEX LUT Entry a Upper Data Register (PEXL0UDR)...........................................................1705
28.5.1.5.1 Offset...................................................................................................................1705
28.5.1.5.2 Function.............................................................................................................. 1705
28.5.1.5.3 Diagram...............................................................................................................1705
28.5.1.5.4 Fields...................................................................................................................1706
28.5.1.6 PEX LUT Entry a Lower Data Register (PEXL0LDR)...........................................................1706
28.5.1.6.1 Offset...................................................................................................................1706
28.5.1.6.2 Function.............................................................................................................. 1706
28.5.1.6.3 Diagram...............................................................................................................1706
28.5.1.6.4 Fields...................................................................................................................1707
28.5.1.7 PEX LUT Entry a Upper Data Register (PEXL1UDR - PEXL31UDR)................................. 1707
28.5.1.7.1 Offset...................................................................................................................1707
28.5.1.7.2 Function.............................................................................................................. 1708
28.5.1.7.3 Diagram...............................................................................................................1708
28.5.1.7.4 Fields...................................................................................................................1708
28.5.1.8 PEX LUT Entry a Lower Data Register (PEXL1LDR - PEXL31LDR)................................. 1708
28.5.1.8.1 Offset...................................................................................................................1708
28.5.1.8.2 Function.............................................................................................................. 1709
28.5.1.8.3 Diagram...............................................................................................................1709
28.5.1.8.4 Fields...................................................................................................................1709
28.6 Functional Description..................................................................................................................................................1710
28.6.1 Architecture..................................................................................................................................................1711
28.6.1.1 PCI Express Transactions........................................................................................................ 1711
28.6.1.2 Lane Reversal...........................................................................................................................1711
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 91
Section number Title Page
28.6.1.3 Transaction ordering rules....................................................................................................... 1712
28.6.1.4 Internal Address Translation Unit............................................................................................1714
28.6.1.4.1 iATU Overview.................................................................................................. 1714
28.6.1.4.2 Programming the iATU...................................................................................... 1715
28.6.1.4.3 Outbound iATU Operation................................................................................. 1716
28.6.1.4.3.1 Overview (Address Match Mode)................................................ 1716
28.6.1.4.3.2 RID BDF Number Replacement.................................................. 1718
28.6.1.4.3.3 CFG Handling.............................................................................. 1718
28.6.1.4.3.4 CFG Shift Feature.........................................................................1718
28.6.1.4.3.5 FMT Translation...........................................................................1719
28.6.1.4.3.6 No Address Match Result.............................................................1719
28.6.1.4.3.7 Writing to a MRdLk Region.........................................................1719
28.6.1.4.3.8 Outbound Programming Example................................................1719
28.6.1.4.4 Inbound iATU Operation....................................................................................1720
28.6.1.4.4.1 Overview...................................................................................... 1720
28.6.1.4.4.2 MEM Match Modes..................................................................... 1721
28.6.1.4.4.3 CFG Handling (Upstream Port)....................................................1723
28.6.1.4.4.4 FMT Translation...........................................................................1723
28.6.1.4.4.5 Inbound Programming Example...................................................1724
28.6.1.5 Memory Space Addressing...................................................................................................... 1725
28.6.1.6 I/O Space Addressing...............................................................................................................1725
28.6.1.7 Configuration Space Addressing............................................................................................. 1725
28.6.1.8 Messages.................................................................................................................................. 1726
28.6.1.8.1 Outbound Message Generation...........................................................................1726
28.6.1.8.2 Inbound Messages...............................................................................................1726
28.6.1.9 Error Handling......................................................................................................................... 1727
28.6.1.9.1 PCI Express Error Logging and Signaling..........................................................1727
28.6.2 Interrupts...................................................................................................................................................... 1729
28.6.3 Initial Credit Advertisement.........................................................................................................................1729
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
92 NXP Semiconductors
Section number Title Page
28.6.4 Power Management......................................................................................................................................1729
28.6.4.1 L2/L3 Ready Link State........................................................................................................... 1730
28.6.5 Hot Reset......................................................................................................................................................1730
28.7 Initialization/Application Information.......................................................................................................................... 1730
28.7.1 Configuring the chip for inbound CCSR accesses.......................................................................................1730
28.7.2 Poisoned TLP handling................................................................................................................................ 1731
Chapter 29
Pre-Boot Loader (PBL)
29.1 Overview.......................................................................................................................................................................1733
29.2 Features summary......................................................................................................................................................... 1734
29.3 Modes of operation....................................................................................................................................................... 1734
29.4 Functional description...................................................................................................................................................1735
29.4.1 Device configuration using reset configuration word (RCW)..................................................................... 1735
29.4.2 Device initialization by PBL........................................................................................................................1735
29.4.2.1 CCSR registers blocked from PBL during secure boot........................................................... 1736
29.4.3 Required format of data structure used by PBL...........................................................................................1737
29.4.4 RCW loading by PBL.................................................................................................................................. 1739
29.4.5 Pre-boot initialization command loading by PBL........................................................................................1740
29.4.6 Reserved address space used as internal PBL commands........................................................................... 1740
29.4.7 Error codes................................................................................................................................................... 1742
29.5 Initialization/Application information.......................................................................................................................... 1751
29.5.1 Starting addresses.........................................................................................................................................1751
29.5.2 Software restrictions.................................................................................................................................... 1751
29.5.3 Software recommendations..........................................................................................................................1752
Chapter 30
Quad Serial Peripheral Interface (QuadSPI)
30.1 The QuadSPI module as implemented on the chip.......................................................................................................1753
30.1.1 LS1043A QuadSPI signals...........................................................................................................................1753
30.1.2 QuadSPI register reset values...................................................................................................................... 1753
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 93
Section number Title Page
30.1.3 QuadSPI_MCR[SCLKCFG] mapping.........................................................................................................1754
30.1.4 QuadSPI boot initialization sequence.......................................................................................................... 1755
30.1.5 LS1043A QuadSPI module special consideration....................................................................................... 1755
30.2 Introduction...................................................................................................................................................................1756
30.2.1 Features........................................................................................................................................................ 1756
30.2.2 Block Diagram............................................................................................................................................. 1757
30.2.3 QuadSPI Modes of Operation...................................................................................................................... 1758
30.2.3.1 Normal Mode........................................................................................................................... 1758
30.2.3.2 Module Disable Mode..............................................................................................................1758
30.2.3.3 Stop Mode................................................................................................................................ 1758
30.2.4 Acronyms and Abbreviations.......................................................................................................................1758
30.2.5 Glossary for QuadSPI module..................................................................................................................... 1759
30.3 External Signal Description.......................................................................................................................................... 1760
30.3.1 Driving External Signals.............................................................................................................................. 1761
30.4 Memory Map and Register Definition..........................................................................................................................1763
30.4.1 Register Write Access.................................................................................................................................. 1763
30.4.2 Peripheral Bus Register Descriptions.......................................................................................................... 1764
30.4.2.1 Module Configuration Register (QuadSPI_MCR).................................................................. 1770
30.4.2.2 IP Configuration Register (QuadSPI_IPCR)........................................................................... 1772
30.4.2.3 Flash Configuration Register (QuadSPI_FLSHCR)................................................................ 1773
30.4.2.4 Buffer0 Configuration Register (QuadSPI_BUF0CR)............................................................ 1774
30.4.2.5 Buffer1 Configuration Register (QuadSPI_BUF1CR)............................................................ 1775
30.4.2.6 Buffer2 Configuration Register (QuadSPI_BUF2CR)............................................................ 1776
30.4.2.7 Buffer3 Configuration Register (QuadSPI_BUF3CR)............................................................ 1777
30.4.2.8 Buffer Generic Configuration Register (QuadSPI_BFGENCR)............................................. 1778
30.4.2.9 Buffer0 Top Index Register (QuadSPI_BUF0IND)................................................................ 1779
30.4.2.10 Buffer1 Top Index Register (QuadSPI_BUF1IND)................................................................ 1779
30.4.2.11 Buffer2 Top Index Register (QuadSPI_BUF2IND)................................................................ 1780
30.4.2.12 Serial Flash Address Register (QuadSPI_SFAR).................................................................... 1781
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
94 NXP Semiconductors
Section number Title Page
30.4.2.13 Sampling Register (QuadSPI_SMPR)..................................................................................... 1781
30.4.2.14 RX Buffer Status Register (QuadSPI_RBSR)......................................................................... 1783
30.4.2.15 RX Buffer Control Register (QuadSPI_RBCT).......................................................................1783
30.4.2.16 TX Buffer Status Register (QuadSPI_TBSR)..........................................................................1784
30.4.2.17 TX Buffer Data Register (QuadSPI_TBDR)........................................................................... 1785
30.4.2.18 Status Register (QuadSPI_SR).................................................................................................1786
30.4.2.19 Flag Register (QuadSPI_FR)................................................................................................... 1788
30.4.2.20 Interrupt and DMA Request Select and Enable Register (QuadSPI_RSER)...........................1791
30.4.2.21 Sequence Suspend Status Register (QuadSPI_SPNDST)........................................................1795
30.4.2.22 Sequence Pointer Clear Register (QuadSPI_SPTRCLR)........................................................ 1797
30.4.2.23 Serial Flash A1 Top Address (QuadSPI_SFA1AD)................................................................ 1798
30.4.2.24 Serial Flash A2 Top Address (QuadSPI_SFA2AD)................................................................ 1798
30.4.2.25 Serial Flash B1Top Address (QuadSPI_SFB1AD)................................................................. 1799
30.4.2.26 Serial Flash B2Top Address (QuadSPI_SFB2AD)................................................................. 1799
30.4.2.27 RX Buffer Data Register (QuadSPI_RBDRn).........................................................................1800
30.4.2.28 LUT Key Register (QuadSPI_LUTKEY)................................................................................1801
30.4.2.29 LUT Lock Configuration Register (QuadSPI_LCKCR)......................................................... 1801
30.4.2.30 Look-up Table register (QuadSPI_LUTn)............................................................................... 1802
30.4.3 Serial Flash Address Assignment................................................................................................................ 1803
30.4.4 AMBA Bus Register Memory Map............................................................................................................. 1804
30.4.5 AHB Bus Register Memory Map Descriptions........................................................................................... 1805
30.4.5.1 AHB Bus Access Considerations.............................................................................................1805
30.4.5.2 Memory Mapped Serial Flash Data - Individual Flash Mode on Flash A............................... 1806
30.4.5.3 Memory Mapped Serial Flash Data - Individual Flash Mode on Flash B............................... 1807
30.4.5.4 Parallel Flash Mode................................................................................................................. 1808
30.4.5.5 AHB RX Data Buffer (QSPI_ARDB0 to QSPI_ARDB31).................................................... 1809
30.4.5.5.1 AHB RX Data Buffer register (ARDBn)............................................................1809
30.5 Interrupt Signals............................................................................................................................................................1812
30.6 Functional Description..................................................................................................................................................1812
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 95
Section number Title Page
30.6.1 Serial Flash Access Schemes....................................................................................................................... 1812
30.6.2 Modes of Operation..................................................................................................................................... 1813
30.6.3 Normal Mode............................................................................................................................................... 1814
30.6.3.1 Programmable Sequence Engine............................................................................................. 1814
30.6.3.2 Flexible AHB buffers...............................................................................................................1816
30.6.3.3 Suspend-Abort Mechanism......................................................................................................1817
30.6.3.4 Look-up Table..........................................................................................................................1818
30.6.3.5 Issuing SFM Commands.......................................................................................................... 1819
30.6.3.6 Flash Programming.................................................................................................................. 1821
30.6.3.7 Flash Read................................................................................................................................1821
30.6.3.8 Byte Ordering of Serial Flash Read Data.................................................................................1826
30.6.3.9 Normal Mode Interrupt and DMA Requests............................................................................1829
30.6.3.10 TX Buffer Operation................................................................................................................ 1831
30.6.3.11 Address scheme........................................................................................................................1831
30.7 Initialization/Application Information.......................................................................................................................... 1832
30.7.1 Power Up and Reset..................................................................................................................................... 1832
30.7.2 Available Status/Flag Information............................................................................................................... 1832
30.7.2.1 IP Commands........................................................................................................................... 1833
30.7.2.2 AHB Commands...................................................................................................................... 1833
30.7.2.3 Overview of Error Flags.......................................................................................................... 1833
30.7.2.4 IP Bus and AHB Access Command Collisions....................................................................... 1835
30.7.3 Exclusive Access to Serial Flash for AHB Commands............................................................................... 1835
30.7.3.1 RX Buffer Read via QSPI_ARDB Registers........................................................................... 1835
30.7.3.2 RX Buffer Read via QSPI_RBDR Registers........................................................................... 1836
30.7.4 Command Arbitration ................................................................................................................................. 1836
30.7.5 Flash Device Selection.................................................................................................................................1837
30.7.6 DMA Usage................................................................................................................................................. 1837
30.7.6.1 DMA Usage in Normal Mode..................................................................................................1837
30.7.6.1.1 Bandwidth considerations...................................................................................1837
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
96 NXP Semiconductors
Section number Title Page
30.7.7 Parallel mode................................................................................................................................................1839
30.8 Byte Ordering - Endianness.......................................................................................................................................... 1841
30.8.1 Programming Flash Data............................................................................................................................. 1842
30.8.2 Reading Flash Data into the RX Buffer....................................................................................................... 1843
30.8.2.1 Readout of the RX Buffer via QSPI_RBDRn..........................................................................1843
30.8.2.2 Readout of the RX Buffer via ARDBn.................................................................................... 1843
30.8.3 Reading Flash Data into the AHB Buffer.................................................................................................... 1844
30.8.3.1 Readout of the AHB Buffer via Memory Mapped Read......................................................... 1844
30.9 Serial Flash Devices......................................................................................................................................................1844
30.9.1 Example Sequences......................................................................................................................................1844
30.9.1.1 Fast Read Sequence (Macronix/Numonyx/Spansion/Winbond)............................................. 1845
30.9.1.2 Fast Read Quad Output (Winbond)......................................................................................... 1845
30.9.1.3 4 x I/O Read Enhance Performance Mode (XIP) (Macronix)................................................. 1846
30.9.1.4 Dual Command Page Program (Numonyx)............................................................................. 1846
30.9.1.5 Sector Erase (Macronix/Spansion/Numonyx)......................................................................... 1847
30.9.1.6 Read Status Register (Macronix/Spansion/Numonyx/Winbond)............................................ 1847
30.9.2 Dual Die Flashes.......................................................................................................................................... 1847
30.9.3 Boot initialization sequence......................................................................................................................... 1848
30.9.4 Serial Flash Clock Frequency Limitations...................................................................................................1849
30.10 Sampling of Serial Flash Input Data.............................................................................................................................1849
30.10.1 Basic Description......................................................................................................................................... 1849
30.10.2 SDR mode.................................................................................................................................................... 1850
30.10.2.1 Internal sampling......................................................................................................................1851
30.10.2.2 DQS sampling method............................................................................................................. 1852
Chapter 31
Queue Direct Memory Access Controller (qDMA)
31.1 Introduction ..................................................................................................................................................................1853
31.1.1 Overview...................................................................................................................................................... 1853
31.1.2 Features........................................................................................................................................................ 1854
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 97
Section number Title Page
31.1.3 Modes of Operation..................................................................................................................................... 1855
31.2 Memory Map................................................................................................................................................................ 1856
31.2.1 qDMA register descriptions......................................................................................................................... 1856
31.2.1.1 qdma Memory map.................................................................................................................. 1857
31.2.1.2 DMA mode register (DMR).....................................................................................................1866
31.2.1.2.1 Offset...................................................................................................................1866
31.2.1.2.2 Function.............................................................................................................. 1866
31.2.1.2.3 Diagram...............................................................................................................1866
31.2.1.2.4 Fields...................................................................................................................1866
31.2.1.3 DMA status register (DSR_P)..................................................................................................1868
31.2.1.3.1 Offset...................................................................................................................1868
31.2.1.3.2 Function.............................................................................................................. 1868
31.2.1.3.3 Diagram...............................................................................................................1868
31.2.1.3.4 Fields...................................................................................................................1868
31.2.1.4 DMA stream ID flush register (DSIDFR)................................................................................1868
31.2.1.4.1 Offset...................................................................................................................1868
31.2.1.4.2 Function.............................................................................................................. 1869
31.2.1.4.3 Diagram...............................................................................................................1869
31.2.1.4.4 Fields...................................................................................................................1869
31.2.1.5 DMA status register (DSR_M)................................................................................................ 1869
31.2.1.5.1 Offset...................................................................................................................1869
31.2.1.5.2 Function.............................................................................................................. 1870
31.2.1.5.3 Diagram...............................................................................................................1870
31.2.1.5.4 Fields...................................................................................................................1870
31.2.1.6 DMA global bandwidth throttle register (DGBTR).................................................................1870
31.2.1.6.1 Offset...................................................................................................................1870
31.2.1.6.2 Function.............................................................................................................. 1871
31.2.1.6.3 Diagram...............................................................................................................1871
31.2.1.6.4 Fields...................................................................................................................1871
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
98 NXP Semiconductors
Section number Title Page
31.2.1.7 IP Block Revision register 0 (IPBRR0)................................................................................... 1872
31.2.1.7.1 Offset...................................................................................................................1872
31.2.1.7.2 Function.............................................................................................................. 1872
31.2.1.7.3 Diagram...............................................................................................................1872
31.2.1.7.4 Fields...................................................................................................................1872
31.2.1.8 IP Block Revision register 1 (IPBRR1)................................................................................... 1873
31.2.1.8.1 Offset...................................................................................................................1873
31.2.1.8.2 Function.............................................................................................................. 1873
31.2.1.8.3 Diagram...............................................................................................................1873
31.2.1.8.4 Fields...................................................................................................................1873
31.2.1.9 DMA error interrupt enable register (DEIER)......................................................................... 1874
31.2.1.9.1 Offset...................................................................................................................1874
31.2.1.9.2 Function.............................................................................................................. 1874
31.2.1.9.3 Diagram...............................................................................................................1874
31.2.1.9.4 Fields...................................................................................................................1875
31.2.1.10 DMA error detect register (DEDR)......................................................................................... 1876
31.2.1.10.1 Offset...................................................................................................................1876
31.2.1.10.2 Function.............................................................................................................. 1876
31.2.1.10.3 Diagram...............................................................................................................1876
31.2.1.10.4 Fields...................................................................................................................1876
31.2.1.11 DMA error capture frame descriptor word 0 register (DECCDW0R).....................................1877
31.2.1.11.1 Offset...................................................................................................................1877
31.2.1.11.2 Function.............................................................................................................. 1877
31.2.1.11.3 Diagram...............................................................................................................1878
31.2.1.11.4 Fields...................................................................................................................1878
31.2.1.12 DMA error capture frame descriptor word 1 register (DECCDW1R).....................................1878
31.2.1.12.1 Offset...................................................................................................................1878
31.2.1.12.2 Diagram...............................................................................................................1878
31.2.1.12.3 Fields...................................................................................................................1879
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 99
Section number Title Page
31.2.1.13 DMA error capture frame descriptor word 2 register (DECCDW2R).....................................1879
31.2.1.13.1 Offset...................................................................................................................1879
31.2.1.13.2 Diagram...............................................................................................................1879
31.2.1.13.3 Fields...................................................................................................................1880
31.2.1.14 DMA error capture frame descriptor word 3 register (DECCDW3R).....................................1880
31.2.1.14.1 Offset...................................................................................................................1880
31.2.1.14.2 Diagram...............................................................................................................1880
31.2.1.14.3 Fields...................................................................................................................1880
31.2.1.15 DMA error capture command queue ID register (DECCQIDR)............................................. 1880
31.2.1.15.1 Offset...................................................................................................................1881
31.2.1.15.2 Function.............................................................................................................. 1881
31.2.1.15.3 Diagram...............................................................................................................1881
31.2.1.15.4 Fields...................................................................................................................1881
31.2.1.16 DMA error capture byte count register (DECBR)................................................................... 1882
31.2.1.16.1 Offset...................................................................................................................1882
31.2.1.16.2 Function.............................................................................................................. 1882
31.2.1.16.3 Diagram...............................................................................................................1882
31.2.1.16.4 Fields...................................................................................................................1883
31.2.1.17 Block a command queue b mode register (B0CQ0MR - B3CQ7MR).................................... 1883
31.2.1.17.1 Offset...................................................................................................................1883
31.2.1.17.2 Function.............................................................................................................. 1883
31.2.1.17.3 Diagram...............................................................................................................1883
31.2.1.17.4 Fields...................................................................................................................1884
31.2.1.18 Block a command queue b status register (B0CQ0SR - B3CQ7SR).......................................1885
31.2.1.18.1 Offset...................................................................................................................1885
31.2.1.18.2 Function.............................................................................................................. 1885
31.2.1.18.3 Diagram...............................................................................................................1885
31.2.1.18.4 Fields...................................................................................................................1885
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
100 NXP Semiconductors
Section number Title Page
31.2.1.19 Block a command queue b extended dequeue pointer address register (B0CQ0EDPAR -
B3CQ7EDPAR)....................................................................................................................... 1886
31.2.1.19.1 Offset...................................................................................................................1886
31.2.1.19.2 Function.............................................................................................................. 1886
31.2.1.19.3 Diagram...............................................................................................................1887
31.2.1.19.4 Fields...................................................................................................................1887
31.2.1.20 Block a command queue b dequeue pointer address register (B0CQ0DPAR - B3CQ7DPA
R)..............................................................................................................................................1887
31.2.1.20.1 Offset...................................................................................................................1887
31.2.1.20.2 Diagram...............................................................................................................1888
31.2.1.20.3 Fields...................................................................................................................1888
31.2.1.21 Block a command queue b extended enqueue pointer address register (B0CQ0EEPAR -
B3CQ7EEPAR)....................................................................................................................... 1888
31.2.1.21.1 Offset...................................................................................................................1888
31.2.1.21.2 Function.............................................................................................................. 1888
31.2.1.21.3 Diagram...............................................................................................................1889
31.2.1.21.4 Fields...................................................................................................................1889
31.2.1.22 Block a command queue b enqueue pointer address register (B0CQ0EPAR - B3CQ7EPA
R)..............................................................................................................................................1889
31.2.1.22.1 Offset...................................................................................................................1889
31.2.1.22.2 Diagram...............................................................................................................1890
31.2.1.22.3 Fields...................................................................................................................1890
31.2.1.23 Block a command queue interrupt enable registers (B0CQIER - B3CQIER)......................... 1890
31.2.1.23.1 Offset...................................................................................................................1890
31.2.1.23.2 Function.............................................................................................................. 1891
31.2.1.23.3 Diagram...............................................................................................................1891
31.2.1.23.4 Fields...................................................................................................................1891
31.2.1.24 Block a command queue interrupt detect registers (B0CQIDR - B3CQIDR)......................... 1892
31.2.1.24.1 Offset...................................................................................................................1892
31.2.1.24.2 Function.............................................................................................................. 1892
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 101
Section number Title Page
31.2.1.24.3 Diagram...............................................................................................................1892
31.2.1.24.4 Fields...................................................................................................................1893
31.2.1.25 Block a status queue mode register (B0SQMR - B3SQMR)...................................................1894
31.2.1.25.1 Offset...................................................................................................................1894
31.2.1.25.2 Function.............................................................................................................. 1894
31.2.1.25.3 Diagram...............................................................................................................1894
31.2.1.25.4 Fields...................................................................................................................1894
31.2.1.26 Block a status queue status register (B0SQSR - B3SQSR)..................................................... 1895
31.2.1.26.1 Offset...................................................................................................................1895
31.2.1.26.2 Function.............................................................................................................. 1895
31.2.1.26.3 Diagram...............................................................................................................1896
31.2.1.26.4 Fields...................................................................................................................1896
31.2.1.27 Block a status queue extended dequeue pointer address register (B0SQEDPAR - B3SQ
EDPAR)................................................................................................................................... 1896
31.2.1.27.1 Offset...................................................................................................................1896
31.2.1.27.2 Function.............................................................................................................. 1897
31.2.1.27.3 Diagram...............................................................................................................1897
31.2.1.27.4 Fields...................................................................................................................1897
31.2.1.28 Block a status queue dequeue pointer address register (B0SQDPAR - B3SQDPAR)............ 1898
31.2.1.28.1 Offset...................................................................................................................1898
31.2.1.28.2 Diagram...............................................................................................................1898
31.2.1.28.3 Fields...................................................................................................................1898
31.2.1.29 Block a status queue extended enqueue pointer address register (B0SQEEPAR - B3SQ
EEPAR)....................................................................................................................................1899
31.2.1.29.1 Offset...................................................................................................................1899
31.2.1.29.2 Function.............................................................................................................. 1899
31.2.1.29.3 Diagram...............................................................................................................1899
31.2.1.29.4 Fields...................................................................................................................1900
31.2.1.30 Block a status queue enqueue pointer address register (B0SQEPAR - B3SQEPAR)............. 1900
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
102 NXP Semiconductors
Section number Title Page
31.2.1.30.1 Offset...................................................................................................................1900
31.2.1.30.2 Diagram...............................................................................................................1900
31.2.1.30.3 Fields...................................................................................................................1901
31.2.1.31 Block a status queue interrupt coalescing register (B0SQICR - B3SQICR)........................... 1901
31.2.1.31.1 Offset...................................................................................................................1901
31.2.1.31.2 Function.............................................................................................................. 1901
31.2.1.31.3 Diagram...............................................................................................................1901
31.2.1.31.4 Fields...................................................................................................................1902
31.2.1.32 Command queue mode register (CQMR)................................................................................ 1903
31.2.1.32.1 Offset...................................................................................................................1903
31.2.1.32.2 Function.............................................................................................................. 1903
31.2.1.32.3 Diagram...............................................................................................................1903
31.2.1.32.4 Fields...................................................................................................................1903
31.2.1.33 Command queue dequeue scheduler configuration register 1 (CQDSCR1)............................1904
31.2.1.33.1 Offset...................................................................................................................1904
31.2.1.33.2 Function.............................................................................................................. 1904
31.2.1.33.3 Diagram...............................................................................................................1904
31.2.1.33.4 Fields...................................................................................................................1905
31.2.1.34 Command queue dequeue scheduler configuration register 2 (CQDSCR2)............................1906
31.2.1.34.1 Offset...................................................................................................................1906
31.2.1.34.2 Function.............................................................................................................. 1906
31.2.1.34.3 Diagram...............................................................................................................1906
31.2.1.34.4 Fields...................................................................................................................1907
31.2.1.35 Command queue interrupt enable register (CQIER)................................................................1907
31.2.1.35.1 Offset...................................................................................................................1907
31.2.1.35.2 Function.............................................................................................................. 1908
31.2.1.35.3 Diagram...............................................................................................................1908
31.2.1.35.4 Fields...................................................................................................................1908
31.2.1.36 Command queue error detect register (CQEDR)..................................................................... 1908
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 103
Section number Title Page
31.2.1.36.1 Offset...................................................................................................................1909
31.2.1.36.2 Function.............................................................................................................. 1909
31.2.1.36.3 Diagram...............................................................................................................1909
31.2.1.36.4 Fields...................................................................................................................1909
31.2.1.37 Command queue error capture extended address register (CQECEAR)................................. 1910
31.2.1.37.1 Offset...................................................................................................................1910
31.2.1.37.2 Function.............................................................................................................. 1910
31.2.1.37.3 Diagram...............................................................................................................1910
31.2.1.37.4 Fields...................................................................................................................1910
31.2.1.38 Command Queue Error Capture Address Register (CQECAR).............................................. 1911
31.2.1.38.1 Offset...................................................................................................................1911
31.2.1.38.2 Diagram...............................................................................................................1911
31.2.1.38.3 Fields...................................................................................................................1911
31.2.1.39 Status queue critical congestion management register (SQCCMR)........................................ 1911
31.2.1.39.1 Offset...................................................................................................................1911
31.2.1.39.2 Function.............................................................................................................. 1912
31.2.1.39.3 Diagram...............................................................................................................1912
31.2.1.39.4 Fields...................................................................................................................1912
31.2.1.40 Command queue block a stream ID register (CQ0SIDR - CQ3SIDR)....................................1912
31.2.1.40.1 Offset...................................................................................................................1912
31.2.1.40.2 Function.............................................................................................................. 1913
31.2.1.40.3 Diagram...............................................................................................................1913
31.2.1.40.4 Fields...................................................................................................................1913
31.3 Functional Description .................................................................................................................................................1914
31.3.1 qDMA Command Queue Mode Operation.................................................................................................. 1914
31.3.1.1 Dequeue Scheduling................................................................................................................ 1914
31.3.1.2 Status Queue............................................................................................................................ 1916
31.3.1.3 qDMA Command Descriptor Formats.....................................................................................1916
31.3.1.3.1 Compound Command Descriptor Format...........................................................1916
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
104 NXP Semiconductors
Section number Title Page
31.3.1.4 The qDMA Compound S/G Format.........................................................................................1918
31.3.1.5 The qDMA Source Descriptor Format.....................................................................................1919
31.3.1.6 The qDMA Destination Descriptor Format............................................................................. 1921
31.3.1.7 The qDMA Scatter Gather Table Format................................................................................ 1923
31.3.1.8 Striding Operation....................................................................................................................1924
31.3.1.8.1 Summary of Striding Rules.................................................................................1926
31.3.1.9 Partition Level Reset Assistance..............................................................................................1926
31.3.1.10 Different Use Cases................................................................................................................. 1927
31.3.1.10.1 Single Destination with Single Source/Destination Data Buffer........................1927
31.3.1.10.2 Single Destination with Multiple Data Buffers.................................................. 1927
31.3.2 qDMA Controller Interrupts........................................................................................................................ 1928
31.3.3 Command Queue Interrupts......................................................................................................................... 1928
31.3.4 Global Bandwidth Throttling....................................................................................................................... 1929
31.3.5 Address Alignment Requirements............................................................................................................... 1930
31.3.6 Transaction Sizes......................................................................................................................................... 1930
31.3.7 Performance Improvements......................................................................................................................... 1930
31.3.7.1 Large Transfers........................................................................................................................ 1930
31.3.7.2 Alignment.................................................................................................................................1931
31.3.8 Low-Power Mode........................................................................................................................................ 1931
31.3.9 DMA Scenarios............................................................................................................................................1931
31.3.9.1 qDMA to Core......................................................................................................................... 1931
31.3.9.2 qDMA to Configuration, Control and Status Registers........................................................... 1932
31.3.9.3 qDMA to PCI-Express............................................................................................................. 1932
31.3.10 Error Handling............................................................................................................................................. 1932
31.3.10.1 Hardware Errors....................................................................................................................... 1932
31.3.10.2 Programming Errors.................................................................................................................1933
31.4 Initialization Information.............................................................................................................................................. 1938
Chapter 32
SATA 3.0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 105
Section number Title Page
32.1 Advanced host controller interface overview .............................................................................................................. 1939
32.2 SATA features summary...............................................................................................................................................1940
32.3 SATA AHCI register descriptions................................................................................................................................ 1940
32.3.1 SATA Memory map.....................................................................................................................................1941
32.3.2 HBA capabilities register (CAP)..................................................................................................................1942
32.3.2.1 Offset........................................................................................................................................1942
32.3.2.2 Function................................................................................................................................... 1942
32.3.2.3 Diagram....................................................................................................................................1942
32.3.2.4 Fields........................................................................................................................................ 1943
32.3.3 Global HBA control register (GHC)............................................................................................................ 1945
32.3.3.1 Offset........................................................................................................................................1945
32.3.3.2 Function................................................................................................................................... 1945
32.3.3.3 Diagram....................................................................................................................................1945
32.3.3.4 Fields........................................................................................................................................ 1946
32.3.4 AHCI version register (VS)......................................................................................................................... 1947
32.3.4.1 Offset........................................................................................................................................1947
32.3.4.2 Function................................................................................................................................... 1947
32.3.4.3 Diagram....................................................................................................................................1947
32.3.4.4 Fields........................................................................................................................................ 1947
32.3.5 Command completion coalescing control register (CCC_CTL)..................................................................1948
32.3.5.1 Offset........................................................................................................................................1948
32.3.5.2 Function................................................................................................................................... 1948
32.3.5.3 Diagram....................................................................................................................................1948
32.3.5.4 Fields........................................................................................................................................ 1948
32.3.6 HBA capabilities extended register (CAP2)................................................................................................ 1949
32.3.6.1 Offset........................................................................................................................................1949
32.3.6.2 Function................................................................................................................................... 1949
32.3.6.3 Diagram....................................................................................................................................1950
32.3.6.4 Fields........................................................................................................................................ 1950
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
106 NXP Semiconductors
Section number Title Page
32.3.7 Port config register (PCFG)......................................................................................................................... 1950
32.3.7.1 Offset........................................................................................................................................1950
32.3.7.2 Function................................................................................................................................... 1951
32.3.7.3 Diagram....................................................................................................................................1951
32.3.7.4 Fields........................................................................................................................................ 1951
32.3.8 Port Phy1Cfg register (PPCFG)................................................................................................................... 1952
32.3.8.1 Offset........................................................................................................................................1952
32.3.8.2 Function................................................................................................................................... 1952
32.3.8.3 Diagram....................................................................................................................................1952
32.3.8.4 Fields........................................................................................................................................ 1952
32.3.9 Port Phy2Cfg register (PP2C)...................................................................................................................... 1954
32.3.9.1 Offset........................................................................................................................................1954
32.3.9.2 Function................................................................................................................................... 1954
32.3.9.3 Diagram....................................................................................................................................1955
32.3.9.4 Fields........................................................................................................................................ 1955
32.3.10 Port Phy3Cfg register (PP3C)...................................................................................................................... 1955
32.3.10.1 Offset........................................................................................................................................1955
32.3.10.2 Function................................................................................................................................... 1955
32.3.10.3 Diagram....................................................................................................................................1956
32.3.10.4 Fields........................................................................................................................................ 1956
32.3.11 Port Phy4Cfg register (PP4C)...................................................................................................................... 1957
32.3.11.1 Offset........................................................................................................................................1957
32.3.11.2 Function................................................................................................................................... 1957
32.3.11.3 Diagram....................................................................................................................................1957
32.3.11.4 Fields........................................................................................................................................ 1958
32.3.12 Port Phy5Cfg register (PP5C)...................................................................................................................... 1958
32.3.12.1 Offset........................................................................................................................................1958
32.3.12.2 Function................................................................................................................................... 1958
32.3.12.3 Diagram....................................................................................................................................1959
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 107
Section number Title Page
32.3.12.4 Fields........................................................................................................................................ 1959
32.3.13 AXI cache control register (AXICC)........................................................................................................... 1959
32.3.13.1 Offset........................................................................................................................................1960
32.3.13.2 Function................................................................................................................................... 1960
32.3.13.3 Diagram....................................................................................................................................1961
32.3.13.4 Fields........................................................................................................................................ 1961
32.3.14 Port AXICfg register (PAXIC).................................................................................................................... 1962
32.3.14.1 Offset........................................................................................................................................1962
32.3.14.2 Function................................................................................................................................... 1962
32.3.14.3 Diagram....................................................................................................................................1963
32.3.14.4 Fields........................................................................................................................................ 1963
32.3.15 Port TransCfg register (PTC)....................................................................................................................... 1964
32.3.15.1 Offset........................................................................................................................................1964
32.3.15.2 Function................................................................................................................................... 1964
32.3.15.3 Diagram....................................................................................................................................1964
32.3.15.4 Fields........................................................................................................................................ 1964
32.3.16 Port LinkCfg register (PLC)........................................................................................................................ 1965
32.3.16.1 Offset........................................................................................................................................1965
32.3.16.2 Function................................................................................................................................... 1965
32.3.16.3 Diagram....................................................................................................................................1965
32.3.16.4 Fields........................................................................................................................................ 1966
32.3.17 Port LinkCfg1 register (PLC1).................................................................................................................... 1967
32.3.17.1 Offset........................................................................................................................................1967
32.3.17.2 Function................................................................................................................................... 1967
32.3.17.3 Diagram....................................................................................................................................1967
32.3.17.4 Fields........................................................................................................................................ 1968
32.3.18 Port LinkCfg2 register (PLC2).................................................................................................................... 1968
32.3.18.1 Offset........................................................................................................................................1968
32.3.18.2 Function................................................................................................................................... 1968
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
108 NXP Semiconductors
Section number Title Page
32.3.18.3 Diagram....................................................................................................................................1969
32.3.18.4 Fields........................................................................................................................................ 1969
32.3.19 Port LinkStatus1 register (PLS1)................................................................................................................. 1969
32.3.19.1 Offset........................................................................................................................................1969
32.3.19.2 Function................................................................................................................................... 1969
32.3.19.3 Diagram....................................................................................................................................1970
32.3.19.4 Fields........................................................................................................................................ 1970
32.3.20 Port CmdConfig register (PCMDC)............................................................................................................ 1971
32.3.20.1 Offset........................................................................................................................................1971
32.3.20.2 Function................................................................................................................................... 1971
32.3.20.3 Diagram....................................................................................................................................1971
32.3.20.4 Fields........................................................................................................................................ 1971
32.3.21 Port PhyControl status register (PPCS)....................................................................................................... 1972
32.3.21.1 Offset........................................................................................................................................1972
32.3.21.2 Function................................................................................................................................... 1972
32.3.21.3 Diagram....................................................................................................................................1972
32.3.21.4 Fields........................................................................................................................................ 1973
32.3.22 Timer control register (TCR)....................................................................................................................... 1973
32.3.22.1 Offset........................................................................................................................................1973
32.3.22.2 Function................................................................................................................................... 1974
32.3.22.3 Diagram....................................................................................................................................1974
32.3.22.4 Fields........................................................................................................................................ 1974
32.3.23 Port x command list base address register (PxCLB)....................................................................................1974
32.3.23.1 Offset........................................................................................................................................1974
32.3.23.2 Diagram....................................................................................................................................1975
32.3.23.3 Fields........................................................................................................................................ 1975
32.3.24 Port x command list base address upper 32-bit register (PxCLBU)............................................................ 1975
32.3.24.1 Offset........................................................................................................................................1975
32.3.24.2 Diagram....................................................................................................................................1976
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 109
Section number Title Page
32.3.24.3 Fields........................................................................................................................................ 1976
32.3.25 Port x FIS base address register (PxFB)...................................................................................................... 1976
32.3.25.1 Offset........................................................................................................................................1976
32.3.25.2 Diagram....................................................................................................................................1976
32.3.25.3 Fields........................................................................................................................................ 1977
32.3.26 Port x FIS base address upper 32-bit register (PxFBU)...............................................................................1977
32.3.26.1 Offset........................................................................................................................................1977
32.3.26.2 Diagram....................................................................................................................................1977
32.3.26.3 Fields........................................................................................................................................ 1978
32.3.27 Port x interrupt status register (PxIS)...........................................................................................................1978
32.3.27.1 Offset........................................................................................................................................1978
32.3.27.2 Diagram....................................................................................................................................1978
32.3.27.3 Fields........................................................................................................................................ 1979
32.3.28 Port x command and status register (PxCMD)............................................................................................ 1980
32.3.28.1 Offset........................................................................................................................................1980
32.3.28.2 Diagram....................................................................................................................................1981
32.3.28.3 Fields........................................................................................................................................ 1981
32.3.29 Port x SATA status register (PxSSTS)........................................................................................................ 1984
32.3.29.1 Offset........................................................................................................................................1984
32.3.29.2 Function................................................................................................................................... 1984
32.3.29.3 Diagram....................................................................................................................................1985
32.3.29.4 Fields........................................................................................................................................ 1985
32.3.30 Port x SATA control register (PxSCTL)......................................................................................................1985
32.3.30.1 Offset........................................................................................................................................1986
32.3.30.2 Function................................................................................................................................... 1986
32.3.30.3 Diagram....................................................................................................................................1986
32.3.30.4 Fields........................................................................................................................................ 1986
32.3.31 Port x SATA error register (PxSERR)......................................................................................................... 1987
32.3.31.1 Offset........................................................................................................................................1987
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
110 NXP Semiconductors
Section number Title Page
32.3.31.2 Function................................................................................................................................... 1987
32.3.31.3 Diagram....................................................................................................................................1987
32.3.31.4 Fields........................................................................................................................................ 1988
32.3.32 Port x command issue register (PxCI)......................................................................................................... 1990
32.3.32.1 Offset........................................................................................................................................1990
32.3.32.2 Diagram....................................................................................................................................1990
32.3.32.3 Fields........................................................................................................................................ 1990
32.3.33 Port x FIS-based switching control register (PxFBS).................................................................................. 1991
32.3.33.1 Offset........................................................................................................................................1991
32.3.33.2 Function................................................................................................................................... 1991
32.3.33.3 Diagram....................................................................................................................................1991
32.3.33.4 Fields........................................................................................................................................ 1991
32.3.34 Port 0 BIST error register (PBERR)............................................................................................................ 1992
32.3.34.1 Offset........................................................................................................................................1992
32.3.34.2 Function................................................................................................................................... 1993
32.3.34.3 Diagram....................................................................................................................................1993
32.3.34.4 Fields........................................................................................................................................ 1993
32.4 Command layer.............................................................................................................................................................1994
32.4.1 Local port context management................................................................................................................... 1994
32.4.2 Vendor-specific BIST operation.................................................................................................................. 1994
32.4.2.1 Command list structure............................................................................................................ 1995
32.4.2.2 Vendor BIST command descriptor command FIS...................................................................1996
32.4.2.3 Receive FIS area reg D2H RFIS structure............................................................................... 1996
32.5 PhyControl BIST modes............................................................................................................................................... 1997
32.6 PHY control configuration register OOB timing setup................................................................................................ 1998
32.7 Modifications to the AHCI standard PRDT entry........................................................................................................ 1999
32.8 Transport layer architectural overview......................................................................................................................... 2000
32.9 Link layer overview...................................................................................................................................................... 2001
32.9.1 General operation......................................................................................................................................... 2001
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 111
Section number Title Page
32.9.2 List of functions........................................................................................................................................... 2002
32.9.3 Link layer state machines.............................................................................................................................2002
32.9.3.1 Link idle state machine............................................................................................................ 2002
32.9.3.2 Transmit state machine............................................................................................................ 2003
32.9.3.3 Receive state machine.............................................................................................................. 2004
32.9.3.4 Power mode change state machine.......................................................................................... 2004
32.9.4 Frame content scrambler and descrambler...................................................................................................2005
32.9.5 CRC generator and checker......................................................................................................................... 2006
32.9.6 8B/10B encode and decode..........................................................................................................................2006
32.9.7 CONT primitive processing......................................................................................................................... 2006
32.9.8 ALIGN insertion.......................................................................................................................................... 2007
32.9.9 Debug functionality......................................................................................................................................2007
32.9.10 BIST support................................................................................................................................................ 2008
32.10 PHY control layer overview......................................................................................................................................... 2009
32.11 Reset..............................................................................................................................................................................2009
32.11.1 Software reset...............................................................................................................................................2010
32.11.2 Port reset...................................................................................................................................................... 2013
32.11.3 HBA reset.....................................................................................................................................................2013
Chapter 33
SerDes Module
33.1 The SerDes module as implemented on the chip..........................................................................................................2015
33.1.1 SerDes lane assignments and multiplexing..................................................................................................2015
33.1.1.1 Configuration of networking SerDes....................................................................................... 2015
33.1.1.2 SerDes protocols...................................................................................................................... 2015
33.1.1.2.1 SerDes lane assignments.....................................................................................2017
33.1.1.2.2 Frame manager MACs .......................................................................................2018
33.1.1.2.3 Disabling unused SerDes modules......................................................................2018
33.1.1.3 Powering down Unused serDes lanes ..................................................................................... 2018
33.1.2 SerDes clocking........................................................................................................................................... 2019
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
112 NXP Semiconductors
Section number Title Page
33.1.2.1 Valid reference clocks and PLL configurations for SerDes protocols ....................................2019
33.2 Overview.......................................................................................................................................................................2020
33.2.1 Features........................................................................................................................................................ 2020
33.3 Modes of Operation...................................................................................................................................................... 2020
33.4 External Signals Description.........................................................................................................................................2020
33.5 SerDes register descriptions..........................................................................................................................................2021
33.5.1 SerDes Memory map................................................................................................................................... 2022
33.5.2 SerDes PLLa Reset Control Register (PLL1RSTCTL - PLL2RSTCTL)....................................................2024
33.5.2.1 Offset........................................................................................................................................2024
33.5.2.2 Function................................................................................................................................... 2024
33.5.2.3 Diagram....................................................................................................................................2025
33.5.2.4 Fields........................................................................................................................................ 2025
33.5.3 SerDes PLLa Control Register 0 (PLL1CR0 - PLL2CR0)..........................................................................2026
33.5.3.1 Offset........................................................................................................................................2026
33.5.3.2 Function................................................................................................................................... 2027
33.5.3.3 Diagram....................................................................................................................................2027
33.5.3.4 Fields........................................................................................................................................ 2027
33.5.4 SerDes PLLa Control Register 1 (PLL1CR1 - PLL2CR1)..........................................................................2029
33.5.4.1 Offset........................................................................................................................................2029
33.5.4.2 Function................................................................................................................................... 2029
33.5.4.3 Diagram....................................................................................................................................2029
33.5.4.4 Fields........................................................................................................................................ 2029
33.5.5 SerDes PLLa Control Register 5 (PLL1CR5 - PLL2CR5)..........................................................................2030
33.5.5.1 Offset........................................................................................................................................2030
33.5.5.2 Function................................................................................................................................... 2030
33.5.5.3 Diagram....................................................................................................................................2030
33.5.5.4 Fields........................................................................................................................................ 2031
33.5.6 SerDes Transmit Calibration Control Register (TCALCR).........................................................................2031
33.5.6.1 Offset........................................................................................................................................2031
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 113
Section number Title Page
33.5.6.2 Function................................................................................................................................... 2032
33.5.6.3 Diagram....................................................................................................................................2032
33.5.6.4 Fields........................................................................................................................................ 2032
33.5.7 SerDes Transmit Calibration Control Register 1 (TCALCR1)....................................................................2032
33.5.7.1 Offset........................................................................................................................................2033
33.5.7.2 Function................................................................................................................................... 2033
33.5.7.3 Diagram....................................................................................................................................2033
33.5.7.4 Fields........................................................................................................................................ 2033
33.5.8 Receive Calibration Control Register (RCALCR).......................................................................................2034
33.5.8.1 Offset........................................................................................................................................2034
33.5.8.2 Function................................................................................................................................... 2034
33.5.8.3 Diagram....................................................................................................................................2034
33.5.8.4 Fields........................................................................................................................................ 2035
33.5.9 SerDes Receive Calibration Control Register 1 (RCALCR1)..................................................................... 2035
33.5.9.1 Offset........................................................................................................................................2035
33.5.9.2 Function................................................................................................................................... 2035
33.5.9.3 Diagram....................................................................................................................................2035
33.5.9.4 Fields........................................................................................................................................ 2036
33.5.10 General Control Register 0 (GR0)............................................................................................................... 2037
33.5.10.1 Offset........................................................................................................................................2037
33.5.10.2 Function................................................................................................................................... 2037
33.5.10.3 Diagram....................................................................................................................................2037
33.5.10.4 Fields........................................................................................................................................ 2037
33.5.11 Lane a Protocol Select Status Register 0 (LNAPSSR0 - LNDPSSR0)....................................................... 2038
33.5.11.1 Offset........................................................................................................................................2038
33.5.11.2 Function................................................................................................................................... 2038
33.5.11.3 Diagram....................................................................................................................................2038
33.5.11.4 Fields........................................................................................................................................ 2039
33.5.12 Protocol Configuration Register 0 (PCCR0)............................................................................................... 2040
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
114 NXP Semiconductors
Section number Title Page
33.5.12.1 Offset........................................................................................................................................2040
33.5.12.2 Function................................................................................................................................... 2040
33.5.12.3 Diagram....................................................................................................................................2040
33.5.12.4 Fields........................................................................................................................................ 2041
33.5.13 Protocol Configuration Register 2 (PCCR2)............................................................................................... 2042
33.5.13.1 Offset........................................................................................................................................2042
33.5.13.2 Function................................................................................................................................... 2042
33.5.13.3 Diagram....................................................................................................................................2042
33.5.13.4 Fields........................................................................................................................................ 2043
33.5.14 Protocol Configuration Register 8 (PCCR8)............................................................................................... 2043
33.5.14.1 Offset........................................................................................................................................2043
33.5.14.2 Function................................................................................................................................... 2043
33.5.14.3 Diagram....................................................................................................................................2044
33.5.14.4 Fields........................................................................................................................................ 2044
33.5.15 Protocol Configuration Register 9 (PCCR9)............................................................................................... 2045
33.5.15.1 Offset........................................................................................................................................2045
33.5.15.2 Function................................................................................................................................... 2046
33.5.15.3 Diagram....................................................................................................................................2046
33.5.15.4 Fields........................................................................................................................................ 2046
33.5.16 Protocol Configuration Register B (PCCRB).............................................................................................. 2047
33.5.16.1 Offset........................................................................................................................................2047
33.5.16.2 Function................................................................................................................................... 2047
33.5.16.3 Diagram....................................................................................................................................2047
33.5.16.4 Fields........................................................................................................................................ 2048
33.5.17 General Control Register 0 - Lane a (LNAGCR0 - LNDGCR0)................................................................ 2049
33.5.17.1 Offset........................................................................................................................................2049
33.5.17.2 Function................................................................................................................................... 2049
33.5.17.3 Diagram....................................................................................................................................2050
33.5.17.4 Fields........................................................................................................................................ 2050
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 115
Section number Title Page
33.5.18 General Control Register 1 - Lane a (LNAGCR1 - LNDGCR1)................................................................ 2052
33.5.18.1 Offset........................................................................................................................................2052
33.5.18.2 Function................................................................................................................................... 2053
33.5.18.3 Diagram....................................................................................................................................2053
33.5.18.4 Fields........................................................................................................................................ 2053
33.5.19 Speed Switch Control Register 0 - Lane a (LNASSCR0 - LNDSSCR0).................................................... 2056
33.5.19.1 Offset........................................................................................................................................2056
33.5.19.2 Function................................................................................................................................... 2056
33.5.19.3 Diagram....................................................................................................................................2056
33.5.19.4 Fields........................................................................................................................................ 2057
33.5.20 Receive Equalization Control Register 0 - Lane a (LNARECR0 - LNDRECR0).......................................2060
33.5.20.1 Offset........................................................................................................................................2060
33.5.20.2 Function................................................................................................................................... 2060
33.5.20.3 Diagram....................................................................................................................................2060
33.5.20.4 Fields........................................................................................................................................ 2061
33.5.21 Receive Equalization Control Register 1- Lane a (LNARECR1 - LNDRECR1)........................................2063
33.5.21.1 Offset........................................................................................................................................2063
33.5.21.2 Function................................................................................................................................... 2064
33.5.21.3 Diagram....................................................................................................................................2064
33.5.21.4 Fields........................................................................................................................................ 2064
33.5.22 Transmit Equalization Control Register 0 - Lane a (LNATECR0 - LNDTECR0)..................................... 2064
33.5.22.1 Offset........................................................................................................................................2064
33.5.22.2 Function................................................................................................................................... 2065
33.5.22.3 Diagram....................................................................................................................................2065
33.5.22.4 Fields........................................................................................................................................ 2065
33.5.23 Speed Switch Control Register 1- Lane 0 (LNASSCR1 - LNDSSCR1)..................................................... 2067
33.5.23.1 Offset........................................................................................................................................2067
33.5.23.2 Function................................................................................................................................... 2068
33.5.23.3 Diagram....................................................................................................................................2068
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
116 NXP Semiconductors
Section number Title Page
33.5.23.4 Fields........................................................................................................................................ 2068
33.5.24 TTL Control Register 0 - Lane a (LNATTLCR0 - LNDTTLCR0)............................................................. 2071
33.5.24.1 Offset........................................................................................................................................2071
33.5.24.2 Function................................................................................................................................... 2072
33.5.24.3 Diagram....................................................................................................................................2072
33.5.24.4 Fields........................................................................................................................................ 2072
33.5.25 Test Control/Status Register 3 - Lane a (LNATCSR3 - LNDTCSR3)........................................................2072
33.5.25.1 Offset........................................................................................................................................2073
33.5.25.2 Function................................................................................................................................... 2073
33.5.25.3 Diagram....................................................................................................................................2073
33.5.25.4 Fields........................................................................................................................................ 2073
33.5.26 PEXa Protocol Control Register 0 (PEXACR0 - PEXCCR0)..................................................................... 2074
33.5.26.1 Offset........................................................................................................................................2074
33.5.26.2 Function................................................................................................................................... 2074
33.5.26.3 Diagram....................................................................................................................................2074
33.5.26.4 Fields........................................................................................................................................ 2075
33.5.27 SGMIIa Protocol Control Register 1 (SGMIIACR1 - SGMIIDCR1)......................................................... 2075
33.5.27.1 Offset........................................................................................................................................2075
33.5.27.2 Function................................................................................................................................... 2075
33.5.27.3 Diagram....................................................................................................................................2076
33.5.27.4 Fields........................................................................................................................................ 2076
33.5.28 SGMIIa Protocol Control Register 3 (SGMIIACR3 - SGMIIDCR3)......................................................... 2077
33.5.28.1 Offset........................................................................................................................................2077
33.5.28.2 Function................................................................................................................................... 2077
33.5.28.3 Diagram....................................................................................................................................2077
33.5.28.4 Fields........................................................................................................................................ 2077
33.5.29 QSGMIIa Protocol Control Register 1 (QSGMIIACR1 - QSGMIIBCR1)................................................. 2078
33.5.29.1 Offset........................................................................................................................................2078
33.5.29.2 Function................................................................................................................................... 2078
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 117
Section number Title Page
33.5.29.3 Diagram....................................................................................................................................2078
33.5.29.4 Fields........................................................................................................................................ 2079
33.5.30 QSGMIIa Protocol Control Register 3 (QSGMIIACR3 - QSGMIIBCR3)................................................. 2079
33.5.30.1 Offset........................................................................................................................................2079
33.5.30.2 Function................................................................................................................................... 2079
33.5.30.3 Diagram....................................................................................................................................2080
33.5.30.4 Fields........................................................................................................................................ 2080
33.5.31 XFIa Protocol Control Register 1 (XFIACR1 - XFIBCR1)........................................................................ 2081
33.5.31.1 Offset........................................................................................................................................2081
33.5.31.2 Function................................................................................................................................... 2081
33.5.31.3 Diagram....................................................................................................................................2082
33.5.31.4 Fields........................................................................................................................................ 2082
33.5.32 XFIa Protocol Control Register 3 (XFIACR3 - XFIBCR3)........................................................................ 2082
33.5.32.1 Offset........................................................................................................................................2082
33.5.32.2 Function................................................................................................................................... 2082
33.5.32.3 Diagram....................................................................................................................................2083
33.5.32.4 Fields........................................................................................................................................ 2083
33.6 MDIO register spaces................................................................................................................................................... 2084
33.6.1 MDIO_XFI_PMD register descriptions.......................................................................................................2085
33.6.1.1 MDIO_XFI_PMD Memory map............................................................................................. 2085
33.6.1.2 XFI PMD Control 1 (XFI_PMD_CR1)................................................................................... 2086
33.6.1.2.1 Offset...................................................................................................................2086
33.6.1.2.2 Function.............................................................................................................. 2086
33.6.1.2.3 Diagram...............................................................................................................2086
33.6.1.2.4 Fields...................................................................................................................2086
33.6.1.3 XFI 10GBASE-R FEC Ability (XFI_10GR_FEC_ABIL)...................................................... 2086
33.6.1.3.1 Offset...................................................................................................................2086
33.6.1.3.2 Function.............................................................................................................. 2087
33.6.1.3.3 Diagram...............................................................................................................2087
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
118 NXP Semiconductors
Section number Title Page
33.6.1.3.4 Fields...................................................................................................................2087
33.6.1.4 XFI 10GBASE-R FEC Control (XFI_10GR_FEC_CTL)....................................................... 2087
33.6.1.4.1 Offset...................................................................................................................2087
33.6.1.4.2 Function.............................................................................................................. 2087
33.6.1.4.3 Diagram...............................................................................................................2088
33.6.1.4.4 Fields...................................................................................................................2088
33.6.1.5 XFI 10GBASE-R FEC Corrected Blocks Counter Lower (XFI_10GR_FEC_COR_BLK_
CNT_L).................................................................................................................................... 2088
33.6.1.5.1 Offset...................................................................................................................2088
33.6.1.5.2 Function.............................................................................................................. 2089
33.6.1.5.3 Diagram...............................................................................................................2089
33.6.1.5.4 Fields...................................................................................................................2089
33.6.1.6 XFI 10GBASE-R FEC Corrected Blocks Counter Upper (XFI_10GR_FEC_COR_BLK_
CNT_U)................................................................................................................................... 2089
33.6.1.6.1 Offset...................................................................................................................2089
33.6.1.6.2 Function.............................................................................................................. 2089
33.6.1.6.3 Diagram...............................................................................................................2089
33.6.1.6.4 Fields...................................................................................................................2090
33.6.1.7 XFI 10GBASE-R FEC Uncorrected Blocks Counter Lower (XFI_10GR_FEC_UNCOR_B
LK_CNT_L).............................................................................................................................2090
33.6.1.7.1 Offset...................................................................................................................2090
33.6.1.7.2 Function.............................................................................................................. 2090
33.6.1.7.3 Diagram...............................................................................................................2090
33.6.1.7.4 Fields...................................................................................................................2090
33.6.1.8 XFI 10GBASE-R FEC Uncorrected Blocks Counter Upper (XFI_10GR_FEC_UNCOR_B
LK_CNT_U)............................................................................................................................ 2091
33.6.1.8.1 Offset...................................................................................................................2091
33.6.1.8.2 Function.............................................................................................................. 2091
33.6.1.8.3 Diagram...............................................................................................................2091
33.6.1.8.4 Fields...................................................................................................................2091
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 119
Section number Title Page
33.6.1.9 XFI 10GBASE-R Vendor-specific PMA Status (XFI_VEND_SPEC_PMA_STAT)............ 2092
33.6.1.9.1 Offset...................................................................................................................2092
33.6.1.9.2 Function.............................................................................................................. 2092
33.6.1.9.3 Diagram...............................................................................................................2092
33.6.1.9.4 Fields...................................................................................................................2092
33.6.2 MDIO_XFI_PCS register descriptions........................................................................................................ 2092
33.6.2.1 MDIO_XFI_PCS Memory map...............................................................................................2093
33.6.2.2 XFI PCS Control 1 (XFI_PCS_CR1)...................................................................................... 2094
33.6.2.2.1 Offset...................................................................................................................2094
33.6.2.2.2 Function.............................................................................................................. 2094
33.6.2.2.3 Diagram...............................................................................................................2094
33.6.2.2.4 Fields...................................................................................................................2094
33.6.2.3 XFI PCS Status 1 (XFI_PCS_SR1)......................................................................................... 2095
33.6.2.3.1 Offset...................................................................................................................2095
33.6.2.3.2 Function.............................................................................................................. 2095
33.6.2.3.3 Diagram...............................................................................................................2095
33.6.2.3.4 Fields...................................................................................................................2096
33.6.2.4 XFI PCS Device Identifier Upper (XFI_PCS_DEV_ID_H)................................................... 2097
33.6.2.4.1 Offset...................................................................................................................2097
33.6.2.4.2 Function.............................................................................................................. 2097
33.6.2.4.3 Diagram...............................................................................................................2097
33.6.2.4.4 Fields...................................................................................................................2097
33.6.2.5 XFI PCS Device Identifier Lower (XFI_PCS_DEV_ID_L)................................................... 2098
33.6.2.5.1 Offset...................................................................................................................2098
33.6.2.5.2 Function.............................................................................................................. 2098
33.6.2.5.3 Diagram...............................................................................................................2098
33.6.2.5.4 Fields...................................................................................................................2098
33.6.2.6 XFI PCS Speed Ability (XFI_PCS_SPEED_ABIL)............................................................... 2099
33.6.2.6.1 Offset...................................................................................................................2099
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
120 NXP Semiconductors
Section number Title Page
33.6.2.6.2 Function.............................................................................................................. 2099
33.6.2.6.3 Diagram...............................................................................................................2099
33.6.2.6.4 Fields...................................................................................................................2099
33.6.2.7 XFI PCS Devices In Package 0 (XFI_PCS_DEV_PRES0).....................................................2100
33.6.2.7.1 Offset...................................................................................................................2100
33.6.2.7.2 Function.............................................................................................................. 2100
33.6.2.7.3 Diagram...............................................................................................................2100
33.6.2.7.4 Fields...................................................................................................................2100
33.6.2.8 XFI PCS Devices in Package 1 (XFI_PCS_DEV_PRES1).....................................................2101
33.6.2.8.1 Offset...................................................................................................................2101
33.6.2.8.2 Function.............................................................................................................. 2101
33.6.2.8.3 Diagram...............................................................................................................2101
33.6.2.8.4 Fields...................................................................................................................2102
33.6.2.9 XFI 10G PCS Control 2 (XFI_PCS_CR2).............................................................................. 2102
33.6.2.9.1 Offset...................................................................................................................2102
33.6.2.9.2 Function.............................................................................................................. 2102
33.6.2.9.3 Diagram...............................................................................................................2103
33.6.2.9.4 Fields...................................................................................................................2103
33.6.2.10 XFI 10G PCS Status 2 (XFI_PCS_SR2)................................................................................. 2103
33.6.2.10.1 Offset...................................................................................................................2103
33.6.2.10.2 Function.............................................................................................................. 2103
33.6.2.10.3 Diagram...............................................................................................................2103
33.6.2.10.4 Fields...................................................................................................................2104
33.6.2.11 XFI PCS Package Identifier Upper (XFI_PCS_PKG_ID_H)..................................................2105
33.6.2.11.1 Offset...................................................................................................................2105
33.6.2.11.2 Function.............................................................................................................. 2105
33.6.2.11.3 Diagram...............................................................................................................2105
33.6.2.11.4 Fields...................................................................................................................2105
33.6.2.12 XFI PCS Package Identifier Lower (XFI_PCS_PKG_ID_L)..................................................2105
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 121
Section number Title Page
33.6.2.12.1 Offset...................................................................................................................2105
33.6.2.12.2 Function.............................................................................................................. 2106
33.6.2.12.3 Diagram...............................................................................................................2106
33.6.2.12.4 Fields...................................................................................................................2106
33.6.2.13 XFI 10GBASE-R PCS Status 1 (XFI_PCS_10GR_SR1)........................................................2106
33.6.2.13.1 Offset...................................................................................................................2106
33.6.2.13.2 Function.............................................................................................................. 2106
33.6.2.13.3 Diagram...............................................................................................................2106
33.6.2.13.4 Fields...................................................................................................................2107
33.6.2.14 XFI 10GBASE-R PCS Status 2 (XFI_PCS_10GR_SR2)........................................................2107
33.6.2.14.1 Offset...................................................................................................................2107
33.6.2.14.2 Function.............................................................................................................. 2108
33.6.2.14.3 Diagram...............................................................................................................2108
33.6.2.14.4 Fields...................................................................................................................2108
33.6.2.15 XFI 10GBASE-R PCS Test Pattern Seed A 0 (XFI_PCS_TP_SEED_A0)............................ 2109
33.6.2.15.1 Offset...................................................................................................................2109
33.6.2.15.2 Function.............................................................................................................. 2109
33.6.2.15.3 Diagram...............................................................................................................2109
33.6.2.15.4 Fields...................................................................................................................2109
33.6.2.16 XFI 10GBASE-R PCS Test Pattern Seed A 1 (XFI_PCS_TP_SEED_A1)............................ 2109
33.6.2.16.1 Offset...................................................................................................................2109
33.6.2.16.2 Function.............................................................................................................. 2110
33.6.2.16.3 Diagram...............................................................................................................2110
33.6.2.16.4 Fields...................................................................................................................2110
33.6.2.17 XFI 10GBASE-R PCS Test Pattern Seed A 2 (XFI_PCS_TP_SEED_A2)............................ 2110
33.6.2.17.1 Offset...................................................................................................................2110
33.6.2.17.2 Function.............................................................................................................. 2110
33.6.2.17.3 Diagram...............................................................................................................2110
33.6.2.17.4 Fields...................................................................................................................2111
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
122 NXP Semiconductors
Section number Title Page
33.6.2.18 XFI 10GBASE-R PCS Test Pattern Seed A 3 (XFI_PCS_TP_SEED_A3)............................ 2111
33.6.2.18.1 Offset...................................................................................................................2111
33.6.2.18.2 Function.............................................................................................................. 2111
33.6.2.18.3 Diagram...............................................................................................................2111
33.6.2.18.4 Fields...................................................................................................................2111
33.6.2.19 XFI 10GBASE-R PCS Test Pattern Seed B 0 (XFI_PCS_TP_SEED_B0).............................2112
33.6.2.19.1 Offset...................................................................................................................2112
33.6.2.19.2 Function.............................................................................................................. 2112
33.6.2.19.3 Diagram...............................................................................................................2112
33.6.2.19.4 Fields...................................................................................................................2112
33.6.2.20 XFI 10GBASE-R PCS Test Pattern Seed B 1 (XFI_PCS_TP_SEED_B1).............................2113
33.6.2.20.1 Offset...................................................................................................................2113
33.6.2.20.2 Function.............................................................................................................. 2113
33.6.2.20.3 Diagram...............................................................................................................2113
33.6.2.20.4 Fields...................................................................................................................2113
33.6.2.21 XFI 10GBASE-R PCS Test Pattern Seed B 2 (XFI_PCS_TP_SEED_B2).............................2113
33.6.2.21.1 Offset...................................................................................................................2113
33.6.2.21.2 Function.............................................................................................................. 2114
33.6.2.21.3 Diagram...............................................................................................................2114
33.6.2.21.4 Fields...................................................................................................................2114
33.6.2.22 XFI 10GBASE-R PCS Test Pattern Seed B 3 (XFI_PCS_TP_SEED_B3).............................2114
33.6.2.22.1 Offset...................................................................................................................2114
33.6.2.22.2 Function.............................................................................................................. 2114
33.6.2.22.3 Diagram...............................................................................................................2114
33.6.2.22.4 Fields...................................................................................................................2115
33.6.2.23 XFI 10GBASE-R PCS Test Pattern Control (XFI_PCS_TP_CR).......................................... 2115
33.6.2.23.1 Offset...................................................................................................................2115
33.6.2.23.2 Function.............................................................................................................. 2115
33.6.2.23.3 Diagram...............................................................................................................2115
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 123
Section number Title Page
33.6.2.23.4 Fields...................................................................................................................2116
33.6.2.24 XFI 10GBASE-R PCS Test Pattern Error Counter (XFI_PCS_TP_ERR_CNT)....................2117
33.6.2.24.1 Offset...................................................................................................................2117
33.6.2.24.2 Function.............................................................................................................. 2117
33.6.2.24.3 Diagram...............................................................................................................2117
33.6.2.24.4 Fields...................................................................................................................2117
33.6.2.25 Vendor Specific PCS Status (XFI_PCS_VENDOR_SR)........................................................ 2117
33.6.2.25.1 Offset...................................................................................................................2118
33.6.2.25.2 Function.............................................................................................................. 2118
33.6.2.25.3 Diagram...............................................................................................................2118
33.6.2.25.4 Fields...................................................................................................................2118
33.6.3 MDIO_XFI_AN register descriptions......................................................................................................... 2119
33.6.3.1 MDIO_XFI_AN Memory map................................................................................................ 2119
33.6.3.2 XFI AN Control (XF_AN_CR)............................................................................................... 2119
33.6.3.2.1 Offset...................................................................................................................2119
33.6.3.2.2 Function.............................................................................................................. 2120
33.6.3.2.3 Diagram...............................................................................................................2120
33.6.3.2.4 Fields...................................................................................................................2120
33.6.3.3 XFI AN Status (XF_AN_SR).................................................................................................. 2121
33.6.3.3.1 Offset...................................................................................................................2121
33.6.3.3.2 Function.............................................................................................................. 2121
33.6.3.3.3 Diagram...............................................................................................................2121
33.6.3.3.4 Fields...................................................................................................................2121
33.6.3.4 XFI AN Device Identifier Upper (XFI_AN_DEV_ID_H)...................................................... 2122
33.6.3.4.1 Offset...................................................................................................................2123
33.6.3.4.2 Function.............................................................................................................. 2123
33.6.3.4.3 Diagram...............................................................................................................2123
33.6.3.4.4 Fields...................................................................................................................2123
33.6.3.5 XFI AN Device Identifier Lower (XFI_DEV_ID_L)..............................................................2123
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
124 NXP Semiconductors
Section number Title Page
33.6.3.5.1 Offset...................................................................................................................2123
33.6.3.5.2 Function.............................................................................................................. 2123
33.6.3.5.3 Diagram...............................................................................................................2124
33.6.3.5.4 Fields...................................................................................................................2124
33.6.3.6 XFI AN Devices In Package 0 (XFI_AN_DEV_PRES0)....................................................... 2124
33.6.3.6.1 Offset...................................................................................................................2124
33.6.3.6.2 Function.............................................................................................................. 2124
33.6.3.6.3 Diagram...............................................................................................................2124
33.6.3.6.4 Fields...................................................................................................................2125
33.6.3.7 XFI AN Devices In Package 1 (XFI_AN_DEV_PRES1)....................................................... 2126
33.6.3.7.1 Offset...................................................................................................................2126
33.6.3.7.2 Function.............................................................................................................. 2126
33.6.3.7.3 Diagram...............................................................................................................2126
33.6.3.7.4 Fields...................................................................................................................2126
33.6.3.8 XFI AN Package Identifier Upper (XF_AN_PKG_ID_H)......................................................2127
33.6.3.8.1 Offset...................................................................................................................2127
33.6.3.8.2 Function.............................................................................................................. 2127
33.6.3.8.3 Diagram...............................................................................................................2127
33.6.3.8.4 Fields...................................................................................................................2127
33.6.3.9 XFI AN Package Identifier Lower (XFI_AN_PKG_ID_L).................................................... 2127
33.6.3.9.1 Offset...................................................................................................................2127
33.6.3.9.2 Function.............................................................................................................. 2128
33.6.3.9.3 Diagram...............................................................................................................2128
33.6.3.9.4 Fields...................................................................................................................2128
33.6.3.10 XFI AN Advertisement 0 (XFI_AN_ADVERT0)...................................................................2128
33.6.3.10.1 Offset...................................................................................................................2128
33.6.3.10.2 Function.............................................................................................................. 2128
33.6.3.10.3 Diagram...............................................................................................................2129
33.6.3.10.4 Fields...................................................................................................................2129
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 125
Section number Title Page
33.6.3.11 XFI AN Advertisement 1 (XFI_AN_ADVERT1)...................................................................2130
33.6.3.11.1 Offset...................................................................................................................2130
33.6.3.11.2 Function.............................................................................................................. 2130
33.6.3.11.3 Diagram...............................................................................................................2130
33.6.3.11.4 Fields...................................................................................................................2130
33.6.3.12 XFI AN Advertisement 2 (XFI_AN_ADVERT2)...................................................................2131
33.6.3.12.1 Offset...................................................................................................................2131
33.6.3.12.2 Function.............................................................................................................. 2131
33.6.3.12.3 Diagram...............................................................................................................2131
33.6.3.12.4 Fields...................................................................................................................2131
33.6.3.13 XFI AN LP Base Page Ability 0 (XFI_AN_LP_BASE_PG_ABIL0).....................................2132
33.6.3.13.1 Offset...................................................................................................................2132
33.6.3.13.2 Function.............................................................................................................. 2132
33.6.3.13.3 Diagram...............................................................................................................2132
33.6.3.13.4 Fields...................................................................................................................2132
33.6.3.14 XFI AN LP Base Page Ability 1 (XFI_AN_LP_BASE_PG_ABIL1).....................................2133
33.6.3.14.1 Offset...................................................................................................................2133
33.6.3.14.2 Function.............................................................................................................. 2133
33.6.3.14.3 Diagram...............................................................................................................2134
33.6.3.14.4 Fields...................................................................................................................2134
33.6.3.15 XFI AN LP Base Page Ability 2 (XFI_AN_LP_BASE_PG_ABIL2).....................................2134
33.6.3.15.1 Offset...................................................................................................................2134
33.6.3.15.2 Function.............................................................................................................. 2134
33.6.3.15.3 Diagram...............................................................................................................2135
33.6.3.15.4 Fields...................................................................................................................2135
33.6.3.16 XFI AN Extended Next Page Transmit 0 (XFI_AN_XNP_TX0)........................................... 2135
33.6.3.16.1 Offset...................................................................................................................2135
33.6.3.16.2 Function.............................................................................................................. 2135
33.6.3.16.3 Diagram...............................................................................................................2136
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
126 NXP Semiconductors
Section number Title Page
33.6.3.16.4 Fields...................................................................................................................2136
33.6.3.17 XFI AN Extended Next Page Transmit 1 (XFI_AN_XNP_TX1)........................................... 2137
33.6.3.17.1 Offset...................................................................................................................2137
33.6.3.17.2 Function.............................................................................................................. 2137
33.6.3.17.3 Diagram...............................................................................................................2137
33.6.3.17.4 Fields...................................................................................................................2137
33.6.3.18 XFI AN Extended Next Page Transmit 2 (XFI_AN_XNP_TX2)........................................... 2137
33.6.3.18.1 Offset...................................................................................................................2137
33.6.3.18.2 Function.............................................................................................................. 2137
33.6.3.18.3 Diagram...............................................................................................................2138
33.6.3.18.4 Fields...................................................................................................................2138
33.6.3.19 XFI AN LP Extended Next Page Ability 0 (XFI_AN_LP_XNP_ABIL0).............................. 2138
33.6.3.19.1 Offset...................................................................................................................2138
33.6.3.19.2 Function.............................................................................................................. 2138
33.6.3.19.3 Diagram...............................................................................................................2138
33.6.3.19.4 Fields...................................................................................................................2139
33.6.3.20 XFI AN LP Extended Next Page Ability 1 (XFI_AN_LP_XNP_ABIL1).............................. 2139
33.6.3.20.1 Offset...................................................................................................................2140
33.6.3.20.2 Function.............................................................................................................. 2140
33.6.3.20.3 Diagram...............................................................................................................2140
33.6.3.20.4 Fields...................................................................................................................2140
33.6.3.21 XFI AN LP Extended Next Page Ability 2 (XFI_AN_LP_XNP_ABIL2).............................. 2140
33.6.3.21.1 Offset...................................................................................................................2140
33.6.3.21.2 Function.............................................................................................................. 2140
33.6.3.21.3 Diagram...............................................................................................................2141
33.6.3.21.4 Fields...................................................................................................................2141
33.6.3.22 XFI Backplane Ethernet Status (XFI_BP_STAT)................................................................... 2141
33.6.3.22.1 Offset...................................................................................................................2141
33.6.3.22.2 Function.............................................................................................................. 2141
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 127
Section number Title Page
33.6.3.22.3 Diagram...............................................................................................................2141
33.6.3.22.4 Fields...................................................................................................................2142
33.6.4 MDIO_XFI_VENDOR_SPEC register descriptions................................................................................... 2142
33.6.4.1 MDIO_XFI_VENDOR_SPEC Memory map..........................................................................2143
33.6.4.2 XFI Revision (XFI_VND_REV)............................................................................................. 2143
33.6.4.2.1 Offset...................................................................................................................2143
33.6.4.2.2 Function.............................................................................................................. 2143
33.6.4.2.3 Diagram...............................................................................................................2143
33.6.4.2.4 Fields...................................................................................................................2144
33.6.4.3 XFI Scratch (XFI_VND_SCRATCH)..................................................................................... 2144
33.6.4.3.1 Offset...................................................................................................................2144
33.6.4.3.2 Function.............................................................................................................. 2144
33.6.4.3.3 Diagram...............................................................................................................2144
33.6.4.3.4 Fields...................................................................................................................2144
33.6.4.4 XFI PCS Interrupt Event (XFI_VND_PCS_INT)................................................................... 2145
33.6.4.4.1 Offset...................................................................................................................2145
33.6.4.4.2 Function.............................................................................................................. 2145
33.6.4.4.3 Diagram...............................................................................................................2145
33.6.4.4.4 Fields...................................................................................................................2145
33.6.4.5 XFI PCS Interrupt Mask (XFI_VND_PCS_INT_MSK)......................................................... 2147
33.6.4.5.1 Offset...................................................................................................................2147
33.6.4.5.2 Function.............................................................................................................. 2147
33.6.4.5.3 Diagram...............................................................................................................2147
33.6.4.5.4 Fields...................................................................................................................2147
33.6.4.6 XFI Auto-Negotiation Interrupt Event (XFI_VND_AN_INT)............................................... 2149
33.6.4.6.1 Offset...................................................................................................................2149
33.6.4.6.2 Function.............................................................................................................. 2149
33.6.4.6.3 Diagram...............................................................................................................2149
33.6.4.6.4 Fields...................................................................................................................2149
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
128 NXP Semiconductors
Section number Title Page
33.6.4.7 XFI Auto-Negotiation Interrupt Mask (XFI_VND_AN_INT_MSK)..................................... 2150
33.6.4.7.1 Offset...................................................................................................................2150
33.6.4.7.2 Function.............................................................................................................. 2150
33.6.4.7.3 Diagram...............................................................................................................2151
33.6.4.7.4 Fields...................................................................................................................2151
33.6.4.8 XFI Link Training Interrupt Event (XFI_VND_LT_INT)...................................................... 2151
33.6.4.8.1 Offset...................................................................................................................2152
33.6.4.8.2 Function.............................................................................................................. 2152
33.6.4.8.3 Diagram...............................................................................................................2152
33.6.4.8.4 Fields...................................................................................................................2152
33.6.4.9 XFI Link Training Interrupt Mask (XFI_VND_LT_INT_MSK)............................................ 2153
33.6.4.9.1 Offset...................................................................................................................2153
33.6.4.9.2 Function.............................................................................................................. 2153
33.6.4.9.3 Diagram...............................................................................................................2153
33.6.4.9.4 Fields...................................................................................................................2153
33.6.5 MDIO_KX_PCS register descriptions.........................................................................................................2154
33.6.5.1 MDIO_KX_PCS Memory map............................................................................................... 2154
33.6.5.2 KX PCS Control (KX_PCS_CR).............................................................................................2155
33.6.5.2.1 Offset...................................................................................................................2155
33.6.5.2.2 Function.............................................................................................................. 2155
33.6.5.2.3 Diagram...............................................................................................................2156
33.6.5.2.4 Fields...................................................................................................................2156
33.6.5.3 KX PCS Status (KX_PCS_SR)................................................................................................2157
33.6.5.3.1 Offset...................................................................................................................2157
33.6.5.3.2 Function.............................................................................................................. 2157
33.6.5.3.3 Diagram...............................................................................................................2157
33.6.5.3.4 Fields...................................................................................................................2157
33.6.5.4 KX PCS Device Identifier Upper (KX_PCS_DEV_ID)..........................................................2157
33.6.5.4.1 Offset...................................................................................................................2158
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 129
Section number Title Page
33.6.5.4.2 Function.............................................................................................................. 2158
33.6.5.4.3 Diagram...............................................................................................................2158
33.6.5.4.4 Fields...................................................................................................................2158
33.6.5.5 KX PCS Device Identifier Lower (KX_PCS_DEV_ID_L).....................................................2158
33.6.5.5.1 Offset...................................................................................................................2158
33.6.5.5.2 Function.............................................................................................................. 2158
33.6.5.5.3 Diagram...............................................................................................................2159
33.6.5.5.4 Fields...................................................................................................................2159
33.6.5.6 KX PCS Devices In Package 0 (KX_PCS_DEV_PRES0)...................................................... 2159
33.6.5.6.1 Offset...................................................................................................................2159
33.6.5.6.2 Function.............................................................................................................. 2159
33.6.5.6.3 Diagram...............................................................................................................2159
33.6.5.6.4 Fields...................................................................................................................2160
33.6.5.7 KX PCS Devices In Package 1 (KX_PCS_DEV_PRES1)...................................................... 2160
33.6.5.7.1 Offset...................................................................................................................2161
33.6.5.7.2 Function.............................................................................................................. 2161
33.6.5.7.3 Diagram...............................................................................................................2161
33.6.5.7.4 Fields...................................................................................................................2161
33.6.5.8 KX PCS Package Identifier Upper (KX_PCS_PKG_ID_U)................................................... 2162
33.6.5.8.1 Offset...................................................................................................................2162
33.6.5.8.2 Function.............................................................................................................. 2162
33.6.5.8.3 Diagram...............................................................................................................2162
33.6.5.8.4 Fields...................................................................................................................2162
33.6.5.9 KX PCS Package Identifier Lower (KX_PCS_PKG_ID_L)................................................... 2162
33.6.5.9.1 Offset...................................................................................................................2162
33.6.5.9.2 Function.............................................................................................................. 2162
33.6.5.9.3 Diagram...............................................................................................................2163
33.6.5.9.4 Fields...................................................................................................................2163
33.6.5.10 SGMII Control (C45_SGMII_CR).......................................................................................... 2163
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
130 NXP Semiconductors
Section number Title Page
33.6.5.10.1 Offset...................................................................................................................2163
33.6.5.10.2 Function.............................................................................................................. 2163
33.6.5.10.3 Diagram...............................................................................................................2163
33.6.5.10.4 Fields...................................................................................................................2164
33.6.5.11 SGMII Status (C45_SGMII_SR)............................................................................................. 2165
33.6.5.11.1 Offset...................................................................................................................2165
33.6.5.11.2 Function.............................................................................................................. 2165
33.6.5.11.3 Diagram...............................................................................................................2165
33.6.5.11.4 Fields...................................................................................................................2166
33.6.5.12 SGMII PHY Identifier Upper (C45_SGMII_PHY_ID_H)......................................................2167
33.6.5.12.1 Offset...................................................................................................................2167
33.6.5.12.2 Function.............................................................................................................. 2167
33.6.5.12.3 Diagram...............................................................................................................2167
33.6.5.12.4 Fields...................................................................................................................2167
33.6.5.13 SGMII PHY Identifier Lower (C45_SGMII_PHY_ID_L)......................................................2167
33.6.5.13.1 Offset...................................................................................................................2167
33.6.5.13.2 Function.............................................................................................................. 2167
33.6.5.13.3 Diagram...............................................................................................................2168
33.6.5.13.4 Fields...................................................................................................................2168
33.6.5.14 SGMII Device Ability for 1000Base-X (C45_SGMII_DEV_ABIL_1KBX)......................... 2168
33.6.5.14.1 Offset...................................................................................................................2168
33.6.5.14.2 Function.............................................................................................................. 2168
33.6.5.14.3 Diagram...............................................................................................................2168
33.6.5.14.4 Fields...................................................................................................................2169
33.6.5.15 SGMII Device Ability for SGMII (C45_SGMII_DEV_ABIL_SGMII)................................. 2170
33.6.5.15.1 Offset...................................................................................................................2170
33.6.5.15.2 Function.............................................................................................................. 2170
33.6.5.15.3 Diagram...............................................................................................................2170
33.6.5.15.4 Fields...................................................................................................................2170
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 131
Section number Title Page
33.6.5.16 SGMII Partner Ability for 1000Base-X (C45_SGMII_LP_DEV_ABIL_1KBX).................. 2171
33.6.5.16.1 Offset...................................................................................................................2171
33.6.5.16.2 Function.............................................................................................................. 2171
33.6.5.16.3 Diagram...............................................................................................................2171
33.6.5.16.4 Fields...................................................................................................................2171
33.6.5.17 SGMII Partner Ability for SGMII (C45_SGMII_LP_DEV_ABIL_SGMII).......................... 2172
33.6.5.17.1 Offset...................................................................................................................2172
33.6.5.17.2 Function.............................................................................................................. 2172
33.6.5.17.3 Diagram...............................................................................................................2173
33.6.5.17.4 Fields...................................................................................................................2173
33.6.5.18 SGMII AN Expansion (C45_SGMII_AN_EXP).....................................................................2174
33.6.5.18.1 Offset...................................................................................................................2174
33.6.5.18.2 Function.............................................................................................................. 2174
33.6.5.18.3 Diagram...............................................................................................................2174
33.6.5.18.4 Fields...................................................................................................................2174
33.6.5.19 SGMII Next Page Transmit (C45_SGMII_NP_TX)............................................................... 2175
33.6.5.19.1 Offset...................................................................................................................2175
33.6.5.19.2 Function.............................................................................................................. 2175
33.6.5.19.3 Diagram...............................................................................................................2175
33.6.5.19.4 Fields...................................................................................................................2175
33.6.5.20 SGMII LP Next Page Receive (C45_SGMII_NP_RX)........................................................... 2176
33.6.5.20.1 Offset...................................................................................................................2176
33.6.5.20.2 Function.............................................................................................................. 2176
33.6.5.20.3 Diagram...............................................................................................................2176
33.6.5.20.4 Fields...................................................................................................................2176
33.6.5.21 SGMII Extended Status (C45_SGMII_XTND_STAT)...........................................................2177
33.6.5.21.1 Offset...................................................................................................................2177
33.6.5.21.2 Function.............................................................................................................. 2177
33.6.5.21.3 Diagram...............................................................................................................2177
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
132 NXP Semiconductors
Section number Title Page
33.6.5.21.4 Fields...................................................................................................................2178
33.6.5.22 SGMII Scratch (C45_SGMII_SCRATCH)............................................................................. 2178
33.6.5.22.1 Offset...................................................................................................................2178
33.6.5.22.2 Function.............................................................................................................. 2178
33.6.5.22.3 Diagram...............................................................................................................2178
33.6.5.22.4 Fields...................................................................................................................2178
33.6.5.23 SGMII Design Revision (C45_SGMII_REV)......................................................................... 2178
33.6.5.23.1 Offset...................................................................................................................2178
33.6.5.23.2 Function.............................................................................................................. 2179
33.6.5.23.3 Diagram...............................................................................................................2179
33.6.5.23.4 Fields...................................................................................................................2179
33.6.5.24 SGMII Link Timer Lower (C45_SGMII_LINK_TMR_L)..................................................... 2179
33.6.5.24.1 Offset...................................................................................................................2179
33.6.5.24.2 Function.............................................................................................................. 2179
33.6.5.24.3 Diagram...............................................................................................................2180
33.6.5.24.4 Fields...................................................................................................................2180
33.6.5.25 SGMII Link Timer Upper (C45_SGMII_LINK_TMR_H)..................................................... 2180
33.6.5.25.1 Offset...................................................................................................................2180
33.6.5.25.2 Function.............................................................................................................. 2180
33.6.5.25.3 Diagram...............................................................................................................2180
33.6.5.25.4 Fields...................................................................................................................2181
33.6.5.26 SGMII IF Mode (C45_SGMII_IF_MODE)............................................................................ 2181
33.6.5.26.1 Offset...................................................................................................................2181
33.6.5.26.2 Function.............................................................................................................. 2181
33.6.5.26.3 Diagram...............................................................................................................2181
33.6.5.26.4 Fields...................................................................................................................2181
33.6.6 MDIO_KX_AN register descriptions.......................................................................................................... 2182
33.6.6.1 MDIO_KX_AN Memory map.................................................................................................2182
33.6.6.2 KX AN Control (KX_AN_CR)............................................................................................... 2183
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 133
Section number Title Page
33.6.6.2.1 Offset...................................................................................................................2183
33.6.6.2.2 Function.............................................................................................................. 2183
33.6.6.2.3 Diagram...............................................................................................................2183
33.6.6.2.4 Fields...................................................................................................................2184
33.6.6.3 KX AN Status (KX_AN_SR).................................................................................................. 2185
33.6.6.3.1 Offset...................................................................................................................2185
33.6.6.3.2 Function.............................................................................................................. 2185
33.6.6.3.3 Diagram...............................................................................................................2185
33.6.6.3.4 Fields...................................................................................................................2185
33.6.6.4 KX AN Device Identifier Upper (KX_AN_DEV_ID_H)....................................................... 2186
33.6.6.4.1 Offset...................................................................................................................2186
33.6.6.4.2 Function.............................................................................................................. 2187
33.6.6.4.3 Diagram...............................................................................................................2187
33.6.6.4.4 Fields...................................................................................................................2187
33.6.6.5 KX AN Device Identifier Lower (KX_AN_DEV_ID_L)....................................................... 2187
33.6.6.5.1 Offset...................................................................................................................2187
33.6.6.5.2 Function.............................................................................................................. 2187
33.6.6.5.3 Diagram...............................................................................................................2187
33.6.6.5.4 Fields...................................................................................................................2188
33.6.6.6 KX AN Devices in Package 0 (KX_AN_DEV_PRES0).........................................................2188
33.6.6.6.1 Offset...................................................................................................................2188
33.6.6.6.2 Function.............................................................................................................. 2188
33.6.6.6.3 Diagram...............................................................................................................2188
33.6.6.6.4 Fields...................................................................................................................2189
33.6.6.7 KX AN Devices in Package 1 (KX_AN_DEV_PRES1).........................................................2189
33.6.6.7.1 Offset...................................................................................................................2190
33.6.6.7.2 Function.............................................................................................................. 2190
33.6.6.7.3 Diagram...............................................................................................................2190
33.6.6.7.4 Fields...................................................................................................................2190
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
134 NXP Semiconductors
Section number Title Page
33.6.6.8 KX AN Package Identifier Upper (KX_AN_PKG_ID_H)......................................................2191
33.6.6.8.1 Offset...................................................................................................................2191
33.6.6.8.2 Function.............................................................................................................. 2191
33.6.6.8.3 Diagram...............................................................................................................2191
33.6.6.8.4 Fields...................................................................................................................2191
33.6.6.9 KX AN Package Identifier Lower (KX_AN_PKG_ID_L)......................................................2191
33.6.6.9.1 Offset...................................................................................................................2191
33.6.6.9.2 Function.............................................................................................................. 2191
33.6.6.9.3 Diagram...............................................................................................................2192
33.6.6.9.4 Fields...................................................................................................................2192
33.6.6.10 KX AN Advertisement 0 (KX_AN_ADVERT0).................................................................... 2192
33.6.6.10.1 Offset...................................................................................................................2192
33.6.6.10.2 Function.............................................................................................................. 2192
33.6.6.10.3 Diagram...............................................................................................................2192
33.6.6.10.4 Fields...................................................................................................................2193
33.6.6.11 KX AN Advertisement 1 (KX_AN_ADVERT1).................................................................... 2194
33.6.6.11.1 Offset...................................................................................................................2194
33.6.6.11.2 Function.............................................................................................................. 2194
33.6.6.11.3 Diagram...............................................................................................................2194
33.6.6.11.4 Fields...................................................................................................................2194
33.6.6.12 KX AN Advertisement 2 (KX_AN_ADVERT2).................................................................... 2195
33.6.6.12.1 Offset...................................................................................................................2195
33.6.6.12.2 Function.............................................................................................................. 2195
33.6.6.12.3 Diagram...............................................................................................................2195
33.6.6.12.4 Fields...................................................................................................................2195
33.6.6.13 KX AN LP Base Page Ability 0 (KX_AN_LP_BASE_PG_ABIL0)...................................... 2196
33.6.6.13.1 Offset...................................................................................................................2196
33.6.6.13.2 Function.............................................................................................................. 2196
33.6.6.13.3 Diagram...............................................................................................................2196
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 135
Section number Title Page
33.6.6.13.4 Fields...................................................................................................................2196
33.6.6.14 KX AN LP Base Page Ability 1 (KX_AN_LP_BASE_PG_ABIL1)...................................... 2197
33.6.6.14.1 Offset...................................................................................................................2197
33.6.6.14.2 Function.............................................................................................................. 2197
33.6.6.14.3 Diagram...............................................................................................................2198
33.6.6.14.4 Fields...................................................................................................................2198
33.6.6.15 KX AN LP Base Page Ability 2 (KX_AN_LP_BASE_PG_ABIL2)...................................... 2198
33.6.6.15.1 Offset...................................................................................................................2198
33.6.6.15.2 Function.............................................................................................................. 2199
33.6.6.15.3 Diagram...............................................................................................................2199
33.6.6.15.4 Fields...................................................................................................................2199
33.6.6.16 KX AN XNP Transmit 0 (KX_AN_XNP_TX0)..................................................................... 2199
33.6.6.16.1 Offset...................................................................................................................2199
33.6.6.16.2 Function.............................................................................................................. 2200
33.6.6.16.3 Diagram...............................................................................................................2200
33.6.6.16.4 Fields...................................................................................................................2200
33.6.6.17 KX AN XNP Transmit 1 (KX_AN_XNP_TX1)..................................................................... 2201
33.6.6.17.1 Offset...................................................................................................................2201
33.6.6.17.2 Function.............................................................................................................. 2201
33.6.6.17.3 Diagram...............................................................................................................2201
33.6.6.17.4 Fields...................................................................................................................2201
33.6.6.18 KX AN XNP Transmit 2 (KX_AN_XNP_TX2)..................................................................... 2201
33.6.6.18.1 Offset...................................................................................................................2202
33.6.6.18.2 Function.............................................................................................................. 2202
33.6.6.18.3 Diagram...............................................................................................................2202
33.6.6.18.4 Fields...................................................................................................................2202
33.6.6.19 KX AN LP XNP Ability 0 (KX_AN_LP_XNP_ABIL0)........................................................ 2202
33.6.6.19.1 Offset...................................................................................................................2202
33.6.6.19.2 Function.............................................................................................................. 2202
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
136 NXP Semiconductors
Section number Title Page
33.6.6.19.3 Diagram...............................................................................................................2203
33.6.6.19.4 Fields...................................................................................................................2203
33.6.6.20 KX AN LP XNP Ability 1 (KX_AN_LP_XNP_ABIL1)........................................................ 2204
33.6.6.20.1 Offset...................................................................................................................2204
33.6.6.20.2 Function.............................................................................................................. 2204
33.6.6.20.3 Diagram...............................................................................................................2204
33.6.6.20.4 Fields...................................................................................................................2204
33.6.6.21 KX AN LP XNP Ability 2 (KX_AN_LP_XNP_ABIL2)........................................................ 2204
33.6.6.21.1 Offset...................................................................................................................2204
33.6.6.21.2 Function.............................................................................................................. 2204
33.6.6.21.3 Diagram...............................................................................................................2205
33.6.6.21.4 Fields...................................................................................................................2205
33.6.6.22 KX Backplane Ethernet Status (KX_BP_STAT).................................................................... 2205
33.6.6.22.1 Offset...................................................................................................................2205
33.6.6.22.2 Function.............................................................................................................. 2205
33.6.6.22.3 Diagram...............................................................................................................2205
33.6.6.22.4 Fields...................................................................................................................2206
33.6.6.23 KX Millisecond Count (KX_MS_CNT)..................................................................................2206
33.6.6.23.1 Offset...................................................................................................................2207
33.6.6.23.2 Function.............................................................................................................. 2207
33.6.6.23.3 Diagram...............................................................................................................2207
33.6.6.23.4 Fields...................................................................................................................2207
33.6.7 MDIO_KX_VENDOR_SPEC register descriptions....................................................................................2207
33.6.7.1 MDIO_KX_VENDOR_SPEC Memory map.......................................................................... 2207
33.6.7.2 KX Revision (KX_VND_REV)...............................................................................................2208
33.6.7.2.1 Offset...................................................................................................................2208
33.6.7.2.2 Function.............................................................................................................. 2208
33.6.7.2.3 Diagram...............................................................................................................2208
33.6.7.2.4 Fields...................................................................................................................2208
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 137
Section number Title Page
33.6.7.3 KX Scratch (KX_VND_SCRATCH)...................................................................................... 2209
33.6.7.3.1 Offset...................................................................................................................2209
33.6.7.3.2 Function.............................................................................................................. 2209
33.6.7.3.3 Diagram...............................................................................................................2209
33.6.7.3.4 Fields...................................................................................................................2209
33.6.7.4 KX PCS Interrupt Event (KX_VND_PCS_INT).....................................................................2209
33.6.7.4.1 Offset...................................................................................................................2209
33.6.7.4.2 Function.............................................................................................................. 2210
33.6.7.4.3 Diagram...............................................................................................................2210
33.6.7.4.4 Fields...................................................................................................................2210
33.6.7.5 KX PCS Interrupt Mask (KX_VND_INT_MSK)................................................................... 2210
33.6.7.5.1 Offset...................................................................................................................2210
33.6.7.5.2 Function.............................................................................................................. 2211
33.6.7.5.3 Diagram...............................................................................................................2211
33.6.7.5.4 Fields...................................................................................................................2211
33.6.7.6 KX AN Interrupt Event (KX_VND_AN_INT)....................................................................... 2211
33.6.7.6.1 Offset...................................................................................................................2211
33.6.7.6.2 Function.............................................................................................................. 2211
33.6.7.6.3 Diagram...............................................................................................................2212
33.6.7.6.4 Fields...................................................................................................................2212
33.6.7.7 KX AN Interrupt Mask (KX_VND_AN_INT_MSK)............................................................. 2212
33.6.7.7.1 Offset...................................................................................................................2213
33.6.7.7.2 Function.............................................................................................................. 2213
33.6.7.7.3 Diagram...............................................................................................................2213
33.6.7.7.4 Fields...................................................................................................................2213
33.6.8 MDIO_SGMII register descriptions............................................................................................................ 2214
33.6.8.1 MDIO_SGMII Memory map................................................................................................... 2214
33.6.8.2 SGMII Control (SGMII_CR)...................................................................................................2214
33.6.8.2.1 Offset...................................................................................................................2215
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
138 NXP Semiconductors
Section number Title Page
33.6.8.2.2 Function.............................................................................................................. 2215
33.6.8.2.3 Diagram...............................................................................................................2215
33.6.8.2.4 Fields...................................................................................................................2215
33.6.8.3 SGMII Status (SGMII_SR)......................................................................................................2216
33.6.8.3.1 Offset...................................................................................................................2216
33.6.8.3.2 Function.............................................................................................................. 2217
33.6.8.3.3 Diagram...............................................................................................................2217
33.6.8.3.4 Fields...................................................................................................................2217
33.6.8.4 SGMII PHY Identifier Upper (SGMII_PHY_ID_H).............................................................. 2218
33.6.8.4.1 Offset...................................................................................................................2218
33.6.8.4.2 Function.............................................................................................................. 2218
33.6.8.4.3 Diagram...............................................................................................................2218
33.6.8.4.4 Fields...................................................................................................................2218
33.6.8.5 SGMII PHY Identifier Lower (SGMII_PHY_ID_L).............................................................. 2219
33.6.8.5.1 Offset...................................................................................................................2219
33.6.8.5.2 Function.............................................................................................................. 2219
33.6.8.5.3 Diagram...............................................................................................................2219
33.6.8.5.4 Fields...................................................................................................................2219
33.6.8.6 SGMII Device Ability for 1000Base-X (SGMII_DEV_ABIL_1KBX).................................. 2220
33.6.8.6.1 Offset...................................................................................................................2220
33.6.8.6.2 Function.............................................................................................................. 2220
33.6.8.6.3 Diagram...............................................................................................................2220
33.6.8.6.4 Fields...................................................................................................................2220
33.6.8.7 SGMII Device Ability for SGMII (SGMII_DEV_ABIL_SGMII)..........................................2221
33.6.8.7.1 Offset...................................................................................................................2221
33.6.8.7.2 Function.............................................................................................................. 2221
33.6.8.7.3 Diagram...............................................................................................................2221
33.6.8.7.4 Fields...................................................................................................................2221
33.6.8.8 SGMII Partner Ability for 1000Base-X (SGMII_LP_DEV_ABIL_1KBX)........................... 2222
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 139
Section number Title Page
33.6.8.8.1 Offset...................................................................................................................2222
33.6.8.8.2 Function.............................................................................................................. 2222
33.6.8.8.3 Diagram...............................................................................................................2222
33.6.8.8.4 Fields...................................................................................................................2223
33.6.8.9 SGMII Partner Ability for SGMII (SGMII_LP_DEV_ABIL_SGMII)................................... 2224
33.6.8.9.1 Offset...................................................................................................................2224
33.6.8.9.2 Function.............................................................................................................. 2224
33.6.8.9.3 Diagram...............................................................................................................2224
33.6.8.9.4 Fields...................................................................................................................2224
33.6.8.10 SGMII AN Expansion (SGMII_AN_EXP)............................................................................. 2225
33.6.8.10.1 Offset...................................................................................................................2225
33.6.8.10.2 Function.............................................................................................................. 2225
33.6.8.10.3 Diagram...............................................................................................................2226
33.6.8.10.4 Fields...................................................................................................................2226
33.6.8.11 SGMII Next Page Transmit (SGMII_NP_TX)........................................................................ 2226
33.6.8.11.1 Offset...................................................................................................................2226
33.6.8.11.2 Function.............................................................................................................. 2226
33.6.8.11.3 Diagram...............................................................................................................2226
33.6.8.11.4 Fields...................................................................................................................2227
33.6.8.12 SGMII LP Next Page Receive (SGMII_NP_RX)....................................................................2227
33.6.8.12.1 Offset...................................................................................................................2227
33.6.8.12.2 Function.............................................................................................................. 2227
33.6.8.12.3 Diagram...............................................................................................................2228
33.6.8.12.4 Fields...................................................................................................................2228
33.6.8.13 SGMII Extended Status (SGMII_XTND_STAT)................................................................... 2228
33.6.8.13.1 Offset...................................................................................................................2228
33.6.8.13.2 Function.............................................................................................................. 2229
33.6.8.13.3 Diagram...............................................................................................................2229
33.6.8.13.4 Fields...................................................................................................................2229
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
140 NXP Semiconductors
Section number Title Page
33.6.8.14 SGMII Scratch (SGMII_SCRATCH)...................................................................................... 2229
33.6.8.14.1 Offset...................................................................................................................2229
33.6.8.14.2 Function.............................................................................................................. 2229
33.6.8.14.3 Diagram...............................................................................................................2229
33.6.8.14.4 Fields...................................................................................................................2230
33.6.8.15 SGMII Design Revision (SGMII_REV)..................................................................................2230
33.6.8.15.1 Offset...................................................................................................................2230
33.6.8.15.2 Function.............................................................................................................. 2230
33.6.8.15.3 Diagram...............................................................................................................2230
33.6.8.15.4 Fields...................................................................................................................2230
33.6.8.16 SGMII Link Timer Lower (SGMII_LINK_TMR_L).............................................................. 2231
33.6.8.16.1 Offset...................................................................................................................2231
33.6.8.16.2 Function.............................................................................................................. 2231
33.6.8.16.3 Diagram...............................................................................................................2231
33.6.8.16.4 Fields...................................................................................................................2231
33.6.8.17 SGMII Link Timer Upper (SGMII_LINK_TMR_H).............................................................. 2232
33.6.8.17.1 Offset...................................................................................................................2232
33.6.8.17.2 Function.............................................................................................................. 2232
33.6.8.17.3 Diagram...............................................................................................................2232
33.6.8.17.4 Fields...................................................................................................................2232
33.6.8.18 SGMII IF Mode (SGMII_IF_MODE)..................................................................................... 2232
33.6.8.18.1 Offset...................................................................................................................2232
33.6.8.18.2 Function.............................................................................................................. 2232
33.6.8.18.3 Diagram...............................................................................................................2233
33.6.8.18.4 Fields...................................................................................................................2233
33.6.9 MDIO_QSGMII register descriptions......................................................................................................... 2233
33.6.9.1 MDIO_QSGMII Memory map................................................................................................ 2234
33.6.9.2 QSGMII Control (QSGMII_CR)............................................................................................. 2234
33.6.9.2.1 Offset...................................................................................................................2234
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 141
Section number Title Page
33.6.9.2.2 Function.............................................................................................................. 2234
33.6.9.2.3 Diagram...............................................................................................................2235
33.6.9.2.4 Fields...................................................................................................................2235
33.6.9.3 QSGMII Status (QSGMII_SR)................................................................................................ 2236
33.6.9.3.1 Offset...................................................................................................................2236
33.6.9.3.2 Function.............................................................................................................. 2236
33.6.9.3.3 Diagram...............................................................................................................2236
33.6.9.3.4 Fields...................................................................................................................2237
33.6.9.4 QSGMII PHY Identifier Upper (QSGMII_PHY_ID_H).........................................................2238
33.6.9.4.1 Offset...................................................................................................................2238
33.6.9.4.2 Function.............................................................................................................. 2238
33.6.9.4.3 Diagram...............................................................................................................2238
33.6.9.4.4 Fields...................................................................................................................2238
33.6.9.5 QSGMII PHY Identifier Lower (QSGMII_PHY_ID_L).........................................................2239
33.6.9.5.1 Offset...................................................................................................................2239
33.6.9.5.2 Function.............................................................................................................. 2239
33.6.9.5.3 Diagram...............................................................................................................2239
33.6.9.5.4 Fields...................................................................................................................2239
33.6.9.6 QSGMII Device Ability for SGMII (QSGMII_DEV_ABIL_SGMII).................................... 2239
33.6.9.6.1 Offset...................................................................................................................2239
33.6.9.6.2 Function.............................................................................................................. 2240
33.6.9.6.3 Diagram...............................................................................................................2240
33.6.9.6.4 Fields...................................................................................................................2240
33.6.9.7 QSGMII Partner Ability for SGMII (QSGMII_LP_DEV_ABIL_SGMII)............................. 2241
33.6.9.7.1 Offset...................................................................................................................2241
33.6.9.7.2 Function.............................................................................................................. 2241
33.6.9.7.3 Diagram...............................................................................................................2241
33.6.9.7.4 Fields...................................................................................................................2241
33.6.9.8 QSGMII AN Expansion (QSGMII_AN_EXP)........................................................................2242
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
142 NXP Semiconductors
Section number Title Page
33.6.9.8.1 Offset...................................................................................................................2242
33.6.9.8.2 Function.............................................................................................................. 2242
33.6.9.8.3 Diagram...............................................................................................................2243
33.6.9.8.4 Fields...................................................................................................................2243
33.6.9.9 QSGMII Next Page Transmit (QSGMII_NP_TX).................................................................. 2243
33.6.9.9.1 Offset...................................................................................................................2243
33.6.9.9.2 Function.............................................................................................................. 2243
33.6.9.9.3 Diagram...............................................................................................................2243
33.6.9.9.4 Fields...................................................................................................................2244
33.6.9.10 QSGMII LP Next Page Receive (QSGMII_NP_RX)..............................................................2244
33.6.9.10.1 Offset...................................................................................................................2244
33.6.9.10.2 Function.............................................................................................................. 2244
33.6.9.10.3 Diagram...............................................................................................................2245
33.6.9.10.4 Fields...................................................................................................................2245
33.6.9.11 QSGMII Extended Status (QSGMII_XTND_STAT)..............................................................2245
33.6.9.11.1 Offset...................................................................................................................2245
33.6.9.11.2 Function.............................................................................................................. 2246
33.6.9.11.3 Diagram...............................................................................................................2246
33.6.9.11.4 Fields...................................................................................................................2246
33.6.9.12 QSGMII Scratch (QSGMII_SCRATCH)................................................................................ 2246
33.6.9.12.1 Offset...................................................................................................................2246
33.6.9.12.2 Function.............................................................................................................. 2246
33.6.9.12.3 Diagram...............................................................................................................2246
33.6.9.12.4 Fields...................................................................................................................2247
33.6.9.13 QSGMII Design Revision (QSGMII_REV)............................................................................ 2247
33.6.9.13.1 Offset...................................................................................................................2247
33.6.9.13.2 Function.............................................................................................................. 2247
33.6.9.13.3 Diagram...............................................................................................................2247
33.6.9.13.4 Fields...................................................................................................................2247
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 143
Section number Title Page
33.6.9.14 QSGMII Link Timer Lower (QSGMII_LINK_TMR_L)........................................................ 2248
33.6.9.14.1 Offset...................................................................................................................2248
33.6.9.14.2 Function.............................................................................................................. 2248
33.6.9.14.3 Diagram...............................................................................................................2248
33.6.9.14.4 Fields...................................................................................................................2248
33.6.9.15 QSGMII Link Timer Upper (QSGMII_LINK_TMR_H)........................................................ 2249
33.6.9.15.1 Offset...................................................................................................................2249
33.6.9.15.2 Function.............................................................................................................. 2249
33.6.9.15.3 Diagram...............................................................................................................2249
33.6.9.15.4 Fields...................................................................................................................2249
33.6.9.16 QSGMII IF Mode (QSGMII_IF_MODE)............................................................................... 2249
33.6.9.16.1 Offset...................................................................................................................2249
33.6.9.16.2 Function.............................................................................................................. 2249
33.6.9.16.3 Diagram...............................................................................................................2250
33.6.9.16.4 Fields...................................................................................................................2250
33.7 Initialization/Application Information.......................................................................................................................... 2250
33.7.1 Initialization................................................................................................................................................. 2251
33.7.1.1 1G SGMII................................................................................................................................ 2251
33.7.1.2 2.5G SGMII............................................................................................................................. 2251
33.7.1.3 1000Base-KX...........................................................................................................................2252
33.7.1.4 QSGMII................................................................................................................................... 2253
33.7.1.5 XFI........................................................................................................................................... 2253
33.7.2 Unused Lanes............................................................................................................................................... 2254
33.7.3 Soft Reset and Reconfiguring Procedures................................................................................................... 2254
33.7.3.1 Lane Reset and Reconfiguration.............................................................................................. 2254
33.7.3.2 Lane Enable After Powerdown................................................................................................ 2254
33.7.3.3 PLL Reset and Reconfiguration............................................................................................... 2255
33.7.4 Quiesce Sequences for System Sleep...........................................................................................................2255
Chapter 34
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
144 NXP Semiconductors
Section number Title Page
Serial Peripheral Interface (SPI)
34.1 The SPI module as implemented on the chip................................................................................................................2257
34.1.1 LS1043A SPI signals................................................................................................................................... 2257
34.1.2 LS1043A SPI module integration................................................................................................................ 2257
34.1.3 LS1043A SPI module special consideration................................................................................................2258
34.2 Introduction...................................................................................................................................................................2258
34.2.1 Block Diagram............................................................................................................................................. 2258
34.2.2 Features........................................................................................................................................................ 2259
34.2.3 Interface configurations............................................................................................................................... 2261
34.2.3.1 SPI configuration..................................................................................................................... 2261
34.2.4 Modes of Operation..................................................................................................................................... 2262
34.2.4.1 Master Mode............................................................................................................................ 2262
34.2.4.2 Module Disable Mode..............................................................................................................2262
34.2.4.3 External Stop Mode................................................................................................................. 2262
34.3 Module signal descriptions........................................................................................................................................... 2263
34.3.1 PCS0—Peripheral Chip Select.....................................................................................................................2263
34.3.2 PCS1–PCS3—Peripheral Chip Selects 1–3................................................................................................. 2263
34.3.3 PCS4—Peripheral Chip Select 4..................................................................................................................2264
34.3.4 PCS5/PCSS—Peripheral Chip Select 5/Peripheral Chip Select Strobe.......................................................2264
34.3.5 SCK—Serial Clock...................................................................................................................................... 2264
34.3.6 SIN—Serial Input........................................................................................................................................ 2264
34.3.7 SOUT—Serial Output..................................................................................................................................2264
34.4 Memory Map/Register Definition.................................................................................................................................2265
34.4.1 Module Configuration Register (SPI_MCR)............................................................................................... 2266
34.4.2 Transfer Count Register (SPI_TCR)............................................................................................................2269
34.4.3 Clock and Transfer Attributes Register (In Master Mode) (SPI_CTARn).................................................. 2270
34.4.4 Status Register (SPI_SR)............................................................................................................................. 2275
34.4.5 DMA/Interrupt Request Select and Enable Register (SPI_RSER).............................................................. 2278
34.4.6 PUSH TX FIFO Register In Master Mode (SPI_PUSHR).......................................................................... 2280
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 145
Section number Title Page
34.4.7 POP RX FIFO Register (SPI_POPR).......................................................................................................... 2283
34.4.8 Transmit FIFO Registers (SPI_TXFR)........................................................................................................ 2283
34.4.9 Receive FIFO Registers (SPI_RXFR)......................................................................................................... 2284
34.4.10 Clock and Transfer Attributes Register Extended (SPI_CTAREn).............................................................2284
34.4.11 Status Register Extended (SPI_SREX)........................................................................................................2286
34.5 Functional description...................................................................................................................................................2287
34.5.1 Start and Stop of module transfers............................................................................................................... 2288
34.5.2 Serial Peripheral Interface SPI configuration.............................................................................................. 2289
34.5.2.1 Master mode.............................................................................................................................2289
34.5.2.2 FIFO disable operation.............................................................................................................2290
34.5.2.3 Transmit First In First Out (TX FIFO) buffering mechanism................................................. 2290
34.5.2.3.1 Filling the TX FIFO............................................................................................ 2291
34.5.2.3.2 Draining the TX FIFO........................................................................................ 2291
34.5.2.4 Command First In First Out (CMD FIFO) Buffering Mechanism.......................................... 2291
34.5.2.5 Receive First In First Out (RX FIFO) buffering mechanism...................................................2292
34.5.2.5.1 Filling the RX FIFO............................................................................................2293
34.5.2.5.2 Draining the RX FIFO........................................................................................ 2293
34.5.3 Module baud rate and clock delay generation............................................................................................. 2293
34.5.3.1 Baud rate generator.................................................................................................................. 2294
34.5.3.2 PCS to SCK Delay (tCSC).......................................................................................................2294
34.5.3.3 After SCK Delay (tASC)......................................................................................................... 2295
34.5.3.4 Delay after Transfer (tDT)....................................................................................................... 2295
34.5.3.5 Peripheral Chip Select Strobe Enable (PCSS )........................................................................ 2296
34.5.4 Transfer formats........................................................................................................................................... 2297
34.5.4.1 Classic SPI Transfer Format (CPHA = 0)................................................................................2297
34.5.4.2 Classic SPI Transfer Format (CPHA = 1)................................................................................2298
34.5.4.3 Continuous Selection Format...................................................................................................2299
34.5.4.4 Fast Continuous Selection Format........................................................................................... 2301
34.5.5 Continuous Serial Communications Clock.................................................................................................. 2303
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
146 NXP Semiconductors
Section number Title Page
34.5.6 Parity Generation and Check....................................................................................................................... 2304
34.5.6.1 Parity for SPI Frames............................................................................................................... 2305
34.5.7 Interrupts/DMA requests..............................................................................................................................2305
34.5.7.1 End Of Queue interrupt request............................................................................................... 2306
34.5.7.2 Transmit FIFO Fill Interrupt or DMA Request....................................................................... 2306
34.5.7.3 Command FIFO Fill Interrupt or DMA Request..................................................................... 2307
34.5.7.4 Transmit FIFO Invalid Write Interrupt Request...................................................................... 2308
34.5.7.5 Transfer Complete Interrupt Request.......................................................................................2308
34.5.7.6 Command Transfer Complete Interrupt Request..................................................................... 2308
34.5.7.7 Receive FIFO Drain Interrupt or DMA Request..................................................................... 2308
34.5.7.8 Receive FIFO Overflow Interrupt Request.............................................................................. 2308
34.5.7.9 SPI Frame Parity Error Interrupt Request................................................................................2309
34.5.8 Power saving features.................................................................................................................................. 2309
34.5.8.1 Stop mode (External Stop mode)............................................................................................. 2309
34.5.8.2 Module Disable mode.............................................................................................................. 2309
34.6 Initialization/application information........................................................................................................................... 2310
34.6.1 How to manage queues................................................................................................................................ 2310
34.6.2 Initializing Module in Master Mode............................................................................................................ 2311
34.6.3 Baud rate settings......................................................................................................................................... 2311
34.6.4 Delay settings............................................................................................................................................... 2312
34.6.5 Calculation of FIFO pointer addresses.........................................................................................................2313
34.6.5.1 Address Calculation for the First-in Entry and Last-in Entry in the TX FIFO........................ 2314
34.6.5.2 Address Calculation for the First-in Entry and Last-in Entry in the CMD FIFO.................... 2314
34.6.5.3 Address Calculation for the First-in Entry and Last-in Entry in the RX FIFO........................2315
Chapter 35
Thermal Monitoring Unit (TMU)
35.1 The TMU module as implemented on the chip............................................................................................................ 2317
35.1.1 Local temperature sensor placement............................................................................................................2317
35.1.2 Initialization Information............................................................................................................................. 2317
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 147
Section number Title Page
35.2 Thermal Monitoring Unit Introduction ........................................................................................................................2321
35.2.1 TMU Overview............................................................................................................................................ 2321
35.2.2 Features........................................................................................................................................................ 2322
35.2.3 Modes of Operation..................................................................................................................................... 2323
35.3 TMU register descriptions............................................................................................................................................ 2323
35.3.1 TMU Memory map...................................................................................................................................... 2323
35.3.2 TMU mode register (TMR)..........................................................................................................................2324
35.3.2.1 Offset........................................................................................................................................2324
35.3.2.2 Function................................................................................................................................... 2324
35.3.2.3 Diagram....................................................................................................................................2325
35.3.2.4 Fields........................................................................................................................................ 2325
35.3.3 TMU status register (TSR)...........................................................................................................................2326
35.3.3.1 Offset........................................................................................................................................2326
35.3.3.2 Function................................................................................................................................... 2326
35.3.3.3 Diagram....................................................................................................................................2326
35.3.3.4 Fields........................................................................................................................................ 2326
35.3.4 TMU monitor temperature measurement interval register (TMTMIR).......................................................2327
35.3.4.1 Offset........................................................................................................................................2327
35.3.4.2 Function................................................................................................................................... 2327
35.3.4.3 Diagram....................................................................................................................................2328
35.3.4.4 Fields........................................................................................................................................ 2329
35.3.5 TMU interrupt enable register (TIER)......................................................................................................... 2329
35.3.5.1 Offset........................................................................................................................................2329
35.3.5.2 Function................................................................................................................................... 2329
35.3.5.3 Diagram....................................................................................................................................2329
35.3.5.4 Fields........................................................................................................................................ 2330
35.3.6 TMU interrupt detect register (TIDR)......................................................................................................... 2330
35.3.6.1 Offset........................................................................................................................................2330
35.3.6.2 Function................................................................................................................................... 2331
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
148 NXP Semiconductors
Section number Title Page
35.3.6.3 Diagram....................................................................................................................................2331
35.3.6.4 Fields........................................................................................................................................ 2331
35.3.7 TMU interrupt site capture register (TISCR)...............................................................................................2332
35.3.7.1 Offset........................................................................................................................................2332
35.3.7.2 Function................................................................................................................................... 2332
35.3.7.3 Diagram....................................................................................................................................2332
35.3.7.4 Fields........................................................................................................................................ 2332
35.3.8 TMU interrupt critical site capture register (TICSCR)................................................................................ 2333
35.3.8.1 Offset........................................................................................................................................2333
35.3.8.2 Function................................................................................................................................... 2333
35.3.8.3 Diagram....................................................................................................................................2333
35.3.8.4 Fields........................................................................................................................................ 2333
35.3.9 TMU monitor high temperature capture register (TMHTCR).....................................................................2334
35.3.9.1 Offset........................................................................................................................................2334
35.3.9.2 Function................................................................................................................................... 2334
35.3.9.3 Diagram....................................................................................................................................2334
35.3.9.4 Fields........................................................................................................................................ 2334
35.3.10 TMU monitor low temperature capture register (TMLTCR)...................................................................... 2335
35.3.10.1 Offset........................................................................................................................................2335
35.3.10.2 Function................................................................................................................................... 2335
35.3.10.3 Diagram....................................................................................................................................2335
35.3.10.4 Fields........................................................................................................................................ 2336
35.3.11 TMU monitor high temperature immediate threshold register (TMHTITR)...............................................2336
35.3.11.1 Offset........................................................................................................................................2336
35.3.11.2 Function................................................................................................................................... 2336
35.3.11.3 Diagram....................................................................................................................................2337
35.3.11.4 Fields........................................................................................................................................ 2337
35.3.12 TMU monitor high temperature average threshold register (TMHTATR)..................................................2337
35.3.12.1 Offset........................................................................................................................................2337
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 149
Section number Title Page
35.3.12.2 Function................................................................................................................................... 2338
35.3.12.3 Diagram....................................................................................................................................2338
35.3.12.4 Fields........................................................................................................................................ 2338
35.3.13 TMU monitor high temperature average critical threshold register (TMHTACTR)...................................2339
35.3.13.1 Offset........................................................................................................................................2339
35.3.13.2 Function................................................................................................................................... 2339
35.3.13.3 Diagram....................................................................................................................................2339
35.3.13.4 Fields........................................................................................................................................ 2339
35.3.14 TMU temperature configuration register (TTCFGR).................................................................................. 2340
35.3.14.1 Offset........................................................................................................................................2340
35.3.14.2 Function................................................................................................................................... 2340
35.3.14.3 Diagram....................................................................................................................................2340
35.3.14.4 Fields........................................................................................................................................ 2340
35.3.15 TMU sensor configuration register (TSCFGR)........................................................................................... 2341
35.3.15.1 Offset........................................................................................................................................2341
35.3.15.2 Function................................................................................................................................... 2341
35.3.15.3 Diagram....................................................................................................................................2341
35.3.15.4 Fields........................................................................................................................................ 2341
35.3.16 TMU report immediate temperature site register a (TRITSR0 - TRITSR4)............................................... 2342
35.3.16.1 Offset........................................................................................................................................2342
35.3.16.2 Function................................................................................................................................... 2342
35.3.16.3 Diagram....................................................................................................................................2342
35.3.16.4 Fields........................................................................................................................................ 2342
35.3.17 TMU report average temperature site register a (TRATSR0 - TRATSR4).................................................2343
35.3.17.1 Offset........................................................................................................................................2343
35.3.17.2 Function................................................................................................................................... 2343
35.3.17.3 Diagram....................................................................................................................................2343
35.3.17.4 Fields........................................................................................................................................ 2344
35.3.18 TMU temperature range 0 control register (TTR0CR)................................................................................ 2344
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
150 NXP Semiconductors
Section number Title Page
35.3.18.1 Offset........................................................................................................................................2344
35.3.18.2 Function................................................................................................................................... 2344
35.3.18.3 Diagram....................................................................................................................................2345
35.3.18.4 Fields........................................................................................................................................ 2345
35.3.19 TMU temperature range 1 control register (TTR1CR)................................................................................ 2346
35.3.19.1 Offset........................................................................................................................................2346
35.3.19.2 Function................................................................................................................................... 2346
35.3.19.3 Diagram....................................................................................................................................2347
35.3.19.4 Fields........................................................................................................................................ 2347
35.3.20 TMU temperature range 2 control register (TTR2CR)................................................................................ 2348
35.3.20.1 Offset........................................................................................................................................2348
35.3.20.2 Function................................................................................................................................... 2348
35.3.20.3 Diagram....................................................................................................................................2348
35.3.20.4 Fields........................................................................................................................................ 2349
35.3.21 TMU temperature range 3 control register (TTR3CR)................................................................................ 2349
35.3.21.1 Offset........................................................................................................................................2349
35.3.21.2 Function................................................................................................................................... 2350
35.3.21.3 Diagram....................................................................................................................................2350
35.3.21.4 Fields........................................................................................................................................ 2350
35.4 Functional Description..................................................................................................................................................2351
35.4.1 Monitoring................................................................................................................................................... 2351
35.4.2 Reporting......................................................................................................................................................2352
Chapter 36
Universal Serial Bus Interface 3.0
36.1 Overview.......................................................................................................................................................................2353
36.1.1 Features........................................................................................................................................................ 2354
36.1.2 Modes of Operation..................................................................................................................................... 2354
36.1.3 External Signals........................................................................................................................................... 2354
36.2 USB Memory Map/Register Definition........................................................................................................................2355
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 151
Section number Title Page
36.2.1 Capability Registers Length and HC Interface Version Number (USBx_CAPLENGTH)..........................2370
36.2.2 Host Controller Structural Parameters 1 (USBx_HCSPARAMS1).............................................................2371
36.2.3 Host Controller Structural Parameters 2 (USBx_HCSPARAMS2).............................................................2371
36.2.4 Host Controller Structural Parameters 3 (USBx_HCSPARAMS3).............................................................2372
36.2.5 Host Controller Capability Parameters 1 (USBx_HCCPARAMS1)........................................................... 2373
36.2.6 Doorbell Offset (USBx_DBOFF)................................................................................................................ 2374
36.2.7 Runtime Register Space Offset (USBx_RTSOFF)...................................................................................... 2375
36.2.8 Host Controller Capability Parameters 2 (USBx_HCCPARAMS2)........................................................... 2375
36.2.9 Global SoC Bus Configuration Register 0 (USBx_GSBUSCFG0)............................................................. 2376
36.2.10 Global SoC Bus Configuration Register 1 (USBx_GSBUSCFG1)............................................................. 2381
36.2.11 Global Tx Threshold Control Register (USBx_GTXTHRCFG)................................................................. 2382
36.2.12 Global Rx Threshold Control Register (USBx_GRXTHRCFG)................................................................. 2383
36.2.13 Global Core Control Register (USBx_GCTL).............................................................................................2385
36.2.14 Global Status Register (USBx_GSTS).........................................................................................................2390
36.2.15 Global User Control Register 1 (USBx_GUCTL1)..................................................................................... 2392
36.2.16 Global User ID Register (USBx_GUID)..................................................................................................... 2396
36.2.17 Global User Control Register (USBx_GUCTL).......................................................................................... 2397
36.2.18 Global SoC Bus Error Address Register low (USBx_GBUSERRADDRLO)............................................ 2400
36.2.19 Global SoC Bus Error Address Register high (USBx_GBUSERRADDRHI)............................................ 2401
36.2.20 Global SS Port to Bus Instance Mapping Register - Low (USBx_GPRTBIMAPLO)................................ 2401
36.2.21 Global SS Port to Bus Instance Mapping Register - High (USBx_GPRTBIMAPHI).................................2402
36.2.22 Global Hardware Parameters Register 0 (USBx_GHWPARAMS0)...........................................................2402
36.2.23 Global Hardware Parameters Register 1 (USBx_GHWPARAMS1)...........................................................2404
36.2.24 Global Hardware Parameters Register 2 (USBx_GHWPARAMS2)...........................................................2407
36.2.25 Global Hardware Parameters Register 3 (USBx_GHWPARAMS3)...........................................................2408
36.2.26 Global Hardware Parameters Register 4 (USBx_GHWPARAMS4)...........................................................2411
36.2.27 Global Hardware Parameters Register 5 (USBx_GHWPARAMS5)...........................................................2413
36.2.28 Global Hardware Parameters Register 6 (USBx_GHWPARAMS6)...........................................................2414
36.2.29 Global Hardware Parameters Register 7 (USBx_GHWPARAMS7)...........................................................2416
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
152 NXP Semiconductors
Section number Title Page
36.2.30 Global High-Speed Port to Bus Instance Mapping Register - Low (USBx_GPRTBIMAP_HSLO).......... 2417
36.2.31 Global High-Speed Port to Bus Instance Mapping Register - High (USBx_GPRTBIMAP_HSHI)...........2417
36.2.32 Global USB2 PHY Configuration Register (USBx_GUSB2PHYCFG)......................................................2418
36.2.33 Global USB 3.0 PIPE Control Register (USBx_GUSB3PIPECTL)............................................................2421
36.2.34 Global Transmit FIFO Size Register (USBx_GTXFIFOSIZn)................................................................... 2423
36.2.35 Global Receive FIFO Size Register (USBx_GRXFIFOSIZn).....................................................................2425
36.2.36 Global Event Buffer Address (Low) Register (USBx_GEVNTADRLO)................................................... 2425
36.2.37 Global Event Buffer Address (High) Register (USBx_GEVNTADRHI)....................................................2426
36.2.38 Global Event Buffer Size Register (USBx_GEVNTSIZ)............................................................................ 2427
36.2.39 Global Event Buffer Count Register (USBx_GEVNTCOUNT)................................................................. 2428
36.2.40 Global Hardware Parameters Register 8 (USBx_GHWPARAMS8)...........................................................2428
36.2.41 Global Device TX FIFO DMA Priority Register (USBx_GTXFIFOPRIDEV).......................................... 2429
36.2.42 Global Host TX FIFO DMA Priority Register (USBx_GTXFIFOPRIHST).............................................. 2430
36.2.43 Global Host RX FIFO DMA Priority Register (USBx_GRXFIFOPRIHST).............................................. 2431
36.2.44 Global Host FIFO DMA High-Low Priority Ratio Register (USBx_GDMAHLRATIO).......................... 2432
36.2.45 Global Frame Length Adjustment Register (USBx_GFLADJ)................................................................... 2433
36.2.46 Device Configuration Register (USBx_DCFG)...........................................................................................2434
36.2.47 Device Control Register (USBx_DCTL)..................................................................................................... 2436
36.2.48 Device Event Enable Register (USBx_DEVTEN)...................................................................................... 2441
36.2.49 Device Status Register (USBx_DSTS)........................................................................................................ 2443
36.2.50 Device Generic Command Parameter Register (USBx_DGCMDPAR)......................................................2446
36.2.51 Device Generic Command Register (USBx_DGCMD)...............................................................................2446
36.2.52 Device Active USB Endpoint Enable Register (USBx_DALEPENA)....................................................... 2449
36.2.53 Device Physical Endpoint-n Command Parameter 2 Register (USBx_DEPCMDPAR2n)......................... 2450
36.2.54 Device Physical Endpoint-n Command Parameter 1 Register (USBx_DEPCMDPAR1n)......................... 2451
36.2.55 Device Physical Endpoint-n Command Parameter 0 Register (USBx_DEPCMDPAR0n)......................... 2451
36.2.56 Device Physical Endpoint-n Command Register (USBx_DEPCMDn)....................................................... 2452
36.2.57 OTG Configuration Register (USBx_OCFG)..............................................................................................2454
36.2.58 OTG Control Register (USBx_OCTL)........................................................................................................ 2456
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 153
Section number Title Page
36.2.59 OTG Events Register (USBx_OEVT)......................................................................................................... 2459
36.2.60 OTG Events Enable Register (USBx_OEVTEN)........................................................................................ 2463
36.2.61 OTG Status Register (USBx_OSTS)........................................................................................................... 2466
36.2.62 ADP Configuration Register (USBx_ADPCFG)......................................................................................... 2468
36.2.63 ADP Control Register (USBx_ADPCTL)................................................................................................... 2469
36.2.64 ADP Event Register (USBx_ADPEVT)...................................................................................................... 2471
36.2.65 ADP Event Enable Register (USBx_ADPEVTEN).....................................................................................2473
36.3 USB PHY Memory Map/Register Definition...............................................................................................................2473
36.3.1 SUP_IDCODE_LO (USB_PHY_SSx_IP_IDCODE_LO).......................................................................... 2474
36.3.2 SUP_IDCODE_HI (USB_PHY_SSx_SUP_IDCODE_HI).........................................................................2474
36.3.3 MPLL_LOOP_CTL (USB_PHY_SSx_MPLL_LOOP_CTL).....................................................................2475
36.3.4 LANE0_RX_OVRD_IN_HI (USB_PHY_SSx_LANE0_RX_OVRD_IN_HI).......................................... 2475
36.4 Functional Description..................................................................................................................................................2476
36.4.1 System memory descriptor and data buffers................................................................................................2476
36.4.2 Device descriptor structures.........................................................................................................................2477
36.4.2.1 Structures................................................................................................................................. 2478
36.4.2.1.1 Normal (Control-Data/Bulk/Interrupt), Isochronous, and Status Transfer
Request Block Structure..................................................................................... 2481
36.4.2.1.2 Setup and Status TRB Structure......................................................................... 2482
36.4.2.1.3 Link TRB Structure.............................................................................................2483
36.4.2.1.4 Chaining Buffers (CHN) and Interrupt On Completion (IOC) Usage................2484
36.4.2.1.5 Interrupt on Short Packet (ISP) and Continue on Short Packet (CSP) Usage.... 2490
36.4.2.1.6 Example of Setting Up TRBs............................................................................. 2490
36.4.3 Device Programming Model........................................................................................................................ 2494
36.4.3.1 Register Initialization............................................................................................................... 2494
36.4.3.1.1 Device Power-On or Soft Reset..........................................................................2495
36.4.3.1.2 Initialization on USB reset..................................................................................2496
36.4.3.1.3 Initialization on connect done.............................................................................2497
36.4.3.1.4 Initialization on SetAddress request................................................................... 2497
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
154 NXP Semiconductors
Section number Title Page
36.4.3.1.5 Initialization on SetConfiguration or SetInterface Request................................ 2497
36.4.3.1.6 Alternate Initialization on SetInterface Request................................................. 2498
36.4.3.1.7 Initialization on Disconnect Event......................................................................2499
36.4.3.1.8 Device-initiated disconnect.................................................................................2499
36.4.3.1.9 Reconnect after Device-Initiated Disconnect..................................................... 2499
36.4.3.2 Operational Model................................................................................................................... 2500
36.4.3.2.1 USB and Physical Endpoints.............................................................................. 2500
36.4.3.2.2 Event Buffers...................................................................................................... 2500
36.4.3.2.3 Transfer and Buffer Rules...................................................................................2506
36.4.3.2.3.1 Number of TRBs Rule..................................................................2507
36.4.3.2.3.2 TRB Control Bit Rules................................................................. 2508
36.4.3.2.3.3 Buffer Size Rules and Zero-Length Packets................................ 2509
36.4.3.2.3.4 Transfer setup recommendations..................................................2509
36.4.3.2.4 Transfer Resource Usage and Transfer State......................................................2511
36.4.3.2.5 Transfer Descriptions..........................................................................................2512
36.4.3.2.5.1 Non-Isochronous OUT Transfers................................................. 2513
36.4.3.2.5.2 Isochronous OUT Transfers......................................................... 2514
36.4.3.2.5.3 Non-isochronous IN transfers.......................................................2514
36.4.3.2.5.4 Isochronous IN Transfers............................................................. 2516
36.4.3.2.6 Handling ENDPOINT_HALT............................................................................ 2517
36.4.3.2.7 Handling L1 Event During a Transfer................................................................ 2517
36.4.3.3 Isochronous Transfer Programming Model............................................................................. 2517
36.4.3.3.1 Definitions...........................................................................................................2518
36.4.3.3.2 Endpoint configuration....................................................................................... 2519
36.4.3.3.3 Transfer configuration........................................................................................ 2519
36.4.3.3.4 Starting a Transfer...............................................................................................2520
36.4.3.3.5 Core Behavior During an Interval.......................................................................2521
36.4.3.3.6 Checking interval status......................................................................................2523
36.4.3.3.7 Adding Intervals to a Transfer............................................................................ 2524
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 155
Section number Title Page
36.4.3.3.8 Moderating Events.............................................................................................. 2525
36.4.3.3.9 Other Types of Isochronous Endpoints...............................................................2525
36.4.3.3.9.1 FIFO-based isochronous IN Endpoints........................................ 2525
36.4.3.3.9.2 FIFO-based isochronous OUT Endpoints.................................... 2527
36.4.3.3.10 End a Transfer.....................................................................................................2527
36.4.3.4 Control transfer programming model...................................................................................... 2527
36.4.3.4.1 Two-stage control transfer programming model................................................ 2529
36.4.3.4.2 Three-stage control transfer programming model.............................................. 2529
36.4.3.4.3 Handling fewer requests than wLength.............................................................. 2530
36.4.3.4.4 Control OUT transfer examples..........................................................................2531
36.4.3.4.5 Control IN transfer examples..............................................................................2532
36.4.3.5 Stream handling in SuperSpeed............................................................................................... 2533
36.4.3.5.1 Stream IDs and transfer resources...................................................................... 2534
36.4.3.5.2 Stream selection and stream programming model..............................................2534
36.4.3.5.3 Data movement within a stream......................................................................... 2535
36.4.3.6 Low power operation............................................................................................................... 2536
36.4.3.6.1 Low power operation of USB............................................................................. 2536
36.4.3.6.2 Low power operation of core..............................................................................2537
36.4.3.6.2.1 Clock-Gating Mode...................................................................... 2538
36.4.4 Host programming model............................................................................................................................ 2538
36.4.4.1 Initializing host registers.......................................................................................................... 2538
36.4.4.2 Host controller capability registers.......................................................................................... 2538
36.4.4.3 xHCI implementation details................................................................................................... 2538
36.4.4.3.1 LHCRST behavior.............................................................................................. 2539
36.4.4.3.2 ENT requirements...............................................................................................2539
36.4.4.3.3 Behavior on babble error.................................................................................... 2539
36.4.4.3.4 Max_exit_latency_too_large message................................................................ 2539
36.4.5 Device physical endpoint-specific commands............................................................................................. 2541
36.4.5.1 Command 1: Set endpoint configuration: DEPCFG................................................................2541
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
156 NXP Semiconductors
Section number Title Page
36.4.5.2 Command 2: Set endpoint transfer resource configuration (DEPXFERCFG)........................ 2543
36.4.5.3 Command 3: Get endpoint state (DEPGETSTATE)............................................................... 2544
36.4.5.4 Commands 4 and 5: Set Stall and Clear Stall (DEPSSTALL, DEPCSTALL)........................2544
36.4.5.5 Command 6: Start transfer (DEPSTRTXFER)........................................................................ 2545
36.4.5.6 Command 7: Update transfer (DEPUPDXFER)......................................................................2546
36.4.5.7 Command 8: End transfer (DEPENDXFER)...........................................................................2547
36.4.5.8 Command 9: Start new configuration (DEPSTARTCFG)...................................................... 2548
36.4.6 OTG............................................................................................................................................................. 2549
36.4.6.1 OTG 2.0 for USB 3.0 Functionality.........................................................................................2549
36.4.6.1.1 Core OTG functions............................................................................................2549
36.4.6.1.1.1 HNP Polling and Enable...............................................................2550
36.4.6.1.2 ADP Functions....................................................................................................2550
36.4.6.1.2.1 Internal ADP controller................................................................ 2550
36.4.6.1.3 Software flow......................................................................................................2552
36.4.6.1.3.1 A-Device activity concise flow.................................................... 2553
36.4.6.1.3.2 B-Device activity concise flow.................................................... 2554
36.4.6.1.4 Programming model............................................................................................2555
36.4.6.1.4.1 Initializing global registers........................................................... 2555
36.4.6.1.4.2 Initializing host registers.............................................................. 2556
36.4.6.1.4.3 Initializing device registers...........................................................2556
36.4.6.1.4.4 Initializing OTG registers.............................................................2556
36.4.6.1.4.5 Programming flow for OTG in USB 3.0...................................... 2556
36.4.6.1.5 Common driver tasks.......................................................................................... 2558
36.4.6.1.6 A-Device flow.....................................................................................................2563
36.4.6.1.7 SRP detection by the core (Timeline for ADevSRPDetEvnt)............................ 2569
36.4.6.1.8 VBUS turned ON by the core (Timeline for ADevBSessEndEvnt)................... 2569
36.4.6.1.9 Core entering A-Host in HS/FS mode (Timeline for ADevBHostEvnt)............ 2570
36.4.6.1.10 B-Device flow.....................................................................................................2570
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 157
Section number Title Page
36.4.6.1.11 Core entering b3_us_peripheral in B-Peripheral in HS/FS mode (Timeline for
BDevSessVldDetEvnt)....................................................................................... 2576
36.4.6.1.12 VBUS change detected on USB (Timeline for BDevVBusChngEvnt).............. 2576
36.4.6.1.13 Internal ADP controller logic..............................................................................2576
36.4.7 Initialization/application information.......................................................................................................... 2577
36.4.8 Power management overview...................................................................................................................... 2577
36.4.8.1 Clock gating............................................................................................................................. 2578
36.4.8.2 Hardware-Controlled LPM...................................................................................................... 2579
36.4.8.2.1 Special consideration for OTG........................................................................... 2579
Chapter 37
Watchdog Timer (WDOG)
37.1 Overview.......................................................................................................................................................................2581
37.1.1 Features........................................................................................................................................................ 2582
37.2 Clocks........................................................................................................................................................................... 2583
37.3 Functional description...................................................................................................................................................2583
37.3.1 Timeout event.............................................................................................................................................. 2583
37.3.1.1 Servicing WDOG to reload the counter................................................................................... 2584
37.3.2 Interrupt event ............................................................................................................................................. 2584
37.3.3 Operations.................................................................................................................................................... 2584
37.3.3.1 Watchdog reset generation.......................................................................................................2584
37.3.4 Reset (HRESET_B)..................................................................................................................................... 2585
37.3.5 Interrupt........................................................................................................................................................2585
37.3.6 Flow Diagrams............................................................................................................................................. 2585
37.4 Initialization.................................................................................................................................................................. 2587
37.5 WDOG Memory Map/Register Definition................................................................................................................... 2588
37.5.1 Watchdog Control Register (WDOGx_WCR).............................................................................................2588
37.5.2 Watchdog Service Register (WDOGx_WSR)............................................................................................. 2590
37.5.3 Watchdog Reset Status Register (WDOGx_WRSR)................................................................................... 2590
37.5.4 Watchdog Interrupt Control Register (WDOGx_WICR)............................................................................ 2591
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
158 NXP Semiconductors
Chapter 1
Overview
1.1 Introduction
The LS1043A QorIQ advanced multicore processor combines two to four Arm®
Cortex®-v8 A53 cores with datapath acceleration optimized for L2/3 packet processing,
single pass security offload, robust traffic management, and quality of service.
This advanced quad-core 64-bit Arm processor is ideal for applications such as, branch
and enterprise routers, switches, firewall, packet filtering processors, and general-purpose
embedded computing applications. The high level of integration delivers significant
performance benefits, such as 10 GbE, mulitple USB 3.0 interfaces, single source clock.
Arm® Cortex ®-A53
ARM Cortex-
ARM
64-bit Cortex-
Core
A53 64b Cores
A53 ARM
64b Cores
Cortex-
A53
ARM64b Cores
Cortex-
32 KB 32 KB
32 KB A53 64b 32 KB
Cores
32 KB
D-Cache 32 KB
I-Cache
D-Cache I-Cache
D-Cache
32 KB I-Cache
32 KB 32-bit
D-Cache I-Cache DDR3L/4
Memory Controller
1 MB L2 - Cache
Secure Boot
Trust Zone CCI-400™ Coherency Fabric
Power Management SMMUs
IFC, QuadSPI, SPI
Security Real Time Debug
SD/SDIO/eMMC Queue Frame Manager
Engine
Manager
PCI Express 2.0
PCI Express 2.0
PCI Express 2.0
(SEC)
QUICC Engine
DMA
Parse, classify, Watchpoint
SATA 3.0
Cross
2x DUART distribute Trigger
4x I2C, 4x GPIO
Perf Trace
Buffer 1G 1G 1G 1/2.5G Monitor
8x FlexTimer Manager
1G 1G 1/2.5/10G
3x USB3.0 w/PHY
6x LPUART DPAA Hardware
4-Lane, 10 GHz SerDes
Core Complex
Accelerators and Memory Control
Basic Peripherals, Interconnect and Debug
Networking Elements
Figure 1-1. Block diagram
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 159
Features summary
1.2 Features summary
This chip includes the following distinctive functions and features:
• Arm® Cortex®-v8 A53 (64-bit) with the following capabilities:
• Speed up to 1.6 GHz
• 32 KB L1 instruction cache and data cache for each core (ECC protection)
• Neon SIMD co-processor
• Arm v8 cryptography extensions
• 1 MB unified I/D L2 cache (ECC protection)
• Hierarchical interconnect fabric
• Hardware managed data coherency
• Up to 400 MHz operation
• Up to 400 MHz operation
• One 32-bit DDR3L/DDR4 SDRAM memory controller
• ECC and interleaving support
• Up to 1.6 GT/s
• Data path acceleration architecture (DPAA) incorporating acceleration for the
following functions:
• Packet parsing, classification, and distribution (FMan)
• Queue management for scheduling, packet sequencing, and congestion
management (QMan)
• Hardware buffer management for buffer allocation and de-allocation (BMan)
• Cryptography acceleration (SEC)
• Parallel Ethernet interfaces
• Up to two RGMII interfaces
• Four SerDes lanes for high-speed peripheral interfaces
• Three PCI Express controllers, supporting x4 operation
• One Serial ATA (SATA 3.0) controller
• Up to four SGMII supporting 1000 Mbps
• Up to two SGMII supporting 2500 Mbps
• Up to one XFI (10GbE) interface
• Up to one QSGMII
• Supports 1000Base-KX
• IEEE® 1588 support
• Supports full-duplex mode only
• Additional peripheral interfaces:
• One quad serial peripheral interface (QuadSPI) controller and one serial
peripheral interface (SPI) controller
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
160 NXP Semiconductors
Chapter 1 Overview
• Integrated flash controller (IFC) supporting NAND and NOR flash with 28-bit
addressing and 16-bit data interface
• Three USB 3.0 controllers with integrated PHY
• One enhanced secure digital host controller (eSDHC) supporting SD 3.0, eMMC
4.4 and eMMC 4.5 modes
• One QUICC engine (QE) block supporting TDM/HDLC
• Four I2C controllers
• Two 16550 compliant DUARTs, and six low power UARTs (LPUART)
• Four general-purpose I/O (GPIO)
• Eight FlexTimers/PWMs
• Five Watchdog timer
• Trust Architecture
• Debug supporting run control, data acquisition, high-speed trace, and
performance/event monitoring
1.3 Application examples
The LS1043A core processors are very flexible and can be configured to meet many
system application needs. The cores can be configured to be used in either a symmetric or
asymmetric multiprocessing modes. For example, cores configured in asymmetric
multiprocessing mode can be used in the case where each core runs operating systems
independently, or in the case where each core performs separate tasks. This flexibility
enables application developers to assign distinct processing resources to distinct tasks
that need guaranteed performance.
The value proposition of this chip is further enhanced by a high degree of peripheral
integration of system controllers such as, DDR4 controller, data path acceleration
architecture (DPAA). The DPAA offloads packet parsing, classification, traffic
management, and quality of service.
1.3.1 Multi-service branch office router
The chip allows for a low cost, feature dense, passively cooled branch office router
design, which features hardware processing for advanced data path off load and has quad-
core Arm 64-bit processors for high touch data and control path applications. It also
supports hardware enabled virtualization elements for 3rd party applications. LS1043A
also delivers the CPU bandwidth needed for next generation wired and wireless
virtualized router platforms supporting SDN and NFV applications while maintaining
high performance VPN links to the cloud.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 161
Application examples
FLASH DDR3L/4
Management
LS1043A
MII/RGMII USB 3.0 LTE module
A53 A53
PCl Express WiFi module
USB 3.0 802.11ac
A53 A53 WiFi module WLAN
PCl Express
4x1 or USB 3.0 SDD/HDD
QSGMII/ or SATA 3.0
10 GbE XFI Security and packet
PHY processing
Up to 6x GbE IPSec, SSL Frag /
interfaces: 1x GE Reassembly,
RGMII
QSGMII and 2x RGMII PHY Classification,
QoS Legacy WAN
GE (HDLC, ISDN)
RGMII or TDM
PHY QE
Figure 1-2. Multi-service branch office router
1.3.2 Security appliance/UTM
In the security appliance space the chip comes with the option for 5 Gbps single pass
cryptographic offload and 10 Gbps data path parse, classification and distribution which
helps in delivering flows to cores for additional security processing. With quad-core
design, the chip can run deep packet inspection, SPI firewall and IDS/IPS within a single
low cost chip.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
162 NXP Semiconductors
Chapter 1 Overview
FLASH DDR3L/4
Management
LS1043A
MII/RGMII
A53 A53
mPCl Express WiFi Module
USB 3.0 802.11ac
A53 A53 WLAN
mPCl Express WiFi Module
Quad
PHY
Ethernet XFI or 2.5G USB 3.0 SDD/HDD
Switch SGMII or SATA 3.0
Quad Security and Packet
PHY Processing
IPSec, SSL Frag /
GE RGMII Reassembly,
PHY Classification,
QoS
GE RGMII
PHY
Figure 1-3. Security appliance/UTM application diagram
1.4 Module features
This section contains a high level view of the chip architecture.
1.4.1 Arm® Cortex®-A53 core
The Arm® Cortex®-A53 processor is an extremely power efficient Armv8 processor
capable of supporting 32-bit and 64-bit code seamlessly. It makes use of a highly
efficient 8-stage in-order pipeline balanced with advanced fetch and data access
techniques for performance.
The multicore processing provides the ability for any of the four component processors,
within a cluster, to shut down when not in use, for instance when the chip is in standby
mode, to save power. When higher performance is required, every processor is in use to
meet the demand while still sharing the workload to keep power consumption as low as
possible.
The LS1043A features four high-performance Cortex A53 cores:
• 64 and 32-bit execution states for scalable high performance
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 163
Module features
• Multiple coherent SMP processor clusters through AMBA® 4 technology
• New instruction set, A64
• In-order pipeline with symmetric dual-issue of most instructions
• 32KB Instruction cache, 32 KB data cache, 1MB unified L2 cache.
• NEON technology - Accelerates multimedia and signal processing algorithms such
as video encode/decode, 2D/3D graphics, gaming, audio and speech processing,
image processing, telephony, and sound synthesis. Also useful in accelerating
floating point code with SIMD execution.
• Hardware-accelerated cryptography - 3x-10x better software encryption performance
Useful for small granule decrypt/encrypt too small to efficiently offload to HW
accelerator
• Floating point unit - Hardware support for floating point operations in half-, single-
and double-precision floating point arithmetic. IEE754-2008 enhancements are
included.
• TrustZone® Technology - Ensures reliable implementation of security applications
ranging from digital rights management to electronic payment.
• Double Precision Floating Point SIMD - Allows SIMD vectorisation to be applied to
a much wider set of algorithms (for example scientific / High Performance
Computing (HPC) and supercomputer).
• 64-bit Virtual address reach - Enables virtual memory beyond 4GB 32b limit.
Important for modern desktop and server software using memory mapped file I/O,
sparse addressing.
• Enhanced Cache management - User space cache operations improve dynamic code
generation efficiency, Data Cache Zero for fast clear.
• Extensive power-saving features - Hierarchical clock gating, power domains,
advanced retention modes
• Hardware virtualization support
• NEON SIMD extensions onboard (per core)
1.4.2 System memory management unit MMU-500
The MMU-500 is a system-level memory management Unit (MMU) that translates an
input address to an output address, by performing one or more translation table walks.
It supports the translation table formats defined by the Arm architecture, and can perform
• Stage 1 translations that translate an input Virtual Address (VA) to an output
Physical Address (PA) or Intermediate Physical Address (IPA).
• Stage 2 translations that translate an input IPA to an output PA.
• Combined stage 1 and stage 2 translations that translate an input VA to an output
IPA, and then translate that IPA to a PA. The MMU-500 performs a translation table
walk for each stage of the translation.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
164 NXP Semiconductors
Chapter 1 Overview
The purpose of separating the process into 2 stages is to allow the guest OS to control the
address translation between VA and what it “thinks” is the PA, while the hypervisor
controls the translation from IPA to PA. This split process allows the hypervisor to
separate the resources of different Virtual Machines (VMs). Address translation is
performed both in the cores and also for IO devices, using the SMMU.
The MMU-500 is a distributed SMMU, which makes use of one central controller (TCU)
and up to 32 translation units (TBUs). In this chip there is a single TCU, supporting a
total of 4 TBUs.
1.4.3 Arm CoreLink CCI-400 cache coherent interconnect
The CCI-400 combines interconnect and coherency functions into a single module. The
CCI-400 cache coherent interconnect is an infrastructure component that supports:
• Data coherency between both Cortex-A53 cores and all I/O masters with three
independent Points-of-Serialization (PoS) and full barrier support high-bandwidth,
cross-bar interconnect functionality between the masters and up to three slaves
• DVM message transport between masters
• Quality-of-Service (QoS) regulation for shaping traffic profiles
• Performance monitoring unit (PMU) to count performance-related events
• Programmers view (PV) to control the coherency and interconnect functionality
1.4.4 PreBoot loader (PBL) and nonvolatile memory interfaces
The PBL functions include the following:
• Simplifies boot operations, replacing pin strapping resistors with configuration data
loaded from nonvolatile memory
• Uses the configuration data to initialize other system logic and to copy data from low
speed memory interfaces IFC, QuadSPI, and SD/eSDHC/eMMC) into fully
initialized DDR or OCRAMs.
• Releases CPU 0 from reset, allowing the boot processes to begin from fast system
memory
The nonvolatile memory interfaces accessible by the PBL are described in the subsequent
sections. These interfaces may be accessed by software running on the CPUs. these are
not dedicated to the PBL. Note that the integrated flash controller (IFC) can be used for
both volatile (SRAM) and nonvolatile memory, as well as a control and low performance
data port for external memory-mapped devices.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 165
Module features
1.4.5 DDR memory controllers
The DDR memory controller supports DDR3L and DDR4 SDRAM. The memory
interface controls main memory accesses and supports a maximum of 32 GB of main
memory. The chip supports chip-select interleaving within the controller.
The DDR memory controller can be configured to retain the currently active SDRAM
page for pipe-lined burst accesses. Page mode support of up to 32 simultaneously open
pages can dramatically reduce access latencies for page hits. Using ECC, the chip detects
and corrects all single-bit errors and detects all double-bit errors and all errors within a
nibble.
In addition, the DDR controller offers an initialization bypass feature for use by system
designers to prevent reinitialization of main memory during system power-on after an
abnormal shutdown. The DDR controller also supports active zeroization of system
memory upon detection of a user-defined security violation.
1.4.6 Enhanced direct memory access (eDMA) and direct
memory access multiplexer (DMAMUX)
It has the following general features:
• 32 channels support independent 8-, 16- or 32-bit single value or block transfers
• Supports variable sized queues and circular queues
• Source and destination address registers are independently configured to post
increment or remain constant
• Each transfer is initiated by a peripheral, CPU, periodic timer interrupt or eDMA
channel request
• Each DMA channel can optionally send an interrupt request to the CPU on
completion of a single value or block transfer
• DMA transfers possible between system memories, General Purpose I/Os (GPIOs)
and Slave Peripherals that support DMA
• Programmable DMAMUX allows assignment of any DMA source to any available
DMA channel with up to a total of 64 potential request sources
The DMA channel request can be initiated by the following peripherals:
• 4x I2C
• 6x LPUART
• 1x SPI
• QuadSPI
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
166 NXP Semiconductors
Chapter 1 Overview
The DMA requests from these peripherals are connected to eDMA through DMAMUX
and the implmentation details can be found in LS1043A DMAMUX module special
consideration.
The DMAMUX selects from many DMA requests down to 16 for the DMA controller.
There are 2 DMAMUXs associated with each 32-channel DMA.
1.4.7 DUART
The DUART supports full-duplex operation and is compatible with the PC16450 and
PC16550 programming models. All the transmitter and receiver support 16-byte FIFOs.
1.4.8 FlexTimer module (FTM)
The key features of the FTM are as follows:
• Selectable FTM source clock and programmable prescaler
• 16-bit counter supporting free-running or initial/final value and counting is up or up-
down
• Input capture, output compare, edge aligned and center aligned PWM modes
• Operation of FTM channels as pairs with equal outputs, pairs with complimentary
outputs, or independent channels with independent outputs
• Deadtime insertion is available for each complementary pair
• Generation of hardware triggers
• Software control of PWM outputs
• Up to 4 fault inputs for global fault control
• Configurable channel polarity
• Programmable interrupt on input capture, reference compare, overflowed counter or
detected fault condition
• Quadrature decoder with input filters, relative position counting and interrupt on
position count or capture of position count on external event
• DMA support for FTM event
1.4.9 Integrated flash controller (IFC)
The integrated flash controller (IFC) is used to interface with external asynchronous
NAND flash, asynchronous NOR flash, SRAM, generic ASIC memories, and EPROM.
The IFC has the following general features:
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 167
Module features
• Flash controller with seven chip-selects
• Functional multiplexing of pins between NAND, NOR, and GPCM
• Supports memory banks of sizes up to 256 MB (for NOR and GPCM)
• Write-protection capability for NAND and NOR devices
• External transceiver enable/disable control on per-bank basis
1.4.9.1 IFC NAND flash controller features
The IFC NAND Flash controller has the following features:
• Support for x8/x16 SLC/MLC NAND flash devices with page sizes up to 8 KB
• Support for ONFI-2.2 asynchronous interface (8-/16-bit)/NVDDR interface and
mandatory commands
• 4-/8-/24-/40-bit ECC generation/checking
• Flexible timing control to allow interfacing with proprietary NAND devices
• Boot chip-select (CS0) available for NAND Flash at system reset
• Execute-in-place boot loading from NAND Flash (in asynchronous mode)
1.4.9.2 IFC NOR flash controller features
The IFC NOR Flash controller has the following features:
• Supports x8/x16 asynchronous NOR Flash devices
• Supports address data multiplexed (ADM) NOR devices
• Flexible timing control allows interfacing with proprietary NOR devices
• Boot chip-select (CS0) available for NOR flash at system reset
1.4.9.3 IFC GPCM controller features
The IFC general-purpose, chip-select controller (GPCM) supports operation in either
normal or generic ASIC modes. Normal mode operation has the following features:
• Support for x8/x16-bit devices
• Compatible with general-purpose, addressable device such as SRAM and ROMs
• External clock is supported with programmable division ratio
• Output enable signal (OE)
• Byte-write enable signals
• Even/Odd parity on data bus
• External access termination signal
• Burst support in GPCM
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
168 NXP Semiconductors
Chapter 1 Overview
General ASIC mode operation has the following features:
• Support for x8/x16 bit devices with shared address/data bus using the following
address and data sequences:
• 16 bit I/O: AADD
• 8 bit I/O : AAAADDDD
• Supports configurable even/odd parity and parity error detection on address/data bus
1.4.10 Universal Serial Bus (USB) controllers and PHY
The USB3.0 controllers provides point-to-point connectivity conforming to the Universal
Serial Bus revision 3.0 specification. The USB controller and integrated PHY can be
configured to operate as a stand-alone host, stand-alone device, or with both host and
device functions operating simultaneously.
The host and device functions are configured to support the following types of USB
transfers:
• Bulk
• Control
• Interrupt
• Isochronous
Key features of the USB controller include the following:
• OTG 2.0
• USB dual-role operation and can be configured as host or device
• Operation as a stand-alone USB device
• One upstream facing port
• Six programmable USB endpoints
• Operation as a stand-alone USB host controller
• USB root hub with one downstream-facing port
• Enhanced host controller interface (EHCI) compatible
• Super-speed (5 GT/s), High-speed (480 Mbps), and full-speed (12 Mbps) operations.
1.4.11 High speed I/O interfaces
The chip supports the SGMII, PCI Express 2.0 controller, and SATA high-speed I/O
interface standards.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 169
Module features
1.4.11.1 Serial ATA (SATA) controller
The SATA controller is compliant with the Serial ATA 3.0 Specification. The SATA
controller has the following features:
• Supports speeds: 1.5 Gbps (first-generation SATA), 3 Gbps (second-generation
SATA), and 6 Gbps (third-generation SATA)
• Single SATA 3.0 controller with chip-level interface
• Supports asynchronous notification and hot-plug
NOTE
This hot-plug capabilities are supported at generation 1 and
generation 2 speeds.
• Asynchronous signal recovery
• Link power management
• Native command queuing
• Staggered spin-up
• Port multiplier support
• Standard ATA master-only emulation
• Contain ATA shadow registers
• SATA superset registers
• SError, SControl, SStatus
• Interrupt driven
• Contains Power management support
• Supports error handling and diagnostic features
• Far-end/near-end loopback
• Failed CRC error reporting
• Increased ALIGN insertion rates
• Scrambling and CONT override
1.4.11.2 PCI Express
Each of the three PCI Express is compatible with the PCI Express Base Specification
Revision 3.0. Key features of the PCI Express interface include the following:
• Power-on reset configuration options allow root complex functionality
• The physical layer operates at 2.5 or 5 Gbps data rate per lane
• Receive and transmit ports operate independently, with an aggregate theoretical
bandwidth of 32 Gbps
• x4, x2, and x1 link widths support
• Both 32- and 40-bit addressing and 256-byte maximum payload size
• Full 64-bit decode with 36-bit wide windows
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
170 NXP Semiconductors
Chapter 1 Overview
• Inbound INTx transactions
• Message Signaled Interrupt (MSI) transactions
1.4.11.3 SGMII
The serial gigabit media independent interface (SGMII) is a high-speed interface linking
the Ethernet controller with an Ethernet PHY. SGMII uses differential signaling for
electrical robustness. Only four signals are required: receive data and its inverse, and
send data and its inverse; no clock signals are required.
1.4.12 QUICC Engine (QE)
Single 32-bit RISC controller for flexible support of communications peripherals
• Serial DMA channel for reception and transmission on all serial channels
• Two UCCs supporting the following interfaces (not all of them simultaneously):
• Serial
• UART
• Asynchronous HDLC (256 Channels) (bit rate up to 2 Mbps)
• TDM interfaces supporting up to 128 QUICC multichannel controller channels
1.4.13 Enhanced secure digital host controller and SDIO
Detailed features of the SD/eSDHC/eMMC controller include the following:
• Conforms to the SD host controller standard specification version 3.0
• Compatible with the MMC system specification version 4.5
• Compatible with the SD memory card physical layer specification version 3.01
• Compatible with the SD - SDIO card specification version 2.0
• Designed to work with eMMC devices as well as SD memory, SDIO, and SD combo
cards and their variants
• Supports SD UHS-1 speed modes
1.4.14 Security Engine (SEC)
The SEC is the chip's security engine, which serves as the latest cryptographic
acceleration and offloading hardware. It combines functions previously implemented in
separate modules to create a modular and scalable acceleration and assurance engine. It
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 171
Module features
also implements block encryption algorithms, stream cipher algorithms, hashing
algorithms, public key algorithms, run-time integrity checking, and a hardware random
number generator. SEC performs higher-level cryptographic operations than previous
cryptographic accelerators. This provides significant improvement to system level
performance. SEC includes the following interfaces:
• A slave bus interface for the processor to write configuration and command
information, and to read status information
• A bus master interface that allows SEC to read/write data from external memory
• A Queue Manager interface that allows SEC to accept jobs directly from the Queue
Manager module
The SEC provides the following functions:
• DMA for bus master operation
• Job Queue Controller with four Job Rings
• Descriptor Controllers (DECOs)
• Responsible for executing descriptors and managing sequencing of keys,
context, and data through the various CHAs
• Performs header and trailer processing as defined by the descriptor
• Run-Time Integrity Checker (RTIC)
• Crypto Hardware Accelerators (CHAs)
• Public Key Hardware Accelerator (PKHA)
• Random Number Generator
• Advanced Encryption Standard Accelerator (AESA)
• Message Digest Hardware Accelerator (MDHA)
• SNOW 3G f8 Hardware Accelerator (SNOW f8)
• SNOW 3G f9 Hardware Accelerator (SNOW f9)
• ZUC Encryption Accelerator (ZUCE)
• ZUC Authentication Accelerator (ZUCA)
• Data Encryption Standard Hardware Accelerator (DESA)
• Cyclic-Redundancy Check Accelerator (CRCA)
• Kasumi f8 and f9 Hardware Accelerator (KFHA)
1.4.15 Inter-Integrated Circuit (I2C)
The I2C allows communication between a number of devices.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
172 NXP Semiconductors
Chapter 1 Overview
1.4.16 Low Power Universal asynchronous receiver/ transmitter
(LPUART)
The chip supports the asynchronous serial bus communication interface with
programmable 8- or 9-bit data format and support of CEA709.1-B (LON), ISO 7816
smart card interface.
1.4.17 Quad Serial Peripheral Interface (QuadSPI)
The QuadSPI has the following general features:
• Interface for up to two external quad serial flash memories for code/data storage and
code execution
• Supports industry standard: Single, dual and quad mode serial flashes
1.4.18 Queue Direct Memory Access Controller (qDMA)
The qDMA controller transfers blocks of data between one source and one or more
destinations. The blocks of data transferred can be represented in memory as contiguous
or non-contiguous using scatter/gather table(s).
The qDMA supports following general features:
• Supports channel virtualization through enqueuing of DMA jobs to, or dequeuing
DMA jobs from, different work queues
• Supports four virtualized blocks for multi core support
• Supports 8 command queues and one status queue per virtualized blocks
• Supports PQ3 legacy direct mode through register interface
If the qDMA is operating in a mixed command queue/legacy mode, legacy mode jobs
will be serviced with highest priority as soon as an engine becomes available.
The qDMA is a high performance DMA and can be used for data transfers between DDR
to DDR, DDR to PCI Express for outbound transactions and DDR to memory-mapped
flash interfaced through IFC.
1.4.19 Serial Peripheral Interface (SPI)
The chip supports the synchronous serial bus for communication to an external device.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 173
Module features
The module supports the following features:
• Full-duplex, three-wire synchronous transfers
• Buffered transmit operation using the transmit first in first out (TX FIFO) with depth
of 16 entries
• Support for 8/16-bit accesses to the PUSH TX FIFO register data field
• Buffered receive operation using the receive FIFO (RX FIFO) with depth of 16
entries
• Asynchronous clocking scheme for register and protocol interfaces
1.4.20 Watchdog Timer (WDOG)
The WDOG module monitors internal system operation and forces a reset in case of
failure. It operates on RTC 32 KHz clock. The chip supports five WDOGs, out of which
one is dedicated for Trustzone support and other four are for A53 cores (one for each core
in the cluster).
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
174 NXP Semiconductors
Chapter 2
Memory Map
2.1 Memory map overview
There are several address domains within the chip, including the following:
• Logical, virtual, and physical (real) address spaces within the Arm Architecture
core(s)
• Internal configuration, control, and status register (CCSR) address space, which is a
special-purpose subset of the internal local address space
NOTE
SCFG_ALTCBAR refers to the higher address bits of the
complete CCSR address space, it refers to 01 as the higher
address.
• Internal debug control and status register (DCSR) address space, which is another
special-purpose set of registers mapped in the internal local address space
• External memory, I/O, and configuration address spaces of the PCI Express links
The MMU in the core handles translation of logical (effective) addresses, into virtual
addresses, and ultimately to the physical addresses for the address space. The MMU is
described in the core reference manual. When the MMU is configured, the size of the
chip's address space is 40-bits providing access to 1 TB; otherwise the address space is
32-bits providing access to 4 GB.
2.2 Fixed memory map
This table shows the system memory map for the chip.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 175
Fixed memory map
Table 2-1. System memory map
Start Address Module Name Size Accessible with x-bit addressing
(Hex)
32 36 40
00_0000_0000 Secure Boot ROM 1 MB Y Y Y
00_0010_0000 Extended Boot 15 MB Y Y Y
ROM
00_0100_0000 CCSR Register 240 MB Y Y Y
Space
00_1000_0000 OCRAM1 64 KB Y Y Y
00_1001_0000 OCRAM2 64 KB Y Y Y
00_1004_0000 Reserved 65408 KB Y Y Y
00_1100_0000 Reserved 16 MB Y Y Y
00_1200_0000 STM 16 MB Y Y Y
00_1300_0000 Reserved 208 MB Y Y Y
00_2000_0000 DCSR 64 MB Y Y Y
00_2400_0000 Reserved 448 MB Y Y Y
00_4000_0000 QuadSPI 512 MB Y Y Y
00_6000_0000 IFC region 512 MB Y Y Y
1(0-512MB)
00_8000_0000 DRAM11 (0-2GB) 2 GB Y Y Y
01_0000_0000 Reserved 0.0625 GB N Y Y
01_0400_0000 Reserved 3.9375 GB N Y Y
02_0000_0000 Reserved 1 GB N Y Y
02_4000_0000 Reserved 7 GB N Y Y
04_0000_0000 Reserved 0.25 GB N Y Y
04_1000_0000 Reserved 0.25 GB N Y Y
04_2000_0000 Reserved 0.25 GB N Y Y
04_3000_0000 Reserved 1.25 GB N Y Y
04_8000_0000 Reserved 2 GB N Y Y
05_0000_0000 QMAN S/W Portal 128 MB N Y Y
05_0800_0000 BMAN S/W Portal 128 MB N Y Y
05_1000_0000 Reserved 4 GB - 256 MB N Y Y
06_0000_0000 Reserved 0.5 GB N Y Y
06_2000_0000 IFC region 2 3.5 GB N Y Y
(512MB-4GB)
07_0000_0000 Reserved 4 GB N Y Y
08_0000_0000 Reserved 2 GB N Y Y
08_8000_0000 DRAM2 1 30 GB N Y Y
10_0000_0000 Reserved 64 GB N Y Y
20_0000_0000 Reserved 128 GB N N Y
40_0000_0000 PCI Express 1 32 GB N N Y
48_0000_0000 PCI Express 2 32 GB N N Y
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
176 NXP Semiconductors
Chapter 2 Memory Map
Table 2-1. System memory map (continued)
Start Address Module Name Size Accessible with x-bit addressing
(Hex)
32 36 40
50_0000_0000 PCI Express 3 32 GB N N Y
58_0000_0000 Reserved 160 GB N N Y
80_0000_0000 Reserved 32 GB N N Y
88_0000_0000 DRAM3 1 480 GB N N Y
(32-512GB)
1. DRAM addresses are remapped, refer section DDR remapping.
2.2.1 DDR remapping
The following table remaps the DDR address to the following physical DRAM address.
This remapped DRAM addresses are seen by the DDR controller.
NOTE
The chip's physical memory mapping defines two or more
memory mapped segments for DDR memory. To achieve larger
than 2 GB of DDR memory on a single chip select and to create
a contiguous memory space to interleave DDR memory, a
remapping logic is implemented. The remapping logic resides
between the chip and DDR. The remapping logic, re-maps the
chip-mapped DDR physical address to DDR address and vice
versa. The remapping logic is not visible or configurable by
software.
Table 2-2. LS1043A Memory Address Remapping
Chip address Segment Size Remapped DRAM address
00_8000_0000 - 00_FFFF_FFFF 5-8 (DRAM region 2 GB 00_0000_0000 to 00_7FFF_FFFF
1)
08_0000_0000 - 08_7FFF_FFFF 12 (Reserved) 2 GB 00_0000_0000 to 00_7FFF_FFFF
08_8000_0000 - 0F_FFFF_FFFF 12 (DRAM region 30 GB 00_8000_0000 to 07_FFFF_FFFF
2)
80_0000_0000 - 87_FFFF_FFFF 16 (Reserved) 32 GB 00_0000_0000 to 07_FFFF_FFFF
88_0000_0000 - FF_FFFF_FFFF 16 (DRAM region 480 GB 08_0000_0000 to 7F_FFFF_FFFF
3)
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 177
CCSR address map
2.3 CCSR address map
The following table lists the base address assigned to each block from the base of the 240
MB CCSR space.
NOTE
Arm® Cortex®-A53 is little endian.
Table 2-3. CCSR Block Base Address Map
Block Base Block Sections CCSR Comments
Address (Hex) configuration bus
endianness
100_0000 - Reserved - -
107_FFFF
108_0000 - DDR memory controller DDR register Big-endian (byte
108_FFFF descriptions swapping required)
109_0000 - Reserved
117_FFFF
118_0000 - Arm coherency module register descriptions Little-endian (byte
118_FFFF (CCI-400) swapping not
required)
119_0000 - Reserved - -
13F_FFFF
140_0000-14F_FFFF GIC-400 - Little-endian (byte See the chapter "Arm
swapping not modules."
required)
150_0000-150_FFFF TZASC register descriptions Little-endian (byte
swapping not
required)
151_0000-151_FFFF Central security unit (CSU) CSU Memory Map/ Little-endian (byte
Register Definition swapping not
required)
152_0000-152_FFFF Platform control Miscellaneous Big-endian (byte
(Miscellaneous system control System Control swapping required)
module (MSCM)) Module (MSCM)
153_0000-153_FFFF IFC IFC memory map/ Big-endian (byte
register definition swapping required)
154_0000-154_FFFF Reserved - -
155_0000-155_FFFF Quad serial peripheral Memory Map and Big-endian (byte
interface (QuadSPI) Register Definition swapping required)
156_0000-156_FFFF Enhanced secured digital host eSDHC register Big-endian (byte
controller (eSDHC) descriptions swapping required)
157_0000-157_FFFF Supplemental configuration SCFG Memory Map/ Big-endian (byte
unit (SCFG) Register Definition swapping required)
158_0000-160_FFFF Reserved - -
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
178 NXP Semiconductors
Chapter 2 Memory Map
Table 2-3. CCSR Block Base Address Map (continued)
Block Base Block Sections CCSR Comments
Address (Hex) configuration bus
endianness
161_0000-161_FFFF Pre-Boot loader (PBL) Reserved address -
space used as internal
PBL commands
162_0000-16F_FFFF Reserved - -
170_0000-17F_FFFF SEC1 - Big-endian (byte See the Security
swapping required) reference manual.
180_0000-187_FFFF Reserved - - -
188_0000-188_FFFF Queue manager (QMan) See the DPAA
1 reference manual
189_0000-189_FFFF Buffer manager (BMan)1 See the DPAA
reference manual
18A_0000-19F_FFFF Reserved - - -
1A0_0000-1AF_FFFF Frame manager (FMan)1 - - See the DPAA
reference manual
1B0_0000-1E7_FFFF Reserved - - -
1E8_0000-1E8_FFFF Security fuse processor (SFP) Security fuse processor Big-endian (byte See QorIQ Trust
(SFP) memory map swapping required) Architecture 2.1 User
Guide
1E9_0000-1E9_FFFF Security Monitor SecMon Register Big-endian (byte See the QorIQ Trust
Descriptions swapping required) Architecture 2.1 User
Guide
1EA_0000-1EA_FFF SerDes control SerDes register Big-endian (byte
F descriptions swapping required)
1EB_0000-1ED_FFF Reserved -
F
1EE_0000-1EE_0FF Device configuration and pin Device Big-endian (byte
F control (DCFG) Configuration/Pin swapping required)
Control Memory Map
1EE_1000-1EE_1FF Clocking Clocking Memory Map Big-endian (byte
F swapping required)
1EE_2000-1EE_2FF Run control/power RCPM Memory Map/ Big-endian (byte
F management (RCPM) Register Definition swapping required)
1EE_3000-1EF_FFF Reserved -
F
1F0_0000-1F0_FFFF Thermal monitoring unit (TMU) TMU register Big-endian (byte
descriptions swapping required)
1F1_0000-20F_FFFF Reserved -
210_0000-210_FFFF Serial peripheral interface Memory Map/Register Big-endian (byte
(SPI) Definition swapping required)
211_0000-217_FFFF Reserved -
218_0000-218_FFFF I2C controller 1 Memory map and Byte accessible
register definition
219_0000-219_FFFF I2C controller 2 Memory map and Byte accessible
register definition
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 179
CCSR address map
Table 2-3. CCSR Block Base Address Map (continued)
Block Base Block Sections CCSR Comments
Address (Hex) configuration bus
endianness
21A_0000-21A_FFFF I2C controller 3 Memory map and Byte accessible
register definition
21B_0000-21B_FFFF I2C controller 4 Memory map and Byte accessible
register definition
21C_0000-21C_FFF DUART1 DUART register Byte accessible
F descriptions
21D_0000-21D_FFF DUART2 DUART register Byte accessible
F descriptions
21E_0000-22F_FFFF Reserved - - -
230_0000-230_FFFF General purpose I/O 1 GPIO register Big-endian (byte
(GPIO1) descriptions swapping required)
231_0000-231_FFFF General purpose I/O 2 GPIO register Big-endian (byte
(GPIO2) descriptions swapping required)
232_0000-232_FFFF General purpose I/O 3 GPIO register Big-endian (byte
(GPIO3) descriptions swapping required)
233_0000-233_FFFF General purpose I/O 4 GPIO register Big-endian (byte
(GPIO4) descriptions swapping required)
234_0000-23F_FFFF Reserved - - -
240_0000-27F_FFFF QUICC engine Big-endian (byte See the QUICC
swapping required) Engine Block
Reference Manual
with Protocol
Interworking.
280_0000-294_FFFF Reserved - - -
295_0000-295_FFFF Low Power universal Register definition Big-endian (byte This is 32-b mode
asynchronous receiver/ swapping required) register accessible IP
transmitter 1 (LPUART1) while DUART is byte
accessible
296_0000-296_FFFF Low Power universal Register definition Big-endian (byte
asynchronous receiver/ swapping required)
transmitter 2 (LPUART2)
297_0000-297_FFFF Low Power universal Register definition Big-endian (byte
asynchronous receiver/ swapping required)
transmitter 3 (LPUART3)
298_0000-298_FFFF Low Power universal Register definition Big-endian (byte
asynchronous receiver/ swapping required)
transmitter 4 (LPUART4)
299_0000-299_FFFF Low Power universal Register definition Big-endian (byte
asynchronous receiver/ swapping required)
transmitter 5 (LPUART5)
29A_0000-29A_FFFF Low Power universal Register definition Big-endian (byte
asynchronous receiver/ swapping required)
transmitter 6 (LPUART6)
29B_0000-29C_FFFF Reserved - - -
29D_0000-29D_FFF FlexTimer module 1 (FTM1) Memory map and Big-endian (byte
F register definition swapping required)
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
180 NXP Semiconductors
Chapter 2 Memory Map
Table 2-3. CCSR Block Base Address Map (continued)
Block Base Block Sections CCSR Comments
Address (Hex) configuration bus
endianness
29E_0000-29E_FFFF FlexTimer module 2 (FTM2) Memory map and Big-endian (byte
register definition swapping required)
29F_0000-29F_FFFF FlexTimer module 3 (FTM3) Memory map and Big-endian (byte
register definition swapping required)
2A0_0000-2A0_FFFF FlexTimer module 4 (FTM4) Memory map and Big-endian (byte
register definition swapping required)
2A1_0000-2A1_FFFF FlexTimer module 5 (FTM5) Memory map and Big-endian (byte
register definition swapping required)
2A2_0000-2A2_FFFF FlexTimer module 6 (FTM6) Memory map and Big-endian (byte
register definition swapping required)
2A3_0000-2A3_FFFF FlexTimer module 7 (FTM7) Memory map and Big-endian (byte
register definition swapping required)
2A4_0000-2A4_FFFF FlexTimer module 8 (FTM8) Memory map and Big-endian (byte
register definition swapping required)
2A5_0000-2A6_FFFF Reserved - - -
2A7_0000-2A7_FFFF Watchdog timer 3 (WDOG3) WDOG Memory Map/ Big-endian (byte
Register Definition swapping required)
2A8_0000-2A8_FFFF Watchdog timer 4 (WDOG4) WDOG Memory Map/ Big-endian (byte
Register Definition swapping required)
2A9_0000-2A9_FFFF Watchdog timer 5 (WDOG5) WDOG Memory Map/ Big-endian (byte
Register Definition swapping required)
2AA_0000-2AC_FFF Reserved -
F
2AD_0000-2AD_FFF Watchdog timer 1 (WDOG1) WDOG Memory Map/ Big-endian (byte
F Register Definition swapping required)
2AE_0000-2AE_FFF Watchdog timer 2 (WDOG2) WDOG Memory Map/ Big-endian (byte
F Register Definition swapping required)
2AF_0000-2AF_FFF Reserved - - -
F
2B0_0000-2B0_FFFF SYS_COUNTER (Secure) Secure system counter Big-endian (byte
memory map/register swapping required)
definition
2B1_0000-2B1_FFFF SYS_COUNTER (Non-secure) Non-Secure system Big-endian (byte
counter memory map/ swapping required)
register definition
2B2_0000-2BF_FFFF Reserved - - -
2C0_0000-2C0_FFF Enhanced direct memory Memory map/register Big-endian (byte 32-bit address space
F access (eDMA) definition swapping required) size
2C1_0000-2C1_FFF Direct memory access Memory map/register Big-endian (byte
F multiplexer 1 (DMAMUX1) definition swapping required)
2C2_0000-2C2_FFF Direct memory access Memory map/register Big-endian (byte
F multiplexer 2 (DMAMUX2) definition swapping required)
2C3_0000-2C9_FFF Reserved - - -
F
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 181
CCSR address map
Table 2-3. CCSR Block Base Address Map (continued)
Block Base Block Sections CCSR Comments
Address (Hex) configuration bus
endianness
2CA_0000-2CA_FFF Interconnect fabric IF Memory Map/ Little-endian (byte
F Register Definition swapping not
required)
2CB_0000-2EF_FFF Reserved - - -
F
2F0_0000-2FF_FFFF USB3.0 controller 1 USB Memory Map/ Little-endian (byte Supports 64-bit
Register Definition swapping not addressing
required)
300_0000-30F_FFFF USB3.0 controller 2 USB Memory Map/ Little-endian (byte Supports 64-bit
Register Definition swapping not addressing
required)
310_0000-31F_FFFF USB3.0 controller 3 USB Memory Map/ Little-endian (byte Supports 64-bit
Register Definition swapping not addressing
required)
320_0000-320_FFFF SATA SATA AHCI register Little-endian (byte
descriptions swapping not
required)
321_0000-33F_FFFF Reserved - - -
340_0000-340_FFFF PCI Express controller 1 PEX register Little-endian (byte
descriptions swapping not
required)
341_0000-341_FFFF PCI Express 1 LUT PEX_LUT register Big-endian (byte
descriptions swapping required)
350_0000-350_FFFF PCI Express controller 2 PEX register Little-endian (byte
descriptions swapping not
required)
351_0000-351_FFFF PCI Express 2 LUT PEX_LUT register Big-endian (byte
descriptions swapping required)
352_0000-35F_FFFF Reserved - -
360_0000-360_FFFF PCI Express controller 3 PEX register Little-endian (byte
descriptions swapping not
required)
361_0000-361_FFFF PCI Express 3 LUT PEX_LUT register Big-endian (byte
descriptions swapping required)
362_0000-837_FFFF Reserved - -
838_0000-83F_FFFF Queue direct memory access qDMA register Little-endian (byte
controller (qDMA) descriptions swapping not
required)
840_0000-84E_FFFF Reserved - -
84F_0000-84F_FFFF USB3 #1 PHY (debug i/f) USB PHY Memory Little-endian (byte
Map/Register Definition swapping not
required)
850_0000-850_FFFF USB3 #2 PHY (debug i/f) USB PHY Memory Little-endian (byte
Map/Register Definition swapping not
required)
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
182 NXP Semiconductors
Chapter 2 Memory Map
Table 2-3. CCSR Block Base Address Map (continued)
Block Base Block Sections CCSR Comments
Address (Hex) configuration bus
endianness
851_0000-851_FFFF USB3 #3 PHY (debug i/f) USB PHY Memory Little-endian (byte
Map/Register Definition swapping not
required)
852_0000-8FF_FFFF Reserved - - -
900_0000-9FF_FFFF SMMU - Little-endian (byte See the chapter "Arm
swapping not modules."
required)
A00_0000-FFF_FFFF Reserved - - -
1. The DPAA components should be in big-endian mode. The DPAA (FMan, QMan, BMan, and Security modules) data
structures can be in the following locations:
• CCSR registers
• Portals
• Frame descriptors such as data structures shared between software/hardware (in DDR):
• Arm A53, little-endian mode: The DPAA software should perform endianness-related byte-swap (for write
access, little endian should be swapped to big endian; for read access, big endian should be swapped to little
endian) for accessing the DPAA components.
• Arm A53, big-endian mode: The DPAA software will not perform endianness-related byte-swap for accessing
the DPAA components.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 183
CCSR address map
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
184 NXP Semiconductors
Chapter 3
Signal Descriptions
3.1 Signals introduction
This chapter describes the external signals and is organized into the following sections:
• Overview of signals and cross-references for signals that serve multiple functions
• List of reset configuration signals
• Signal multiplexing details
• List of output signal states at reset
3.2 Signals overview
The signals are grouped as follows:
• DDR memory controller interface signals
• Integrated Flash controller interface signals
• DUART/LPUART interface signals
• I2C interface signals
• Enhanced SDHC interface signals
• Serial peripheral interface (SPI) signals
• IEEE 1588 timestamp signals
• Ethernet management interface signals
• Ethernet controller RGMII interface signals
• QE-TDM/HDLC interface signals
• General-purpose input/output, security monitor, system control, power management,
and debug signals
• Clock and JTAG signals
• Power-on-reset configuration signals
• QuadSPI interface signals
• FlexTimer module interface signals
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 185
Signals overview
Note that individual chapters of this document provide details for each signal, describing
each signal's behavior when the signal is asserted or negated and when the signal is an
input or an output.
The following tables provides a summary of the signals grouped by function. This table
details the signal name, interface, alternate functions, and whether the signal is an input,
output, or bidirectional. The direction of the multiplexed signals applies for the primary
signal function listed in the left-most column of the table for that row (and does not apply
for the state of the reset configuration signals). Finally, the tables provide a pointer to the
table where the signal function is described.
Table 3-1. LS1043 Signal Reference by Functional Block
Name Description Alternate Function(s) Pin
type
DDR SDRAM Memory Interface 1 (See DDR Signals Overview for more details.)
D1_MA00 Address - O
D1_MA01 Address - O
D1_MA02 Address - O
D1_MA03 Address - O
D1_MA04 Address - O
D1_MA05 Address - O
D1_MA06 Address - O
D1_MA07 Address - O
D1_MA08 Address - O
D1_MA09 Address - O
D1_MA10 Address - O
D1_MA11 Address - O
D1_MA12 Address - O
D1_MA13 Address - O
D1_MA14 Address - O
D1_MA15 Address - O
D1_MAPAR_ERR_B Address Parity Error I
D1_MAPAR_OUT Address Parity Out - O
D1_MBA0 Bank Select - O
D1_MBA1 Bank Select - O
D1_MBA2 Bank Select - O
D1_MCAS_B Column Address Strobe - O
D1_MCK0 Clock - O
D1_MCK0_B Clock Complement - O
D1_MCK1 Clock - O
D1_MCK1_B Clock Complement - O
D1_MCKE0 Clock Enable - O
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
186 NXP Semiconductors
Chapter 3 Signal Descriptions
Table 3-1. LS1043 Signal Reference by Functional Block (continued)
Name Description Alternate Function(s) Pin
type
D1_MCKE1 Clock Enable - O
D1_MCS0_B Chip Select - O
D1_MCS1_B Chip Select - O
D1_MCS2_B Chip Select - O
D1_MCS3_B Chip Select - O
D1_MDIC0 Driver Impedence Calibration - IO
D1_MDIC1 Driver Impedence Calibration - IO
D1_MDM0 Data Mask - O
D1_MDM1 Data Mask - O
D1_MDM2 Data Mask - O
D1_MDM3 Data Mask - O
D1_MDM8 Data Mask - O
D1_MDQ00 Data - IO
D1_MDQ01 Data - IO
D1_MDQ02 Data - IO
D1_MDQ03 Data - IO
D1_MDQ04 Data - IO
D1_MDQ05 Data - IO
D1_MDQ06 Data - IO
D1_MDQ07 Data - IO
D1_MDQ08 Data - IO
D1_MDQ09 Data - IO
D1_MDQ10 Data - IO
D1_MDQ11 Data - IO
D1_MDQ12 Data - IO
D1_MDQ13 Data - IO
D1_MDQ14 Data - IO
D1_MDQ15 Data - IO
D1_MDQ16 Data - IO
D1_MDQ17 Data - IO
D1_MDQ18 Data - IO
D1_MDQ19 Data - IO
D1_MDQ20 Data - IO
D1_MDQ21 Data - IO
D1_MDQ22 Data - IO
D1_MDQ23 Data - IO
D1_MDQ24 Data - IO
D1_MDQ25 Data - IO
D1_MDQ26 Data - IO
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 187
Signals overview
Table 3-1. LS1043 Signal Reference by Functional Block (continued)
Name Description Alternate Function(s) Pin
type
D1_MDQ27 Data - IO
D1_MDQ28 Data - IO
D1_MDQ29 Data - IO
D1_MDQ30 Data - IO
D1_MDQ31 Data - IO
D1_MDQS0 Data Strobe - IO
D1_MDQS0_B Data Strobe - IO
D1_MDQS1 Data Strobe - IO
D1_MDQS1_B Data Strobe - IO
D1_MDQS2 Data Strobe - IO
D1_MDQS2_B Data Strobe - IO
D1_MDQS3 Data Strobe - IO
D1_MDQS3_B Data Strobe - IO
D1_MDQS8 Data Strobe - IO
D1_MDQS8_B Data Strobe - IO
D1_MECC0 Error Correcting Code - IO
D1_MECC1 Error Correcting Code - IO
D1_MECC2 Error Correcting Code - IO
D1_MECC3 Error Correcting Code - IO
D1_MODT0 On Die Termination - O
D1_MODT1 On Die Termination - O
D1_MRAS_B Row Address Strobe - O
D1_MWE_B Write Enable - O
Integrated Flash Controller (See External signal descriptions for more details.)
IFC_A16 IFC Address QSPI_A_CS0 O
IFC_A17 IFC Address QSPI_A_CS1 O
IFC_A18 IFC Address QSPI_A_SCK O
IFC_A19 IFC Address QSPI_B_CS0 O
IFC_A20 IFC Address QSPI_B_CS1 O
IFC_A21 IFC Address QSPI_B_SCK O
cfg_dram_type
IFC_A22 / IFC_WP1_B IFC Address QSPI_A_DATA0 O
IFC_A23 / IFC_WP2_B IFC Address QSPI_A_DATA1 O
IFC_A24 / IFC_WP3_B IFC Address QSPI_A_DATA2 O
IFC_A25 / IFC_CS4_B / IFC Address GPIO2_25 O
IFC_RB2_B QSPI_A_DATA3
FTM5_CH0
IFC_A26 / IFC_CS5_B / IFC Address GPIO2_26 O
IFC_RB3_B FTM5_CH1
IFC_A27 / IFC_CS6_B IFC Address GPIO2_27 O
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
188 NXP Semiconductors
Chapter 3 Signal Descriptions
Table 3-1. LS1043 Signal Reference by Functional Block (continued)
Name Description Alternate Function(s) Pin
type
FTM5_EXTCLK
IFC_AD00 IFC Address / Data cfg_gpinput0 IO
IFC_AD01 IFC Address / Data cfg_gpinput1 IO
IFC_AD02 IFC Address / Data cfg_gpinput2 IO
IFC_AD03 IFC Address / Data cfg_gpinput3 IO
IFC_AD04 IFC Address / Data cfg_gpinput4 IO
IFC_AD05 IFC Address / Data cfg_gpinput5 IO
IFC_AD06 IFC Address / Data cfg_gpinput6 IO
IFC_AD07 IFC Address / Data cfg_gpinput7 IO
IFC_AD08 IFC Address / Data cfg_rcw_src0 IO
IFC_AD09 IFC Address / Data cfg_rcw_src1 IO
IFC_AD10 IFC Address / Data cfg_rcw_src2 IO
IFC_AD11 IFC Address / Data cfg_rcw_src3 IO
IFC_AD12 IFC Address / Data cfg_rcw_src4 IO
IFC_AD13 IFC Address / Data cfg_rcw_src5 IO
IFC_AD14 IFC Address / Data cfg_rcw_src6 IO
IFC_AD15 IFC Address / Data cfg_rcw_src7 IO
IFC_AVD IFC Address Valid O
IFC_BCTL IFC Buffer control O
IFC_CLE IFC Command Latch Enable / Write Enable cfg_rcw_src8 O
IFC_CLK0 IFC Clock - O
IFC_CLK1 IFC Clock - O
IFC_CS0_B IFC Chip Select - O
IFC_CS1_B IFC Chip Select GPIO2_10 O
FTM7_CH0
IFC_CS2_B IFC Chip Select GPIO2_11 O
FTM7_CH1
IFC_CS3_B IFC Chip Select GPIO2_12 O
QSPI_B_DATA3
FTM7_EXTCLK
IFC_CS4_B / IFC_A25 / IFC Chip Select GPIO2_25 O
IFC_RB2_B QSPI_A_DATA3
FTM5_CH0
IFC_CS5_B / IFC_A26 / IFC Chip Select GPIO2_26 O
IFC_RB3_B FTM5_CH1
IFC_CS6_B / IFC_A27 IFC Chip Select GPIO2_27 O
FTM5_EXTCLK
IFC_NDDDR_CLK IFC NAND DDR Clock - O
IFC_NDDQS IFC DQS Strobe - IO
IFC_OE_B IFC Output Enable cfg_eng_use1 O
IFC_PAR0 IFC Address & Data Parity GPIO2_13 IO
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 189
Signals overview
Table 3-1. LS1043 Signal Reference by Functional Block (continued)
Name Description Alternate Function(s) Pin
type
QSPI_B_DATA0
FTM6_CH0
IFC_PAR1 IFC Address & Data Parity GPIO2_14 IO
QSPI_B_DATA1
FTM6_CH1
IFC_PERR_B IFC Parity Error GPIO2_15 I
QSPI_B_DATA2
FTM6_EXTCLK
IFC_RB0_B IFC Ready / Busy CS0 I
IFC_RB1_B IFC Ready / Busy CS1 I
IFC_RB2_B / IFC_A25 / IFC Ready/Busy CS 2 GPIO2_25 I
IFC_CS4_B QSPI_A_DATA3
FTM5_CH0
IFC_RB3_B / IFC_A26 / IFC Ready/Busy CS 3 GPIO2_26 I
IFC_CS5_B FTM5_CH1
IFC_TE IFC External Transceiver Enable cfg_ifc_te O
IFC_WE0_B IFC Write Enable cfg_eng_use0 O
IFC_WP0_B IFC Write Protect cfg_eng_use2 O
IFC_WP1_B / IFC_A22 IFC Write Protect QSPI_A_DATA0 O
IFC_WP2_B / IFC_A23 IFC Write Protect QSPI_A_DATA1 O
IFC_WP3_B / IFC_A24 IFC Write Protect QSPI_A_DATA2 O
DUART (See DUART external signal descriptions for more details.)
UART1_CTS_B / Clear To Send GPIO1_21 I
UART3_SIN FTM4_CH4
LPUART2_SIN
UART1_RTS_B / Ready to Send GPIO1_19 O
UART3_SOUT LPUART2_SOUT
FTM4_CH2
UART1_SIN Receive Data GPIO1_17 I
UART1_SOUT Transmit Data GPIO1_15 O
UART2_CTS_B / Clear To Send GPIO1_22 I
UART4_SIN FTM4_CH5
LPUART1_CTS_B
LPUART4_SIN
UART2_RTS_B / Ready to Send GPIO1_20 O
UART4_SOUT LPUART4_SOUT
FTM4_CH3
LPUART1_RTS_B
UART2_SIN Receive Data GPIO1_18 I
FTM4_CH1
LPUART1_SIN
UART2_SOUT Transmit Data GPIO1_16 O
LPUART1_SOUT
FTM4_CH0
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
190 NXP Semiconductors
Chapter 3 Signal Descriptions
Table 3-1. LS1043 Signal Reference by Functional Block (continued)
Name Description Alternate Function(s) Pin
type
UART3_SIN / Receive Data GPIO1_21 I
UART1_CTS_B FTM4_CH4
LPUART2_SIN
UART3_SOUT / Transmit Data GPIO1_19 O
UART1_RTS_B LPUART2_SOUT
FTM4_CH2
UART4_SIN / Receive Data GPIO1_22 I
UART2_CTS_B FTM4_CH5
LPUART1_CTS_B
LPUART4_SIN
UART4_SOUT / Transmit Data GPIO1_20 O
UART2_RTS_B LPUART4_SOUT
FTM4_CH3
LPUART1_RTS_B
SPI Interface (See LS1043A SPI signals for more details.)
SPI_CLK SPI Clock O
SPI_CS0_B SPI Chip Select GPIO2_00 O
SDHC_DAT4
SDHC_VS
SPI_CS1_B SPI Chip Select GPIO2_01 O
SDHC_DAT5
SDHC_CMD_DIR
SPI_CS2_B SPI Chip Select GPIO2_02 O
SDHC_DAT6
SDHC_DAT0_DIR
SPI_CS3_B SPI Chip Select GPIO2_03 O
SDHC_DAT7
SDHC_DAT123_DI
R
SPI_MISO Master In Slave Out SDHC_CLK_SYNC I
_IN
SPI_MOSI Master Out Slave In SDHC_CLK_SYNC O
_OUT
eSDHC (See eSDHC signal descriptions for more details.)
SDHC_CD_B Command IIC2_SCL I
GPIO4_02
FTM3_QD_PHA
CLK9
QE_SI1_STROBE0
BRGO2
SDHC_CLK Host to Card Clock GPIO2_09 O
LPUART3_CTS_B
LPUART6_SIN
FTM4_QD_PHB
SDHC_CLK_SYNC_IN IN SPI_MISO I
SDHC_CLK_SYNC_OUT OUT SPI_MOSI O
SDHC_CMD Command/Response GPIO2_04 IO
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 191
Signals overview
Table 3-1. LS1043 Signal Reference by Functional Block (continued)
Name Description Alternate Function(s) Pin
type
LPUART3_SOUT
FTM4_CH6
SDHC_CMD_DIR DIR SPI_CS1_B O
GPIO2_01
SDHC_DAT5
SDHC_DAT0 Data GPIO2_05 IO
FTM4_CH7
LPUART3_SIN
SDHC_DAT0_DIR DIR SPI_CS2_B O
GPIO2_02
SDHC_DAT6
SDHC_DAT1 Data GPIO2_06 IO
LPUART5_SOUT
FTM4_FAULT
LPUART2_RTS_B
SDHC_DAT123_DIR DIR SPI_CS3_B O
GPIO2_03
SDHC_DAT7
SDHC_DAT2 Data GPIO2_07 IO
LPUART2_CTS_B
LPUART5_SIN
FTM4_EXTCLK
SDHC_DAT3 Data GPIO2_08 IO
LPUART6_SOUT
FTM4_QD_PHA
LPUART3_RTS_B
SDHC_DAT4 Data SPI_CS0_B IO
GPIO2_00
SDHC_VS
SDHC_DAT5 Data SPI_CS1_B IO
GPIO2_01
SDHC_CMD_DIR
SDHC_DAT6 Data SPI_CS2_B IO
GPIO2_02
SDHC_DAT0_DIR
SDHC_DAT7 Data SPI_CS3_B IO
GPIO2_03
SDHC_DAT123_DI
R
SDHC_VS VS SPI_CS0_B O
GPIO2_00
SDHC_DAT4
SDHC_WP Write Protect IIC2_SDA I
GPIO4_03
FTM3_QD_PHB
CLK10
QE_SI1_STROBE1
BRGO3
Programmable Interrupt Controller
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
192 NXP Semiconductors
Chapter 3 Signal Descriptions
Table 3-1. LS1043 Signal Reference by Functional Block (continued)
Name Description Alternate Function(s) Pin
type
EVT9_B Interrupt Output O
IRQ00 External Interrupt I
IRQ01 External Interrupt I
IRQ02 External Interrupt I
IRQ03 External Interrupt GPIO1_23 I
FTM3_CH7
TDMB_TSYNC
UC3_RTSB_TXEN
IRQ04 External Interrupt GPIO1_24 I
FTM3_CH0
TDMA_RXD
UC1_RXD7
TDMA_TXD
IRQ05 External Interrupt GPIO1_25 I
FTM3_CH1
TDMA_RSYNC
UC1_CTSB_RXDV
IRQ06 External Interrupt GPIO1_26 I
FTM3_CH2
TDMA_RXD_EXC
TDMA_TXD
UC1_TXD7
IRQ07 External Interrupt GPIO1_27 I
FTM3_CH3
TDMA_TSYNC
UC1_RTSB_TXEN
IRQ08 External Interrupt GPIO1_28 I
FTM3_CH4
TDMB_RXD
UC3_RXD7
TDMB_TXD
IRQ09 External Interrupt GPIO1_29 I
FTM3_CH5
TDMB_RSYNC
UC3_CTSB_RXDV
IRQ10 External Interrupt GPIO1_30 I
FTM3_CH6
TDMB_RXD_EXC
TDMB_TXD
UC3_TXD7
IRQ11 External Interrupt GPIO1_31 I
Battery Backed Trust (See Signals for more details.)
TA_BB_TMP_DETECT_ Battery Backed Tamper Detect - I
B
Trust (See Signals for more details.)
TA_TMP_DETECT_B Tamper Detect I
System Control (See External signal descriptions for more details.)
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 193
Signals overview
Table 3-1. LS1043 Signal Reference by Functional Block (continued)
Name Description Alternate Function(s) Pin
type
HRESET_B Hard Reset - IO
PORESET_B Power On Reset - I
RESET_REQ_B Reset Request (POR or Hard) O
Power Management (See External signal descriptions for more details.)
ASLEEP Asleep GPIO1_13 O
SYSCLK (See External signal descriptions for more details.)
SYSCLK System Clock - I
DDR Clocking (See External signal descriptions for more details.)
DDRCLK DDR Controller Clock - I
RTC (See External signal descriptions for more details.)
RTC Real Time Clock GPIO1_14 I
Debug
CKSTP_OUT_B This signal is reserved for internal use. Refer the - O
chip specific design checklist for more information.
CLK_OUT Clock Out - O
EVT0_B Event 0 - IO
EVT1_B Event 1 - IO
EVT2_B Event 2 - IO
EVT3_B Event 3 - IO
EVT4_B Event 4 - IO
EVT5_B Event 5 IIC3_SCL IO
GPIO4_10
USB2_DRVVBUS
BRGO4
FTM8_CH0
CLK11
EVT6_B Event 6 IIC3_SDA IO
GPIO4_11
USB2_PWRFAULT
BRGO1
FTM8_CH1
CLK12_CLK8
EVT7_B Event 7 IIC4_SCL IO
GPIO4_12
USB3_DRVVBUS
TDMA_RQ
FTM3_FAULT
UC1_CDB_RXER
EVT8_B Event 8 IIC4_SDA IO
GPIO4_13
USB3_PWRFAULT
TDMB_RQ
FTM3_EXTCLK
UC3_CDB_RXER
DFT
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
194 NXP Semiconductors
Chapter 3 Signal Descriptions
Table 3-1. LS1043 Signal Reference by Functional Block (continued)
Name Description Alternate Function(s) Pin
type
JTAG_BSR_VSEL An IEEE 1149.1 JTAG compliance enable pin. - I
0: Normal operation.
1: To be compliant to the 1149.1 specification for
boundary scan functions. The JTAG compliant state
is documented in the BSDL.
NOTE: When this pin is tied high, the USB PHY will
not come out or reset in normal functional
mode.
SCAN_MODE_B Reserved - I
TBSCAN_EN_B An IEEE 1149.1 JTAG compliance enable pin. 0:To - I
be compliant to the 1149.1 specification for boundary
scan functions. The JTAG compliant state is
documented in the BSDL. 1: JTAG connects to DAP
controller for the Arm core debug.
TEST_SEL_B Reserved - I
JTAG
TCK Test Clock - I
TDI Test Data In - I
TDO Test Data Out - O
TMS Test Mode Select - I
TRST_B Test Reset - I
Analog Signals
D1_MVREF SSTL Reference Voltage - IO
D1_TPA DDR Controller 1 Test Point Analog - IO
FA_ANALOG_G_V Reserved - IO
FA_ANALOG_PIN Reserved - IO
TD1_ANODE Thermal diode anode - IO
TD1_CATHODE Thermal diode cathode - IO
TH_TPA Thermal Test Point Analog - -
SerDes (See External Signals Description for more details.)
SD1_IMP_CAL_RX SerDes Receive Impedence Calibration - I
SD1_IMP_CAL_TX SerDes Transmit Impedance Calibration - I
SD1_PLL1_TPA SerDes PLL 1 Test Point Analog - O
SD1_PLL1_TPD SerDes Test Point Digital - O
SD1_PLL2_TPA SerDes PLL 2 Test Point Analog - O
SD1_PLL2_TPD SerDes Test Point Digital - O
SD1_REF_CLK1_N SerDes PLL 1 Reference Clock Complement - I
SD1_REF_CLK1_P SerDes PLL 1 Reference Clock - I
SD1_REF_CLK2_N SerDes PLL 2 Reference Clock Complement - I
SD1_REF_CLK2_P SerDes PLL 2 Reference Clock - I
SD1_RX0_N SerDes Receive Data (negative) - I
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 195
Signals overview
Table 3-1. LS1043 Signal Reference by Functional Block (continued)
Name Description Alternate Function(s) Pin
type
SD1_RX0_P SerDes Receive Data (positive) - I
SD1_RX1_N SerDes Receive Data (negative) - I
SD1_RX1_P SerDes Receive Data (positive) - I
SD1_RX2_N SerDes Receive Data (negative) - I
SD1_RX2_P SerDes Receive Data (positive) - I
SD1_RX3_N SerDes Receive Data (negative) - I
SD1_RX3_P SerDes Receive Data (positive) - I
SD1_TX0_N SerDes Transmit Data (negative) - O
SD1_TX0_P SerDes Transmit Data (positive) - O
SD1_TX1_N SerDes Transmit Data (negative) - O
SD1_TX1_P SerDes Transmit Data (positive) - O
SD1_TX2_N SerDes Transmit Data (negative) - O
SD1_TX2_P SerDes Transmit Data (positive) - O
SD1_TX3_N SerDes Transmit Data (negative) - O
SD1_TX3_P SerDes Transmit Data (positive) - O
USB3 PHY 1 (See External Signals for more details.)
USB1_D_M USB PHY HS Data (-) - IO
USB1_D_P USB PHY HS Data (+) - IO
USB1_ID USB PHY ID Detect - I
USB1_RESREF USB PHY Impedance Calibration - IO
USB1_RX_M USB PHY SS Receive Data (-) - I
USB1_RX_P USB PHY SS Receive Data (+) - I
USB1_TX_M USB PHY SS Transmit Data (-) - O
USB1_TX_P USB PHY SS Transmit Data (+) - O
USB1_VBUS USB PHY VBUS - I
USB3 PHY 2 (See External Signals for more details.)
USB2_D_M USB PHY HS Data (-) - IO
USB2_D_P USB PHY HS Data (+) - IO
USB2_ID USB PHY ID Detect - I
USB2_RESREF USB PHY Impedance Calibration - IO
USB2_RX_M USB PHY SS Receive Data (-) - I
USB2_RX_P USB PHY SS Receive Data (+) - I
USB2_TX_M USB PHY SS Transmit Data (-) - O
USB2_TX_P USB PHY SS Transmit Data (+) - O
USB2_VBUS USB PHY VBUS - I
USB3 PHY 3 (See External Signals for more details.)
USB3_D_M USB PHY HS Data (-) - IO
USB3_D_P USB PHY HS Data (+) - IO
USB3_ID USB PHY ID Detect - I
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
196 NXP Semiconductors
Chapter 3 Signal Descriptions
Table 3-1. LS1043 Signal Reference by Functional Block (continued)
Name Description Alternate Function(s) Pin
type
USB3_RESREF USB PHY Impedance Calibration - IO
USB3_RX_M USB PHY SS Receive Data (-) - I
USB3_RX_P USB PHY SS Receive Data (+) - I
USB3_TX_M USB PHY SS Transmit Data (-) - O
USB3_TX_P USB PHY SS Transmit Data (+) - O
USB3_VBUS USB PHY VBUS - I
Ethernet Management Interface 1(See DPAA reference manual for more details.)
EMI1_MDC Management Data Clock GPIO3_00 O
EMI1_MDIO Management Data In/Out GPIO3_01 IO
Ethernet Management Interface 2(See DPAA reference manual for more details.)
EMI2_MDC Management Data Clock GPIO4_00 O
EMI2_MDIO Management Data In/Out GPIO4_01 IO
Ethernet Controller 1(See DPAA reference manual for more details.)
EC1_GTX_CLK Transmit Clock Out GPIO3_07 O
FTM1_EXTCLK
EC1_GTX_CLK125 Reference Clock GPIO3_08 I
EC1_RXD0 Receive Data GPIO3_12 I
FTM1_CH0
EC1_RXD1 Receive Data GPIO3_11 I
FTM1_CH1
EC1_RXD2 Receive Data GPIO3_10 I
FTM1_CH6
EC1_RXD3 Receive Data GPIO3_09 I
FTM1_CH4
EC1_RX_CLK Receive Clock GPIO3_13 I
FTM1_QD_PHA
EC1_RX_DV Receive Data Valid GPIO3_14 I
FTM1_QD_PHB
EC1_TXD0 Transmit Data GPIO3_05 O
FTM1_CH2
EC1_TXD1 Transmit Data GPIO3_04 O
FTM1_CH3
EC1_TXD2 Transmit Data GPIO3_03 O
FTM1_CH7
EC1_TXD3 Transmit Data GPIO3_02 O
FTM1_CH5
EC1_TX_EN Transmit Enable GPIO3_06 O
FTM1_FAULT
Ethernet Controller 2(See DPAA reference manual for more details.)
EC2_GTX_CLK Transmit Clock Out GPIO3_20 O
FTM2_EXTCLK
EC2_GTX_CLK125 Reference Clock GPIO3_21 I
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 197
Signals overview
Table 3-1. LS1043 Signal Reference by Functional Block (continued)
Name Description Alternate Function(s) Pin
type
EC2_RXD0 Receive Data GPIO3_25 I
TSEC_1588_TRIG
_IN2
FTM2_CH0
EC2_RXD1 Receive Data GPIO3_24 I
TSEC_1588_PULS
E_OUT1
FTM2_CH1
EC2_RXD2 Receive Data GPIO3_23 I
FTM2_CH6
EC2_RXD3 Receive Data GPIO3_22 I
FTM2_CH4
EC2_RX_CLK Receive Clock GPIO3_26 I
TSEC_1588_CLK_I
N
FTM2_QD_PHA
EC2_RX_DV Receive Data Valid GPIO3_27 I
TSEC_1588_TRIG
_IN1
FTM2_QD_PHB
EC2_TXD0 Transmit Data GPIO3_18 O
TSEC_1588_PULS
E_OUT2
FTM2_CH2
EC2_TXD1 Transmit Data GPIO3_17 O
TSEC_1588_CLK_
OUT
FTM2_CH3
EC2_TXD2 Transmit Data GPIO3_16 O
TSEC_1588_ALAR
M_OUT1
FTM2_CH7
EC2_TXD3 Transmit Data GPIO3_15 O
TSEC_1588_ALAR
M_OUT2
FTM2_CH5
EC2_TX_EN Transmit Enable GPIO3_19 O
FTM2_FAULT
I2C (See External signal descriptions for more details.)
IIC1_SCL Serial Clock (supports PBL) IO
IIC1_SDA Serial Data (supports PBL) IO
IIC2_SCL Serial Clock GPIO4_02 IO
SDHC_CD_B
FTM3_QD_PHA
CLK9
QE_SI1_STROBE0
BRGO2
IIC2_SDA Serial Data GPIO4_03 IO
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
198 NXP Semiconductors
Chapter 3 Signal Descriptions
Table 3-1. LS1043 Signal Reference by Functional Block (continued)
Name Description Alternate Function(s) Pin
type
SDHC_WP
FTM3_QD_PHB
CLK10
QE_SI1_STROBE1
BRGO3
IIC3_SCL Serial Clock GPIO4_10 IO
EVT5_B
USB2_DRVVBUS
BRGO4
FTM8_CH0
CLK11
IIC3_SDA Serial Data GPIO4_11 IO
EVT6_B
USB2_PWRFAULT
BRGO1
FTM8_CH1
CLK12_CLK8
IIC4_SCL Serial Clock GPIO4_12 IO
EVT7_B
USB3_DRVVBUS
TDMA_RQ
FTM3_FAULT
UC1_CDB_RXER
IIC4_SDA Serial Data GPIO4_13 IO
EVT8_B
USB3_PWRFAULT
TDMB_RQ
FTM3_EXTCLK
UC3_CDB_RXER
USB (See External Signals for more details.)
USB2_DRVVBUS DRV VBus IIC3_SCL O
GPIO4_10
EVT5_B
BRGO4
FTM8_CH0
CLK11
USB2_PWRFAULT PWR Fault IIC3_SDA I
GPIO4_11
EVT6_B
BRGO1
FTM8_CH1
CLK12_CLK8
USB3_DRVVBUS DRV Bus IIC4_SCL O
GPIO4_12
EVT7_B
TDMA_RQ
FTM3_FAULT
UC1_CDB_RXER
USB3_PWRFAULT PWR Fault IIC4_SDA I
GPIO4_13
EVT8_B
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 199
Signals overview
Table 3-1. LS1043 Signal Reference by Functional Block (continued)
Name Description Alternate Function(s) Pin
type
TDMB_RQ
FTM3_EXTCLK
UC3_CDB_RXER
USB_DRVVBUS USB_DRVVBUS GPIO4_29 O
USB_PWRFAULT USB_PWRFAULT GPIO4_30 I
Battery Backed RTC (See External signal descriptions for more details.)
TA_BB_RTC This signal is reserved for internal information. Refer - I
the chip specific design checklist for more
information.
DSYSCLK (See External signal descriptions for more details.)
DIFF_SYSCLK Single Source System Clock Differential (positive) - I
DIFF_SYSCLK_B Single Source System Clock Differential (negative) - I
Power-On-Reset Configuration (See Configuration signals sampled at reset for more details.)
cfg_dram_type Power-on-Reset Configuration IFC_A21 I
QSPI_B_SCK
cfg_eng_use0 Power-on-Reset Configuration IFC_WE0_B I
cfg_eng_use1 Power-on-Reset Configuration IFC_OE_B I
cfg_eng_use2 Power-on-Reset Configuration IFC_WP0_B I
cfg_gpinput0 Power-on-Reset Configuration IFC_AD00 I
cfg_gpinput1 Power-on-Reset Configuration IFC_AD01 I
cfg_gpinput2 Power-on-Reset Configuration IFC_AD02 I
cfg_gpinput3 Power-on-Reset Configuration IFC_AD03 I
cfg_gpinput4 Power-on-Reset Configuration IFC_AD04 I
cfg_gpinput5 Power-on-Reset Configuration IFC_AD05 I
cfg_gpinput6 Power-on-Reset Configuration IFC_AD06 I
cfg_gpinput7 Power-on-Reset Configuration IFC_AD07 I
cfg_ifc_te Power-on-Reset Configuration IFC_TE I
cfg_rcw_src0 Power-on-Reset Configuration IFC_AD08 I
cfg_rcw_src1 Power-on-Reset Configuration IFC_AD09 I
cfg_rcw_src2 Power-on-Reset Configuration IFC_AD10 I
cfg_rcw_src3 Power-on-Reset Configuration IFC_AD11 I
cfg_rcw_src4 Power-on-Reset Configuration IFC_AD12 I
cfg_rcw_src5 Power-on-Reset Configuration IFC_AD13 I
cfg_rcw_src6 Power-on-Reset Configuration IFC_AD14 I
cfg_rcw_src7 Power-on-Reset Configuration IFC_AD15 I
cfg_rcw_src8 Power-on-Reset Configuration IFC_CLE I
General Purpose Input/Output (See GPIO signal descriptions for more details.)
GPIO1_13 General Purpose Input/Output ASLEEP O
GPIO1_14 General Purpose Input/Output RTC IO
GPIO1_15 General Purpose Input/Output UART1_SOUT IO
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
200 NXP Semiconductors
Chapter 3 Signal Descriptions
Table 3-1. LS1043 Signal Reference by Functional Block (continued)
Name Description Alternate Function(s) Pin
type
GPIO1_16 General Purpose Input/Output UART2_SOUT IO
LPUART1_SOUT
FTM4_CH0
GPIO1_17 General Purpose Input/Output UART1_SIN IO
GPIO1_18 General Purpose Input/Output UART2_SIN IO
FTM4_CH1
LPUART1_SIN
GPIO1_19 General Purpose Input/Output UART1_RTS_B IO
UART3_SOUT
LPUART2_SOUT
FTM4_CH2
GPIO1_20 General Purpose Input/Output UART2_RTS_B IO
UART4_SOUT
LPUART4_SOUT
FTM4_CH3
LPUART1_RTS_B
GPIO1_21 General Purpose Input/Output UART1_CTS_B IO
UART3_SIN
FTM4_CH4
LPUART2_SIN
GPIO1_22 General Purpose Input/Output UART2_CTS_B IO
UART4_SIN
FTM4_CH5
LPUART1_CTS_B
LPUART4_SIN
GPIO1_23 General Purpose Input/Output IRQ03 IO
FTM3_CH7
TDMB_TSYNC
UC3_RTSB_TXEN
GPIO1_24 General Purpose Input/Output IRQ04 IO
FTM3_CH0
TDMA_RXD
UC1_RXD7
TDMA_TXD
GPIO1_25 General Purpose Input/Output IRQ05 IO
FTM3_CH1
TDMA_RSYNC
UC1_CTSB_RXDV
GPIO1_26 General Purpose Input/Output IRQ06 IO
FTM3_CH2
TDMA_RXD_EXC
TDMA_TXD
UC1_TXD7
GPIO1_27 General Purpose Input/Output IRQ07 IO
FTM3_CH3
TDMA_TSYNC
UC1_RTSB_TXEN
GPIO1_28 General Purpose Input/Output IRQ08 IO
FTM3_CH4
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 201
Signals overview
Table 3-1. LS1043 Signal Reference by Functional Block (continued)
Name Description Alternate Function(s) Pin
type
TDMB_RXD
UC3_RXD7
TDMB_TXD
GPIO1_29 General Purpose Input/Output IRQ09 IO
FTM3_CH5
TDMB_RSYNC
UC3_CTSB_RXDV
GPIO1_30 General Purpose Input/Output IRQ10 IO
FTM3_CH6
TDMB_RXD_EXC
TDMB_TXD
UC3_TXD7
GPIO1_31 General Purpose Input/Output IRQ11 IO
GPIO2_00 General Purpose Input/Output SPI_CS0_B IO
SDHC_DAT4
SDHC_VS
GPIO2_01 General Purpose Input/Output SPI_CS1_B IO
SDHC_DAT5
SDHC_CMD_DIR
GPIO2_02 General Purpose Input/Output SPI_CS2_B IO
SDHC_DAT6
SDHC_DAT0_DIR
GPIO2_03 General Purpose Input/Output SPI_CS3_B IO
SDHC_DAT7
SDHC_DAT123_DI
R
GPIO2_04 General Purpose Input/Output SDHC_CMD IO
LPUART3_SOUT
FTM4_CH6
GPIO2_05 General Purpose Input/Output SDHC_DAT0 IO
FTM4_CH7
LPUART3_SIN
GPIO2_06 General Purpose Input/Output SDHC_DAT1 IO
LPUART5_SOUT
FTM4_FAULT
LPUART2_RTS_B
GPIO2_07 General Purpose Input/Output SDHC_DAT2 IO
LPUART2_CTS_B
LPUART5_SIN
FTM4_EXTCLK
GPIO2_08 General Purpose Input/Output SDHC_DAT3 IO
LPUART6_SOUT
FTM4_QD_PHA
LPUART3_RTS_B
GPIO2_09 General Purpose Input/Output SDHC_CLK IO
LPUART3_CTS_B
LPUART6_SIN
FTM4_QD_PHB
GPIO2_10 General Purpose Input/Output IFC_CS1_B IO
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
202 NXP Semiconductors
Chapter 3 Signal Descriptions
Table 3-1. LS1043 Signal Reference by Functional Block (continued)
Name Description Alternate Function(s) Pin
type
FTM7_CH0
GPIO2_11 General Purpose Input/Output IFC_CS2_B IO
FTM7_CH1
GPIO2_12 General Purpose Input/Output IFC_CS3_B IO
QSPI_B_DATA3
FTM7_EXTCLK
GPIO2_13 General Purpose Input/Output IFC_PAR0 IO
QSPI_B_DATA0
FTM6_CH0
GPIO2_14 General Purpose Input/Output IFC_PAR1 IO
QSPI_B_DATA1
FTM6_CH1
GPIO2_15 General Purpose Input/Output IFC_PERR_B IO
QSPI_B_DATA2
FTM6_EXTCLK
GPIO2_25 General Purpose Input/Output IFC_A25 IO
QSPI_A_DATA3
FTM5_CH0
IFC_CS4_B
IFC_RB2_B
GPIO2_26 General Purpose Input/Output IFC_A26 IO
FTM5_CH1
IFC_CS5_B
IFC_RB3_B
GPIO2_27 General Purpose Input/Output IFC_A27 IO
FTM5_EXTCLK
IFC_CS6_B
GPIO3_00 General Purpose Input/Output EMI1_MDC IO
GPIO3_01 General Purpose Input/Output EMI1_MDIO IO
GPIO3_02 General Purpose Input/Output EC1_TXD3 IO
FTM1_CH5
GPIO3_03 General Purpose Input/Output EC1_TXD2 IO
FTM1_CH7
GPIO3_04 General Purpose Input/Output EC1_TXD1 IO
FTM1_CH3
GPIO3_05 General Purpose Input/Output EC1_TXD0 IO
FTM1_CH2
GPIO3_06 General Purpose Input/Output EC1_TX_EN IO
FTM1_FAULT
GPIO3_07 General Purpose Input/Output EC1_GTX_CLK IO
FTM1_EXTCLK
GPIO3_08 General Purpose Input/Output EC1_GTX_CLK12 IO
5
GPIO3_09 General Purpose Input/Output EC1_RXD3 IO
FTM1_CH4
GPIO3_10 General Purpose Input/Output EC1_RXD2 IO
FTM1_CH6
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 203
Signals overview
Table 3-1. LS1043 Signal Reference by Functional Block (continued)
Name Description Alternate Function(s) Pin
type
GPIO3_11 General Purpose Input/Output EC1_RXD1 IO
FTM1_CH1
GPIO3_12 General Purpose Input/Output EC1_RXD0 IO
FTM1_CH0
GPIO3_13 General Purpose Input/Output EC1_RX_CLK IO
FTM1_QD_PHA
GPIO3_14 General Purpose Input/Output EC1_RX_DV IO
FTM1_QD_PHB
GPIO3_15 General Purpose Input/Output EC2_TXD3 IO
TSEC_1588_ALAR
M_OUT2
FTM2_CH5
GPIO3_16 General Purpose Input/Output EC2_TXD2 IO
TSEC_1588_ALAR
M_OUT1
FTM2_CH7
GPIO3_17 General Purpose Input/Output EC2_TXD1 IO
TSEC_1588_CLK_
OUT
FTM2_CH3
GPIO3_18 General Purpose Input/Output EC2_TXD0 IO
TSEC_1588_PULS
E_OUT2
FTM2_CH2
GPIO3_19 General Purpose Input/Output EC2_TX_EN IO
FTM2_FAULT
GPIO3_20 General Purpose Input/Output EC2_GTX_CLK IO
FTM2_EXTCLK
GPIO3_21 General Purpose Input/Output EC2_GTX_CLK12 IO
5
GPIO3_22 General Purpose Input/Output EC2_RXD3 IO
FTM2_CH4
GPIO3_23 General Purpose Input/Output EC2_RXD2 IO
FTM2_CH6
GPIO3_24 General Purpose Input/Output EC2_RXD1 IO
TSEC_1588_PULS
E_OUT1
FTM2_CH1
GPIO3_25 General Purpose Input/Output EC2_RXD0 IO
TSEC_1588_TRIG
_IN2
FTM2_CH0
GPIO3_26 General Purpose Input/Output EC2_RX_CLK IO
TSEC_1588_CLK_I
N
FTM2_QD_PHA
GPIO3_27 General Purpose Input/Output EC2_RX_DV IO
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
204 NXP Semiconductors
Chapter 3 Signal Descriptions
Table 3-1. LS1043 Signal Reference by Functional Block (continued)
Name Description Alternate Function(s) Pin
type
TSEC_1588_TRIG
_IN1
FTM2_QD_PHB
GPIO4_00 General Purpose Input/Output EMI2_MDC IO
GPIO4_01 General Purpose Input/Output EMI2_MDIO IO
GPIO4_02 General Purpose Input/Output IIC2_SCL IO
SDHC_CD_B
FTM3_QD_PHA
CLK9
QE_SI1_STROBE0
BRGO2
GPIO4_03 General Purpose Input/Output IIC2_SDA IO
SDHC_WP
FTM3_QD_PHB
CLK10
QE_SI1_STROBE1
BRGO3
GPIO4_10 General Purpose Input/Output IIC3_SCL IO
EVT5_B
USB2_DRVVBUS
BRGO4
FTM8_CH0
CLK11
GPIO4_11 General Purpose Input/Output IIC3_SDA IO
EVT6_B
USB2_PWRFAULT
BRGO1
FTM8_CH1
CLK12_CLK8
GPIO4_12 General Purpose Input/Output IIC4_SCL IO
EVT7_B
USB3_DRVVBUS
TDMA_RQ
FTM3_FAULT
UC1_CDB_RXER
GPIO4_13 General Purpose Input/Output IIC4_SDA IO
EVT8_B
USB3_PWRFAULT
TDMB_RQ
FTM3_EXTCLK
UC3_CDB_RXER
GPIO4_29 General Purpose Input/Output USB_DRVVBUS IO
GPIO4_30 General Purpose Input/Output USB_PWRFAULT IO
Frequency Timer Module 1 (See LS1043A FlexTimer signals for more details.)
FTM1_CH0 Channel 0 EC1_RXD0 IO
GPIO3_12
FTM1_CH1 Channel 1 EC1_RXD1 IO
GPIO3_11
FTM1_CH2 Channel 2 EC1_TXD0 IO
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 205
Signals overview
Table 3-1. LS1043 Signal Reference by Functional Block (continued)
Name Description Alternate Function(s) Pin
type
GPIO3_05
FTM1_CH3 Channel 3 EC1_TXD1 IO
GPIO3_04
FTM1_CH4 Channel 4 EC1_RXD3 IO
GPIO3_09
FTM1_CH5 Channel 5 EC1_TXD3 IO
GPIO3_02
FTM1_CH6 Channel 6 EC1_RXD2 IO
GPIO3_10
FTM1_CH7 Channel 7 EC1_TXD2 IO
GPIO3_03
FTM1_EXTCLK Ext Clock EC1_GTX_CLK I
GPIO3_07
FTM1_FAULT Fault EC1_TX_EN I
GPIO3_06
FTM1_QD_PHA Phase A EC1_RX_CLK I
GPIO3_13
FTM1_QD_PHB Phase B EC1_RX_DV I
GPIO3_14
Frequency Timer Module 2 (See LS1043A FlexTimer signals for more details.)
FTM2_CH0 Channel 0 EC2_RXD0 IO
GPIO3_25
TSEC_1588_TRIG
_IN2
FTM2_CH1 Channel 1 EC2_RXD1 IO
GPIO3_24
TSEC_1588_PULS
E_OUT1
FTM2_CH2 Channel 2 EC2_TXD0 IO
GPIO3_18
TSEC_1588_PULS
E_OUT2
FTM2_CH3 Channel 3 EC2_TXD1 IO
GPIO3_17
TSEC_1588_CLK_
OUT
FTM2_CH4 Channel 4 EC2_RXD3 IO
GPIO3_22
FTM2_CH5 Channel 5 EC2_TXD3 IO
GPIO3_15
TSEC_1588_ALAR
M_OUT2
FTM2_CH6 Channel 6 EC2_RXD2 IO
GPIO3_23
FTM2_CH7 Channel 7 EC2_TXD2 IO
GPIO3_16
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
206 NXP Semiconductors
Chapter 3 Signal Descriptions
Table 3-1. LS1043 Signal Reference by Functional Block (continued)
Name Description Alternate Function(s) Pin
type
TSEC_1588_ALAR
M_OUT1
FTM2_EXTCLK Ext Clock EC2_GTX_CLK I
GPIO3_20
FTM2_FAULT Fault EC2_TX_EN I
GPIO3_19
FTM2_QD_PHA Phase A EC2_RX_CLK I
GPIO3_26
TSEC_1588_CLK_I
N
FTM2_QD_PHB Phase B EC2_RX_DV I
GPIO3_27
TSEC_1588_TRIG
_IN1
Frequency Timer Module 3 (See LS1043A FlexTimer signals for more details.)
FTM3_CH0 Channel 0 IRQ04 IO
GPIO1_24
TDMA_RXD
UC1_RXD7
TDMA_TXD
FTM3_CH1 Channel 1 IRQ05 IO
GPIO1_25
TDMA_RSYNC
UC1_CTSB_RXDV
FTM3_CH2 Channel 2 IRQ06 IO
GPIO1_26
TDMA_RXD_EXC
TDMA_TXD
UC1_TXD7
FTM3_CH3 Channel 3 IRQ07 IO
GPIO1_27
TDMA_TSYNC
UC1_RTSB_TXEN
FTM3_CH4 Channel 4 IRQ08 IO
GPIO1_28
TDMB_RXD
UC3_RXD7
TDMB_TXD
FTM3_CH5 Channel 5 IRQ09 IO
GPIO1_29
TDMB_RSYNC
UC3_CTSB_RXDV
FTM3_CH6 Channel 6 IRQ10 IO
GPIO1_30
TDMB_RXD_EXC
TDMB_TXD
UC3_TXD7
FTM3_CH7 Channel 7 IRQ03 IO
GPIO1_23
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 207
Signals overview
Table 3-1. LS1043 Signal Reference by Functional Block (continued)
Name Description Alternate Function(s) Pin
type
TDMB_TSYNC
UC3_RTSB_TXEN
FTM3_EXTCLK Ext Clock IIC4_SDA I
GPIO4_13
EVT8_B
USB3_PWRFAULT
TDMB_RQ
UC3_CDB_RXER
FTM3_FAULT Fault IIC4_SCL I
GPIO4_12
EVT7_B
USB3_DRVVBUS
TDMA_RQ
UC1_CDB_RXER
FTM3_QD_PHA Phase A IIC2_SCL I
GPIO4_02
SDHC_CD_B
CLK9
QE_SI1_STROBE0
BRGO2
FTM3_QD_PHB Phase B IIC2_SDA I
GPIO4_03
SDHC_WP
CLK10
QE_SI1_STROBE1
BRGO3
Frequency Timer Module 4 (See LS1043A FlexTimer signals for more details.)
FTM4_CH0 Channel 0 UART2_SOUT IO
GPIO1_16
LPUART1_SOUT
FTM4_CH1 Channel 1 UART2_SIN IO
GPIO1_18
LPUART1_SIN
FTM4_CH2 Channel 2 UART1_RTS_B IO
GPIO1_19
UART3_SOUT
LPUART2_SOUT
FTM4_CH3 Channel 3 UART2_RTS_B IO
GPIO1_20
UART4_SOUT
LPUART4_SOUT
LPUART1_RTS_B
FTM4_CH4 Channel 4 UART1_CTS_B IO
GPIO1_21
UART3_SIN
LPUART2_SIN
FTM4_CH5 Channel 5 UART2_CTS_B IO
GPIO1_22
UART4_SIN
LPUART1_CTS_B
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
208 NXP Semiconductors
Chapter 3 Signal Descriptions
Table 3-1. LS1043 Signal Reference by Functional Block (continued)
Name Description Alternate Function(s) Pin
type
LPUART4_SIN
FTM4_CH6 Channel 6 SDHC_CMD IO
GPIO2_04
LPUART3_SOUT
FTM4_CH7 Channel 7 SDHC_DAT0 IO
GPIO2_05
LPUART3_SIN
FTM4_EXTCLK Ext Clock SDHC_DAT2 I
GPIO2_07
LPUART2_CTS_B
LPUART5_SIN
FTM4_FAULT Fault SDHC_DAT1 I
GPIO2_06
LPUART5_SOUT
LPUART2_RTS_B
FTM4_QD_PHA Phase A SDHC_DAT3 I
GPIO2_08
LPUART6_SOUT
LPUART3_RTS_B
FTM4_QD_PHB Phase B SDHC_CLK I
GPIO2_09
LPUART3_CTS_B
LPUART6_SIN
Frequency Timer Module 5 (See LS1043A FlexTimer signals for more details.)
FTM5_CH0 Channel 0 IFC_A25 IO
GPIO2_25
QSPI_A_DATA3
IFC_CS4_B
IFC_RB2_B
FTM5_CH1 Channel 1 IFC_A26 IO
GPIO2_26
IFC_CS5_B
IFC_RB3_B
FTM5_EXTCLK Ext Clock IFC_A27 I
GPIO2_27
IFC_CS6_B
Frequency Timer Module 6 (See LS1043A FlexTimer signals for more details.)
FTM6_CH0 Channel 0 IFC_PAR0 IO
GPIO2_13
QSPI_B_DATA0
FTM6_CH1 Channel 1 IFC_PAR1 IO
GPIO2_14
QSPI_B_DATA1
FTM6_EXTCLK Ext Clock IFC_PERR_B I
GPIO2_15
QSPI_B_DATA2
Frequency Timer Module 7 (See LS1043A FlexTimer signals for more details.)
FTM7_CH0 Channel 0 IFC_CS1_B IO
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 209
Signals overview
Table 3-1. LS1043 Signal Reference by Functional Block (continued)
Name Description Alternate Function(s) Pin
type
GPIO2_10
FTM7_CH1 Channel 1 IFC_CS2_B IO
GPIO2_11
FTM7_EXTCLK Ext Clock IFC_CS3_B I
GPIO2_12
QSPI_B_DATA3
Frequency Timer Module 8 (See LS1043A FlexTimer signals for more details.)
FTM8_CH0 Channel 0 IIC3_SCL IO
GPIO4_10
EVT5_B
USB2_DRVVBUS
BRGO4
CLK11
FTM8_CH1 Channel 1 IIC3_SDA IO
GPIO4_11
EVT6_B
USB2_PWRFAULT
BRGO1
CLK12_CLK8
LPUART (See Chip LPUART signals for more details.)
LPUART1_CTS_B / Clear to send UART2_CTS_B I
LPUART4_SIN GPIO1_22
UART4_SIN
FTM4_CH5
LPUART1_RTS_B / Request to send UART2_RTS_B O
LPUART4_SOUT GPIO1_20
UART4_SOUT
FTM4_CH3
LPUART1_SIN Receive data UART2_SIN I
GPIO1_18
FTM4_CH1
LPUART1_SOUT Transmit data UART2_SOUT IO
GPIO1_16
FTM4_CH0
LPUART2_CTS_B / Clear to send SDHC_DAT2 I
LPUART5_SIN GPIO2_07
FTM4_EXTCLK
LPUART2_RTS_B / Request to send SDHC_DAT1 O
LPUART5_SOUT GPIO2_06
FTM4_FAULT
LPUART2_SIN Receive data UART1_CTS_B I
GPIO1_21
UART3_SIN
FTM4_CH4
LPUART2_SOUT Transmit data UART1_RTS_B IO
GPIO1_19
UART3_SOUT
FTM4_CH2
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
210 NXP Semiconductors
Chapter 3 Signal Descriptions
Table 3-1. LS1043 Signal Reference by Functional Block (continued)
Name Description Alternate Function(s) Pin
type
LPUART3_CTS_B / Clear to send SDHC_CLK I
LPUART6_SIN GPIO2_09
FTM4_QD_PHB
LPUART3_RTS_B / Request to send SDHC_DAT3 O
LPUART6_SOUT GPIO2_08
FTM4_QD_PHA
LPUART3_SIN Receive data SDHC_DAT0 I
GPIO2_05
FTM4_CH7
LPUART3_SOUT Transmit data SDHC_CMD IO
GPIO2_04
FTM4_CH6
LPUART4_SIN / Receive data UART2_CTS_B I
LPUART1_CTS_B GPIO1_22
UART4_SIN
FTM4_CH5
LPUART4_SOUT / Transmit data UART2_RTS_B IO
LPUART1_RTS_B GPIO1_20
UART4_SOUT
FTM4_CH3
LPUART5_SIN / Receive data SDHC_DAT2 I
LPUART2_CTS_B GPIO2_07
FTM4_EXTCLK
LPUART5_SOUT / Transmit data SDHC_DAT1 IO
LPUART2_RTS_B GPIO2_06
FTM4_FAULT
LPUART6_SIN / Receive data SDHC_CLK I
LPUART3_CTS_B GPIO2_09
FTM4_QD_PHB
LPUART6_SOUT / Transmit data SDHC_DAT3 IO
LPUART3_RTS_B GPIO2_08
FTM4_QD_PHA
QUICC Engine(See QUICC Engine Block Reference Manual with Protocol Interworking for more details.)
CLK10 / QE clock IIC2_SDA I
QE_SI1_STROBE1 GPIO4_03
SDHC_WP
FTM3_QD_PHB
BRGO3
CLK11 QE clock IIC3_SCL I
GPIO4_10
EVT5_B
USB2_DRVVBUS
BRGO4
FTM8_CH0
CLK12_CLK8 QE clock IIC3_SDA I
GPIO4_11
EVT6_B
USB2_PWRFAULT
BRGO1
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 211
Signals overview
Table 3-1. LS1043 Signal Reference by Functional Block (continued)
Name Description Alternate Function(s) Pin
type
FTM8_CH1
CLK9 / QE clock IIC2_SCL I
QE_SI1_STROBE0 GPIO4_02
SDHC_CD_B
FTM3_QD_PHA
BRGO2
QE_SI1_STROBE0 / SI strobe IIC2_SCL O
CLK9 GPIO4_02
SDHC_CD_B
FTM3_QD_PHA
BRGO2
QE_SI1_STROBE1 / SI strobe IIC2_SDA O
CLK10 GPIO4_03
SDHC_WP
FTM3_QD_PHB
BRGO3
UC1_CDB_RXER Receive error IIC4_SCL I
GPIO4_12
EVT7_B
USB3_DRVVBUS
TDMA_RQ
FTM3_FAULT
UC1_CTSB_RXDV Receive data IRQ05 I
GPIO1_25
FTM3_CH1
TDMA_RSYNC
UC1_RTSB_TXEN Transmit enable IRQ07 O
GPIO1_27
FTM3_CH3
TDMA_TSYNC
UC1_RXD7 Receive data IRQ04 I
GPIO1_24
FTM3_CH0
TDMA_RXD
TDMA_TXD
UC1_TXD7 Transmit data IRQ06 O
GPIO1_26
FTM3_CH2
TDMA_RXD_EXC
TDMA_TXD
UC3_CDB_RXER Receive error IIC4_SDA I
GPIO4_13
EVT8_B
USB3_PWRFAULT
TDMB_RQ
FTM3_EXTCLK
UC3_CTSB_RXDV Receive data IRQ09 I
GPIO1_29
FTM3_CH5
TDMB_RSYNC
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
212 NXP Semiconductors
Chapter 3 Signal Descriptions
Table 3-1. LS1043 Signal Reference by Functional Block (continued)
Name Description Alternate Function(s) Pin
type
UC3_RTSB_TXEN Transmit enable IRQ03 O
GPIO1_23
FTM3_CH7
TDMB_TSYNC
UC3_RXD7 Receive data IRQ08 I
GPIO1_28
FTM3_CH4
TDMB_RXD
TDMB_TXD
UC3_TXD7 Transmit data IRQ10 O
GPIO1_30
FTM3_CH6
TDMB_RXD_EXC
TDMB_TXD
Baud rate generator
BRGO1 Baud Rate Generator 1 IIC3_SDA O
GPIO4_11
EVT6_B
USB2_PWRFAULT
FTM8_CH1
CLK12_CLK8
BRGO2 Baud Rate Generator 2 IIC2_SCL O
GPIO4_02
SDHC_CD_B
FTM3_QD_PHA
CLK9
QE_SI1_STROBE0
BRGO3 Baud Rate Generator 3 IIC2_SDA O
GPIO4_03
SDHC_WP
FTM3_QD_PHB
CLK10
QE_SI1_STROBE1
BRGO4 Baud Rate Generator 4 IIC3_SCL O
GPIO4_10
EVT5_B
USB2_DRVVBUS
FTM8_CH0
CLK11
Time Division Multiplexing(See QUICC Engine Block Reference Manual with Protocol Interworking for more
details.)
TDMA_RQ RQ IIC4_SCL O
GPIO4_12
EVT7_B
USB3_DRVVBUS
FTM3_FAULT
UC1_CDB_RXER
TDMA_RSYNC RSYNC IRQ05 I
GPIO1_25
FTM3_CH1
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 213
Signals overview
Table 3-1. LS1043 Signal Reference by Functional Block (continued)
Name Description Alternate Function(s) Pin
type
UC1_CTSB_RXDV
TDMA_RXD / RXD IRQ04 I
TDMA_TXD GPIO1_24
FTM3_CH0
UC1_RXD7
TDMA_RXD_EXC / Recieve Data IRQ06 I
TDMA_TXD GPIO1_26
FTM3_CH2
UC1_TXD7
TDMA_TSYNC TSYNC IRQ07 I
GPIO1_27
FTM3_CH3
UC1_RTSB_TXEN
TDMA_TXD / Transmit Data IRQ04 O
TDMA_RXD GPIO1_24
FTM3_CH0
UC1_RXD7
TDMA_TXD / Transmit Data IRQ06 O
TDMA_RXD_EXC GPIO1_26
FTM3_CH2
UC1_TXD7
TDMB_RQ RQ IIC4_SDA O
GPIO4_13
EVT8_B
USB3_PWRFAULT
FTM3_EXTCLK
UC3_CDB_RXER
TDMB_RSYNC RSYNC IRQ09 I
GPIO1_29
FTM3_CH5
UC3_CTSB_RXDV
TDMB_RXD / RXD IRQ08 I
TDMB_TXD GPIO1_28
FTM3_CH4
UC3_RXD7
TDMB_RXD_EXC / Recieve Data IRQ10 I
TDMB_TXD GPIO1_30
FTM3_CH6
UC3_TXD7
TDMB_TSYNC TSYNC IRQ03 I
GPIO1_23
FTM3_CH7
UC3_RTSB_TXEN
TDMB_TXD / Transmit Data IRQ08 O
TDMB_RXD GPIO1_28
FTM3_CH4
UC3_RXD7
TDMB_TXD / Transmit Data IRQ10 O
TDMB_RXD_EXC GPIO1_30
FTM3_CH6
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
214 NXP Semiconductors
Chapter 3 Signal Descriptions
Table 3-1. LS1043 Signal Reference by Functional Block (continued)
Name Description Alternate Function(s) Pin
type
UC3_TXD7
TSEC_1588(See DPAA reference manual for more details.)
TSEC_1588_ALARM_O Alarm Out EC2_TXD2 O
UT1 GPIO3_16
FTM2_CH7
TSEC_1588_ALARM_O Alarm Out EC2_TXD3 O
UT2 GPIO3_15
FTM2_CH5
TSEC_1588_CLK_IN Clock In EC2_RX_CLK I
GPIO3_26
FTM2_QD_PHA
TSEC_1588_CLK_OUT Clock Out EC2_TXD1 O
GPIO3_17
FTM2_CH3
TSEC_1588_PULSE_OU Pulse Out EC2_RXD1 O
T1 GPIO3_24
FTM2_CH1
TSEC_1588_PULSE_OU Pulse Out EC2_TXD0 O
T2 GPIO3_18
FTM2_CH2
TSEC_1588_TRIG_IN1 Trigger In EC2_RX_DV I
GPIO3_27
FTM2_QD_PHB
TSEC_1588_TRIG_IN2 Trigger In EC2_RXD0 I
GPIO3_25
FTM2_CH0
QSPI (See LS1043A QuadSPI signals for more details.)
QSPI_A_CS0 Chip Select IFC_A16 O
QSPI_A_CS1 Chip Select IFC_A17 O
QSPI_A_DATA0 Data IFC_A22 IO
IFC_WP1_B
QSPI_A_DATA1 Data IFC_A23 IO
IFC_WP2_B
QSPI_A_DATA2 Data IFC_A24 IO
IFC_WP3_B
QSPI_A_DATA3 Data IFC_A25 IO
GPIO2_25
FTM5_CH0
IFC_CS4_B
IFC_RB2_B
QSPI_A_SCK QSPI_A Clock IFC_A18 O
QSPI_B_CS0 Chip Select IFC_A19 O
QSPI_B_CS1 Chip Select IFC_A20 O
QSPI_B_DATA0 Data IFC_PAR0 IO
GPIO2_13
FTM6_CH0
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 215
Configuration signals sampled at reset
Table 3-1. LS1043 Signal Reference by Functional Block (continued)
Name Description Alternate Function(s) Pin
type
QSPI_B_DATA1 Data IFC_PAR1 IO
GPIO2_14
FTM6_CH1
QSPI_B_DATA2 Data IFC_PERR_B IO
GPIO2_15
FTM6_EXTCLK
QSPI_B_DATA3 Data IFC_CS3_B IO
GPIO2_12
FTM7_EXTCLK
QSPI_B_DATA3 Data IFC_CS3_B IO
GPIO2_12
FTM7_EXTCLK
QSPI_B_SCK QSPI_B Clock IFC_A21 O
cfg_dram_type
3.3 Configuration signals sampled at reset
The signals that serve alternate functions as configuration input signals during system
reset are summarized in this table.
Note that throughout this document, the reset configuration signals are described as being
sampled at the negation of PORESET_B. However, there is a setup and hold time for
these signals relative to the rising edge of PORESET_B, as described in the chip's data
sheet document.
The reset configuration signals are multiplexed with other functional signals. The values
on these signals during reset are interpreted to be logic one or zero, regardless of whether
the functional signal name is defined as active-low. The reset configuration signals have
internal pull-up resistors so that if the signals are not driven, the default value is high (a
one), as shown in the table. Some signals must be driven high or low during the reset
period. For details about all the signals that require external pull-up resistors, see the data
sheet document.
Table 3-2. Reset configuration signals
Reset configuration name Functional interface Functional Signal Name Default
cfg_rcw_src[0:7] IFC IFC_AD[8:15] 1111 1111
cfg_rcw_src[8] IFC IFC_CLE 11
cfg_ifc_te IFC IFC_TE 1
cfg_dram_type IFC IFC_A[21] 1
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
216 NXP Semiconductors
Chapter 3 Signal Descriptions
Table 3-2. Reset configuration signals (continued)
Reset configuration name Functional interface Functional Signal Name Default
cfg_gpinput[0:7] IFC IFC_AD[0:7] 1111 1111
cfg_eng_use0 IFC IFC_WE0_B 1
cfg_eng_use1 IFC IFC_OE_B 1
cfg_eng_use2 IFC IFC_WP0_B 1
1. cfg_rcw_src[0:8]=1_1111_1111 is not a valid setting; They must be set to one of the valid options defined in Reset
configuration word (RCW) source
3.4 Signal multiplexing details
Due to the extensive functionality present on the chip and the limited number of external
signals available, several functional blocks share signal resources through multiplexing.
These signals are designated in the Alternate function(s) column of Table 3-1 . In this
case when there is alternate functionality between multiple functional blocks, the signal's
function is determined at the chip level (rather than at the block level) typically by a reset
configuration word (RCW) option. For example, the signal SPI_CS_B[0:3]/
SDHC_DAT[4:7]/GPIO2[0:3] can be utilized by either the SPI block, the eSDHC block,
or by GPIO2. Because these signals alternatively service three different functional
blocks, their function is determined at the chip level by RCW[SPI_BASE]. The following
sections describe external signal functional selection using the RCW.
3.4.1 UART, GPIO, FTM, and LPUART signal multiplexing
The functionality of these signals is determined by the RCW[UART_BASE] and
RCW[UART_EXT]).
Table 3-3. UART signal configuration
Signal name Signal function RCW[UART_BASE] RCW[UART_EXT]
UART1_SOUT GPIO1[15] 0h 000
UART1_SOUT 3h, 4h, 5h, 6h, 7h
UART1_SIN GPIO1[17] 0h 0xx
UART1_SIN 3h, 4h, 5h, 6h, 7h
UART1_SIN Don't care
UART1_RTS_B GPIO1[19] 0h, 3h, 5h 000
UART1_RTS_B 4h, 6h
UART3_SOUT 7h
LPUART2_SOUT Don't care 001/ 010
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 217
Signal multiplexing details
Table 3-3. UART signal configuration (continued)
Signal name Signal function RCW[UART_BASE] RCW[UART_EXT]
FTM4_CH2 Don't care 011
UART1_CTS_B GPIO1[21] 0h, 3h, 5h 000
UART1_CTS_B 4h, 6h
UART3_SIN 7h
LPUART2_SIN Don't care 001/010
FTM4_CH4 Don't care 011
UART2_SOUT GPIO1[16] 0h, 3h, 4h 000
UART2_SOUT 6h, 5h, 7h
LPUART1_SOUT Don't care 001/010
FTM4_CH0 Don't care 011
UART2_SIN GPIO1[18] 0h, 3h, 4h 000
UART2_SIN 6h, 5h, 7h
LPUART1_SIN Don't care 001/010
FTM4_CH1 Don't care 011
UART2_RTS_B GPIO1[20] 0h, 3h, 4h, 5h 000
UART2_RTS_B 6h
UART4_SOUT 7h
LPUART1_RTS_B Don't care 001
LPUART4_SOUT 010
FTM4_CH3 011
UART2_CTS_B GPIO1[22] 0h, 3h, 4h, 5h
UART2_CTS_B 6h
UART4_SIN 7h
LPUART1_CTS_B Don't care 001
LPUART4_SIN 010
FTM4_CH5 011
3.4.2 ASLEEP and GPIO1 signal multiplexing
The power management signal, ASLEEP, is shared with GPO1[13]. The functionality of
this signal is determined by the ASLEEP field in the reset configuration word
(RCW[ASLEEP]).
Table 3-4. ASLEEP signal configuration
Signal name Signal function RCW[ASLEEP]
ASLEEP ASLEEP 0
GPO1[13] 1
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
218 NXP Semiconductors
Chapter 3 Signal Descriptions
3.4.3 RTC and GPIO1 signal multiplexing
The clocking signal, RTC, is shared with GPIO1[14]. The functionality of this signal is
determined by the RTC field in the reset configuration word (RCW[RTC]).
Table 3-5. RTC signal configuration
Signal name Signal function RCW[RTC]
RTC RTC 0
GPIO1[14] 1
3.4.4 eSDHC, GPIO2, and GPIO4 signal multiplexing
The eSDHC interface shares signals with GPIO2 and GPIO4. The functionality of these
signals are determined by the SDHC_BASE and SDHC fields in the reset configuration
word (RCW[SDHC_BASE] and RCW[SDHC]).
Table 3-6. eSDHC BASE signal configuration
Signal name Signal RCW[SDHC_BASE] RCW[SDHC_EXT]
function
SDHC_CMD SDHC_CMD 0 000
GPIO2[4] 1
LPUART3_S Don't care 001/010
OUT
FTM4_CH6 011
SDHC_DAT[0] SDHC_DAT[ 0 000
0]
GPIO2[5] 1
LPUART3_SI Don't care 001/010
N
FTM4_CH7 011
SDHC_DAT[1] SDHC_DAT[ 0 000
1]
GPIO2[6] 1
LPUART2_R Don't care 001
TS_B
LPUART5_S 010
OUT
FTM4_FAUL 011
T
SDHC_DAT[2] SDHC_DAT[ 0 000
2]
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 219
Signal multiplexing details
Table 3-6. eSDHC BASE signal configuration
(continued)
Signal name Signal RCW[SDHC_BASE] RCW[SDHC_EXT]
function
GPIO2[7] 1
LPUART2_C Don't care 001
TS_B
LPUART5_SI 010
N
FTM4_EXTC 011
LK
SDHC_DAT[3] SDHC_DAT[ 0 000
3]
GPIO2[8] 1
LPUART3_R Don't care 001
TS_B
LPUART6_S 010
OUT
FTM4_QD_P 011
HA
SDHC_CLK SDHC_CLK 0 000
GPIO2[9] 1
LPUART3_C Don't care 001
TS_B
LPUART6_SI 010
N
FTM4_QD_P 011
HB
3.4.5 External IRQ, QE, and GPIO1 signal multiplexing
External IRQ share signals with GPIO1. The functionality of these signals is determined
by the IRQ_BASE and IRQ_EXT fields in the reset configuration word
(RCW[IRQ_BASE] and RCW[IRQ_EXT]).
Table 3-7. IRQn signal configuration
Signal name Signal function RCW[IRQ_BASE] RCW[IRQ_EXT]
IRQ[3] IRQ[3] 0 000
GPIO1[23] 1
TDMB_TSYNC Don't care 001
UC3_RTSB_TXEN 010
FTM3_CH7 011
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
220 NXP Semiconductors
Chapter 3 Signal Descriptions
Table 3-7. IRQn signal configuration (continued)
Signal name Signal function RCW[IRQ_BASE] RCW[IRQ_EXT]
IRQ[4] IRQ[4] 0 000
GPIO1[24] 1
TDMA_TXD/TDMA_RXD Don't care 001
UC1_RXD[7] 010
FTM3_CH0 011
IRQ[5] IRQ[5] 0 000
GPIO1[25] 1
TDMA_RSYNC Don't care 001
UC1_CTSB_RXDV 010
FTM3_CH1 011
IRQ[6] IRQ[6] 0 000
GPIO1[26] 1
TDMA_TXD/TDMA_RXD_EXC Don't care 001
UC1_TXD[7] 010
FTM3_CH2 011
IRQ[7] IRQ[7] 0 000
GPIO1[27] 1
TDMA_TSYNC Don't care 001
UC1_RTSB_TXEN 010
FTM3_CH3 011
IRQ[8] IRQ[8] 0 000
GPIO1[28] 1
TDMB_TXD/TDMB_RXD Don't care 001
UC3_RXD[7] 010
FTM3_CH4 011
IRQ[9] IRQ[9] 0 000
GPIO1[29] 1
TDMB_RSYNC Don't care 001
UC3_CTSB_RXDV 010
FTM3_CH5 011
IRQ[10] IRQ[10] 0 000
GPIO1[30] 1
TDMB_TXD/TDMB_RXD_EXC Don't care 001
UC3_TXD[7] 010
FTM3_CH6 011
IRQ[11] IRQ[11] 0 000/011
GPIO1[31] 1
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 221
Signal multiplexing details
3.4.6 SPI, eSDHC, USB and GPIO2 signal multiplexing
The SPI share signals with the eSDHC and GPIO2. The functionality of these signals is
determined by the SPI_BASE and SPI_EXT fields in the reset configuration word
(RCW[SPI_BASE] and RCW[SPI_EXT]).
Table 3-8. SPI Signal configuration
Signal name Signal function RCW[SPI_BASE] RCW[SPI_EXT]
SPI_CS_B[0] SPI_CS_B[0] 00 000/010
SDHC_DAT[4] 01
GPIO2[0] 10
Reserved 11
SDHC_VS Don't care 001
SPI_CS_B[1] SPI_CS_B[1] 00 000/001/010
SDHC_DAT[5] 01
GPIO2[1] 10
SDHC_CMD_DIR 11
SPI_CS_B[2] SPI_CS_B[2] 00 000/001/010
SDHC_DAT[6] 01
GPIO2[2] 10
SDHC_DAT0_DIR 11
SPI_CS_B[3] SPI_CS_B[3] 00 000/001/010
SDHC_DAT[7] 01
GPIO2[3] 10
SDHC_DAT123_DIR 11
SPI_MOSI SPI_MOSI 00 000/010
SDHC_CLK_SYNC_OUT Don't care 001
SPI_MISO SPI_MISO 00 000/010
SDHC_CLK_SYNC_IN Don't care 001
SPI_CLK SPI_CLK 00 000
Reserved Don't care 001
Reserved 010
NOTE
• 8 bit MMC DDR is not supported.
• SPI_CLK is available only when RCW[SPI_EXT]=000
and RCW[SPI_BASE]=00. Some SPI signals are also
available when RCW[SPI_EXT]=010, however SPI_CLK
must be generated by master.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
222 NXP Semiconductors
Chapter 3 Signal Descriptions
3.4.7 IFC, QuadSPI, FTM and GPIO2 signal multiplexing
The integrated Flash controller shares signals with QuadSPI, FTM and GPIO2. The
functionality of these signals is determined by the IFC_GRP_[n]_BASE fields and
IFC_GRP_[m]_BASE]in the reset configuration word as described in the following table.
Table 3-9. IFC signal configuration
Signal Signal IFC_A_22 IFC_GRP_[n]_BASE] IFC_GRP_[m]_EXT]
name function _24 E1 D A F E1 D A
IFC_A[16] IFC_A[16] - - - - 000
QSPI_A_C - - - - 001
S0
IFC_A[17] IFC_A[17] - - - - 000
QSPI_A_C - - - - 001
S1
IFC_A[18] IFC_A[18] - - - - 000
QSPI_A_S - - - - 001 -
CK
IFC_A[19] IFC_A[19] - - - - 000
QSPI_B_C - - - - 001
S0
IFC_A[20] IFC_A[20] - - - - 000
QSPI_B_C - - - - 001
S1
IFC_A[21] IFC_A[21] - - - - 000
QSPI_B_S - - - - 001
CK
IFC_A[22] IFC_A[22] 0 - - 000
IFC_WP_B[ 1 - - 000
1]
QSPI_A_D Don't care - - 001
ATA[0]
IFC_A[23] IFC_A[23] 0 - - 000
IFC_WP_B[ 1 - - 000
2]
QSPI_A_D Don't care - - 001
ATA[1]
IFC_A[24] IFC_A[24] 0 - - 000
IFC_WP_B[ 1 - - 000
3]
QSPI_A_D Don't care - - 001
ATA[2]
IFC_A[25] IFC_A[25] - - - 00 - - - 000
GPIO2[25] - - - 01 - - - 000
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 223
Signal multiplexing details
Table 3-9. IFC signal configuration (continued)
IFC_RB_B[ - - - 10 - - - 000
2]
Reserved - - - 11 - - - 000
QSPI_A_D - - - Don't care - - - 001
ATA[3]
FTM5_CH0 - - - Don't care - - - 010
IFC_CS_B[ - - - Don't care - - - 100
4]
IFC_A[26] IFC_A[26] - - - 00 - - - 000
GPIO2[26] - - - 01 - - - 000
IFC_RB_B[ - - - 10 - - - 000
3]
Reserved - - - 11 - - - 000
QSPI_A_D - - - Don't care - - - 001
QS
FTM5_CH1 - - - Don't care - - - 010
IFC_CS_B[ - - - Don't care - - - 100
5]
IFC_A[27] IFC_A[27] - - - 00 - - - 000
GPIO2[27] - - - 01 - - - 000
QSPI_B_D - - - - - - - 001
QS
FTM5_EXT - - - - - - - 010
CLK
IFC_CS_B[ - - - - - - - 100
6]
IFC_PAR[0 IFC_PAR[0] - - 0 - - - 000 -
] GPIO2[13] - - 1 - - - -
QSPI_B_D - - Don't care - - 001 -
ATA[0]
FTM6_CH0 - - Don't care - - - 010 -
IFC_PAR[1 IFC_PAR[1] - - 0 - - - 000 -
] GPIO2[14] - - 1 - - - 000 -
QSPI_B_D - - Don't care - - - 001 -
ATA[1]
FTM6_CH1 - - Don't care - - - 010 -
IFC_CS_B[ IFC_CS_B[ - 0 - - - 000/001 - -
1] 1]
GPIO2[10] - 1 - - - - -
FTM7_CH0 - Don't care - - - 010 - -
IFC_CS_B[ IFC_CS_B[ - 0 - - - 000/001 - -
2] 2]
GPIO2[11] - 1 - - - - -
FTM7_CH1 - Don't care - - - 010 - -
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
224 NXP Semiconductors
Chapter 3 Signal Descriptions
Table 3-9. IFC signal configuration (continued)
IFC_CS_B[ IFC_CS_B[ - 0 - - - 000 - -
3] 3]
GPIO2[12] - 1 - - - 000 - -
QSPI_B_D - Don't care - - - 001 - -
ATA[3]
FTM7_EXT - - - - 010 - -
CLK
IFC_PERR IFC_PERR - - 0 - - - 000 -
_B _B
GPIO2[15] - - 1 - - -
QSPI_B_D - - Don't care - - - 001 -
ATA[2]
FTM6_EXT - - - - - 010 -
CLK
3.4.8 Ethernet controller 1, FTM1, and GPIO3 signal multiplexing
The Ethernet controller 1 (EC1) RGMII interface shares signals with FTM and GPIO3.
The functionality of these signals is determined by the EC1 field in the reset
configuration word (RCW[EC1]) .
Table 3-10. EC1 RGMII signal configuration
Signal name Signal function RCW[EC1]
EC1_TXD[3:0] EC1_TXD[3:0] 000
GPIO3[2:5] 001
FTM1_CH5, FTM1_CH7, FTM1_CH3, 101
FTM1_CH2
EC1_TX_EN EC1_TX_EN 000
GPIO3[6] 001
FTM1_FAULT 101
EC1_GTX_CLK EC1_GTX_CLK 000
GPIO3[7] 001
FTM1_EXT_CLK 101
EC1_GTX_CLK125 EC1_GTX_CLK125 000
GPIO3[8] 001
EC1_RXD[3:0] EC1_RXD[3:0] 000
GPIO3[9:12] 001
FTM1_CH4, FTM1_CH6, FTM1_CH1, 101
FTM1_CH0
EC1_RX_CLK EC1_RX_CLK 000
GPIO3[13] 001
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 225
Signal multiplexing details
Table 3-10. EC1 RGMII signal configuration (continued)
Signal name Signal function RCW[EC1]
FTM1_QD_PHA 101
EC1_RX_DV EC1_RX_DV 000
GPIO3[14] 001
FTM1_QD_PHB 101
3.4.9 Ethernet controller 2, GPIO3, FTM2, and IEEE1588 signal
multiplexing
The Ethernet controller 2 (EC2) RGMII interface shares signals with GPIO3 and GPIO4.
The functionality of these signals is determined by the EC2 field in the reset
configuration word (RCW[EC2]).
Table 3-11. EC2 RGMII signal configuration
Signal name Signal function RCW[EC2]
EC2_TXD[3:0] EC2_TXD[3:0] 000
GPIO3[15:18] 001
TSEC_1588_ALARM_OUT[2:1], 010
TSEC_1588_CLK_OUT,
TSEC_1588_PULSE_OUT2
FTM2_CH5, FTM2_CH7, FTM2_CH3, FTM2_CH2 101
EC2_TX_EN EC2_TX_EN 000
GPIO3[19] 001, 010
FTM2_FAULT 101
EC2_GTX_CLK EC2_GTX_CLK 000
GPIO3[20] 001, 010
FTM2_EXTCLK 101
EC2_GTX_CLK125 EC2_GTX_CLK125 000
GPIO3[21] 001, 010
EC2_RXD[3:2] EC2_RXD[3:2] 000
GPIO3[22:23] 001, 010
FTM2_CH4, FTM2_CH6 101
EC2_RXD[1] EC2_RXD[1] 000
GPIO3[24] 001
TSEC_1588_PULSE_OUT1 010
FTM2_CH1 101
EC2_RXD[0] EC2_RXD[0] 000
GPIO3[25] 001
FTM2_CH0 101
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
226 NXP Semiconductors
Chapter 3 Signal Descriptions
Table 3-11. EC2 RGMII signal configuration (continued)
Signal name Signal function RCW[EC2]
TSEC1588_TRIG_IN2 010
EC2_RX_DV EC2_RX_DV 000
GPIO3[27] 001
TSEC1588_TRIG_IN1 010
FTM2_QD_PHB 101
EC2_RX_CLK EC2_RX_CLK 000
GPIO3[26] 001
TSEC_1588_CLK_IN 010
FTM2_QD_PHA 101
3.4.10 Ethernet management interface1 and GPIO3 signal
multiplexing
The Ethernet management interface1 (EMI1) shares signals with GPIO3. The
functionality of these signals is determined by the EM1 field in the reset configuration
word (RCW[EM1]) .
Table 3-12. EC1 RGMII signal configuration
Signal name Signal function RCW[EM1]
EMI1_MDC EMI1_MDC 0
GPIO_3[0] 1
EMI1_MDIO EMI1_MDIO 0
GPIO_3[1] 1
3.4.11 Ethernet management interface2 and GPIO4 signal
multiplexing
The Ethernet management interface 2 (EMI2) shares signals with GPIO4. The
functionality of these signals is determined by the EM2 field in the reset configuration
word (RCW[EM2]) .
Table 3-13. EC1 RGMII signal configuration
Signal name Signal function RCW[EM2]
EMI2_MDC EMI1_MDC 0
GPIO_4[0] 1
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 227
Signal multiplexing details
Table 3-13. EC1 RGMII signal configuration (continued)
Signal name Signal function RCW[EM2]
EMI2_MDIO 0
GPIO_4[1] 1
3.4.12 I2C2, GPIO4, FTM, QE and eSDHC signal multiplexing
The I2C2 interface shares signals with GPIO4 and esDHC. The functionality of these
signals is determined by the RCW[I2C2_EXT].
Table 3-14. I2C2 signal configuration
Signal name Signal function RCW[I2C2_EXT]
IIC2_SCL IIC2_SCL 000
SDHC_CD_B 001
GPIO_4[2] 010
FTM3_QD_PHA 011
QE_SI1_STROBE[0] 100
CLK9 101
BRGO2 110
IIC2_SDA IIC2_SDA 000
SDHC_WP 001
GPIO_4[3] 010
FTM3_QD_PHB 011
QE_SI1_STROBE[1] 100
CLK10 101
BRGO3 110
3.4.13 USB and GPIO4 signal multiplexing
The USB (USB_DRVVBUS/USB_PWRFAULT) shares signals with GPIO4. The
functionality of these signals is determined by the reset configuration word (RCW).
Table 3-15. USB signal configuration
Signal name Signal function RCW[USB_DRVVBUS]/
RCW[USB_PWRFAULT]
USB_DRVVBUS USB_DRVVBUS 0
GPIO4[29] 1
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
228 NXP Semiconductors
Chapter 3 Signal Descriptions
Table 3-15. USB signal configuration
(continued)
Signal name Signal function RCW[USB_DRVVBUS]/
RCW[USB_PWRFAULT]
USB_PWRFAULT USB_PWRFAULT 0
GPIO4[30] 1
3.5 Output Signal States During Reset
When a system reset is initiated (HRESET_B or PORESET_B sampled asserted by the
chip), the chip aborts all current internal and external transactions and releases the
bidirectional I/O signals to a high-impedance state. However, some signals get stable
values at power-on reset.
While the the chip is in reset, it drives HRESET_B asserted and ignores most input
signals (except for the reset configuration signals) and drives output-only signal
MODT[0:1]) to an inactive state. Signal MCKE[0:1] is driven to an inactive state after
PORESET_B is de-asserted.
Note that signals associated with all potential RCW source interfaces are enabled and
active while the chip is in reset (that is, while HRESET_B is being driven asserted by the
chip, but after PORESET_B is deasserted). This is necessary to allow the interfaces to be
used for fetching configuration information from non-volatile memory devices.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 229
Output Signal States During Reset
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
230 NXP Semiconductors
Chapter 4
Reset, Clocking, and Initialization
4.1 Reset, clocking, and initialization overview
This content describes the reset, clocking, and initialization, including a definition of the
reset configuration signals and the options they select.Note that other chapters in this
book may describe specific aspects of initialization for individual blocks.
The reset, clocking, and control signals provide many options for operation. Additionally,
many modes are selected with reset configuration signals during a power on reset
(assertion of PORESET_B) and by using the reset configuration word (RCW)
functionality.
4.2 External signal descriptions
The table below summarizes the external signals described in this chapter.
Table 4-3 and Table 4-4 have detailed signal descriptions, but this table contains
references to additional sections that contain more information.
Table 4-1. Reset and Control Signals Summary
Signal I/O Description References
(Section/Page)
PORESET_B I Power on reset input. Table 4-3
HRESET_B I/O Hard reset input. Functions as an output Table 4-3
during initial steps in the power on reset
sequence. See Power-on reset sequence
for more information. For reset assertion to
the chip, use only PORESET_B.
RESET_REQ_B O Reset request output. An internal block Table 4-3
requests that either HRESET_B or
PORESET_B be asserted.
CKSTP_OUT_B O Checkstop out. Table 4-3
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 231
External signal descriptions
Table 4-1. Reset and Control Signals Summary (continued)
Signal I/O Description References
(Section/Page)
This signal is reserved for internal use.
Refer the chip specific design checklist for
more information.
ASLEEP O Asleep Table 4-3
TA_TMP_DETECT_B I Tamper Detect. Table 4-3
TA_BB_TMP_DETECT_B I Low Power Tamper Detect. Table 4-3
Table 4-2. Clock Signals Summary
Signal I/O Description References
SYSCLK I Primary clock input. Table 4-4
DIFF_SYSCLK I Single Oscillator Source" Table 4-4
Clock Differential (positive)
DIFF_SYSCLK_B I Single Oscillator Source" Table 4-4
Clock Differential (positive)
RTC I Real time clock input. Table 4-4
TA_BB_RTC I Low-power real time clock. Table 4-4
This signal is reserved for
internal use. Refer the chip
specific design checklist for
more information.
SD_REF_CLKn_P/ I SerDes high-speed interface Table 4-4
SD_REF_CLKn_N reference clock n.
CLK_OUT O Diagnostic clock output. Table 4-4
DDRCLK I Reference clock for DDR Table 4-4
controller.
The following sections describe the reset and clock signals in detail.
4.2.1 System control signals
The table below describes some of the system control signals. Power-on reset
configuration describes the signals that also function as reset configuration signals.
Table 4-3. System control signals: Detailed signal descriptions
Signal I/O Description
PORESET_B I Power on reset. Causes the chip to abort all current internal and external
transactions and set all registers to their default values. PORESET_B may be
asserted completely asynchronously with respect to all other signals.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
232 NXP Semiconductors
Chapter 4 Reset, Clocking, and Initialization
Table 4-3. System control signals: Detailed signal descriptions (continued)
Signal I/O Description
State Asserted/Negated-See Signal Descriptions and Power-on reset
Meaning configuration for more information on the interpretation of the other
signals during reset.
Timing Assertion/Negation-The chip data sheet gives specific timing
information for this signal and the reset configuration signals.
HRESET_B I/O Hard reset. Causes the chip to abort all current internal and external transactions
and set all registers to their default values. HRESET_B may be asserted completely
asynchronously with respect to all other signals. HRESET_B is driven as an output
during the first part of the power on reset sequence, after which, it becomes an
input, allowing external devices to stall/hold the reset sequence. See Hard reset
sequence for more information. For reset assertion to the chip, use only
PORESET_B.
State Asserted/Negated-See and Power-on reset configuration for more
Meaning information on the interpretation of the other signals during reset.
Timing Assertion/Negation-The chip data sheet gives specific timing
information for this signal.
RESET_REQ_B O Reset request. Indicates to the board (system in which the chip is embedded) that a
condition requiring the assertion of HRESET_B or PORESET_B has been detected.
State Asserted-An event has triggered a request for either a hard reset or a
Meaning power on reset. See Reset Request Status Register
(DCFG_CCSR_RSTRQSR1)
Negated-Indicates no reset request.
Timing Assertion/Negation-May occur any time. Once asserted,
RESET_REQ_B does not negate until either HRESET_B or
PORESET_B is asserted.
CKSTP_OUT_B O Checkstop out.
Note that in LS1043A chip this signal is reserved for internal use. For more
information, refer the chip specific design checklist.
State Asserted-Indicates that the chip is in a checkstop state.
Meaning
Negated-Indicates normal operation. After CKSTP_OUT_B has been
asserted, it is negated after the next negation (low-to-high transition)
of PORESET_B.
Timing Assertion-May occur at any time; may be asserted asynchronously to
the input clocks.
Negation-Must remain asserted until the chip has been reset with a
PORESET_B.
ASLEEP O Power Management Signal. See External Signal Description
TA_TMP_DETECT_B I Tamper Detect.
TA_BB_TMP_DETECT_B I Low Power Tamper Detect.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 233
Clocking Memory Map
4.2.2 External clock signals
The table below describes some of the external clock signals of the chip. Note that some
clock signals are specific to modules within the chip, and although some of their
functionality is described here, they are defined in detail in their respective chapters.
Table 4-4. Clock External Signals-Detailed Signal Descriptions
Signal I/O Description
SYSCLK I System clock (SYSCLK). SYSCLK is the primary clock input to the chip.
Timing Assertion/Negation-See the chip data sheet for specific timing
information for this signal.
DIFF_SYSCLK, DIFF_SYSCLK_B I Differential system clock positive terminal /Differential system clock negative
terminal. These signals provide the clock to System Clock associated PLL’s and if
programmed to DDR PLL.
Timing Assertion/Negation-See the chip data sheet for specific timing
information for this signal.
RTC I Real time clock. The RTC timing specifications are given in the chip data sheet .
Timing Assertion/Negation-See the chip data sheet for specific timing
information for this signal.
TA_BB_RTC I This signal is reserved for internal use.
Timing Assertion/Negation-Refer the chip specific design checklist for more
information.
SD_REF_CLKn_P, I SerDes high-speed interface differential reference clocks. These differential clock
SD_REF_CLKn_N inputs are used to independently clock the banks/ports of high-speed differential
signal lanes available on the chip. The SerDes reference clock timing specifications
are given in the chip data sheet . See the Valid reference clocks and PLL
configurations for SerDes protocols in the SerDes module chapter.
Timing Assertion/Negation-See the chip data sheet for specific timing
information for these signals.
CLK_OUT O Diagnostic clock output. This output may be configured to offer one of a variety of
internal system clocks to external hardware for diagnostic or debug purposes. See
CLK_OUT configuration.
DDRCLK I DDR controller complex clock. DDRCLK is the reference clock to the DDR PLL.
4.3 Clocking Memory Map
The following table summarizes the memory mapped registers which are used to
configure clocking features.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
234 NXP Semiconductors
Chapter 4 Reset, Clocking, and Initialization
Clocking memory map
Offset
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Core cluster n clock control/status register
1EE_1000 32 R/W 0000_0000h 4.3.1/235
(Clocking_CLKCCSR)
Clock generator n hardware accelerator control/status
1EE_1010 32 R/W 0000_0000h 4.3.2/236
register (Clocking_CL1KCGHWACSR)
Clock generator n hardware accelerator control/status
1EE_1030 32 R/W 0000_0000h 4.3.2/236
register (Clocking_CL2KCGHWACSR)
1EE_1800 PLL cluster n general status register (Clocking_PLLC1GSR) 32 R 0000_0000h 4.3.3/238
1EE_1820 PLL cluster n general status register (Clocking_PLLC2GSR) 32 R 0000_0000h 4.3.3/238
Platform clock domain control/status register
1EE_1A00 32 R/W 0000_0000h 4.3.4/240
(Clocking_CLKPCSR)
1EE_1C00 Platform PLL general status register (Clocking_PLLPGSR) 32 R/W 0000_0000h 4.3.5/241
1EE_1C20 DDR PLL general status register (Clocking_PLLDGSR) 32 R/W 0000_0000h 4.3.6/243
4.3.1 Core cluster n clock control/status register
(Clocking_CLKCCSR)
The CLKCnCSR registers control the clock frequency selection for each core cluster.
Table 4-5. Core cluster assignments to CLKCnCSR registers
Register Cluster Group Core Cluster
CLKC1CSR Cluster Group A (CGA) Core Cluster 1
Address: 1EE_1000h base + 0h offset = 1EE_1000h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
Reserved
CLKSEL Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 235
Clocking Memory Map
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Clocking_CLKCCSR field descriptions
Field Description
0 This field is reserved.
- Reserved
1–4 Clock Select. Selects the clock source for the corresponding core cluster. See Table 4-5 above.
CLKSEL
0000 Corresponding cluster group PLL1 output
0001 Corresponding cluster group PLL1 output divide-by-2
0010 Reserved
0011 Reserved
0100 Corresponding cluster group PLL2 output
0101 Corresponding cluster group PLL2 output divide-by-2
0110 Corresponding cluster group PLL2 output divide-by-4
0111-1111 Reserved
5–31 This field is reserved.
- Reserved
4.3.2 Clock generator n hardware accelerator control/status register
(Clocking_CLnKCGHWACSR)
The CLKCGnHWACSR registers control the clock frequency selection for each
hardware accelerator.
Table 4-6. Hardware accelerator assignments to CLKCGnHWACSR registers
Register Cluster Group Mux Hardware Accelerator
CLKCG1HWACSR CGA M1 FMan
Refer
RCW[HWA_CGA_M1_CLK_S
EL] for more information.
CLKCG2HWACSR CGA M2 eSDHC
QuadSPI
Refer
RCW[HWA_CGA_M2_CLK_S
EL] for more information.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
236 NXP Semiconductors
Chapter 4 Reset, Clocking, and Initialization
Address: 1EE_1000h base + 10h offset + (32d × i), where i=0d to 1d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
Reserved
HWACLKSEL Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Clocking_CLnKCGHWACSR field descriptions
Field Description
0 This field is reserved.
- Reserved
1–4 Hardware accelerator clock select. Selects the clock source for peripheral hardware accelerators. See
HWACLKSEL Table 4-6 above.
CLKCG1HWACSR[HWACLKSEL] reflects the values programmed in RCW[HWA_CGA_M1_CLK_SEL]
and CLKCG2HWACSR[HWACLKSEL] reflects the values programmed in
RCW[HWA_CGA_M2_CLK_SEL].
CLKCG1HWACSR (CGA_M1):
0000 Reserved
0001 Reserved
0010 CGA PLL1 divide-by-2
0011 CGA PLL1 divide-by-3
0100 Reserved
0101 Reserved
0110 CGA PLL2 divide-by-2
0111 CGA PLL2 divide-by-3
CLKCG2HWACSR (CGA_M2):
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 237
Clocking Memory Map
Clocking_CLnKCGHWACSR field descriptions (continued)
Field Description
0000 Reserved
0001 CGA PLL2 divide-by-1
0010 Reserved
0011 CGA PLL2 divide-by-3
0100-1111 Reserved
5–31 This field is reserved.
- Reserved
4.3.3 PLL cluster n general status register (Clocking_PLLCnGSR)
The PLLCnGSR registers provide information regarding the cluster PLL configuration.
Table 4-7. PLL assignments to PLLCnGSR
registers
Register Cluster Group PLL
PLLC1GSR CGA PLL1
PLLC2GSR CGA PLL2
Address: 1EE_1000h base + 800h offset + (32d × i), where i=0d to 1d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
KILL Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
238 NXP Semiconductors
Chapter 4 Reset, Clocking, and Initialization
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R CFG
Reserved
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Clocking_PLLCnGSR field descriptions
Field Description
0 Writing a 1 to this bit disables the PLL.
KILL
If PLLnGSR[CFG] indicates 0b00000, the PLL is bypassed and this bit (KILL) is set.
0 PLL is active.
1 PLL is disabled.
1–22 This field is reserved.
- Reserved
23–30 Reflects the current PLL multiplier configuration. Indicates the frequency for this PLL.
CFG
PLLC1GSR[CFG] reflects the values programmed in RCW[CGA_PLL1_RAT] and PLLC2GSR[CFG]
reflects the values programmed in RCW[CGA_PLL2_CFG].
Defined settings are from 00_0101 (5:1) through 10_1000 (40:1).
All other encodings are reserved.
NOTE: Not all ratios are supported due to frequency restrictions. Refer to the chip data sheet for the
supported frequencies.
31 This field is reserved.
- Reserved
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 239
Clocking Memory Map
4.3.4 Platform clock domain control/status register
(Clocking_CLKPCSR)
The CLKPCSR register selects which signal to observe on the CLK_OUT pad.
Address: 1EE_1000h base + A00h offset = 1EE_1A00h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CLKOEN
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
CLKOSEL CLKODIV Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Clocking_CLKPCSR field descriptions
Field Description
0–14 This field is reserved.
- Reserved
15 CLK_OUT pad enable
CLKOEN
0 Release CLK_OUT pad to high impedance
1 Enable CLK_OUT pad
16–20 Selects core related clock signal for observation on CLK_OUT pad
CLKOSEL
11011 Platform Clock /2
11110 Platform feedback clock
11111 SYSCLK
All others Reserved
21–22 Selects division setting for clock-out mux output to reduce the frequency of the signal to a more
CLKODIV observable/measurable range.
00 No division (divide-by-1)
01 Divide-by-2
10 Divide-by-4
11 Divide-by-8
23–31 This field is reserved.
- Reserved
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
240 NXP Semiconductors
Chapter 4 Reset, Clocking, and Initialization
4.3.5 Platform PLL general status register (Clocking_PLLPGSR)
The PLLPGSR register provides information regarding the PLL's configuration.
Address: 1EE_1000h base + C00h offset = 1EE_1C00h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R CFG
Reserved Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 241
Clocking Memory Map
Clocking_PLLPGSR field descriptions
Field Description
0–24 This field is reserved.
- Reserved
25–30 Reflects the current PLL multiplier configuration. Indicates the frequency for this PLL.
CFG
Reflects the values programmed in RCW[SYS_PLL_RAT].
Defined settings are from 0_0111 (7:1) through 1_0000 (16:1).
All other encodings are reserved.
NOTE: Not all ratios are supported due to frequency restrictions. Refer to the chip data sheet for the
supported frequencies.
31 This field is reserved.
- Reserved
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
242 NXP Semiconductors
Chapter 4 Reset, Clocking, and Initialization
4.3.6 DDR PLL general status register (Clocking_PLLDGSR)
The PLLDGSR register provides information regarding the DDR PLL configuration.
Address: 1EE_1000h base + C20h offset = 1EE_1C20h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
KILL Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R CFG
Reserved Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 243
Functional description
Clocking_PLLDGSR field descriptions
Field Description
0 Writing a 1 to this bit disables the PLL.
KILL
If PLLnGSR[CFG] indicates 0b00000, the PLL is bypassed and this bit (KILL) is set. 0 PLL is active.
1 PLL is disabled.
1–22 This field is reserved.
- Reserved
23–30 Reflects the current PLL multiplier configuration. Indicates the frequency for this PLL.
CFG
Reflects the values programmed in RCW[MEM_PLL_RAT].
31 This field is reserved.
- Reserved
4.4 Functional description
This section describes the various ways to reset the chip, the POR sequence, the hard
reset sequence, the POR configurations, the reset configuration word (RCW), and the
clocking on the device.
4.4.1 Power-on reset sequence
Assertion of the external PORESET_B signal initiates the power-on reset flow.
See the chip data sheet for more information regarding power sequencing and
PORESET_B input requirements.
After the negation of PORESET_B, the reset control logic begins cycling the device
through its full reset and RCW configuration process. The chip asserts HRESET_B
throughout the power-on reset process, including RCW configuration. Reset and RCW
configuration time varies depending on the configuration source and SYSCLK frequency.
Initially, the RCW source POR configuration inputs are sampled to determine the
configuration source. Next, the device begins loading the RCW data. The system PLL
begins to lock according to the clock ratio/mode values communicated in the RCW data.
Once the PLL locks and the RCW data is loaded, HRESET_B is released by the device
and the clocking unit begins distributing PLL outputs throughout the device. Pre-boot
initialization is then optionally performed, and the cores are permitted to boot.
The detailed POR sequence for the device is as follows:
1. The external logic drives cfg_eng_use0 to a valid state. An internal multiplexer
selects between differential and single ended clock correspondingly.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
244 NXP Semiconductors
Chapter 4 Reset, Clocking, and Initialization
2. The external system logic asserts PORESET_B and power is applied to comply with
the chip's data sheet .
3. PORESET_B asserted causes all registers to be initialized to their default states and
most I/O drivers to be released to high impedance (some clock, clock enables, and
system control signals are active).
NOTE
The common on-chip processor (COP) requires the ability
to independently assert PORESET_B and TRST_B to fully
control the processor. If a JTAG/COP port is used, follow
the JTAG/COP interface connection recommendations
given in the chip's data sheet . If the JTAG interface and
COP header are not being used, it is recommended that
TRST_B be tied to PORESET_B so that TRST_B is
asserted when PORESET_B is asserted, ensuring that the
JTAG scan chain is initialized during the power-on reset
flow. See the JTAG configuration signals section in the
chip's data sheet for more information.
4. The system applies a toggling SYSCLK signal and stable POR configuration inputs.
At this point, SYSCLK is propagated throughout the device; the platform PLL is
running in bypass mode.
5. The device begins driving HRESET_B asserted after sampling the assertion of
PORESET_B.
6. External system logic negates PORESET_B after its required hold time and after
POR configuration inputs have been valid for their required setup times.
7. The device samples the RCW source POR configuration inputs (cfg_rcw_src[0:n])
on deassertion of PORESET_B to determine the RCW source. Note that the POR
configuration inputs are sampled only on a PORESET_B.
8. The device initiates and completes reset of the rest of the platform logic. Note that
this platform reset step is the point where the device hard reset process (HRESET_B)
begins if an external device asserts HRESET_B (assuming the device is not already
sequencing through the power-on reset process).
9. Some of the I/O drivers are enabled; specifically, any signals required by the
interface specified as the source of RCW data in cfg_rcw_src[0:n]. All of the DDR
I/Os become enabled at this point (though MCKE, MCK, MODT are enabled from
the beginning). The ASLEEP signal is also enabled at this point.
10. If the IFC's NAND Flash interface is configured as the RCW source, the reset block
instructs the IFC to load a boot block from Flash into the internal buffer RAM of the
IFC. Once complete, the reset block proceeds to instruct the Pre-Boot Loader to
begin reading in RCW data. Note that if the IFC NAND Flash interface reports an
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 245
Functional description
ECC error, the device reset sequence is halted indefinitely, waiting for another
PORESET_B or hard reset.
11. The pre-boot loader (PBL) starts loading the RCW data from the interface specified
by cfg_rcw_src[0:n] configuration inputs and stores that 64 bytes of data to the
RCWSR registers within the device configuration block. Loading time varies and
depends on the source of the RCW. Note that if a hard-coded RCW option is used,
this PBL RCW loading process is effectively bypassed and the device is
automatically configured according to the specific RCW field encodings pre-
assigned for the given hard-coded RCW option (see Table 4-14) for more
information .
12. The PLLs begin to lock.
13. The sequence then waits for the PBL RCW process to be completed (loading of all
512 bits). If the PBL reports an error during its process of loading the RCW data, the
device reset sequence is halted indefinitely, waiting for another PORESET_B or hard
reset.
14. The platform clock tree is then switched over and is driven by the output of the
platform PLL.
15. The device stops driving HRESET_B at this point. All other I/O drivers are enabled
at this point.
16. If the IFC's NAND Flash interface is:
• configured as the pre-boot initialization source
OR
• the boot device target AND not fused as secure boot
AND
• the IFC's NAND Flash interface was NOT previously used as the RCW source,
then the reset block informs the IFC to load a boot block from Flash into the
internal buffer RAM of the IFC. Once complete, the IFC signals back to the reset
block, and the reset block can proceed. Note that if the IFC reports an ECC error,
the device reset sequence is halted indefinitely, waiting for a hard reset or
PORESET_B.
17. The PBL performs pre-boot initialization, if enabled by RCW, by reading data from
either the eSDHC, QuadSPI, or IFC interface and writing to CCSR space or local
memory space (OCRAM1 or OCRAM2, DDR). If the PBL reports an error during its
pre-boot initialization process, the device reset sequence is halted indefinitely,
waiting for a hard reset or PORESET_B.
18. Any external device optionally driving HRESET_B negates it if not done earlier. If
other external devices do not release HRESET_B, the device reset sequence stalls at
this point.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
246 NXP Semiconductors
Chapter 4 Reset, Clocking, and Initialization
19. System ready state. The peripheral interfaces are released to accept external requests,
and the boot vector fetches by the cores are allowed to proceed unless processor
booting is further held off by the boot release register (BRR) in the device
configuration module. The ASLEEP signal negates synchronized to a rising edge of
SYSCLK, indicating the ready state of the system. After reaching this system ready
state, the ASLEEP signal transitions to the asserted state when the device enters sleep
mode.
NOTE
After completing reset, software should check the
SerDesx_PLLnRSTCTL[RST_DONE] field to make sure that
each active SerDes PLL on the device has locked. Transactions
or packet data cannot be transferred through the targeted lane(s)
of the SerDes interface if the PLL associated with the lane(s)
does not lock properly. Note that a SerDes PLL will not lock if
the corresponding reference clock is not provided.
Figure below shows a timing diagram of the POR sequence.
PORESET_B
HRESET_B
(high impedance)
RESET_REQ_B
(high impedance)
ASLEEP
SYSCLK
POR Configs
Figure 4-1. Power-on reset sequence
4.4.2 Hard reset sequence
The hard reset sequence is initiated by the external system asserting HRESET_B. Upon
sampling the HRESET_B asserted, the device then begins driving HRESET itself
throughout the hard reset state.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 247
Functional description
Reset and RCW configuration time varies subject to the configuration source and
SYSCLK frequency. The reset configuration input signals are not sampled by a hard reset
(only a power-on reset), so the device immediately begins loading RCW data and
configures the device as explained in Reset configuration word (RCW). After the
configuration sequence completes, the device releases the HRESET signal and exits the
hard reset state. After negation is detected, a 16-cycle period is taken before testing for
the presence of an external reset. The hard reset sequence begins with reset of the device
at step 8 in Power-on reset sequence.
4.4.3 Core soft reset
The following steps need to be performed by the software for the core soft reset:
1. Write 1 to SCFG_CORESRENCR[CORESREN] bit, to enable the soft reset to the
corresponding core.
2. Write 1 to SCFG_CORE0_SFT_RST[SOFT_RESET],
SCFG_CORE1_SFT_RST[SOFT_RESET],
SCFG_CORE2_SFT_RST[SOFT_RESET], and
SCFG_CORE3_SFT_RST[SOFT_RESET] to enable the soft reset to the core 0, core
1, core 2, and core 3 respectively. Writing to this bit triggers the corresponding
interrupt to respective cores (Interrupt ID 196 and Interrupt ID 197). The interrupts
need to configured as edge trigger interrupt.
3. Perform the GIC interrupt mapping:
• Enable the interrupt.
• Select edge trigger mode.
• Route 196 to core 0, 197 to core 1, 200 to core 2, and 201 to core 3.
4. In the core corresponding ISR will be programmed with WFI.
5. Core executes WFI instructions after receiving the interrupt.
6. Once the core executes WFI instruction, COP generates the corresponding core soft
reset.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
248 NXP Semiconductors
Chapter 4 Reset, Clocking, and Initialization
4.4.4 RCW state timing
The following table provides the state timing for diffrent RCW/PBI source.
Table 4-8. RCW state timing
RCW/PBI RCW RCW source System PLL RCW source PBI Time(no. No. of
source loading time interface locking time interface of platform transactions
(no. of frequency (RCW (no. of SYSCLK frequency (PBI clock cycles) in PBI
SYSCLK loading phase in cycles) phase in terms
cycles) terms of SYSCLK of platform
ratio) clock ratio)
NAND-16 (2K 234322 SYSCLK/4 68616 platform clock/8 381814 2 writes of 4
page size) byte each
NOR-16 47260 SYSCLK/4 68616 platform clock/8 9454 2 writes of 4
byte each
SD 811549 SYSCLK/512 68616 platform clock/80 137018 2 writes of 4
byte each
QuadSPI 283242 SYSCLK/256 68616 platform 19053 2 writes of 4
clock/256 byte each
The figure below shows the reset timeline diagram in accordance with the power-on reset
sequence.
Platform operating at SYSCLK Platform operating at platform PLL clock
Step 6 Step 10, 12 Step 11 Step 13 Step 16 Step 18
PORESET Platform clock
deassertion PBL loads RCW PLL locking switching happens PBI phase System ready
Figure 4-2. Reset Timeline Diagram
4.4.5 Power-on reset configuration
Various device functions are initialized by sampling certain signals during power on
reset.
The values of all these signals are sampled into registers when PORESET_B is
deasserted. These inputs are to be pulled high or low by external resistors. During
PORESET_B, all other signal drivers connected to these signals must be in the high-
impedance state.
All POR configuration signals have internal pull-up resistors so that if the desired setting
is high, there is no need for a pull-up resistor on the board. See the chip data sheet for
proper pull-down resistor values for POR configuration signals, when necessary.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 249
Functional description
This section describes the functions and modes configured by the POR configuration
signals.
NOTE
In the following tables, the binary value 0 represents a signal
pulled down to GND and a value of 1 represents a signal pulled
up to that signal's corresponding VDD voltage level, regardless
of the sense of the functional signal name.
4.4.5.1 Reset configuration word (RCW) source
The reset configuration word (RCW) source inputs, cfg_rcw_src[0:8], are multiplexed on
{IFC_AD[8:15], IFC_CLE}. These configuration inputs select the source for the RCW
data as shown in the following table. The encoded values latched on these signals during
POR are accessible in PORSR1[RCW_SRC], as described in POR Status Register 1
(DCFG_CCSR_PORSR1).
Table 4-9. RCW source encodings
cfg_rcw_src value RCW source
(Binary)
0_0000_xxxx Reserved
0_0001_xxxx 8-bit NOR Flash
cfg_rcw_src[5]:
0 Address shift "left" (most significant bits are IFC_AD[0:n-1]
1 Address shift "right" (least significant bits are IFC_AD[0:n-1]
cfg_rcw_src[6:7]:
00 Shift left by 10 to provide 22b addressability OR shift right by appropriate amount
(depends on Port Size selected) and provide 22b addressability.
01 Shift left by 7 to provide up to 25b addressability OR shift right by appropriate amount
(depends on Port Size selected) and provide up to 25b addressability.
10 Shift left by 4 to provide up to 28b addressability OR shift right by appropriate amount
(depends on Port Size selected) and provide up to 28b addressability.
cfg_rcw_src[8]:
0 CS before AVD (address valid supports internal latch based asynchronous NOR
devices)
1 AVD before CS (supports simple asynchronous NOR devices)
0_0010_xxxx 16-bit NOR Flash
cfg_rcw_src[5:8] encodings are the same as those described for 0_0001_xxxx (8-bit
NOR Flash)
0_0011_000-0_0011_1111 Reserved
0_0100_00001 SD/MMC (eSDHC)
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
250 NXP Semiconductors
Chapter 4 Reset, Clocking, and Initialization
Table 4-9. RCW source encodings (continued)
cfg_rcw_src value RCW source
(Binary)
0_0100_0001-0_0100_0011 Reserved
0_0100_010x1 QuadSPI (QuadSPI)
0_0100_0110-0_0100_1001 Reserved
0_0100_1010-0_0111_1111 Reserved
0_100x_xxxx1 Reserved
0_1010_0000-0_1111_1111 Reserved
1_0000_00xx 8-bit NAND Flash, 512-byte page, 32 pages/block
cfg_rcw_src[7]:
0 Bad Block Indicator in page 0/1
1 Bad Block Indicator in page 0 or last page
cfg_rcw_src[8]:
0 ECC disabled
1 4 bits per 520 bytes
1_0000_01xx 8-bit NAND Flash, 2 KB page, 64 pages/block
cfg_rcw_src[7:8] encodings are the same as those described for 1_0000_00xx (8-bit
NAND Flash, 512-byte page, 32 pages/block)
1_0000_10xx 8-bit NAND Flash, 2 KB page, 128 pages/block
cfg_rcw_src[7:8] encodings are the same as those described for 1_0000_00xx (8-bit
NAND Flash, 512-byte page, 32 pages/block)
1_0000_11xx Reserved
1_0001_xxxx 8-bit NAND Flash, 4 KB page, 128 pages/block
cfg_rcw_src[5]:
0 Bad Block Indicator in page 0/1
1 Bad Block Indicator in page 0 or last page
cfg_rcw_src[6:8]:
000 ECC disabled
001 4 bits per 520 byte sector
010-100 Reserved
101 8 bits per 528 byte sector
110 24 bits per 1 KB sector
111 40 bits per 1 KB sector
1_0010_xxxx 8-bit NAND Flash, 4 KB page, 256 pages/block
cfg_rcw_src[5:8] encodings are the same as those described for 1_0001_xxxx (8-bit
NAND Flash, 4 KB page, 128 pages/block)
1_0011_xxxx 8-bit NAND Flash, 4 KB page, 512 pages/block
cfg_rcw_src[5:8] encodings are the same as those described for 1_0001_xxxx (8-bit
NAND Flash, 4 KB page, 128 pages/block)
1_0100_xxxx 8-bit NAND Flash, 8 KB page, 128 pages/block
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 251
Functional description
Table 4-9. RCW source encodings (continued)
cfg_rcw_src value RCW source
(Binary)
cfg_rcw_src[5:8] encodings are the same as those described for 1_0001_xxxx (8-bit
NAND Flash, 4 KB page, 128 pages/block)
1_0101_xxxx 8-bit NAND Flash, 8 KB page, 256 pages/block
cfg_rcw_src[5:8] encodings are the same as those described for 1_0001_xxxx (8-bit
NAND Flash, 4 KB page, 128 pages/block)
1_0110_xxxx 8-bit NAND Flash, 8 KB page, 512 pages/block
cfg_rcw_src[5:8] encodings are the same as those described for 1_0001_xxxx (8-bit
NAND Flash, 4 KB page, 128 pages/block)
1_0111_xxxx Reserved
1_1000_00xx 16-bit NAND Flash, 512-byte page, 32 pages/block
cfg_rcw_src[7:8] encodings are the same as those described for 1_0000_00xx (8-bit
NAND Flash, 512-byte page, 32 pages/block)
1_1000_01xx 16-bit NAND Flash, 2 KB page, 64 pages/block
cfg_rcw_src[7:8] encodings are the same as those described for 1_0000_00xx (8-bit
NAND Flash, 512-byte page, 32 pages/block)
1_1000_10xx 16-bit NAND Flash, 2 KB page, 128 pages/block
cfg_rcw_src[7:8] encodings are the same as those described for 1_0000_00xx (8-bit
NAND Flash, 512-byte page, 32 pages/block)
1_1000_11xx Reserved
1_1001_xxxx 16-bit NAND Flash, 4 KB page, 128 pages/block
cfg_rcw_src[5:8] encodings are the same as those described for 1_0001_xxxx (8-bit
NAND Flash, 4 KB page, 128 pages/block)
1_1010_xxxx 16-bit NAND Flash, 4 KB page, 256 pages/block
cfg_rcw_src[5:8] encodings are the same as those described for 1_0001_xxxx (8-bit
NAND Flash, 4 KB page, 128 pages/block)
1_1011_xxxx 16-bit NAND Flash, 4 KB page, 512 pages/block
cfg_rcw_src[5:8] encodings are the same as those described for 1_0001_xxxx (8-bit
NAND Flash, 4 KB page, 128 pages/block)
1_1100_xxxx 16-bit NAND Flash, 8 KB page, 128 pages/block
cfg_rcw_src[5:8] encodings are the same as those described for 1_0001_xxxx (8-bit
NAND Flash, 4 KB page, 128 pages/block)
1_1101_xxxx 16-bit NAND Flash, 8 KB page, 256 pages/block
cfg_rcw_src[5:8] encodings are the same as those described for 1_0001_xxxx (8-bit
NAND Flash, 4 KB page, 128 pages/block)
1_1110_xxxx 16-bit NAND Flash, 8 KB page, 512 pages/block
cfg_rcw_src[5:8] encodings are the same as those described for 1_0001_xxxx (8-bit
NAND Flash, 4 KB page, 128 pages/block)
1_1111_xxxx Reserved
1. Not valid as an RCW[IFC_MODE] encoding
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
252 NXP Semiconductors
Chapter 4 Reset, Clocking, and Initialization
4.4.5.2 General-purpose input
The general-purpose inputs listed in this table are available for application-specific use.
The encoded values latched on these signals during POR are accessible in
GPPORCR1[POR_CFG_VEC], as described in General-Purpose POR Configuration
Register (DCFG_CCSR_GPPORCR1).
Table 4-10. General-purpose input
Functional signals Reset configuration name Value (binary) General-purpose input
IFC_AD[0:7] cfg_gpinput[0:7] all Application-defined
Default (1111_1111)
4.4.5.3 DRAM type select
The DRAM type select input, described in this table, specifies the DDR technology and,
thus, voltage (GVDD) to be used with the DDR memory controllers.
The encoded value latched on this signal during POR is accessible in
PORSR2[DRAM_TYPE], as described in POR Status Register 2
(DCFG_CCSR_PORSR2).
Table 4-11. DRAM type select
Functional signals Reset configuration name Value (binary) DRAM type
IFC_A21 cfg_dram_type 0 DDR4 technology (1.2 V)
(Default 1) 1 DDR3L technology (1.35 V)
4.4.5.4 Single oscillator source clock select
The single oscillator source clock select input, described in this table, selects between
SYSCLK (single ended) and DIFF_SYSCLK/DIFF_SYSCLK_B (differential) inputs.
Table 4-12. Single oscillator source clock select
Functional signals Reset configuration name Value (binary) Options
IFC_WE0_B Default (1) cfg_eng_use0 0 DIFF_SYSCLK/DIFF_SYSCLK_B
(differential)
1 SYSCLK (single ended)
IFC_OE_B cfg_eng_use1 1 Reserved. Should be set to 1.
IFC_WP_B[0] cfg_eng_use2 Reserved Reserved
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 253
Functional description
4.4.5.5 IFC external transceiver enable polarity select
The IFC external transceiver enable polarity select input, described in this table, specifies
the polarity of the IFC_TE output signal to accommodate external transceivers with either
active-high or active-low enable inputs.
The encoded value latched on this signal during POR is accessible in PORSR1[IFC_TE].
See External transceiver enable (TE) for more information.
Table 4-13. IFC external transceiver enable polarity select
Functional signals Reset configuration name Value (binary) IFC external transmitter polarity
IFC_TE cfg_ifc_te 0 IFC drives logic 1 for TE assertion
Default (1) 1 IFC drives logic 0 for TE assertion
4.4.6 Reset configuration word (RCW)
The chip uses an external memory interface to import a subset of the reset configuration
information from a memory device during reset.
Such information is called reset configuration word (RCW) data.
The pre-boot loader (PBL) loads RCW data from a non-volatile memory device interface,
as specified by the RCW source configuration inputs (cfg_rcw_src[0:8]-see Reset
configuration word (RCW) source for more information). See Pre-Boot Loader for details
on the operation of the PBL. Note that this approach does not completely remove the
necessity for at least a few power-on reset (POR) configuration signals. As noted, POR
config signals are used to control RCW source information in addition to other low-level
system configuration.
The logic involved is clocked directly from SYSCLK since RCW importing takes place
before on-chip PLLs are configured.
The RCW is 512 bits long in order to contain all necessary configuration information for
the chip. RCW data is read from external memory and written to the RCW status registers
(see Reset Control Word Status Register n (DCFG_CCSR_RCWSRn)) contained in the
Device Configuration and Pin Control module , after which the device is configured as
specified in the RCW. Required format of data structure used by PBL provides details of
the data structure that is required to reside in non-volatile memory.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
254 NXP Semiconductors
Chapter 4 Reset, Clocking, and Initialization
NOTE
The chip makes all the required pins available for selected
source interface for RCW. Any other multiplexing options on
these pins will be overridden.
4.4.6.1 RCW field definitions
This table describes the function of the individual bits of the 512-bit (64-byte) RCW data
structure.
NOTE
Unless noted otherwise, any bit ranges in the table listed as
reserved must be populated with 0.
Table 4-14. RCW Field Descriptions
Bit(s) (of Field Name Description Notes/comments
0-511)
PLL configuration (bits 0-127)
0-1 SYS_PLL_CFG System PLL configuration. Options:
00 For all valid Platform PLL frequencies
01-11 Reserved
2-6 SYS_PLL_RAT System PLL multiplier/ratio This field selects the platform clock:SYSCLK ratio.
Options:
0_0000 Reserved
0_0011 3:1
0_0100 4:1
0_0101 5:1
0_0110 6:1
0_0111 7:1
0_1000 8:1
0_1001 9:1
0_1010 10:1
0_1011 11:1
0_1100 12:1
0_1101 13:1
0_1110 14:1
0_1111 15:1
1_0000 16:1
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 255
Functional description
Table 4-14. RCW Field Descriptions (continued)
Bit(s) (of Field Name Description Notes/comments
0-511)
NOTE: All ratios may not be supported due to
frequency restrictions. Refer to the chip data
sheet for the supported frequencies.
7 Reserved
8-9 MEM_PLL_CFG Memory controller complex This field configures the memory complex PLLs for
PLL configuration (applies to
the frequency of the reference clock applied.
all DDR controllers).
Options:
00 All valid DDR PLL frequencies.
01-11 Reserved
10-15 MEM_PLL_RAT Memory controller complex This field configures the DDR PLL:SYSCLK Ratio.
PLL multiplier/ratio.
Options:
00_0110-Reserved
00_0111-Reserved
00_1000 8:1
00_1001 9:1
00_1010 10:1
00_1011 11:1
00_1100 12:1
00_1101 13:1
00_1110 14:1
00_1111 15:1
01_0000 16:1
01_0001 17:1
01_0010 18:1
01_0011 19:1
01_0100 20:1
01_0101 21:1
01_0110 22:1
01_0111 23:1
01_1000 24:1
01_1001-11_1111-Reserved
NOTE: All ratios may not be supported due to
frequency restrictions. Refer to the chip data
sheet for the supported frequencies.
16-23 Reserved
24-25 CGA_PLL1_CFG Cluster group A PLL 1 Options
configuration
00 For Cluster PLL frequencies >= 1 GHz.
01-11 Reserved
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
256 NXP Semiconductors
Chapter 4 Reset, Clocking, and Initialization
Table 4-14. RCW Field Descriptions (continued)
Bit(s) (of Field Name Description Notes/comments
0-511)
26-31 CGA_PLL1_RAT Cluster group A PLL 1 Options:
multiplier/ratio
00_0101 through 10_1000 5:1 through 40:1 Async
All other encodings are reserved.
For 1 GHz frequency:
The value of this field should be the required
multiplication ratio and C1_PLL_SEL should be set to
4’b0000 (CGA_PLL1). For example in order to achieve
1000 MHz core clock frequency with reference clock
frequency of 100 MHz, the ratio should be 10(0xA) for
locking the CGA PLL1 at 1000 MHz and
C1_PLL_SEL=4’b0000 to achieve 1000 MHz core
clock frequency.
For less than 1 GHz operation:
The value of this field should be twice the required
core clock frequency and C1_PLL_SEL should be set
to 4’b001 (CGA_PLL1/2). For example inorder to
achieve 800 MHz core clock frequency with reference
clock frequency of 100 MHz, the ratio should be
16(0x10) for locking the CGA PLL1 at 1600 MHz and
C1_PLL_SEL=4’b0001 to achieve 800 MHz core clock
frequency.
NOTE: Not all ratios are supported due to frequency
restrictions. Refer to the chip data sheet for
the supported frequencies.
32-33 CGA_PLL2_CFG Cluster group A PLL 2 Options:
configuration
00 00 For Cluster PLL frequencies >= 1 GHz.
01-11 Reserved.
34-39 CGA_PLL2_RAT Cluster group A PLL 2 Options:
multiplier/ratio
00_0101 5:1 Async
00_0110 6:1 Async
00_0111 7:1 Async
00_1000 8:1 Async
00_1001 9:1 Async
00_1010 10:1 Async
00_1011 11:1 Async
00_1100 12:1 Async
00_1101 13:1 Async
00_1110 14:1 Async
.........
10_0111 39:1 Async
10_1000 40:1 Async
All other encodings are reserved.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 257
Functional description
Table 4-14. RCW Field Descriptions (continued)
Bit(s) (of Field Name Description Notes/comments
0-511)
NOTE: All ratios may not be supported due to
frequency restrictions. Refer to the chip data
sheet for the supported frequencies.
40-95 Reserved
96-99 C1_PLL_SEL Cluster 1 PLL select. Options:
0000 CGA_PLL1 /1
0001 CGA_PLL1 /2
0100 CGA_PLL2 /1
0101 CGA_PLL2 /2
All other encodings are reserved.
NOTE: All the four cores are in cluster 1 and run at
the same frequency.
100-127 Reserved
SerDes PLL and Protocol configuration (bits 128-183)
128-143 SRDS_PRTCL_S1 SerDes protocol select SerDes See SerDes protocols for a complete list of the options
1 and the definitions of this encoded field.
144-157 Reserved Reserved
158 FM1_MAC_RAT FM1to MAC1 ratio Reserved. Must be set as 0’b1.
159 Reserved Reserved
160-161 SRDS_PLL_REF_CLK SerDes PLL reference clock This field selects the PLL reference clock frequency
_SEL_S1 select - SerDes 1. for SerDes1
Bit 160: SerDes 1, PLL1
Bit 161: SerDes 1, PLL2
Selection for protocols PCI express operating at 1.25
or 2.5 or 5 GT/s:
0 100 MHz
1 125 MHz
Selection for protocols operating at 3 or 6 Gbps
0 100 MHz
1 125 MHz
Selection for protocols operating at 3.125 and 10
Gbps:
0 125 MHz
1 156.25 MHz (XFI)
NOTE: The higher or lower reference clock frequency
depends on the protocol and its operating
frequency. See the "Valid reference clocks
and PLL configurations for SerDes protocols"
section in the SerDes Module chapter for
more details.
162-163 Reserved Set to 0’b0.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
258 NXP Semiconductors
Chapter 4 Reset, Clocking, and Initialization
Table 4-14. RCW Field Descriptions (continued)
Bit(s) (of Field Name Description Notes/comments
0-511)
164-165 Reserved
166 HDLC1_MODE This field selects the HDLC1_MODE option, TXD open-drain mode:
HDLC1/TDM pin multiplexing
0 - TXD configured in normal functional mode
related operating modes
including TXD open-drain 1 - TXD configured in open-drain mode for either
mode. HDLC or TDM.
Note: TXD open-drain mode is not supported at the
same time as the TDM Switch Receive Transmit
Mode.
167 HDLC2_MODE This field selects the HDLC2_MODE option, TXD open-drain mode:
HDLC2/TDM pin muxing
0 - TXD configured in normal functional mode
related operating modes
including TXD open-drain 1 - TXD configured in open-drain mode for either
mode. HDLC or TDM.
Note: TXD open-drain mode is not supported at the
same time as the TDM Switch Receive Transmit
Mode.
168-169 SRDS_PLL_PD_S1 SerDes PLL power down This field is used to power down the SerDes 1 PLLs.
SerDes 1.
Bit 168 corresponds to SerDes 1, PLL1 and bit 169
corresponds to SerDes 1, PLL2.
Option :
0 PLL is not powered down.
1 PLL is powered down.
This field is ignored if the respective SRDS_PRTCL_*
field does not use a given SerDes PLL. For more
information, refer Disabling unused SerDes modules.
170-175 Reserved
176-177 SRDS_DIV_PEX SerDes frequency divider- PCI This field controls the frequncy of PCI-Express
express protocols on SerDes lanes that are operating 5/2.5G.
Lanes that supporting other frequencies and protocols
are unaffected by this field.
Options:
0x Can train up to a max rate of 5G
10 Can train up to a max rate of 2.5G
11 Reserved
178-183 Reserved
MISC PLL-RELATED (BITS 184-191)
184-185 Reserved, Set to 0'b00.
186-187 DDR_REFCLK_SEL DDR reference clock selection Options:
00 The DDRCLK pin provides the reference clock to
the DDR PLL
01 DIFF_SYSCLK/DIFF_SYSCLK_B provides the
reference clock to the DDR PLL
10 Reserved
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 259
Functional description
Table 4-14. RCW Field Descriptions (continued)
Bit(s) (of Field Name Description Notes/comments
0-511)
11 Reserved
188 SerDes_REFCLK_SEL SerDes PLL2 reference clock Selects the reference clock for SerDes PLL2 (used for
selection single oscillator reference clock selection for SerDes)
Set to 0’b0.
189 Reserved
190-191 DDR_FDBK_MULT DDR PLL feedback path Set this value to 10.
selection and multiplication
enabler
Boot configuration (bits 192-223)
192-195 PBI_SRC Pre-boot initialization source. The following restriction apply:
The pre-Boot loader fetches
• RCW and pre-boot initialization data must be
address/data pairs from the
loaded from the same non-volatile memory
selected interface for the
device
purpose of pre-boot
Initialization of CCSR and/or The hard coded RCW source options are not
local memory space. considered their own memory interface for this
purpose.
Options:
010x QSPI
0110 SD/MMC
1110 IFC (The RCW field IFC_MODE configures the
IFC, provided the IFC has not already been configured
by the cfg_rcw_src configuration input signals, which
have precedence.)
All other encodings are reserved.
196-200 Reserved
201 BOOT_HO Boot hold off Options:
0 All cores except core 0 in hold off
1 All cores in hold off
202 SB_EN Secure boot enable NOTE: Note that secure boot is enabled if either this
RCW bit is set or the Intent to Secure fuse
value is set. See chapter "Secure Boot and
Trust Architecture" for more information.
Options:
0 Secure boot is not enabled
1 Secure boot is enabled
203-211 IFC_MODE Integrated Flash controller When PBI_SRC is configured for IFC, this field selects
mode the IFC mode for pre-boot initialization. Note that
cfg_rcw_src have precedence over configuring the
IFC, see the definition of the PBI_SRC field.
Valid IFC_MODE encodings are a subset of the
cfg_rcw_src encodings. See Reset configuration word
(RCW) source for the valid encodings for this field.
212-213 Reserved Set to 00
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
260 NXP Semiconductors
Chapter 4 Reset, Clocking, and Initialization
Table 4-14. RCW Field Descriptions (continued)
Bit(s) (of Field Name Description Notes/comments
0-511)
214-215 Reserved Set to 00
216-223 Reserved
Clocking configuration (bits 224-255)
224-226 HWA_CGA_M1_CLK_ Hardware accelerator block This controls the async clock frequency provided to
SEL cluster group A, mux 1 clock FMAN module
select.
Options:
000 - Reserved.
001 Reserved
010 Asynchronous mode - Cluster group A PLL 1 /2
011 Asynchronous mode - Cluster group A PLL 1 /3
100 Reserved
101 Reserved
110 Async mode -- Cluster Group A PLL 2 /2 is clock
111 Async mode -- Cluster Group A PLL 2 /3 is clock
227-229 Reserved
230-231 DRAM_LAT DDR latency Options:
00 6-6-6 or 7-7-7 DRAMs
01 8-8-8, 9-9-9, 10-10-10, 11-11-11, or higher latency
DRAMs
10 Reserved
11 5-5-5 DRAMs
NOTE: If DDR latency is not known at the time the
RCW is loaded, it is acceptable to
conservatively configure this field as 01. This
field is used for optimizing the DDR interface.
No functional issues result if this field does
not match the latency of the actual DRAM's
used.
232 DDR_RATE DDR data rate Reserved. Must be 0.
233 Reserved
234 DDR_RSV0 Reserved Set to 0.
235 Reserved
236-241 Reserved Reserved. Must be set to 0.
242 SYS_PLL_SPD System PLL speed select Reserved. Must be set to 1.
243 MEM_PLL_SPD Memory controller complex Set to 0.
PLL Speed select
244 CGA_PLL1_SPD Cluster group A PLL1 speed Set to 0.
select
245 CGA_PLL2_SPD Cluster Group A PLL2 speed Options:
select
0 High speed operation (from 1000.2 MHz to 1400
MHz
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 261
Functional description
Table 4-14. RCW Field Descriptions (continued)
Bit(s) (of Field Name Description Notes/comments
0-511)
1 Low speed operation (from 800 MHz to 1000.1 MHz)
246-255 Reserved
Memory and high speed I/O configuration (bits 256-287)
256-263 Reserved
264-266 HOST_AGT_PEX Host/agent PEX. Configures Set to 000 (Host mode). EP mode is not supported.
Host/Agent mode for all PCI
Express Interfaces.
267-268 Reserved Set to 0'b0
269-287 Reserved
General purpose information (bits 288-319)
288-295 GP_INFO General purpose information. This field has no effect on functional logic; it may be
used by software.
296-298 Reserved
299-319 GP_INFO General purpose information. This field has no effect on functional logic; it may be
used by software.
Engineering use configuration (bits 320-351)
320-351 Reserved
Group A pin configuration (bits 352-383)
352-353 Reserved
354-356 UART_EXT This field configures the Options:
functionality of UART pins
000 See UART_BASE field definition
together with UART_BASE
field. 001 {UART1_SOUT/GPIO1_15, LPUART1_SOUT,
UART1_SIN/GPIO1_17, LPUART1_SIN,
LPUART2_SOUT, LPUART1_RTS_B, LPUART2_SIN,
LPUART1_CTS_B}
010 {UART1_SOUT/GPIO1_15, LPUART1_SOUT,
UART1_SIN/GPIO1_17, LPUART1_SIN,
LPUART2_SOUT, LPUART4_SOUT, LPUART2_SIN,
LPUART4_SIN}
011 {UART1_SOUT/GPIO1_15, FTM4_CH0,
UART1_SIN/GPIO1_17, FTM4_CH1, FTM4_CH2,
FTM4_CH3, FTM4_CH4, FTM4_CH5}
Settings not shown are reserved
For more details, refer UART, GPIO, FTM, and
LPUART signal multiplexing
357-359 IRQ_EXT This field configures the Options:
functionality of IRQ[3:5] pins
000 See IRQ_BASE field definition
together with IRQ_BASE field.
001 {TDMB_TSYNC, TDMA_TXD/TDMA_RXD,
TDMA_RSYNC, TDMA_TXD/TDMA_RXD_EXC,
TDMA_TSYNC, TDMB_TXD/TDMB_RXD,
TDMB_RSYNC, TDMB_TXD/TDMB_RXD_EXC,
GPIO1_31 }
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
262 NXP Semiconductors
Chapter 4 Reset, Clocking, and Initialization
Table 4-14. RCW Field Descriptions (continued)
Bit(s) (of Field Name Description Notes/comments
0-511)
>010 {UC3_RTSB_TXEN, UC1_RXD7,
UC1_CTSB_RXDV, UC1_TXD7, UC1_RTSB_TXEN,
UC3_RXD7, UC3_CTSB_RXDV, UC3_TXD7,
GPIO1_31}
011 { FTM3_CH7, FTM3_CH0, FTM3_CH1,
FTM3_CH2, FTM3_CH3, FTM3_CH4, FTM3_CH5,
FTM3_CH6, GPIO1_31}
Settings not shown are reserved.
For more details, refer External IRQ, QE, and GPIO1
signal multiplexing
360-362 SPI_EXT This field configures Options:
functionality of SPI pins
000 See SPI_BASE field definition.
together with SPI_BASE field.
001 {SDHC_CLK_SYNC_OUT,
SDHC_CLK_SYNC_IN, Reserved, SDHC_VS,
SPI_CS_B[1]/GPIO2_1/SDHC_DAT5/
SDHC_CMD_DIR, SPI_CS_B[2]/GPIO2_2/
SDHC_DAT6/SDHC_DAT0_DIR, SPI_CS_B[3]/
GPIO2_3/SDHC_DAT7/SDHC_DAT123_DIR}
010 {SPI_MOSI, SPI_MIS0, Reserved, SPI_CS_B[0]/
GPIO2_0/SDHC_DAT4, SPI_CS_B[1]/GPIO2_1/
SDHC_DAT5/SDHC_CMD_DIR, SPI_CS_B[2]/
GPIO2_2/SDHC_DAT6/SDHC_DAT0_DIR,
SPI_CS_B[3]/GPIO2_3/SDHC_DAT7/
SDHC_DAT123_DIR}
Settings not shown are reserved.
For more details, refer SPI, eSDHC, USB and GPIO2
signal multiplexing
363-365 SDHC_EXT This field configures the Options:
functionality of the SDHC pins
000 See SDHC_BASE field definition
together with SDHC_BASE
field 001 { LPUART3_SOUT, LPUART3_SIN,
LPUART2_RTS_B, LPUART2_CTS_B,
LPUART3_RTS_B, LPUART3_CTS_B }
010 { LPUART3_SOUT, LPUART3_SIN,
LPUART5_SOUT, LPUART5_SIN, LPUART6_SOUT,
LPUART6_SIN }
011 { FTM4_CH6, FTM4_CH7, FTM4_FAULT,
FTM4_EXTCLK, FTM4_QD_PHA, FTM4_QD_PHB}
Settings not shown are reserved.
For more details, refer eSDHC, GPIO2, and GPIO4
signal multiplexing
366-368 UART_BASE This field configures Options:
functionality of UART pins.
000 {GPIO1_15, GPIO1_17, GPIO1_19, GPIO1_21,
GPIO1_16, GPIO1_18, GPIO1_20, GPIO1_22}
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 263
Functional description
Table 4-14. RCW Field Descriptions (continued)
Bit(s) (of Field Name Description Notes/comments
0-511)
011 {UART1_SOUT, UART1_SIN, GPIO1[19],
GPIO1[21], GPIO1[16], GPIO1[18]. GPIO1_20],
GPIO1_22] }
100 {UART1_SOUT, UART1_SIN, UART1_RTS_B,
UART1_CTS_B, GPIO1_16], GPIO1_18, GPIO1_20,
GPIO1_22}
101 {UART1_SOUT, UART1_SIN, GPIO1_19,
GPIO1_[21], UART2_SOUT, UART2_SIN,
GPIO1_20], GPIO1_22}
110 {UART1_SOUT, UART1_SIN, UART1_RTS_B,
UART1_CTS_B, UART2_SOUT, UART2_SIN,
UART2_RTS_B, UART2_CTS_B}
111 {UART1_SOUT, UART1_SIN, UART3_SOUT,
UART3_SIN, UART2_SOUT, UART2_SIN,
UART4_SOUT, UART4_SIN}
NOTE: Note that UART_EXT field must be set to all
0's for UART_BASE to take effect.
369 ASLEEP This field configures Options:
functionality of ASLEEP pin.
0 ASLEEP
1 GPIO1_13
370 RTC This field configures Options:
functionality of RTC pin.
0 RTC
1 GPIO1_14
371 SDHC_BASE This field configures Options:
functionality of SDHC pins:
0 {SDHC_CMD, SDHC_DAT[0:3], SDHC_CLK}
{{SDHC_CMD,
SDHC_DAT[0:3], SDHC_CLK} 1 GPIO2[4:9]
NOTE: If cfg_rcw_src selects SD/MMC as the RCW
source, the SDHC pins are driven with SDHC
functionality regardless of the setting of this
field.
372 IRQ_OUT This field configures Reserved. Set to 1.
functionality of the IRQ_OUT
pin.
373-381 IRQ_BASE This field configures Options for each bit:
functionality of IRQ[3:11] pins.
0 IRQ
The corresponding GPIOs for
these pins are GPIO1[23:31]. 1 GPIO
382-383 SPI_BASE This field configures Options:
functionality of the
00 SPI_CS_B[0:3], SPI_MOSI, SPI_MISO, SPI_CLK
SPI_CS_B[0:3] pins.
01 SDHC_DAT[4:7] for 8-bit MMC card support
10 GPIO2[0:3]
11 {Reserved, SDHC_CMD_DIR, SDHC_DAT0_DIR,
SDHC_DAT123_DIR}
Group B pin configuration (bits 384-415)
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
264 NXP Semiconductors
Chapter 4 Reset, Clocking, and Initialization
Table 4-14. RCW Field Descriptions (continued)
Bit(s) (of Field Name Description Notes/comments
0-511)
384-386 IFC_GRP_A_EXT This field configures the Options:
functionality of Group A of the
000 See IFC_GRP_A_BASE field definition
IFC pins together with
IFC_GRP_A_BASE field. 001 { QSPI_A_DATA[3]}
010 { FTM5_CH0, FTM5_CH1, FTM5_EXTCLK }
100 { IFC_CS_B[4], IFC_CS_B[5], IFC_CS_B[6] }
Settings not shown are reserved.
NOTE: • If IFC_CS_B[5] is used, then
IFC_RB_B[3] cannot be used and vice-
versa
• If QuadSPI is selected for cfg_rcw_src
then this bit must be set to 001.
387-392 Reserved
393-395 IFC_GRP_D_EXT This fiels configures the Options:
functionality of Group D of the
000 See IFC_GRP_D_BASE field definition
IFC pins, together with
IFC_GRP_D_BASE field. 001 {QSPI_B_DATA[0], QSPI_B_DATA[1],
QSPI_B_DATA[2]}
010 { FTM6_CH0, FTM6_CH1, FTM6_EXTCLK }
Settings not shown are reserved
396-398 IFC_GRP_E1_EXT This field configures Options:
functionality of Group E1 of
000 See IFC_GRP_E1_BASE field definition
the IFC pins, together with
IFC_GRP_E1_BASE field. 001 { IFC_CS_B[1]/GPIO2_10, IFC_CS_B[2]/
GPIO2_11, QSPI_B_DATA[3] }
010 { FTM7_CH0, FTM7_CH1, FTM7_EXTCLK }
Settings not shown are reserved.
Note: This field has additional effect, as also used as
IFC_GRP_E3_EXT. The primary functionality of GRP_
E3 is selected only when this field is 3’b000.
399-401 IFC_GRP_F_EXT This field configures Options:
functionality of Group F of the
000 {IFC_A[16:24]/IFC_WP_B[1:3]}
IFC pins.
001 {QSPI_A_CS0, QSPI_A_CS1, QSPI_A_SCK,
QSPI_B_CS0, QSPI_B_CS1, QSPI_B_SCK,
QSPI_A_DATA[0], QSPI_A_DATA[1],
QSPI_A_DATA[2]}
Settings not shown are reserved.
NOTE: If QuadSPI is selected for cfg_rcw_src then
this bit must be set to 001.
402-404 IFC_GRP_G_EXT This field configures Settings not shown are reserved.
functionality of Group G of the
IFC pins.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 265
Functional description
Table 4-14. RCW Field Descriptions (continued)
Bit(s) (of Field Name Description Notes/comments
0-511)
405 IFC_GRP_E1_BASE Together with Options:
IFC_GRP_E1_EXT field, this
0 IFC_CS_B[1:3]
field configures functionality of
Group E1 of the IFC pins. 1 {GPIO2[10:12]}
406 Reserved
407 IFC_GRP_D_BASE Together with Options:
IFC_GRP_D_EXT field, This
0 {IFC_PAR[0:1]/IFC_PERR_B}
field configures functionality of
Group D of the IFC pins. 1 {GPIO2[13:15]}
408 Reserved
409-411 Reserved
412-413 IFC_GRP_A_BASE This field configures Options:
functionality of Group A of the
00 {IFC_A[25:27]}
IFC pins.
01 {GPIO2[25:27]}
10 {IFC_RB_B[2:3], Reserved}
Whenever IFC is selected for less than 28 bits (25-bits
or 22-bits) using cfg_rcw_src, this field should be set
such that IFC_AD is not selected. When IFC is
selected as 25-b or 22-b
addressing,RCW[IFC_GRP_A_BASE] should not be
set to 00.
414 Reserved
415 IFC_A_22_24 This field configures Options:
functionality of the IFC pins
0 {IFC_A[22:24]}
IFC_A[22:24] for 16b data bus
pinouts which pinout 25b or 1 {IFC_WP_B[1:3]}
28b of addressability.
Whenever IFC is selected for 22-b functionality using
cfg_rcw_src, this field should be chosen such that
IFC_AD is not selected. And, When IFC is selected as
22-b addressing, RCW[IFC_A_22_24] should not be
set to 0.
SoC-Specific configuration (bits 416-447)
416-418 EC1 Selects the functionality Options:
assigned to the EC1 pins.
000 RGMII1
001 GPIO3
010 Reserved
011 Reserved
100 Reserved
101 FTM1
110 Reserved
111 Reserved
419-421 EC2 Selects the functionality Options:
assigned to the EC2 pins.
000 RGMII2
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
266 NXP Semiconductors
Chapter 4 Reset, Clocking, and Initialization
Table 4-14. RCW Field Descriptions (continued)
Bit(s) (of Field Name Description Notes/comments
0-511)
001 GPIO3, GPIO3[19:23]
010 IEEE 1588
011 Reserved
100 Reserved
101 FTM2
110 Reserved
111 Reserved
When configured for IEEE1588, the EC2 pins that are
not available for IEEE1588 are configured for GPIO.
422-424 Reserved
425 EM1 Configures functionality of the Options:
EM1 MDC_MDIO pins.
(MDC_MDIO) 0 MDC/MDIO (EM1)
1 GPIO_3
426 EM2 Configures functionality of the Options:
EM2 MDC_MDIO pins.
(MDC_MDIO) 0 MDC/MDIO (EM2)
1 GPIO_4
427 EMI2_DMODE This field selects the EMI 2, MDIO Open-Drain mode:
Ethernet management
Recommended setting for this bit is 0'b1.
interface MDIO pin
multiplexing related operating Options:
modes.
0 MDIO configured in normal functional mode
1 MDIO configured in Open-Drain mode.
428 EMI2_CMODE This field selects the EMI 2- MDC Open-Drain mode:
Ethernet management
Recommended setting for this bit is 0'b1.
interface MDC pin multiplexing
related operating modes. Options:
0 MDC configured in normal functional mode
1 MDC configured in Open-Drain mode.
429 USB_DRVVBUS This field configures the Options:
functionality of the
0 USB_DRVVBUS
USB_DRVVBUS pin.
1 GPIO4_29
NOTE: Refer USB DRVVBUS Control Register
(SCFG_USBDRVVBUS_SELCR) for
USB_DRV_VBUS to USB Controller
mapping.
430 USB_PWRFAULT This field configures the Options:
functionality of the
0 USB_PWRFAULT
USB_PWRFAULT signal.
1 GPIO4_30
NOTE: Refer USB PWRFAULTControl Register
(SCFG_USBPWRFAULT_SELCR) for
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 267
Functional description
Table 4-14. RCW Field Descriptions (continued)
Bit(s) (of Field Name Description Notes/comments
0-511)
USB_PWRFAULT to USB Controller
mapping.
431-432 Reserved
433-434 TVDD_VSEL Configures voltage of the Options:
TVDD IO domain.
00 1.2 V or 1.8 V
01 2.5 V
10 Reserved
11 Auto-voltage selection enabled. This is used only
for hard-coded RCW values.
435-436 DVDD_VSEL Configures voltage of the Options:
DVDD IO domain.
00 1.8V
01 Reserved
10 3.3V
11 Auto-voltage selection enabled. This is used only
for hard-coded RCW values.
437 QE_CLK_OVRRIDE Configure the selection of QE Options:
clocks on IIC2_SCL.
0 Select as per IIC2_EXT(RCW[445-447]). Options for
IIC2_EXT:RCW[445-447] available are:
101 - CLK9, CLK10
110 - BRGO2,BRGO3
1 Toggle the I2C_SCL functionality. Options for
IIC2_EXT:RCW[445-447] available are:
101 - BRGO2, CLK10
110 - CLK9,BRGO3
NOTE: This overrides only for CLK9 Vs BRGO2 on
IIC2_SCL pin. If QE functionality is not
selected then this pin should be set to 0.
438 EMI1_DMODE This field selects the EMI 1, MDIO Open-Drain mode:
Ethernet management
Recommended setting for this bit is 0'b1.
interface MDIO pin
multiplexing related operating Options:
modes.
0 MDIO configured in normal functional mode
1 MDIO configured in Open-Drain mode.
439-440 EVDD_VSEL Configures voltage of the Options:
EVDD IO domain.
00 1.8V
01 Reserved
10 3.3V
11 Auto-voltage selection enabled. This is used only
for hard-coded RCW values or while the voltage
transition is happening from 3.3 V to 1.8 V.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
268 NXP Semiconductors
Chapter 4 Reset, Clocking, and Initialization
Table 4-14. RCW Field Descriptions (continued)
Bit(s) (of Field Name Description Notes/comments
0-511)
441-443 IIC2_BASE This field configures Set to 0b000.
functionality of the IIC pins.
444 EMI1_CMODE This field selects the EMI 1- MDC Open-Drain mode:
Ethernet management
Recommended setting for this bit is 0'b1.
interface MDC pin multiplexing
related operating modes. Options:
0 MDC configured in normal functional mode
1 MDC configured in Open-Drain mode.
445-447 IIC2_EXT Selects between IIC2 base Options:
functionality and extension
000 IIC2_SCL, IIC2_SDA
001 SDHC_CD_B, SDHC_WP
010 GPIO4_2, GPIO4_3
011 FTM3_QD_PHA, FTM3_QD_PHB
100 QE_SI1_STROBE[0], QE_SI1_STROBE[1]
101 CLK9, CLK10
110 BRGO2, BRGO3
Settings not shown are reserved.
448-471 Reserved
472-481 SYSCLK_FREQ SYSCLK frequency This field is used for proper hardware configuration of
the Arm generic timer and by software to determine
the frequency of SYSCLK. The value in this field is
multiplied by 166.667 KHz. It is used to provide
information to determine the frequency of operation of
the Arm Generic Timer. The allowable range depends
on the range of SYSCLK frequencies supported.
The frequency for Arm generic timer is SYSCLK/4.
Example values(in decimal, not hexadecimal):
10’d384 - 64 MHz
10’d400 - 66.667 MHz
10’d500 - 83.3 MHz
10’d600 - 100 MHz
482-493 Reserved
494-508 Reserved Set to 0’b0.
509-511 HWA_CGA_M2_CLK_ Hardware accelerator block This field allows for a platform accelerator block’s (or
SEL cluster group A mux 2 clock multiple blocks’) frequency to be maximized (using
select. async clock) by leveraging cluster group A mux 2.
This controls the async clock frequency provided to
eSDHC and QuadSPI.
Options:
001 Async mode, Cluster Group A PLL 2 /1 is clock
011 Async mode, Cluster Group A PLL 2 /3 is clock
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 269
Functional description
Table 4-14. RCW Field Descriptions
Bit(s) (of Field Name Description Notes/comments
0-511)
Setting not shown are reserved.
When eSDHC used in MMC4.5 in SDR mode:
• CGA2PLL should be set for 1200 MHz
• HWA_CGA_M2_CLK_SEL should be set for
3’b001
• /6 occurs local to the eSDHC
• Net result is a 200 MHz clock
When eSDHC used in MMC4.2 or MMC4.5 DDR
mode:
• Settings above must be chosen to generate a
clock that is 300 MHz. This can be
accomplished using 900 MHz / 3
• /6 occurs local to the eSDHC
• Net result is a 50 MHz clock
4.4.6.2 Hard-coded RCW options
If any of the hard-coded RCW options are used, the PBL RCW loading process is
bypassed and the device is automatically configured according to the specific RCW field
encodings that are pre-assigned for the given hard-coded RCW option. The hard-coded
RCW options can be useful if the board has no valid RCW present or if the customer is
unable to load in the RCW from a non-volatile memory. Using a hard-coded RCW option
allows the part to be initialized so that the desired RCW can be programmed or restored.
NOTE
Hard-coded RCW option is not recommended as a feature to be
used for functional bring-up (DDR and SerDes functionality). It
can be used to bring-up the board with blank flash where flash
needs to be programmed for RCW information through JTAG
interface.
The hard-coded RCW option should be selected based on the system SYSCLK and
DDRCLK frequency combination.
NOTE
If a hard-coded RCW option is used, the user should not enable
the core and the DDR controllers. The user may enable the core
and DDR controllers after a valid RCW is restored.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
270 NXP Semiconductors
Chapter 4 Reset, Clocking, and Initialization
Table 4-15. Hard-Coded RCW Options
cfg_rcw_src[0:8] Encoding Comments
0_1001_1010 (0x9A) SYSCLK DDRCLK
66 MHz 100 MHz
0_1001_1110 (0x9E), 0_1001_1111 (0x9F) SYSCLK DDRCLK
100 MHz 100 MHz
4.4.6.3 RCW settings for hard-coded Options
Table 4-16. RCW Settings for hard-coded RCW options
RCW Field cfg_rcw_src[0:8] = cfg_rcw_src[0:8] = cfg_rcw_src[0:8] =
0_1001_1010 (0x9A) 0_1001_1110 0_1001_1111
(0x9E) (0x9F)
PLL CONFIGURATION (BITS 0-127)
SYS_PLL_CFG 0's
SYS_PLL_RAT 4:1 3:1
(must be an even ratio)
MEM_PLL_CFG 0's
MEM_PLL_RAT 13:1
CGA_PLL1_CFG 0's
CGA_PLL1_RAT 18:1 12:1
CGA_PLL2_CFG 0's
CGA_PLL2_RAT 15:1 10:1
C1_PLL_SEL CGA_PLL1 / 1
SerDes PLL AND PROTOCOL CONFIGURATION (BITS 128-183)
SRDS_PRTCL_S1 SerDes 1 set to a value of 0x0000 (All lanes used)
FM1_MAC_RAT 1'b1
SRDS_PLL_REF_CLK_SEL_S1 0'b00 (SerDes 1 Refclk: PLL1 = 100 MHz, PLL2 = 100 MHz)
HDLC1_MODE 2'b00
HDLC2_MODE 2'b00
SRDS_PLL_PD_S1 PLL1 = not powered down, PLL2 = powered down
SRDS_DIV_PEX 2'b01 (5G)
MISC PLL-RELATED (BITS 184-191)
DDR_REFCLK_SEL 2'b00 2'b01
SerDes_REFCLK_SEL 1'b1
DDR_FDBK_MULT 2'b10
BOOT CONFIGURATION (BITS 192-223)
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 271
Functional description
Table 4-16. RCW Settings for hard-coded RCW options (continued)
RCW Field cfg_rcw_src[0:8] = cfg_rcw_src[0:8] = cfg_rcw_src[0:8] =
0_1001_1010 (0x9A) 0_1001_1110 0_1001_1111
(0x9E) (0x9F)
PBI_SRC Disabled
BOOT_HO All cores other than core 0
SB_EN Secure boot disabled
IFC_MODE 0-don't care
CLOCKING CONFIGURATION (BITS 224-255)
HWA_CGA_M1_CLK_SEL Cluster Group A PLL 2 /2
DRAM_LAT Set to 2’b01.
DDR_RATE Divide by 2
DP_DIV 2'b00
OCN_DIV 2'b00
SYS_PLL_SPD 1'b1 1'b0
MEM_PLL_SPD 1'b0
CGA_PLL1_SPD 1'b0
CGA_PLL2_SPD 1'b0
MEMORY AND HIGH SPEED I/O CONFIGURATION (BITS 256-287)
RIO_DEVICE_ID 0'b0
RIO_SYS_SIZE 0'b0
HOST_AGT_PEX All in Agent Mode
GENERAL PURPOSE INFORMATION (BITS 288-319)
GP_INFO 0x0
ENGINEERING USE CONFIGURATION (BITS 320-351)
ENG_USE All Zeros
CHASSIS GROUP A PIN CONFIGURATION (BITS 352-383)
UART_EXT All Zeros (configured by UART_BASE)
IRQ_EXT All Zeros (configured by IRQ_BASE)
SPI_EXT All Zeros (configured by SPI_BASE)
UART_BASE1 All Zeros (all GPIOs)
ASLEEP Zero (Asleep)
RTC Zero (RTC)
SDHC_BASE Zero (SD/MMC)
IRQ_OUT All Zeros (EVT_B[9])
IRQ_BASE All Zeros (All IRQs)
SPI_BASE All Zeros (All Chip Selects of SPI)
CHASSIS GROUP B PIN CONFIGURATION (BITS 384-415)
IFC_GRP_A_EXT All Zeros (configured by IFC_GRP_A_BASE)
IFC_GRP_B_EXT All Zeros (configured by IFC_GRP_B_BASE)
IFC_GRP_C_EXT All Zeros (configured by IFC_GRP_C_BASE)
IFC_GRP_D_EXT All Zeros (configured by IFC_GRP_D_BASE)
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
272 NXP Semiconductors
Chapter 4 Reset, Clocking, and Initialization
Table 4-16. RCW Settings for hard-coded RCW options (continued)
RCW Field cfg_rcw_src[0:8] = cfg_rcw_src[0:8] = cfg_rcw_src[0:8] =
0_1001_1010 (0x9A) 0_1001_1110 0_1001_1111
(0x9E) (0x9F)
IFC_GRP_E1_EXT All Zeros (configured by IFC_GRP_E1_BASE)
IFC_GRP_E2_EXT Zero (configured by IFC_GRP_E2_BASE)
IFC_GRP_F_EXT All Zeros (configured by IFC_GRP_F_BASE)
IFC_GRP_G_EXT All Zeros (configured by IFC_GRP_G_BASE)
IFC_GRP_E1_BASE Zero (IFC Chip Selects 1-3)
IFC_GRP_E2_BASE Zero (IFC Chip Selects 4-7)
IFC_GRP_D_BASE Zero (IFC Parity)
IFC_GRP_C_BASE Zero (IFC Address bits 26-31)
IFC_GRP_B_BASE All Zeros (IFC Address/Data bits 28-31)
IFC_GRP_A_BASE All Zeros (IFC Address/Data bits 25-27)
SoC SPECIFIC CONFIGURATION (BITS 416-447)
EC1 3'b001 (GPIO)
EC2 3'b001 (GPIO)
EM1 (MDC/MDIO) 1'b1 (GPIO)
EM2 (MDC/MDIO) 1'b1 (GPIO)
EMI2_DMODE 1'b0 (Normal functional mode)
EMI2_CMODE 1'b0 (Normal functional mode)
USB_DRVVBUS 1'b1 (GPIO)
USB_PWRFAULT 1'b1 (GPIO)
TVDD_VSEL 2'b11 (Auto)
DVDD_VSEL 2'b11 (Auto)
QE_CLK_OVRRIDE 1'b0
EMI1_DMODE 1'b0 (Normal functional mode)
EVDD_VSEL 2'b11 (Auto)
IIC2_BASE 3'b000
EMI1_CMODE 1'b0 (Normal functional mode)
IIC2_EXT 3'b010 (GPIO)
PLL AND CLOCKING CONFIGURATION EXPANSION (BITS 448-511)
SYSCLK_FREQ 10'h190 10'h258
HWA_CGA_M2_CLK_SEL 3'b001 (Cluster Group A PLL 2 divide by 1)
1. By default UART is not configured, so boot code need to override the RCW for UART prompt in hard-coded RCW mode.
4.4.7 Clocking
The following sections describe the clocking within the chip.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 273
Functional description
4.4.7.1 Single source clocking
The chip supports the single source clocking options with single, two, and more reference
oscillators.
4.4.7.1.1 Single oscillator source reference clock mode
In this mode, single on-board oscillator would provide the single reference clock (100
MHz) to the following PLLs:
• Platform PLL
• Core PLLs
• USB PLL
• DDR PLL
And, require two additional reference clocks for:
• SerDes PLLs
NOTE
The chip will not complete the reset sequence if SerDes
reference clocks are not provided and the PLLs are enabled in
the RCW (RCW SRDS_PLL_PD_S1).
The reset configuration field identifies whether the SYSCLK (single-ended) or
DIFF_SYSCLK (differential) is selected as the clock input to the chip.
The RCW[DDR_REFCLK_SEL] bit is used to select clock input (DIFF_SYSCLK or
DDRCLK) to the DDR PLL.
The following figure shows the system view of single oscillator source clocking. In this
figure, the on-board oscillator generates three differential clock outputs. The first
differential output is used to provide the clock to system clock associated PLLs and DDR
PLL. However, the second and third differential outputs are used to provide clocks to
SerDes PLLs.
A multiplexer between system clock and DIFF_SYSCLK/DIFF_SYSCLK_B is used to
provide the USB PHY reference clock to the USB PLL. And, multiplexer between
DIFF_SYSCLK/DIFF_SYSCLK_B inputs and DDRCLK is used to provide reference
clock to the DDR PLL.
The duty cycle reshaper reshapes the 125 MHz ECn_GTX_CLK125 which is fed into
frame manager for transmission as ECn_GTX_CLK.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
274 NXP Semiconductors
Chapter 4 Reset, Clocking, and Initialization
RGMII1 TX CLK (125MHz)
FMAN-MAC
EC1_GTX_CLK125
Duty Cycle 125MHz duty cycle corrected clock
MUX
RGMII2 TX CLK (125MHz)
EC2_GTX_CLK125 Reshaper
SYSCLK 1.0 - 1.6 GHz
MUX
SYS_REF_CLK
Core PLL
DIFF_SYSCLK_B/DIFF_SYSCLK
400 MHZ
Platform PLL
Platform Clock
On Board RCW[SYS_PLL_CFG]
Oscillator RCW[SYS_PLL_RAT]
RCW[SYS_PLL_SPD]
100 MHZ
3 Differential outputs
(SCFG_USB_REFCLK_SELCR[1-3])
cfg_eng_use0
SD1_REF_CLK1_P/SD1_REF_CLK1_N
SD1_REF_CLK2_P/SD1_REF_CLK2_N
MUX
USB PHY
3 instances
MUX
1G-1.6G
DDR Controller
DDR
PLL
DDRCLK
RCW[MEM_PLL_RAT]
RCW[MEM_PLL_CFG]
RCW[DDR_REFCLK_SEL] RCW[MEM_PLL_SPD]
SerDes PLL1
SerDes PLL2
Figure 4-3. Single Oscillator Source Clocking
4.4.7.1.2 Dual reference clock mode
In this configuration, a single on-board oscillator must provide two copies of the single
ended reference clock (maximum frequency is 100 MHz), one for the following PLLs:
• Platform PLL, Core PLLs, USB PHY
• DDR PLL
A separate differential clock is provided to the SerDes.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 275
Functional description
RGMII1 TX CLK (125MHz)
FMAN-MAC
EC1_GTX_CLK125
Duty Cycle 125MHz duty cycle corrected clock
MUX
EC2_GTX_CLK125 Reshaper RGMII2 TX CLK (125MHz)
SYSCLK
MUX
SYS_REF_CLK 1.0 - 1.6 GHz
Core PLL
400 MHZ
Platform PLL
Platform Clock
On Board On Board RCW[SYS_PLL_CFG]
Oscillator Oscillator
RCW[SYS_PLL_RAT]
RCW[SYS_PLL_SPD]
100 MHZ
100 MHZ
2 Differential outputs
2 Single ended output
cfg_eng_use0 (SCFG_USB_REFCLK_SELCR[1-3])
SD1_REF_CLK2_P/SD1_REF_CLK2_N
SD1_REF_CLK1_P/SD1_REF_CLK1_N
MUX
USB PHY
3 instances
DDR_PLL
MUX
1G - 1.6G
DDR Controller
DDRCLK
RCW[MEM_PLL_CFG]
RCW[DDR_REFCLK_SEL] RCW[MEM_PLL_RAT]
RCW[MEM_PLL_SPD]
SerDes PLL1
SerDes PLL2
Figure 4-4. Dual reference clocking
4.4.7.1.3 Multiple reference clock mode
In this configuration, the SYSCLK signal provides the reference clock for the following
PLLs:
• Platform PLL
• Core PLL
The DDR PLL is clocked by the DDRCLK signal. This clock is selected through
RCW[DDR_REFCLK_SEL] and one or two additional reference clocks are provided to
the SerDes.
The USB3 PLLs is clocked from either SYSCLK or DIFF_SYSCLK/DIFF_SYSCLK_B.
The selection of this clock is through SCFG_USB_REFCLK_SELCRn register.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
276 NXP Semiconductors
Chapter 4 Reset, Clocking, and Initialization
RGMII1 TX CLK (125MHz)
FMAN-MAC
EC1_GTX_CLK125
125MHz duty cycle corrected clock RGMII2 TX CLK (125MHz)
MUX
EC2_GTX_CLK125 Duty Cycle
Reshaper
On Board
Oscillator
100Mz SYSCLK
1 Single-ended output
MUX
SYS_REF_CLK 1.0 - 1.6 GHz
Core PLL
DIFF_SYSCLK_B/DIFF_SYSCLK
400 MHz
Platform PLL
Platform Clock
On Board RCW[SYS_PLL_CFG]
Oscillator RCW[SYS_PLL_RAT]
RCW[SYS_PLL_SPD]
100 MHZ
3 Differential outputs
cfg_eng_use0 (SCFG_USB_REFCLK_SELCR[1-3])
On Board
SD1_REF_CLK1_P/SD1_REF_CLK1_N
SD1_REF_CLK2_P/SD1_REF_CLK2_N
Oscillator
MUX
100Mz USB PHY
2 Single-ended output 3 instances
MUX
1G-1.6G
DDR Controller
DDR
PLL
DDRCLK
RCW[MEM_PLL_RAT]
RCW[MEM_PLL_CFG]
RCW[DDR_REFCLK_SEL] RCW[MEM_PLL_SPD]
SerDes PLL1
SerDes PLL2
Figure 4-5. Multiple reference clocking
4.4.7.2 IP logic clock distribution and configuration
The chip takes primary clocking input from the external SYSCLK signal. As shown in
Figure 4-6, the SYSCLK input (frequency) is multiplied using multiple phase locked
loops (PLL) to create a variety of frequencies which can then be passed to a variety of
internal logic, including cores and peripheral IP modules.
The DDR PLL is used to provide clocking to the DDR memory controller complexes.
The DDR PLL may use the DIFF_SYSCLK/DIFF_SYSCLK_B input clock as a
reference to create a unique DDR memory controller complex clock. In this case, the
DDR complex operates asynchronously with respect to the platform clock.
Note that many of the IP modules contain logic allowing software to further modify their
external interface clocks within the IP module. See the applicable IP module chapter for
details.
The following figures describes internal logic clock distribution along with the means to
configure the various ratios and clock sources. Note that the following figures are not
intended to reflect external interface clocking. Although sometimes dependent on or
derived from logic clocking, a full description of external interface clocking is described
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 277
Functional description
within the applicable IP module chapter of this reference manual. Each of the four
SerDes bank external interfaces are clocked by dedicated SerDes reference clock inputs
(SD1_REF_CLK1/SD1_REF_CLK2). (See Valid reference clocks and PLL
configurations for SerDes protocols for details regarding valid combinations of external
reference clocks and RCW configurations.)
NOTE
For any operations above 52 MHz, eSDHC must be clocked by
PLL source by setting eSDHCCTL[PCS] to 1.
CGA_PLL1
1/2
RCW[CGA_PLL1_RAT]
1/3
RCW[CGA_PLL1_CFG]
RCW[CGA_PLL1_SPD]
cluster1 clock Core
C1
Cluster 1
CGA_PLL2 (all cores)
1/2
RCW[CGA_PLL2_RAT] 1/3
SYSCLK
RCW[CGA_PLL2_CFG]
RCW[CGA_PLL2_SPD]
RCW[C1_PLL_SEL]
RCW[HWA_CGA_M1_CLK_SEL]
M1
FMAN
RCW[HWA_CGA_M2_CLK_SEL]
/2
M2
/4/8/12/16/20
MUX
/24/32/64/256
RCW[SYS_PLL_CFG]
RCW[SYS_PLL_RAT] SCFG_QSPI_CFG[CLK_SEL]
RCW[SYS_PLL_SPD]
platform clock
Platform PLL to IP Modules
Figure 4-6. Clock subsystem block diagram - cluster group A
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
278 NXP Semiconductors
Chapter 4 Reset, Clocking, and Initialization
to CGA M1
1/4 SYS_REF_CLK 4x GPIO
System
1/4
Counter 2x DUART
LPUART1
Core/CGA PLL1 to CGA M1/CGA M2
5x LPUART
CFG_ENG_USE0 Core/CGA PLL2 to CGA M1/CGA M2 I2C1
3x I2C
platform clk
MUX
SYSCLK Platform PLL SPI
SYS_REF_CLK
RCW[SYS_PLL_CFG] CSU
RCW[SYS_PLL_RAT]
RCW[SYS_PLL_SPD] Platform
Logic
SecMon
eSDHC
1/3
1/3 QuadSPI
RCW[USB3_REFCLK_SEL]
FTM
PBL
MUX
USB PHY
Debug/PerfMon
RCPM
TA_BB_RTC
5x WDOG IFC
RTC
SEC
3x PCIe
SATA
RCW[DDR_REFCLK_SEL] eDMA
USB 3.0
DIFF_SYSCLK_B
qDMA
DIFF_SYSCLK DDR
PLL
DDRCLK 4x SMMU
GIC-400
RCW[MEM_PLL_RAT]
RCW[MEM_PLL_CFG] DDR data rate
DDR Controller QUICC
RCW[MEM_PLL_SPD] Engine
Note that TA_BB_RTC is for internal use only.
Figure 4-7. Clock subsystem block diagram - IP modules
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 279
Functional description
4.4.7.3 CLK_OUT configuration
The CLK_OUT signal can be configured to offer external hardware one of a variety of
internal clock signals for debug or diagnostic purposes.
(See for details.)
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
280 NXP Semiconductors
Chapter 5
Interrupt Assignments
5.1 Introduction
This chapter describes GIC interrupt assignments for the chip. These are the on-chip
interrupt sources from peripheral logic within the integrated device.
5.2 Internal interrupt sources
The implementation of the GIC handles up to 256 interrupt requests to the Arm core. The
following table shows the assignments of the internal interrupt sources.
Table 5-1. Interrupt assignments
Internal Interrupt Source Comments
Interrupt
Number
0-31 Arm internal interrupts These are software generated interrupts for
communication among cores and are triggered
through GIC-400 registers. See Arm generic
interrupt controller (GIC-400) for more information.
32 FTM5 All FTM interrupts are ORed together.
33 FTM6 See FTM Interrupts for more information.
34-63 Reserved
64 Reserved
65 Thermal monitor unit alarm See TMU interrupt enable register (TIER) for more
information.
66 Thermal monitor unit critical alarm
67-70 Reserved
71 qDMA INT0 Virtualized qDMA
72 qDMA INT1 See Command Queue Interrupts for more
73 qDMA INT2 information.
74 qDMA INT3
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 281
Internal interrupt sources
Table 5-1. Interrupt assignments (continued)
Internal Interrupt Source Comments
Interrupt
Number
75 IFC All IFC interrupts are ORed together and connected
to this interrupt.
See Common Event and Error Interrupt Enable
register (IFC_CM_EVTER_INTR_EN) for more
information.
76 Frame manager (FMan) See DPAA reference manual.
77 FMAN/QMAN/BMAN error
78 MDIO management interrupt 1 (1 G)
79 MDIO management interrupt 2 (10 G)(XFI)
80 LPUART1 All LPUART interrupts are ORed together.
81 LPUART2 See Interrupts and status flags for more information.
82 LPUART3
83 LPUART4
84 LPUART5
85 LPUART6
86 DUART1 See Interrupt control logic for more information.
87 DUART2
88 I2C1 All I2C interrupts are ORed together.
89 I2C2 See I2C Bus Status Register (I2C_IBSR) for more
90 I2C3 information.
91 I2C4
92 USB1 See USBSTS register in Table 36-3 for more
information.
93 USB2
94 eSDHC (SD/MMC) See Interrupt status register (IRQSTAT) for more
information.
95 USB3 See USBSTS register in Table 36-3 for more
information.
96 SPI1 See Interrupts/DMA requests for more information.
97 Reserved
98 GPIO1 All GPIO interrupts are ORed together.
99 GPIO2 See GPIO interrupt event register (GPIER) for more
100 GPIO3 information.
101 SATA 3.0
102 EPU All EPU interrupts are ORed together and connected
to this interrupt.
103 SEC job queue 1 For more information, refer Security Reference
Manual.
104 SEC job queue 2
105 SEC job queue 3
106 SEC job queue 4
107 SEC global
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
282 NXP Semiconductors
Chapter 5 Interrupt Assignments
Table 5-1. Interrupt assignments (continued)
Internal Interrupt Source Comments
Interrupt
Number
108 Platform control (Miscellaneous system control All Platform Control interrupts are ORed together
module (MSCM)) and connected to this interrupt.
See Miscellaneous System Control Module
(MSCM) for more information.
109 uQE (QE interrupt + QE critical + QE error)
110 SecMon secure See SecMon_HP Security Violation Status Register
(HPSVSR) for more information.
111 Secmon non-secure See SecMon_HP Status Register (HPSR) for more
information.
112 CSU
113 WDOG3 See Interrupt event for more information.
114 WDOG4
115 WDOG1
116 WDOG2
117 WDOG5
118 FTM1 All FTM interrupts are ORed together.
119 FTM2 See FTM Interrupts for more information.
120 FTM3
121 FTM4
122 Reserved
123 FTM7 All FTM interrupts are ORed together.
124 FTM8 See FTM Interrupts for more information.
125 TZASC All TZASC interrupts are ORed together and
connected to this interrupt.
See TrustZone Address Space Controller (TZASC)
for more information.
126 A53 core 2 CTI IRQ Core 0 and core 1 cross trigger interrupt
127 A53 core 2 PMU IRQ See Arm® Cortex®-A53 core for more information.
128 A53 core 3 CTI IRQ
129 A53 core 3 PMU IRQ
130 Reserved
131 QuadSPI All QuadSPI interrupts are ORed together and
connected to this interrupt.
See Interrupt Signals for more information.
132-134 Reserved
135 eDMA
136 A53 core 0 CTI IRQ Core 0 and core 1 cross trigger interrupt
137 A53 core 1 CTI IRQ See Arm® Cortex®-A53 core for more information.
138 A53 core 0 PMU IRQ
139 A53 core 1 PMU IRQ
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 283
Internal interrupt sources
Table 5-1. Interrupt assignments (continued)
Internal Interrupt Source Comments
Interrupt
Number
140 A53 AXI Error / A53 Int Err It represents the combined interrupt for L1 D-cache
ECC error (for all cores) and L2 cache errors.
See Arm® Cortex®-A53 core for more information.
141 CCI400 ERRORIRQ / CCI EVNTCNTOVERFLOW CCI-400 error interrupt
CCI-400 transaction bus error due to any transaction
error in CCI-400 interconnect and connected to
nERRORIRQ of CCI-400.
See The CCI-400 module as implemented on the
chip for more information.
142 PEX1 INT (INTA, INTB, INTC, or INTD) See PCI Express Interrupt Pin Register (Interrupt_Pi
n_Register) for more information.
143 PEX MSI1 INT2 See PCI Express MSI implementation for more
information.
144 PEX MSI1 INT3
145 PEX MSI1 INT4
146-147 Reserved
148 PEX MSI1 INT1 See PCI Express MSI implementation for more
information.
149 PEX1 PME Refer PM_PME messages in the Power
Management chapter of PCI Express™ Base
Specification, Revision 3.0 for more information.
150 PEX1 CFG err interrupt
151 Reserved
152 PEX2 INT (INTA, INTB, INTC, or INTD) See PCI Express Interrupt Pin Register (Interrupt_Pi
n_Register) for more information.
153 PEX MSI2 INT2 See PCI Express MSI implementation for more
information.
154 PEX MSI2 INT3
155 PEX MSI2 INT4
156-157 Reserved
158 PEX MSI2 INT1 See PCI Express MSI implementation for more
information.
159 PEX2 PME Refer PM_PME messages in the Power
Management chapter of PCI Express™ Base
Specification, Revision 3.0 for more information.
160 PEX2 CFG err interrupt
161-162 Reserved
163 IRQ0 IRQ0-11 are external IO signals connected to
interrupt controller. The polarity of these IRQ's are
164 IRQ1
programmable in Interrupt Polarity Register
165 IRQ2 (SCFG_INTPCR).
The external IO signals(IRQ0-11) are directly
connected to interrupt lines and hence the status of
these interrupts are available in the corresponding
GIC-400 registers.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
284 NXP Semiconductors
Chapter 5 Interrupt Assignments
Table 5-1. Interrupt assignments (continued)
Internal Interrupt Source Comments
Interrupt
Number
166 GPIO4 All GPIO interrupts are ORed together.
See GPIO interrupt event register (GPIER) for more
information.
167 IRQ3 IRQ0-11 are external IO signals connected to
interrupt controller. The polarity of these IRQ's are
168 IRQ4
programmable in Interrupt Polarity Register
169 IRQ5 (SCFG_INTPCR).
The external IO signals(IRQ0-11) are directly
connected to interrupt lines and hence the status of
these interrupts are available in the corresponding
GIC-400 registers.
170 qDMA
171-173 Reserved
174 SMMU-500 (TCU) non-secure This is a single non-secure interrupt from SMMU and
ORed of the following interrupts:
175 SMMU-500 (TCU) secure
• Configuration fault interrupt
• Global fault interrupt
• Performance interrupt
• Context interrupt
See System memory management unit (MMU-500)
for more information.
176 DDR controller (error) Memory error interrupt enable (ERR_INT_EN) for
more information.
177 IRQ6 IRQ0-11 are external IO signals connected to
interrupt controller. The polarity of these IRQ's are
178 IRQ7
programmable in Interrupt Polarity Register
179 IRQ8 (SCFG_INTPCR).
The external IO signals(IRQ0-11) are directly
connected to interrupt lines and hence the status of
these interrupts are available in the corresponding
GIC-400 registers.
180 Reserved
181 IRQ9 IRQ0-11 are external IO signals connected to
interrupt controller. The polarity of these IRQ's are
182 IRQ10
programmable in Interrupt Polarity Register
183 IRQ11 (SCFG_INTPCR).
The external IO signals(IRQ0-11) are directly
connected to interrupt lines and hence the status of
these interrupts are available in the corresponding
GIC-400 registers.
184 Reserved
185 qDMA error interrupt LS1043A assigns individual interrupts (71-74) to
each core.
186 PEX3 INT (INTA, INTB, INTC or INTD) See PCI Express Interrupt Pin Register (Interrupt_Pi
n_Register) for more information.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 285
Internal interrupt sources
Table 5-1. Interrupt assignments (continued)
Internal Interrupt Source Comments
Interrupt
Number
187 PEX MSI3 INT2 See PCI Express MSI implementation for more
information.
188 PEX MSI3 INT3
189 PEX MSI3 INT4
190-191 Reserved
192 PEX MSI3 INT1 See PCI Express MSI implementation for more
information.
193 PEX3 PME Refer PM_PME messages in the Power
Management chapter of PCI Express™ Base
Specification, Revision 3.0 for more information.
194 PEX3 CFG err interrupt
195 Reserved
196 Soft reset core 0 Edge triggered only. This interrupt facilitates core 0
soft reset sequence and should be configured as
edge interrupt. See Core soft reset for more
information.
197 Soft reset core 1 Edge triggered only. This interrupt facilitates core 1
soft reset sequence and should be configured as
edge interrupt. See Core soft reset for more
information.
198-199 Reserved
200 Soft reset core 2 Edge triggered only. This interrupt facilitates core 2
soft reset sequence and should be configured as
edge interrupt. See Core soft reset for more
information.
201 Soft reset core 3 Edge triggered only. This interrupt facilitates core 3
soft reset sequence and should be configured as
edge interrupt. See See Core soft reset for more
information.
202-203 Reserved
204 Queue manager portal 0 See DPAA reference manual.
205 Buffer manager portal 0
206 Queue manager portal 1
207 Buffer manager portal 1
208 Queue manager portal 2
209 Buffer manager portal 2
210 Queue manager portal 3
211 Buffer manager portal 3
212 Queue manager portal 4
213 Buffer manager portal 4
214 Queue manager portal 5
215 Buffer manager portal 5
216 Queue manager portal 6
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
286 NXP Semiconductors
Chapter 5 Interrupt Assignments
Table 5-1. Interrupt assignments (continued)
Internal Interrupt Source Comments
Interrupt
Number
217 Buffer manager portal 6
218 Queue manager portal 7
219 Buffer manager portal 7
220 Queue manager portal 8
221 Buffer manager portal 8
222 Queue manager portal 9
223 Buffer manager portal 9
224 COMMIRQ0
225 COMMIRQ1
226 COMMIRQ2
227 COMMIRQ3
228 MBEE Internal RAM Multi-bit ECC Error
229 Virtual CPU interface maintenance interrupt Core 0
230 Virtual CPU interface maintenance interrupt Core 1
231 Virtual CPU interface maintenance interrupt Core 2
232 Virtual CPU interface maintenance interrupt Core 3
233 Reserved Edge interrupt
234 PEX 1 Hot Reset Edge interrupt
235 PEX 1 Link Down Edge interrupt
236 PEX 1 Link Up Edge interrupt
237 Reserved Edge interrupt
238 PEX 2 Hot Reset Edge interrupt
239 PEX 2 Link Down Edge interrupt
240 PEX 2 Link Up Edge interrupt
241 Reserved Edge interrupt
242 PEX 3 Hot Reset Edge interrupt
243 PEX 3 Link Down Edge interrupt
244 PEX 3 Link Up Edge interrupt
245-255 Reserved
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 287
Internal interrupt sources
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
288 NXP Semiconductors
Chapter 6
Arm Modules
6.1 Introduction
The chip implements the following Arm modules:
• Arm® Cortex®-A53 core
• Arm generic interrupt controller (GIC-400)
• System memory management unit (MMU-500)
• Cache coherent interconnect (CCI-400)
• Arm CoreLink™ TrustZone address space controller (TZC-380)
This chapter provides a brief overview of the core, interrupt controller, and memory
management unit. For more information on these modules, see the Arm documentation
that accompanies this reference manual.
Table 6-1. Related resources from Arm
Resource IP Revision
Arm® Cortex®-A53 MPCore Processor Technical Reference Manual r0p4
CoreLink™ GIC-400 Generic Interrupt Controller Technical Reference Manual r0p1
Arm® CoreLink™ MMU-500 System Memory Management Unit Technical Reference Manual r2p2
For information on other Arm modules, see the following:
• Cache Coherent Interconnect (CCI-400)
• Arm CoreLink™ TrustZone Address Space Controller (TZC-380)
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 289
Arm® Cortex®-A53 core
6.2 Arm® Cortex®-A53 core
The Arm® Cortex®-A53 processor is an extremely power efficient Armv8 processor
capable of supporting 32-bit and 64-bit code seamlessly. It makes use of a highly
efficient 8-stage in-order pipeline balanced with advanced fetch and data access
techniques for performance.
The multicore processing provides the ability for any of the four component processors,
within a cluster, to shut down when not in use, for instance when the device is in standby
mode, to save power. When higher performance is required, every processor is in use to
meet the demand while still sharing the workload to keep power consumption as low as
possible.
The LS1043A features four high-performance Cortex A53 cores:
• 64 and 32-bit execution states for scalable high performance
• Multiple coherent SMP processor clusters through AMBA® 4 technology
• New instruction set, A64
• In-order pipeline with symmetric dual-issue of most instructions
• 32 KB Instruction Cache, 32 KB Data Cache, 1 MB unified L2 Cache.
• NEON technology - Accelerates multimedia and signal processing algorithms such
as video encode/decode, 2D/3D graphics, gaming, audio and speech processing,
image processing, telephony, and sound synthesis. Also useful in accelerating
floating point code with SIMD execution.
• Hardware-accelerated cryptography - 3x-10x better software encryption performance
Useful for small granule decrypt/encrypt too small to efficiently offload to HW
accelerator
• Floating point unit - Hardware support for floating point operations in half-, single-
and double-precision floating point arithmetic. IEE754-2008 enhancements are
included.
• TrustZone® Technology - Ensures reliable implementation of security applications
ranging from digital rights management to electronic payment.
• Double Precision Floating Point SIMD - Allows SIMD vectorisation to be applied to
a much wider set of algorithms (for example scientific / high performance computing
(HPC) and supercomputer).
• 64-bit Virtual address reach - Enables virtual memory beyond 4GB 32b limit.
Important for modern desktop and server software using memory mapped file I/O,
sparse addressing.
• Enhanced Cache management - User space cache operations improve dynamic code
generation efficiency, data cache zero for fast clear.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
290 NXP Semiconductors
Chapter 6 Arm Modules
• Extensive power-saving features - Hierarchical clock gating, power domains,
advanced retention modes
• Hardware virtualization support
• Arranged as a cluster of four cores sharing a single 1 MB L2 cache
• NEON SIMD extensions onboard (per core)
• Single-threaded cores with 32 KB L1 data cache and 32 KB L1 instruction cache
• In-order pipeline with symmetric dual-issue of most instructions.
LS1043A contains one Arm Cortex A53 MPCore cluster, each with four 64-bit Arm A53
v8 cores connected to a shared L2 cache. The following table summarizes the core-cluster
sub-system implementation within the chip:
Table 6-2. Summary: core cluster sub-system implementation
A53 MPCore parameter Options Selection Comments
Number of cores 1, 2, 3, 4 4
L1 Icache size 8K, 16K, 32K, 64K 32K
L1 Dcache size 8K, 16K, 32K, 64K 32K Applies to all cores
L2 cache Included, not included Included Applies to all cores
L2 cache size 128K, 256K, 512K, 1024K, 1024K
2048K
L2 data RAM input latency 1 cycle, 2 cycles 1 cycle
L2 data RAM output latency 2 cycles, 3 cycles 2 cycles
SCU L2 cache protection Included, not included Included
Advanced SIMD and floating- Included, not included Included Applies to all cores
point extension
Cryptography extension Included, not included Included Applies to all cores
CPU cache protection Included, not included Included Applies to all cores
Master memory interface AMBA 5 CHI, AMBA 4 ACE AMBA 4 ACE
Accelerator coherency port Included, not included Included
Debug memory map v7, v8 v8
6.3 Arm generic interrupt controller (GIC-400)
Generic interrupt controller (GIC) is a centralized resource for supporting and managing
interrupts in a system that includes at least one processor. It provides:
• registers for managing interrupt sources, interrupt behavior, and interrupt routing to
one or more processors
• support for the following:
• the Arm architecture security extensions
• the Arm architecture virtualization extensions
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 291
System memory management unit (MMU-500)
• enabling, disabling, and generating processor interrupts from hardware (peripheral)
interrupt sources
• Software-generated interrupts (SGIs) interrupt masking and prioritization
uniprocessor and multiprocessor environments
For LS1043A, GIC-400 registers memory-map is aligned to 64 KB.
Table 6-3. GIC memory allocation
Start address End address Size Allocation
0x0140_0000 0x0140_FFFF 64K Reserved
0x0141_0000 0x0141_FFFF 64K Distributor
0x0142_0000 0x0142_FFFF 64K CPU interfaces (GICC_CTLR available at 0x142_0000)
0x0143_0000 0x0143_FFFF 64K CPU interfaces (GICC_DIR available at 0x143_0000)
0x0144_0000 0x0144_FFFF 64K Virtual interface control block, for the processor that is
performing the access
0x0145_0000 0x0145_FFFF 64K Virtual interface control block, for the processor selected
by address bits [11:9]
0x0146_0000 0x0146_FFFF 64K Virtual CPU interfaces (GICV_CTLR available at
0x146_F000)
0x0147_0000 0x0147_FFFF 64K Virtual CPU interfaces (GICV_DIR available at address
0x147_0000)
6.4 System memory management unit (MMU-500)
The MMU-500 is a system-level Memory Management Unit (MMU) that translates an
input address to an output address, by performing one or more translation table walks.
It supports the translation table formats defined by the Arm architecture, and can perform
• Stage 1 translations that translate an input Virtual Address (VA) to an output
Physical Address (PA) or Intermediate Physical Address (IPA).
• Stage 2 translations that translate an input IPA to an output PA.
• Combined stage 1 and stage 2 translations that translate an input VA to an output
IPA, and then translate that IPA to a PA. The MMU-500 performs a translation table
walk for each stage of the translation.
• The purpose of separating the process into 2 stages is to allow the guest OS to control
the address translation between VA and what it “thinks” is the PA, while the
Hypervisor controls the translation from IPA to PA. This split process allows the
Hypervisor to separate the resources of different Virtual Machines (VMs). Address
translation is performed both in the cores and also for IO devices, using the System
Memory Management Unit (SMMU).
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
292 NXP Semiconductors
Chapter 6 Arm Modules
The MMU-500 is a distributed SMMU, which makes use of one central controller (TCU)
and up to 32 translation units (TBUs). In this chip there is a is a single TCU, supporting a
total of 4 TBUs. The SMMU supports 8 Stream ID bits and SSD. The security attributes
and other security features depends on the SSD.
The SSD is secure state determination. In LS1043A, the SSD table is initialized to
contain only two entries 0 (secure transaction) and 1 (non-secure transaction). And, these
entries are indexed by the NS_IN attribute (0 for secure and 1 for non-secure) of the
transaction.
Each master has an unique stream ID assigned to it. The StreamID is an identifier
attached to each transaction in order to determine the translation context. The SMMU
uses in hit/miss mechanism for the following concatenation {tbu number, stream_id}.
This concatenation (and not just the stream id) is then assigned (if exist)to a context bank
that determines the translation type and form. Another parameter that affects the
translation is the SSD value. Secure transactions can only be subjected to a stage 2
translation, so this value also plays a part in the translation process.
The isolation context identifier (ICID) maps an incoming transaction from IO device to
one of the context, it maps to StreamID as described in Arm documentations. All the
SMMU support 8 ICID bits and SSD index. The address translation depends only on the
ICID of the incoming transaction. The security attributes and other security features
depends on the SSD index.
Some masters have an unique ICID assigned to it and is configurable through SCFG
registers. The ICID is an identifier attached to each transaction in order to determine the
translation context. The SSD index and ICID for the masters are identical and share the
same register field of ICID registers.
Table 6-4. ICID connectivity
IO Device ICID Connectivity
IP Driven SCFG Register
FMan ICID output of FMan not configured through SCFG registers
QMan/BMan ICID output of QMan/ not configured through SCFG registers
BMan
SEC ICID output of SEC not configured through SCFG registers
PCI express ICID output of PCI not configured through SCFG registers
1, 2, 3 Express
qDMA ICID output of qDMA not configured through SCFG registers
SATA - One register to define 8 bits for ICID. Refer SATA ICID register (SATA_ICID) in chapter
"Supplemental Configuration Unit".
USB 1, 2, 3 - One register to define 8 bits for ICID. Refer USB1 ICID register (USB1_ICID), USB2
ICID Register (USB2_ICID), and USB3 ICID Register (USB3_ICID) in chapter
"Supplemental Configuration Unit".
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 293
System memory management unit (MMU-500)
Table 6-4. ICID connectivity (continued)
IO Device ICID Connectivity
IP Driven SCFG Register
eDMA - One register to define 8 bits for ICID. Refer eDMA ICID register (DMA_ICID) in chapter
"Supplemental Configuration Unit".
Debug path - One register to define 8 bits for ICID. Refer Debug ICID register (Debug_ICID) in
chapter "Supplemental Configuration Unit".
eSDHC - One register to define 8 bits for ICID. Refer eSDHC ICID register (SDHC_ICID) in
chapter "Supplemental Configuration Unit".
All the SMMU's support cache coherency for the page table walks and DVM transactions
for page table cache maintenance operations. The PAGESIZE for all the SMMU's are 64
KB size.
The key guideline in the SMMU structure is that any transaction from any IP to a
memory location (either to another IP or to the external memory) must go through the
SMMU. This is true even if the device generates transactions using physical address, as
the SMMU is also required for resource separation between VMs and must therefore
inspect every transaction.
The following SMMU registers are implementation specific and their values are
mentioned below:
Register Secure access Non-secure access
SMMU_IDR0 32’hFC01_7E40 32’h7C01_7E40
SMMU_IDR1 32’h4000_1F20 32’h4000_0020
SMMU_IDR2 32’h0000_5555 32’h0000_5555
SMMU_IDR7 32’h0000_0021 32’h0000_0021
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
294 NXP Semiconductors
Chapter 7
CSU, OCRAM, and MSCM
7.1 Central Security Unit
The CSU manages the system security policy for accessing device peripherals. The CSU
allows trusted code to set individual security access privileges for each of the peripherals,
using one of eight security access privilege levels.
CSU features include:
• Configuration of peripheral access permissions for those peripherals unable to
control their own access permissions
• Note that some peripherals/bus slaves have their own access control capabilities
(ability to reject transactions from unauthorized masters).
• Optional locking of individual CSU settings until the next POR
• Additional general purpose security related control bits
The CSU controls four parameters, allowing for eight security access privilege levels.
• Secure World vs Non-Secure World access
• Supervisor vs User access
• Read access
• Write access
Supervisor access is superset access to both User and Supervisor. Secure World access is
superset access to both Non-Secure and Secure World.
The OCRAM is 64KB of On-Chip SRAM, restricted to Secure World access only by the
CSU.
CSU related platform control registers are found in the Miscellaneous System Control
Module. The MSCM provides error reporting related to attempted access control
violations blocked by the CSU.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 295
Central Security Unit
7.1.1 CSU Memory Map/Register Definition
The following registers, CSL and SA are collectively referred to as CSU Security Control
Registers (SCRs) and can be written only by software executing in the TrustZone Secure
Supervisor Mode.
CSU memory map
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
151_0000 Config Security Level (CSU_CSL) 32 R/W 0033_0033h 7.1.1.1/296
151_0218 Secure Access register (CSU_SA0) 32 R/W 0000_0000h 7.1.1.2/302
151_021C Secure Access register (CSU_SA1) 32 R/W 0000_0000h 7.1.1.2/302
7.1.1.1 Config Security Level (CSU_CSL)
Each Config Security Level Register holds the config security level bits (access
permission bits) for two targets. In the below table all peripherals are initially Secure
User/Supervisor Read/Write Enabled, with no access by non-secure world masters. The
CSL registers allow secure world to make the various peripherals’ registers accessible to
non-secure world software and bus masters.
NOTE
The PCI express, IFC, QuadSPI, eSDHC, SATA, USB, FMAN,
QMAN, BMAN, and FlexTimer modules must be configured as
non-secure peripherals and their default value needs to be
configured as SL7-SL0 for all accesses enabled.
Table 7-1. CSL Device Peripherals
Offset CSL Register[bits] Reset value (in binary) Peripheral
0xBASE_0000 CSL0[24:16] 0_0011_0011 PCI express controller 2 IO
configuration space and
memory space
CSL0[8:0] 0_0011_0011 PCI express controller 1 IO
configuration space and
memory space
0xBASE_0004 CSL1[24:16] 0_0011_0011 Reserved
CSL1[8:0] 0_0011_0011 Integrated Flash Controller
(IFC) memory space
0xBASE_0008 CSL2[24:16] 0_0011_0011 OCRAM1
CSL2[8:0] 0_0011_0011 Reserved
0xBASE_000C CSL3[24:16] 0_0011_0011 PCI express controller 1
registers (including LUT)
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
296 NXP Semiconductors
Chapter 7 CSU, OCRAM, and MSCM
Table 7-1. CSL Device Peripherals (continued)
Offset CSL Register[bits] Reset value (in binary) Peripheral
CSL3[8:0] 0_0011_0011 OCRAM2
0xBASE_0010 CSL4[24:16] 0_0011_0011 QuadSPI (QSPI) memory
space
CSL4[8:0] 0_0011_0011 PCI express controller 2
registers (including LUT)
0xBASE_0014 CSL5[24:16] 0_0011_0011 SATA controller registers
CSL5[8:0] 0_0011_0011 USB 3.0 controllers registers
USB controller 1 and PHY
registers
0xBASE_0018 CSL6[24:16] 0_0011_0011 QMan and BMan Software
portal
CSL6[8:0] 0_0011_0011 Reserved
0xBASE_001C CSL7[24:16] 0_0011_0011 Reserved
CSL7[8:0] 0_0011_0011 Reserved
0xBASE_0020 CSL8[24:16] 0_0011_0011 PCI express controller 3
CCSR registers (including
LUT)
CSL8[8:0] 0_0011_0011 PCI express controller 3 (this
includes memory, IO and
Configuration space)
0xBASE_0024 CSL9[24:16] 0_0011_0011 Reserved
CSL9[8:0] 0_0011_0011 Reserved
0xBASE_0028 CSL10[24:16] 0_0011_0011 USB3 controller and PHY
registers (CCSR)
CSL10[8:0] 0_0011_0011 USB controller 2 and PHY
registers (CCSR)
0xBASE_002C CSL11[24:16] 0_0011_0011 Reserved
CSL11[8:0] 0_0011_0011 Reserved
0xBASE_0030 CSL12[24:16] 0_0011_0011 Reserved
CSL12[8:0] 0_0011_0011 Reserved
0xBASE_0034 CSL13[24:16] 0_0011_0011 Reserved
CSL13[8:0] 0_0011_0011 Reserved
0xBASE_0038 CSL14[24:16] 0_0011_0011 Reserved
CSL14[8:0] 0_0011_0011 Reserved
0xBASE_003C CSL15[24:16] 0_0011_0011 Reserved
CSL15[8:0] 0_0011_0011 Reserved
0xBASE_0040 CSL16[24:16] 0_0011_0011 SerDes registers
CSL16[8:0] 0_0011_0011 qDMA registers
0xBASE_0044 CSL17[24:16] 0_0011_0011 Low Power UART (LPUART)
controller 2 registers
CSL17[8:0] 0_0011_0011 Low Power UART (LPUART)
controller 1 registers
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 297
Central Security Unit
Table 7-1. CSL Device Peripherals (continued)
Offset CSL Register[bits] Reset value (in binary) Peripheral
0xBASE_0048 CSL18[24:16] 0_0011_0011 Low Power UART (LPUART)
controller 4 registers
CSL18[8:0] 0_0011_0011 Low Power UART (LPUART)
controller 3 registers
0xBASE_004C CSL19[24:16] 0_0011_0011 Low Power UART (LPUART)
controller 6 registers
CSL19[8:0] 0_0011_0011 Low Power UART (LPUART)
controller 5 registers
0xBASE_0050 CSL20[24:16] 0_0011_0011 Reserved
CSL20[8:0] 0_0011_0011 De-serial serial peripheral
interface 1 (SPI1) registers
0xBASE_0054 CSL21[24:16] 0_0011_0011 QuadSPI (QSPI) controller
registers
CSL21[8:0] 0_0011_0011 Enhanced Secured Digital
Host Controller (eSDHC)
registers
0xBASE_0058 CSL22[24:16] 0_0011_0011 Reserved
CSL22[8:0] 0_0011_0011 Integrated Flash Controller
(IFC) registers
0xBASE_005C CSL23[24:16] 0_0011_0011 I2C Controller 1 registers
CSL23[8:0] 0_0011_0011 Reserved
0xBASE_0060 CSL24[24:16] 0_0011_0011 I2C Controller 3 registers
CSL24[8:0] 0_0011_0011 I2C Controller 2 registers
0xBASE_0064 CSL25[24:16] 0_0011_0011 DUART 2 registers
CSL25[8:0] 0_0011_0011 DUART 1 registers
0xBASE_0068 CSL26[24:16] 0_0011_0011 Watchdog 2 registers
CSL26[8:0] 0_0011_0011 Watchdog 1 registers
0xBASE_006C CSL27[24:16] 0_0011_0011 Enhanced DMA (eDMA)
registers
CSL27[8:0] 0_0011_0011 System Counter registers?
0xBASE_0070 CSL28[24:16] 0_0011_0011 Direct Memory Access
Multiplexer 2
CSL28[8:0] 0_0011_0011 Direct Memory Access
Multiplexer 1
0xBASE_0074 CSL29[24:16] 0_0011_0011 DDR controller registers
CSL29[8:0] 0_0011_0011 QUICC Engine registers
0xBASE_0078 CSL30[24:16] 0_0011_0011 DCFG, CCU, RCPM
CSL30[8:0] 0_0011_0011 Secure Boot ROM controller
registers
0xBASE_007C CSL31[24:16] 0_0011_0011 Security Fuse Processor
(SFP) registers
CSL31[8:0] 0_0011_0011 Thermal Monitoring Unit
(TMU) registers
0xBASE_0080 CSL32[24:16] 0_0011_0011 Security Monitor registers
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
298 NXP Semiconductors
Chapter 7 CSU, OCRAM, and MSCM
Table 7-1. CSL Device Peripherals (continued)
Offset CSL Register[bits] Reset value (in binary) Peripheral
CSL32[8:0] 0_0011_0011 Supplemental configuration
unit (SCFG)
0xBASE_0084 CSL33[24:16] 0_0011_0011 Frame Manager (FMan)
registers
CSL33[8:0] 0_0011_0011 SEC 5.5 registers
0xBASE_0088 CSL34[24:16] 0_0011_0011 Buffer Manager(BMan)
registers
CSL34[8:0] 0_0011_0011 Queue Manager(QMan)
registers
0xBASE_008C CSL35[24:16] 0_0011_0011 General Purpose IO (GPIO)
controller 2 registers
CSL35[8:0] 0_0011_0011 General Purpose IO (GPIO)
controller 1 registers
0xBASE_0090 CSL36[24:16] 0_0011_0011 General Purpose IO (GPIO)
controller 4 registers
CSL36[8:0] 0_0011_0011 General Purpose IO (GPIO)
controller 3 registers
0xBASE_0094 CSL37[24:16] 0_0011_0011 Platform Control registers
Similar to COP SCFG and
stores the status and address
attributes of the blocked/failed
transactions to the modules
CSL37[8:0] 0_0011_0011 Central Security Unit (CSU)
registers
0xBASE_0098 CSL38[24:16] 0_0011_0011 Reserved
CSL38[8:0] 0_0011_0011 I2C Controller 4 registers
0xBASE_009C CSL39[24:16] 0_0011_0011 Watchdog 4 registers
CSL39[8:0] 0_0011_0011 Watchdog 3 registers
0xBASE_00A0 CSL40[24:16] 0_0011_0011 Reserved
CSL40[8:0] 0_0011_0011 Watchdog 5 registers
0xBASE_00A4 CSL41[24:16] 0_0011_0011 Reserved
CSL41[8:0] 0_0011_0011 Reserved
0xBASE_00A8 CSL42[24:16] 0_0011_0011 Reserved
CSL42[8:0] 0_0011_0011 Reserved
0xBASE_00AC CSL43[24:16] 0_0011_0011 Flex Timer Module 2
controller registers
CSL43[8:0] 0_0011_0011 Flex Timer Module 1
controller registers
0xBASE_00B0 CSL44[24:16] 0_0011_0011 FlexTimer Module 4 controller
registers
CSL44[8:0] 0_0011_0011 Flex Timer Module 3
controller registers
0xBASE_00B4 CSL45[24:16] 0_0011_0011 FlexTimer Module 6 controller
registers
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 299
Central Security Unit
Table 7-1. CSL Device Peripherals (continued)
Offset CSL Register[bits] Reset value (in binary) Peripheral
CSL45[8:0] 0_0011_0011 Flex Timer Module 5
controller registers
0xBASE_00B8 CSL46[24:16] 0_0011_0011 FlexTimer Module 8 controller
registers
CSL46[8:0] 0_0011_0011 FlexTimer Module 7 controller
registers
CSL47-CSL59 0_0011_0011 Reserved
CSL60_REG[8:0] 0_0011_0011 DCSR
Address: 151_0000h base + 0h offset = 151_0000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reserved L2 SL15 SL14 SL13 SL12 SL11 SL10 SL9 SL8
Reset 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved L1 SL7 SL6 SL5 SL4 SL3 SL2 SL1 SL0
Reset 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1
CSU_CSL field descriptions
Field Description
31–25 This field is reserved.
-
24 Lock bit corresponding to the slave. (It is written by secure software.)
L2
0 Not locked. Bits 16-23 can be written by software.
1 Locked. Bits 16-23 cannot be written by software.
23 SL15
SL15
0 Non-secured supervisor write access disabled
1 Non-secured supervisor write access enabled
22 SL14
SL14
0 Non-secured user write access disabled
1 Non-secured user write access enabled
21 SL13
SL13
0 Secured supervisor write access disabled
1 Secured supervisor write access enabled
20 SL12
SL12
0 Secured user write access disabled
1 Secured user write access enabled
19 SL11
SL11
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
300 NXP Semiconductors
Chapter 7 CSU, OCRAM, and MSCM
CSU_CSL field descriptions (continued)
Field Description
0 Non-secured supervisor read access disabled
1 Non-secured supervisor read access enabled
18 SL10
SL10
0 Non-secured user read access disabled
1 Non-secured user read access enabled
17 SL9
SL9
0 Secured supervisor read access disabled
1 Secured supervisor read access enabled
16 SL8
SL8
0 Secured user read access disabled
1 Secured user read access enabled
15–9 This field is reserved.
-
8 Lock bit corresponding to the slave. (It is written by secure software.)
L1
0 Not locked. Bits 0-7 can be written by software.
1 Locked. Bits 0-7 cannot be written by software.
7 SL7
SL7
0 Non-secured supervisor write access disabled
1 Non-secured supervisor write access enabled
6 SL6
SL6
0 Non-secured user write access disabled
1 Non-secured user write access enabled
5 SL5
SL5
0 Secured supervisor write access disabled
1 Secured supervisor write access enabled
4 SL4
SL4
0 Secured user write access disabled
1 Secured user write access enabled
3 SL3
SL3
0 Non-secured supervisor read rccess disabled
1 Non-secured supervisor read access enabled
2 SL2
SL2
0 Non-secured user read access disabled
1 Non-secured user Read access enabled
1 SL1
SL1
0 Secured supervisor read access disabled
1 Secured supervisor read access enabled
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 301
Central Security Unit
CSU_CSL field descriptions (continued)
Field Description
0 SL0
SL0
0 Secured user read access disabled
1 Secured user read access enabled
7.1.1.2 Secure Access register (CSU_SAn)
The following table provides the mapping of CSU secure access register bits.
Table 7-2. Mapping of CSU secure access register bits
Offset Register Bits Reset Description
0xBASE_218 csu_sa0[5-4] 0x0 Software-override bit for
SPNIDEN signal connectivity
to core, CCI-400, SMMU, and
debug components.
0xBASE_218 csu_sa0[7-6] 0x0 Software-override bit for
NIDEN signal connectivity to
core, CCI-400, SMMU, and
debug components.
0xBASE_218 csu_sa0[9-8] 0x0 Software-override bit for
SPIDEN signal connectivity to
core, SMMU, and debug
components
0xBASE_218 csu_sa0[11-10] 0x0 Software-Override bit for
DBGEN signal connectivity to
core, SMMU, and debug
components
0xBASE_218 csu_sa0[13-12] 0x0 CP15SDISABLE for core 0
0xBASE_218 csu_sa0[15-14] 0x0 CP15SDISABLE for core 1
0xBASE_218 csu_sa0[17-16] 0x0 CFGDISABLE for GIC-400
0xBASE_218 csu_sa0[19-18] 0x0 Non-secure attribute control
for debug components
0xBASE_218 csu_sa0[23-20] 0x0 -
0xBASE_218 csu_sa0[25-24] 0x0 CP15DISABLE for core2-
0xBASE_218 csu_sa0[27-26] 0x0 CP15DISABLE for core3-
0xBASE_218 csu_sa0[31-28] 0x0 -
0xBASE_21C csu_sa1[3-2] 0x0 Trust Zone address space
controller bypass mux. The
TZASC module is disabled
and logically bypassed.
0xBASE_21C csu_sa1[5-4] 0x0 Secure boot lock for Trust-
Zone address space controller
registers
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
302 NXP Semiconductors
Chapter 7 CSU, OCRAM, and MSCM
Address: 151_0000h base + 218h offset + (4d × i), where i=0d to 1d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SA15_n
SA14_n
SA13_n
SA12_n
SA11_n
SA10_n
SA9_n
SA8_n
L15_n
L14_n
L13_n
L12_n
L11_n
L10_n
L9_n L8_n
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
SA7_n
SA6_n
SA5_n
SA4_n
SA3_n
SA2_n
SA1_n
SA0_n
L7_n L6_n L5_n L4_n L3_n L2_n L1_n L0_n
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CSU_SAn field descriptions
Field Description
31 Lock bit set by secure software.
L15_n
0 Stands for no lock condition and (2*n)th bit can be written by software.
1 Stands for locking of (2*n) th bit and once set software cannot write on the SA field.
30 Secured access indicator
SA15_n
0 Stands for Secured Access indication for nth Type 1 Master corresponding to this 32-bit register.
1 Stands for Non-Secured Access for that master.
29 Lock bit set by secure software.
L14_n
0 Stands for no lock condition and (2*n)th bit can be written by software.
1 Stands for locking of (2*n) th bit and once set software cannot write on the SA field.
28 Secured access indicator
SA14_n
0 Stands for Secured Access indication for nth Type 1 Master corresponding to this 32-bit register.
1 Stands for Non-Secured Access for that master.
27 Lock bit set by secure software.
L13_n
0 Stands for no lock condition and (2*n)th bit can be written by software.
1 Stands for locking of (2*n) th bit and once set software cannot write on the SA field.
26 Secured access indicator
SA13_n
0 Stands for Secured Access indication for nth Type 1 Master corresponding to this 32-bit register.
1 Stands for Non-Secured Access for that master.
25 Lock bit set by secure software.
L12_n
0 Stands for no lock condition and (2*n)th bit can be written by software.
1 Stands for locking of (2*n) th bit and once set software cannot write on the SA field.
24 Secured access indicator
SA12_n
0 Stands for Secured Access indication for nth Type 1 Master corresponding to this 32-bit register.
1 Stands for Non-Secured Access for that master.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 303
Central Security Unit
CSU_SAn field descriptions (continued)
Field Description
23 Lock bit set by secure software.
L11_n
0 Stands for no lock condition and (2*n)th bit can be written by software.
1 Stands for locking of (2*n) th bit and once set software cannot write on the SA field.
22 Secured access indicator
SA11_n
0 Stands for Secured Access indication for nth Type 1 Master corresponding to this 32-bit register.
1 Stands for Non-Secured Access for that master.
21 Lock bit set by secure software.
L10_n
0 Stands for no lock condition and (2*n)th bit can be written by software.
1 Stands for locking of (2*n) th bit and once set software cannot write on the SA field.
20 Secured access indicator
SA10_n
0 Stands for Secured Access indication for nth Type 1 Master corresponding to this 32-bit register.
1 Stands for Non-Secured Access for that master.
19 Lock bit set by secure software.
L9_n
0 Stands for no lock condition and (2*n)th bit can be written by software.
1 Stands for locking of (2*n) th bit and once set software cannot write on the SA field.
18 Secured access indicator
SA9_n
0 Stands for Secured Access indication for nth Type 1 Master corresponding to this 32-bit register.
1 Stands for Non-Secured Access for that master.
17 Lock bit set by secure software.
L8_n
0 Stands for no lock condition and (2*n)th bit can be written by software.
1 Stands for locking of (2*n) th bit and once set software cannot write on the SA field.
16 Secured access indicator
SA8_n
0 Stands for Secured Access indication for nth Type 1 Master corresponding to this 32-bit register.
1 Stands for Non-Secured Access for that master.
15 Lock bit set by secure software.
L7_n
0 Stands for no lock condition and (2*n)th bit can be written by software.
1 Stands for locking of (2*n) th bit and once set software cannot write on the SA field.
14 Secured access indicator
SA7_n
0 Stands for Secured Access indication for nth Type 1 Master corresponding to this 32-bit register.
1 Stands for Non-Secured Access for that master.
13 Lock bit set by secure software.
L6_n
0 Stands for no lock condition and (2*n)th bit can be written by software.
1 Stands for locking of (2*n) th bit and once set software cannot write on the SA field.
12 Secured access indicator
SA6_n
0 Stands for Secured Access indication for nth Type 1 Master corresponding to this 32-bit register.
1 Stands for Non-Secured Access for that master.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
304 NXP Semiconductors
Chapter 7 CSU, OCRAM, and MSCM
CSU_SAn field descriptions (continued)
Field Description
11 Lock bit set by secure software.
L5_n
0 Stands for no lock condition and (2*n)th bit can be written by software.
1 Stands for locking of (2*n) th bit and once set software cannot write on the SA field.
10 Secured access indicator
SA5_n
0 Stands for Secured Access indication for nth Type 1 Master corresponding to this 32-bit register.
1 Stands for Non-Secured Access for that master.
9 Lock bit set by secure software.
L4_n
0 Stands for no lock condition and (2*n)th bit can be written by software.
1 Stands for locking of (2*n) th bit and once set software cannot write on the SA field.
8 Secured access indicator
SA4_n
0 Stands for Secured Access indication for nth Type 1 Master corresponding to this 32-bit register.
1 Stands for Non-Secured Access for that master.
7 Lock bit set by secure software.
L3_n
0 Stands for no lock condition and (2*n)th bit can be written by software.
1 Stands for locking of (2*n) th bit and once set software cannot write on the SA field.
6 Secured access indicator
SA3_n
0 Stands for Secured Access indication for nth Type 1 Master corresponding to this 32-bit register.
1 Stands for Non-Secured Access for that master.
5 Lock bit set by secure software.
L2_n
0 Stands for no lock condition and (2*n)th bit can be written by software.
1 Stands for locking of (2*n) th bit and once set software cannot write on the SA field.
4 Secured access indicator
SA2_n
0 Stands for Secured Access indication for nth Type 1 Master corresponding to this 32-bit register.
1 Stands for Non-Secured Access for that master.
3 Lock bit set by secure software.
L1_n
0 Stands for no lock condition and (2*n)th bit can be written by software.
1 Stands for locking of (2*n) th bit and once set software cannot write on the SA field.
2 Secured access indicator
SA1_n
0 Stands for Secured Access indication for nth Type 1 Master corresponding to this 32-bit register.
1 Stands for Non-Secured Access for that master.
1 Lock bit set by secure software.
L0_n
0 Stands for no lock condition and (2*n)th bit can be written by software.
1 Stands for locking of (2*n) th bit and once set software cannot write on the SA field.
0 Secured access indicator
SA0_n
0 Stands for Secured Access indication for nth Type 1 Master corresponding to this 32-bit register.
1 Stands for Non-Secured Access for that master.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 305
On-Chip RAM memory controller (OCRAM)
7.1.2 Initialization Policy
For peripherals whose access controls are configured in the CSU
1. Set (and optionally lock) the CSU_CSLn register fields to set each peripheral’s
access permissions as a target
2. Set (and optionally lock) the CSU_SA register fields
NOTE
Once set, CSU lock bits can only be cleared by a device reset.
7.2 On-Chip RAM memory controller (OCRAM)
The on-chip RAM is implemented as a slave device on the 64-bit system AXI bus. There
are two OCRAMs in the chip and access can be controlled through CSU peripheral
register programming.
Each OCRAM occupies a 64 KB of address region and the start address of each OCRAM
(64 KB each) in the memory map is given below:
• OCRAM1: 0x1000_0000
• OCRAM2: 0x1001_0000.
NOTE
The OCRAM1 and OCRAM2 memory content is not initialized
to zero by the chip. The software must initialize both OCRAM1
and OCRAM2 in full width (64-bit) access and then perform a
write to bit 5 and 6 at address 0x2014_0534 and 0x2014_0544,
respectively with the value 0x0 to clear the single and multi-bit
ECC errors for OCRAM1 and OCRAM2. Also, the ECC error
interrupt needs to be cleared in GIC (MBEE). Once completed,
the host processor enables interrupt related to ECC errors from
OCRAM1 and OCRAM2
7.3 Miscellaneous System Control Module (MSCM)
The MSCM (platform control) stores the status and address attributes of a transaction to a
peripheral which was blocked by the CSU. The MSCM also enables CSU interrupts.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
306 NXP Semiconductors
Chapter 7 CSU, OCRAM, and MSCM
7.3.1 MSCM Access Control and TrustZone Security
(ACTZS)Memory Map/Register Definition
The ACTZS configuration portion of the MSCM programming model map is shown in
the table below. It is partitioned into two sections:
Offset addresses 0xC00 - 0xC18 define interrupt configurability of CSU related access
violation reporting.
Offset addresses 0xD00 - 0xDDC contain captured access address and attribute
information for CSL-detected violations.
Attempted writes to read-only registers are simply ignored (RO/WI). This section
contains the target access fault information like CSLn attribute check logic plus an array
of 128-bit register structures containing captured CSLn fault information.
All the register accesses are privilege/supervisor
MSCM_ACTZS memory map
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
ACTZS CSL Interrupt Enable Register
152_0C10 32 R/W 0000_0000h 7.3.1.1/307
(MSCM_ACTZS_CSLIER)
152_0C14 ACTZS CSL Interrupt Register (MSCM_ACTZS_CSLIR) 32 R/W 0000_0000h 7.3.1.2/310
ACTZS CSL Interrupt Overrun Register
152_0C18 32 R/W 0000_0000h 7.3.1.3/313
(MSCM_ACTZS_CSOVR)
7.3.1.1 ACTZS CSL Interrupt Enable Register
(MSCM_ACTZS_CSLIER)
The CSLn interrupt enable register is a 32-bit register containing a bit map of interrupt
enables for CSLn logic reporting access check violations.
As the individual CSLn levels are evaluated for each bus transfer, access violations are
error terminated and the resulting error status flags collected and posted in the
MSCM_CSLIR.
The CSLIER also contains a lock bit (RO) that may be set to disable writes to the
register, preserving the enabled/disabled state of the CSLn interrupts.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 307
Miscellaneous System Control Module (MSCM)
Address: 152_0000h base + C10h offset = 152_0C10h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CIE21
CIE20
CIE19
CIE18
CIE17
CIE16
Lock Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
Reserved
Reserved
CIE15
CIE13
CIE12
CIE10
CIE9 CIE8 Reserved CIE4 CIE3 CIE2 CIE1 CIE0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MSCM_ACTZS_CSLIER field descriptions
Field Description
0 Read-Only. This register bit provides a mechanism to "lock" the configuration state defined by
Lock MSCM_CSLIER. Once asserted, attempted writes to the MSCM_CSLIER register are ignored until the
next system reset clears the flag.
0 writes to the MSCM_CSLIER are allowed
1 writes to the MSCM_CSLIER are ignored
1–9 This field is reserved.
- This field is reserved
10 CSLn Interrupt Enable. This field enables/disables each CSLn access violation alert interrupt.
CIE21
if CIE21= 0, the CSLn access check interrupt is disabled.
if CIE21= 1, the CSLn access check interrupt is enabled.
The individual CIE21 are mapped to QMAN software portal.
11 CSLn Interrupt Enable. This field enables/disables each CSLn access violation alert interrupt.
CIE20
if CIE20= 0, the CSLn access check interrupt is disabled.
if CIE20= 1, the CSLn access check interrupt is enabled.
The individual CIE20 are mapped to USB 3 Controller 3 Register space(CCSR).
12 CSLn Interrupt Enable. This field enables/disables each CSLn access violation alert interrupt.
CIE19
if CIE19= 0, the CSLn access check interrupt is disabled.
if CIE19= 1, the CSLn access check interrupt is enabled.
The individual CIE19 are mapped to USB 3Controller 2 Register space(CCSR).
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
308 NXP Semiconductors
Chapter 7 CSU, OCRAM, and MSCM
MSCM_ACTZS_CSLIER field descriptions (continued)
Field Description
13 CSLn Interrupt Enable. This field enables/disables each CSLn access violation alert interrupt.
CIE18
if CIE18 = 0, the CSLn access check interrupt is disabled.
if CIE18 = 1, the CSLn access check interrupt is enabled.
The individual CIE18 are mapped to OCRAM2 memory space.
14 CSLn Interrupt Enable. This field enables/disables each CSLn access violation alert interrupt.
CIE17
if CIE17 = 0, the CSLn access check interrupt is disabled.
if CIE17 = 1, the CSLn access check interrupt is enabled.
The individual CIE17 are mapped to OCRAM1 memory space.
15 CSLn Interrupt Enable. This field enables/disables each CSLn access violation alert interrupt.
CIE16
if CIE16= 0, the CSLn access check interrupt is disabled.
if CIE16= 1, the CSLn access check interrupt is enabled.
The individual CIE16 are mapped to SATA Register space(CCSR).
16 CSLn Interrupt Enable. This field enables/disables each CSLn access violation alert interrupt.
CIE15
if CIE15= 0, the CSLn access check interrupt is disabled.
if CIE15= 1, the CSLn access check interrupt is enabled.
The individual CIE15 are mapped to PCI Express memory map space.
17 This field is reserved.
- Reserved
18 CSLn Interrupt Enable. This field enables/disables each CSLn access violation alert interrupt.
CIE13
if CIE13= 0, the CSLn access check interrupt is disabled.
if CIE13= 1, the CSLn access check interrupt is enabled.
The individual CIE13 are mapped to GIC Register space (CCSR).
19 CSLn Interrupt Enable. This field enables/disables each CSLn access violation alert interrupt.
CIE12
if CIE12= 0, the CSLn access check interrupt is disabled.
if CIE12= 1, the CSLn access check interrupt is enabled.
The individual CIE12 are mapped to USB3 Controller Register space(CCSR).
20 This field is reserved.
- Reserved
21 CSLn Interrupt Enable. This field enables/disables each CSLn access violation alert interrupt.
CIE10
if CIE10= 0, the CSLn access check interrupt is disabled.
if CIE10= 1, the CSLn access check interrupt is enabled.
The individual CIE10 are mapped to SATA Register space(CCSR).
22 CSLn Interrupt Enable. This field enables/disables each CSLn access violation alert interrupt.
CIE9
if CIE9= 0, the CSLn access check interrupt is disabled.
if CIE9= 1, the CSLn access check interrupt is enabled.
The individual CIE9 are mapped to IFC Memory space.
23 CSLn Interrupt Enable. This field enables/disables each CSLn access violation alert interrupt.
CIE8
if CIE8 = 0, the CSLn access check interrupt is disabled.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 309
Miscellaneous System Control Module (MSCM)
MSCM_ACTZS_CSLIER field descriptions (continued)
Field Description
if CIE8 = 1, the CSLn access check interrupt is enabled.
The individual CIE8 are mapped to Register Configuration Space of all the IP modules in CCSR Space
except PCI Express controllers, SATA controller, USB 3 Controller Register configuration space.
24–26 This field is reserved.
- Reserved
27 CSLn Interrupt Enable. This field enables/disables each CSLn access violation alert interrupt.
CIE4
if CIE4 = 0, the CSLn access check interrupt is disabled.
if CIE4 = 1, the CSLn access check interrupt is enabled.
The individual CIE4 are mapped to QuadSPI memory space.
28 CSLn Interrupt Enable. This field enables/disables each CSLn access violation alert interrupt.
CIE3
if CIE3 = 0, the CSLn access check interrupt is disabled.
if CIE3 = 1, the CSLn access check interrupt is enabled.
The individual CIE3 are mapped to PCI Express controller 2 Register space(CCSR).
29 CSLn Interrupt Enable. This field enables/disables each CSLn access violation alert interrupt.
CIE2
if CIE2 = 0, the CSLn access check interrupt is disabled.
if CIE2 = 1, the CSLn access check interrupt is enabled.
The individual CIE2 are mapped to PCI Express controller 1 Register space(CCSR).
30 CSLn Interrupt Enable. This field enables/disables each CSLn access violation alert interrupt.
CIE1
if CIE1 = 0, the CSLn access check interrupt is disabled.
if CIE1 = 1, the CSLn access check interrupt is enabled.
The individual CIE1 are mapped to PCI Express controller 2 IO Config Space and memory space.
31 CSLn Interrupt Enable. This field enables/disables each CSLn access violation alert interrupt.
CIE0
if CIE0 = 0, the CSLn access check interrupt is disabled.
if CIE0 = 1, the CSLn access check interrupt is enabled.
The individual CIE0 are mapped to PCI Express controller 1 IO Config Space and memory space.
7.3.1.2 ACTZS CSL Interrupt Register (MSCM_ACTZS_CSLIR)
The CSLn interrupt register is a 32-bit register containing a bit map of interrupts for
CSLn logic reporting access check violations.
As the individual CSLn levels are evaluated for each bus transfer, access violations are
error terminated and the resulting error status flags collected and posted in the
MSCM_CSLIR.
The MSCM_CSLIR records all CSLn access violations regardless of the state of the
interrupt enable (MSCM_CSLIER). Accordingly, this register can be used by both
interrupt service routines and/or bus error exception handlers to quickly determine the
source of the CSLn access check violation. Each individual interrupt flag in this register
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
310 NXP Semiconductors
Chapter 7 CSU, OCRAM, and MSCM
is cleared by writing a "1" to it; this would typically be done after the captured fail
address and attribute information is retrieved from the appropriate MSCM_CSF*R
register. Additionally, the clearing of an interrupt flag in this register also clears the
corresponding bit in the MSCM_CSLOVR register and rearms the logic for capturing the
failed access information.
Address: 152_0000h base + C14h offset = 152_0C14h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
Reserved
INT13
INT12
INT10
Reserved INT9 INT8 Reserved INT4 INT3 INT2 INT1 INT0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MSCM_ACTZS_CSLIR field descriptions
Field Description
0–17 This field is reserved.
- This field is reserved
18 CSLn Interrupt Enable. This field enables/disables each CSLn access violation alert interrupt.
INT13
if INT13= 0, the CSLn access check interrupt is disabled.
if INT13 = 1, the CSLn access check interrupt is enabled.
The individual CIE13 are mapped to GIC Register space(CCSR).
19 CSLn Interrupt Enable. This field enables/disables each CSLn access violation alert interrupt.
INT12
if INT12= 0, the CSLn access check interrupt is disabled.
if INT12 = 1, the CSLn access check interrupt is enabled.
The individual CIE12 are mapped to USB 3 Controller Register space(CCSR).
20 This field is reserved.
- Reserved
21 CSLn Interrupt Enable. This field enables/disables each CSLn access violation alert interrupt.
INT10
if INT10 = 0, the CSLn access check interrupt is disabled.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 311
Miscellaneous System Control Module (MSCM)
MSCM_ACTZS_CSLIR field descriptions (continued)
Field Description
if INT10 = 1, the CSLn access check interrupt is enabled.
The individual CIE10 are mapped to SATA register space(CCSR).
22 CSLn Interrupt Enable. This field enables/disables each CSLn access violation alert interrupt.
INT9
if INT9 = 0, the CSLn access check interrupt is disabled.
if INT9 = 1, the CSLn access check interrupt is enabled.
The individual CIE9 are mapped to IFC memory space.
23 CSLn Interrupt Enable. This field enables/disables each CSLn access violation alert interrupt.
INT8
if INT8 = 0, the CSLn access check interrupt is disabled.
if INT8 = 1, the CSLn access check interrupt is enabled.
The individual CIE8 are mapped to Register Configuration Space of all the IP modules in CCSR Space
except PCI Express controllers, , SATA controller, USB 3 Controller Register configuration space.
24–26 This field is reserved.
- Reserved
27 CSLn Interrupt Enable. This field enables/disables each CSLn access violation alert interrupt.
INT4
if INT4 = 0, the CSLn access check interrupt is disabled.
if INT4 = 1, the CSLn access check interrupt is enabled.
The individual CIE4 are mapped to QuadSPI memory space.
28 CSLn Interrupt Enable. This field enables/disables each CSLn access violation alert interrupt.
INT3
if INT3 = 0, the CSLn access check interrupt is disabled.
if INT3 = 1, the CSLn access check interrupt is enabled.
The individual CIE3 are mapped to PCI Express controller 2 Register space (CCSR).
29 CSLn Interrupt Enable. This field enables/disables each CSLn access violation alert interrupt.
INT2
if INT2 = 0, the CSLn access check interrupt is disabled.
if INT2 = 1, the CSLn access check interrupt is enabled.
The individual CIE2 are mapped to PCI Express controller 1 Register space (CCSR).
30 CSLn Interrupt Enable. This field enables/disables each CSLn access violation alert interrupt.
INT1
if INT1 = 0, the CSLn access check interrupt is disabled.
if INT1 = 1, the CSLn access check interrupt is enabled.
The individual CIE1 are mapped to PCI Express controller 2 IO config space and memory space.
31 CSLn Interrupt Enable. This field enables/disables each CSLn access violation alert interrupt.
INT0
if INT0 = 0, the CSLn access check interrupt is disabled.
if INT0 = 1, the CSLn access check interrupt is enabled.
The individual CIE0 are mapped to PCI Express controller 1 IO config space and memory space.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
312 NXP Semiconductors
Chapter 7 CSU, OCRAM, and MSCM
7.3.1.3 ACTZS CSL Interrupt Overrun Register
(MSCM_ACTZS_CSOVR)
The CSLn interrupt overrun register is a 32-bit read-only register containing a bit map of
overrun interrupt conditions for the CSLn logic reporting access check violations.
The overrun condition is simply defined as the detection of another CSLn access check
violation before the previous one has been full processed and cleared. Stated differently,
if a CSLn access check violation is detected and the corresponding MSCM_CSLIR[i] bit
still asserted, the MSCM_CSOVR[i] bit is set.
Additionally, for the slave ACTZS ports using the AXI bus protocol, it is possible to
detect simultaneous access violations on the read and write channels. For this condition,
the CSLn Fail Status Registers (MSCM_CSFARn, MSCM_CSFCRn, MSCM_CSFIRn)
capture the information associated with the write access and set the appropriate overrun
indicator in the MSCM_CSOVR.
Each individual interrupt flags is cleared by writing a "1" to it and this is typically be
done after the captured fail address and attribute information is retrieved from the
appropriate MSCM_CSF*R register. The clearing of an interrupt flag in the
MSCM_CSLIR also clears the corresponding bit in the MSCM_CSOVR register and
rearms the logic for capturing the fail access information.
Address: 152_0000h base + C18h offset = 152_0C18h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
Reserved
OVR13
OVR12
OVR10
OVR9
OVR8
OVR4
OVR3
OVR2
OVR1
OVR0
Reserved Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 313
Miscellaneous System Control Module (MSCM)
MSCM_ACTZS_CSOVR field descriptions
Field Description
0–17 This field is reserved.
- This field is reserved.
18 CSLn Interrupt Enable. This field enables/disables each CSLn access violation alert interrupt.
OVR13
if OVR13= 0, the CSLn access check interrupt is disabled.
if OVR13 = 1, the CSLn access check interrupt is enabled.
The individual CIE13 are mapped to GIC Register space(CCSR).
19 CSLn Interrupt Enable. This field enables/disables each CSLn access violation alert interrupt.
OVR12
if OVR12= 0, the CSLn access check interrupt is disabled.
if OVR12 = 1, the CSLn access check interrupt is enabled.
The individual CIE12 are mapped to USB 3 Controller Register space(CCSR).
20 This field is reserved.
- Reserved
21 CSLn Interrupt Enable. This field enables/disables each CSLn access violation alert interrupt.
OVR10
if OVR10 = 0, the CSLn access check interrupt is disabled.
if OVR10 = 1, the CSLn access check interrupt is enabled.
The individual CIE10 are mapped to SATA Register space(CCSR).
22 CSLn Interrupt Enable. This field enables/disables each CSLn access violation alert interrupt.
OVR9
if OVR9 = 0, the CSLn access check interrupt is disabled.
if OVR9 = 1, the CSLn access check interrupt is enabled.
The individual CIE9 are mapped to IFC Memory space.
23 CSLn Interrupt Enable. This field enables/disables each CSLn access violation alert interrupt.
OVR8
if OVR8 = 0, the CSLn access check interrupt is disabled.
if OVR8 = 1, the CSLn access check interrupt is enabled.
The individual CIE8 are mapped to Register Configuration Space of all the IP modules in CCSR Space
except PCI Express controllers, , SATA controller, USB 3 Controller Register config space.
24–26 This field is reserved.
- Reserved
27 CSLn Interrupt Enable. This field enables/disables each CSLn access violation alert interrupt.
OVR4
if OVR4 = 0, the CSLn access check interrupt is disabled.
if OVR4 = 1, the CSLn access check interrupt is enabled.
The individual CIE4 are mapped to QuadSPI memory space.
28 CSLn Interrupt Enable. This field enables/disables each CSLn access violation alert interrupt.
OVR3
if OVR3 = 0, the CSLn access check interrupt is disabled.
if OVR3 = 1, the CSLn access check interrupt is enabled.
The individual CIE3 are mapped to PCI Express controller 2 Register space(CCSR).
29 CSLn Interrupt Enable. This field enables/disables each CSLn access violation alert interrupt.
OVR2
if OVR2 = 0, the CSLn access check interrupt is disabled.
if OVR2 = 1, the CSLn access check interrupt is enabled.
The individual CIE2 are mapped to PCI Express controller 1 Register space(CCSR).
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
314 NXP Semiconductors
Chapter 7 CSU, OCRAM, and MSCM
MSCM_ACTZS_CSOVR field descriptions (continued)
Field Description
30 CSLn Interrupt Enable. This field enables/disables each CSLn access violation alert interrupt.
OVR1
if OVR1 = 0, the CSLn access check interrupt is disabled.
if OVR1 = 1, the CSLn access check interrupt is enabled.
The individual CIE1 are mapped to PCI Express controller 2 IO config space and memory space.
31 CSLn Interrupt Enable. This field enables/disables each CSLn access violation alert interrupt.
OVR0
if OVR0 = 0, the CSLn access check interrupt is disabled.
if OVR0 = 1, the CSLn access check interrupt is enabled.
The individual CIE0 are mapped to PCI Express controller 1 IO config space and memory space.
7.3.2 ACTZS CSLn Fail Status Capture Registers (Memory Map/
Register Definition)
This section of the MSCM_ACTZS programming model contains an array of four word
(128-bit) data values containing address and attribute information corresponding to CSLn
access check violations. The format of this data structure is identical to the fail status
information captured by the TZASC when they detect a security violation.
When a CSLn access check violation is detected, the bus transaction is error terminated,
the appropriate bit in the MSCM_CSLIR set and the fail address and attribute
information captured in the corresponding data structure. The contents of the captured
fail data is unaffected until the interrupt flag is cleared by writing a 1 to it, at which time,
the capturing of fail information is rearmed.
The LS1 implementation supports n = [0-14] and contains an array of ten 128-bit data
structures and four reserved structures as defined in table below.
Table 7-3. MSCM CSLn Fail Status Capture Registers
Base Offset Source
Address
0xD00 PCI Express controller 1 IO Config Space and
memory space
0xD10 PCI Express controller 2 IO Config Space and
memory space
0xD20 PCI Express controller 1 Register space(CCSR)
0xD30 PCI Express controller 2 Register space(CCSR)
0xD40 QuadSPI memory space
0xD50-0xD70 Reserved
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 315
Miscellaneous System Control Module (MSCM)
Table 7-3. MSCM CSLn Fail Status Capture Registers
(continued)
Base Offset Source
Address
0xD80 Register configuration space of all the IP modules
in CCSR Space except PCI Express controllers,
SATA controller, USB 3 controller register config
space
0xD90 IFC Memory space
0xDA0 SATA Register space(CCSR)
0xDB0 Reserved
0xDC0 USB 3 controller1 Register space(CCSR)
0xDD0-0xDE0 Reserved
0xDF0 PCI Express controller 3 IO Config Space and
memory space
0xE00 PCI Express controller 3 Register space(CCSR)
0xE10 OCRAM1 Memory Space
0xE20 OCRAM2 Memory Space
0xE30 USB Controller 2 CCSR register(CCSR)
0xE40 USB Controller 3 register space(CCSR)
0xE50 QMan/BMan Software portal memory space
All the register accesses are privilege/supervisor.
MSCM memory map
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
ACTZS CSLn Fail Status Address (Low) Register
152_0D00 32 R/W 0000_0000h 7.3.2.1/319
(MSCM_CSFAR0)
ACTZS CSLn Fail Status Control Register
152_0D08 32 R/W 0000_0000h 7.3.2.2/320
(MSCM_CSFCR0)
ACTZS CSLn Fail Status Master ID Register
152_0D0C 32 R/W 0000_0000h 7.3.2.3/321
(MSCM_CSFIR0)
ACTZS CSLn Fail Status Address (Low) Register
152_0D10 32 R/W 0000_0000h 7.3.2.1/319
(MSCM_CSFAR1)
ACTZS CSLn Fail Status Control Register
152_0D18 32 R/W 0000_0000h 7.3.2.2/320
(MSCM_CSFCR1)
ACTZS CSLn Fail Status Master ID Register
152_0D1C 32 R/W 0000_0000h 7.3.2.3/321
(MSCM_CSFIR1)
ACTZS CSLn Fail Status Address (Low) Register
152_0D20 32 R/W 0000_0000h 7.3.2.1/319
(MSCM_CSFAR2)
ACTZS CSLn Fail Status Control Register
152_0D28 32 R/W 0000_0000h 7.3.2.2/320
(MSCM_CSFCR2)
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
316 NXP Semiconductors
Chapter 7 CSU, OCRAM, and MSCM
MSCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
ACTZS CSLn Fail Status Master ID Register
152_0D2C 32 R/W 0000_0000h 7.3.2.3/321
(MSCM_CSFIR2)
ACTZS CSLn Fail Status Address (Low) Register
152_0D30 32 R/W 0000_0000h 7.3.2.1/319
(MSCM_CSFAR3)
ACTZS CSLn Fail Status Control Register
152_0D38 32 R/W 0000_0000h 7.3.2.2/320
(MSCM_CSFCR3)
ACTZS CSLn Fail Status Master ID Register
152_0D3C 32 R/W 0000_0000h 7.3.2.3/321
(MSCM_CSFIR3)
ACTZS CSLn Fail Status Address (Low) Register
152_0D40 32 R/W 0000_0000h 7.3.2.1/319
(MSCM_CSFAR4)
ACTZS CSLn Fail Status Control Register
152_0D48 32 R/W 0000_0000h 7.3.2.2/320
(MSCM_CSFCR4)
ACTZS CSLn Fail Status Master ID Register
152_0D4C 32 R/W 0000_0000h 7.3.2.3/321
(MSCM_CSFIR4)
ACTZS CSLn Fail Status Address (Low) Register
152_0D80 32 R/W 0000_0000h 7.3.2.4/322
(MSCM_CSFAR8)
ACTZS CSLn Fail Status Control Register
152_0D88 32 R/W 0000_0000h 7.3.2.5/323
(MSCM_CSFCR8)
ACTZS CSLn Fail Status Master ID Register
152_0D8C 32 R/W 0000_0000h 7.3.2.6/324
(MSCM_CSFIR8)
ACTZS CSLn Fail Status Address (Low) Register
152_0D90 32 R/W 0000_0000h 7.3.2.4/322
(MSCM_CSFAR9)
ACTZS CSLn Fail Status Control Register
152_0D98 32 R/W 0000_0000h 7.3.2.5/323
(MSCM_CSFCR9)
ACTZS CSLn Fail Status Master ID Register
152_0D9C 32 R/W 0000_0000h 7.3.2.6/324
(MSCM_CSFIR9)
ACTZS CSLn Fail Status Address (Low) Register
152_0DA0 32 R/W 0000_0000h 7.3.2.4/322
(MSCM_CSFAR10)
ACTZS CSLn Fail Status Control Register
152_0DA8 32 R/W 0000_0000h 7.3.2.5/323
(MSCM_CSFCR10)
ACTZS CSLn Fail Status Master ID Register
152_0DAC 32 R/W 0000_0000h 7.3.2.6/324
(MSCM_CSFIR10)
ACTZS CSLn Fail Status Address (Low) Register
152_0DC0 32 R/W 0000_0000h 7.3.2.7/325
(MSCM_CSFAR12)
ACTZS CSLn Fail Status Control Register
152_0DC8 32 R/W 0000_0000h 7.3.2.8/326
(MSCM_CSFCR12)
ACTZS CSLn Fail Status Master ID Register
152_0DCC 32 R/W 0000_0000h 7.3.2.9/327
(MSCM_CSFIR12)
ACTZS CSLn Fail Status Address (Low) Register 7.3.2.10/
152_0DF0 32 R/W 0000_0000h
(MSCM_CSFAR14) 328
ACTZS CSLn Fail Status Master ID Register 7.3.2.11/
152_0DF8 32 R/W 0000_0000h
(MSCM_CSFIR14) 329
ACTZS CSLn Fail Status Control Register 7.3.2.12/
152_0DFC 32 R/W 0000_0000h
(MSCM_CSFCR14) 329
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 317
Miscellaneous System Control Module (MSCM)
MSCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
ACTZS CSLn Fail Status Address (Low) Register 7.3.2.10/
152_0E00 32 R/W 0000_0000h
(MSCM_CSFAR15) 328
ACTZS CSLn Fail Status Master ID Register 7.3.2.11/
152_0E08 32 R/W 0000_0000h
(MSCM_CSFIR15) 329
ACTZS CSLn Fail Status Control Register 7.3.2.12/
152_0E0C 32 R/W 0000_0000h
(MSCM_CSFCR15) 329
ACTZS CSLn Fail Status Address (Low) Register 7.3.2.10/
152_0E10 32 R/W 0000_0000h
(MSCM_CSFAR16) 328
ACTZS CSLn Fail Status Master ID Register 7.3.2.11/
152_0E18 32 R/W 0000_0000h
(MSCM_CSFIR16) 329
ACTZS CSLn Fail Status Control Register 7.3.2.12/
152_0E1C 32 R/W 0000_0000h
(MSCM_CSFCR16) 329
ACTZS CSLn Fail Status Address (Low) Register 7.3.2.10/
152_0E20 32 R/W 0000_0000h
(MSCM_CSFAR17) 328
ACTZS CSLn Fail Status Master ID Register 7.3.2.11/
152_0E28 32 R/W 0000_0000h
(MSCM_CSFIR17) 329
ACTZS CSLn Fail Status Control Register 7.3.2.12/
152_0E2C 32 R/W 0000_0000h
(MSCM_CSFCR17) 329
ACTZS CSLn Fail Status Address (Low) Register 7.3.2.10/
152_0E30 32 R/W 0000_0000h
(MSCM_CSFAR18) 328
ACTZS CSLn Fail Status Master ID Register 7.3.2.11/
152_0E38 32 R/W 0000_0000h
(MSCM_CSFIR18) 329
ACTZS CSLn Fail Status Control Register 7.3.2.12/
152_0E3C 32 R/W 0000_0000h
(MSCM_CSFCR18) 329
ACTZS CSLn Fail Status Address (Low) Register 7.3.2.10/
152_0E40 32 R/W 0000_0000h
(MSCM_CSFAR19) 328
ACTZS CSLn Fail Status Master ID Register 7.3.2.11/
152_0E48 32 R/W 0000_0000h
(MSCM_CSFIR19) 329
ACTZS CSLn Fail Status Control Register 7.3.2.12/
152_0E4C 32 R/W 0000_0000h
(MSCM_CSFCR19) 329
ACTZS CSLn Fail Status Address (Low) Register 7.3.2.10/
152_0E50 32 R/W 0000_0000h
(MSCM_CSFAR20) 328
ACTZS CSLn Fail Status Master ID Register 7.3.2.11/
152_0E58 32 R/W 0000_0000h
(MSCM_CSFIR20) 329
ACTZS CSLn Fail Status Control Register 7.3.2.12/
152_0E5C 32 R/W 0000_0000h
(MSCM_CSFCR20) 329
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
318 NXP Semiconductors
Chapter 7 CSU, OCRAM, and MSCM
7.3.2.1 ACTZS CSLn Fail Status Address (Low) Register
(MSCM_CSFARn)
The CSFARn is a 32-bit read-only register for capturing the low-order 32 bits of the 40-
bit physical address of the last captured access check violation detected by the CSLn
logic. When the CSLn logic detects an access violation, the address and attributes
associated with the memory reference are loaded into the CSFARn, CSFCRn and
CSFIRn registers, and the appropriate flag in the CSLn interrupt register (CSLIR) is
asserted.
For the slave ACTZS ports using the AXI bus protocol, it is possible to detect
simultaneous access violations on the read and write channels. For this condition, the
CSLn fail status registers (MSCM_CSFARn, MSCM_CSFCRn, MSCM_CSFIRn)
capture the information associated with the write access and additionally set the
appropriate overrun indicator in the MSCM_CSOVR.
The contents of the MSCM_CSFARn is unaffected until the corresponding
MSCM_CSLIR interrupt flag is cleared by writing a 1 to it, at which time, the capturing
of fail information is rearmed.
Attempted privileged mode writes are ignored.
NOTE
The next sequential word at offset address 0xD04 + 16*n is
reserved for systems where the address space is larger than 4
Gbytes.
Address: 152_0000h base + D00h offset + (16d × i), where i=0d to 4d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
FAD
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MSCM_CSFARn field descriptions
Field Description
0–31 CSLn Fail Address. This read-only field specifies the system address from the last captured CSLn access
FAD check violation.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 319
Miscellaneous System Control Module (MSCM)
7.3.2.2 ACTZS CSLn Fail Status Control Register (MSCM_CSFCRn)
The CSFCRn is a 32-bit read-only register for capturing specific attribute bits of the last
captured access check violation detected by the CSLn logic. When the CSLn logic detects
an access violation, the address and attributes associated with the memory reference are
loaded into the CSFARn, CSFCRn and CSFIRn registers, and the appropriate flag in the
CSLn Interrupt Register (CSLIR) is asserted.
For the slave ACTZS ports using the AXI bus protocol, it is possible to detect
simultaneous access violations on the read and write channels. For this condition, the
CSLn Fail Status Registers (MSCM_CSFARn, MSCM_CSFCRn, MSCM_CSFIRn)
capture the information associated with the write access and additionally set the
appropriate overrun indicator in the MSCM_CSOVR.
The contents of the MSCM_CSFCRn is unaffected until the corresponding
MSCM_CSLIR interrupt flag is cleared by writing a 1 to it, at which time, the capturing
of fail information is rearmed.
Attempted privileged mode writes are ignored.
Address: 152_0000h base + D08h offset + (16d × i), where i=0d to 4d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
W
Reserved FWT Reserved FNS FPR Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MSCM_CSFCRn field descriptions
Field Description
0–6 This field is reserved.
- Reserved
7 CSLn Fail Write. This read-only field specifies the read/write attribute from the last captured CSLn access
FWT check violation.
if FWT = 0, then the last captured CSLn access check violation was a read.
if FWT = 1, then the last captured CSLn access check violation was a write.
8–9 This field is reserved.
- Reserved
10 CSLn Fail Nonsecure. This read-only field specifies the secure/nonsecure attribute from the last captured
FNS CSLn access check violation.
if FNS = 0, the last captured CSLn access check violation was a secure access.
if FNS = 1, the last captured CSLn access check violation was a nonsecure access.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
320 NXP Semiconductors
Chapter 7 CSU, OCRAM, and MSCM
MSCM_CSFCRn field descriptions (continued)
Field Description
11 CSLn Fail Privileged. This read-only field specifies the user/privileged attribute from the last captured
FPR CSLn access check violation.
if FPR = 0, the last captured CSLn access check violation was a user mode access.
if FPR = 1, the last captured CSLn access check violation was a privileged access.
12–31 This field is reserved.
- Reserved
7.3.2.3 ACTZS CSLn Fail Status Master ID Register (MSCM_CSFIRn)
The CSFIRn is a 32-bit read-only register for capturing the 4 LSB bits of the AXI ID
attribute of the last captured access check violation detected by the CSLn logic. When the
CSLn logic detects an access violation, the address and attributes associated with the
memory reference are loaded into the CSFARn, CSFCRn and CSFIRn registers, and the
appropriate flag in the CSLn interrupt register (CSLIR) is asserted.
For the slave ACTZS ports using the AXI bus protocol, it is possible to detect
simultaneous access violations on the read and write channels. For this condition, the
CSLn fail status registers (MSCM_CSFARn, MSCM_CSFCRn, MSCM_CSFIRn)
capture the information associated with the write access and additionally set the
appropriate overrun indicator in the MSCM_CSOVR.
The contents of the MSCM_CSFIRn is unaffected until the corresponding
MSCM_CSLIR interrupt flag is cleared by writing a 1 to it, at which time, the capturing
of fail information is rearmed.
Attempted privileged mode writes are ignored.
Address: 152_0000h base + D0Ch offset + (16d × i), where i=0d to 4d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
Reserved FMID
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MSCM_CSFIRn field descriptions
Field Description
0–26 This field is reserved.
- Reserved
27–31 CSLn Fail Master ID. This read-only field specifies the master ID from the last captured CSLn access
FMID check violation.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 321
Miscellaneous System Control Module (MSCM)
7.3.2.4 ACTZS CSLn Fail Status Address (Low) Register
(MSCM_CSFARn)
The CSFARn is a 32-bit read-only register for capturing the low-order 32 bits of the 40-
bit physical address of the last captured access check violation detected by the CSLn
logic. When the CSLn logic detects an access violation, the address and attributes
associated with the memory reference are loaded into the CSFARn, CSFCRn and
CSFIRn registers, and the appropriate flag in the CSLn interrupt register (CSLIR) is
asserted.
For the slave ACTZS ports using the AXI bus protocol, it is possible to detect
simultaneous access violations on the read and write channels. For this condition, the
CSLn fail status registers (MSCM_CSFARn, MSCM_CSFCRn, MSCM_CSFIRn)
capture the information associated with the write access and additionally set the
appropriate overrun indicator in the MSCM_CSOVR.
The contents of the MSCM_CSFARn is unaffected until the corresponding
MSCM_CSLIR interrupt flag is cleared by writing a 1 to it, at which time, the capturing
of fail information is rearmed.
Attempted privileged mode writes are ignored.
NOTE
The next sequential word at offset address 0xD04 + 16*n is
reserved for systems where the address space is larger than 4
Gbytes.
Address: 152_0000h base + D80h offset + (16d × i), where i=0d to 2d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
FAD
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MSCM_CSFARn field descriptions
Field Description
0–31 CSLn Fail Address. This read-only field specifies the system address from the last captured CSLn access
FAD check violation.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
322 NXP Semiconductors
Chapter 7 CSU, OCRAM, and MSCM
7.3.2.5 ACTZS CSLn Fail Status Control Register (MSCM_CSFCRn)
The CSFCRn is a 32-bit read-only register for capturing specific attribute bits of the last
captured access check violation detected by the CSLn logic. When the CSLn logic detects
an access violation, the address and attributes associated with the memory reference are
loaded into the CSFARn, CSFCRn and CSFIRn registers, and the appropriate flag in the
CSLn Interrupt Register (CSLIR) is asserted.
For the slave ACTZS ports using the AXI bus protocol, it is possible to detect
simultaneous access violations on the read and write channels. For this condition, the
CSLn Fail Status Registers (MSCM_CSFARn, MSCM_CSFCRn, MSCM_CSFIRn)
capture the information associated with the write access and additionally set the
appropriate overrun indicator in the MSCM_CSOVR.
The contents of the MSCM_CSFCRn is unaffected until the corresponding
MSCM_CSLIR interrupt flag is cleared by writing a 1 to it, at which time, the capturing
of fail information is rearmed.
Attempted privileged mode writes are ignored.
Address: 152_0000h base + D88h offset + (16d × i), where i=0d to 2d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
W
Reserved FWT Reserved FNS FPR Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MSCM_CSFCRn field descriptions
Field Description
0–6 This field is reserved.
- Reserved
7 CSLn Fail Write. This read-only field specifies the read/write attribute from the last captured CSLn access
FWT check violation.
if FWT = 0, then the last captured CSLn access check violation was a read.
if FWT = 1, then the last captured CSLn access check violation was a write.
8–9 This field is reserved.
- Reserved
10 CSLn Fail Nonsecure. This read-only field specifies the secure/nonsecure attribute from the last captured
FNS CSLn access check violation.
if FNS = 0, the last captured CSLn access check violation was a secure access.
if FNS = 1, the last captured CSLn access check violation was a nonsecure access.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 323
Miscellaneous System Control Module (MSCM)
MSCM_CSFCRn field descriptions (continued)
Field Description
11 CSLn Fail Privileged. This read-only field specifies the user/privileged attribute from the last captured
FPR CSLn access check violation.
if FPR = 0, the last captured CSLn access check violation was a user mode access.
if FPR = 1, the last captured CSLn access check violation was a privileged access.
12–31 This field is reserved.
- Reserved
7.3.2.6 ACTZS CSLn Fail Status Master ID Register (MSCM_CSFIRn)
The CSFIRn is a 32-bit read-only register for capturing the 4 LSB bits of the AXI ID
attribute of the last captured access check violation detected by the CSLn logic. When the
CSLn logic detects an access violation, the address and attributes associated with the
memory reference are loaded into the CSFARn, CSFCRn and CSFIRn registers, and the
appropriate flag in the CSLn interrupt register (CSLIR) is asserted.
For the slave ACTZS ports using the AXI bus protocol, it is possible to detect
simultaneous access violations on the read and write channels. For this condition, the
CSLn fail status registers (MSCM_CSFARn, MSCM_CSFCRn, MSCM_CSFIRn)
capture the information associated with the write access and additionally set the
appropriate overrun indicator in the MSCM_CSOVR.
The contents of the MSCM_CSFIRn is unaffected until the corresponding
MSCM_CSLIR interrupt flag is cleared by writing a 1 to it, at which time, the capturing
of fail information is rearmed.
Attempted privileged mode writes are ignored.
Address: 152_0000h base + D8Ch offset + (16d × i), where i=0d to 2d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
Reserved FMID
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MSCM_CSFIRn field descriptions
Field Description
0–26 This field is reserved.
- Reserved
27–31 CSLn Fail Master ID. This read-only field specifies the master ID from the last captured CSLn access
FMID check violation.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
324 NXP Semiconductors
Chapter 7 CSU, OCRAM, and MSCM
7.3.2.7 ACTZS CSLn Fail Status Address (Low) Register
(MSCM_CSFARn)
The CSFARn is a 32-bit read-only register for capturing the low-order 32 bits of the 40-
bit physical address of the last captured access check violation detected by the CSLn
logic. When the CSLn logic detects an access violation, the address and attributes
associated with the memory reference are loaded into the CSFARn, CSFCRn and
CSFIRn registers, and the appropriate flag in the CSLn interrupt register (CSLIR) is
asserted.
For the slave ACTZS ports using the AXI bus protocol, it is possible to detect
simultaneous access violations on the read and write channels. For this condition, the
CSLn fail status registers (MSCM_CSFARn, MSCM_CSFCRn, MSCM_CSFIRn)
capture the information associated with the write access and additionally set the
appropriate overrun indicator in the MSCM_CSOVR.
The contents of the MSCM_CSFARn is unaffected until the corresponding
MSCM_CSLIR interrupt flag is cleared by writing a 1 to it, at which time, the capturing
of fail information is rearmed.
Attempted privileged mode writes are ignored.
NOTE
The next sequential word at offset address 0xD04 + 16*n is
reserved for systems where the address space is larger than 4
Gbytes.
Address: 152_0000h base + DC0h offset + (16d × i), where i=0d to 0d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
FAD
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MSCM_CSFARn field descriptions
Field Description
0–31 CSLn Fail Address. This read-only field specifies the system address from the last captured CSLn access
FAD check violation.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 325
Miscellaneous System Control Module (MSCM)
7.3.2.8 ACTZS CSLn Fail Status Control Register (MSCM_CSFCRn)
The CSFCRn is a 32-bit read-only register for capturing specific attribute bits of the last
captured access check violation detected by the CSLn logic. When the CSLn logic detects
an access violation, the address and attributes associated with the memory reference are
loaded into the CSFARn, CSFCRn and CSFIRn registers, and the appropriate flag in the
CSLn Interrupt Register (CSLIR) is asserted.
For the slave ACTZS ports using the AXI bus protocol, it is possible to detect
simultaneous access violations on the read and write channels. For this condition, the
CSLn Fail Status Registers (MSCM_CSFARn, MSCM_CSFCRn, MSCM_CSFIRn)
capture the information associated with the write access and additionally set the
appropriate overrun indicator in the MSCM_CSOVR.
The contents of the MSCM_CSFCRn is unaffected until the corresponding
MSCM_CSLIR interrupt flag is cleared by writing a 1 to it, at which time, the capturing
of fail information is rearmed.
Attempted privileged mode writes are ignored.
Address: 152_0000h base + DC8h offset + (16d × i), where i=0d to 0d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
W
Reserved FWT Reserved FNS FPR Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MSCM_CSFCRn field descriptions
Field Description
0–6 This field is reserved.
- Reserved
7 CSLn Fail Write. This read-only field specifies the read/write attribute from the last captured CSLn access
FWT check violation.
if FWT = 0, then the last captured CSLn access check violation was a read.
if FWT = 1, then the last captured CSLn access check violation was a write.
8–9 This field is reserved.
- Reserved
10 CSLn Fail Nonsecure. This read-only field specifies the secure/nonsecure attribute from the last captured
FNS CSLn access check violation.
if FNS = 0, the last captured CSLn access check violation was a secure access.
if FNS = 1, the last captured CSLn access check violation was a nonsecure access.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
326 NXP Semiconductors
Chapter 7 CSU, OCRAM, and MSCM
MSCM_CSFCRn field descriptions (continued)
Field Description
11 CSLn Fail Privileged. This read-only field specifies the user/privileged attribute from the last captured
FPR CSLn access check violation.
if FPR = 0, the last captured CSLn access check violation was a user mode access.
if FPR = 1, the last captured CSLn access check violation was a privileged access.
12–31 This field is reserved.
- Reserved
7.3.2.9 ACTZS CSLn Fail Status Master ID Register (MSCM_CSFIRn)
The CSFIRn is a 32-bit read-only register for capturing the 4 LSB bits of the AXI ID
attribute of the last captured access check violation detected by the CSLn logic. When the
CSLn logic detects an access violation, the address and attributes associated with the
memory reference are loaded into the CSFARn, CSFCRn and CSFIRn registers, and the
appropriate flag in the CSLn interrupt register (CSLIR) is asserted.
For the slave ACTZS ports using the AXI bus protocol, it is possible to detect
simultaneous access violations on the read and write channels. For this condition, the
CSLn fail status registers (MSCM_CSFARn, MSCM_CSFCRn, MSCM_CSFIRn)
capture the information associated with the write access and additionally set the
appropriate overrun indicator in the MSCM_CSOVR.
The contents of the MSCM_CSFIRn is unaffected until the corresponding
MSCM_CSLIR interrupt flag is cleared by writing a 1 to it, at which time, the capturing
of fail information is rearmed.
Attempted privileged mode writes are ignored.
Address: 152_0000h base + DCCh offset + (16d × i), where i=0d to 0d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
Reserved FMID
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MSCM_CSFIRn field descriptions
Field Description
0–26 This field is reserved.
- Reserved
27–31 CSLn Fail Master ID. This read-only field specifies the master ID from the last captured CSLn access
FMID check violation.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 327
Miscellaneous System Control Module (MSCM)
7.3.2.10 ACTZS CSLn Fail Status Address (Low) Register
(MSCM_CSFARn)
The CSFARn is a 32-bit read-only register for capturing the low-order 32 bits of the 40-
bit physical address last captured access check violation detected by the CSLn logic.
When the CSLn logic detects an access violation, the address and attributes associated
with the memory reference are loaded into the CSFARn, CSFCRn and CSFIRn registers,
and the appropriate flag in the CSLn interrupt register (CSLIR) is asserted.
For the slave ACTZS ports using the AXI bus protocol, it is possible to detect
simultaneous access violations on the read and write channels. For this condition, the
CSLn fail status registers (MSCM_CSFARn, MSCM_CSFCRn, MSCM_CSFIRn)
capture the information associated with the write access and additionally set the
appropriate overrun indicator in the MSCM_CSOVR.
The contents of the MSCM_CSFARn is unaffected until the corresponding
MSCM_CSLIR interrupt flag is cleared by writing a 1 to it, at which time, the capturing
of fail information is rearmed.
Attempted privileged mode writes are ignored.
NOTE
The next sequential word at offset address 0xD04 + 16*n is
reserved for systems where the address space is larger than 4
Gbytes.
Address: 152_0000h base + DF0h offset + (16d × i), where i=0d to 6d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
FAD
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MSCM_CSFARn field descriptions
Field Description
0–31 CSLn Fail Address. This read-only field specifies the system address from the last captured CSLn access
FAD check violation.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
328 NXP Semiconductors
Chapter 7 CSU, OCRAM, and MSCM
7.3.2.11 ACTZS CSLn Fail Status Master ID Register (MSCM_CSFIRn)
The CSFIRn is a 32-bit read-only register for capturing the 4 LSB bits of the AXI ID
attribute of the last captured access check violation detected by the CSLn logic. When the
CSLn logic detects an access violation, the address and attributes associated with the
memory reference are loaded into the CSFARn, CSFCRn and CSFIRn registers, and the
appropriate flag in the CSLn interrupt register (CSLIR) is asserted.
For the slave ACTZS ports using the AXI bus protocol, it is possible to detect
simultaneous access violations on the read and write channels. For this condition, the
CSLn fail status registers (MSCM_CSFARn, MSCM_CSFCRn, MSCM_CSFIRn)
capture the information associated with the write access and additionally set the
appropriate overrun indicator in the MSCM_CSOVR.
The contents of the MSCM_CSFIRn is unaffected until the corresponding
MSCM_CSLIR interrupt flag is cleared by writing a 1 to it, at which time, the capturing
of fail information is rearmed.
Attempted privileged mode writes are ignored.
Address: 152_0000h base + DF8h offset + (16d × i), where i=0d to 6d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
Reserved FMID
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MSCM_CSFIRn field descriptions
Field Description
0–26 This field is reserved.
- Reserved
27–31 CSLn Fail Master ID. This read-only field specifies the master ID from the last captured CSLn access
FMID check violation.
7.3.2.12 ACTZS CSLn Fail Status Control Register (MSCM_CSFCRn)
The CSFCRn is a 32-bit read-only register for capturing specific attribute bits of the last
captured access check violation detected by the CSLn logic. When the CSLn logic detects
an access violation, the address and attributes associated with the memory reference are
loaded into the CSFARn, CSFCRn and CSFIRn registers, and the appropriate flag in the
CSLn Interrupt Register (CSLIR) is asserted.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 329
Miscellaneous System Control Module (MSCM)
For the slave ACTZS ports using the AXI bus protocol, it is possible to detect
simultaneous access violations on the read and write channels. For this condition, the
CSLn Fail Status Registers (MSCM_CSFARn, MSCM_CSFCRn, MSCM_CSFIRn)
capture the information associated with the write access and additionally set the
appropriate overrun indicator in the MSCM_CSOVR.
The contents of the MSCM_CSFCRn is unaffected until the corresponding
MSCM_CSLIR interrupt flag is cleared by writing a 1 to it, at which time, the capturing
of fail information is rearmed.
Attempted privileged mode writes are ignored.
Address: 152_0000h base + DFCh offset + (16d × i), where i=0d to 6d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
W
Reserved FWT Reserved FNS FPR Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MSCM_CSFCRn field descriptions
Field Description
0–6 This field is reserved.
- Reserved
7 CSLn Fail Write. This read-only field specifies the read/write attribute from the last captured CSLn access
FWT check violation.
if FWT = 0, then the last captured CSLn access check violation was a read.
if FWT = 1, then the last captured CSLn access check violation was a write.
8–9 This field is reserved.
- Reserved
10 CSLn Fail Nonsecure. This read-only field specifies the secure/nonsecure attribute from the last captured
FNS CSLn access check violation.
if FNS = 0, the last captured CSLn access check violation was a secure access.
if FNS = 1, the last captured CSLn access check violation was a nonsecure access.
11 CSLn Fail Privileged. This read-only field specifies the user/privileged attribute from the last captured
FPR CSLn access check violation.
if FPR = 0, the last captured CSLn access check violation was a user mode access.
if FPR = 1, the last captured CSLn access check violation was a privileged access.
12–31 This field is reserved.
- Reserved
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
330 NXP Semiconductors
Chapter 8
System Counter
8.1 System counter
The system counter implements the Arm Generic Timer requirements mentioned in the
chapter "System Level Implementation of the Generic Timer" of Armv8, for Armv8-A
architecture profile.
8.1.1 Secure system counter memory map/register definition
This table shows the register list of CCSR access control unit.
Secure_system_counter memory map
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
2B0_0000 Control register (Secure_system_counter_CNTCR) 32 R/W 0000_0000h 8.1.1.1/332
LSB of counter count value register
2B0_0008 32 R/W 0000_0000h 8.1.1.2/332
(Secure_system_counter_CNTCV1)
MSB of counter count value register
2B0_000C 32 R/W 0000_0000h 8.1.1.3/333
(Secure_system_counter_CNTCV2)
Counter frequency mode table base frequency register
2B0_0020 32 R/W 00BE_BC20h 8.1.1.4/333
(Secure_system_counter_CNTFID0)
Counter frequency mode table end frequency register
2B0_0024 32 R/W 0000_0000h 8.1.1.5/334
(Secure_system_counter_CNTFID1)
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 331
System counter
8.1.1.1 Control register (Secure_system_counter_CNTCR)
This register enables the counter.
Address: 2B0_0000h base + 0h offset = 2B0_0000h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
W
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
Reserved EN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Secure_system_counter_CNTCR field descriptions
Field Description
0–30 This field is reserved.
-
31 Enables the counter
EN
0 System counter disabled.
1 System counter enabled.
8.1.1.2 LSB of counter count value register
(Secure_system_counter_CNTCV1)
This register indicates the current LSB count value of the 64-bit counter. The register is
writable only by secure writes. When the counter is enabled, the effect of writing the
register is unpredictable.
Address: 2B0_0000h base + 8h offset = 2B0_0008h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
CNCTV1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Secure_system_counter_CNTCV1 field descriptions
Field Description
0–31 Counter count value bits CNCTV[31:0]. The EN bit must be cleared before writing to this bits, otherwise
CNCTV1 the effect of the write is unpredictable. Writes to these registers are rare. In a system that uses security,
these registers are writable only by secure writes.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
332 NXP Semiconductors
Chapter 8 System Counter
Secure_system_counter_CNTCV1 field descriptions (continued)
Field Description
0 System counter disabled.
1 System counter enabled.
8.1.1.3 MSB of counter count value register
(Secure_system_counter_CNTCV2)
This register indicates the current MSB count value of the 64-bit counter. The register is
writable only by secure writes. When the counter is enabled, the effect of writing the
register is unpredictable.
Address: 2B0_0000h base + Ch offset = 2B0_000Ch
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
CNCTV2
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Secure_system_counter_CNTCV2 field descriptions
Field Description
0–31 Counter Count Value bits CNCTV[63:32]. The EN bit must be cleared before writing to this bits, otherwise
CNCTV2 the effect of the write is UNPREDICTABLE. Writes to these registers are rare. In a system that uses
security, these registers are writable only by Secure writes.
8.1.1.4 Counter frequency mode table base frequency register
(Secure_system_counter_CNTFID0)
This register specifies the base frequency of the system counter. The system counter
always works with SYS_REF_CLK/4 frequency clock. The initial value of this register is
25 MHz (100 MHz/4). The software needs to update this register initially to reflect the
correct frequency based on system reference clock.
Address: 2B0_0000h base + 20h offset = 2B0_0020h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
CNT_BASE
Reset 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 0 1 0 1 1 1 1 0 0 0 0 1 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 333
System counter
Secure_system_counter_CNTFID0 field descriptions
Field Description
0–31 System counter base frequency. Holds the clock frequency of the counter.
CNT_BASE
Initial value is set to 25 MHz that corresponds to 100 MHz SYSCLK frequency.
8.1.1.5 Counter frequency mode table end frequency register
(Secure_system_counter_CNTFID1)
This register specifies the end frequency of the system counter.
Address: 2B0_0000h base + 24h offset = 2B0_0024h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
END_MARKER
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Secure_system_counter_CNTFID1 field descriptions
Field Description
0–31 System counter END frequency. Indicates the end of frequency mode table.
END_MARKER
8.1.2 Non-Secure system counter memory map/register
definition
The non-secure counter memory map provides register list for the non-secure world to
access the counter values.
Non_Secure_SYS_Counter memory map
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
LSB of Counter Count Value
2B1_0000 32 R 0000_0000h 8.1.2.1/335
(Non_Secure_SYS_Counter_CNCTV_RO1)
MSB of counter count value register
2B1_0004 32 R 0000_0000h 8.1.2.2/335
(Non_Secure_SYS_Counter_CNCTV2_RO2)
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
334 NXP Semiconductors
Chapter 8 System Counter
8.1.2.1 LSB of Counter Count Value
(Non_Secure_SYS_Counter_CNCTV_RO1)
This register is read-only and contains the current LSB count value of the 64-bit counter.
Address: 2B1_0000h base + 0h offset = 2B1_0000h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R CNCTV_RO1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Non_Secure_SYS_Counter_CNCTV_RO1 field descriptions
Field Description
0–31 Counter count value bits CNCTV[31:0]
CNCTV_RO1
8.1.2.2 MSB of counter count value register
(Non_Secure_SYS_Counter_CNCTV2_RO2)
The register is read-only and contains the current MSB count value of the 64-bit counter.
Address: 2B1_0000h base + 4h offset = 2B1_0004h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R CNCTV_RO2
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Non_Secure_SYS_Counter_CNCTV2_RO2 field descriptions
Field Description
0–31 Counter count value bits CNCTV[63:32]
CNCTV_RO2
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 335
System counter
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
336 NXP Semiconductors
Chapter 9
Interconnect Fabric
9.1 Introduction
The interconnect fabric has QoS (quality of service) regulators enabled for data traffic
originating from PCI express masters and qDMA master. The various options of QoS are
bypass, fixed, limiter, and regulator modes. See Figure 10-1 for the connectivity of
interconnect fabric with PCI Express, qDMA, and CCI-400.
9.2 QoS generators
The initiators such as PCI express masters and qDMA can optionally be configured with
one of three types of QoS generators: fixed, limiter, and regulator. The functionality of
each type of QoS generator is a superset of the previous and if configured so can be
programmed under software control to behave like the subset type of generator. When
software switches the mode of a QoS generator, bandwidth counters are reset.
9.2.1 Fixed QoS generator
A fixed QoS generator assigns an urgency to each packet. The urgency can be different
for read and for write transactions. It can be configured so that the fixed read and write
urgencies are programmable by software.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 337
IF Memory Map/Register Definition
9.2.2 Limiter QoS generator
A limiter is an access control mechanism. It monitors the bandwidth of request packets
sent by the initiators, by accumulating the data length of each packet and decrementing
the accumulator at a specific rate. Read and write requests are accumulated together. The
accumulator is decremented at an interval determined by the saturation parameter.
Thereby, the accumulator represents the bandwidth within a certain sliding time window.
9.2.3 Regulator QoS generator
The regulator QoS generator modulates the priority value between two run-time
programmable values whenever a run-time programmable bandwidth ceiling is exceeded.
Socket transactions subject to such regulation are transmitted with a demoted level of
urgency, instead of being stalled as in limiter mode.
9.3 IF Memory Map/Register Definition
This table shows the register memory map for the interconnect.
IF memory map
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
2CA_2688 Priority qdma (IF_prio_qdma_read_only) 32 R/W 8000_0100h 9.3.1/339
2CA_268C Mode qdma (IF_mod_qdma_read_only) 32 R/W 0000_0002h 9.3.2/340
2CA_2690 Bandwidth qdma (IF_bw_qdma_read_only) 32 R/W 0000_0005h 9.3.3/340
2CA_2694 Saturation qdma (IF_sat_qdma_read_only) 32 R/W 0000_0100h 9.3.4/341
2CA_2698 ExtControl qdma (IF_ext_cntrl_qdma_read_only) 32 R/W 0000_0000h 9.3.5/341
2CA_2708 Priority qdma (IF_prio_qdma_write_only) 32 R/W 8000_0100h 9.3.6/342
2CA_270C Mode qdma (IF_mod_qdma_write_only) 32 R/W 0000_0002h 9.3.7/342
2CA_2710 Bandwidth qdma (IF_bw_qdma_write_only) 32 R/W 0000_0005h 9.3.8/343
2CA_2714 Saturation qdma (IF_sat_qdma_write_only) 32 R/W 0000_0100h 9.3.9/343
2CA_2718 ExtControl qdma (IF_ext_cntrl_qdma_write_only) 32 R/W 0000_0000h 9.3.10/344
2CA_2788 Priority pex (IF_prio_pex_read_only) 32 R/W 8000_0100h 9.3.11/344
2CA_278C Mode_pex (IF_mod_pex_read_only) 32 R/W 0000_0002h 9.3.12/345
2CA_2790 Bandwidth_pex (IF_bw_pex_read_only) 32 R/W 0000_0005h 9.3.13/346
2CA_2794 Saturation_pex (IF_sat_pex_read_only) 32 R/W 0000_0100h 9.3.14/346
2CA_2798 ExtControl_pex_ro (IF_ext_cntrl_pex_ro) 32 R/W 0000_0000h 9.3.15/347
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
338 NXP Semiconductors
Chapter 9 Interconnect Fabric
IF memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
2CA_2808 Priority_pex (IF_prio_pex_write_only) 32 R/W 8000_0100h 9.3.16/347
2CA_280C Mode_pex (IF_mod_pex_write_only) 32 R/W 0000_0002h 9.3.17/348
2CA_2810 Bandwidth_pex (IF_bw_smmu_pex_write_only) 32 R/W 0000_0005h 9.3.18/349
2CA_2814 Saturation_pex (IF_sat_pex_write_only) 32 R/W 0000_0100h 9.3.19/349
2CA_2818 ExtControl_pex_wo (IF_ext_cntrl_pex_write_only) 32 R/W 0000_0000h 9.3.20/350
9.3.1 Priority qdma (IF_prio_qdma_read_only)
Address: 2CA_0000h base + 2688h offset = 2CA_2688h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R Mark
Reserved
W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved P1 Reserved P0
W
Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
IF_prio_qdma_read_only field descriptions
Field Description
31 It works as backward compatibility marker when set to 0.
Mark
30–11 This field is reserved.
—
10–8 In programmable or bandwidth limiter mode the priority level for read transactions.
P1
In bandwidth regulator mode the priority level when the used throughput is below the threshold.
In bandwidth regulator mode P1 should have a value equal or greater than P0.
7–3 This field is reserved.
—
P0 In programmable or bandwidth limiter mode the priority level for write transactions.
In bandwidth regulator mode the priority level when the used throughput is above the threshold.
In bandwidth regulator mode P0 should have a value equal or lower than P1.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 339
IF Memory Map/Register Definition
9.3.2 Mode qdma (IF_mod_qdma_read_only)
Address: 2CA_0000h base + 268Ch offset = 2CA_268Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved Mode
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
IF_mod_qdma_read_only field descriptions
Field Description
31–2 This field is reserved.
—
Mode 00 Programmable mode: a programmed priority is assigned to each read or write.
01 Bandwidth limiter mode: a hard limit restricts throughput.
10 Bypass mode.
11 Bandwidth regulator mode: priority decreases when throughput exceeds a threshold.
9.3.3 Bandwidth qdma (IF_bw_qdma_read_only)
Address: 2CA_0000h base + 2690h offset = 2CA_2690h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved Bandwidth
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
IF_bw_qdma_read_only field descriptions
Field Description
31–13 This field is reserved.
—
Bandwidth In bandwidth limiter or bandwidth regulator mode, the bandwidth threshold in units of 1/256th bytes per
cycle. For example 80 Mbps on a 250 MHz interface is value 0x0052.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
340 NXP Semiconductors
Chapter 9 Interconnect Fabric
9.3.4 Saturation qdma (IF_sat_qdma_read_only)
Address: 2CA_0000h base + 2694h offset = 2CA_2694h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved Saturation
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
IF_sat_qdma_read_only field descriptions
Field Description
31–10 This field is reserved.
—
Saturation In bandwidth limiter or bandwidth regulator mode, the maximum data count value in units of 16 bytes. This
determines the window of time over which bandwidth is measured. For example to measure bandwidth
within a 1000 cycle window on a 64-bit interface is value 0x1F4.
9.3.5 ExtControl qdma (IF_ext_cntrl_qdma_read_only)
Address: 2CA_0000h base + 2698h offset = 2CA_2698h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SocketQosEn
R
ExtThrEn
IntClkEn
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IF_ext_cntrl_qdma_read_only field descriptions
Field Description
31–3 This field is reserved.
—
2 IntClkEn
IntClkEn
1 ExtThrEn
ExtThrEn
0 SocketQosEn
SocketQosEn
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 341
IF Memory Map/Register Definition
9.3.6 Priority qdma (IF_prio_qdma_write_only)
Address: 2CA_0000h base + 2708h offset = 2CA_2708h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R Mark
Reserved
W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved P1 Reserved P0
W
Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
IF_prio_qdma_write_only field descriptions
Field Description
31 It works as backward compatibility marker when set to 0.
Mark
30–11 This field is reserved.
—
10–8 In programmable or bandwidth limiter mode the priority level for read transactions.
P1
In bandwidth regulator mode the priority level when the used throughput is below the threshold.
In bandwidth regulator mode P1 should have a value equal or greater than P0.
7–3 This field is reserved.
—
P0 In programmable or bandwidth limiter mode the priority level for write transactions.
In bandwidth regulator mode the priority level when the used throughput is above the threshold.
In bandwidth regulator mode P0 should have a value equal or lower than P1.
9.3.7 Mode qdma (IF_mod_qdma_write_only)
Address: 2CA_0000h base + 270Ch offset = 2CA_270Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved Mode
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
342 NXP Semiconductors
Chapter 9 Interconnect Fabric
IF_mod_qdma_write_only field descriptions
Field Description
31–2 This field is reserved.
—
Mode 00 Programmable mode: a programmed priority is assigned to each read or write.
01 Bandwidth limiter mode: a hard limit restricts throughput.
10 Bypass mode.
11 Bandwidth regulator mode: priority decreases when throughput exceeds a threshold.
9.3.8 Bandwidth qdma (IF_bw_qdma_write_only)
Address: 2CA_0000h base + 2710h offset = 2CA_2710h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved Bandwidth
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
IF_bw_qdma_write_only field descriptions
Field Description
31–13 This field is reserved.
—
Bandwidth In bandwidth limiter or bandwidth regulator mode, the bandwidth threshold in units of 1/256th bytes per
cycle. For example 80 Mbps on a 250 MHz interface is value 0x0052.
9.3.9 Saturation qdma (IF_sat_qdma_write_only)
Address: 2CA_0000h base + 2714h offset = 2CA_2714h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved Saturation
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
IF_sat_qdma_write_only field descriptions
Field Description
31–10 This field is reserved.
—
Saturation In bandwidth limiter or bandwidth regulator mode, the maximum data count value in units of 16 bytes. This
determines the window of time over which bandwidth is measured. For example to measure bandwidth
within a 1000 cycle window on a 64-bit interface is value 0x1F4.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 343
IF Memory Map/Register Definition
9.3.10 ExtControl qdma (IF_ext_cntrl_qdma_write_only)
Address: 2CA_0000h base + 2718h offset = 2CA_2718h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SocketQosEn
R
ExtThrEn
IntClkEn
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IF_ext_cntrl_qdma_write_only field descriptions
Field Description
31–3 This field is reserved.
—
2 —
IntClkEn
1 ExtThrEn
ExtThrEn
0 SocketQosEn
SocketQosEn
9.3.11 Priority pex (IF_prio_pex_read_only)
Address: 2CA_0000h base + 2788h offset = 2CA_2788h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R Mark
Reserved
W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved P1 Reserved P0
W
Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
344 NXP Semiconductors
Chapter 9 Interconnect Fabric
IF_prio_pex_read_only field descriptions
Field Description
31 It works as backward compatibility marker when set to 0.
Mark
30–11 This field is reserved.
—
10–8 In programmable or bandwidth limiter mode the priority level for read transactions.
P1
In bandwidth regulator mode the priority level when the used throughput is below the threshold.
In bandwidth regulator mode P1 should have a value equal or greater than P0.
7–3 This field is reserved.
—
P0 In programmable or bandwidth limiter mode the priority level for write transactions.
In bandwidth regulator mode the priority level when the used throughput is above the threshold.
In bandwidth regulator mode P0 should have a value equal or lower than P1.
9.3.12 Mode_pex (IF_mod_pex_read_only)
Address: 2CA_0000h base + 278Ch offset = 2CA_278Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved Mode
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
IF_mod_pex_read_only field descriptions
Field Description
31–2 This field is reserved.
—
Mode 00 Programmable mode: a programmed priority is assigned to each read or write.
01 Bandwidth limiter mode: a hard limit restricts throughput.
10 Bypass mode.
11 Bandwidth regulator mode: priority decreases when throughput exceeds a threshold.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 345
IF Memory Map/Register Definition
9.3.13 Bandwidth_pex (IF_bw_pex_read_only)
Address: 2CA_0000h base + 2790h offset = 2CA_2790h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved Bandwidth
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
IF_bw_pex_read_only field descriptions
Field Description
31–13 This field is reserved.
—
Bandwidth In bandwidth limiter or bandwidth regulator mode, the bandwidth threshold in units of 1/256th bytes per
cycle. For example 80 Mbps on a 250 MHz interface is value 0x0052.
9.3.14 Saturation_pex (IF_sat_pex_read_only)
Address: 2CA_0000h base + 2794h offset = 2CA_2794h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved Saturation
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
IF_sat_pex_read_only field descriptions
Field Description
31–10 This field is reserved.
—
Saturation In bandwidth limiter or bandwidth regulator mode, the maximum data count value in units of 16 bytes. This
determines the window of time over which bandwidth is measured. For example to measure bandwidth
within a 1000 cycle window on a 64-bit interface is value 0x1F4.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
346 NXP Semiconductors
Chapter 9 Interconnect Fabric
9.3.15 ExtControl_pex_ro (IF_ext_cntrl_pex_ro)
Address: 2CA_0000h base + 2798h offset = 2CA_2798h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SocketQosEn
R
ExtThrEn
IntClkEn
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IF_ext_cntrl_pex_ro field descriptions
Field Description
31–3 This field is reserved.
—
2 IntClkEn
IntClkEn
1 ExtThrEn
ExtThrEn
0 SocketQosEn
SocketQosEn
9.3.16 Priority_pex (IF_prio_pex_write_only)
Address: 2CA_0000h base + 2808h offset = 2CA_2808h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R Mark
Reserved
W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved P1 Reserved P0
W
Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 347
IF Memory Map/Register Definition
IF_prio_pex_write_only field descriptions
Field Description
31 It works as backward compatibility marker when set to 0.
Mark
30–11 This field is reserved.
—
10–8 In programmable or bandwidth limiter mode the priority level for read transactions.
P1
In bandwidth regulator mode the priority level when the used throughput is below the threshold.
In bandwidth regulator mode P1 should have a value equal or greater than P0.
7–3 This field is reserved.
—
P0 In programmable or bandwidth limiter mode the priority level for write transactions.
In bandwidth regulator mode the priority level when the used throughput is above the threshold.
In bandwidth regulator mode P0 should have a value equal or lower than P1.
9.3.17 Mode_pex (IF_mod_pex_write_only)
Address: 2CA_0000h base + 280Ch offset = 2CA_280Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved Mode
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
IF_mod_pex_write_only field descriptions
Field Description
31–2 This field is reserved.
—
Mode 00 Programmable mode: a programmed priority is assigned to each read or write.
01 Bandwidth limiter mode: a hard limit restricts throughput.
10 Bypass mode.
11 Bandwidth regulator mode: priority decreases when throughput exceeds a threshold.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
348 NXP Semiconductors
Chapter 9 Interconnect Fabric
9.3.18 Bandwidth_pex (IF_bw_smmu_pex_write_only)
Address: 2CA_0000h base + 2810h offset = 2CA_2810h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved Bandwidth
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
IF_bw_smmu_pex_write_only field descriptions
Field Description
31–13 This field is reserved.
—
Bandwidth In bandwidth limiter or bandwidth regulator mode, the bandwidth threshold in units of 1/256th bytes per
cycle. For example 80 Mbps on a 250 MHz interface is value 0x0052.
9.3.19 Saturation_pex (IF_sat_pex_write_only)
Address: 2CA_0000h base + 2814h offset = 2CA_2814h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved Saturation
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
IF_sat_pex_write_only field descriptions
Field Description
31–10 This field is reserved.
—
Saturation In bandwidth limiter or bandwidth regulator mode, the maximum data count value in units of 16 bytes. This
determines the window of time over which bandwidth is measured. For example to measure bandwidth
within a 1000 cycle window on a 64-bit interface is value 0x1F4.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 349
IF Memory Map/Register Definition
9.3.20 ExtControl_pex_wo (IF_ext_cntrl_pex_write_only)
Address: 2CA_0000h base + 2818h offset = 2CA_2818h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SocketQosEn
R
ExtThrEn
IntClkEn
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IF_ext_cntrl_pex_write_only field descriptions
Field Description
31–3 This field is reserved.
—
2 IntClkEn
IntClkEn
1 ExtThrEn
ExtThrEn
0 SocketQosEn
SocketQosEn
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
350 NXP Semiconductors
Chapter 10
Cache Coherent Interconnect (CCI-400)
10.1 The CCI-400 module as implemented on the chip
The CCI-400 is the main coherent interconnect of the chip. The CCI-400 interconnect
supports two ACE masters, three-Ace-Lite masters, and three slave interfaces.
This section provides details about how the CCI-400 module is implemented on the chip.
10.1.1 LS1043A CCI module integration
The register offset in CCI-400 starts from 0x90000 and should be treated as 0x0000 due
to implementation. The CCI-400 base address is 0x1180000 for LS1043A. See Figure
10-1 below for the MMU-500 and CCI-400 connectivity.
The CCI-400 supports coherent/snoop transactions (write unique and read once) from the
masters. The master that doesn't have the capability to generate coherent/snoop
transactions have chip defined registers (Snoop Configuration Register
(SCFG_SNPCNFGCR)) to generate snoop transactions. Once the corresponding field in
this register is set, all the transactions are considered as snoop/coherent data.
Unlike the other masters where certain data transactions can be coherent/snoop, the
masters whose snoop is enabled through this register, all transactions are considered
snoop/coherent.
Similarly there exists QOS (QOS1 Register (SCFG_QOS1), QOS2 Register
(SCFG_QOS2)) for programming QoS for data transactions from the corresponding
masters. The masters which can generate QoS are not mentioned in this register.
Only nERRORIRQ interrupt is connected to the interrupt controller.
NOTE
The CCI-400 has per core lock-reservation monitor individually
for secure and non-secure exclusive (ARLOCK/AWLOCK)
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 351
The CCI-400 module as implemented on the chip
transactions (that is, a total of eight monitors). These
transactions are terminated at the CCI level, as the system
beyond CCI do not support the “lock transactions”. Transaction
should be marked with domain setting, such as “01- Inner
sharable” or “10- Outersharable”.
10.1.2 Connections to the CCI-400 interconnect
The following are the connections to the CCI-400 interconnect:
• 2x full ACE slave ports. One (S4 128-b ACE interface) is used to connect the quad
core A53 core platform. The other (S3) is left unused.
• 3x ACE-Lite and DVM ports, used to connect to IO-Coherent masters
• S0 Ace-Lite slave interface (FMan, SEC, QMan/BMan masters through NoC and
SMMU-500 TCU and TBU)
• S1 Ace-Lite slave interface (qDMA and PCI express masters through
Interconnect fabric and TBU1, TBU2)
• S2 Ace-Lite slave interface (All other masters through Interconnect Fabric and
SMMU-500 TBU3)
Three ACE-Lite master ports
• M0 for peripheral access (all the peripherals except PCI express controllers through
Interconnect fabric)
• M1 AXI3 allocated for DDR memory
• M2 (connected to Interconnect Fabric through CPE425 for PCI express traffic)
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
352 NXP Semiconductors
Chapter 10 Cache Coherent Interconnect (CCI-400)
A53 S4
core cluster DDR
M1 TZASC
controller
FMan/QMan/BMan
TBU0+TCU S0
SEC
CCI-400
Not Used S3
M0 OCRAM1
TBU3 S2 OCRAM2
3xUSB 3.0
CCSR
eSDHC S1 M2
uQE IFC
Interconnect Fabric (IF)
eDMA QuadSPI
SATA TBU2 PCI Express1
TBU1 PCI Express2
PCI Express3
qDMA
Figure 10-1. Chip interconnect
10.1.3 Snoop transaction configurations
The following table provides the snoop transaction configurations for different modules:
Table 10-1. Snoop transaction configuration for modules
Module Snoop transaction configuration
FMAN Refer LS1043ADPAARM for more details.
BMAN/QMAN
SEC All transactions from SEC are tagged as snoop configuration if the SCFG_SNPCNFGCR[SECRDSNP],
SCFG_SNPCNFGCR[SECWRSNP], SEC_MCFGR[ARCACHE], and MCFG[AWCACHE] bits are set.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 353
Functional Description
Table 10-1. Snoop transaction configuration for modules (continued)
Module Snoop transaction configuration
Refer Snoop Configuration Register (SCFG_SNPCNFGCR) and Master Configuration (MCFGR) in
security reference manual for details.
PCI Expressn Snoop transactions are dependent on PCI Express protocol and controlled by PCI Express IATU registers.
Refer PEX register descriptions for details.
qDMA Global snoop is controlled by DMA mode register, legacy mode - DMA legacy attribute register, queue
mode - command queue mode register. Refer DMA mode register (DMR), Command queue mode register
(CQMR) for details.
SATA All transactions from SATA are tagged as snoop configuration if the SCFG_SNPCNFGCR[SATARDSNP],
SCFG_SNPCNFGCR[SATAWRSNP], SATA_AXICC[EARC], and SATA_AXICC[EAWC] bits are set. Refer
Snoop Configuration Register (SCFG_SNPCNFGCR) and AXI cache control register (AXICC) for details.
USBn3.0 All transactions from USB 3.0 are tagged as snoop configuration if the
SCFG_SNPCNFGCR[USBnRDSNP], SCFG_SNPCNFGCR[USBnWRSNP] and USBx_GSBUSCFG0 bits
are set. Refer Snoop Configuration Register (SCFG_SNPCNFGCR) and Global SoC Bus Configuration
Register 0 (USB_GSBUSCFG0) for details.
QUICC Engine Snoop transactions from QUICC Engine are controlled by bus mode register. Refer to the bus mode
register in QEIWRM for details.
eDMA All transactions from eDMA are tagged as snoop configuration if the SCFG_SNPCNFGCR[eDMASNP] bit
is set. Refer Snoop Configuration Register (SCFG_SNPCNFGCR) for details.
10.2 Functional Description
This chapter describes the functionality of the CoreLink CCI-400 Cache Coherent
Interconnect.
10.2.1 About the functions
The CCI-400 combines interconnect and coherency functions into a single module.
10.2.2 Snoop connectivity and control
The CCI-400 has a fully-connected snoop topology, so if they are enabled:
• Each ACE slave interface snoops the other ACE slave interface.
• ACE-Lite slave interfaces snoop both ACE slave interfaces.
• DVM messages are broadcast through all enabled slave interfaces.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
354 NXP Semiconductors
Chapter 10 Cache Coherent Interconnect (CCI-400)
Snooping and DVM message broadcast are disabled at reset, so you must enable the
appropriate masters for snooping and DVM messages using the Snoop Control Registers
before shareable or DVM messages are sent to the CCI-400. See Snoop Control Registers
(Snoop_Control_Register_S0 - Snoop_Control_Register_S4).
Each ACE slave interface has programmable bits in the Snoop Control Registers. These
bits control the issuing of snoop and DVM message requests on that interface.
NOTE
ACE-Lite slave interfaces have programmable bits to enable
DVM messages only.
These programmable bits of the Snoop Control Registers are tied LOW at reset so you
must program them HIGH for each master in the shareable domain before shareable
transactions or DVM messages are sent to the CCI-400. Before disabling a master, you
must disable snoop and DVM messages to that master by programming the relevant
Snoop Control Register bits LOW.
To avoid deadlock through having AC requests enabled to interfaces where masters are
not present, or not able to process them, the CCI-400 has the following hardware and
software override mechanisms:
• Each slave interface has an ACCHANNELEN input bit that, if you tie it LOW,
prevents that interface from issuing any AC requests.
NOTE
These bits are only sampled at reset.
• There are bits in the Control Override Register to disable all snooping or all DVM
message broadcast, irrespective of the programming of the Snoop Control Register.
10.2.2.1 Removing a master from the coherent domain
If you want to remove a master from the coherent domain, for example if a processor is
being powered down, take the following actions:
1. Stop the processor from issuing shareable transactions. See the documentation of the
processor.
2. Clean any shareable data in the processor cache. See the documentation of the
processor.
3. Use the Snoop Control Register to prevent any more snoops or DVM messages being
sent to the processor. See the Snoop Control Registers (Snoop_Control_Register_S0
- Snoop_Control_Register_S4).
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 355
Functional Description
4. Poll the CCI Status Register to confirm that the changes to the Snoop Control
Register have completed. See the Status Register (Status_Register).
After you complete these actions, the master is no longer in the coherent domain and you
can power it down or disable it. You must enable snoops to that master again before it
allocates any shareable data in its cache.
10.2.3 Speculative fetch
For an application where the probability of a miss is high, then the snoop request and
response time adds directly to the latency for each transaction labelled as shareable. To
mitigate this, you can program each master interface to issue a fetch downstream in
parallel with issuing a snoop request. This is known as a speculative fetch.
In the event that the snoop associated with a speculative fetch hits in a cache, then the
data from the snoop is returned in preference to the data from the speculative fetch.
A speculative fetch is issued before all hazards that had arisen from the corresponding
snoop have been resolved. Therefore, it is sometimes necessary to discard the data
returned from memory and retry the fetch. These cases are:
• When a hazarding write transaction is detected. This hazarding write transaction
must be ordered before the speculative fetch.
• When data from the speculative fetch returns before the snoop response for that
transaction, and the read data buffer is already occupied by data waiting for a snoop
response.
You can use the PMU to record the number of retry transactions for each master
interface.
NOTE
Speculative fetches are only issued for these read-type
transactions:
• ReadOnce .
• ReadClean .
• ReadNotSharedDirty .
• ReadUnique .
• ReadShared.
Although speculative fetches reduce the latency in the case of a snoop miss, there is a
bandwidth and power penalty because of the additional transactions on a snoop hit.
Therefore, you can disable speculative fetches where you expect a significant number of
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
356 NXP Semiconductors
Chapter 10 Cache Coherent Interconnect (CCI-400)
snoops to hit. You can use the Speculation Control Register to disable speculative fetches
for a master or a slave interface. For example, you can disable speculative fetches for
transactions from a master that is not latency sensitive. See Speculation Control Register
(Speculation_Control_Register).
10.2.4 Security
If you are building a system based on the Secure and Non-secure capabilities that Arm
TrustZone® technology provides, then you must consider security issues. This section
describes:
• Internal programmers view.
• Security of master interfaces.
10.2.4.1 Internal programmers view
With the exception of the PMU registers, the programmers view defaults to Secure access
only, as follows:
• Non-secure read requests to Secure registers receive a DECERR response,
RRESP[1:0] == 0b11 , and zeroed data.
• Non-secure write requests to Secure registers receive a DECERR response,
BRESP[1:0] == 0b11 and are Write-Ignored (WI).
NOTE
Some accesses might receive a response before they reach the
CCI-400 registers and so do not receive a DECERR response
nor affect the register values. An example of this is a cache
maintenance operation that incorrectly addresses the CCI-400
register space.
You can override these security settings in the Secure Access Register. At reset, you can
only access this using Secure requests, but if you write to it, this enables Non-secure
access to all registers in the CCI-400 except for the Control Override Register and Secure
Access Register. See Control Override Register (Control_Override_Register) and Secure
Access Register (Secure_Access_Register).
10.2.4.2 Security of master interfaces
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 357
Functional Description
Transactions from the CCI-400 master interfaces always retain the security setting of the
originating transactions. This applies to:
• Non-shareable transactions.
• Snoop misses.
• Speculative fetches.
• CCI-400-generated writes.
10.2.5 Error responses
The CCI-400 uses a mixture of precise and imprecise signaling of error responses, where:
• Precise errors are signalled back to the master on the R and B channels for the
precise transaction that caused the error.
• Imprecise errors are not signalled on R and B channels but are instead signalled using
the nERRORIRQ output pin (See Table "Interrupt Assignments" in the "Interrupt
Assignments" chapter). You can identify the interface that received the error
response by reading the Imprecise Error Register. See Imprecise Error Register (Impr
ecise_Error_Register).
10.2.5.1 Imprecise errors
Table 10-2 shows the errors that are signalled as imprecise. All other sources of error are
signalled precisely.
NOTE
An error is signalled either precisely or imprecisely, but never
both.
Table 10-2. Imprecise errors
Transaction causing error Channel receiving error Imprecise error indicator from
A ReadX snoop that misses in the cache CR Slave interface receiving the CR
and fetches data from downstream response
Distributed Virtual Memory message CR Slave interface receiving the CR
response
Speculative fetch that returns an error, R Master interface receiving the R
but the snoop returns data response
Speculative fetch that must be retried R Master interface receiving the R
response
Write that the CCI-400 generated B Master interface receiving the B
response
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
358 NXP Semiconductors
Chapter 10 Cache Coherent Interconnect (CCI-400)
Table 10-2. Imprecise errors (continued)
Snoop error generated by a CR Master interface receiving the CR
WriteLineUnique or WriteUnique response
transaction
Write error for WriteUnique transactions B Slave interface that received the
that have been split but not the last transaction that was split
transaction in the split sequence
The CCI-400 generates a precise DECERR response in the case of a security violation on
a CCI-400 register access. See Imprecise Error Register (Imprecise_Error_Register) and
Security .
10.2.6 Barriers
The CCI-400 supports all types of AMBA 4 barrier transactions. Each slave interface
broadcasts these to every master interface, ensuring that intermediate transaction source
and sink points observe the barrier correctly.
10.2.7 DVM messages
The ACE slave interfaces support DVM messages through their regular AC and CR
channels. The ACE-Lite interfaces all contain AC and CR channels to support DVM
messages only. Each slave interface has a programmable enable bit to determine whether
it supports the issuing of AC requests for DVM messages. DVM messages are handled as
regular transactions in the CCI-400, except that they are decoded based on the DVM
message indicator, instead of the address, to ensure that multi-transaction DVM messages
are correctly ordered.
The Snoop Control Registers and Control Override Register control the issuing of DVM
message requests. See Snoop Control Registers (Snoop_Control_Register_S0 - Snoop_
Control_Register_S4) and Control Override Register (Control_Override_Register).
ACE and ACE-Lite, plus DVM slave interfaces support all types of DVM transaction.
These are:
• DVM Operation.
• DVM Synchronization.
• DVM Complete.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 359
Functional Description
The R channel response to a DVM messages is sent immediately by the CCI-400. If the
DVM message results in an error response, this is signaled imprecisely. For more
information, see Error responses .
NOTE
• A master that issues DVM messages must also be able to
receive DVM messages. The slave interface through which
the master connects must have DVM messages enabled.
10.2.8 Quality of Service
The CCI-400 supports QoS with the following independent mechanisms:
• QoS value
• Regulation based on outstanding transactions .
10.2.8.1 QoS value
Each CCI-400 slave interface has ARQOS and AWQOS input signals that transport a
transaction-based QoS value. This determines the relative priority between transactions
on that interface, or between interfaces. The CCI-400 uses the QoS value when it chooses
between transaction requests at arbitration points and within queues. Transaction requests
with the highest QoS value are prioritized. The CCI-400 uses a Least Recently Granted
(LRG) scheme when two or more transactions share the highest value.
QoS values are propagated by CCI-400.
NOTE
Ensure that you balance the relative priorities of all slave
interfaces. For example, setting each to the highest QoS value
reduces the arbitration to LRG and no advantage is gained from
having a QoS value.
You can override the ARQOS and AWQOS input signals from each slave interface by
using a programmable register if the relevant static input signal, QOSOVERRIDE[4:0],
with one bit for each of slave interfaces 4-0, is HIGH. The QoS override is either based
on a programmable value or uses performance feedback to set the value within a
programmable range. Transactions that the CCI-400 generates use the same QoS value as
the instigating transaction or the override value if QOSOVERRIDE is set.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
360 NXP Semiconductors
Chapter 10 Cache Coherent Interconnect (CCI-400)
NOTE
QOSOVERRIDE[4:0] input signal is not controllable in this
device and set to zero.
NOTE
QOSOVERRIDE only applies to transactions that have a
ARQOS or AWQOS value of 0. Therefore, each interface can
have a mixture of traffic that is overridden or regulated and
other traffic, with non-zero QoS value, that is unaffected. For
example, high priority MMU page table requests might be
mixed with high-bandwidth media requests that require
regulation.
QoS value regulation
CCI-400 regulation mechanisms vary the transaction QoS value depending on latency or
bandwidth achieved through that slave interface. You can program target latency or
bandwidth and a QoS value range for each regulator. Arm recommends that achievable
targets are set so that the regulator uses the minimum QoS value in most cases and only
increases the QoS value, up to the programmed maximum, under worst case conditions.
The maximum value for each regulator is 0 at reset, so you must program a maximum
value before the regulator can be used.
You can control the rate of change of the regulator integrator by using a programmable
scale factor. There are two types of QoS value regulation:
• Regulation based on latency.
• Regulation based on bandwidth.
Regulation based on latency
In this regulation mode, QoS values change based on measured latency. The value tends
to increase if the latency is greater than the target and decrease if the latency is lower than
the target.
Regulation based on bandwidth
For bandwidth regulation, the target used for feedback is the period between successive
request handshakes, in cycles. The value tends to increase if the period is greater than the
target and decrease if the period is lower than the target. If the average number of bytes
per request is known, this is equivalent to a bandwidth measure. Shareable transactions in
the CCI-400 are 64 bytes in size, so this is usually a good approximation to use.
There are two modes of operation available when you are using this type of regulation:
Normal mode
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 361
Functional Description
In this mode the QoS value remains stable when the master is idle, this is equivalent to
measuring the average bandwidth only when the master is active. This is the default
mode.
Quiesce High mode
In this mode, the QoS value tends to the maximum programmed value when the master is
idle, so when it becomes active, the initial transactions have a high QoS value. This mode
is suitable for latency sensitive masters because it allows the master to be serviced with
high priority while the bandwidth requirement is below that set. If the master starts to
exceed its programmed bandwidth, the priority is reduced. You can use this mechanism
to ensure that other masters are not excluded when latency sensitive masters take
significant bandwidth.
You enable QoS value regulation by setting the appropriate control bits. See Qos Control
Register (Qos_Control_Register_S0 - Qos_Control_Register_S4). When you enable QoS
value regulation, ARQOS and AWQOS values are driven by those generated by the
regulators, if the original transaction has a zero QoS value and the QOSOVERRIDE
configuration input is HIGH.
You can program the regulator mode using the QoS Control Registers.
NOTE
• Turning QoS value regulation on when
QOSOVERRIDE[x] is set LOW for a specific interface
has no effect.
• Transactions that do not transfer data are not counted for
QoS value regulation and do not have their QoS value
overridden. These transactions are:
• CleanUnique .
• MakeUnique .
• CleanShared .
• CleanInvalid .
• MakeInvalid .
• Evict .
• Barriers.
• DVM transactions.
10.2.8.2 Regulation based on outstanding transactions
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
362 NXP Semiconductors
Chapter 10 Cache Coherent Interconnect (CCI-400)
The CCI-400 offers an additional mechanism for regulating traffic flows for the benefit
of overall performance. Each ACE-Lite slave interface has an optional, programmable
mechanism for limiting the number of outstanding read and write transactions, where an
Outstanding Transaction (OT) is a read request without read data, or a write request
without a response. This can be used where QoS value regulation is not effective because
the system is not sensitive to QoS value. The disadvantage of this form of regulation is
that it might stall the master even when the system is idle and traffic from this master is
not affecting the performance of other masters.
You can characterize a sequence of transactions, with periods when there are no
outstanding transactions, by using a fractional outstanding transaction number. For
example, if requests occur every 100 cycles, but it only takes 50 cycles for the last
response to arrive, then this corresponds to 0.5 OTs. The sum of the integer and fractional
values represents a maximum of the mean number of OTs in a sliding window and,
consequently, also over all time. If the fractional part is 0, the number of OTs is never
permitted to exceed the integer part. If the fractional part is not 0, the number of OTs is
not permitted to exceed one more than the integer part. This mean value is only achieved
if the attached master maintains the maximum number of transactions it is able to issue at
all times. Therefore, if the integer part is 0 and the fractional part is 0.5, and transactions
have a lifespan of 50 cycles, then a master can issue a transaction. It finishes after 50
cycles and it cannot issue the next transaction until 100 cycles, maintaining a mean
number of outstanding transactions as 0.5.
If you enable regulation, the following programmable values set the permitted number of
outstanding transactions:
• OT integer.
• OT fraction.
NOTE
• Outstanding transaction regulation only counts transactions
with a zero QoS value.
• Outstanding transaction regulation does not count or
override transactions that have no data associated with
them. These transactions are:
• CleanUnique .
• MakeUnique .
• CleanShared .
• CleanInvalid .
• MakeInvalid .
• Evict .
• Barriers.
• DVM transactions.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 363
Functional Description
Read Queue Slot Reservation
Each master interface of the CCI-400 has a queue that stores read requests. If this
becomes full with low priority requests, higher priority requests are blocked. To avoid
this, the CCI-400 reserves a number of slots for high priority requests and a number of
slots for high or medium priority requests. Table Regulation based on outstanding
transactions shows a summary of the possible configurations.
Table 10-3. Slots reserved for high and medium priority traffic in each master interface
Read tracker size, as determined by Number of reserved slots for medium Number of reserved slots for only
the Mlx_R_MAX parameter or high priority requests high priority requests
2-4 0 0
5-7 0 1
8-15 1 1
16-128 3 1
For example, assume the read tracker size is 32, implying that three slots are reserved for
medium to high priority requests and one slot is reserved for high priority requests. In this
case:
• The maximum number of slots available for high priority requests is 32.
• The maximum number of slots available for medium priority requests is 32 - 1 = 31.
• The maximum number of slots available for low priority requests is 32 - 3 - 1 = 28.
The QoS values that are considered as high and medium priority can be configured at the
design time using the R_THRESHOLD_UPPER and R_THRESHOLD_LOWER
parameters however the values configured for these two parameters in this chip are 15
and 11.
10.2.8.3 QoS programmable registers
Programmers Model describes the following registers:
• Read Channel QoS Value Override Register.
• Write Channel QoS Value Override Register.
• QoS Control Register.
• Max OT Registers.
• Regulator Target Registers.
• QoS Regulator Scale Factor Registers.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
364 NXP Semiconductors
Chapter 10 Cache Coherent Interconnect (CCI-400)
10.3 register descriptions
10.3.1 CCI400 Registers Memory map
Base address: 118_0000h
Offset Register Width Access Reset value
(In bits)
0h Control Override Register (Control_Override_Register) 32 RW See
description.
4h Speculation Control Register (Speculation_Control_Register) 32 RW See
description.
8h Secure Access Register (Secure_Access_Register) 32 RW See
description.
Ch Status Register (Status_Register) 32 RO See
description.
10h Imprecise Error Register (Imprecise_Error_Register) 32 RW See
description.
1000h Snoop Control Registers (Snoop_Control_Register_S0) 32 RW See
description.
1004h Shareable Override Registers (Shareable_Override_Register_S0) 32 RW See
description.
1100h Read Channel QoS Value Override Register (Read_Qos_Override_ 32 RW See
Register_S0) description.
1104h Write Qos Override Register (Write_Qos_Override_Register_S0) 32 RW See
description.
110Ch Qos Control Register (Qos_Control_Register_S0) 32 RW See
description.
1110h Max OT Registers (Max_OT_Register_S0) 32 RW See
description.
1130h Regulator Target Registers (Target_Latency_Register_S0) 32 RW See
description.
1138h QoS Range Register (Qos_Range_Register_S0) 32 RW See
description.
2000h Snoop Control Registers (Snoop_Control_Register_S1) 32 RW See
description.
2004h Shareable Override Registers (Shareable_Override_Register_S1) 32 RW See
description.
2100h Read Channel QoS Value Override Register (Read_Qos_Override_ 32 RW See
Register_S1) description.
2104h Write Qos Override Register (Write_Qos_Override_Register_S1) 32 RW See
description.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 365
register descriptions
Offset Register Width Access Reset value
(In bits)
210Ch Qos Control Register (Qos_Control_Register_S1) 32 RW See
description.
2110h Max OT Registers (Max_OT_Register_S1) 32 RW See
description.
2130h Regulator Target Registers (Target_Latency_Register_S1) 32 RW See
description.
2138h QoS Range Register (Qos_Range_Register_S1) 32 RW See
description.
2268h QoS Regulator Scale Factor Registers (Latency_Regulation_Regis 32 RW See
ter_S0) description.
3000h Snoop Control Registers (Snoop_Control_Register_S2) 32 RW See
description.
3004h Shareable Override Registers (Shareable_Override_Register_S2) 32 RW See
description.
3100h Read Channel QoS Value Override Register (Read_Qos_Override_ 32 RW See
Register_S2) description.
3104h Write Qos Override Register (Write_Qos_Override_Register_S2) 32 RW See
description.
310Ch Qos Control Register (Qos_Control_Register_S2) 32 RW See
description.
3110h Max OT Registers (Max_OT_Register_S2) 32 RW See
description.
3130h Regulator Target Registers (Target_Latency_Register_S2) 32 RW See
description.
3138h QoS Range Register (Qos_Range_Register_S2) 32 RW See
description.
3268h QoS Regulator Scale Factor Registers (Latency_Regulation_Regis 32 RW See
ter_S1) description.
4000h Snoop Control Registers (Snoop_Control_Register_S3) 32 RW See
description.
4004h Shareable Override Registers (Shareable_Override_Register_S3) 32 RW See
description.
4100h Read Channel QoS Value Override Register (Read_Qos_Override_ 32 RW See
Register_S3) description.
4104h Write Qos Override Register (Write_Qos_Override_Register_S3) 32 RW See
description.
410Ch Qos Control Register (Qos_Control_Register_S3) 32 RW See
description.
4110h Max OT Registers (Max_OT_Register_S3) 32 RW See
description.
4130h Regulator Target Registers (Target_Latency_Register_S3) 32 RW See
description.
4138h QoS Range Register (Qos_Range_Register_S3) 32 RW See
description.
4268h QoS Regulator Scale Factor Registers (Latency_Regulation_Regis 32 RW See
ter_S2) description.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
366 NXP Semiconductors
Chapter 10 Cache Coherent Interconnect (CCI-400)
Offset Register Width Access Reset value
(In bits)
5000h Snoop Control Registers (Snoop_Control_Register_S4) 32 RW See
description.
5004h Shareable Override Registers (Shareable_Override_Register_S4) 32 RW See
description.
5100h Read Channel QoS Value Override Register (Read_Qos_Override_ 32 RW See
Register_S4) description.
5104h Write Qos Override Register (Write_Qos_Override_Register_S4) 32 RW See
description.
510Ch Qos Control Register (Qos_Control_Register_S4) 32 RW See
description.
5110h Max OT Registers (Max_OT_Register_S4) 32 RW See
description.
5130h Regulator Target Registers (Target_Latency_Register_S4) 32 RW See
description.
5138h QoS Range Register (Qos_Range_Register_S4) 32 RW See
description.
5268h QoS Regulator Scale Factor Registers (Latency_Regulation_Regis 32 RW See
ter_S3) description.
6268h QoS Regulator Scale Factor Registers (Latency_Regulation_Regis 32 RW See
ter_S4) description.
10.3.2 Control Override Register (Control_Override_Register)
10.3.2.1 Offset
Register Offset
Control_Override_Reg 0h
ister
10.3.2.2 Function
The Control Override register is an additional control register that provides a fail-safe
override for some CCI-400 functions, if these cause problems that you cannot otherwise
work around. If you cannot avoid using them, only set them using non-bufferable
transactions, and before barriers, shareable transactions, or DVM messages are issued
into the CCI-400. This can be, for example, very early in the boot sequence, prior to the
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 367
register descriptions
installation of any Secure OS. You can access the Control Override Register using Secure
transactions only, irrespective of the programming of the Secure Access Register .
Available in all CCI-400 configurations.
10.3.2.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset u u u u u u u u u u u u u u u u
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Disable_Retry_Reduction_Buffers
Disable_Speculative_Fetches
Disable_Priority_Promotion
DVM_Message_Disable
Terminate_Barriers
Snoop_Disable
Reserved
Reset u u u u u u u u u u 0 0 0 0 0 0
10.3.2.4 Fields
Field Function
31-6 Reserved
—
5 Disable retry reduction buffers for speculative fetches
0b - Retry reduction buffers enabled.
Disable_Retry_
1b - Retry reduction buffers disabled.
Reduction_Buffe
rs
4 ARQOSARBS inputs are ignored
0b - The CCI-400 uses ARQOSARBS inputs to promote the priority of earlier requests.
Disable_Priority
1b - The CCI-400 ignores ARQOSARBS inputs.
_Promotion
3 Terminate Barriers
0b - Master interfaces terminate barriers according to the BARRIERTERMINATE inputs.
Terminate_Barri
1b - All master interfaces terminate barriers.
ers
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
368 NXP Semiconductors
Chapter 10 Cache Coherent Interconnect (CCI-400)
Field Function
2 Disable Speculative Fetches
0b - Send speculative fetches according to the Speculation Control Register. See Speculation
Disable_Specul
Control Register.
ative_Fetches
1b - Disable speculative fetches from all master interfaces.
1 DVM Message Disable
0b - Send DVM messages according to the Snoop Control Registers. See Snoop Control Registers.
DVM_Message_
1b - Disable propagation of all DVM messages.
Disable
0 Snoop Disable
0b - Snoop masters according to the Snoop Control Registers. See Snoop Control Registers.
Snoop_Disable
1b - Disable all snoops, but not DVM messages.
10.3.3 Speculation Control Register (Speculation_Control_Regi
ster)
10.3.3.1 Offset
Register Offset
Speculation_Control_ 4h
Register
10.3.3.2 Function
The Speculation Control register disables speculative fetches for a master interface or for
traffic through a specific slave interface. Speculative fetches are not issued if they are
disabled in either the slave or master interface for a particular transaction. Access
controlled by Secure Access Register, see Secure Access Register. Available in all
CCI-400 configurations.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 369
register descriptions
10.3.3.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Disable_Speculative_Fetches_S
Reserved
Reset u u u u u u u u u u u 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Disable_Speculative_Fetches_M
Reserved
Reset u u u u u u u u u u u u u 0 0 0
10.3.3.4 Fields
Field Function
31-21 Reserved
—
20-16 Disable speculative fetches from slave
Disable_Specul Disable speculative fetches for transactions through a slave interface. One bit for each slave interface:
ative_Fetches_S S4, S3, S2, S1, and S0:
00000b - Enable speculative fetches.
00001b - Disable speculative fetches.
15-3 Reserved
—
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
370 NXP Semiconductors
Chapter 10 Cache Coherent Interconnect (CCI-400)
Field Function
2-0 Disable speculative fetches from master
Disable_Specul Disable speculative fetches from a master interface. One bit for each master interface: M2, M1, and M0.
ative_Fetches_ 000b - Enable speculative fetches.
M 001b - Disable speculative fetches.
10.3.4 Secure Access Register (Secure_Access_Register)
10.3.4.1 Offset
Register Offset
Secure_Access_Register 8h
10.3.4.2 Function
The Secure Access register controls secure access. You can only write to this register
using Secure transactions. Available in all CCI-400 configurations.
NOTE
This register enables Non-secure access to the CCI-400
registers for all masters. This compromises the security of your
system.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 371
register descriptions
10.3.4.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset u u u u u u u u u u u u u u u u
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Secure_Access_Control
Reserved
Reset u u u u u u u u u u u u u u u 0
10.3.4.4 Fields
Field Function
31-1 Reserved
—
0 Secure Access Control
Secure_Access Non-secure register access override:
_Control 0b - Disable Non-secure access to CCI-400 registers.
1b - Enable Non-secure access to CCI-400 registers.
10.3.5 Status Register (Status_Register)
10.3.5.1 Offset
Register Offset
Status_Register Ch
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
372 NXP Semiconductors
Chapter 10 Cache Coherent Interconnect (CCI-400)
10.3.5.2 Function
The Status Register safely enables and disables snooping. When changing the snoop or
DVM message enables using the Snoop Control Registers, see Snoop Control Registers,
there is a delay until the changes are registered in all parts of the CCI-400. The
change_pending bit in the Status Register indicates whether there are any changes to the
enables that have not yet been applied, or whether a slave interface has been disabled for
future snoop and DVM messages, but has outstanding AC requests. There are no usage
constraints. Available in all CCI-400 configurations.
NOTE
After writing to the snoop or DVM enable bits, the controller
must wait for the register write to complete, then test that the
change_pending bit is LOW before it turns an attached device
on or off.
10.3.5.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset u u u u u u u u u u u u u u u u
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCI_Status
Reserved
W
Reset u u u u u u u u u u u u u u u 0
10.3.5.4 Fields
Field Function
31-1 Reserved
—
0 CCI_Status
CCI_Status Indicates whether any changes to the snoop or DVM enables is pending in the CCI-400
0b - No change pending.
1b - Change pending.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 373
register descriptions
10.3.6 Imprecise Error Register (Imprecise_Error_Register)
10.3.6.1 Offset
Register Offset
Imprecise_Error_Register 10h
10.3.6.2 Function
The Imprecise Error register records the CCI-400 interfaces that received an error that is
not signaled precisely. The appropriate bit is set, with respect to the interface on which
the error was received. Bits are set when one or more error responses are detected, and
they are reset on a write of 1 to the corresponding bit. Accessible using only Secure
accesses, unless you set the Secure Access Register. See Secure Access Register bit
assignments. There are no usage constraints. Available in all CCI-400 configurations.
NOTE
If any of the imprecise error indicator bits are set, the
nERRORIRQ signal is asserted, active LOW.
10.3.6.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Imp_Err_S4
Imp_Err_S3
Imp_Err_S2
Imp_Err_S1
Imp_Err_S0
Reserved
Reset u u u u u u u u u u u 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Imp_Err_M2
Imp_Err_M1
Imp_Err_M0
Reserved
Reset u u u u u u u u u u u u u 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
374 NXP Semiconductors
Chapter 10 Cache Coherent Interconnect (CCI-400)
10.3.6.4 Fields
Field Function
31-21 Reserved
—
20 Imprecise error indicator for slave interface S4
Imp_Err_S4
19 Imprecise error indicator for slave interface S3
Imp_Err_S3
18 Imprecise error indicator for slave interface S2
Imp_Err_S2
17 Imprecise error indicator for slave interface S1
Imp_Err_S1
16 Imprecise error indicator for slave interface S0
Imp_Err_S0
15-3 Reserved.
—
2 Imprecise error indicator for master interface M2
Imp_Err_M2
1 Imprecise error indicator for master interface M1
Imp_Err_M1
0 Imprecise error indicator for master interface M0
0b - No error from the time this bit was last reset.
Imp_Err_M0
1b - An error response has been received, but not signalled precisely.
10.3.7 Snoop Control Registers (Snoop_Control_Register_S0 -
Snoop_Control_Register_S4)
10.3.7.1 Offset
For a = 0 to 4:
Register Offset
Snoop_Control_Register 1000h + (a × 1000h)
_Sa
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 375
register descriptions
10.3.7.2 Function
The Snoop Control register controls the issuing of snoop and DVM requests on each
slave interface. You can read the register to determine if the interface supports snoops or
DVM messages. Enabling snoop or DVM requests on an interface that does not support
them has no effect. One Snoop Control Register exists for each slave interface.
Accessible using only Secure accesses, unless you set the Secure Access Register. See
Secure Access Register bit assignments. Available in all CCI-400 configurations.
NOTE
• If the ACCHANNELEN input is LOW for this interface,
write accesses to this register are ignored and snoop or
DVM requests cannot be enabled.
• If snoops are disabled in the Control Override Register,
write accesses to the snoop enable bit[0] are ignored.
• If DVM messages are disabled in the Control Override
Register, write accesses to the DVM enable bit[1] are
ignored.
10.3.7.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Support_snoops
Support_DVMs
Reserved
W
Reset 0 0 u u u u u u u u u u u u u u
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Enable_Snoop
Enable_DVMs
Reserved
Reset u u u u u u u u u u u u u u 0 u
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
376 NXP Semiconductors
Chapter 10 Cache Coherent Interconnect (CCI-400)
10.3.7.4 Fields
Field Function
31 Slave interface supports DVM messages
Support_DVMs This is overridden to 0x0 if you set the Control Override Register [1]. See Control Override Register.
30 Slave interface supports snoops
Support_snoops This is overridden to 0x0 if you set the Control Override Register [0]. See Control Override Register.
29-2 Reserved
—
1 Enable DVMs
Enable_DVMs Enable issuing of DVM message requests from slave interface. RAZ/WI for interfaces not supporting
DVM messages:
0b - Disable DVM message requests.
1b - Enable DVM message requests.
0 Enable Snoop
Enable_Snoop Enable issuing of snoop requests from this slave interface. RAZ/WI for interfaces not supporting snoops:
0b - Disable snoop requests.
1b - Enable snoop requests.
NOTE: This bit is reserved for Snoop_Control_Register_S0, Snoop_Control_Register_S1,
Snoop_Control_Register_S2, and Snoop_Control_Register_S3.
10.3.8 Shareable Override Registers (Shareable_Override_Regis
ter_S0 - Shareable_Override_Register_S4)
10.3.8.1 Offset
For a = 0 to 4:
Register Offset
Shareable_Override_Reg 1004h + (a × 1000h)
ister_Sa
10.3.8.2 Function
The Shareable Override register overrides shareability of normal transactions through this
interface. The following transaction types are unaffected by any override:
• FIXED-type bursts.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 377
register descriptions
• Device transactions.
• Barrier.
• DVM message transactions.
Usage constraints This register is for ACE-Lite slave interfaces only. See the AMBA
AXI and ACE Protocol Specification. Accessible using only Secure accesses, unless you
set the Secure Access Register. See Secure Access Register bit assignments. Available in
all CCI-400 configurations.
NOTE
Exclusive accesses must not be issued on an interface that is
being overridden as shareable. If the CCI-400 is programmed to
override transactions as shareable, Exclusive accesses are
overridden to normal accesses. An exclusive write then receives
an OKAY response to indicate that the slave does not support
exclusive accesses.
10.3.8.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset u u u u u u u u u u u u u u u u
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AxDomain_Override
Reserved
Reset u u u u u u u u u u u u u u 0 0
10.3.8.4 Fields
Field Function
31-2 Reserved
—
1-0 AxDOMAIN override
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
378 NXP Semiconductors
Chapter 10 Cache Coherent Interconnect (CCI-400)
Field Function
AxDomain_Over Shareable override for slave interface
ride 00b - Do not override AxDOMAIN inputs.
01b - Do not override AxDOMAIN inputs.
10b - Override AxDOMAIN inputs to 0b00, all transactions are treated as non-shareable.ReadOnce
becomes ReadNoSnoop.WriteUnique and WriteLineUnique become WriteNoSnoop.
11b - Override AxDOMAIN inputs to 0b01, normal transactions are treated as
shareable.ReadNoSnoop becomes ReadOnce.WriteNoSnoop becomes WriteUnique.
10.3.9 Read Channel QoS Value Override Register (Read_Qos_
Override_Register_S0 - Read_Qos_Override_Register_S4)
10.3.9.1 Offset
For a = 0 to 4:
Register Offset
Read_Qos_Override_Re 1100h + (a × 1000h)
gister_Sa
10.3.9.2 Function
The Read Channel QoS Value Override register contains override values for ARQOS,
with a register for each slave interface. This value is used if you set the
QOSOVERRIDE[4:0] input signal bit for this slave interface and the QoS value regulator
is not enabled. You can also use this register to read the current value of the QoS value
regulator for read accesses when the regulator is enabled. Accessible using only Secure
accesses, unless you set the Secure Access Register. See Secure Access Register bit
assignments. Available in all CCI-400 configurations.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 379
register descriptions
10.3.9.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset u u u u u u u u u u u u u u u u
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARQOS_override_readback
ARQOS_value
Reserved
Reserved
R
W
Reset u u u u 0 0 0 0 u u u u 0 0 0 0
10.3.9.4 Fields
Field Function
31-12 Reserved
—
11-8 ARQOS override readback
ARQOS_overrid Reads what value is currently applied to transactions with ARQOS=0, provided QOSOVERRIDE is HIGH
e_readback and the QoS value regulator is enabled.
7-4 Reserved
—
3-0 ARQOS value
ARQOS_value ARQOS value override for slave interface
10.3.10 Write Qos Override Register (Write_Qos_Override_Regis
ter_S0 - Write_Qos_Override_Register_S4)
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
380 NXP Semiconductors
Chapter 10 Cache Coherent Interconnect (CCI-400)
10.3.10.1 Offset
For a = 0 to 4:
Register Offset
Write_Qos_Override_Re 1104h + (a × 1000h)
gister_Sa
10.3.10.2 Function
The Write Channel QoS Value Override Register characteristics are: Purpose Contains
override values for AWQOS, with a register for each slave interface. This value is used if
you set the QOSOVERRIDE[4:0] input signal bit for this slave interface and the QoS
value regulator is not enabled. You can also read the current value of the QoS value
regulator for write accesses when the regulator is enabled. Accessible using only Secure
accesses, unless you set the Secure Access Register. See Secure Access Register bit
assignments. Available in all CCI-400 configurations.
10.3.10.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset u u u u u u u u u u u u u u u u
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWQOS_override_readback
AWQOS_value
Reserved
Reserved
W
Reset u u u u 0 0 0 0 u u u u 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 381
register descriptions
10.3.10.4 Fields
Field Function
31-12 Reserved.
—
11-8 AWQOS override readback
AWQOS_overrid Reads what value is currently applied to transactions with AWQOS=0, provided QOSOVERRIDE is HIGH
e_readback and the QoS value regulator is enabled.
7-4 Reserved.
—
3-0 AWQOS value
AWQOS_value AWQOS value override for slave interface S0
10.3.11 Qos Control Register (Qos_Control_Register_S0 - Qos_
Control_Register_S4)
10.3.11.1 Offset
For a = 0 to 4:
Register Offset
Qos_Control_Register_S 110Ch + (a × 1000h)
a
10.3.11.2 Function
The QoS Control register controls the regulators that are enabled on the slave interfaces.
Accessible using only Secure accesses, unless you set the Secure Access Register. See
Secure Access Register bit assignments on page 3-10. Available in all CCI-400
configurations.
NOTE
When outstanding transaction regulation is enabled or disabled
for an interface, changes take effect only when there are no
outstanding transactions in that interface.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
382 NXP Semiconductors
Chapter 10 Cache Coherent Interconnect (CCI-400)
10.3.11.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
QoS_regulation_disabled
Bandwidth_regulation_mode
AWQOS_regulation_mode
ARQOS_regulation_mode
Reserved
Reserved
R
W
Reset 0 u u u u u u u u u 0 0 u u u 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARQOS_regulation_read
AWQOS_regulation_write
AW_OT_regulation
AR_OT_regulation
Reserved
Reset u u u u u u u u u u u u 0 0 0 0
10.3.11.4 Fields
Field Function
31 QoS regulation disabled
QoS_regulation Determines whether this CCI-400 implementation supports QoS regulation.
_disabled 0b - QoS regulation fully supported as described in this document. See Quality of Service.
1b - QoS regulation not supported, reads and writes to this register have no effect.
30-22 Reserved
—
21 Bandwidth regulation mode
Bandwidth_regul Sets the mode for bandwidth regulation:
ation_mode 0b - Normal mode. The QoS value is stable when the master is idle.
1b - Quiesce High mode. The QoS value tends to the maximum when the master is idle.
20 ARQOS regulation mode
Configures the mode of the QoS value regulator for read transactions:
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 383
register descriptions
Field Function
ARQOS_regulati 0b - Latency mode.
on_mode 1b - Period mode, for bandwidth regulation.
19-17 Reserved
—
16 AWQOS_regulation_mode
AWQOS_regulat Configures the mode of the QoS value regulator for write transactions:
ion_mode 0b - Latency mode.
1b - Period mode, for bandwidth regulation.
15-4 Reserved
—
3 AR_OT_regulation
AR_OT_regulati Enable regulation of outstanding read transactions for slave interfaces
on
• ACE-Lite interfaces only, for example S0, S1, and S2.
• RAZ/WI for ACE interfaces, for example S3 and S4.
2 AW_OT_regulation
AW_OT_regulati Enable regulation of outstanding write transactions for slave interfaces
on
• ACE-Lite interfaces only, for example S0, S1, and S2.
• RAZ/WI for ACE interfaces, for example S3 and S4.
1 ARQOS regulation read
ARQOS_regulati Enable QoS value regulation on reads for slave interfaces
on_read
0 AWQOS regulation write
AWQOS_regulat Enable QoS value regulation on writes for slave interfaces
ion_write
10.3.12 Max OT Registers (Max_OT_Register_S0 - Max_OT_R
egister_S4)
10.3.12.1 Offset
For a = 0 to 4:
Register Offset
Max_OT_Register_Sa 1110h + (a × 1000h)
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
384 NXP Semiconductors
Chapter 10 Cache Coherent Interconnect (CCI-400)
10.3.12.2 Function
The Max OT registers determine how many outstanding transactions are permitted when
the OT regulator is enabled for each ACE-Lite slave interface. One register exists for
each of the S0, S1, and S2 slave interfaces. A value of 0 for both the integer and
fractional parts disables the programmable regulation so that the hardware limits apply. A
value of 0 for the fractional part disables the regulation of fractional outstanding
transactions. If int is the value of the integer part and frac is the value of the fractional
part, then: Maximum mean number of outstanding transactions = int + frac/256.
Setting the maximum outstanding transaction size greater than that configured in the
RTL, using the R_MAX or W_MAX parameters, has no effect. Accessible using only
Secure accesses, unless you set the Secure Access Register. See Secure Access Register
bit assignments.
Available in all CCI-400 configurations.
10.3.12.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Frac_OT_AR
Int_OT_AR
Reserved
Reset u u 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Frac_OT_AW
Int_OT_AW
Reserved
Reset u u 0 0 0 0 0 0 0 0 0 0 0 0 0 0
10.3.12.4 Fields
Field Function
31-30 Reserved
—
29-24 Int_OT_AR
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 385
register descriptions
Field Function
Int_OT_AR Integer part of the maximum outstanding AR addresses S0
23-16 Frac_OT_AR
Frac_OT_AR Fractional part of the maximum outstanding AR addresses S0
15-14 Reserved
—
13-8 Int_OT_AW
Int_OT_AW Integer part of the maximum outstanding AW addresses S0
7-0 Frac_OT_AW
Frac_OT_AW Fractional part of the maximum outstanding AW addresses S0
10.3.13 Regulator Target Registers (Target_Latency_Register_S0
- Target_Latency_Register_S4)
10.3.13.1 Offset
For a = 0 to 4:
Register Offset
Target_Latency_Register 1130h + (a × 1000h)
_Sa
10.3.13.2 Function
The Regulator Target registers determines the target, in cycles, for the regulation of reads
and writes. The target is either transaction latency or inter-transaction period, depending
on the programming of the QoS Control Register. A value of 0 corresponds to no
regulation. One register exists for each slave interface.
Accessible using only Secure accesses, unless you set the Secure Access Register. See
Secure Access Register bit assignments.
Only has an effect when QOSOVERRIDE is HIGH for the associated interface.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
386 NXP Semiconductors
Chapter 10 Cache Coherent Interconnect (CCI-400)
10.3.13.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved AR_Lat
W
Reset u u u u 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved AW_Lat
W
Reset u u u u 0 0 0 0 0 0 0 0 0 0 0 0
10.3.13.4 Fields
Field Function
31-28 Reserved
—
27-16 AR channel target latency
AR_Lat
15-12 Reserved
—
11-0 AW channel target latency
AW_Lat
10.3.14 QoS Range Register (Qos_Range_Register_S0 - Qos_
Range_Register_S4)
10.3.14.1 Offset
For a = 0 to 4:
Register Offset
Qos_Range_Register_Sa 1138h + (a × 1000h)
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 387
register descriptions
10.3.14.2 Function
The QoS Range register enables you to program the minimum and maximum values for
the ARQOS and AWQOS signals that the QV regulators generate. One register exists for
each slave interface.
Accessible using only Secure accesses, unless you set the Secure Access Register. See
Secure Access Register bit assignments.
Only has an effect when QOSOVERRIDE is HIGH for the associated interface.
10.3.14.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved Max_ARQOS Reserved Min_ARQOS
W
Reset u u u u 0 0 0 0 u u u u 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved Max_AWQOS Reserved Min_AWQOS
W
Reset u u u u 0 0 0 0 u u u u 0 0 0 0
10.3.14.4 Fields
Field Function
31-28 Reserved
—
27-24 Maximum ARQOS value
Max_ARQOS
23-20 Reserved
—
19-16 Minimum ARQOS value
Min_ARQOS
15-12 Reserved
—
11-8 Maximum AWQOS value
Max_AWQOS
7-4 Reserved
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
388 NXP Semiconductors
Chapter 10 Cache Coherent Interconnect (CCI-400)
Field Function
—
3-0 Minimum AWQOS value
Min_AWQOS
10.3.15 QoS Regulator Scale Factor Registers (Latency_Regulati
on_Register_S0 - Latency_Regulation_Register_S4)
10.3.15.1 Offset
For a = 0 to 4:
Register Offset
Latency_Regulation_Regi 2268h + (a × 1000h)
ster_Sa
10.3.15.2 Function
The QoS Regulator Scale Factor Registers characteristics are: Purpose QoS regulation
value, AWQOS or ARQOS, scale factor coded for powers of 2 in the range 2–5-2–12, to
match a 16-bit integrator. One register exists for each slave interface.
Accessible using only Secure accesses, unless you set the Secure Access Register. See
Secure Access Register bit assignments.
Only has an effect when QOSOVERRIDE is HIGH for the associated interface.
The table here shows the mapping of Scale Factor Register value to the scale factor.
Table 10-4. Mapping of Scale Factor Register value to Regulator scale factor
Scale Factor Register value Scale factor
0x0 2–5
0x1 2–6
0x2 2–7
0x3 2–8
0x4 2–9
0x5 2–10
0x6 2–11
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 389
register descriptions
Table 10-4. Mapping of Scale Factor Register value to Regulator scale factor (continued)
0x7 2–12
10.3.15.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset u u u u u u u u u u u u u u u u
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AW_Scale_Fact
AR_Scale_Fact
Reserved
Reserved
W
Reset u u u u u 0 0 0 u u u u u 0 0 0
10.3.15.4 Fields
Field Function
31-11 Reserved
—
10-8 ARQOS Scale Factor
AR_Scale_Fact ARQOS scale factor, power of 2 in the range 2–5-2–12.
7-3 Reserved
—
2-0 AWQOS Scale Factor
AW_Scale_Fact AWQOS scale factor, power of 2 in the range 2–5-2–12.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
390 NXP Semiconductors
Chapter 11
Arm CoreLink™ TrustZone Address Space
Controller TZC-380
11.1 Introduction
This chapter introduces the CoreLink TrustZone Address Space Controller (TZC-380).
11.1.1 Overview
The TZASC is an advanced microcontroller bus architecture (AMBA) compliant system-
on-chip (SoC) peripheral. It is a high-performance, area-optimized address space
controller with on-chip AMBA bus interfaces that conform to the AMBA advanced
eXtensible interface (AXI) protocol and the AMBA advanced peripheral bus (APB)
protocol.
The TZASC can be configured to provide the optimum security address region control
functions required for intended application. See Features for a summary of the
configurable features supported.
NOTE
The software should configure the TZASC bypass mux
(csu_sa1[2-3]) to disable the bypass operation and use the
TZASC default region before any transaction goes to DDR.
The figure below shows the TZASC in an example system:
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 391
Miscellaneous signal descriptions
TZASC-380
Core
Address
DDR controller
CCI-400 Region Control
Other
initiators
MUX
csu_sa1[2-3]
Figure 11-1. Example system
11.1.1.1 Features
The TZASC provides the following features:
• Programs security access permissions for each address region
• Transfers data between master and slave only if the security status of the AXI
transaction matches the security settings of the memory region it addresses
• Prevents write access to various registers after assertion of secure_boot_lock, which
is controlled by the CSU_SA1[4:5] bit. Refer CSU Memory Map/Register Definition
for details.
The number of address regions can be configured to:
• 2 regions
• 4 regions
• 8 regions
• 16 regions.
11.2 Miscellaneous signal descriptions
There are two miscellaneous signals provided by TZASC:
• secure_boot_lock. The assertion of this signal is controlled by the CSU_SA1[4:5]
bit. Refer CSU Memory Map/Register Definition for details.
• tzasc_int. The assertion of this signals is controlled by the TZASC interrupt (#125).
Refer Internal interrupt sources for details.
The figure below shows the signals provided by the TZASC:
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
392 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
secure_boot_lock TZASC tzasc_int
Figure 11-2. Miscellaneous signals
Asserting secure_boot_lock enhances the security of the TZASC. See Preventing writes
to registers and using secure_boot_lock.
You can program the TZASC to assert tzasc_int when it denies an AXI master access to a
region. See Denied AXI transactions.
11.3 Functional description
This chapter describes the TZASC operation. It contains the following sections:
• Functional operation
• Constraints of use
11.3.1 Functional operation
The TZASC performs security checks on AXI accesses to memory and DDR memory
space. This supports configurable number of regions. Each region is programmable for
size, base address, enable, and security parameters. Using the secure_boot_lock, the
programmers view can be locked to prevent erroneous writes. See Preventing writes to
registers and using secure_boot_lock. The TZASC provides programmability in reporting
faults using AXI response channel and interrupt.
Memory
AXI TZC-380 AXI SDRAM
controller
AXI
AXI Interconnect
master
AXI to APB
AXI bridge APB
Figure 11-3. Functional operation of TZASC
NOTE
The CoreLink TrustZone Address Space Controller (TZC-380)
Supplement to AMBA Designer (ADR-301) User Guide
provides information about how to configure the controller.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 393
Functional description
11.3.1.1 Regions
A region is a contiguous area of address space. The TZASC provides each region with a
programmable security permissions field. The security permissions value is used to
enable the TZASC to either accept or deny a transaction access to that region. The
transaction's secure vs non-secure attributes are used to determine the security settings of
that transaction.
The TZASC always provides two regions, region 0 and region 1, and you can configure it
to provide additional regions. With the exception of region 0, the TZASC enables you to
program the following operating parameters for each region:
• Region enable.
• Security permissions.
• Base address.
• Size. The minimum address size of a region is 32KB.
• Subregion disable. See Subregions.
NOTE
Region 0 is known as the background region because it
occupies the total memory space. You can program the security
permissions of region 0, but the following parameters are fixed:
• Base address:0x0
• Size:The AXI_ADDRESS_MSB configuration parameter
controls the address range of the TZASC, and therefore the
region size.
• Subregion disable:This feature is not available for region
0.
11.3.1.2 Priority
The priority of a region is fixed and is determined by the region number. Figure 11-4
shows how the priority of a region increases with the region number.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
394 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
Region n–1
.
.
. Priority
Region 2 level
Region 1
Region 0
Figure 11-4. Region priority
When a transaction is received, its address is checked for a match with all the configured
regions in turn. The order in which the regions are checked is determined by the priority
level, the highest priority level is first. The first region that matches the transaction
address match is used as the matching region. The matching regions security permission
determines whether the transaction is permitted.
11.3.1.3 Subregions
The TZASC divides each region into eight equal-sized, non-overlapping subregions.
Figure 11-5 shows the subregions for an example region that is programmed to occupy an
address span of 32KB.
0x7FFF
Subregion 7
0x6FFF
Subregion 6
0x5FFF
Subregion 5
0x4FFF
Region Subregion 4
that
0x3FFF
spans
32KB Subregion 3
0x2FFF
Subregion 2
0x1FFF
Subregion 1
0x0FFF
Subregion 0
Figure 11-5. Subregion example
11.3.1.4 Subregion disable
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 395
Functional description
With the exception of region 0, you can program the TZASC to disable any or all of the
eight subregions that comprise a region. When a subregion is disabled, the security
permissions for its address range are provided by the next highest priority region that
overlaps the address range.
Example configuration for subregion disable
Figure 11-6 shows an example configuration that supports four regions, where:
• region 2 and region 3 are partially overlapped
• region 1 and region 3 are partially overlapped
• region 0 is overlapped with all regions.
With some subregions of region 1, region 2, and region 3 are disabled, and the resulting
region permissions of the entire address space is shown in the Figure 11-6.
Priority
Region
Region 3 Region 2 Region 1 Region 0 permissions
AXI_ADDRESS_MSB
parameter controls
the size of region 0
sp2
Disabled sp0
sp3
Disabled sp2
sp3
Disabled sp0
Disabled
sp1
sp3
sp1
Disabled sp0
sp1
0x0
Figure 11-6. Subregion disable example
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
396 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
NOTE
In Figure 11-6
• all subregions are enabled unless otherwise stated
• spn represents the region permissions of region n .
11.3.1.5 Region security permissions
The TZASC enables you to program the security access permissions for any region that it
is configured. A region is assigned a security permissions field, sp<n>, in its
region_attributes_<n> Register that enables you to have complete control of the
permissions for that region. See register descriptions.
Security inversion
There are two modes of operation for the region security permissions, with or without
security inversion.
By default, if you program a region to support non-secure accesses, the TZASC ensures
that region must also support secure accesses. For example, if you program the region
permissions for region 3 to be non-secure read only, the TZASC permits access to region
3 for secure reads and non-secure reads.
If you require that some regions are not accessible to masters in Secure state, but are
accessible in Non-secure state, then you must enable security inversion.
See Region security permissions and Security Inversion Register (security_inversion_en)
for more information.
Programming security permissions when security inversion is disabled
By default, security inversion is disabled and therefore the TZASC only permits you to
program certain combinations of security permissions. These combinations ensure that a
master in Secure state is not denied access to a region that is programmed to only accept
non-secure accesses. Table 11-1 shows the possible security permissions when security
inversion is disabled.
Table 11-1. Region security permissions when security inversion is disabled
sp<n> field controls if the TZASC permits access for the following AXI transactions
sp<n> field1 Secure read Secure write Non-secure read Non-secure write
b0000 No No No No
b0100 No Yes No No
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 397
Functional description
Table 11-1. Region security permissions when security inversion is disabled (continued)
b0001, b0101 No Yes No Yes
b1000 Yes No No No
b0010, b1010 Yes No Yes No
b1100 Yes Yes No No
b1001, b1101 Yes Yes No Yes
b0110, b1110 Yes Yes Yes No
b0011, b0111, b1011, Yes Yes Yes Yes
b1111
1. See Region Attributes 0 Register (region_attributes_0) for programming information.
Programming security permissions when security inversion is enabled
If you enable security inversion, the TZASC permits you to program any combination of
security permissions as Table 11-2 shows.
Table 11-2. Region security permissions when security inversion is enabled
sp<n> field controls if the TZASC permits access for the following AXI transactions
sp<n> field1 Secure read Secure write Non-secure read Non-secure write
b0000 No No No No
b0001 No No No Yes
b0010 No No Yes No
b0011 No No Yes Yes
b0100 No Yes No No
b0101 No Yes No Yes
b0110 No Yes Yes No
b0111 No Yes Yes Yes
b1000 Yes No No No
b1001 Yes No No Yes
b1010 Yes No Yes No
b1011 Yes No Yes Yes
b1100 Yes Yes No No
b1101 Yes Yes No Yes
b1110 Yes Yes Yes No
b1111 Yes Yes Yes Yes
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
398 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
1. See Region Attributes 0 Register (region_attributes_0) for programming information.
Table 11-3 shows a typical example of memory map along with the register
programming. The TZASC is configured to have 16 regions.
Table 11-3. Typical example of memory map along with the register programming
Region Region1 Lock Starting Region size Region size Sp2 Description
address
Region_0 Enable No 0x0 max - 1100 Secure Read
(Default) Write access
(RW).
Region_1 Enable No 0x0 64MB b011001 1111 Non-secure
Read or Write
access (R/W),
Secure R/W.
Region_2 Enable No 0x0 16MB b010111 1110 Non-secure
Read Only
access (RO),
Secure RW
for the normal
world OS
kernel.
Region_3 Enable No 0x3D00000 512KB b010010 1111 Regularly
switched Non-
secure, or
Secure RW
for a more
complex
shared
memory
buffers.
Region_4 Enable No 0x3D80000 512KB b010010 1100 Non-secure
No Access
(NA), Secure
RW, a
dedicated
area for
secure LCD
Controller
frame buffer.
Region_5 Enable No 0x80000000 32KB b001110 1111 Non-secure
RW, Secure
RW for
address range
of general
peripherals
such as
screen
control, and
keyboard
hardware.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 399
Functional description
Table 11-3. Typical example of memory map along with the register programming
(continued)
Region_6 Enable Yes 0x3C00000 512KB b010010 1011 Non-secure
RW, Secure
RO for
streaming
from the
normal world
to the secure
world.
Region_7 Enable Yes 0x3C80000 512KB b010010 1110 Non-secure
RO, Secure
RW for
streaming
from the
secure world
to the normal
world.
Region_8 Enable Yes 0x3E00000 512KB b010010 1000 Non-secure
NA, Secure
RO for the
secure world
OS kernel.
Region_9 Enable Yes 0x3E80000 512KB b010010 1100 Non-secure
NA, Secure
RW for the
secure world
OS
applications,
heap, and
stacks.
Region_10 Enable Yes 0x3F00000 1MB b010011 1100 Non-secure
NA, Secure
RW for
Secure world
OS
applications,
heap, and
stacks.
Region_11 Enable Yes 0x80008000 32KB b001110 1100 Non-secure
3 NA, Secure
RW for
address range
of secure
peripherals
such as
Random
Number
Generator
(RNG), and
cryptography
support
hardware.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
400 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
Table 11-3. Typical example of memory map along with the register programming
(continued)
Region_12 Enable Yes 0xF0000000 256MB b011011 0011 Non-secure
RW, Secure
NA for FLASH
holding
normal world
OS plus disk.
Region_13 Enable Yes 0xF0000000 1MB b010011 1100 Non-secure
NA, Secure
RW for
FLASH for
secure boot,
secure world
OS, secure
configuration
details.
Region_14 Disable - - - - - -
Region_15 Disable - - - - - -
1. Region can be either Enable or Disable.
2. Security Permission (sp).
3. In a more typical system, these devices would be protected by a TrustZone Protection Controller (BP147), and associated
TrustZone aware AXI to APB Bridges (BP135).
NOTE
The implementers system design, and security requirements are
taken into account for this example. And any actual software
programming must depend on the system where TZASC is
plugged.
11.3.1.6 Denied AXI transactions
If an AXI transaction has insufficient security privileges then for:
• Reads:The TZASC responds to the master by setting all bits of the read data bus to
zero.
NOTE
If the TZASC is programmed to perform speculative
accesses, it discards the data that it receives on read data.
• Writes:The TZASC prevents the transfer of data from the master to the slave by
discarding the data of write data bus. If you program the TZASC to perform
speculative accesses, it modifies the transfer to the slave by setting all bits of the:
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 401
Functional description
• write data bus to zero
• write data strobe to zero.
NOTE
The action Register controls whether the TZASC signals to
the master when a region permission failure occurs, and if
so, the type of response it provides. See Action register
(action).
11.3.1.7 Speculative accesses
By default, the TZASC performs read or write speculative accesses that means it
forwards an AXI transaction address to a slave, before it verifies that the AXI transaction
is permitted to read address or write address respectively.
The TZASC only permits the transfer of data between its AXI bus interfaces, after
verifying the access that the read or write access is permitted respectively. If the
verification fails, then it prevents the transfer of data between the master and slave as
Denied AXI transactions describes.
You can disable speculative accesses by programming the speculation_control Register.
See Speculation Control Register (speculation_control). When speculative accesses are
disabled, the TZASC verifies the permissions of the access before it forwards the access
to the slave. If the TZASC:
• Permits the access, it commences an AXI transaction to the slave, and it adds one
clock latency.
• Denies the access, it prevents the transfer of data between the master and slave as
Denied AXI transactions describes. In this situation, the slave is unaware when the
TZASC prevents the master from accessing the slave.
NOTE
Enabling speculative access is a potential security risk, if the
device that is being protected reacts to this transaction. Most
devices do not have to react to this level of access, and
speculative access is much faster than validating the address
before issuing the transaction.
11.3.1.8 Preventing writes to registers and using secure_boot_lock
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
402 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
By suitably programming lockdown Register, see Lockdown Select Register (lockdown_
select), and asserting secure_boot_lock signal makes the following registers read only:
• speculation_control Register. See Speculation Control Register (speculation_cont
rol).
• security_inversion_en Register. See Security Inversion Register (security_inversion_
en).
• lockdown_range Register. See Lockdown Range Register (lockdown_range).
Locking down the region using lockdown_range and lockdown_select registers
By programming the lockdown_select, and lockdown_range registers, and asserting the
secure_boot_lock signal, you can lockdown the behavior of the TZASC so that it
prevents unintentional or erroneous write to the regions specified in the lockdown_range
Register. However, read access to those regions is permitted:
• region_setup_low_<n> Register. See Region Setup Low 0 Register (region_setup_
low_0)
• region_setup_high_<n> Register. See Region Setup High 0 Register (region_setup_
high_0)
• region_attributes_<n> Register. See Region Attributes 0 Register (region_attributes_
0).
The TZASC expects the secure_boot_lock signal to be asserted for at least one clock
cycle. One clock after the secure_boot_lock is sampled HIGH by TZASC, then the
registers mentioned in Locking down the region using lockdown_range and
lockdown_select registers cannot be written, unless the TZASC is reset by asserting
aresetn.
11.3.1.9 Using locked transaction sequences
If a master performs locked transaction sequences, a transaction might stall, or an AXI
protocol violation might occur when:
Transaction sequence crosses a 4 KB boundary
If a locked transaction sequence crosses a 4 KB boundary and the regions have different
region permissions, the TZASC might prevent access to the second region and therefore
the slave would not receive the latter part of the locked transaction sequence.
NOTE
The AXI protocol recommends that locked transaction
sequences do not cross a 4 KB address boundary.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 403
Functional description
Secure state change
During a locked transaction sequence, if a master changes the state of secure and non-
secure attributes and the region has different region permissions for Secure state and
Non-secure state, the TZASC might deny a transaction and therefore the slave would not
receive the latter part of the locked transaction sequence.
Reads and writes
During a locked transaction sequence, if a master performs reads and writes to a region,
depending on the region permissions, the TZASC might deny a transaction and therefore
the slave would not receive the latter part of the locked transaction sequence.
11.3.1.10 Using exclusive accesses
If a master performs exclusive accesses to an address region, you must program the
TZASC to permit read and write accesses to that address region, for the expected settings
of secure and non-secure attributes, otherwise the read or write transaction might fail.
11.3.2 Constraints of use
The TZASC has the following considerations relating to change in programmers view on
an active system:
• When changing the setting of a TZASC region,
• The current accepted AXI transaction, if it falls into that region, would act
according to the previous settings for that region.
• Any other outstanding AXI transactions, that falls into that region, would effect
by the new settings for that region.
• Given little ability to predict that the mentioned AXI transactions would effect, it is
obviously desirable that there are no outstanding AXI transactions when a regions
setting are changed.
• In simple systems this can potentially be achieved by the core not accessing the
given region during the period of the cores transition between security states.
Even in these cases, the status of cached data and instructions needs to be
considered.
• In more complicated systems the code that changes the TZASC region settings
must have to inform other AXI bus masters to desist or complete acting on that
region before performing the region setting changes. After having such an action
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
404 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
acknowledged the code must also have to instigate a suitable delay before then
acting.
An example of this can be an LCD controller dealing with a frame buffer that is
switching between a Normal world and Secure world use.
NOTE
There is no direct mechanism to ascertain if there are any
outstanding AXI transactions, and so the designer must use
their system knowledge to apply reasonable mechanisms.
It is recommended that any DECERR, or TZASC interrupt handler is designed to expect,
and potentially ignore events generated under these circumstances.
11.4 register descriptions
The following information applies to the TZASC registers:
• The base address of the TZASC is not fixed, and can be different for any particular
system implementation. The offset of each register from the base address is fixed.
• Do not attempt to access reserved or unused address locations. Attempting to access
these location can result in Unpredictable behavior of the TZASC.
• Unless otherwise stated in the accompanying text:
• do not modify undefined register bits
• ignore undefined register bits on reads
• all register bits are reset to a logic 0 by a system or power-on reset.
• For programming the registers, the TZASC supports data in word-invariant
endianness.
• System designers must ensure that only processors in Secure state can access the
registers, otherwise it can compromise the security of the system.
NOTE
See Constraints of use for more information about
considerations relating to change in programmers view on an
active system.
The TZASC register map consists of the following regions:
• Configuration, lockdown, and interrupt : Use these registers to determine the global
configuration of the TZASC, and control its operating state.
• Fail status : These registers provide information about an access that failed because
of insufficient permissions.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 405
register descriptions
• Control : Use these registers to enable the TZASC to perform security inversion or
speculative accesses.
• Region control : Use these registers to control the operating state of each region.
• Integration test : Use these registers when testing the integration of the TZASC in a
System-on-Chip (SoC).
• Component configuration : These registers enable the identification of system
components by software.
11.4.1 TZASC Memory map
Base address: 150_0000h
Offset Register Width Access Reset value
(In bits)
0h Configuration Register (configuration) 32 RO 0000_270Fh
4h Action register (action) 32 RW 0000_0001h
8h Lockdown Range Register (lockdown_range) 32 RW 0000_0000h
Ch Lockdown Select Register (lockdown_select) 32 RW 0000_0000h
10h Interrupt Status Register (int_status) 32 RO 0000_0000h
14h Interrupt Clear Register (int_clear) 32 WO 0000_0000h
20h Fail Address Low Register (fail_address_low) 32 RO 0000_0000h
24h Fail Address High Register (fail_address_high) 32 RO 0000_0000h
28h Fail Control Register (fail_control) 32 RO 0000_0000h
2Ch Fail ID Register (fail_id) 32 RO 0000_0000h
30h Speculation Control Register (speculation_control) 32 RW 0000_0000h
34h Security Inversion Register (security_inversion_en) 32 RW 0000_0000h
100h Region Setup Low 0 Register (region_setup_low_0) 32 RO 0000_0000h
104h Region Setup High 0 Register (region_setup_high_0) 32 RO 0000_0000h
108h Region Attributes 0 Register (region_attributes_0) 32 RW C000_0000h
110h Region Setup Low 1 Register (region_setup_low_1) 32 RO 0000_0000h
114h Region Setup High 1 Register (region_setup_high_1) 32 RO 0000_0000h
118h Region Attributes 1 Register (region_attributes_1) 32 RW 0000_001Ch
120h Region Setup Low 2 Register (region_setup_low_2) 32 RO 0000_0000h
124h Region Setup High 2 Register (region_setup_high_2) 32 RO 0000_0000h
128h Region Attributes 2 Register (region_attributes_2) 32 RW 0000_001Ch
130h Region Setup Low 3 Register (region_setup_low_3) 32 RO 0000_0000h
134h Region Setup High 3 Register (region_setup_high_3) 32 RO 0000_0000h
138h Region Attributes 3 Register (region_attributes_3) 32 RW 0000_001Ch
140h Region Setup Low 4 Register (region_setup_low_4) 32 RO 0000_0000h
144h Region Setup High 4 Register (region_setup_high_4) 32 RO 0000_0000h
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
406 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
Offset Register Width Access Reset value
(In bits)
148h Region Attributes 4 Register (region_attributes_4) 32 RW 0000_001Ch
150h Region Setup Low 5 Register (region_setup_low_5) 32 RO 0000_0000h
154h Region Setup High 5 Register (region_setup_high_5) 32 RO 0000_0000h
158h Region Attributes 5 Register (region_attributes_5) 32 RW 0000_001Ch
160h Region Setup Low 6 Register (region_setup_low_6) 32 RO 0000_0000h
164h Region Setup High 6 Register (region_setup_high_6) 32 RO 0000_0000h
168h Region Attributes 6 Register (region_attributes_6) 32 RW 0000_001Ch
170h Region Setup Low 7 Register (region_setup_low_7) 32 RO 0000_0000h
174h Region Setup High 7 Register (region_setup_high_7) 32 RO 0000_0000h
178h Region Attributes 7 Register (region_attributes_7) 32 RW 0000_001Ch
180h Region Setup Low 8 Register (region_setup_low_8) 32 RO 0000_0000h
184h Region Setup High 8 Register (region_setup_high_8) 32 RO 0000_0000h
188h Region Attributes 8 Register (region_attributes_8) 32 RW 0000_001Ch
190h Region Setup Low 9 Register (region_setup_low_9) 32 RO 0000_0000h
194h Region Setup High 9 Register (region_setup_high_9) 32 RO 0000_0000h
198h Region Attributes 9 Register (region_attributes_9) 32 RW 0000_001Ch
1A0h Region Setup Low 10 Register (region_setup_low_10) 32 RO 0000_0000h
1A4h Region Setup High 10 Register (region_setup_high_10) 32 RO 0000_0000h
1A8h Region Attributes 10 Register (region_attributes_10) 32 RW 0000_001Ch
1B0h Region Setup Low 11 Register (region_setup_low_11) 32 RO 0000_0000h
1B4h Region Setup High 11 Register (region_setup_high_11) 32 RO 0000_0000h
1B8h Region Attributes 11 Register (region_attributes_11) 32 RW 0000_001Ch
1C0h Region Setup Low 12 Register (region_setup_low_12) 32 RO 0000_0000h
1C4h Region Setup High 12 Register (region_setup_high_12) 32 RO 0000_0000h
1C8h Region Attributes 12 Register (region_attributes_12) 32 RW 0000_001Ch
1D0h Region Setup Low 13 Register (region_setup_low_13) 32 RO 0000_0000h
1D4h Region Setup High 13 Register (region_setup_high_13) 32 RO 0000_0000h
1D8h Region Attributes 13 Register (region_attributes_13) 32 RW 0000_001Ch
1E0h Region Setup Low 14 Register (region_setup_low_14) 32 RO 0000_0000h
1E4h Region Setup High 14 Register (region_setup_high_14) 32 RO 0000_0000h
1E8h Region Attributes 14 Register (region_attributes_14) 32 RW 0000_001Ch
1F0h Region Setup Low 15 Register (region_setup_low_15) 32 RO 0000_0000h
1F4h Region Setup High 15 Register (region_setup_high_15) 32 RO 0000_0000h
1F8h Region Attributes 15 Register (region_attributes_15) 32 RW 0000_001Ch
E00h Integration Test Control Register (itcrg) 32 RW 0000_0000h
E04h Integration Test Input Register (itip) 32 RO 0000_0000h
E08h Integration Test Output Register (itop) 32 RW 0000_0000h
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 407
register descriptions
11.4.2 Configuration Register (configuration)
11.4.2.1 Offset
Register Offset
configuration 0h
11.4.2.2 Function
The configuration Register provides information about the configuration of the TZASC.
There are no usage constraints. Available in all configurations of the TZASC.
11.4.2.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
address_width
no_of_regions
Reserved
Reserved
W
Reset 0 0 1 0 0 1 1 1 0 0 0 0 1 1 1 1
11.4.2.4 Fields
Field Function
31-14 Reserved, Should be Zero (SBZ).
—
13-8 address_width
address_width Returns the width of the AXI address bus. Read as:
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
408 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
Field Function
b000000-b011110 = reserved
b011111 = 32-bit
b100000 = 33-bit
b100001 = 34-bit
...
b111110 = 63-bit
b111111 = 64-bit.
7-4 Reserved, Should be Zero (SBZ).
—
3-0 no_of_regions
no_of_regions Returns the number of regions that the TZASC provides:
b0000 = reserved
b0001 = 2 regions
b0010 = 3 regions
b0011 = 4 regions
...
b1111 = 16 regions.
11.4.3 Action register (action)
11.4.3.1 Offset
Register Offset
action 4h
11.4.3.2 Function
The action Register controls the response signaling behavior of the TZASC to region
permission failures. There are no usage constraints.Available in all configurations of the
TZASC.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 409
register descriptions
11.4.3.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reaction_value
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
11.4.3.4 Fields
Field Function
31-2 Reserved, Should be Zero (SBZ).
—
1-0 reaction_value
reaction_value Controls how the TZASC uses the bresps[1:0], rresps[1:0], and tzasc_int signals when a region
permission failure occurs:
b00 = sets tzasc_int LOW and issues an OKAY response
b01 = sets tzasc_int LOW and issues a DECERR response
b10 = sets tzasc_int HIGH and issues an OKAY response
b11 = sets tzasc_int HIGH and issues a DECERR response.
11.4.4 Lockdown Range Register (lockdown_range)
11.4.4.1 Offset
Register Offset
lockdown_range 8h
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
410 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
11.4.4.2 Function
The lockdown_range Register controls the range of regions that are locked down.The
lockdown_select Register can restrict the access type of this register to RO. Available in
all configurations of the TZASC.
11.4.4.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
enable
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
lockdown_regions
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11.4.4.4 Fields
Field Function
31 enable
enable When set to 1, it enables the lockdown_regions field to control the regions that are to be locked.
30-4 Reserved, Should be Zero (SBZ).
—
3-0 lockdown_regions
lockdown_regio Controls the number of regions to lockdown when the enable bit is set to 1:
ns
b0000 = region no_of_regions–1 is locked
b0001 = region no_of_regions–1 to region no_of_regions–2 are locked
b0010 = region no_of_regions–1 to region no_of_regions–3 are locked
b0011 = region no_of_regions–1 to region no_of_regions–4 are locked
...
b1111 = region no_of_regions–1 to region no_of_regions–16 are locked.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 411
register descriptions
Field Function
no_of_regions is the value of the no_of_regions field in the configuration Register. See Configuration
Register.
NOTE: The value programmed in lockdown_range Register must not be greater than no_of_regions-1
else all regions are locked.
11.4.5 Lockdown Select Register (lockdown_select)
11.4.5.1 Offset
Register Offset
lockdown_select Ch
11.4.5.2 Function
The lockdown_select Register controls whether the TZASC permits write accesses to the
following registers:
• Lockdown Range Register
• Speculation Control Register
• Security Inversion Enable Register
After aresetn goes HIGH, the TZASC only permits write access to this register, if
secure_boot_lock remains LOW. When secure_boot_lock is HIGH for one aclk period,
or more then the TZASC ignores writes to this register.
This register is available in all configurations of the TZASC.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
412 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
11.4.5.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
acc_speculation_cntl
region_register
security_inv
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11.4.5.4 Fields
Field Function
31-3 Reserved, Should be Zero (SBZ).
—
2 acc_speculation_cntl
acc_speculation Modifies the access type of the speculation_control Register:
_cntl
0 = no effect. speculation_control Register remains RW.
1 = speculation_control Register is RO.
See Speculation Control Register for more information.
1 security_inv
security_inv Modifies the access type of the security_inversion_en Register:
0 = no effect. security_inversion_en Register remains RW.
1 = security_inversion_en Register is RO.
See Security Inversion Enable Register for more information.
0 region_register
region_register Modifies the access type of the lockdown_range Register:
0 = no effect. lockdown_range Register remains RW.
1 = lockdown_range Register is RO.
See Lockdown Range Register for more information.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 413
register descriptions
11.4.6 Interrupt Status Register (int_status)
11.4.6.1 Offset
Register Offset
int_status 10h
11.4.6.2 Function
The int_status register characteristics are: Returns the status of the interrupt. There are no
usage constraints. Available in all configurations of the TZASC.
11.4.6.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
overrun
Reserved
status
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11.4.6.4 Fields
Field Function
31-2 Reserved, Should be Zero (SBZ).
—
1 overrun
overrun When set to 1, it indicates the occurrence of two or more region permission failures since the interrupt
was last cleared
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
414 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
Field Function
0 status
status Returns the status of the interrupt:
0 = interrupt is inactive
1 = interrupt is active.
11.4.7 Interrupt Clear Register (int_clear)
11.4.7.1 Offset
Register Offset
int_clear 14h
11.4.7.2 Function
The int_clear Register clears the interrupt. There are no usage constraints. Available in all
configurations of the TZASC.
11.4.7.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W int_clear
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W int_clear
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 415
register descriptions
11.4.7.4 Fields
Field Function
31-0 int_clear
int_clear Writing any value to the int_clear Register sets the:
• status bit to 0 in the int_status Register
• overrun bit to 0 in the int_status Register.
See Interrupt Status register for details.
11.4.8 Fail Address Low Register (fail_address_low)
11.4.8.1 Offset
Register Offset
fail_address_low 20h
11.4.8.2 Function
The fail_address_low Register returns the address, the lower 32-bits, of the first access
that failed a region permission, after the interrupt was cleared. There are no usage
constraints. Available in all configurations of the TZASC.
11.4.8.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R add_status_low
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R add_status_low
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
416 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
11.4.8.4 Fields
Field Function
31-0 add_status_low
add_status_low Returns the AXI address bits [31:0] of the first access to fail a region permission check after the interrupt
was cleared.
11.4.9 Fail Address High Register (fail_address_high)
11.4.9.1 Offset
Register Offset
fail_address_high 24h
11.4.9.2 Function
The fail_address_high Register returns the address, the upper 32-bits, of the first access
that failed a region permission, after the interrupt was cleared. There are no usage
constraints. Only available when the TZASC has an AXI address width of greater than 32
bits.
11.4.9.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R add_status_high
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R add_status_high
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 417
register descriptions
11.4.9.4 Fields
Field Function
31-0 add_status_high
add_status_high Returns the address bits [AXI_ADDRESS_MSB:32] of the first access to fail a region permission check
after the interrupt was cleared. The size of this bitfield varies as [n:0} where n = AXI_ADDRESS_MSB–
32..
11.4.10 Fail Control Register (fail_control)
11.4.10.1 Offset
Register Offset
fail_control 28h
11.4.10.2 Function
The fail_control Register returns the control status information of the first access that
failed a region permission, after the interrupt was cleared. There are no usage constraints.
Available in all configurations of the TZASC.
11.4.10.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
stky_write_reg
nonsecure
privileged
Reserved
Reserved
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
418 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
11.4.10.4 Fields
Field Function
31-25 Reserved, Should be Zero (SBZ).
—
24 stky_write_reg
stky_write_reg This bit indicates whether the first access to fail a region permission check was a write or read as:
0 = read access
1 = write access.
23-22 Reserved, Should be Zero (SBZ).
—
21 nonsecure
nonsecure After clearing the interrupt status, this bit indicates whether the first access to fail a region permission
check was non-secure. Read as:
0 = secure access
1 = non-secure access.
20 privileged
privileged After clearing the interrupt status, this bit indicates whether the first access to fail a region permission
check was privileged. Read as:
0 = unprivileged access
1 = privileged access.
19-0 Reserved, Should be Zero (SBZ).
—
11.4.11 Fail ID Register (fail_id)
11.4.11.1 Offset
Register Offset
fail_id 2Ch
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 419
register descriptions
11.4.11.2 Function
The fail_id Register returns the master AXI ID of the first access that failed a region
permission, after the interrupt was cleared. There are no usage constraints. Available in
all configurations of the TZASC.
11.4.11.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R fail_id
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11.4.11.4 Fields
Field Function
31-12 Reserved, Should be Zero (SBZ).
—
11-0 fail_id
fail_id Returns the master AXI ID of the first access to fail a region permission check after the interrupt was
cleared. The size of this bit field is [n:0] where n = AID_WIDTH-1.
11.4.12 Speculation Control Register (speculation_control)
11.4.12.1 Offset
Register Offset
speculation_control 30h
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
420 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
11.4.12.2 Function
The speculation_control Register controls the read access speculation and write access
speculation. The lockdown_select Register can restrict the access type of this register to
RO. See Lockdown Select Register for more details. Available in all configurations of the
TZASC.
11.4.12.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
read_speculation
write_speculation
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11.4.12.4 Fields
Field Function
31-2 Reserved, Should be Zero (SBZ).
—
1 write_speculation
write_speculatio Controls the write access speculation:
n
0 = write access speculation is enabled. This is the default.
1 = write access speculation is disabled.
0 read_speculation
read_speculatio Controls the read access speculation:
n
0 = read access speculation is enabled. This is the default.
1 = read access speculation is disabled.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 421
register descriptions
11.4.13 Security Inversion Register (security_inversion_en)
11.4.13.1 Offset
Register Offset
security_inversion_en 34h
11.4.13.2 Function
The security_inversion_en Register controls whether the TZASC enables security
inversion to occur. Usage constraints The lockdown_select Register can restrict the
access type of this register to RO. See Lockdown Select Register for more details.
Available in all configurations of the TZASC.
11.4.13.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
security_inversion_en
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
422 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
11.4.13.4 Fields
Field Function
31-1 Reserved, Should be Zero (SBZ).
—
0 security_inversion_en
security_inversio Controls whether the TZASC permits security inversion to occur:
n_en
0 = security inversion is not permitted. This is the default.
1 = security inversion is permitted. This enables a region to be accessible to masters in Non-secure state
but not accessible to masters in Secure state.
11.4.14 Region Setup Low 0 Register (region_setup_low_0)
11.4.14.1 Offset
Register Offset
region_setup_low_0 100h
11.4.14.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R base_address_low0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
base_address_low0
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 423
register descriptions
11.4.14.3 Fields
Field Function
31-15 base_address_low0
base_address_l Controls the base address [31:15] of region n. For region 0, this field is Read Only (RO). The TZASC sets
ow0 the base address of region 0 to 0x0.
The TZASC only permits a region to start at address 0x0, or at a multiple of its region size. For example,
if the size of a region is 512MB, and it is not at address 0x0, the only valid settings for this field are:
b00100000000000000
b01000000000000000
b01100000000000000
b10000000000000000
b10100000000000000
b11000000000000000
b11100000000000000
If you attempt to set an inappropriate base address for the size of the region, the TZASC ignores certain
bits depending on the region size. See Table on register size for more information.
14-0 Reserved, Should be Zero (SBZ).
—
11.4.15 Region Setup High 0 Register (region_setup_high_0)
11.4.15.1 Offset
Register Offset
region_setup_high_0 104h
11.4.15.2 Function
The region_setup_high register is none for region 0, for other regions it controls the base
address [63:32] of region n.There are no usage constraints. Available in all configurations
of the TZASC.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
424 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
11.4.15.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R base_address_high0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R base_address_high0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11.4.15.4 Fields
Field Function
31-0 base_address_high0
base_address_h Controls the base address [63:32] of region n. For region 0, this field is RO. The TZASC sets the base
igh0 address of region 0 to 0x0.
The TZASC only permits a region to start at address 0x0, or at a multiple of its region size. If you program
a region size to be 8GB or more, then the TZASC might ignore certain bits depending on the region size.
11.4.16 Region Attributes 0 Register (region_attributes_0)
11.4.16.1 Offset
Register Offset
region_attributes_0 108h
11.4.16.2 Function
The region_attributes_0 register controls the permissions for region 0. There are no usage
constraints. Available in all configurations of the TZASC.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 425
register descriptions
11.4.16.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
sp0 Reserved
W
Reset 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11.4.16.4 Fields
Field Function
31-28 sp0
sp0 Permissions setting for region n. If an AXI transaction occurs to region n, the value in the spn field
controls whether the TZASC permits the transaction to proceed.
27-0 Reserved, Should be Zero (SBZ).
—
11.4.17 Region Setup Low 1 Register (region_setup_low_1)
11.4.17.1 Offset
Register Offset
region_setup_low_1 110h
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
426 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
11.4.17.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R base_address_low1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
base_address_low1
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11.4.17.3 Fields
Field Function
31-15 base_address_low1
base_address_l Controls the base address [31:15] of region n. For region 0, this field is Read Only (RO). The TZASC sets
ow1 the base address of region 0 to 0x0.
The TZASC only permits a region to start at address 0x0, or at a multiple of its region size. For example,
if the size of a region is 512MB, and it is not at address 0x0, the only valid settings for this field are:
b00100000000000000
b01000000000000000
b01100000000000000
b10000000000000000
b10100000000000000
b11000000000000000
b11100000000000000
If you attempt to set an inappropriate base address for the size of the region, the TZASC ignores certain
bits depending on the region size. See Table on register size for more information.
14-0 Reserved, Should be Zero (SBZ).
—
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 427
register descriptions
11.4.18 Region Setup High 1 Register (region_setup_high_1)
11.4.18.1 Offset
Register Offset
region_setup_high_1 114h
11.4.18.2 Function
The region_setup_high register is none for region 0, for other regions it controls the base
address [63:32] of region n.There are no usage constraints. Available in all configurations
of the TZASC.
11.4.18.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R base_address_high1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R base_address_high1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11.4.18.4 Fields
Field Function
31-0 base_address_high1
base_address_h Controls the base address [63:32] of region n. For region 0, this field is RO. The TZASC sets the base
igh1 address of region 0 to 0x0.
The TZASC only permits a region to start at address 0x0, or at a multiple of its region size. If you program
a region size to be 8GB or more, then the TZASC might ignore certain bits depending on the region size.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
428 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
11.4.19 Region Attributes 1 Register (region_attributes_1)
11.4.19.1 Offset
Register Offset
region_attributes_1 118h
11.4.19.2 Function
The region_attributes_n register controls the permissions, region size, subregion disable,
and region enable. There are no usage constraints. Available in all configurations of the
TZASC.
Table 11-4. Region size
size<n> field Size of region <n> Base address [1] constraints
b000000-b001101 Reserved -
b001110 32KB -
b001111 64KB Bit [15] must be zero
b010000 128KB Bits [16:15] must be zero
b010001 256KB Bits [17:15] must be zero
b010010 512KB Bits [18:15] must be zero
b010011 1MB Bits [19:15] must be zero
b010100 2MB Bits [20:15] must be zero
b010101 4MB Bits [21:15] must be zero
b010110 8MB Bits [22:15] must be zero
b010111 16MB Bits [23:15] must be zero
b011000 32MB Bits [24:15] must be zero
b011001 64MB Bits [25:15] must be zero
b011010 128MB Bits [26:15] must be zero
b011011 256MB Bits [27:15] must be zero
b011100 512MB Bits [28:15] must be zero
b011101 1GB Bits [29:15] must be zero
b011110 2GB Bits [30:15] must be zero
b011111 4GB Bits [31:15] must be zero
b100000 8GB Bits [32:15] must be zero
b100001 16GB Bits [33:15] must be zero
b100010 32GB Bits [34:15] must be zero
b100011 64GB Bits [35:15] must be zero
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 429
register descriptions
Table 11-4. Region size (continued)
b100100 128GB Bits [36:15] must be zero
b100101 256GB Bits [37:15] must be zero
b100110 512GB Bits [38:15] must be zero
b100111 1TB Bits [39:15] must be zero
b101000 2TB Bits [40:15] must be zero
b101001 4TB Bits [41:15] must be zero
b101010 8TB Bits [42:15] must be zero
b101011 16TB Bits [43:15] must be zero
b101100 32TB Bits [44:15] must be zero
b101101 64TB Bits [45:15] must be zero
b101110 128TB Bits [46:15] must be zero
b101111 256TB Bits [47:15] must be zero
b110000 512TB Bits [48:15] must be zero
b110001 1PB Bits [49:15] must be zero
b110010 2PB Bits [50:15] must be zero
b110011 4PB Bits [51:15] must be zero
b110100 8PB Bits [52:15] must be zero
b110101 16PB Bits [53:15] must be zero
b110110 32PB Bits [54:15] must be zero
b110111 64PB Bits [55:15] must be zero
b111000 128PB Bits [56:15] must be zero
b111001 256PB Bits [57:15] must be zero
b111010 512PB Bits [58:15] must be zero
b111011 1EB Bits [59:15] must be zero
b111100 2EB Bits [60:15] must be zero
b111101 4EB Bits [61:15] must be zero
b111110 8EB Bits [62:15] must be zero
b111111 16EB Bits [63:15] must be zero
[1]The region_setup_low_<n> Register and region_setup_high_<n> Register contain the
base address. See Table 313 on page 318 and Table 314 on page 319.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
430 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
11.4.19.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
sp1 Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
subregion_disable1
Reserved
size1
en1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0
11.4.19.4 Fields
Field Function
31-28 sp1
sp1 Permissions setting for region n. If an AXI transaction occurs to region n, the value in the spn field
controls whether the TZASC permits the transaction to proceed.
27-16 Reserved, Should be Zero (SBZ).
—
15-8 subregion_disable1
subregion_disab Regions are split into eight equal-sized sub-regions, and each bit enables the corresponding subregion to
le1 be disabled:
Bit [15] = 1 Subregion 7 is disabled.
Bit [14] = 1 Subregion 6 is disabled.
Bit [13] = 1 Subregion 5 is disabled.
Bit [12] = 1 Subregion 4 is disabled.
Bit [11] = 1 Subregion 3 is disabled.
Bit [10] = 1 Subregion 2 is disabled.
Bit [9] = 1 Subregion 1 is disabled.
Bit [8] = 1 Subregion 0 is disabled.
7 Reserved, Should be Zero (SBZ).
—
6-1 size1
size1
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 431
register descriptions
Field Function
Size of region n.The AXI address width, that is AXI_ADDRESS_MSB+1, controls the upper limit value of
this field.
The table below shows how the size n field controls the region size and what constraints, if any, the
TZASC applies to the base address to ensure that a region starts on the boundary of the region size.
0 en1
en1 Enable for region n:
0 = region n is disabled
1 = region n is enabled.
11.4.20 Region Setup Low 2 Register (region_setup_low_2)
11.4.20.1 Offset
Register Offset
region_setup_low_2 120h
11.4.20.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R base_address_low2
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
base_address_low2
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
432 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
11.4.20.3 Fields
Field Function
31-15 base_address_low2
base_address_l Controls the base address [31:15] of region n. For region 0, this field is Read Only (RO). The TZASC sets
ow2 the base address of region 0 to 0x0.
The TZASC only permits a region to start at address 0x0, or at a multiple of its region size. For example,
if the size of a region is 512MB, and it is not at address 0x0, the only valid settings for this field are:
b00100000000000000
b01000000000000000
b01100000000000000
b10000000000000000
b10100000000000000
b11000000000000000
b11100000000000000
If you attempt to set an inappropriate base address for the size of the region, the TZASC ignores certain
bits depending on the region size. See Table on register size for more information.
14-0 Reserved, Should be Zero (SBZ).
—
11.4.21 Region Setup High 2 Register (region_setup_high_2)
11.4.21.1 Offset
Register Offset
region_setup_high_2 124h
11.4.21.2 Function
The region_setup_high register is none for region 0, for other regions it controls the base
address [63:32] of region n.There are no usage constraints. Available in all configurations
of the TZASC.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 433
register descriptions
11.4.21.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R base_address_high2
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R base_address_high2
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11.4.21.4 Fields
Field Function
31-0 base_address_high2
base_address_h Controls the base address [63:32] of region n. For region 0, this field is RO. The TZASC sets the base
igh2 address of region 0 to 0x0.
The TZASC only permits a region to start at address 0x0, or at a multiple of its region size. If you program
a region size to be 8GB or more, then the TZASC might ignore certain bits depending on the region size.
11.4.22 Region Attributes 2 Register (region_attributes_2)
11.4.22.1 Offset
Register Offset
region_attributes_2 128h
11.4.22.2 Function
The region_attributes_n register controls the permissions, region size, subregion disable,
and region enable. There are no usage constraints. Available in all configurations of the
TZASC.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
434 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
Table 11-5. Region size
size<n> field Size of region <n> Base address [1] constraints
b000000-b001101 Reserved -
b001110 32KB -
b001111 64KB Bit [15] must be zero
b010000 128KB Bits [16:15] must be zero
b010001 256KB Bits [17:15] must be zero
b010010 512KB Bits [18:15] must be zero
b010011 1MB Bits [19:15] must be zero
b010100 2MB Bits [20:15] must be zero
b010101 4MB Bits [21:15] must be zero
b010110 8MB Bits [22:15] must be zero
b010111 16MB Bits [23:15] must be zero
b011000 32MB Bits [24:15] must be zero
b011001 64MB Bits [25:15] must be zero
b011010 128MB Bits [26:15] must be zero
b011011 256MB Bits [27:15] must be zero
b011100 512MB Bits [28:15] must be zero
b011101 1GB Bits [29:15] must be zero
b011110 2GB Bits [30:15] must be zero
b011111 4GB Bits [31:15] must be zero
b100000 8GB Bits [32:15] must be zero
b100001 16GB Bits [33:15] must be zero
b100010 32GB Bits [34:15] must be zero
b100011 64GB Bits [35:15] must be zero
b100100 128GB Bits [36:15] must be zero
b100101 256GB Bits [37:15] must be zero
b100110 512GB Bits [38:15] must be zero
b100111 1TB Bits [39:15] must be zero
b101000 2TB Bits [40:15] must be zero
b101001 4TB Bits [41:15] must be zero
b101010 8TB Bits [42:15] must be zero
b101011 16TB Bits [43:15] must be zero
b101100 32TB Bits [44:15] must be zero
b101101 64TB Bits [45:15] must be zero
b101110 128TB Bits [46:15] must be zero
b101111 256TB Bits [47:15] must be zero
b110000 512TB Bits [48:15] must be zero
b110001 1PB Bits [49:15] must be zero
b110010 2PB Bits [50:15] must be zero
b110011 4PB Bits [51:15] must be zero
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 435
register descriptions
Table 11-5. Region size (continued)
b110100 8PB Bits [52:15] must be zero
b110101 16PB Bits [53:15] must be zero
b110110 32PB Bits [54:15] must be zero
b110111 64PB Bits [55:15] must be zero
b111000 128PB Bits [56:15] must be zero
b111001 256PB Bits [57:15] must be zero
b111010 512PB Bits [58:15] must be zero
b111011 1EB Bits [59:15] must be zero
b111100 2EB Bits [60:15] must be zero
b111101 4EB Bits [61:15] must be zero
b111110 8EB Bits [62:15] must be zero
b111111 16EB Bits [63:15] must be zero
[1]The region_setup_low_<n> Register and region_setup_high_<n> Register contain the
base address. See Table 313 on page 318 and Table 314 on page 319.
11.4.22.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
sp2 Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
subregion_disable2
Reserved
size2
en2
W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0
11.4.22.4 Fields
Field Function
31-28 sp2
sp2
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
436 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
Field Function
Permissions setting for region n. If an AXI transaction occurs to region n, the value in the spn field
controls whether the TZASC permits the transaction to proceed.
27-16 Reserved, Should be Zero (SBZ).
—
15-8 subregion_disable2
subregion_disab Regions are split into eight equal-sized sub-regions, and each bit enables the corresponding subregion to
le2 be disabled:
Bit [15] = 1 Subregion 7 is disabled.
Bit [14] = 1 Subregion 6 is disabled.
Bit [13] = 1 Subregion 5 is disabled.
Bit [12] = 1 Subregion 4 is disabled.
Bit [11] = 1 Subregion 3 is disabled.
Bit [10] = 1 Subregion 2 is disabled.
Bit [9] = 1 Subregion 1 is disabled.
Bit [8] = 1 Subregion 0 is disabled.
7 Reserved, Should be Zero (SBZ).
—
6-1 size2
size2 Size of region n.The AXI address width, that is AXI_ADDRESS_MSB+1, controls the upper limit value of
this field.
The table below shows how the size n field controls the region size and what constraints, if any, the
TZASC applies to the base address to ensure that a region starts on the boundary of the region size.
0 en2
en2 Enable for region n:
0 = region n is disabled
1 = region n is enabled.
11.4.23 Region Setup Low 3 Register (region_setup_low_3)
11.4.23.1 Offset
Register Offset
region_setup_low_3 130h
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 437
register descriptions
11.4.23.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R base_address_low3
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
base_address_low3
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11.4.23.3 Fields
Field Function
31-15 base_address_low3
base_address_l Controls the base address [31:15] of region n. For region 0, this field is Read Only (RO). The TZASC sets
ow3 the base address of region 0 to 0x0.
The TZASC only permits a region to start at address 0x0, or at a multiple of its region size. For example,
if the size of a region is 512MB, and it is not at address 0x0, the only valid settings for this field are:
b00100000000000000
b01000000000000000
b01100000000000000
b10000000000000000
b10100000000000000
b11000000000000000
b11100000000000000
If you attempt to set an inappropriate base address for the size of the region, the TZASC ignores certain
bits depending on the region size. See Table on register size for more information.
14-0 Reserved, Should be Zero (SBZ).
—
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
438 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
11.4.24 Region Setup High 3 Register (region_setup_high_3)
11.4.24.1 Offset
Register Offset
region_setup_high_3 134h
11.4.24.2 Function
The region_setup_high register is none for region 0, for other regions it controls the base
address [63:32] of region n.There are no usage constraints. Available in all configurations
of the TZASC.
11.4.24.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R base_address_high3
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R base_address_high3
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11.4.24.4 Fields
Field Function
31-0 base_address_high3
base_address_h Controls the base address [63:32] of region n. For region 0, this field is RO. The TZASC sets the base
igh3 address of region 0 to 0x0.
The TZASC only permits a region to start at address 0x0, or at a multiple of its region size. If you program
a region size to be 8GB or more, then the TZASC might ignore certain bits depending on the region size.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 439
register descriptions
11.4.25 Region Attributes 3 Register (region_attributes_3)
11.4.25.1 Offset
Register Offset
region_attributes_3 138h
11.4.25.2 Function
The region_attributes_n register controls the permissions, region size, subregion disable,
and region enable. There are no usage constraints. Available in all configurations of the
TZASC.
Table 11-6. Region size
size<n> field Size of region <n> Base address [1] constraints
b000000-b001101 Reserved -
b001110 32KB -
b001111 64KB Bit [15] must be zero
b010000 128KB Bits [16:15] must be zero
b010001 256KB Bits [17:15] must be zero
b010010 512KB Bits [18:15] must be zero
b010011 1MB Bits [19:15] must be zero
b010100 2MB Bits [20:15] must be zero
b010101 4MB Bits [21:15] must be zero
b010110 8MB Bits [22:15] must be zero
b010111 16MB Bits [23:15] must be zero
b011000 32MB Bits [24:15] must be zero
b011001 64MB Bits [25:15] must be zero
b011010 128MB Bits [26:15] must be zero
b011011 256MB Bits [27:15] must be zero
b011100 512MB Bits [28:15] must be zero
b011101 1GB Bits [29:15] must be zero
b011110 2GB Bits [30:15] must be zero
b011111 4GB Bits [31:15] must be zero
b100000 8GB Bits [32:15] must be zero
b100001 16GB Bits [33:15] must be zero
b100010 32GB Bits [34:15] must be zero
b100011 64GB Bits [35:15] must be zero
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
440 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
Table 11-6. Region size (continued)
b100100 128GB Bits [36:15] must be zero
b100101 256GB Bits [37:15] must be zero
b100110 512GB Bits [38:15] must be zero
b100111 1TB Bits [39:15] must be zero
b101000 2TB Bits [40:15] must be zero
b101001 4TB Bits [41:15] must be zero
b101010 8TB Bits [42:15] must be zero
b101011 16TB Bits [43:15] must be zero
b101100 32TB Bits [44:15] must be zero
b101101 64TB Bits [45:15] must be zero
b101110 128TB Bits [46:15] must be zero
b101111 256TB Bits [47:15] must be zero
b110000 512TB Bits [48:15] must be zero
b110001 1PB Bits [49:15] must be zero
b110010 2PB Bits [50:15] must be zero
b110011 4PB Bits [51:15] must be zero
b110100 8PB Bits [52:15] must be zero
b110101 16PB Bits [53:15] must be zero
b110110 32PB Bits [54:15] must be zero
b110111 64PB Bits [55:15] must be zero
b111000 128PB Bits [56:15] must be zero
b111001 256PB Bits [57:15] must be zero
b111010 512PB Bits [58:15] must be zero
b111011 1EB Bits [59:15] must be zero
b111100 2EB Bits [60:15] must be zero
b111101 4EB Bits [61:15] must be zero
b111110 8EB Bits [62:15] must be zero
b111111 16EB Bits [63:15] must be zero
[1]The region_setup_low_<n> Register and region_setup_high_<n> Register contain the
base address. See Table 313 on page 318 and Table 314 on page 319.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 441
register descriptions
11.4.25.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
sp3 Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
subregion_disable3
Reserved
size3
en3
W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0
11.4.25.4 Fields
Field Function
31-28 sp3
sp3 Permissions setting for region n. If an AXI transaction occurs to region n, the value in the spn field
controls whether the TZASC permits the transaction to proceed.
27-16 Reserved, Should be Zero (SBZ).
—
15-8 subregion_disable3
subregion_disab Regions are split into eight equal-sized sub-regions, and each bit enables the corresponding subregion to
le3 be disabled:
Bit [15] = 1 Subregion 7 is disabled.
Bit [14] = 1 Subregion 6 is disabled.
Bit [13] = 1 Subregion 5 is disabled.
Bit [12] = 1 Subregion 4 is disabled.
Bit [11] = 1 Subregion 3 is disabled.
Bit [10] = 1 Subregion 2 is disabled.
Bit [9] = 1 Subregion 1 is disabled.
Bit [8] = 1 Subregion 0 is disabled.
7 Reserved, Should be Zero (SBZ).
—
6-1 size3
size3
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
442 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
Field Function
Size of region n.The AXI address width, that is AXI_ADDRESS_MSB+1, controls the upper limit value of
this field.
The table below shows how the size n field controls the region size and what constraints, if any, the
TZASC applies to the base address to ensure that a region starts on the boundary of the region size.
0 en3
en3 Enable for region n:
0 = region n is disabled
1 = region n is enabled.
11.4.26 Region Setup Low 4 Register (region_setup_low_4)
11.4.26.1 Offset
Register Offset
region_setup_low_4 140h
11.4.26.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R base_address_low4
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
base_address_low4
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 443
register descriptions
11.4.26.3 Fields
Field Function
31-15 base_address_low4
base_address_l Controls the base address [31:15] of region n. For region 0, this field is Read Only (RO). The TZASC sets
ow4 the base address of region 0 to 0x0.
The TZASC only permits a region to start at address 0x0, or at a multiple of its region size. For example,
if the size of a region is 512MB, and it is not at address 0x0, the only valid settings for this field are:
b00100000000000000
b01000000000000000
b01100000000000000
b10000000000000000
b10100000000000000
b11000000000000000
b11100000000000000
If you attempt to set an inappropriate base address for the size of the region, the TZASC ignores certain
bits depending on the region size. See Table on register size for more information.
14-0 Reserved, Should be Zero (SBZ).
—
11.4.27 Region Setup High 4 Register (region_setup_high_4)
11.4.27.1 Offset
Register Offset
region_setup_high_4 144h
11.4.27.2 Function
The region_setup_high register is none for region 0, for other regions it controls the base
address [63:32] of region n.There are no usage constraints. Available in all configurations
of the TZASC.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
444 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
11.4.27.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R base_address_high4
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R base_address_high4
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11.4.27.4 Fields
Field Function
31-0 base_address_high4
base_address_h Controls the base address [63:32] of region n. For region 0, this field is RO. The TZASC sets the base
igh4 address of region 0 to 0x0.
The TZASC only permits a region to start at address 0x0, or at a multiple of its region size. If you program
a region size to be 8GB or more, then the TZASC might ignore certain bits depending on the region size.
11.4.28 Region Attributes 4 Register (region_attributes_4)
11.4.28.1 Offset
Register Offset
region_attributes_4 148h
11.4.28.2 Function
The region_attributes_n register controls the permissions, region size, subregion disable,
and region enable. There are no usage constraints. Available in all configurations of the
TZASC.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 445
register descriptions
Table 11-7. Region size
size<n> field Size of region <n> Base address [1] constraints
b000000-b001101 Reserved -
b001110 32KB -
b001111 64KB Bit [15] must be zero
b010000 128KB Bits [16:15] must be zero
b010001 256KB Bits [17:15] must be zero
b010010 512KB Bits [18:15] must be zero
b010011 1MB Bits [19:15] must be zero
b010100 2MB Bits [20:15] must be zero
b010101 4MB Bits [21:15] must be zero
b010110 8MB Bits [22:15] must be zero
b010111 16MB Bits [23:15] must be zero
b011000 32MB Bits [24:15] must be zero
b011001 64MB Bits [25:15] must be zero
b011010 128MB Bits [26:15] must be zero
b011011 256MB Bits [27:15] must be zero
b011100 512MB Bits [28:15] must be zero
b011101 1GB Bits [29:15] must be zero
b011110 2GB Bits [30:15] must be zero
b011111 4GB Bits [31:15] must be zero
b100000 8GB Bits [32:15] must be zero
b100001 16GB Bits [33:15] must be zero
b100010 32GB Bits [34:15] must be zero
b100011 64GB Bits [35:15] must be zero
b100100 128GB Bits [36:15] must be zero
b100101 256GB Bits [37:15] must be zero
b100110 512GB Bits [38:15] must be zero
b100111 1TB Bits [39:15] must be zero
b101000 2TB Bits [40:15] must be zero
b101001 4TB Bits [41:15] must be zero
b101010 8TB Bits [42:15] must be zero
b101011 16TB Bits [43:15] must be zero
b101100 32TB Bits [44:15] must be zero
b101101 64TB Bits [45:15] must be zero
b101110 128TB Bits [46:15] must be zero
b101111 256TB Bits [47:15] must be zero
b110000 512TB Bits [48:15] must be zero
b110001 1PB Bits [49:15] must be zero
b110010 2PB Bits [50:15] must be zero
b110011 4PB Bits [51:15] must be zero
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
446 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
Table 11-7. Region size (continued)
b110100 8PB Bits [52:15] must be zero
b110101 16PB Bits [53:15] must be zero
b110110 32PB Bits [54:15] must be zero
b110111 64PB Bits [55:15] must be zero
b111000 128PB Bits [56:15] must be zero
b111001 256PB Bits [57:15] must be zero
b111010 512PB Bits [58:15] must be zero
b111011 1EB Bits [59:15] must be zero
b111100 2EB Bits [60:15] must be zero
b111101 4EB Bits [61:15] must be zero
b111110 8EB Bits [62:15] must be zero
b111111 16EB Bits [63:15] must be zero
[1]The region_setup_low_<n> Register and region_setup_high_<n> Register contain the
base address. See Table 313 on page 318 and Table 314 on page 319.
11.4.28.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
sp4 Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
subregion_disable4
Reserved
size4
en4
W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0
11.4.28.4 Fields
Field Function
31-28 sp4
sp4
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 447
register descriptions
Field Function
Permissions setting for region n. If an AXI transaction occurs to region n, the value in the spn field
controls whether the TZASC permits the transaction to proceed.
27-16 Reserved, Should be Zero (SBZ).
—
15-8 subregion_disable4
subregion_disab Regions are split into eight equal-sized sub-regions, and each bit enables the corresponding subregion to
le4 be disabled:
Bit [15] = 1 Subregion 7 is disabled.
Bit [14] = 1 Subregion 6 is disabled.
Bit [13] = 1 Subregion 5 is disabled.
Bit [12] = 1 Subregion 4 is disabled.
Bit [11] = 1 Subregion 3 is disabled.
Bit [10] = 1 Subregion 2 is disabled.
Bit [9] = 1 Subregion 1 is disabled.
Bit [8] = 1 Subregion 0 is disabled.
7 Reserved, Should be Zero (SBZ).
—
6-1 size4
size4 Size of region n.The AXI address width, that is AXI_ADDRESS_MSB+1, controls the upper limit value of
this field.
The table below shows how the size n field controls the region size and what constraints, if any, the
TZASC applies to the base address to ensure that a region starts on the boundary of the region size.
0 en4
en4 Enable for region n:
0 = region n is disabled
1 = region n is enabled.
11.4.29 Region Setup Low 5 Register (region_setup_low_5)
11.4.29.1 Offset
Register Offset
region_setup_low_5 150h
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
448 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
11.4.29.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R base_address_low5
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
base_address_low5
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11.4.29.3 Fields
Field Function
31-15 base_address_low5
base_address_l Controls the base address [31:15] of region n. For region 0, this field is Read Only (RO). The TZASC sets
ow5 the base address of region 0 to 0x0.
The TZASC only permits a region to start at address 0x0, or at a multiple of its region size. For example,
if the size of a region is 512MB, and it is not at address 0x0, the only valid settings for this field are:
b00100000000000000
b01000000000000000
b01100000000000000
b10000000000000000
b10100000000000000
b11000000000000000
b11100000000000000
If you attempt to set an inappropriate base address for the size of the region, the TZASC ignores certain
bits depending on the region size. See Table on register size for more information.
14-0 Reserved, Should be Zero (SBZ).
—
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 449
register descriptions
11.4.30 Region Setup High 5 Register (region_setup_high_5)
11.4.30.1 Offset
Register Offset
region_setup_high_5 154h
11.4.30.2 Function
The region_setup_high register is none for region 0, for other regions it controls the base
address [63:32] of region n.There are no usage constraints. Available in all configurations
of the TZASC.
11.4.30.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R base_address_high5
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R base_address_high5
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11.4.30.4 Fields
Field Function
31-0 base_address_high5
base_address_h Controls the base address [63:32] of region n. For region 0, this field is RO. The TZASC sets the base
igh5 address of region 0 to 0x0.
The TZASC only permits a region to start at address 0x0, or at a multiple of its region size. If you program
a region size to be 8GB or more, then the TZASC might ignore certain bits depending on the region size.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
450 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
11.4.31 Region Attributes 5 Register (region_attributes_5)
11.4.31.1 Offset
Register Offset
region_attributes_5 158h
11.4.31.2 Function
The region_attributes_n register controls the permissions, region size, subregion disable,
and region enable. There are no usage constraints. Available in all configurations of the
TZASC.
Table 11-8. Region size
size<n> field Size of region <n> Base address [1] constraints
b000000-b001101 Reserved -
b001110 32KB -
b001111 64KB Bit [15] must be zero
b010000 128KB Bits [16:15] must be zero
b010001 256KB Bits [17:15] must be zero
b010010 512KB Bits [18:15] must be zero
b010011 1MB Bits [19:15] must be zero
b010100 2MB Bits [20:15] must be zero
b010101 4MB Bits [21:15] must be zero
b010110 8MB Bits [22:15] must be zero
b010111 16MB Bits [23:15] must be zero
b011000 32MB Bits [24:15] must be zero
b011001 64MB Bits [25:15] must be zero
b011010 128MB Bits [26:15] must be zero
b011011 256MB Bits [27:15] must be zero
b011100 512MB Bits [28:15] must be zero
b011101 1GB Bits [29:15] must be zero
b011110 2GB Bits [30:15] must be zero
b011111 4GB Bits [31:15] must be zero
b100000 8GB Bits [32:15] must be zero
b100001 16GB Bits [33:15] must be zero
b100010 32GB Bits [34:15] must be zero
b100011 64GB Bits [35:15] must be zero
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 451
register descriptions
Table 11-8. Region size (continued)
b100100 128GB Bits [36:15] must be zero
b100101 256GB Bits [37:15] must be zero
b100110 512GB Bits [38:15] must be zero
b100111 1TB Bits [39:15] must be zero
b101000 2TB Bits [40:15] must be zero
b101001 4TB Bits [41:15] must be zero
b101010 8TB Bits [42:15] must be zero
b101011 16TB Bits [43:15] must be zero
b101100 32TB Bits [44:15] must be zero
b101101 64TB Bits [45:15] must be zero
b101110 128TB Bits [46:15] must be zero
b101111 256TB Bits [47:15] must be zero
b110000 512TB Bits [48:15] must be zero
b110001 1PB Bits [49:15] must be zero
b110010 2PB Bits [50:15] must be zero
b110011 4PB Bits [51:15] must be zero
b110100 8PB Bits [52:15] must be zero
b110101 16PB Bits [53:15] must be zero
b110110 32PB Bits [54:15] must be zero
b110111 64PB Bits [55:15] must be zero
b111000 128PB Bits [56:15] must be zero
b111001 256PB Bits [57:15] must be zero
b111010 512PB Bits [58:15] must be zero
b111011 1EB Bits [59:15] must be zero
b111100 2EB Bits [60:15] must be zero
b111101 4EB Bits [61:15] must be zero
b111110 8EB Bits [62:15] must be zero
b111111 16EB Bits [63:15] must be zero
[1]The region_setup_low_<n> Register and region_setup_high_<n> Register contain the
base address. See Table 313 on page 318 and Table 314 on page 319.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
452 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
11.4.31.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
sp5 Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
subregion_disable5
Reserved
size5
en5
W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0
11.4.31.4 Fields
Field Function
31-28 sp5
sp5 Permissions setting for region n. If an AXI transaction occurs to region n, the value in the spn field
controls whether the TZASC permits the transaction to proceed.
27-16 Reserved, Should be Zero (SBZ).
—
15-8 subregion_disable5
subregion_disab Regions are split into eight equal-sized sub-regions, and each bit enables the corresponding subregion to
le5 be disabled:
Bit [15] = 1 Subregion 7 is disabled.
Bit [14] = 1 Subregion 6 is disabled.
Bit [13] = 1 Subregion 5 is disabled.
Bit [12] = 1 Subregion 4 is disabled.
Bit [11] = 1 Subregion 3 is disabled.
Bit [10] = 1 Subregion 2 is disabled.
Bit [9] = 1 Subregion 1 is disabled.
Bit [8] = 1 Subregion 0 is disabled.
7 Reserved, Should be Zero (SBZ).
—
6-1 size5
size5
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 453
register descriptions
Field Function
Size of region n.The AXI address width, that is AXI_ADDRESS_MSB+1, controls the upper limit value of
this field.
The table below shows how the size n field controls the region size and what constraints, if any, the
TZASC applies to the base address to ensure that a region starts on the boundary of the region size.
0 en5
en5 Enable for region n:
0 = region n is disabled
1 = region n is enabled.
11.4.32 Region Setup Low 6 Register (region_setup_low_6)
11.4.32.1 Offset
Register Offset
region_setup_low_6 160h
11.4.32.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R base_address_low6
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
base_address_low6
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
454 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
11.4.32.3 Fields
Field Function
31-15 base_address_low6
base_address_l Controls the base address [31:15] of region n. For region 0, this field is Read Only (RO). The TZASC sets
ow6 the base address of region 0 to 0x0.
The TZASC only permits a region to start at address 0x0, or at a multiple of its region size. For example,
if the size of a region is 512MB, and it is not at address 0x0, the only valid settings for this field are:
b00100000000000000
b01000000000000000
b01100000000000000
b10000000000000000
b10100000000000000
b11000000000000000
b11100000000000000
If you attempt to set an inappropriate base address for the size of the region, the TZASC ignores certain
bits depending on the region size. See Table on register size for more information.
14-0 Reserved, Should be Zero (SBZ).
—
11.4.33 Region Setup High 6 Register (region_setup_high_6)
11.4.33.1 Offset
Register Offset
region_setup_high_6 164h
11.4.33.2 Function
The region_setup_high register is none for region 0, for other regions it controls the base
address [63:32] of region n.There are no usage constraints. Available in all configurations
of the TZASC.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 455
register descriptions
11.4.33.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R base_address_high6
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R base_address_high6
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11.4.33.4 Fields
Field Function
31-0 base_address_high6
base_address_h Controls the base address [63:32] of region n. For region 0, this field is RO. The TZASC sets the base
igh6 address of region 0 to 0x0.
The TZASC only permits a region to start at address 0x0, or at a multiple of its region size. If you program
a region size to be 8GB or more, then the TZASC might ignore certain bits depending on the region size.
11.4.34 Region Attributes 6 Register (region_attributes_6)
11.4.34.1 Offset
Register Offset
region_attributes_6 168h
11.4.34.2 Function
The region_attributes_n register controls the permissions, region size, subregion disable,
and region enable. There are no usage constraints. Available in all configurations of the
TZASC.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
456 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
Table 11-9. Region size
size<n> field Size of region <n> Base address [1] constraints
b000000-b001101 Reserved -
b001110 32KB -
b001111 64KB Bit [15] must be zero
b010000 128KB Bits [16:15] must be zero
b010001 256KB Bits [17:15] must be zero
b010010 512KB Bits [18:15] must be zero
b010011 1MB Bits [19:15] must be zero
b010100 2MB Bits [20:15] must be zero
b010101 4MB Bits [21:15] must be zero
b010110 8MB Bits [22:15] must be zero
b010111 16MB Bits [23:15] must be zero
b011000 32MB Bits [24:15] must be zero
b011001 64MB Bits [25:15] must be zero
b011010 128MB Bits [26:15] must be zero
b011011 256MB Bits [27:15] must be zero
b011100 512MB Bits [28:15] must be zero
b011101 1GB Bits [29:15] must be zero
b011110 2GB Bits [30:15] must be zero
b011111 4GB Bits [31:15] must be zero
b100000 8GB Bits [32:15] must be zero
b100001 16GB Bits [33:15] must be zero
b100010 32GB Bits [34:15] must be zero
b100011 64GB Bits [35:15] must be zero
b100100 128GB Bits [36:15] must be zero
b100101 256GB Bits [37:15] must be zero
b100110 512GB Bits [38:15] must be zero
b100111 1TB Bits [39:15] must be zero
b101000 2TB Bits [40:15] must be zero
b101001 4TB Bits [41:15] must be zero
b101010 8TB Bits [42:15] must be zero
b101011 16TB Bits [43:15] must be zero
b101100 32TB Bits [44:15] must be zero
b101101 64TB Bits [45:15] must be zero
b101110 128TB Bits [46:15] must be zero
b101111 256TB Bits [47:15] must be zero
b110000 512TB Bits [48:15] must be zero
b110001 1PB Bits [49:15] must be zero
b110010 2PB Bits [50:15] must be zero
b110011 4PB Bits [51:15] must be zero
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 457
register descriptions
Table 11-9. Region size (continued)
b110100 8PB Bits [52:15] must be zero
b110101 16PB Bits [53:15] must be zero
b110110 32PB Bits [54:15] must be zero
b110111 64PB Bits [55:15] must be zero
b111000 128PB Bits [56:15] must be zero
b111001 256PB Bits [57:15] must be zero
b111010 512PB Bits [58:15] must be zero
b111011 1EB Bits [59:15] must be zero
b111100 2EB Bits [60:15] must be zero
b111101 4EB Bits [61:15] must be zero
b111110 8EB Bits [62:15] must be zero
b111111 16EB Bits [63:15] must be zero
[1]The region_setup_low_<n> Register and region_setup_high_<n> Register contain the
base address. See Table 313 on page 318 and Table 314 on page 319.
11.4.34.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
sp6 Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
subregion_disable6
Reserved
size6
en6
W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0
11.4.34.4 Fields
Field Function
31-28 sp6
sp6
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
458 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
Field Function
Permissions setting for region n. If an AXI transaction occurs to region n, the value in the spn field
controls whether the TZASC permits the transaction to proceed.
27-16 Reserved, Should be Zero (SBZ).
—
15-8 subregion_disable6
subregion_disab Regions are split into eight equal-sized sub-regions, and each bit enables the corresponding subregion to
le6 be disabled:
Bit [15] = 1 Subregion 7 is disabled.
Bit [14] = 1 Subregion 6 is disabled.
Bit [13] = 1 Subregion 5 is disabled.
Bit [12] = 1 Subregion 4 is disabled.
Bit [11] = 1 Subregion 3 is disabled.
Bit [10] = 1 Subregion 2 is disabled.
Bit [9] = 1 Subregion 1 is disabled.
Bit [8] = 1 Subregion 0 is disabled.
7 Reserved, Should be Zero (SBZ).
—
6-1 size6
size6 Size of region n.The AXI address width, that is AXI_ADDRESS_MSB+1, controls the upper limit value of
this field.
The table below shows how the size n field controls the region size and what constraints, if any, the
TZASC applies to the base address to ensure that a region starts on the boundary of the region size.
0 en6
en6 Enable for region n:
0 = region n is disabled
1 = region n is enabled.
11.4.35 Region Setup Low 7 Register (region_setup_low_7)
11.4.35.1 Offset
Register Offset
region_setup_low_7 170h
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 459
register descriptions
11.4.35.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R base_address_low7
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
base_address_low7
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11.4.35.3 Fields
Field Function
31-15 base_address_low7
base_address_l Controls the base address [31:15] of region n. For region 0, this field is Read Only (RO). The TZASC sets
ow7 the base address of region 0 to 0x0.
The TZASC only permits a region to start at address 0x0, or at a multiple of its region size. For example,
if the size of a region is 512MB, and it is not at address 0x0, the only valid settings for this field are:
b00100000000000000
b01000000000000000
b01100000000000000
b10000000000000000
b10100000000000000
b11000000000000000
b11100000000000000
If you attempt to set an inappropriate base address for the size of the region, the TZASC ignores certain
bits depending on the region size. See Table on register size for more information.
14-0 Reserved, Should be Zero (SBZ).
—
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
460 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
11.4.36 Region Setup High 7 Register (region_setup_high_7)
11.4.36.1 Offset
Register Offset
region_setup_high_7 174h
11.4.36.2 Function
The region_setup_high register is none for region 0, for other regions it controls the base
address [63:32] of region n.There are no usage constraints. Available in all configurations
of the TZASC.
11.4.36.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R base_address_high7
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R base_address_high7
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11.4.36.4 Fields
Field Function
31-0 base_address_high7
base_address_h Controls the base address [63:32] of region n. For region 0, this field is RO. The TZASC sets the base
igh7 address of region 0 to 0x0.
The TZASC only permits a region to start at address 0x0, or at a multiple of its region size. If you program
a region size to be 8GB or more, then the TZASC might ignore certain bits depending on the region size.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 461
register descriptions
11.4.37 Region Attributes 7 Register (region_attributes_7)
11.4.37.1 Offset
Register Offset
region_attributes_7 178h
11.4.37.2 Function
The region_attributes_n register controls the permissions, region size, subregion disable,
and region enable. There are no usage constraints. Available in all configurations of the
TZASC.
Table 11-10. Region size
size<n> field Size of region <n> Base address [1] constraints
b000000-b001101 Reserved -
b001110 32KB -
b001111 64KB Bit [15] must be zero
b010000 128KB Bits [16:15] must be zero
b010001 256KB Bits [17:15] must be zero
b010010 512KB Bits [18:15] must be zero
b010011 1MB Bits [19:15] must be zero
b010100 2MB Bits [20:15] must be zero
b010101 4MB Bits [21:15] must be zero
b010110 8MB Bits [22:15] must be zero
b010111 16MB Bits [23:15] must be zero
b011000 32MB Bits [24:15] must be zero
b011001 64MB Bits [25:15] must be zero
b011010 128MB Bits [26:15] must be zero
b011011 256MB Bits [27:15] must be zero
b011100 512MB Bits [28:15] must be zero
b011101 1GB Bits [29:15] must be zero
b011110 2GB Bits [30:15] must be zero
b011111 4GB Bits [31:15] must be zero
b100000 8GB Bits [32:15] must be zero
b100001 16GB Bits [33:15] must be zero
b100010 32GB Bits [34:15] must be zero
b100011 64GB Bits [35:15] must be zero
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
462 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
Table 11-10. Region size (continued)
b100100 128GB Bits [36:15] must be zero
b100101 256GB Bits [37:15] must be zero
b100110 512GB Bits [38:15] must be zero
b100111 1TB Bits [39:15] must be zero
b101000 2TB Bits [40:15] must be zero
b101001 4TB Bits [41:15] must be zero
b101010 8TB Bits [42:15] must be zero
b101011 16TB Bits [43:15] must be zero
b101100 32TB Bits [44:15] must be zero
b101101 64TB Bits [45:15] must be zero
b101110 128TB Bits [46:15] must be zero
b101111 256TB Bits [47:15] must be zero
b110000 512TB Bits [48:15] must be zero
b110001 1PB Bits [49:15] must be zero
b110010 2PB Bits [50:15] must be zero
b110011 4PB Bits [51:15] must be zero
b110100 8PB Bits [52:15] must be zero
b110101 16PB Bits [53:15] must be zero
b110110 32PB Bits [54:15] must be zero
b110111 64PB Bits [55:15] must be zero
b111000 128PB Bits [56:15] must be zero
b111001 256PB Bits [57:15] must be zero
b111010 512PB Bits [58:15] must be zero
b111011 1EB Bits [59:15] must be zero
b111100 2EB Bits [60:15] must be zero
b111101 4EB Bits [61:15] must be zero
b111110 8EB Bits [62:15] must be zero
b111111 16EB Bits [63:15] must be zero
[1]The region_setup_low_<n> Register and region_setup_high_<n> Register contain the
base address. See Table 313 on page 318 and Table 314 on page 319.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 463
register descriptions
11.4.37.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
sp7 Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
subregion_disable7
Reserved
size7
en7
W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0
11.4.37.4 Fields
Field Function
31-28 sp7
sp7 Permissions setting for region n. If an AXI transaction occurs to region n, the value in the spn field
controls whether the TZASC permits the transaction to proceed.
27-16 Reserved, Should be Zero (SBZ).
—
15-8 subregion_disable7
subregion_disab Regions are split into eight equal-sized sub-regions, and each bit enables the corresponding subregion to
le7 be disabled:
Bit [15] = 1 Subregion 7 is disabled.
Bit [14] = 1 Subregion 6 is disabled.
Bit [13] = 1 Subregion 5 is disabled.
Bit [12] = 1 Subregion 4 is disabled.
Bit [11] = 1 Subregion 3 is disabled.
Bit [10] = 1 Subregion 2 is disabled.
Bit [9] = 1 Subregion 1 is disabled.
Bit [8] = 1 Subregion 0 is disabled.
7 Reserved, Should be Zero (SBZ).
—
6-1 size7
size7
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
464 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
Field Function
Size of region n.The AXI address width, that is AXI_ADDRESS_MSB+1, controls the upper limit value of
this field.
The table below shows how the size n field controls the region size and what constraints, if any, the
TZASC applies to the base address to ensure that a region starts on the boundary of the region size.
0 en7
en7 Enable for region n:
0 = region n is disabled
1 = region n is enabled.
11.4.38 Region Setup Low 8 Register (region_setup_low_8)
11.4.38.1 Offset
Register Offset
region_setup_low_8 180h
11.4.38.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R base_address_low8
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
base_address_low8
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 465
register descriptions
11.4.38.3 Fields
Field Function
31-15 base_address_low8
base_address_l Controls the base address [31:15] of region n. For region 0, this field is Read Only (RO). The TZASC sets
ow8 the base address of region 0 to 0x0.
The TZASC only permits a region to start at address 0x0, or at a multiple of its region size. For example,
if the size of a region is 512MB, and it is not at address 0x0, the only valid settings for this field are:
b00100000000000000
b01000000000000000
b01100000000000000
b10000000000000000
b10100000000000000
b11000000000000000
b11100000000000000
If you attempt to set an inappropriate base address for the size of the region, the TZASC ignores certain
bits depending on the region size. See Table on register size for more information.
14-0 Reserved, Should be Zero (SBZ).
—
11.4.39 Region Setup High 8 Register (region_setup_high_8)
11.4.39.1 Offset
Register Offset
region_setup_high_8 184h
11.4.39.2 Function
The region_setup_high register is none for region 0, for other regions it controls the base
address [63:32] of region n.There are no usage constraints. Available in all configurations
of the TZASC.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
466 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
11.4.39.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R base_address_high8
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R base_address_high8
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11.4.39.4 Fields
Field Function
31-0 base_address_high8
base_address_h Controls the base address [63:32] of region n. For region 0, this field is RO. The TZASC sets the base
igh8 address of region 0 to 0x0.
The TZASC only permits a region to start at address 0x0, or at a multiple of its region size. If you program
a region size to be 8GB or more, then the TZASC might ignore certain bits depending on the region size.
11.4.40 Region Attributes 8 Register (region_attributes_8)
11.4.40.1 Offset
Register Offset
region_attributes_8 188h
11.4.40.2 Function
The region_attributes_n register controls the permissions, region size, subregion disable,
and region enable. There are no usage constraints. Available in all configurations of the
TZASC.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 467
register descriptions
Table 11-11. Region size
size<n> field Size of region <n> Base address [1] constraints
b000000-b001101 Reserved -
b001110 32KB -
b001111 64KB Bit [15] must be zero
b010000 128KB Bits [16:15] must be zero
b010001 256KB Bits [17:15] must be zero
b010010 512KB Bits [18:15] must be zero
b010011 1MB Bits [19:15] must be zero
b010100 2MB Bits [20:15] must be zero
b010101 4MB Bits [21:15] must be zero
b010110 8MB Bits [22:15] must be zero
b010111 16MB Bits [23:15] must be zero
b011000 32MB Bits [24:15] must be zero
b011001 64MB Bits [25:15] must be zero
b011010 128MB Bits [26:15] must be zero
b011011 256MB Bits [27:15] must be zero
b011100 512MB Bits [28:15] must be zero
b011101 1GB Bits [29:15] must be zero
b011110 2GB Bits [30:15] must be zero
b011111 4GB Bits [31:15] must be zero
b100000 8GB Bits [32:15] must be zero
b100001 16GB Bits [33:15] must be zero
b100010 32GB Bits [34:15] must be zero
b100011 64GB Bits [35:15] must be zero
b100100 128GB Bits [36:15] must be zero
b100101 256GB Bits [37:15] must be zero
b100110 512GB Bits [38:15] must be zero
b100111 1TB Bits [39:15] must be zero
b101000 2TB Bits [40:15] must be zero
b101001 4TB Bits [41:15] must be zero
b101010 8TB Bits [42:15] must be zero
b101011 16TB Bits [43:15] must be zero
b101100 32TB Bits [44:15] must be zero
b101101 64TB Bits [45:15] must be zero
b101110 128TB Bits [46:15] must be zero
b101111 256TB Bits [47:15] must be zero
b110000 512TB Bits [48:15] must be zero
b110001 1PB Bits [49:15] must be zero
b110010 2PB Bits [50:15] must be zero
b110011 4PB Bits [51:15] must be zero
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
468 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
Table 11-11. Region size (continued)
b110100 8PB Bits [52:15] must be zero
b110101 16PB Bits [53:15] must be zero
b110110 32PB Bits [54:15] must be zero
b110111 64PB Bits [55:15] must be zero
b111000 128PB Bits [56:15] must be zero
b111001 256PB Bits [57:15] must be zero
b111010 512PB Bits [58:15] must be zero
b111011 1EB Bits [59:15] must be zero
b111100 2EB Bits [60:15] must be zero
b111101 4EB Bits [61:15] must be zero
b111110 8EB Bits [62:15] must be zero
b111111 16EB Bits [63:15] must be zero
[1]The region_setup_low_<n> Register and region_setup_high_<n> Register contain the
base address. See Table 313 on page 318 and Table 314 on page 319.
11.4.40.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
sp8 Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
subregion_disable8
Reserved
size8
en8
W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0
11.4.40.4 Fields
Field Function
31-28 sp8
sp8
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 469
register descriptions
Field Function
Permissions setting for region n. If an AXI transaction occurs to region n, the value in the spn field
controls whether the TZASC permits the transaction to proceed.
27-16 Reserved, Should be Zero (SBZ).
—
15-8 subregion_disable8
subregion_disab Regions are split into eight equal-sized sub-regions, and each bit enables the corresponding subregion to
le8 be disabled:
Bit [15] = 1 Subregion 7 is disabled.
Bit [14] = 1 Subregion 6 is disabled.
Bit [13] = 1 Subregion 5 is disabled.
Bit [12] = 1 Subregion 4 is disabled.
Bit [11] = 1 Subregion 3 is disabled.
Bit [10] = 1 Subregion 2 is disabled.
Bit [9] = 1 Subregion 1 is disabled.
Bit [8] = 1 Subregion 0 is disabled.
7 Reserved, Should be Zero (SBZ).
—
6-1 size8
size8 Size of region n.The AXI address width, that is AXI_ADDRESS_MSB+1, controls the upper limit value of
this field.
The table below shows how the size n field controls the region size and what constraints, if any, the
TZASC applies to the base address to ensure that a region starts on the boundary of the region size.
0 en8
en8 Enable for region n:
0 = region n is disabled
1 = region n is enabled.
11.4.41 Region Setup Low 9 Register (region_setup_low_9)
11.4.41.1 Offset
Register Offset
region_setup_low_9 190h
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
470 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
11.4.41.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R base_address_low9
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
base_address_low9
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11.4.41.3 Fields
Field Function
31-15 base_address_low9
base_address_l Controls the base address [31:15] of region n. For region 0, this field is Read Only (RO). The TZASC sets
ow9 the base address of region 0 to 0x0.
The TZASC only permits a region to start at address 0x0, or at a multiple of its region size. For example,
if the size of a region is 512MB, and it is not at address 0x0, the only valid settings for this field are:
b00100000000000000
b01000000000000000
b01100000000000000
b10000000000000000
b10100000000000000
b11000000000000000
b11100000000000000
If you attempt to set an inappropriate base address for the size of the region, the TZASC ignores certain
bits depending on the region size. See Table on register size for more information.
14-0 Reserved, Should be Zero (SBZ).
—
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 471
register descriptions
11.4.42 Region Setup High 9 Register (region_setup_high_9)
11.4.42.1 Offset
Register Offset
region_setup_high_9 194h
11.4.42.2 Function
The region_setup_high register is none for region 0, for other regions it controls the base
address [63:32] of region n.There are no usage constraints. Available in all configurations
of the TZASC.
11.4.42.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R base_address_high9
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R base_address_high9
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11.4.42.4 Fields
Field Function
31-0 base_address_high9
base_address_h Controls the base address [63:32] of region n. For region 0, this field is RO. The TZASC sets the base
igh9 address of region 0 to 0x0.
The TZASC only permits a region to start at address 0x0, or at a multiple of its region size. If you program
a region size to be 8GB or more, then the TZASC might ignore certain bits depending on the region size.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
472 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
11.4.43 Region Attributes 9 Register (region_attributes_9)
11.4.43.1 Offset
Register Offset
region_attributes_9 198h
11.4.43.2 Function
The region_attributes_n register controls the permissions, region size, subregion disable,
and region enable. There are no usage constraints. Available in all configurations of the
TZASC.
Table 11-12. Region size
size<n> field Size of region <n> Base address [1] constraints
b000000-b001101 Reserved -
b001110 32KB -
b001111 64KB Bit [15] must be zero
b010000 128KB Bits [16:15] must be zero
b010001 256KB Bits [17:15] must be zero
b010010 512KB Bits [18:15] must be zero
b010011 1MB Bits [19:15] must be zero
b010100 2MB Bits [20:15] must be zero
b010101 4MB Bits [21:15] must be zero
b010110 8MB Bits [22:15] must be zero
b010111 16MB Bits [23:15] must be zero
b011000 32MB Bits [24:15] must be zero
b011001 64MB Bits [25:15] must be zero
b011010 128MB Bits [26:15] must be zero
b011011 256MB Bits [27:15] must be zero
b011100 512MB Bits [28:15] must be zero
b011101 1GB Bits [29:15] must be zero
b011110 2GB Bits [30:15] must be zero
b011111 4GB Bits [31:15] must be zero
b100000 8GB Bits [32:15] must be zero
b100001 16GB Bits [33:15] must be zero
b100010 32GB Bits [34:15] must be zero
b100011 64GB Bits [35:15] must be zero
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 473
register descriptions
Table 11-12. Region size (continued)
b100100 128GB Bits [36:15] must be zero
b100101 256GB Bits [37:15] must be zero
b100110 512GB Bits [38:15] must be zero
b100111 1TB Bits [39:15] must be zero
b101000 2TB Bits [40:15] must be zero
b101001 4TB Bits [41:15] must be zero
b101010 8TB Bits [42:15] must be zero
b101011 16TB Bits [43:15] must be zero
b101100 32TB Bits [44:15] must be zero
b101101 64TB Bits [45:15] must be zero
b101110 128TB Bits [46:15] must be zero
b101111 256TB Bits [47:15] must be zero
b110000 512TB Bits [48:15] must be zero
b110001 1PB Bits [49:15] must be zero
b110010 2PB Bits [50:15] must be zero
b110011 4PB Bits [51:15] must be zero
b110100 8PB Bits [52:15] must be zero
b110101 16PB Bits [53:15] must be zero
b110110 32PB Bits [54:15] must be zero
b110111 64PB Bits [55:15] must be zero
b111000 128PB Bits [56:15] must be zero
b111001 256PB Bits [57:15] must be zero
b111010 512PB Bits [58:15] must be zero
b111011 1EB Bits [59:15] must be zero
b111100 2EB Bits [60:15] must be zero
b111101 4EB Bits [61:15] must be zero
b111110 8EB Bits [62:15] must be zero
b111111 16EB Bits [63:15] must be zero
[1]The region_setup_low_<n> Register and region_setup_high_<n> Register contain the
base address. See Table 313 on page 318 and Table 314 on page 319.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
474 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
11.4.43.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
sp9 Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
subregion_disable9
Reserved
size9
en9
W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0
11.4.43.4 Fields
Field Function
31-28 sp9
sp9 Permissions setting for region n. If an AXI transaction occurs to region n, the value in the spn field
controls whether the TZASC permits the transaction to proceed.
27-16 Reserved, Should be Zero (SBZ).
—
15-8 subregion_disable9
subregion_disab Regions are split into eight equal-sized sub-regions, and each bit enables the corresponding subregion to
le9 be disabled:
Bit [15] = 1 Subregion 7 is disabled.
Bit [14] = 1 Subregion 6 is disabled.
Bit [13] = 1 Subregion 5 is disabled.
Bit [12] = 1 Subregion 4 is disabled.
Bit [11] = 1 Subregion 3 is disabled.
Bit [10] = 1 Subregion 2 is disabled.
Bit [9] = 1 Subregion 1 is disabled.
Bit [8] = 1 Subregion 0 is disabled.
7 Reserved, Should be Zero (SBZ).
—
6-1 size9
size9
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 475
register descriptions
Field Function
Size of region n.The AXI address width, that is AXI_ADDRESS_MSB+1, controls the upper limit value of
this field.
The table below shows how the size n field controls the region size and what constraints, if any, the
TZASC applies to the base address to ensure that a region starts on the boundary of the region size.
0 en9
en9 Enable for region n:
0 = region n is disabled
1 = region n is enabled.
11.4.44 Region Setup Low 10 Register (region_setup_low_10)
11.4.44.1 Offset
Register Offset
region_setup_low_10 1A0h
11.4.44.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R base_address_low10
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
base_address_low10
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
476 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
11.4.44.3 Fields
Field Function
31-15 base_address_low10
base_address_l Controls the base address [31:15] of region n. For region 0, this field is Read Only (RO). The TZASC sets
ow10 the base address of region 0 to 0x0.
The TZASC only permits a region to start at address 0x0, or at a multiple of its region size. For example,
if the size of a region is 512MB, and it is not at address 0x0, the only valid settings for this field are:
b00100000000000000
b01000000000000000
b01100000000000000
b10000000000000000
b10100000000000000
b11000000000000000
b11100000000000000
If you attempt to set an inappropriate base address for the size of the region, the TZASC ignores certain
bits depending on the region size. See Table on register size for more information.
14-0 Reserved, Should be Zero (SBZ).
—
11.4.45 Region Setup High 10 Register (region_setup_high_10)
11.4.45.1 Offset
Register Offset
region_setup_high_10 1A4h
11.4.45.2 Function
The region_setup_high register is none for region 0, for other regions it controls the base
address [63:32] of region n.There are no usage constraints. Available in all configurations
of the TZASC.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 477
register descriptions
11.4.45.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R base_address_high10
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R base_address_high10
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11.4.45.4 Fields
Field Function
31-0 base_address_high10
base_address_h Controls the base address [63:32] of region n. For region 0, this field is RO. The TZASC sets the base
igh10 address of region 0 to 0x0.
The TZASC only permits a region to start at address 0x0, or at a multiple of its region size. If you program
a region size to be 8GB or more, then the TZASC might ignore certain bits depending on the region size.
11.4.46 Region Attributes 10 Register (region_attributes_10)
11.4.46.1 Offset
Register Offset
region_attributes_10 1A8h
11.4.46.2 Function
The region_attributes_n register controls the permissions, region size, subregion disable,
and region enable. There are no usage constraints. Available in all configurations of the
TZASC.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
478 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
Table 11-13. Region size
size<n> field Size of region <n> Base address [1] constraints
b000000-b001101 Reserved -
b001110 32KB -
b001111 64KB Bit [15] must be zero
b010000 128KB Bits [16:15] must be zero
b010001 256KB Bits [17:15] must be zero
b010010 512KB Bits [18:15] must be zero
b010011 1MB Bits [19:15] must be zero
b010100 2MB Bits [20:15] must be zero
b010101 4MB Bits [21:15] must be zero
b010110 8MB Bits [22:15] must be zero
b010111 16MB Bits [23:15] must be zero
b011000 32MB Bits [24:15] must be zero
b011001 64MB Bits [25:15] must be zero
b011010 128MB Bits [26:15] must be zero
b011011 256MB Bits [27:15] must be zero
b011100 512MB Bits [28:15] must be zero
b011101 1GB Bits [29:15] must be zero
b011110 2GB Bits [30:15] must be zero
b011111 4GB Bits [31:15] must be zero
b100000 8GB Bits [32:15] must be zero
b100001 16GB Bits [33:15] must be zero
b100010 32GB Bits [34:15] must be zero
b100011 64GB Bits [35:15] must be zero
b100100 128GB Bits [36:15] must be zero
b100101 256GB Bits [37:15] must be zero
b100110 512GB Bits [38:15] must be zero
b100111 1TB Bits [39:15] must be zero
b101000 2TB Bits [40:15] must be zero
b101001 4TB Bits [41:15] must be zero
b101010 8TB Bits [42:15] must be zero
b101011 16TB Bits [43:15] must be zero
b101100 32TB Bits [44:15] must be zero
b101101 64TB Bits [45:15] must be zero
b101110 128TB Bits [46:15] must be zero
b101111 256TB Bits [47:15] must be zero
b110000 512TB Bits [48:15] must be zero
b110001 1PB Bits [49:15] must be zero
b110010 2PB Bits [50:15] must be zero
b110011 4PB Bits [51:15] must be zero
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 479
register descriptions
Table 11-13. Region size (continued)
b110100 8PB Bits [52:15] must be zero
b110101 16PB Bits [53:15] must be zero
b110110 32PB Bits [54:15] must be zero
b110111 64PB Bits [55:15] must be zero
b111000 128PB Bits [56:15] must be zero
b111001 256PB Bits [57:15] must be zero
b111010 512PB Bits [58:15] must be zero
b111011 1EB Bits [59:15] must be zero
b111100 2EB Bits [60:15] must be zero
b111101 4EB Bits [61:15] must be zero
b111110 8EB Bits [62:15] must be zero
b111111 16EB Bits [63:15] must be zero
[1]The region_setup_low_<n> Register and region_setup_high_<n> Register contain the
base address. See Table 313 on page 318 and Table 314 on page 319.
11.4.46.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
sp10 Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
subregion_disable10
Reserved
size10
en10
W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0
11.4.46.4 Fields
Field Function
31-28 sp10
sp10
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
480 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
Field Function
Permissions setting for region n. If an AXI transaction occurs to region n, the value in the spn field
controls whether the TZASC permits the transaction to proceed.
27-16 Reserved, Should be Zero (SBZ).
—
15-8 subregion_disable10
subregion_disab Regions are split into eight equal-sized sub-regions, and each bit enables the corresponding subregion to
le10 be disabled:
Bit [15] = 1 Subregion 7 is disabled.
Bit [14] = 1 Subregion 6 is disabled.
Bit [13] = 1 Subregion 5 is disabled.
Bit [12] = 1 Subregion 4 is disabled.
Bit [11] = 1 Subregion 3 is disabled.
Bit [10] = 1 Subregion 2 is disabled.
Bit [9] = 1 Subregion 1 is disabled.
Bit [8] = 1 Subregion 0 is disabled.
7 Reserved, Should be Zero (SBZ).
—
6-1 size10
size10 Size of region n.The AXI address width, that is AXI_ADDRESS_MSB+1, controls the upper limit value of
this field.
The table below shows how the size n field controls the region size and what constraints, if any, the
TZASC applies to the base address to ensure that a region starts on the boundary of the region size.
0 en10
en10 Enable for region n:
0 = region n is disabled
1 = region n is enabled.
11.4.47 Region Setup Low 11 Register (region_setup_low_11)
11.4.47.1 Offset
Register Offset
region_setup_low_11 1B0h
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 481
register descriptions
11.4.47.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R base_address_low11
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
base_address_low11
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11.4.47.3 Fields
Field Function
31-15 base_address_low11
base_address_l Controls the base address [31:15] of region n. For region 0, this field is Read Only (RO). The TZASC sets
ow11 the base address of region 0 to 0x0.
The TZASC only permits a region to start at address 0x0, or at a multiple of its region size. For example,
if the size of a region is 512MB, and it is not at address 0x0, the only valid settings for this field are:
b00100000000000000
b01000000000000000
b01100000000000000
b10000000000000000
b10100000000000000
b11000000000000000
b11100000000000000
If you attempt to set an inappropriate base address for the size of the region, the TZASC ignores certain
bits depending on the region size. See Table on register size for more information.
14-0 Reserved, Should be Zero (SBZ).
—
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
482 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
11.4.48 Region Setup High 11 Register (region_setup_high_11)
11.4.48.1 Offset
Register Offset
region_setup_high_11 1B4h
11.4.48.2 Function
The region_setup_high register is none for region 0, for other regions it controls the base
address [63:32] of region n.There are no usage constraints. Available in all configurations
of the TZASC.
11.4.48.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R base_address_high11
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R base_address_high11
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11.4.48.4 Fields
Field Function
31-0 base_address_high11
base_address_h Controls the base address [63:32] of region n. For region 0, this field is RO. The TZASC sets the base
igh11 address of region 0 to 0x0.
The TZASC only permits a region to start at address 0x0, or at a multiple of its region size. If you program
a region size to be 8GB or more, then the TZASC might ignore certain bits depending on the region size.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 483
register descriptions
11.4.49 Region Attributes 11 Register (region_attributes_11)
11.4.49.1 Offset
Register Offset
region_attributes_11 1B8h
11.4.49.2 Function
The region_attributes_n register controls the permissions, region size, subregion disable,
and region enable. There are no usage constraints. Available in all configurations of the
TZASC.
Table 11-14. Region size
size<n> field Size of region <n> Base address [1] constraints
b000000-b001101 Reserved -
b001110 32KB -
b001111 64KB Bit [15] must be zero
b010000 128KB Bits [16:15] must be zero
b010001 256KB Bits [17:15] must be zero
b010010 512KB Bits [18:15] must be zero
b010011 1MB Bits [19:15] must be zero
b010100 2MB Bits [20:15] must be zero
b010101 4MB Bits [21:15] must be zero
b010110 8MB Bits [22:15] must be zero
b010111 16MB Bits [23:15] must be zero
b011000 32MB Bits [24:15] must be zero
b011001 64MB Bits [25:15] must be zero
b011010 128MB Bits [26:15] must be zero
b011011 256MB Bits [27:15] must be zero
b011100 512MB Bits [28:15] must be zero
b011101 1GB Bits [29:15] must be zero
b011110 2GB Bits [30:15] must be zero
b011111 4GB Bits [31:15] must be zero
b100000 8GB Bits [32:15] must be zero
b100001 16GB Bits [33:15] must be zero
b100010 32GB Bits [34:15] must be zero
b100011 64GB Bits [35:15] must be zero
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
484 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
Table 11-14. Region size (continued)
b100100 128GB Bits [36:15] must be zero
b100101 256GB Bits [37:15] must be zero
b100110 512GB Bits [38:15] must be zero
b100111 1TB Bits [39:15] must be zero
b101000 2TB Bits [40:15] must be zero
b101001 4TB Bits [41:15] must be zero
b101010 8TB Bits [42:15] must be zero
b101011 16TB Bits [43:15] must be zero
b101100 32TB Bits [44:15] must be zero
b101101 64TB Bits [45:15] must be zero
b101110 128TB Bits [46:15] must be zero
b101111 256TB Bits [47:15] must be zero
b110000 512TB Bits [48:15] must be zero
b110001 1PB Bits [49:15] must be zero
b110010 2PB Bits [50:15] must be zero
b110011 4PB Bits [51:15] must be zero
b110100 8PB Bits [52:15] must be zero
b110101 16PB Bits [53:15] must be zero
b110110 32PB Bits [54:15] must be zero
b110111 64PB Bits [55:15] must be zero
b111000 128PB Bits [56:15] must be zero
b111001 256PB Bits [57:15] must be zero
b111010 512PB Bits [58:15] must be zero
b111011 1EB Bits [59:15] must be zero
b111100 2EB Bits [60:15] must be zero
b111101 4EB Bits [61:15] must be zero
b111110 8EB Bits [62:15] must be zero
b111111 16EB Bits [63:15] must be zero
[1]The region_setup_low_<n> Register and region_setup_high_<n> Register contain the
base address. See Table 313 on page 318 and Table 314 on page 319.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 485
register descriptions
11.4.49.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
sp11 Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
subregion_disable11
Reserved
size11
en11
W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0
11.4.49.4 Fields
Field Function
31-28 sp11
sp11 Permissions setting for region n. If an AXI transaction occurs to region n, the value in the spn field
controls whether the TZASC permits the transaction to proceed.
27-16 Reserved, Should be Zero (SBZ).
—
15-8 subregion_disable11
subregion_disab Regions are split into eight equal-sized sub-regions, and each bit enables the corresponding subregion to
le11 be disabled:
Bit [15] = 1 Subregion 7 is disabled.
Bit [14] = 1 Subregion 6 is disabled.
Bit [13] = 1 Subregion 5 is disabled.
Bit [12] = 1 Subregion 4 is disabled.
Bit [11] = 1 Subregion 3 is disabled.
Bit [10] = 1 Subregion 2 is disabled.
Bit [9] = 1 Subregion 1 is disabled.
Bit [8] = 1 Subregion 0 is disabled.
7 Reserved, Should be Zero (SBZ).
—
6-1 size11
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
486 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
Field Function
size11 Size of region n.The AXI address width, that is AXI_ADDRESS_MSB+1, controls the upper limit value of
this field.
The table below shows how the size n field controls the region size and what constraints, if any, the
TZASC applies to the base address to ensure that a region starts on the boundary of the region size.
0 en11
en11 Enable for region n:
0 = region n is disabled
1 = region n is enabled.
11.4.50 Region Setup Low 12 Register (region_setup_low_12)
11.4.50.1 Offset
Register Offset
region_setup_low_12 1C0h
11.4.50.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R base_address_low12
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
base_address_low12
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 487
register descriptions
11.4.50.3 Fields
Field Function
31-15 base_address_low12
base_address_l Controls the base address [31:15] of region n. For region 0, this field is Read Only (RO). The TZASC sets
ow12 the base address of region 0 to 0x0.
The TZASC only permits a region to start at address 0x0, or at a multiple of its region size. For example,
if the size of a region is 512MB, and it is not at address 0x0, the only valid settings for this field are:
b00100000000000000
b01000000000000000
b01100000000000000
b10000000000000000
b10100000000000000
b11000000000000000
b11100000000000000
If you attempt to set an inappropriate base address for the size of the region, the TZASC ignores certain
bits depending on the region size. See Table on register size for more information.
14-0 Reserved, Should be Zero (SBZ).
—
11.4.51 Region Setup High 12 Register (region_setup_high_12)
11.4.51.1 Offset
Register Offset
region_setup_high_12 1C4h
11.4.51.2 Function
The region_setup_high register is none for region 0, for other regions it controls the base
address [63:32] of region n.There are no usage constraints. Available in all configurations
of the TZASC.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
488 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
11.4.51.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R base_address_high12
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R base_address_high12
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11.4.51.4 Fields
Field Function
31-0 base_address_high12
base_address_h Controls the base address [63:32] of region n. For region 0, this field is RO. The TZASC sets the base
igh12 address of region 0 to 0x0.
The TZASC only permits a region to start at address 0x0, or at a multiple of its region size. If you program
a region size to be 8GB or more, then the TZASC might ignore certain bits depending on the region size.
11.4.52 Region Attributes 12 Register (region_attributes_12)
11.4.52.1 Offset
Register Offset
region_attributes_12 1C8h
11.4.52.2 Function
The region_attributes_n register controls the permissions, region size, subregion disable,
and region enable. There are no usage constraints. Available in all configurations of the
TZASC.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 489
register descriptions
Table 11-15. Region size
size<n> field Size of region <n> Base address [1] constraints
b000000-b001101 Reserved -
b001110 32KB -
b001111 64KB Bit [15] must be zero
b010000 128KB Bits [16:15] must be zero
b010001 256KB Bits [17:15] must be zero
b010010 512KB Bits [18:15] must be zero
b010011 1MB Bits [19:15] must be zero
b010100 2MB Bits [20:15] must be zero
b010101 4MB Bits [21:15] must be zero
b010110 8MB Bits [22:15] must be zero
b010111 16MB Bits [23:15] must be zero
b011000 32MB Bits [24:15] must be zero
b011001 64MB Bits [25:15] must be zero
b011010 128MB Bits [26:15] must be zero
b011011 256MB Bits [27:15] must be zero
b011100 512MB Bits [28:15] must be zero
b011101 1GB Bits [29:15] must be zero
b011110 2GB Bits [30:15] must be zero
b011111 4GB Bits [31:15] must be zero
b100000 8GB Bits [32:15] must be zero
b100001 16GB Bits [33:15] must be zero
b100010 32GB Bits [34:15] must be zero
b100011 64GB Bits [35:15] must be zero
b100100 128GB Bits [36:15] must be zero
b100101 256GB Bits [37:15] must be zero
b100110 512GB Bits [38:15] must be zero
b100111 1TB Bits [39:15] must be zero
b101000 2TB Bits [40:15] must be zero
b101001 4TB Bits [41:15] must be zero
b101010 8TB Bits [42:15] must be zero
b101011 16TB Bits [43:15] must be zero
b101100 32TB Bits [44:15] must be zero
b101101 64TB Bits [45:15] must be zero
b101110 128TB Bits [46:15] must be zero
b101111 256TB Bits [47:15] must be zero
b110000 512TB Bits [48:15] must be zero
b110001 1PB Bits [49:15] must be zero
b110010 2PB Bits [50:15] must be zero
b110011 4PB Bits [51:15] must be zero
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
490 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
Table 11-15. Region size (continued)
b110100 8PB Bits [52:15] must be zero
b110101 16PB Bits [53:15] must be zero
b110110 32PB Bits [54:15] must be zero
b110111 64PB Bits [55:15] must be zero
b111000 128PB Bits [56:15] must be zero
b111001 256PB Bits [57:15] must be zero
b111010 512PB Bits [58:15] must be zero
b111011 1EB Bits [59:15] must be zero
b111100 2EB Bits [60:15] must be zero
b111101 4EB Bits [61:15] must be zero
b111110 8EB Bits [62:15] must be zero
b111111 16EB Bits [63:15] must be zero
[1]The region_setup_low_<n> Register and region_setup_high_<n> Register contain the
base address. See Table 313 on page 318 and Table 314 on page 319.
11.4.52.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
sp12 Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
subregion_disable12
Reserved
size12
en12
W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0
11.4.52.4 Fields
Field Function
31-28 sp12
sp12
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 491
register descriptions
Field Function
Permissions setting for region n. If an AXI transaction occurs to region n, the value in the spn field
controls whether the TZASC permits the transaction to proceed.
27-16 Reserved, Should be Zero (SBZ).
—
15-8 subregion_disable12
subregion_disab Regions are split into eight equal-sized sub-regions, and each bit enables the corresponding subregion to
le12 be disabled:
Bit [15] = 1 Subregion 7 is disabled.
Bit [14] = 1 Subregion 6 is disabled.
Bit [13] = 1 Subregion 5 is disabled.
Bit [12] = 1 Subregion 4 is disabled.
Bit [11] = 1 Subregion 3 is disabled.
Bit [10] = 1 Subregion 2 is disabled.
Bit [9] = 1 Subregion 1 is disabled.
Bit [8] = 1 Subregion 0 is disabled.
7 Reserved, Should be Zero (SBZ).
—
6-1 size12
size12 Size of region n.The AXI address width, that is AXI_ADDRESS_MSB+1, controls the upper limit value of
this field.
The table below shows how the size n field controls the region size and what constraints, if any, the
TZASC applies to the base address to ensure that a region starts on the boundary of the region size.
0 en12
en12 Enable for region n:
0 = region n is disabled
1 = region n is enabled.
11.4.53 Region Setup Low 13 Register (region_setup_low_13)
11.4.53.1 Offset
Register Offset
region_setup_low_13 1D0h
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
492 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
11.4.53.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R base_address_low13
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
base_address_low13
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11.4.53.3 Fields
Field Function
31-15 base_address_low13
base_address_l Controls the base address [31:15] of region n. For region 0, this field is Read Only (RO). The TZASC sets
ow13 the base address of region 0 to 0x0.
The TZASC only permits a region to start at address 0x0, or at a multiple of its region size. For example,
if the size of a region is 512MB, and it is not at address 0x0, the only valid settings for this field are:
b00100000000000000
b01000000000000000
b01100000000000000
b10000000000000000
b10100000000000000
b11000000000000000
b11100000000000000
If you attempt to set an inappropriate base address for the size of the region, the TZASC ignores certain
bits depending on the region size. See Table on register size for more information.
14-0 Reserved, Should be Zero (SBZ).
—
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 493
register descriptions
11.4.54 Region Setup High 13 Register (region_setup_high_13)
11.4.54.1 Offset
Register Offset
region_setup_high_13 1D4h
11.4.54.2 Function
The region_setup_high register is none for region 0, for other regions it controls the base
address [63:32] of region n.There are no usage constraints. Available in all configurations
of the TZASC.
11.4.54.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R base_address_high13
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R base_address_high13
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11.4.54.4 Fields
Field Function
31-0 base_address_high13
base_address_h Controls the base address [63:32] of region n. For region 0, this field is RO. The TZASC sets the base
igh13 address of region 0 to 0x0.
The TZASC only permits a region to start at address 0x0, or at a multiple of its region size. If you program
a region size to be 8GB or more, then the TZASC might ignore certain bits depending on the region size.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
494 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
11.4.55 Region Attributes 13 Register (region_attributes_13)
11.4.55.1 Offset
Register Offset
region_attributes_13 1D8h
11.4.55.2 Function
The region_attributes_n register controls the permissions, region size, subregion disable,
and region enable. There are no usage constraints. Available in all configurations of the
TZASC.
Table 11-16. Region size
size<n> field Size of region <n> Base address [1] constraints
b000000-b001101 Reserved -
b001110 32KB -
b001111 64KB Bit [15] must be zero
b010000 128KB Bits [16:15] must be zero
b010001 256KB Bits [17:15] must be zero
b010010 512KB Bits [18:15] must be zero
b010011 1MB Bits [19:15] must be zero
b010100 2MB Bits [20:15] must be zero
b010101 4MB Bits [21:15] must be zero
b010110 8MB Bits [22:15] must be zero
b010111 16MB Bits [23:15] must be zero
b011000 32MB Bits [24:15] must be zero
b011001 64MB Bits [25:15] must be zero
b011010 128MB Bits [26:15] must be zero
b011011 256MB Bits [27:15] must be zero
b011100 512MB Bits [28:15] must be zero
b011101 1GB Bits [29:15] must be zero
b011110 2GB Bits [30:15] must be zero
b011111 4GB Bits [31:15] must be zero
b100000 8GB Bits [32:15] must be zero
b100001 16GB Bits [33:15] must be zero
b100010 32GB Bits [34:15] must be zero
b100011 64GB Bits [35:15] must be zero
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 495
register descriptions
Table 11-16. Region size (continued)
b100100 128GB Bits [36:15] must be zero
b100101 256GB Bits [37:15] must be zero
b100110 512GB Bits [38:15] must be zero
b100111 1TB Bits [39:15] must be zero
b101000 2TB Bits [40:15] must be zero
b101001 4TB Bits [41:15] must be zero
b101010 8TB Bits [42:15] must be zero
b101011 16TB Bits [43:15] must be zero
b101100 32TB Bits [44:15] must be zero
b101101 64TB Bits [45:15] must be zero
b101110 128TB Bits [46:15] must be zero
b101111 256TB Bits [47:15] must be zero
b110000 512TB Bits [48:15] must be zero
b110001 1PB Bits [49:15] must be zero
b110010 2PB Bits [50:15] must be zero
b110011 4PB Bits [51:15] must be zero
b110100 8PB Bits [52:15] must be zero
b110101 16PB Bits [53:15] must be zero
b110110 32PB Bits [54:15] must be zero
b110111 64PB Bits [55:15] must be zero
b111000 128PB Bits [56:15] must be zero
b111001 256PB Bits [57:15] must be zero
b111010 512PB Bits [58:15] must be zero
b111011 1EB Bits [59:15] must be zero
b111100 2EB Bits [60:15] must be zero
b111101 4EB Bits [61:15] must be zero
b111110 8EB Bits [62:15] must be zero
b111111 16EB Bits [63:15] must be zero
[1]The region_setup_low_<n> Register and region_setup_high_<n> Register contain the
base address. See Table 313 on page 318 and Table 314 on page 319.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
496 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
11.4.55.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
sp13 Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
subregion_disable13
Reserved
size13
en13
W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0
11.4.55.4 Fields
Field Function
31-28 sp13
sp13 Permissions setting for region n. If an AXI transaction occurs to region n, the value in the spn field
controls whether the TZASC permits the transaction to proceed.
27-16 Reserved, Should be Zero (SBZ).
—
15-8 subregion_disable13
subregion_disab Regions are split into eight equal-sized sub-regions, and each bit enables the corresponding subregion to
le13 be disabled:
Bit [15] = 1 Subregion 7 is disabled.
Bit [14] = 1 Subregion 6 is disabled.
Bit [13] = 1 Subregion 5 is disabled.
Bit [12] = 1 Subregion 4 is disabled.
Bit [11] = 1 Subregion 3 is disabled.
Bit [10] = 1 Subregion 2 is disabled.
Bit [9] = 1 Subregion 1 is disabled.
Bit [8] = 1 Subregion 0 is disabled.
7 Reserved, Should be Zero (SBZ).
—
6-1 size13
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 497
register descriptions
Field Function
size13 Size of region n.The AXI address width, that is AXI_ADDRESS_MSB+1, controls the upper limit value of
this field.
The table below shows how the size n field controls the region size and what constraints, if any, the
TZASC applies to the base address to ensure that a region starts on the boundary of the region size.
0 en13
en13 Enable for region n:
0 = region n is disabled
1 = region n is enabled.
11.4.56 Region Setup Low 14 Register (region_setup_low_14)
11.4.56.1 Offset
Register Offset
region_setup_low_14 1E0h
11.4.56.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R base_address_low14
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
base_address_low14
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
498 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
11.4.56.3 Fields
Field Function
31-15 base_address_low14
base_address_l Controls the base address [31:15] of region n. For region 0, this field is Read Only (RO). The TZASC sets
ow14 the base address of region 0 to 0x0.
The TZASC only permits a region to start at address 0x0, or at a multiple of its region size. For example,
if the size of a region is 512MB, and it is not at address 0x0, the only valid settings for this field are:
b00100000000000000
b01000000000000000
b01100000000000000
b10000000000000000
b10100000000000000
b11000000000000000
b11100000000000000
If you attempt to set an inappropriate base address for the size of the region, the TZASC ignores certain
bits depending on the region size. See Table on register size for more information.
14-0 Reserved, Should be Zero (SBZ).
—
11.4.57 Region Setup High 14 Register (region_setup_high_14)
11.4.57.1 Offset
Register Offset
region_setup_high_14 1E4h
11.4.57.2 Function
The region_setup_high register is none for region 0, for other regions it controls the base
address [63:32] of region n.There are no usage constraints. Available in all configurations
of the TZASC.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 499
register descriptions
11.4.57.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R base_address_high14
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R base_address_high14
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11.4.57.4 Fields
Field Function
31-0 base_address_high14
base_address_h Controls the base address [63:32] of region n. For region 0, this field is RO. The TZASC sets the base
igh14 address of region 0 to 0x0.
The TZASC only permits a region to start at address 0x0, or at a multiple of its region size. If you program
a region size to be 8GB or more, then the TZASC might ignore certain bits depending on the region size.
11.4.58 Region Attributes 14 Register (region_attributes_14)
11.4.58.1 Offset
Register Offset
region_attributes_14 1E8h
11.4.58.2 Function
The region_attributes_n register controls the permissions, region size, subregion disable,
and region enable. There are no usage constraints. Available in all configurations of the
TZASC.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
500 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
Table 11-17. Region size
size<n> field Size of region <n> Base address [1] constraints
b000000-b001101 Reserved -
b001110 32KB -
b001111 64KB Bit [15] must be zero
b010000 128KB Bits [16:15] must be zero
b010001 256KB Bits [17:15] must be zero
b010010 512KB Bits [18:15] must be zero
b010011 1MB Bits [19:15] must be zero
b010100 2MB Bits [20:15] must be zero
b010101 4MB Bits [21:15] must be zero
b010110 8MB Bits [22:15] must be zero
b010111 16MB Bits [23:15] must be zero
b011000 32MB Bits [24:15] must be zero
b011001 64MB Bits [25:15] must be zero
b011010 128MB Bits [26:15] must be zero
b011011 256MB Bits [27:15] must be zero
b011100 512MB Bits [28:15] must be zero
b011101 1GB Bits [29:15] must be zero
b011110 2GB Bits [30:15] must be zero
b011111 4GB Bits [31:15] must be zero
b100000 8GB Bits [32:15] must be zero
b100001 16GB Bits [33:15] must be zero
b100010 32GB Bits [34:15] must be zero
b100011 64GB Bits [35:15] must be zero
b100100 128GB Bits [36:15] must be zero
b100101 256GB Bits [37:15] must be zero
b100110 512GB Bits [38:15] must be zero
b100111 1TB Bits [39:15] must be zero
b101000 2TB Bits [40:15] must be zero
b101001 4TB Bits [41:15] must be zero
b101010 8TB Bits [42:15] must be zero
b101011 16TB Bits [43:15] must be zero
b101100 32TB Bits [44:15] must be zero
b101101 64TB Bits [45:15] must be zero
b101110 128TB Bits [46:15] must be zero
b101111 256TB Bits [47:15] must be zero
b110000 512TB Bits [48:15] must be zero
b110001 1PB Bits [49:15] must be zero
b110010 2PB Bits [50:15] must be zero
b110011 4PB Bits [51:15] must be zero
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 501
register descriptions
Table 11-17. Region size (continued)
b110100 8PB Bits [52:15] must be zero
b110101 16PB Bits [53:15] must be zero
b110110 32PB Bits [54:15] must be zero
b110111 64PB Bits [55:15] must be zero
b111000 128PB Bits [56:15] must be zero
b111001 256PB Bits [57:15] must be zero
b111010 512PB Bits [58:15] must be zero
b111011 1EB Bits [59:15] must be zero
b111100 2EB Bits [60:15] must be zero
b111101 4EB Bits [61:15] must be zero
b111110 8EB Bits [62:15] must be zero
b111111 16EB Bits [63:15] must be zero
[1]The region_setup_low_<n> Register and region_setup_high_<n> Register contain the
base address. See Table 313 on page 318 and Table 314 on page 319.
11.4.58.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
sp14 Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
subregion_disable14
Reserved
size14
en14
W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0
11.4.58.4 Fields
Field Function
31-28 sp14
sp14
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
502 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
Field Function
Permissions setting for region n. If an AXI transaction occurs to region n, the value in the spn field
controls whether the TZASC permits the transaction to proceed.
27-16 Reserved, Should be Zero (SBZ).
—
15-8 subregion_disable14
subregion_disab Regions are split into eight equal-sized sub-regions, and each bit enables the corresponding subregion to
le14 be disabled:
Bit [15] = 1 Subregion 7 is disabled.
Bit [14] = 1 Subregion 6 is disabled.
Bit [13] = 1 Subregion 5 is disabled.
Bit [12] = 1 Subregion 4 is disabled.
Bit [11] = 1 Subregion 3 is disabled.
Bit [10] = 1 Subregion 2 is disabled.
Bit [9] = 1 Subregion 1 is disabled.
Bit [8] = 1 Subregion 0 is disabled.
7 Reserved, Should be Zero (SBZ).
—
6-1 size14
size14 Size of region n.The AXI address width, that is AXI_ADDRESS_MSB+1, controls the upper limit value of
this field.
The table below shows how the size n field controls the region size and what constraints, if any, the
TZASC applies to the base address to ensure that a region starts on the boundary of the region size.
0 en14
en14 Enable for region n:
0 = region n is disabled
1 = region n is enabled.
11.4.59 Region Setup Low 15 Register (region_setup_low_15)
11.4.59.1 Offset
Register Offset
region_setup_low_15 1F0h
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 503
register descriptions
11.4.59.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R base_address_low15
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
base_address_low15
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11.4.59.3 Fields
Field Function
31-15 base_address_low15
base_address_l Controls the base address [31:15] of region n. For region 0, this field is Read Only (RO). The TZASC sets
ow15 the base address of region 0 to 0x0.
The TZASC only permits a region to start at address 0x0, or at a multiple of its region size. For example,
if the size of a region is 512MB, and it is not at address 0x0, the only valid settings for this field are:
b00100000000000000
b01000000000000000
b01100000000000000
b10000000000000000
b10100000000000000
b11000000000000000
b11100000000000000
If you attempt to set an inappropriate base address for the size of the region, the TZASC ignores certain
bits depending on the region size. See Table on register size for more information.
14-0 Reserved, Should be Zero (SBZ).
—
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
504 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
11.4.60 Region Setup High 15 Register (region_setup_high_15)
11.4.60.1 Offset
Register Offset
region_setup_high_15 1F4h
11.4.60.2 Function
The region_setup_high register is none for region 0, for other regions it controls the base
address [63:32] of region n.There are no usage constraints. Available in all configurations
of the TZASC.
11.4.60.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R base_address_high15
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R base_address_high15
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11.4.60.4 Fields
Field Function
31-0 base_address_high15
base_address_h Controls the base address [63:32] of region n. For region 0, this field is RO. The TZASC sets the base
igh15 address of region 0 to 0x0.
The TZASC only permits a region to start at address 0x0, or at a multiple of its region size. If you program
a region size to be 8GB or more, then the TZASC might ignore certain bits depending on the region size.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 505
register descriptions
11.4.61 Region Attributes 15 Register (region_attributes_15)
11.4.61.1 Offset
Register Offset
region_attributes_15 1F8h
11.4.61.2 Function
The region_attributes_n register controls the permissions, region size, subregion disable,
and region enable. There are no usage constraints. Available in all configurations of the
TZASC.
Table 11-18. Region size
size<n> field Size of region <n> Base address [1] constraints
b000000-b001101 Reserved -
b001110 32KB -
b001111 64KB Bit [15] must be zero
b010000 128KB Bits [16:15] must be zero
b010001 256KB Bits [17:15] must be zero
b010010 512KB Bits [18:15] must be zero
b010011 1MB Bits [19:15] must be zero
b010100 2MB Bits [20:15] must be zero
b010101 4MB Bits [21:15] must be zero
b010110 8MB Bits [22:15] must be zero
b010111 16MB Bits [23:15] must be zero
b011000 32MB Bits [24:15] must be zero
b011001 64MB Bits [25:15] must be zero
b011010 128MB Bits [26:15] must be zero
b011011 256MB Bits [27:15] must be zero
b011100 512MB Bits [28:15] must be zero
b011101 1GB Bits [29:15] must be zero
b011110 2GB Bits [30:15] must be zero
b011111 4GB Bits [31:15] must be zero
b100000 8GB Bits [32:15] must be zero
b100001 16GB Bits [33:15] must be zero
b100010 32GB Bits [34:15] must be zero
b100011 64GB Bits [35:15] must be zero
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
506 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
Table 11-18. Region size (continued)
b100100 128GB Bits [36:15] must be zero
b100101 256GB Bits [37:15] must be zero
b100110 512GB Bits [38:15] must be zero
b100111 1TB Bits [39:15] must be zero
b101000 2TB Bits [40:15] must be zero
b101001 4TB Bits [41:15] must be zero
b101010 8TB Bits [42:15] must be zero
b101011 16TB Bits [43:15] must be zero
b101100 32TB Bits [44:15] must be zero
b101101 64TB Bits [45:15] must be zero
b101110 128TB Bits [46:15] must be zero
b101111 256TB Bits [47:15] must be zero
b110000 512TB Bits [48:15] must be zero
b110001 1PB Bits [49:15] must be zero
b110010 2PB Bits [50:15] must be zero
b110011 4PB Bits [51:15] must be zero
b110100 8PB Bits [52:15] must be zero
b110101 16PB Bits [53:15] must be zero
b110110 32PB Bits [54:15] must be zero
b110111 64PB Bits [55:15] must be zero
b111000 128PB Bits [56:15] must be zero
b111001 256PB Bits [57:15] must be zero
b111010 512PB Bits [58:15] must be zero
b111011 1EB Bits [59:15] must be zero
b111100 2EB Bits [60:15] must be zero
b111101 4EB Bits [61:15] must be zero
b111110 8EB Bits [62:15] must be zero
b111111 16EB Bits [63:15] must be zero
[1]The region_setup_low_<n> Register and region_setup_high_<n> Register contain the
base address. See Table 313 on page 318 and Table 314 on page 319.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 507
register descriptions
11.4.61.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
sp15 Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
subregion_disable15
Reserved
size15
en15
W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0
11.4.61.4 Fields
Field Function
31-28 sp15
sp15 Permissions setting for region n. If an AXI transaction occurs to region n, the value in the spn field
controls whether the TZASC permits the transaction to proceed.
27-16 Reserved, Should be Zero (SBZ).
—
15-8 subregion_disable15
subregion_disab Regions are split into eight equal-sized sub-regions, and each bit enables the corresponding subregion to
le15 be disabled:
Bit [15] = 1 Subregion 7 is disabled.
Bit [14] = 1 Subregion 6 is disabled.
Bit [13] = 1 Subregion 5 is disabled.
Bit [12] = 1 Subregion 4 is disabled.
Bit [11] = 1 Subregion 3 is disabled.
Bit [10] = 1 Subregion 2 is disabled.
Bit [9] = 1 Subregion 1 is disabled.
Bit [8] = 1 Subregion 0 is disabled.
7 Reserved, Should be Zero (SBZ).
—
6-1 size15
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
508 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
Field Function
size15 Size of region n.The AXI address width, that is AXI_ADDRESS_MSB+1, controls the upper limit value of
this field.
The table below shows how the size n field controls the region size and what constraints, if any, the
TZASC applies to the base address to ensure that a region starts on the boundary of the region size.
0 en15
en15 Enable for region n:
0 = region n is disabled
1 = region n is enabled.
11.4.62 Integration Test Control Register (itcrg)
11.4.62.1 Offset
Register Offset
itcrg E00h
11.4.62.2 Function
The itcrg register enables the integration test logic. Use this in integration test mode.
Available in all configurations of the TZASC.
11.4.62.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
int_test_en
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 509
register descriptions
11.4.62.4 Fields
Field Function
31-1 Undefined. Write as zero.
—
0 int_test_en
int_test_en Controls the enabling of, or provides the status of, the integration test logic:
0 = integration test logic is disabled
1 = integration test logic is enabled.
11.4.63 Integration Test Input Register (itip)
11.4.63.1 Offset
Register Offset
itip E04h
11.4.63.2 Function
The itip register enables a processor to read the status of secure_boot_lock. Integration
test logic must be enabled otherwise reads return 0x0. See Integration Test Control
Register for information about enabling the integration test logic. Available in all
configurations of the TZASC.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
510 NXP Semiconductors
Chapter 11 Arm CoreLink™ TrustZone Address Space Controller TZC-380
11.4.63.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
itip_secure_boot_lock
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11.4.63.4 Fields
Field Function
31-1 Reserved.
—
0 itip_secure_boot_lock
itip_secure_boot
_lock
11.4.64 Integration Test Output Register (itop)
11.4.64.1 Offset
Register Offset
itop E08h
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 511
register descriptions
11.4.64.2 Function
The itop register enables a processor to set the status of tzasc_int in integration test mode.
Usage constraints Integration test logic must be enabled otherwise it ignores writes and
reads return 0x0. See Integration Test Control Register for information about enabling the
integration test logic. Available in all configurations of the TZASC.
11.4.64.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
itop_int
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11.4.64.4 Fields
Field Function
31-1 Undefined. Write as zero.
—
0 itop_int
itop_int Set or reset the value of tzasc_int port by writing 1 or 0 into itop_int bit. If you read, the written value can
be read back.
0 = tzasc_int is LOW
1 = tzasc_int is HIGH.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
512 NXP Semiconductors
Chapter 12
Supplemental Configuration Unit
12.1 Introduction
The supplemental configuration unit provides device specific configuration and status
registers for the device. It is the chip defined module for extending the device
configuration unit (DCFG) module. It provides a set of CCSR space registers in addition
to those available in the device configuration unit. There are no source and target IDs
associated with this unit
12.2 Overview
The supplement configuration unit contains the following registers:
• Chip specific control and status registers (CCSR)
• Pinmux control registers(CCSR)
12.3 SCFG Memory Map/Register Definition
SCFG memory map
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
USB1 Parameter 1 Control Register
157_0070 32 R/W 25E7_2B2Ah 12.3.1/517
(SCFG_USB1PRM1CR)
USB1 Parameter 2 Control Register
157_0074 32 R/W 17C1_FF48h 12.3.2/519
(SCFG_USB1PRM2CR)
USB1 Parameter 3 Control Register
157_0078 32 R/W 0000_0000h 12.3.3/520
(SCFG_USB1PRM3CR)
USB2 Parameter 1 Control Register
157_007C 32 R/W 25E7_2B2Ah 12.3.4/521
(SCFG_USB2PRM1CR)
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 513
SCFG Memory Map/Register Definition
SCFG memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
USB2 Parameter 2 Control Register
157_0080 32 R/W 17C1_FF48h 12.3.5/523
(SCFG_USB2PRM2CR)
157_0084 USB2 Parameter3 Control Register (SCFG_USB2PRM3CR) 32 R/W 0000_0000h 12.3.6/524
USB3 Parameter 1 Control Register
157_0088 32 R/W 25E7_2B2Ah 12.3.7/525
(SCFG_USB3PRM1CR)
USB3 Parameter 2 Control Register
157_008C 32 R/W 17C1_FF48h 12.3.8/526
(SCFG_USB3PRM2CR)
USB3 Parameter 3 Control Register
157_0090 32 R/W 0000_0000h 12.3.9/528
(SCFG_USB3PRM3CR)
12.3.10/
157_0100 USB2 ICID Register (SCFG_USB2_ICID) 32 R/W 0000_0000h
529
12.3.11/
157_0104 USB3 ICID Register (SCFG_USB3_ICID) 32 R/W 0000_0000h
530
12.3.12/
157_0114 qDMA ICID Register (SCFG_DMA_ICID) 32 R/W 0000_0000h
531
12.3.13/
157_0118 SATA ICID Register (SCFG_SATA_ICID) 32 R/W 0000_0000h
532
12.3.14/
157_011C USB1 ICID Register (SCFG_USB1_ICID) 32 R/W 0000_0000h
533
12.3.15/
157_0120 QE ICID Register (SCFG_QE_ICID) 32 R/W 0000_0000h
534
12.3.16/
157_0124 eSDHC ICID Register (SCFG_SDHC_ICID) 32 R/W 0000_0000h
535
12.3.17/
157_0128 eDMA ICID Register (SCFG_eDMA_ICID) 32 R/W 0000_0000h
536
12.3.18/
157_012C ETR ICID Register (SCFG_ETR_ICID) 32 R/W 0000_0000h
537
12.3.19/
157_0130 Core 0 soft reset Register (SCFG_CORE0_SFT_RST) 32 R/W 0000_0000h
538
12.3.20/
157_0134 Core 1 soft reset Register (SCFG_CORE1_SFT_RST) 32 R/W 0000_0000h
539
12.3.21/
157_0138 Core 2 soft reset Register (SCFG_CORE2_SFT_RST) 32 R/W 0000_0000h
540
12.3.22/
157_013C Core 3soft reset Register (SCFG_CORE3_SFT_RST) 32 R/W 0000_0000h
541
12.3.23/
157_0144 PEX PME control register (SCFG_PEXPMECR) 32 R/W 0000_0000h
542
12.3.24/
157_0154 FTM chain configuration (SCFG_FTM_CHAIN_CONFIG) 32 R/W 0000_0000h
543
12.3.25/
157_0158 ALTCBAR Register (SCFG_ALTCBAR) 32 R/W 0000_0000h
544
12.3.26/
157_015C QSPI CONFIG Register (SCFG_QSPI_CFG) 32 R/W 0010_0000h
544
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
514 NXP Semiconductors
Chapter 12 Supplemental Configuration Unit
SCFG memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
12.3.27/
157_016C QOS1 Register (SCFG_QOS1) 32 R/W 0000_0000h
545
12.3.28/
157_0170 QOS2 Register (SCFG_QOS2) 32 R/W 0000_0000h
546
GIC-400 Address 64K Page Alignment Register 12.3.29/
157_0188 32 R/W 0700_0000h
(SCFG_GIC400_ADDR_ALIGN_64K) 547
12.3.30/
157_018C Debug ICID Register (SCFG_Debug_ICID) 32 R/W 0700_0000h
548
12.3.31/
157_01A4 Snoop Configuration Register (SCFG_SNPCNFGCR) 32 R/W 0000_0000h
549
12.3.32/
157_01AC Interrupt Polarity Register (SCFG_INTPCR) 32 R/W 0000_0000h
551
12.3.33/
157_0204 CORE Soft Reset Enable Register (SCFG_CORESRENCR) 32 R/W 0000_0000h
553
12.3.34/
157_0220 Core 0 Reset Vector Base Address0 (SCFG_RVBAR0_0) 32 R/W 0000_0000h
553
12.3.35/
157_0224 Core 0 Reset Vector Base Address1 (SCFG_RVBAR0_1) 32 R/W 0000_0000h
554
12.3.36/
157_0228 Core 1 Reset Vector Base Address0 (SCFG_RVBAR1_0) 32 R/W 0000_0000h
555
12.3.37/
157_022C Core 1 Reset Vector Base Address1 (SCFG_RVBAR1_1) 32 R/W 0000_0000h
555
12.3.38/
157_0230 Core 2 Reset Vector Base Address0 (SCFG_RVBAR2_0) 32 R/W 0000_0000h
556
12.3.39/
157_0234 Core 2 Reset Vector Base Address1 (SCFG_RVBAR2_1) 32 R/W 0000_0000h
556
12.3.40/
157_0238 Core 3 Reset Vector Base Address0 (SCFG_RVBAR3_0) 32 R/W 0000_0000h
557
12.3.41/
157_023C Core 3 Reset Vector Base Address1 (SCFG_RVBAR3_1) 32 R/W 0000_0000h
557
Core Low Power Mode Control Status Register 12.3.42/
157_0240 32 R/W 0101_0101h
(SCFG_LPMCSR) 558
12.3.43/
157_0404 ECGTX Clock Mux Control Register (SCFG_ECGTXCMCR) 32 R/W 0000_0000h
560
12.3.44/
157_0408 SDHC IO VSEL Control Register (SCFG_SDHCIOVSELCR) 32 R/W 0000_0000h
561
Extended RCW PinMux Control Register 12.3.45/
157_040C 32 R/W 0000_0000h
(SCFG_RCWPMUXCR0) 562
USB DRVVBUS Control Register 12.3.46/
157_0410 32 R/W 0000_0000h
(SCFG_USBDRVVBUS_SELCR) 564
USB PWRFAULTControl Register 12.3.47/
157_0414 32 R/W 0000_0000h
(SCFG_USBPWRFAULT_SELCR) 564
USB PHY1 Reference Clock Select Register 12.3.48/
157_0418 32 R/W 8000_009Eh
(SCFG_USB_REFCLK_SELCR1) 565
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 515
SCFG Memory Map/Register Definition
SCFG memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
USB PHY2 Reference Clock Select Register 12.3.49/
157_041C 32 R/W 8000_009Eh
(SCFG_USB_REFCLK_SELCR2) 566
USB PHY3 Reference Clock Select Register 12.3.50/
157_0420 32 R/W 8000_009Eh
(SCFG_USB_REFCLK_SELCR3) 567
12.3.51/
157_0424 Retention Request Control Register (SCFG_RETREQCR) 32 R/W 0000_0000h
568
12.3.52/
157_042C CORE PM Control Register (SCFG_COREPMCR) 32 R/W 0000_0000h
569
SCRATCHRWn - Scratch Read Write Registers 12.3.53/
157_0600 32 R/W 0000_0000h
(SCFG_SCRATCHRW0) 569
SCRATCHRWn - Scratch Read Write Registers 12.3.53/
157_0604 32 R/W 0000_0000h
(SCFG_SCRATCHRW1) 569
SCRATCHRWn - Scratch Read Write Registers 12.3.53/
157_0608 32 R/W 0000_0000h
(SCFG_SCRATCHRW2) 569
SCRATCHRWn - Scratch Read Write Registers 12.3.53/
157_060C 32 R/W 0000_0000h
(SCFG_SCRATCHRW3) 569
12.3.54/
157_0680 Core Boot Control Register (SCFG_COREBCR) 32 R/W 0000_0000h
570
Shared Message Signaled Interrupt Index Register 12.3.55/
157_1000 32 R/W 0000_0000h
(SCFG_G0MSIIR) 571
Shared Message Signaled Interrupt Register 12.3.56/
157_1010 32 R 0000_0000h
(SCFG_G0MSIR1) 573
Shared Message Signaled Interrupt Register 12.3.57/
157_1014 32 R 0000_0000h
(SCFG_G0MSIR2) 573
Shared Message Signaled Interrupt Register 12.3.58/
157_1018 32 R 0000_0000h
(SCFG_G0MSIR3) 574
Shared Message Signaled Interrupt Register 12.3.59/
157_101C 32 R 0000_0000h
(SCFG_G0MSIR4) 574
Shared Message Signaled Interrupt Index Register 12.3.60/
157_2000 32 R/W 0000_0000h
(SCFG_G1MSIIR) 575
Shared Message Signaled Interrupt Register 12.3.61/
157_2010 32 R 0000_0000h
(SCFG_G1MSIR1) 577
Shared Message Signaled Interrupt Register 12.3.62/
157_2014 32 R 0000_0000h
(SCFG_G1MSIR2) 577
Shared Message Signaled Interrupt Register 12.3.63/
157_2018 32 R 0000_0000h
(SCFG_G1MSIR3) 578
Shared Message Signaled Interrupt Register 12.3.64/
157_201C 32 R 0000_0000h
(SCFG_G1MSIR4) 578
Shared Message Signaled Interrupt Index Register 12.3.65/
157_3000 32 R/W 0000_0000h
(SCFG_G2MSIIR) 579
Shared Message Signaled Interrupt Register 12.3.66/
157_3010 32 R 0000_0000h
(SCFG_G2MSIR1) 581
Shared Message Signaled Interrupt Register 12.3.67/
157_3014 32 R 0000_0000h
(SCFG_G2MSIR2) 581
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
516 NXP Semiconductors
Chapter 12 Supplemental Configuration Unit
SCFG memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Shared Message Signaled Interrupt Register 12.3.68/
157_3018 32 R 0000_0000h
(SCFG_G2MSIR3) 582
Shared Message Signaled Interrupt Register 12.3.69/
157_301C 32 R 0000_0000h
(SCFG_G2MSIR4) 582
12.3.1 USB1 Parameter 1 Control Register (SCFG_USB1PRM1CR)
This register contains the USB1 parameters signals. This register is reset on HRESET.
Note that the signals described in the register are described as big endian(0:x) however
the signals in the USB1 interface are little endian(x:0). The connectivity is done in such a
way that bit 0 of the following register field corresponds to bit 0 of the USB1 interface.
Address: 157_0000h base + 70h offset = 157_0070h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
TXPREEMPAMPT
TXHSXVTUNE
R
UNE
COMPDISTUNE OTGTUNE0 SQRXTUNE TXFSLSTUNE
Reset 0 0 1 0 0 1 0 1 1 1 1 0 0 1 1 1
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
TXPREEMPPULSE
TXPREEMPAMPT
TXRISETUNE
TXRESTUNE
R
TUNE
UNE
TXVREFTUNE PCSTXDEEMPH3P5DB
Reset 0 0 1 0 1 0 1 1 0 0 1 0 1 0 1 0
SCFG_USB1PRM1CR field descriptions
Field Description
0–2 It drives the value of USB3 COMPDISTUNE signal.
COMPDISTUNE
Disconnect threshold adjustment: It adjusts the voltage level for the threshold used to detect a
disconnect event at the host.
3–5 It drives the value of USB3 OTGTUNE0 signal.
OTGTUNE0
VBUS valid threshold adjustment: This bus adjusts the voltage level for the VBUS valid threshold.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 517
SCFG Memory Map/Register Definition
SCFG_USB1PRM1CR field descriptions (continued)
Field Description
6–8 It drives the value of USB3 SQRXTUNE signal.
SQRXTUNE
Squelch threshold adjustment: It adjusts the voltage level for the threshold used to detect valid
high speed data.
9–12 It drives the value of USB3 TXFSLSTUNE signal.
TXFSLSTUNE
FS/LS source impedance adjustment: It adjusts the low and full speed single-ended source
impedance while driving high.
13–14 It drives the value of USB3 TXHSXVTUNE signal.
TXHSXVTUNE
Transmitter high speed crossover adjustment: This bus adjusts the voltage at which the D+ and
D- signals cross while transmitting in HS mode.
11 Default
10 + 15 mV
01 – 15 mV
00 Reserved
15–16 It drives the value of USB3 TXPREEMPAMPTUNE signal.
TXPREEMPAMPTUNE
HS transmitter pre-emphasis current control: This signal controls the amount of current sourced to
D+ and D- after a J-to-K or K-to-J transition. The HS transmitter pre-emphasis current is defined in
terms of unit amounts. One unit amount is approximately 600 μA and is defined as 1X pre-
emphasis current.
11 HS transmitter pre-emphasis circuit sources 3X pre-emphasis current
10 HS transmitter pre-emphasis circuit sources 2X pre-emphasis current
01 HS transmitter pre-emphasis circuit sources 1X preemphasis current
00 HS transmitter pre-emphasis disabled (Default)
17 It drives the value of USB3 TXPREEMPPULSETUNE signal.
TXPREEMPPULSETUNE
HS transmitter pre-emphasis duration control: This signal controls the duration for which the HS
pre-emphasis current is sourced onto D+ or D-. The HS transmitter pre-emphasis duration is
defined in terms of unit amounts. One unit of pre-emphasis duration is approximately 580 ps and
is defined as 1X pre-emphasis duration. This signal is valid only if either
TXPREEMPAMPTUNE[1] or TXPREEMPAMPTUNE[0] is set to 1'b1.
1 1X, short pre-emphasis current duration
0 2X (Default), long pre-emphasis current duration
18–19 It drives the value of USB3 TXRESTUNE signal.
TXRESTUNE
USB source impedance adjustment: This bus adjusts the driver source impedance to compensate
for added series resistance on the USB.
11 Source impedance is decreased by approximately 4 Ω.
10 Source impedance is decreased by approximately 2 Ω.
01 Default
00 Source impedance is increased by approximately 1.5 Ω.
20–21 It drives the value of USB3 TXRISETUNE signal.
TXRISETUNE
HS transmitter rise/fall time adjustment: It adjusts the rise/fall times of the high-speed waveform.
22–25 It drives the value of USB3 TXVREFTUNE signal.
TXVREFTUNE
HS DC voltage level adjustment: It adjusts the high speed DC level voltage.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
518 NXP Semiconductors
Chapter 12 Supplemental Configuration Unit
SCFG_USB1PRM1CR field descriptions (continued)
Field Description
26–31 It drives the value of USB3 pcs_tx_deemph_3p5db (Tx de-emphasis at 3.5 dB) signal.
PCSTXDEEMPH3P5DB
12.3.2 USB1 Parameter 2 Control Register (SCFG_USB1PRM2CR)
The USB1 parameter 2 control register contains the USB1 parameters signals. This
register is reset on HRESET.
Note that the signals described in the register are described as big endian(0:x) however
the signals in the USB1 interface are little endian(x:0). The connectivity is done in such a
way that bit 0 of the following register field corresponds to bit 0 of the USB1 interface.
Address: 157_0000h base + 74h offset = 157_0074h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
W
PCSRXLOSMASKVAL PCSTXDEEMPH6DB
Reset 0 0 0 1 0 1 1 1 1 1 0 0 0 0 0 1
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
PCSTXSWINGFULL LOSBIAS TXVBOOSTLVL —
Reset 1 1 1 1 1 1 1 1 0 1 0 0 1 0 0 0
SCFG_USB1PRM2CR field descriptions
Field Description
0–9 It drives the value of USB3 pcs_rx_los_mask_val signal.
PCSRXLOSMASKVAL
Configurable loss-of-signal mask width: It sets the number of reference clock cycles to mask the
incoming LFPS in U3 and U2 states. It masks the incoming LFPS for the number of reference clock
cycles equal to the value of pcs_rx_los_mask_val[9:0]. This control filters out short, non-compliant
LFPS glitches sent by a non-compliant host.
If this bus is set to 10'b0, it disables masking. This bus should be accessible to general configuration
registers for system testing and debug. The value should be defined only in reset. Changing this
value during operation might disrupt normal operation of the link.
10–15 It drives the value of USB3 pcs_tx_deemph_6db signal.
PCSTXDEEMPH6DB
Tx de-emphasis at 6 dB: This bus is provided for completeness and as a second potential launch
amplitude.
16–22 It drives the value of USB3 pcs_tx_swing_full signal.
PCSTXSWINGFULL
Tx amplitude (full swing mode): This static value sets the launch amplitude of the transmitter.
23–25 It drives the value of USB3 los_bias signal.
LOSBIAS
Loss-of-signal detector threshold level control: It sets the LOS detection threshold level.
A positive binary bit setting change results in a +15 mVp incremental change in the LOS threshold. A
negative binary bit setting change results in a –15 mVp incremental change in the LOS threshold.
The 3b'000 setting is reserved and must not be used.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 519
SCFG Memory Map/Register Definition
SCFG_USB1PRM2CR field descriptions (continued)
Field Description
26–28 It drives the value of USB3 tx_vboost_lvl signal.
TXVBOOSTLVL
Tx voltage boost level: It sets the boosted transmit launch amplitude (mVppd).
29–31 Reserved
—
12.3.3 USB1 Parameter 3 Control Register (SCFG_USB1PRM3CR)
The USB1 parameter 3 control register contains the USB1 parameters signals. This
register is reset on HRESET.
Note that the signals described in the register are described as big endian(0:x) however
the signals in the USB1 interface are little endian(x:0). The connectivity is done in such a
way that bit 0 of the following register field corresponds to bit 0 of the USB1 interface.
Address: 157_0000h base + 78h offset = 157_0078h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
LNTX2RXLPB
VATESTENB
LPBKENB0
USB1ACJT mPLL_MULT
K
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
—
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCFG_USB1PRM3CR field descriptions
Field Description
0–4 Drives the value of USB3 acjt_level signal
USB1ACJT
5–6 Drives the value of USB3 PHY VATESTENB signal
VATESTENB
7 Drives the value of USB3 PHY LOOPBACKENB0 signal
LPBKENB0
8 Drives the value of all 3 USB3 PHYs lane0_tx2rx_loopbk signal
LNTX2RXLPBK
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
520 NXP Semiconductors
Chapter 12 Supplemental Configuration Unit
SCFG_USB1PRM3CR field descriptions (continued)
Field Description
9–15 Drives the value of USB3 mpll_multiplier signal
mPLL_MULT
16–31 Reserved
—
12.3.4 USB2 Parameter 1 Control Register (SCFG_USB2PRM1CR)
The USB2 parameter 1 control register contains the USB2 parameters signals. This
register is reset on HRESET.
Note that the signals described in the register are described as big endian(0:x) however
the signals in the USB2 interface are little endian(x:0). The connectivity is done in such a
way that bit 0 of the following register field corresponds to bit 0 of the USB2 interface.
Address: 157_0000h base + 7Ch offset = 157_007Ch
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
TXPREEMPAMPT
TXHSXVTUNE
R
UNE
COMPDISTUNE OTGTUNE0 SQRXTUNE TXFSLSTUNE
Reset 0 0 1 0 0 1 0 1 1 1 1 0 0 1 1 1
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
TXPREEMPPULSE
TXPREEMPAMPT
TXRISETUNE
TXRESTUNE
R
TUNE
UNE
TXVREFTUNE PCSTXDEEMPH3P5DB
Reset 0 0 1 0 1 0 1 1 0 0 1 0 1 0 1 0
SCFG_USB2PRM1CR field descriptions
Field Description
0–2 It drives the value of USB3 COMPDISTUNE signal.
COMPDISTUNE
Disconnect threshold adjustment: It adjusts the voltage level for the threshold used to detect a
disconnect event at the host.
3–5 It drives the value of USB3 OTGTUNE0 signal.
OTGTUNE0
VBUS valid threshold adjustment: This bus adjusts the voltage level for the VBUS valid threshold.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 521
SCFG Memory Map/Register Definition
SCFG_USB2PRM1CR field descriptions (continued)
Field Description
6–8 It drives the value of USB3 SQRXTUNE signal.
SQRXTUNE
Squelch threshold adjustment: It adjusts the voltage level for the threshold used to detect valid
high speed data.
9–12 It drives the value of USB3 TXFSLSTUNE signal.
TXFSLSTUNE
FS/LS source impedance adjustment: It adjusts the low and full speed single-ended source
impedance while driving high.
13–14 It drives the value of USB3 TXHSXVTUNE signal.
TXHSXVTUNE
Transmitter high speed crossover adjustment: This bus adjusts the voltage at which the D+ and
D- signals cross while transmitting in HS mode.
11 Default
10 + 15 mV
01 – 15 mV
00 Reserved
15–16 It drives the value of USB3 TXPREEMPAMPTUNE signal.
TXPREEMPAMPTUNE
HS transmitter pre-emphasis current control: This signal controls the amount of current sourced to
D+ and D- after a J-to-K or K-to-J transition. The HS transmitter pre-emphasis current is defined in
terms of unit amounts. One unit amount is approximately 600 μA and is defined as 1X pre-
emphasis current.
11 HS transmitter pre-emphasis circuit sources 3X pre-emphasis current
10 HS transmitter pre-emphasis circuit sources 2X pre-emphasis current
01 HS transmitter pre-emphasis circuit sources 1X preemphasis current
00 HS transmitter pre-emphasis disabled (Default)
17 It drives the value of USB3 TXPREEMPPULSETUNE signal.
TXPREEMPPULSETUNE
HS transmitter pre-emphasis duration control: This signal controls the duration for which the HS
pre-emphasis current is sourced onto D+ or D-. The HS transmitter pre-emphasis duration is
defined in terms of unit amounts. One unit of pre-emphasis duration is approximately 580 ps and
is defined as 1X pre-emphasis duration. This signal is valid only if either
TXPREEMPAMPTUNE[1] or TXPREEMPAMPTUNE[0] is set to 1'b1.
1 1X, short pre-emphasis current duration
0 2X (Default), long pre-emphasis current duration
18–19 It drives the value of USB3 TXRESTUNE signal.
TXRESTUNE
USB source impedance adjustment: This bus adjusts the driver source impedance to compensate
for added series resistance on the USB.
11 Source impedance is decreased by approximately 4 Ω.
10 Source impedance is decreased by approximately 2 Ω.
01 Default
00 Source impedance is increased by approximately 1.5 Ω.
20–21 It drives the value of USB3 TXRISETUNE signal.
TXRISETUNE
HS transmitter rise/fall time adjustment: It adjusts the rise/fall times of the high-speed waveform.
22–25 It drives the value of USB3 TXVREFTUNE signal.
TXVREFTUNE
HS DC voltage level adjustment: It adjusts the high speed DC level voltage.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
522 NXP Semiconductors
Chapter 12 Supplemental Configuration Unit
SCFG_USB2PRM1CR field descriptions (continued)
Field Description
26–31 It drives the value of USB3 pcs_tx_deemph_3p5db (Tx de-emphasis at 3.5 dB) signal.
PCSTXDEEMPH3P5DB
12.3.5 USB2 Parameter 2 Control Register (SCFG_USB2PRM2CR)
The USB2 parameter 2 control register contains the USB2 parameters signals. This
register is reset on HRESET.
Note that the signals described in the register are described as big endian(0:x) however
the signals in the USB2 interface are little endian(x:0). The connectivity is done in such a
way that bit 0 of the following register field corresponds to bit 0 of the USB2 interface.
Address: 157_0000h base + 80h offset = 157_0080h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
W
PCSRXLOSMASKVAL PCSTXDEEMPH6DB
Reset 0 0 0 1 0 1 1 1 1 1 0 0 0 0 0 1
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
PCSTXSWINGFULL LOSBIAS TXVBOOSTLVL —
Reset 1 1 1 1 1 1 1 1 0 1 0 0 1 0 0 0
SCFG_USB2PRM2CR field descriptions
Field Description
0–9 It drives the value of USB3 pcs_rx_los_mask_val signal.
PCSRXLOSMASKVAL
Configurable loss-of-signal mask width: It sets the number of reference clock cycles to mask the
incoming LFPS in U3 and U2 states. It masks the incoming LFPS for the number of reference clock
cycles equal to the value of pcs_rx_los_mask_val[9:0]. This control filters out short, non-compliant
LFPS glitches sent by a non-compliant host.
If this bus is set to 10'b0, it disables masking. This bus should be accessible to general configuration
registers for system testing and debug. The value should be defined only in reset. Changing this
value during operation might disrupt normal operation of the link.
10–15 It drives the value of USB3 pcs_tx_deemph_6db signal.
PCSTXDEEMPH6DB
Tx de-emphasis at 6 dB: This bus is provided for completeness and as a second potential launch
amplitude.
16–22 It drives the value of USB3 pcs_tx_swing_full signal.
PCSTXSWINGFULL
Tx amplitude (full swing mode): This static value sets the launch amplitude of the transmitter.
23–25 It drives the value of USB3 los_bias signal.
LOSBIAS
Loss-of-signal detector threshold level control: It sets the LOS detection threshold level.
A positive binary bit setting change results in a +15 mVp incremental change in the LOS threshold. A
negative binary bit setting change results in a –15 mVp incremental change in the LOS threshold.
The 3b'000 setting is reserved and must not be used.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 523
SCFG Memory Map/Register Definition
SCFG_USB2PRM2CR field descriptions (continued)
Field Description
26–28 It drives the value of USB3 tx_vboost_lvl signal.
TXVBOOSTLVL
Tx voltage boost level: It sets the boosted transmit launch amplitude (mVppd).
29–31 Reserved
—
12.3.6 USB2 Parameter3 Control Register (SCFG_USB2PRM3CR)
The USB2 parameter 3 control register contains the USB2 parameters signals. This
register is reset on HRESET
Note that the signals described in the register are described as big endian(0:x) however
the signals in the USB2 interface are little endian(x:0). The connectivity is done in such a
way that bit 0 of the following register field corresponds to bit 0 of the USB2 interface.
Address: 157_0000h base + 84h offset = 157_0084h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
LPBKENB0
USB2ACJT VATESTENB — mPLL_MULT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
—
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCFG_USB2PRM3CR field descriptions
Field Description
0–4 Drives the value of USB2 acjt_level signal
USB2ACJT
5–6 Drives the value of USB3 PHY VATESTENB signal
VATESTENB
7 Drives the value of USB3 PHY LOOPBACKENB0 signal
LPBKENB0
8 Reserved
—
9–15 Drives the value of USB3 mpll_multiplier signal
mPLL_MULT
16–31 Reserved
—
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
524 NXP Semiconductors
Chapter 12 Supplemental Configuration Unit
12.3.7 USB3 Parameter 1 Control Register (SCFG_USB3PRM1CR)
The USB3 parameter 1 control register contains the USB3 parameters signals. This
register is reset on HRESET.
Note that the signals described in the register are described as big endian(0:x) however
the signals in the USB3 interface are little endian(x:0). The connectivity is done in such a
way that bit 0 of the following register field corresponds to bit 0 of the USB3 interface.
Address: 157_0000h base + 88h offset = 157_0088h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
TXPREEMPAMPT
TXHSXVTUNE
R
UNE
COMPDISTUNE OTGTUNE0 SQRXTUNE TXFSLSTUNE
Reset 0 0 1 0 0 1 0 1 1 1 1 0 0 1 1 1
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
TXPREEMPPULSE
TXPREEMPAMPT
TXRISETUNE
TXRESTUNE
R
TUNE
UNE
TXVREFTUNE PCSTXDEEMPH3P5DB
Reset 0 0 1 0 1 0 1 1 0 0 1 0 1 0 1 0
SCFG_USB3PRM1CR field descriptions
Field Description
0–2 It drives the value of USB3 COMPDISTUNE signal.
COMPDISTUNE
Disconnect threshold adjustment: It adjusts the voltage level for the threshold used to detect a
disconnect event at the host.
3–5 It drives the value of USB3 OTGTUNE0 signal.
OTGTUNE0
VBUS valid threshold adjustment: This bus adjusts the voltage level for the VBUS valid threshold.
6–8 It drives the value of USB3 SQRXTUNE signal.
SQRXTUNE
Squelch threshold adjustment: It adjusts the voltage level for the threshold used to detect valid
high speed data.
9–12 It drives the value of USB3 TXFSLSTUNE signal.
TXFSLSTUNE
FS/LS source impedance adjustment: It adjusts the low and full speed single-ended source
impedance while driving high.
13–14 It drives the value of USB3 TXHSXVTUNE signal.
TXHSXVTUNE
Transmitter high speed crossover adjustment: This bus adjusts the voltage at which the D+ and
D- signals cross while transmitting in HS mode.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 525
SCFG Memory Map/Register Definition
SCFG_USB3PRM1CR field descriptions (continued)
Field Description
11 Default
10 + 15 mV
01 – 15 mV
00 Reserved
15–16 It drives the value of USB3 TXPREEMPAMPTUNE signal.
TXPREEMPAMPTUNE
HS transmitter pre-emphasis current control: This signal controls the amount of current sourced to
D+ and D- after a J-to-K or K-to-J transition. The HS transmitter pre-emphasis current is defined in
terms of unit amounts. One unit amount is approximately 600 μA and is defined as 1X pre-
emphasis current.
11 HS transmitter pre-emphasis circuit sources 3X pre-emphasis current
10 HS transmitter pre-emphasis circuit sources 2X pre-emphasis current
01 HS transmitter pre-emphasis circuit sources 1X preemphasis current
00 HS transmitter pre-emphasis disabled (Default)
17 It drives the value of USB3 TXPREEMPPULSETUNE signal.
TXPREEMPPULSETUNE
HS transmitter pre-emphasis duration control: This signal controls the duration for which the HS
pre-emphasis current is sourced onto D+ or D-. The HS transmitter pre-emphasis duration is
defined in terms of unit amounts. One unit of pre-emphasis duration is approximately 580 ps and
is defined as 1X pre-emphasis duration. This signal is valid only if either
TXPREEMPAMPTUNE[1] or TXPREEMPAMPTUNE[0] is set to 1'b1.
1 1X, short pre-emphasis current duration
0 2X (Default), long pre-emphasis current duration
18–19 It drives the value of USB3 TXRESTUNE signal.
TXRESTUNE
USB source impedance adjustment: This bus adjusts the driver source impedance to compensate
for added series resistance on the USB.
11 Source impedance is decreased by approximately 4 Ω.
10 Source impedance is decreased by approximately 2 Ω.
01 Default
00 Source impedance is increased by approximately 1.5 Ω.
20–21 It drives the value of USB3 TXRISETUNE signal.
TXRISETUNE
HS transmitter rise/fall time adjustment: It adjusts the rise/fall times of the high-speed waveform.
22–25 It drives the value of USB3 TXVREFTUNE signal.
TXVREFTUNE
HS DC voltage level adjustment: It adjusts the high speed DC level voltage.
26–31 It drives the value of USB3 pcs_tx_deemph_3p5db (Tx de-emphasis at 3.5 dB) signal.
PCSTXDEEMPH3P5DB
12.3.8 USB3 Parameter 2 Control Register (SCFG_USB3PRM2CR)
The USB3 parameter 2 control register contains the USB3 parameters signals. This
register is reset on HRESET.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
526 NXP Semiconductors
Chapter 12 Supplemental Configuration Unit
Note that the signals described in the register are described as big endian(0:x) however
the signals in the USB3 interface are little endian(x:0). The connectivity is done in such a
way that bit 0 of the following register field corresponds to bit 0 of the USB3 interface.
Address: 157_0000h base + 8Ch offset = 157_008Ch
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
W
PCSRXLOSMASKVAL PCSTXDEEMPH6DB
Reset 0 0 0 1 0 1 1 1 1 1 0 0 0 0 0 1
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
PCSTXSWINGFULL LOSBIAS TXVBOOSTLVL —
Reset 1 1 1 1 1 1 1 1 0 1 0 0 1 0 0 0
SCFG_USB3PRM2CR field descriptions
Field Description
0–9 It drives the value of USB3 pcs_rx_los_mask_val signal.
PCSRXLOSMASKVAL
Configurable loss-of-signal mask width: It sets the number of reference clock cycles to mask the
incoming LFPS in U3 and U2 states. It masks the incoming LFPS for the number of reference clock
cycles equal to the value of pcs_rx_los_mask_val[9:0]. This control filters out short, non-compliant
LFPS glitches sent by a non-compliant host.
If this bus is set to 10'b0, it disables masking. This bus should be accessible to general configuration
registers for system testing and debug. The value should be defined only in reset. Changing this
value during operation might disrupt normal operation of the link.
10–15 It drives the value of USB3 pcs_tx_deemph_6db signal.
PCSTXDEEMPH6DB
Tx de-emphasis at 6 dB: This bus is provided for completeness and as a second potential launch
amplitude.
16–22 It drives the value of USB3 pcs_tx_swing_full signal.
PCSTXSWINGFULL
Tx amplitude (full swing mode): This static value sets the launch amplitude of the transmitter.
23–25 It drives the value of USB3 los_bias signal.
LOSBIAS
Loss-of-signal detector threshold level control: It sets the LOS detection threshold level.
A positive binary bit setting change results in a +15 mVp incremental change in the LOS threshold. A
negative binary bit setting change results in a –15 mVp incremental change in the LOS threshold.
The 3b'000 setting is reserved and must not be used.
26–28 It drives the value of USB3 tx_vboost_lvl signal.
TXVBOOSTLVL
Tx voltage boost level: It sets the boosted transmit launch amplitude (mVppd).
29–31 Reserved
—
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 527
SCFG Memory Map/Register Definition
12.3.9 USB3 Parameter 3 Control Register (SCFG_USB3PRM3CR)
Note that the signals described in the register are described as big endian(0:x) however
the signals in the USB3 interface are little endian(x:0). The connectivity is done in such a
way that bit 0 of the following register field corresponds to bit 0 of the USB3 interface.
Address: 157_0000h base + 90h offset = 157_0090h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
LPBKENB0
R
USB3ACJT VATESTENB — mPLL_MULT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
—
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCFG_USB3PRM3CR field descriptions
Field Description
0–4 Drives the value of USB3 acjt_level signal
USB3ACJT
5–6 Drives the value of USB3 PHY VATESTENB signal
VATESTENB
7 Drives the value of USB3 PHY LOOPBACKENB0 signal
LPBKENB0
8 Reserved
—
9–15 Drives the value of USB3 mpll_multiplier signal
mPLL_MULT
16–31 Reserved
—
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
528 NXP Semiconductors
Chapter 12 Supplemental Configuration Unit
12.3.10 USB2 ICID Register (SCFG_USB2_ICID)
The USB2 ICID register contains the bits to provide the ICID for USB2. This register is
reset at HRESET.
Address: 157_0000h base + 100h offset = 157_0100h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Lock_Bit
ICID —
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
—
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCFG_USB2_ICID field descriptions
Field Description
0–7 ICID of USB2 controller (ICID input to the SMMU).
ICID
8 1 Register bits are locked. Any write to update ICID or lock field have no effect.
Lock_Bit
0 Register bits are open. Write can be done to ICID and lock field.
9–31 Reserved
—
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 529
SCFG Memory Map/Register Definition
12.3.11 USB3 ICID Register (SCFG_USB3_ICID)
The USB3 ICID register contains the bits to provide the ICID for USB3. This register is
reset at HRESET.
Address: 157_0000h base + 104h offset = 157_0104h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Lock_Bit
ICID —
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
—
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCFG_USB3_ICID field descriptions
Field Description
0–7 ICID of USB3 controller (input to the SMMU).
ICID
8 1 Register bits are locked. Any write to update ICID or lock field have no effect.
Lock_Bit
0 Register bits are open. Write can be done to ICID and lock field.
9–31 Reserved
—
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
530 NXP Semiconductors
Chapter 12 Supplemental Configuration Unit
12.3.12 qDMA ICID Register (SCFG_DMA_ICID)
The qDMA ICID register contains the bits to provide the ICID for qDMA to the SMMU.
This register is reset at HRESET.
Address: 157_0000h base + 114h offset = 157_0114h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Lock_Bit
ICID —
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
—
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCFG_DMA_ICID field descriptions
Field Description
0–7 ICID of qDMA (input to the SMMU).
ICID
8 1 Register bits are locked. Any write to update ICID or lock field have no effect.
Lock_Bit
0 Register bits are open. Write can be done to ICID and lock field.
9–31 Reserved
—
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 531
SCFG Memory Map/Register Definition
12.3.13 SATA ICID Register (SCFG_SATA_ICID)
The SATA ICID register contains the bits to provide the ICID for SATA to the SMMU.
This register is reset at HRESET.
Address: 157_0000h base + 118h offset = 157_0118h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Lock_Bit
ICID —
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
—
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCFG_SATA_ICID field descriptions
Field Description
0–7 ICID of SATA controller (input to the SMMU).
ICID
8 1 Register bits are locked. Any write to update ICID or lock field have no effect.
Lock_Bit
0 Register bits are open. Write can be done to ICID and lock field.
9–31 Reserved
—
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
532 NXP Semiconductors
Chapter 12 Supplemental Configuration Unit
12.3.14 USB1 ICID Register (SCFG_USB1_ICID)
The USB1 ICID register contains the bits to provide the ICID for USB1. This register is
reset at HRESET.
Address: 157_0000h base + 11Ch offset = 157_011Ch
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Lock_Bit
ICID —
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
—
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCFG_USB1_ICID field descriptions
Field Description
0–7 ICID of USB1 controller (input to the SMMU).
ICID
8 1 Register bits are locked. Any write to update ICID or lock field have no effect.
Lock_Bit
0 Register bits are open. Write can be done to ICID and lock field.
Once this bit is set, write access is disabled to ICID[0:7] bit.
9–31 Reserved
—
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 533
SCFG Memory Map/Register Definition
12.3.15 QE ICID Register (SCFG_QE_ICID)
The QE ICID register contains the bits to provide the ICID for QE to the SMMU. This
register is reset at HRESET.
Address: 157_0000h base + 120h offset = 157_0120h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Lock_Bit
ICID —
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
—
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCFG_QE_ICID field descriptions
Field Description
0–7 ICID of QE (input to the SMMU).
ICID
8 1 Register bits are locked. Any write to update ICID or lock field have no effect.
Lock_Bit
0 Register bits are open. Write can be done to ICID and lock field.
Once this bit is set, write access is disabled to ICID[0:7] bit.
9–31 Reserved
—
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
534 NXP Semiconductors
Chapter 12 Supplemental Configuration Unit
12.3.16 eSDHC ICID Register (SCFG_SDHC_ICID)
The eSDHC ICID register contains the bits to provide the ICID for eSDHC to the
SMMU. This register is reset at HRESET.
Address: 157_0000h base + 124h offset = 157_0124h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Lock_Bit
ICID —
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
—
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCFG_SDHC_ICID field descriptions
Field Description
0–7 ICID of eSDHC (input to the SMMU).
ICID
8 1 Register bits are locked. Any write to update ICID or lock field have no effect.
Lock_Bit
0 Register bits are open. Write can be done to ICID and lock field.
Once this bit is set, write access is disabled to ICID[0:7] bit.
9–31 Reserved
—
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 535
SCFG Memory Map/Register Definition
12.3.17 eDMA ICID Register (SCFG_eDMA_ICID)
The eDMA ICID register contains the bits to provide the ICID for eDMA to the SMMU.
This register is reset at HRESET.
Address: 157_0000h base + 128h offset = 157_0128h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Lock_Bit
ICID _
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
_
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCFG_eDMA_ICID field descriptions
Field Description
0–7 ICID of eDMA (input to the SMMU).
ICID
8 1 Register bits are locked. Any write to update ICID or lock field have no effect.
Lock_Bit
0 Register bits are open. Write can be done to ICID and lock field.
Once this bit is set, write access is disabled to ICID[0:7] bit.
9–31 Reserved
_
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
536 NXP Semiconductors
Chapter 12 Supplemental Configuration Unit
12.3.18 ETR ICID Register (SCFG_ETR_ICID)
The ETR ICID register contains the bits to provide the ICID for ETR to the SMMU. This
register is reset at HRESET
Address: 157_0000h base + 12Ch offset = 157_012Ch
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Lock_Bit
ICID —
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
—
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCFG_ETR_ICID field descriptions
Field Description
0–7 ICID of ETR (input to the SMMU).
ICID
8 1 Register bits are locked. Any write to update ICID or lock field have no effect.
Lock_Bit
0 Register bits are open. Write can be done to ICID and lock field.
Once this bit is set, write access is disabled to ICID[0:7] bit.
9–31 Reserved
—
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 537
SCFG Memory Map/Register Definition
12.3.19 Core 0 soft reset Register (SCFG_CORE0_SFT_RST)
The core0 soft reset register contains the bits to provide the soft reset to core0 of A53
complex. This register is reset at HRESET.
Address: 157_0000h base + 130h offset = 157_0130h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
soft_reset
—
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
—
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCFG_CORE0_SFT_RST field descriptions
Field Description
0 Reset process is initiated for core 0 when 1 is written on this bit. The bit is self clearing, and read always
soft_reset get 0.
0 Default
1 Reset core 0 (self-clearing bit)
1–31 Reserved
—
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
538 NXP Semiconductors
Chapter 12 Supplemental Configuration Unit
12.3.20 Core 1 soft reset Register (SCFG_CORE1_SFT_RST)
The core1 soft reset register contains the bits to provide the soft reset to core1 of A53
complex. This register is reset at HRESET.
Address: 157_0000h base + 134h offset = 157_0134h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
soft_reset
—
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
—
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCFG_CORE1_SFT_RST field descriptions
Field Description
0 Reset process is initiated for core 1 when a 1 is written on this bit. The bit is self clearing, and read always
soft_reset get 0.
0 Default
1 Reset core 1 (self-clearing bit)
1–31 Reserved
—
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 539
SCFG Memory Map/Register Definition
12.3.21 Core 2 soft reset Register (SCFG_CORE2_SFT_RST)
The core2 soft reset register contains the bits to provide the soft reset to core2 of A53
complex. This register is reset at HRESET.
Address: 157_0000h base + 138h offset = 157_0138h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
soft_reset
—
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
—
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCFG_CORE2_SFT_RST field descriptions
Field Description
0 Reset process is initiated for core 2 when a 1 is written on this bit. The bit is self clearing, and read always
soft_reset get 0.
0 Default
1 Reset core 2 (self-clearing bit)
1–31 Reserved
—
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
540 NXP Semiconductors
Chapter 12 Supplemental Configuration Unit
12.3.22 Core 3soft reset Register (SCFG_CORE3_SFT_RST)
The core3 soft reset register contains the bits to provide the soft reset to core3 of A53
complex. This register is reset at HRESET.
Address: 157_0000h base + 13Ch offset = 157_013Ch
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
soft_reset
—
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
—
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCFG_CORE3_SFT_RST field descriptions
Field Description
0 Reset process is initiated for core 3 when a 1 is written on this bit. The bit is self clearing, and read always
soft_reset get 0.
0 Default
1 Reset core 3 (self-clearing bit)
1–31 Reserved
—
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 541
SCFG Memory Map/Register Definition
12.3.23 PEX PME control register (SCFG_PEXPMECR)
The PEX PME control register contains the bits to generate PM turnoff message for
power management. This register is reset at HRESET.
Address: 157_0000h base + 144h offset = 157_0144h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PEX1PME
PEX2PME
PEX3PME
R
Reserved Reserved Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCFG_PEXPMECR field descriptions
Field Description
0 Generates PM turnoff message for power management for PCI Express1.
PEX1PME
It should be cleared by software.
0 Default
1 RC mode only
1–3 This field is reserved.
-
4 Generates PM turnoff message for power management for PCI Express2.
PEX2PME
It should be cleared by software.
0 Default
1 RC mode only
5–7 This field is reserved.
-
8 Generates PM turnoff message for power management for PCI Express3.
PEX3PME
It should be cleared by software.
0 Default
1 RC mode only
9–31 This field is reserved.
-
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
542 NXP Semiconductors
Chapter 12 Supplemental Configuration Unit
12.3.24 FTM chain configuration (SCFG_FTM_CHAIN_CONFIG)
This register contains the bits to enable chaining of FlexTimers. This register is reset at
HRESET.
Address: 157_0000h base + 154h offset = 157_0154h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
FTM_CHN1
FTM_CHN2
FTM_CHN3
FTM_CHN4
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCFG_FTM_CHAIN_CONFIG field descriptions
Field Description
0–15 This field is reserved.
- Reserved
16 FTM_CHN1
FTM_CHN1
0 FTM1 and FTM5 are not chained
1 FTM1 and FTM5 are chained
17 FTM_CHN2
FTM_CHN2
0 FTM2 and FTM6 are not chained
1 FTM2 and FTM6 are chained
18 FTM_CHN3
FTM_CHN3
0 FTM3 and FTM7 are not chained
1 FTM3 and FTM7 are chained
19 FTM_CHN4
FTM_CHN4
0 FTM4 and FTM8 are not chained
1 FTM4 and FTM8 are chained
20–31 This field is reserved.
- Reserved
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 543
SCFG Memory Map/Register Definition
12.3.25 ALTCBAR Register (SCFG_ALTCBAR)
The ALTCBAR register contains the bits for alternate configuration base address register
for PBL. This register is reset at HRESET.
Address: 157_0000h base + 158h offset = 157_0158h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
ALTCBAR —
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCFG_ALTCBAR field descriptions
Field Description
0–23 Alt configuration base address register for PBL.
ALTCBAR
24–31 Reserved
—
12.3.26 QSPI CONFIG Register (SCFG_QSPI_CFG)
The QuadSPI configuration register contains the bits for QuadSPI configuration. This
register is reset at HRESET.
Address: 157_0000h base + 15Ch offset = 157_015Ch
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
CLK_SEL Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCFG_QSPI_CFG field descriptions
Field Description
0–3 These bits control the division of CGA1/CGA2 PLL clock to generate QuadSPI interface clocks.
CLK_SEL
0000 Divide by 256
0001 Divide by 64
0010 Divide by 32
0011 Divide by 24
0100 Divide by 20
0101 Divide by 16
0110 Divide by 12
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
544 NXP Semiconductors
Chapter 12 Supplemental Configuration Unit
SCFG_QSPI_CFG field descriptions (continued)
Field Description
0111 Divide by 8
4–31 This field is reserved.
— Reserved
12.3.27 QOS1 Register (SCFG_QOS1)
The QOS1 register contains the bits for QoS inputs to CCI/interconnect fabric. This
register is reset at HRESET. Note that the bits are described as [x:x+3] however are
connected to QOS ports as [3:0]. So, there is a bit reversal involved.
Address: 157_0000h base + 16Ch offset = 157_016Ch
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
eDMA_QoS USB2_QoS USB3_QoS qDMA_QoS PEX2_QoS PEX1_QoS SEC_QoS FM_QoS
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCFG_QOS1 field descriptions
Field Description
0–3 QOS[3:0] for eDMA.
eDMA_QoS
4–7 QOS[3:0] for USB2.
USB2_QoS
8–11 QOS[3:0] for USB3.
USB3_QoS
12–15 QOS[3:0] for qDMA.
qDMA_QoS
16–19 QOS[3:0] for PCI Express2.
PEX2_QoS
20–23 QOS[3:0] for PCI Express1.
PEX1_QoS
24–27 QOS[3:0] for SEC.
SEC_QoS
28–31 QOS[3:0] for FMan.
FM_QoS
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 545
SCFG Memory Map/Register Definition
12.3.28 QOS2 Register (SCFG_QOS2)
The QOS2 register contains the bits for QoS inputs to CCI/interconnect fabric. This
register is reset at HRESET. Note that the bits are described as [x:x+3]however are
connected to QOS ports as [3:0]. So, there is a bit reversal involved.
Address: 157_0000h base + 170h offset = 157_0170h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
USB1_QoS PEX3_QoS QMan_QoS A53_QoS — eSDHC_QoS QE_QoS SATA_QoS
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCFG_QOS2 field descriptions
Field Description
0–3 QOS[3:0] for USB1.
USB1_QoS
4–7 QOS[3:0] for PCI Express3.
PEX3_QoS
8–11 QOS[3:0] for QMan.
QMan_QoS
12–15 QOS[3:0] for A53.
A53_QoS
16–19 Reserved
—
20–23 QOS[3:0] for eSDHC.
eSDHC_QoS
24–27 QOS[3:0] for QE.
QE_QoS
28–31 QOS[3:0] for SATA.
SATA_QoS
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
546 NXP Semiconductors
Chapter 12 Supplemental Configuration Unit
12.3.29 GIC-400 Address 64K Page Alignment Register
(SCFG_GIC400_ADDR_ALIGN_64K)
The GIC-400 address 64 K page alignment register controls the GIC-400 addressing.
This register is reset at PORESET.
Address: 157_0000h base + 188h offset = 157_0188h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
GIC_ADDR
—
W
Reset 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
—
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCFG_GIC400_ADDR_ALIGN_64K field descriptions
Field Description
0 Controls the GIC-400 addressing.
GIC_ADDR
0 The addressing of GIC-400 is 64 K page aligned (Default).
1 The GIC-400 addressing is non-64 K page aligned.
1–31 Reserved
—
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 547
SCFG Memory Map/Register Definition
12.3.30 Debug ICID Register (SCFG_Debug_ICID)
The debug ICID register contains the bits to provide the ICID for the debug components
to the SMMU. This register is reset at HRESET.
Address: 157_0000h base + 18Ch offset = 157_018Ch
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Lock_Bit
ICID —
W
Reset 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
—
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCFG_Debug_ICID field descriptions
Field Description
0–7 ICID input to the SMMU.
ICID
8 1 Register bits are locked. Any write to update ICID or lock field have no effect.
Lock_Bit
0 Register bits are open. Write can be done to ICID and lock field.
9–31 Reserved
—
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
548 NXP Semiconductors
Chapter 12 Supplemental Configuration Unit
12.3.31 Snoop Configuration Register (SCFG_SNPCNFGCR)
The snoop configuration control register contains the bits to drive snoop signal for
various masters. This register is reset at HRESET.
Address: 157_0000h base + 1A4h offset = 157_01A4h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SATAWRSNP
USB1WRSNP
USB2WRSNP
SATARDSNP
USB1RDSNP
DBGWRSNP
SECWRSNP
DBGRDSNP
SECRDSNP
eDMASNP
—
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
USB3WRSNP
USB2RDSNP
USB3RDSNP
—
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCFG_SNPCNFGCR field descriptions
Field Description
0 Drives SEC Read snoop signal.
SECRDSNP
0 SEC reads are not snoopable
1 SEC reads are snoopable
1
SECWRSNP
Controls snoop attribute of SEC writes.
0 SEC writes are not snoopable
1 SEC writes are snoopable
2–7 Reserved
—
8 Drives SATA read snoop signal.
SATARDSNP
0 SATA reads are not snoopable
1 SATA reads are snoopable
9
SATAWRSNP
Controls snoop attribute of SATA writes.
0 SATA writes are not snoopable
1 SATA writes are snoopable
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 549
SCFG Memory Map/Register Definition
SCFG_SNPCNFGCR field descriptions (continued)
Field Description
9 Drives USB1 read snoop signal
USB1RDSNP
0 USB1 reads are not snoopable
1 USB1 reads are snoopable
11
USB1WRSNP
Controls snoop attribute of USB3 writes.
0 USB1 writes are not snoopable
1 USB1 writes are snoopable
12
DBGRDSNP
0 Debug reads are not snoopable
1 Debug reads are snoopable
13 Drives DEBUG (debug and etr port of interconnect fabric) Write Snoop signal.
DBGWRSNP
Controls snoop attribute of Debug writes.
0 Debug writes are not snoopable
1 Debug writes are snoopable
14 Drives eDMA snoop signal. If eDMA is used for SPI, I2C, QuadSPI, FlexTimer, and LPUART then this bit
eDMASNP configures the snooping attribute for all the transactions (R/W) initiated by eDMA on the behalf of these
IPs.
0 eDMA transactions are not snoopable
1 eDMA transactions are snoopable
15 Drives USB2 write snoop signal.
USB2WRSNP
0 USB2 writes are not snoopable
1 USB2 writes are snoopable
16 Drives USB2 read snoop signal.
USB2RDSNP
0 USB2 reads are not snoopable
1 USB2 reads are snoopable
17 Drives USB3 write snoop signal.
USB3WRSNP
0 USB3 writes are not snoopable
1 USB3 writes are snoopable
18 Drives USB3 read snoop signal.
USB3RDSNP
0 USB3 reads are not snoopable
1 USB3 reads are snoopable
19–31 Reserved
—
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
550 NXP Semiconductors
Chapter 12 Supplemental Configuration Unit
12.3.32 Interrupt Polarity Register (SCFG_INTPCR)
The interrupt polarity control register contains the bits to control the polarity of the
IRQ0-11. This register is reset at HRESET.
Address: 157_0000h base + 1ACh offset = 157_01ACh
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
IRQ10INTP
IRQ11INTP
IRQ0INTP
IRQ1INTP
IRQ2INTP
IRQ3INTP
IRQ4INTP
IRQ5INTP
IRQ6INTP
IRQ7INTP
IRQ8INTP
IRQ9INTP
R
—
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
—
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCFG_INTPCR field descriptions
Field Description
0 Controls the polarity of IRQ0
IRQ0INTP
0 IRQ0 is active high
1 IRQ0 is active low
1 Controls the polarity of IRQ1
IRQ1INTP
0 IRQ1 is active high
1 IRQ1 is active low
2 Controls the polarity of IRQ2
IRQ2INTP
0 IRQ2 is active high
1 IRQ2 is active low
3 Controls the polarity of IRQ3
IRQ3INTP
0 IRQ3 is active high
1 IRQ3 is active low
4 Controls the polarity of IRQ4
IRQ4INTP
0 IRQ4 is active high
1 IRQ4 is active low
5 Controls the polarity of IRQ5
IRQ5INTP
0 IRQ5 is active high
1 IRQ5 is active low
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 551
SCFG Memory Map/Register Definition
SCFG_INTPCR field descriptions (continued)
Field Description
6 Controls the polarity of IRQ6
IRQ6INTP
0 IRQ6 is active high
1 IRQ6 is active low
7 Controls the polarity of IRQ7
IRQ7INTP
0 IRQ7 is active high
1 IRQ7 is active low
8 Controls the polarity of IRQ8
IRQ8INTP
0 IRQ8 is active high
1 IRQ8 is active low
9 Controls the polarity of IRQ9
IRQ9INTP
0 IRQ9 is active high
1 IRQ9 is active low
10 Controls the polarity of IRQ10
IRQ10INTP
0 IRQ10 is active high
1 IRQ10 is active low
11 Controls the polarity of IRQ11
IRQ11INTP
0 IRQ11 is active high
1 IRQ11 is active low
12–31 Reserved
—
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
552 NXP Semiconductors
Chapter 12 Supplemental Configuration Unit
12.3.33 CORE Soft Reset Enable Register (SCFG_CORESRENCR)
The core soft reset enable control register contains the bit to enable the core soft reset
functionality. This register is reset at PORESET.
Address: 157_0000h base + 204h offset = 157_0204h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CORESREN
—
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
—
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCFG_CORESRENCR field descriptions
Field Description
0 Controls the enable of core soft reset functionality
CORESREN
0 Core soft-reset is disabled(Default)
1 Core soft-reset is enabled
1–31 Reserved
—
12.3.34 Core 0 Reset Vector Base Address0 (SCFG_RVBAR0_0)
The core 0 reset vector base address0 register controls the reset vector base address for
core 0 for bits [33:2]. This register is reset at PORESET. This register should be
programmed in the PBI phase.
NOTE
After core warm reset, the core can boot from a reset vector
configured in SCFG_RVBAR0_0 (Core 0 Reset Vector Base
Address0) and SCFG_RVBARn_1 (Core 0 Reset Vector Base
Address1).
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 553
SCFG Memory Map/Register Definition
The 40-b address should be programmed in RVBARn_0/
RVBARn_1 register for the entry point of the vector from
where the core executes the first instruction after coming out
from the warm-reset. If it is not configured, its reset value will
be 0x0 and the first instruction will be executed from the
internal boot ROM.
Address: 157_0000h base + 220h offset = 157_0220h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
RVBAR0_0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCFG_RVBAR0_0 field descriptions
Field Description
0–31 Core 0 reset vector base address for bits [33:2].
RVBAR0_0
12.3.35 Core 0 Reset Vector Base Address1 (SCFG_RVBAR0_1)
The core 0 reset vector base address1 register controls the reset vector base address for
core 0 for bits [39:34]. This register is reset at PORESET. This register should be
programmed in the PBI phase.
NOTE
After core warm reset, the core can boot from a reset vector
configured in SCFG_RVBAR0_0 (Core 0 Reset Vector Base
Address0) and SCFG_RVBARn_1 (Core 0 Reset Vector Base
Address1).
The 40-b address should be programmed in RVBARn_0/
RVBARn_1 register for the entry point of the vector from
where the core executes the first instruction after coming out
from the warm-reset. If it is not configured, its reset value will
be 0x0 and the first instruction will be executed from the
internal boot ROM.
Address: 157_0000h base + 224h offset = 157_0224h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
RVBAR0_1 —
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
554 NXP Semiconductors
Chapter 12 Supplemental Configuration Unit
SCFG_RVBAR0_1 field descriptions
Field Description
0–5 Core 0 reset vector base address for bits [39:34].
RVBAR0_1
6–31 Reserved
—
12.3.36 Core 1 Reset Vector Base Address0 (SCFG_RVBAR1_0)
The core 1 reset vector base address0 register controls the reset vector base address for
core 1 for bits [33:2]. This register is reset at PORESET. This register should be
programmed in the PBI phase.
Address: 157_0000h base + 228h offset = 157_0228h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
RVBAR1_0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCFG_RVBAR1_0 field descriptions
Field Description
0–31 Core 1 reset vector base address for bits [33:2].
RVBAR1_0
12.3.37 Core 1 Reset Vector Base Address1 (SCFG_RVBAR1_1)
The RVBAR1_1 register controls the reset vector base address for core 1 for bits [39:34].
This register is reset at PORESET. This register should be programmed in the PBI phase.
Address: 157_0000h base + 22Ch offset = 157_022Ch
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
RVBAR1_1 —
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCFG_RVBAR1_1 field descriptions
Field Description
0–5 Core 1 reset vector base address for bits [39:34].
RVBAR1_1
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 555
SCFG Memory Map/Register Definition
SCFG_RVBAR1_1 field descriptions (continued)
Field Description
6–31 Reserved
—
12.3.38 Core 2 Reset Vector Base Address0 (SCFG_RVBAR2_0)
The core 2 reset vector base address0 register controls the reset vector base address for
core 0 for bits [33:2]. This register is reset at PORESET. This register should be
programmed in the PBI phase.
Address: 157_0000h base + 230h offset = 157_0230h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
RVBAR2_0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCFG_RVBAR2_0 field descriptions
Field Description
0–31 Core 2 reset vector base address for bits [33:2].
RVBAR2_0
12.3.39 Core 2 Reset Vector Base Address1 (SCFG_RVBAR2_1)
The core 2 reset vector base address1 register controls the reset vector base address for
core 2 for bits [39:34]. This register is reset at PORESET. This register should be
programmed in the PBI phase.
Address: 157_0000h base + 234h offset = 157_0234h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
RVBAR2_1 —
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCFG_RVBAR2_1 field descriptions
Field Description
0–5 Core 2 reset vector base address for bits [39:34].
RVBAR2_1
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
556 NXP Semiconductors
Chapter 12 Supplemental Configuration Unit
SCFG_RVBAR2_1 field descriptions (continued)
Field Description
6–31 Reserved
—
12.3.40 Core 3 Reset Vector Base Address0 (SCFG_RVBAR3_0)
The core 3 reset vector base address0 controls the reset vector base address for core 3 for
bits [33:2]. This register is reset at PORESET. This register should be programmed in the
PBI phase.
Address: 157_0000h base + 238h offset = 157_0238h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
RVBAR3_0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCFG_RVBAR3_0 field descriptions
Field Description
0–31 Core 3 reset vector base address for bits [33:2].
RVBAR3_0
12.3.41 Core 3 Reset Vector Base Address1 (SCFG_RVBAR3_1)
The core 3 reset vector base address1 register controls the reset vector base address for
core 3 for bits [39:34]. This register is reset at PORESET. This register should be
programmed in the PBI phase.
Address: 157_0000h base + 23Ch offset = 157_023Ch
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
RVBAR3_1 —
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCFG_RVBAR3_1 field descriptions
Field Description
0–5 Core 3 reset vector base address for bits [39:34].
RVBAR3_1
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 557
SCFG Memory Map/Register Definition
SCFG_RVBAR3_1 field descriptions (continued)
Field Description
6–31 Reserved
—
12.3.42 Core Low Power Mode Control Status Register
(SCFG_LPMCSR)
The LPMCSR register provides status and control bits for various signals on A53. This
register is reset at PORESET.
Address: 157_0000h base + 240h offset = 157_0240h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CPUQACCEPTn
CPUQACCEPTn
CPUQACTIVE3
CPUQACTIVE2
CPUQDENY3
CPUQDENY2
CPUQREQn3
CPUQREQn2
R
SMPEN3
SMPEN2
— —
3
2
W
Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
CPUQACCEPTn
CPUQACCEPTn
CPUQACTIVE1
CPUQACTIVE0
CPUQDENY1
CPUQDENY0
CPUQREQn1
CPUQREQn0
R
SMPEN1
SMPEN0
— —
1
0
W
Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1
SCFG_LPMCSR field descriptions
Field Description
0–2 Reserved
—
3 Status bit for SMPEN signal of core 3.
SMPEN3
4 Status bit for CPUQDENY signal for core 3.
CPUQDENY3
5 Status bit for CPUQACCEPTn signal for core 3.
CPUQACCEPTn3
6 Status bit for CPUQACTIVE signal for core 3.
CPUQACTIVE3
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
558 NXP Semiconductors
Chapter 12 Supplemental Configuration Unit
SCFG_LPMCSR field descriptions (continued)
Field Description
7 Control bit for CPUQREQn for core 3.
CPUQREQn3
8–10 Reserved
—
11 Status bit for SMPEN signal of core 2.
SMPEN2
12 Status bit for CPUQDENY signal for core 2.
CPUQDENY2
13 Status bit for CPUQACCEPTn signal for core 2.
CPUQACCEPTn2
14 Status bit for CPUQACTIVE signal for core 2.
CPUQACTIVE2
15 Control bit for CPUQREQn for core 2.
CPUQREQn2
16–18 Reserved
—
19 Status bit for SMPEN signal of core 1.
SMPEN1
20 Status bit for CPUQDENY signal for core 1.
CPUQDENY1
21 Status bit for CPUQACCEPTn signal for core 1.
CPUQACCEPTn1
22 Status bit for CPUQACTIVE signal for core 1.
CPUQACTIVE1
23 Control bit for CPUQREQn for core 1.
CPUQREQn1
24–26 Reserved
—
27 Status bit for SMPEN signal of core 0.
SMPEN0
28 Status bit for CPUQDENY signal for core 0.
CPUQDENY0
29 Status bit for CPUQACCEPTn signal for core 0.
CPUQACCEPTn0
30 Status bit for CPUQACTIVE signal for core 0.
CPUQACTIVE0
31 Control bit for CPUQREQn for core 0.
CPUQREQn0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 559
SCFG Memory Map/Register Definition
12.3.43 ECGTX Clock Mux Control Register (SCFG_ECGTXCMCR)
The ECGTX clock mux control register contains the bits to support FMan clock
multiplexing. This register is reset on PORESET.
Address: 157_0000h base + 404h offset = 157_0404h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R CLK_SEL
— —
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
—
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCFG_ECGTXCMCR field descriptions
Field Description
0–3 Reserved
—
4 Selects 125MHz reference clock for RGMII.
CLK_SEL
0 EC1_GTX_CLK125 is used as clock source
1 EC2_GTX_CLK125 is used as clock source
5–31 Reserved
—
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
560 NXP Semiconductors
Chapter 12 Supplemental Configuration Unit
12.3.44 SDHC IO VSEL Control Register (SCFG_SDHCIOVSELCR)
The SDHC IO VSEL control register contains the bits to support SDHC IO voltage
switching. This register is reset on HRESET.
Address: 157_0000h base + 408h offset = 157_0408h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
TGLEN
VSELVAL —
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SDHC_VS
R
—
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCFG_SDHCIOVSELCR field descriptions
Field Description
0 SDHC IO voltage switching enable
TGLEN
0 Voltage switching not enabled (default)
1 Voltage switching enabled.
1–2 Configures voltage for SDHC ( if enabled by TGLEN)
VSELVAL
0b00 - 1.8V
0b01 - Reserved
0b10 - 3.3V
0b11 - Auto-voltage-selection enabled
3–30 Reserved
—
31 SCFG bit reflecting shadow bit controlled by switch for SDHC:VOLT_SEL
SDHC_VS
0 Change the SD bus supply voltage to high voltage range, 3.3V
1 Change the SD bus supply voltage to low voltage range, 1.8V
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 561
SCFG Memory Map/Register Definition
12.3.45 Extended RCW PinMux Control Register
(SCFG_RCWPMUXCR0)
The extended RCW controlled pinmux register contains the bits to provide bits for pin
multiplexing control. This register is reset on HRESET.
Address: 157_0000h base + 40Ch offset = 157_040Ch
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
W
—
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
— IIC3_SCL — IIC3_SDA — IIC4_SCL — IIC4_SDA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCFG_RCWPMUXCR0 field descriptions
Field Description
0–16 Reserved
—
17–19 Configures functionality of the IIC3_SCL.
IIC3_SCL
Options:
000 IIC3_SCL
001 GPIO_4[10]
010 EVT_B[5]
011 USB2_DRVVBUS
100 BRGO4
101 FTM8_CH0
110 CLK11
111 Reserved
20 Reserved
—
21–23 Configures functionality of the IIC3_SDA
IIC3_SDA
Options:
000 IIC3_SDA
001 GPIO_4[11]
010 EVT_B[6]
011 USB2_PWRFAULT
100 BRGO1
101 FTM8_CH1
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
562 NXP Semiconductors
Chapter 12 Supplemental Configuration Unit
SCFG_RCWPMUXCR0 field descriptions (continued)
Field Description
110 CLK12_CLK8 (2 pins of QE are connected)
111 Reserved
24 Reserved
—
25–27 Configures functionality of the IIC4_SCL
IIC4_SCL
000 IIC4_SCL
001 GPIO_4[12]
010 EVT_B[7]
011 USB3_DRVVBUS
100 TDMA_RQ
101 FTM3_FAULT
110 UC1_CDB_RXER
111 Reserved
Refer USB DRVVBUS Select Register (USB_DRVVBUS_SELCR) for USB3_DRV_VBUS to USB
controller mapping.
28 Reserved
—
29–31 Configures functionality of the IIC4_SCL
IIC4_SDA
Options:
000 IIC4_SDA
001 GPIO_4[13]
010 EVT_B[8]
011 USB3_PWRFAULT
100 TDMB_RQ
101 FTM3_EXTCLK
110 UC3_CDB_RXER
111 IIC4_SDA
Refer USB PWRFAULT Select Register (USB_PWRFAULT_SELCR) for USB3_PWRFAULT to USB
controller mapping.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 563
SCFG Memory Map/Register Definition
12.3.46 USB DRVVBUS Control Register
(SCFG_USBDRVVBUS_SELCR)
The USB DRVVBUS select register contains the bits to provide control the USB which
drives USBn_DRVVBUS.This register is reset on HRESET.
Address: 157_0000h base + 410h offset = 157_0410h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
USB_
—
W SEL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCFG_USBDRVVBUS_SELCR field descriptions
Field Description
0–29 Reserved
—
30–31 Selection of USB Controller to drive USB_DRVVBUS I/O
USB_SEL
Options:
00 USB_DRVVBUS I/O driven by USB Controller 1
01 USB_DRVVBUS I/O driven by USB Controller 2
10 Reserved
11 USB_DRVVBUS I/O driven by USB Controller 3
12.3.47 USB PWRFAULTControl Register
(SCFG_USBPWRFAULT_SELCR)
The USB PWRFAULT select register defines how USB_PWR_FAULT is sampled by all
three controllers. This register is reset on HRESET.
Address: 157_0000h base + 414h offset = 157_0414h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
W
—
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
— USB3_SEL USB2_SEL USB1_SEL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
564 NXP Semiconductors
Chapter 12 Supplemental Configuration Unit
SCFG_USBPWRFAULT_SELCR field descriptions
Field Description
0–25 Reserved
—
26–27 USB controller 3 connectivity
USB3_SEL
Option(s):
00 USB controller 3 has its PWRFAULT input tied inactive (no fault)
01 USB controller 3 receives PWRFAULT from shared USB_PWRFAULT I/O.
10 USB controller 3 receives PWRFAULT from dedicated USB3_PWRFAULT I/O
11 Reserved
28–29 USB controller 2 connectivity
USB2_SEL
Option(s):
00 USB controller 2 has its PWRFAULT input tied inactive (no fault)
01 USB controller 2 receives PWRFAULT from shared USB_PWRFAULT I/O.
10 USB controller 2 receives PWRFAULT from dedicated USB2_PWRFAULT I/O
11 Reserved
30–31 USB Controller 1 connectivity
USB1_SEL
Option(s):
00 USB controller 1 has its PWRFAULT input tied inactive (no fault)
01 USB controller 1 receives PWRFAULT from shared USB_PWRFAULT I/O.
10 Reserved
11 Reserved
12.3.48 USB PHY1 Reference Clock Select Register
(SCFG_USB_REFCLK_SELCR1)
The USB PHY1 reference clock select register contains bits to select the reference clock
for USB PHY1. This register is reset on HRESET.
Address: 157_0000h base + 418h offset = 157_0418h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
W
RST —
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
— FSEL CKSEL
Reset 0 0 0 0 0 0 0 0 1 0 0 1 1 1 1 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 565
SCFG Memory Map/Register Definition
SCFG_USB_REFCLK_SELCR1 field descriptions
Field Description
0 Active high reset.
RST
0 Reset is de-asserted
1 Reset is asserted
1–23 Reserved
—
24–29 Controls USB PHY PLL reference clock frequency.
FSEL
Recommended value is 5'b100111 that corresponds to 100 MHz.
30–31 Selects the reference clock for USB PHY 1 PLL.
CKSEL
00 SYSCLK
10 DIFF_SYSCLK/DIFF_SYSCLK_B
12.3.49 USB PHY2 Reference Clock Select Register
(SCFG_USB_REFCLK_SELCR2)
The The USB PHY2 reference clock select register contains bits to select the reference
clock for USB PHY2. This register is reset on HRESET.
Address: 157_0000h base + 41Ch offset = 157_041Ch
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
W
RST —
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
— FSEL CKSEL
Reset 0 0 0 0 0 0 0 0 1 0 0 1 1 1 1 0
SCFG_USB_REFCLK_SELCR2 field descriptions
Field Description
0 Active high reset.
RST
0 Reset is de-asserted
1 Reset is asserted
1–23 Reserved
—
24–29 Controls USB PHY PLL reference clock frequency.
FSEL
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
566 NXP Semiconductors
Chapter 12 Supplemental Configuration Unit
SCFG_USB_REFCLK_SELCR2 field descriptions (continued)
Field Description
Recommended value is 5'b100111 that corresponds to 100 MHz.
30–31 Selects the reference clock for USB PHY 2 PLL
CKSEL
00 SYSCLK
10 DIFF_SYSCLK/DIFF_SYSCLK_B
12.3.50 USB PHY3 Reference Clock Select Register
(SCFG_USB_REFCLK_SELCR3)
The USB PHY3 reference clock select register contains bits to select the reference clock
for USB PHY3. This register is reset on HRESET.
Address: 157_0000h base + 420h offset = 157_0420h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
W
RST —
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
— FSEL CKSEL
Reset 0 0 0 0 0 0 0 0 1 0 0 1 1 1 1 0
SCFG_USB_REFCLK_SELCR3 field descriptions
Field Description
0 Active high reset.
RST
0 Reset is de-asserted
1 Reset is asserted
1–23 Reserved
—
24–29 Controls USB PHY PLL reference clock frequency.
FSEL
Recommended value is 5'b100111 that corresponds to 100 MHz.
30–31 Selects the reference clock for USB PHY 3 PLL
CKSEL
00 SYSCLK
10 DIFF_SYSCLK/DIFF_SYSCLK_B
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 567
SCFG Memory Map/Register Definition
12.3.51 Retention Request Control Register (SCFG_RETREQCR)
The RETREQCR register contain the bits to enable retention request. This register is
reset on HRESET.
Address: 157_0000h base + 424h offset = 157_0424h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
RETREQ0
RETREQ1
RETREQ2
RETREQ3
—
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
—
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCFG_RETREQCR field descriptions
Field Description
0 Retention request enable 0.
RETREQ0
1 Retention request enable 1.
RETREQ1
2 Retention request enable 2.
RETREQ2
3 Retention request enable 3.
RETREQ3
4–31 Reserved
—
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
568 NXP Semiconductors
Chapter 12 Supplemental Configuration Unit
12.3.52 CORE PM Control Register (SCFG_COREPMCR)
The COREPMCR register contains control bit to enable WFIL2. This register is reset on
HRESET.
Address: 157_0000h base + 42Ch offset = 157_042Ch
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
—
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
WFIL2EN
—
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCFG_COREPMCR field descriptions
Field Description
0–30 Reserved
—
31 WFIL2 Enable for core A53.
WFIL2EN
12.3.53 SCRATCHRWn - Scratch Read Write Registers
(SCFG_SCRATCHRWn)
The SCRATCHn read write register n(n=1 to 4), provides read/write scratch register
locations available to the user. It provides expansion bits for device control. This register
is reset on HRESET.
Note that the SCRATCHRW1 and SCRATCHR2 registers are used for non-secure boot
whereas SCRATCHRW3 and SCRACTHRW4 registers are defined for secure-boot.
When performing non-secure boot, these registers are defined as follows:
SCRATCHRW1 - Reserved for future use in case boot location pointer is 64 bit. The
value must be 0.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 569
SCFG Memory Map/Register Definition
SCRATCHRW2 - 32-bit boot location pointer (BOOTLOCPTR)
When performing secure boot, these registers are defined as follows:
SCRATCHRW3 - Register that indicate failures in SEC self tests (if any) conducted as
part of secure boot flow
SCRATCHRW4- Register to control setting of ClientPD in SMMU at IBR exit.
• SFP_OSPR(ITS) = 1, Register is don’t care and ClientPD bit is always left set as 0
• SFP_OSPR(ITS)ITS = 0, SB_EN = 1
• SCRATCHRW4 = 0 (default), ClientPD is left set as 0
• SCRATCHRW4 = non-zero, ClientPD is reset to 1 (by-pass mode)
Address: 157_0000h base + 600h offset + (4d × i), where i=0d to 3d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
VAL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCFG_SCRATCHRWn field descriptions
Field Description
0–31 32-bit scratch contents
VAL
12.3.54 Core Boot Control Register (SCFG_COREBCR)
The COREBCR register provides expansion bits for device control. This register is reset
on HRESET. The bits get set on assertion of core reset.
Address: 157_0000h base + 680h offset = 157_0680h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
—
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
CORE3
CORE2
CORE1
CORE0
—
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
570 NXP Semiconductors
Chapter 12 Supplemental Configuration Unit
SCFG_COREBCR field descriptions
Field Description
0–27 Reserved
—
28 Write 1 to clear bit for core 3. Also set with core 3 reset.
CORE3
29 Write 1 to clear bit for core 2.Also set with core 2 reset
CORE2
30 Write 1 to clear bit for core 1. Also set with core 1 reset.
CORE1
31 Write 1 to clear bit for core 0. Also set with core 0 reset.
CORE0
12.3.55 Shared Message Signaled Interrupt Index Register
(SCFG_G0MSIIR)
The group 0 (G0) shared message signaled interrupt index register provides the
mechanism for setting an interrupt in the MSIR. When MSIIR is written, MSIIR[IBS]
selects the shared interrupt field in the selected MSIR register. MSIIR is primarily
intended to support PCI express MSIs.
This register can be written by any of the PCI Express Endpoint device.
Address: 157_0000h base + 1000h offset = 157_1000h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
— IBS SRS —
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCFG_G0MSIIR field descriptions
Field Description
0–2 Reserved
—
3–5 Interrupt bit selects the bit of the chosen logical section to be set in the GnMSIRx.
IBS
MSIR1
000 Set field SH0 (bit 0)
001 Set field SH1 (bit 1)
010 Set field SH2 (bit 2)
011 Set field SH3 (bit 3)
100 Set field SH4 (bit 4)
101 Set field SH5 (bit 5)
110 Set field SH6 (bit 6)
111 Set field SH7 (bit 7)
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 571
SCFG Memory Map/Register Definition
SCFG_G0MSIIR field descriptions (continued)
Field Description
MSIR2
000 Set field SH8 (bit 8)
001 Set field SH9 (bit 9)
010 Set field SH10 (bit 10)
011 Set field SH11 (bit 11)
100 Set field SH12 (bit 12)
101 Set field SH13 (bit 13)
110 Set field SH14 (bit 114)
111 Set field SH15 (bit 15)
MSIR3
000 Set field SH16 (bit 16)
001 Set field SH17 (bit 17)
010 Set field SH18 (bit 18)
011 Set field SH19 (bit 19)
100 Set field SH20 (bit 20)
101 Set field SH21 (bit 21)
110 Set field SH22 (bit 22)
111 Set field SH23 (bit 23)
MSIR4
000 Set field SH24 (bit 24)
001 Set field SH25 (bit 25)
010 Set field SH26 (bit 26)
011 Set field SH27 (bit 27)
100 Set field SH28 (bit 28)
101 Set field SH29 (bit 29)
110 Set field SH30 (bit 30)
111 Set field SH31 (bit 31)
6–7 Shared interrupt register select. Selects the MSIR to be written.
SRS
00 MSIR 1
01 MSIR 2
01 MSIR 3
11 MSIR 4
8–31 Reserved
—
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
572 NXP Semiconductors
Chapter 12 Supplemental Configuration Unit
12.3.56 Shared Message Signaled Interrupt Register
(SCFG_G0MSIR1)
The group 0 shared message signaled interrupt register indicates which of the up to 8
interrupt sources sharing a message register have pending interrupts. This register is
cleared when read; write to the register has no effect.
Address: 157_0000h base + 1010h offset = 157_1010h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
SHn —
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCFG_G0MSIR1 field descriptions
Field Description
0–7 Message sharer n has a pending interrupt.
SHn
8–31 Reserved
—
12.3.57 Shared Message Signaled Interrupt Register
(SCFG_G0MSIR2)
The group 0(G0) shared message signaled interrupt register indicates which of the up to 8
interrupt sources sharing a message register have pending interrupts. This register is
cleared when read; write to the register has no effect.
Address: 157_0000h base + 1014h offset = 157_1014h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
— SHn —
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCFG_G0MSIR2 field descriptions
Field Description
0–7 Reserved
—
8–15 Message sharer n has a pending interrupt.
SHn
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 573
SCFG Memory Map/Register Definition
SCFG_G0MSIR2 field descriptions (continued)
Field Description
16–31 Reserved
—
12.3.58 Shared Message Signaled Interrupt Register
(SCFG_G0MSIR3)
The group 0(G0) shared message signaled interrupt register indicates which of the up to 8
interrupt sources sharing a message register have pending interrupts. This register is
cleared when read; write to the register has no effect.
Address: 157_0000h base + 1018h offset = 157_1018h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
— SHn —
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCFG_G0MSIR3 field descriptions
Field Description
0–15 Reserved
—
16–23 Message sharer n has a pending interrupt.
SHn
24–31 Reserved
—
12.3.59 Shared Message Signaled Interrupt Register
(SCFG_G0MSIR4)
The group 0(G0) shared message signaled interrupt register indicates which of the up to 8
interrupt sources sharing a message register have pending interrupts. This register is
cleared when read; write to the register has no effect.
Address: 157_0000h base + 101Ch offset = 157_101Ch
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
— SHn
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
574 NXP Semiconductors
Chapter 12 Supplemental Configuration Unit
SCFG_G0MSIR4 field descriptions
Field Description
0–23 Reserved
—
24–31 Message sharer n has a pending interrupt.
SHn
12.3.60 Shared Message Signaled Interrupt Index Register
(SCFG_G1MSIIR)
The G1 shared message signaled interrupt index register provides the mechanism for
setting an interrupt in the MSIR. When MSIIR is written, MSIIR[IBS] selects the shared
interrupt field in the selected MSIR register. This register is primarily intended to support
PCI Express MSIs.
This register can be written by any of the PCI Express Endpoint device.
Address: 157_0000h base + 2000h offset = 157_2000h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
— IBS SRS —
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCFG_G1MSIIR field descriptions
Field Description
0–2 Reserved
—
3–5 Interrupt bit selects the bit of the chosen logical section to be set in the GnMSIRx.
IBS
MSIR1
000 Set field SH0 (bit 0)
001 Set field SH1 (bit 1)
010 Set field SH2 (bit 2)
011 Set field SH3 (bit 3)
100 Set field SH4 (bit 4)
101 Set field SH5 (bit 5)
110 Set field SH6 (bit 6)
111 Set field SH7 (bit 7)
MSIR2
000 Set field SH8 (bit 8)
001 Set field SH9 (bit 9)
010 Set field SH10 (bit 10)
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 575
SCFG Memory Map/Register Definition
SCFG_G1MSIIR field descriptions (continued)
Field Description
011 Set field SH11 (bit 11)
100 Set field SH12 (bit 12)
101 Set field SH13 (bit 13)
110 Set field SH14 (bit 114)
111 Set field SH15 (bit 15)
MSIR3
000 Set field SH16 (bit 16)
001 Set field SH17 (bit 17)
010 Set field SH18 (bit 18)
011 Set field SH19 (bit 19)
100 Set field SH20 (bit 20)
101 Set field SH21 (bit 21)
110 Set field SH22 (bit 22)
111 Set field SH23 (bit 23)
MSIR4
000 Set field SH24 (bit 24)
001 Set field SH25 (bit 25)
010 Set field SH26 (bit 26)
011 Set field SH27 (bit 27)
100 Set field SH28 (bit 28)
101 Set field SH29 (bit 29)
110 Set field SH30 (bit 30)
111 Set field SH31 (bit 31)
6–7 Shared interrupt register select. Selects the MSIR to be written.
SRS
00 MSIR 1
01 MSIR 2
01 MSIR 3
11 MSIR 4
8–31 Reserved
—
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
576 NXP Semiconductors
Chapter 12 Supplemental Configuration Unit
12.3.61 Shared Message Signaled Interrupt Register
(SCFG_G1MSIR1)
The group 1 shared message signaled interrupt register indicates which of the up to 8
interrupt sources sharing a message register have pending interrupts. This register is
cleared when read; write to the register has no effect.
Address: 157_0000h base + 2010h offset = 157_2010h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
SHn —
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCFG_G1MSIR1 field descriptions
Field Description
0–7 Message sharer n has a pending interrupt.
SHn
8–31 Reserved
—
12.3.62 Shared Message Signaled Interrupt Register
(SCFG_G1MSIR2)
The group 1 shared message signaled interrupt register indicates which of the up to 8
interrupt sources sharing a message register have pending interrupts. This register is
cleared when read; write to the register has no effect.
Address: 157_0000h base + 2014h offset = 157_2014h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
— SHn —
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCFG_G1MSIR2 field descriptions
Field Description
0–7 Reserved
—
8–15 Message sharer n has a pending interrupt.
SHn
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 577
SCFG Memory Map/Register Definition
SCFG_G1MSIR2 field descriptions (continued)
Field Description
16–31 Reserved
—
12.3.63 Shared Message Signaled Interrupt Register
(SCFG_G1MSIR3)
The group 1 shared message signaled interrupt register indicates which of the up to 8
interrupt sources sharing a message register have pending interrupts. This register is
cleared when read; write to the register has no effect.
Address: 157_0000h base + 2018h offset = 157_2018h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
— SHn —
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCFG_G1MSIR3 field descriptions
Field Description
0–15 Reserved
—
16–23 Message sharer n has a pending interrupt.
SHn
24–31 Reserved
—
12.3.64 Shared Message Signaled Interrupt Register
(SCFG_G1MSIR4)
The group 1 shared message signaled interrupt register indicates which of the up to 8
interrupt sources sharing a message register have pending interrupts. This register is
cleared when read; write to the register has no effect.
Address: 157_0000h base + 201Ch offset = 157_201Ch
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
— SHn
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
578 NXP Semiconductors
Chapter 12 Supplemental Configuration Unit
SCFG_G1MSIR4 field descriptions
Field Description
0–23 Reserved
—
24–31 Message sharer n has a pending interrupt.
SHn
12.3.65 Shared Message Signaled Interrupt Index Register
(SCFG_G2MSIIR)
The G2 shared message signaled interrupt index register provides the mechanism for
setting an interrupt in the MSIR. When MSIIR is written, MSIIR[IBS] selects the shared
interrupt field in the selected MSIR register. MSIIR is primarily intended to support PCI
Express MSIs.
This register can be written by any of the PCI Express Endpoint device.
Address: 157_0000h base + 3000h offset = 157_3000h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
— IBS SRS —
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCFG_G2MSIIR field descriptions
Field Description
0–2 Reserved
—
3–5 Interrupt bit selects the bit of the chosen logical section to be set in the GnMSIRx.
IBS
MSIR1
000 Set field SH0 (bit 0)
001 Set field SH1 (bit 1)
010 Set field SH2 (bit 2)
011 Set field SH3 (bit 3)
100 Set field SH4 (bit 4)
101 Set field SH5 (bit 5)
110 Set field SH6 (bit 6)
111 Set field SH7 (bit 7)
MSIR2
000 Set field SH8 (bit 8)
001 Set field SH9 (bit 9)
010 Set field SH10 (bit 10)
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 579
SCFG Memory Map/Register Definition
SCFG_G2MSIIR field descriptions (continued)
Field Description
011 Set field SH11 (bit 11)
100 Set field SH12 (bit 12)
101 Set field SH13 (bit 13)
110 Set field SH14 (bit 114)
111 Set field SH15 (bit 15)
MSIR3
000 Set field SH16 (bit 16)
001 Set field SH17 (bit 17)
010 Set field SH18 (bit 18)
011 Set field SH19 (bit 19)
100 Set field SH20 (bit 20)
101 Set field SH21 (bit 21)
110 Set field SH22 (bit 22)
111 Set field SH23 (bit 23)
MSIR4
000 Set field SH24 (bit 24)
001 Set field SH25 (bit 25)
010 Set field SH26 (bit 26)
011 Set field SH27 (bit 27)
100 Set field SH28 (bit 28)
101 Set field SH29 (bit 29)
110 Set field SH30 (bit 30)
111 Set field SH31 (bit 31)
6–7 Shared interrupt register select. Selects the MSIR to be written.
SRS
00 MSIR 1
01 MSIR 2
01 MSIR 3
11 MSIR 4
8–31 Reserved
—
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
580 NXP Semiconductors
Chapter 12 Supplemental Configuration Unit
12.3.66 Shared Message Signaled Interrupt Register
(SCFG_G2MSIR1)
The group 2 shared message signaled interrupt register indicates which of the up to 8
interrupt sources sharing a message register have pending interrupts. This register is
cleared when read; write to the register has no effect.
Address: 157_0000h base + 3010h offset = 157_3010h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
SHn —
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCFG_G2MSIR1 field descriptions
Field Description
0–7 Message sharer n has a pending interrupt.
SHn
8–31 Reserved
—
12.3.67 Shared Message Signaled Interrupt Register
(SCFG_G2MSIR2)
The group 2 shared message signaled interrupt register indicates which of the up to 8
interrupt sources sharing a message register have pending interrupts. This register is
cleared when read; write to the register has no effect.
Address: 157_0000h base + 3014h offset = 157_3014h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
— SHn —
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCFG_G2MSIR2 field descriptions
Field Description
0–7 Reserved
—
8–15 Message sharer n has a pending interrupt.
SHn
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 581
SCFG Memory Map/Register Definition
SCFG_G2MSIR2 field descriptions (continued)
Field Description
16–31 Reserved
—
12.3.68 Shared Message Signaled Interrupt Register
(SCFG_G2MSIR3)
The group 2 shared message signaled interrupt register indicates which of the up to 8
interrupt sources sharing a message register have pending interrupts. This register is
cleared when read; write to the register has no effect.
Address: 157_0000h base + 3018h offset = 157_3018h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
— SHn —
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCFG_G2MSIR3 field descriptions
Field Description
0–15 Reserved
—
16–23 Message sharer n has a pending interrupt.
SHn
24–31 Reserved
—
12.3.69 Shared Message Signaled Interrupt Register
(SCFG_G2MSIR4)
The group 2 shared message signaled interrupt register indicates which of the up to 8
interrupt sources sharing a message register have pending interrupts. This register is
cleared when read; write to the register has no effect.
Address: 157_0000h base + 301Ch offset = 157_301Ch
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
— SHn
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
582 NXP Semiconductors
Chapter 12 Supplemental Configuration Unit
SCFG_G2MSIR4 field descriptions
Field Description
0–23 Reserved
—
24–31 Message sharer n has a pending interrupt.
SHn
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 583
SCFG Memory Map/Register Definition
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
584 NXP Semiconductors
Chapter 13
Device Configuration and Pin Control
13.1 Device Configuration and Pin Control Introduction
This chapter describes the device configuration and pin control facilities of the chip.
The device configuration unit provides general purpose configuration and status for the
device and the pin control block implements general purpose configuration and status
registers for the device, and the logic to configure the I/O pads to operate according to the
requirements of the functional components. It also controls the data path between the SoC
components and the I/O pads. The pin control block consists of the pins control module,
the functional I/O multiplexing, and the JTAG boundary scan logic.
13.2 Features
The device configuration unit features the following:
• Pin sampling of device configuration pins at power-on reset and a corresponding
POR status register for capturing the values of these configuration pins
• Reset Configuration Word (RCW) support via a set of RCW status registers written
by the Preboot Loader (PBL) during power-on or hard reset in the PBL's RCW stage
• Boot release registers(s) used for releasing cores for booting
• Register file for the Reset module including:
• Register for initiating a device RESET_REQ_B through software
• Set of registers for control and status of sources on the device which can drive
the device's RESET_REQ_B pin
• Core and device disable registers used for gating off clocks for any IP blocks or cores
which are not used at all by an application
• Two small sets of scratch registers:
• One set of read / write scratch registers
• One set of write-once / read scratch registers
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 585
Device Configuration/Pin Control Memory Map
13.3 Device Configuration/Pin Control Memory Map
The table below shows the memory-mapped CCSR registers of the Device Config
module and lists the offset, name, and a cross-reference to the complete description of
each register. These registers only support 32-bit accesses.
DCFG_CCSR memory map
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
1EE_0000 POR Status Register 1 (DCFG_CCSR_PORSR1) 32 R See section 13.3.1/592
1EE_0004 POR Status Register 2 (DCFG_CCSR_PORSR2) 32 R See section 13.3.2/593
General-Purpose POR Configuration Register
1EE_0020 32 R See section 13.3.3/595
(DCFG_CCSR_GPPORCR1)
1EE_0070 Device Disable Register 1 (DCFG_CCSR_DEVDISR1) 32 R/W 0000_0000h 13.3.4/595
1EE_0074 Device Disable Register 2 (DCFG_CCSR_DEVDISR2) 32 R/W 0000_0000h 13.3.5/597
1EE_0078 Device Disable Register 3 (DCFG_CCSR_DEVDISR3) 32 R/W 0000_0000h 13.3.6/599
1EE_007C Device Disable Register 4 (DCFG_CCSR_DEVDISR4) 32 R/W 0000_0000h 13.3.7/600
1EE_0080 Device Disable Register 5 (DCFG_CCSR_DEVDISR5) 32 R/W 0000_0000h 13.3.8/601
1EE_0094 Core Disable Register (DCFG_CCSR_COREDISR) 32 R/W 0000_0000h 13.3.9/604
13.3.10/
1EE_00A4 System Version Register (DCFG_CCSR_SVR) 32 R See section
606
13.3.11/
1EE_00B0 Reset Control Register (DCFG_CCSR_RSTCR) 32 R/W 0000_0000h
607
Reset Request Preboot Loader Status Register 13.3.12/
1EE_00B4 32 w1c 0000_0000h
(DCFG_CCSR_RSTRQPBLSR) 608
13.3.13/
1EE_00C0 Reset Request Mask Register (DCFG_CCSR_RSTRQMR1) 32 R/W 0000_4000h
609
13.3.14/
1EE_00C8 Reset Request Status Register (DCFG_CCSR_RSTRQSR1) 32 w1c 0000_0000h
611
13.3.15/
1EE_00E4 Boot Release Register (DCFG_CCSR_BRR) 32 R/W 0000_0000h
615
Reset Control Word Status Register n 13.3.16/
1EE_0100 32 R See section
(DCFG_CCSR_RCWSR1) 616
Reset Control Word Status Register n 13.3.16/
1EE_0104 32 R See section
(DCFG_CCSR_RCWSR2) 616
Reset Control Word Status Register n 13.3.16/
1EE_0108 32 R See section
(DCFG_CCSR_RCWSR3) 616
Reset Control Word Status Register n 13.3.16/
1EE_010C 32 R See section
(DCFG_CCSR_RCWSR4) 616
Reset Control Word Status Register n 13.3.16/
1EE_0110 32 R See section
(DCFG_CCSR_RCWSR5) 616
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
586 NXP Semiconductors
Chapter 13 Device Configuration and Pin Control
DCFG_CCSR memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Reset Control Word Status Register n 13.3.16/
1EE_0114 32 R See section
(DCFG_CCSR_RCWSR6) 616
Reset Control Word Status Register n 13.3.16/
1EE_0118 32 R See section
(DCFG_CCSR_RCWSR7) 616
Reset Control Word Status Register n 13.3.16/
1EE_011C 32 R See section
(DCFG_CCSR_RCWSR8) 616
Reset Control Word Status Register n 13.3.16/
1EE_0120 32 R See section
(DCFG_CCSR_RCWSR9) 616
Reset Control Word Status Register n 13.3.16/
1EE_0124 32 R See section
(DCFG_CCSR_RCWSR10) 616
Reset Control Word Status Register n 13.3.16/
1EE_0128 32 R See section
(DCFG_CCSR_RCWSR11) 616
Reset Control Word Status Register n 13.3.16/
1EE_012C 32 R See section
(DCFG_CCSR_RCWSR12) 616
Reset Control Word Status Register n 13.3.16/
1EE_0130 32 R See section
(DCFG_CCSR_RCWSR13) 616
Reset Control Word Status Register n 13.3.16/
1EE_0134 32 R See section
(DCFG_CCSR_RCWSR14) 616
Reset Control Word Status Register n 13.3.16/
1EE_0138 32 R See section
(DCFG_CCSR_RCWSR15) 616
Reset Control Word Status Register n 13.3.16/
1EE_013C 32 R See section
(DCFG_CCSR_RCWSR16) 616
Scratch Read / Write Register n 13.3.17/
1EE_0200 32 R/W 0000_0000h
(DCFG_CCSR_SCRATCHRW1) 617
Scratch Read / Write Register n 13.3.17/
1EE_0204 32 R/W 0000_0000h
(DCFG_CCSR_SCRATCHRW2) 617
Scratch Read / Write Register n 13.3.17/
1EE_0208 32 R/W 0000_0000h
(DCFG_CCSR_SCRATCHRW3) 617
Scratch Read / Write Register n 13.3.17/
1EE_020C 32 R/W 0000_0000h
(DCFG_CCSR_SCRATCHRW4) 617
13.3.18/
1EE_0300 Scratch Read Register n (DCFG_CCSR_SCRATCHW1R1) 32 R/W 0000_0000h
618
13.3.18/
1EE_0304 Scratch Read Register n (DCFG_CCSR_SCRATCHW1R2) 32 R/W 0000_0000h
618
13.3.18/
1EE_0308 Scratch Read Register n (DCFG_CCSR_SCRATCHW1R3) 32 R/W 0000_0000h
618
13.3.18/
1EE_030C Scratch Read Register n (DCFG_CCSR_SCRATCHW1R4) 32 R/W 0000_0000h
618
13.3.19/
1EE_0400 Core Reset Status Register n (DCFG_CCSR_CRSTSR0) 32 R/W 0000_0000h
618
13.3.19/
1EE_0404 Core Reset Status Register n (DCFG_CCSR_CRSTSR1) 32 R/W 0000_0000h
618
13.3.19/
1EE_0408 Core Reset Status Register n (DCFG_CCSR_CRSTSR2) 32 R/W 0000_0000h
618
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 587
Device Configuration/Pin Control Memory Map
DCFG_CCSR memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
13.3.19/
1EE_040C Core Reset Status Register n (DCFG_CCSR_CRSTSR3) 32 R/W 0000_0000h
618
13.3.20/
1EE_0608 DMA Control Register (DCFG_CCSR_DMACR1) 32 R/W 0000_0000h
621
Topology Initiator Type n Register 13.3.21/
1EE_0740 32 R See section
(DCFG_CCSR_TP_ITYP0) 622
Topology Initiator Type n Register 13.3.21/
1EE_0744 32 R See section
(DCFG_CCSR_TP_ITYP1) 622
Topology Initiator Type n Register 13.3.21/
1EE_0748 32 R See section
(DCFG_CCSR_TP_ITYP2) 622
Topology Initiator Type n Register 13.3.21/
1EE_074C 32 R See section
(DCFG_CCSR_TP_ITYP3) 622
Topology Initiator Type n Register 13.3.21/
1EE_0750 32 R See section
(DCFG_CCSR_TP_ITYP4) 622
Topology Initiator Type n Register 13.3.21/
1EE_0754 32 R See section
(DCFG_CCSR_TP_ITYP5) 622
Topology Initiator Type n Register 13.3.21/
1EE_0758 32 R See section
(DCFG_CCSR_TP_ITYP6) 622
Topology Initiator Type n Register 13.3.21/
1EE_075C 32 R See section
(DCFG_CCSR_TP_ITYP7) 622
Topology Initiator Type n Register 13.3.21/
1EE_0760 32 R See section
(DCFG_CCSR_TP_ITYP8) 622
Topology Initiator Type n Register 13.3.21/
1EE_0764 32 R See section
(DCFG_CCSR_TP_ITYP9) 622
Topology Initiator Type n Register 13.3.21/
1EE_0768 32 R See section
(DCFG_CCSR_TP_ITYP10) 622
Topology Initiator Type n Register 13.3.21/
1EE_076C 32 R See section
(DCFG_CCSR_TP_ITYP11) 622
Topology Initiator Type n Register 13.3.21/
1EE_0770 32 R See section
(DCFG_CCSR_TP_ITYP12) 622
Topology Initiator Type n Register 13.3.21/
1EE_0774 32 R See section
(DCFG_CCSR_TP_ITYP13) 622
Topology Initiator Type n Register 13.3.21/
1EE_0778 32 R See section
(DCFG_CCSR_TP_ITYP14) 622
Topology Initiator Type n Register 13.3.21/
1EE_077C 32 R See section
(DCFG_CCSR_TP_ITYP15) 622
Topology Initiator Type n Register 13.3.21/
1EE_0780 32 R See section
(DCFG_CCSR_TP_ITYP16) 622
Topology Initiator Type n Register 13.3.21/
1EE_0784 32 R See section
(DCFG_CCSR_TP_ITYP17) 622
Topology Initiator Type n Register 13.3.21/
1EE_0788 32 R See section
(DCFG_CCSR_TP_ITYP18) 622
Topology Initiator Type n Register 13.3.21/
1EE_078C 32 R See section
(DCFG_CCSR_TP_ITYP19) 622
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
588 NXP Semiconductors
Chapter 13 Device Configuration and Pin Control
DCFG_CCSR memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Topology Initiator Type n Register 13.3.21/
1EE_0790 32 R See section
(DCFG_CCSR_TP_ITYP20) 622
Topology Initiator Type n Register 13.3.21/
1EE_0794 32 R See section
(DCFG_CCSR_TP_ITYP21) 622
Topology Initiator Type n Register 13.3.21/
1EE_0798 32 R See section
(DCFG_CCSR_TP_ITYP22) 622
Topology Initiator Type n Register 13.3.21/
1EE_079C 32 R See section
(DCFG_CCSR_TP_ITYP23) 622
Topology Initiator Type n Register 13.3.21/
1EE_07A0 32 R See section
(DCFG_CCSR_TP_ITYP24) 622
Topology Initiator Type n Register 13.3.21/
1EE_07A4 32 R See section
(DCFG_CCSR_TP_ITYP25) 622
Topology Initiator Type n Register 13.3.21/
1EE_07A8 32 R See section
(DCFG_CCSR_TP_ITYP26) 622
Topology Initiator Type n Register 13.3.21/
1EE_07AC 32 R See section
(DCFG_CCSR_TP_ITYP27) 622
Topology Initiator Type n Register 13.3.21/
1EE_07B0 32 R See section
(DCFG_CCSR_TP_ITYP28) 622
Topology Initiator Type n Register 13.3.21/
1EE_07B4 32 R See section
(DCFG_CCSR_TP_ITYP29) 622
Topology Initiator Type n Register 13.3.21/
1EE_07B8 32 R See section
(DCFG_CCSR_TP_ITYP30) 622
Topology Initiator Type n Register 13.3.21/
1EE_07BC 32 R See section
(DCFG_CCSR_TP_ITYP31) 622
Topology Initiator Type n Register 13.3.21/
1EE_07C0 32 R See section
(DCFG_CCSR_TP_ITYP32) 622
Topology Initiator Type n Register 13.3.21/
1EE_07C4 32 R See section
(DCFG_CCSR_TP_ITYP33) 622
Topology Initiator Type n Register 13.3.21/
1EE_07C8 32 R See section
(DCFG_CCSR_TP_ITYP34) 622
Topology Initiator Type n Register 13.3.21/
1EE_07CC 32 R See section
(DCFG_CCSR_TP_ITYP35) 622
Topology Initiator Type n Register 13.3.21/
1EE_07D0 32 R See section
(DCFG_CCSR_TP_ITYP36) 622
Topology Initiator Type n Register 13.3.21/
1EE_07D4 32 R See section
(DCFG_CCSR_TP_ITYP37) 622
Topology Initiator Type n Register 13.3.21/
1EE_07D8 32 R See section
(DCFG_CCSR_TP_ITYP38) 622
Topology Initiator Type n Register 13.3.21/
1EE_07DC 32 R See section
(DCFG_CCSR_TP_ITYP39) 622
Topology Initiator Type n Register 13.3.21/
1EE_07E0 32 R See section
(DCFG_CCSR_TP_ITYP40) 622
Topology Initiator Type n Register 13.3.21/
1EE_07E4 32 R See section
(DCFG_CCSR_TP_ITYP41) 622
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 589
Device Configuration/Pin Control Memory Map
DCFG_CCSR memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Topology Initiator Type n Register 13.3.21/
1EE_07E8 32 R See section
(DCFG_CCSR_TP_ITYP42) 622
Topology Initiator Type n Register 13.3.21/
1EE_07EC 32 R See section
(DCFG_CCSR_TP_ITYP43) 622
Topology Initiator Type n Register 13.3.21/
1EE_07F0 32 R See section
(DCFG_CCSR_TP_ITYP44) 622
Topology Initiator Type n Register 13.3.21/
1EE_07F4 32 R See section
(DCFG_CCSR_TP_ITYP45) 622
Topology Initiator Type n Register 13.3.21/
1EE_07F8 32 R See section
(DCFG_CCSR_TP_ITYP46) 622
Topology Initiator Type n Register 13.3.21/
1EE_07FC 32 R See section
(DCFG_CCSR_TP_ITYP47) 622
Topology Initiator Type n Register 13.3.21/
1EE_0800 32 R See section
(DCFG_CCSR_TP_ITYP48) 622
Topology Initiator Type n Register 13.3.21/
1EE_0804 32 R See section
(DCFG_CCSR_TP_ITYP49) 622
Topology Initiator Type n Register 13.3.21/
1EE_0808 32 R See section
(DCFG_CCSR_TP_ITYP50) 622
Topology Initiator Type n Register 13.3.21/
1EE_080C 32 R See section
(DCFG_CCSR_TP_ITYP51) 622
Topology Initiator Type n Register 13.3.21/
1EE_0810 32 R See section
(DCFG_CCSR_TP_ITYP52) 622
Topology Initiator Type n Register 13.3.21/
1EE_0814 32 R See section
(DCFG_CCSR_TP_ITYP53) 622
Topology Initiator Type n Register 13.3.21/
1EE_0818 32 R See section
(DCFG_CCSR_TP_ITYP54) 622
Topology Initiator Type n Register 13.3.21/
1EE_081C 32 R See section
(DCFG_CCSR_TP_ITYP55) 622
Topology Initiator Type n Register 13.3.21/
1EE_0820 32 R See section
(DCFG_CCSR_TP_ITYP56) 622
Topology Initiator Type n Register 13.3.21/
1EE_0824 32 R See section
(DCFG_CCSR_TP_ITYP57) 622
Topology Initiator Type n Register 13.3.21/
1EE_0828 32 R See section
(DCFG_CCSR_TP_ITYP58) 622
Topology Initiator Type n Register 13.3.21/
1EE_082C 32 R See section
(DCFG_CCSR_TP_ITYP59) 622
Topology Initiator Type n Register 13.3.21/
1EE_0830 32 R See section
(DCFG_CCSR_TP_ITYP60) 622
Topology Initiator Type n Register 13.3.21/
1EE_0834 32 R See section
(DCFG_CCSR_TP_ITYP61) 622
Topology Initiator Type n Register 13.3.21/
1EE_0838 32 R See section
(DCFG_CCSR_TP_ITYP62) 622
Topology Initiator Type n Register 13.3.21/
1EE_083C 32 R See section
(DCFG_CCSR_TP_ITYP63) 622
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
590 NXP Semiconductors
Chapter 13 Device Configuration and Pin Control
DCFG_CCSR memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Core Cluster n Topology Register 13.3.22/
1EE_0844 32 R See section
(DCFG_CCSR_TP_CLUSTER1) 623
13.3.23/
1EE_0E60 DDR Clock Disable Register (DCFG_CCSR_DDRCLKDR) 32 R/W 0000_0000h
624
13.3.24/
1EE_0E60 DDR Clock Disable Register (DCFG_CCSR_DDRCLKDR) 32 R/W 0000_0000h
625
13.3.25/
1EE_0E68 IFC Clock Disable Register (DCFG_CCSR_IFCCLKDR) 32 R/W 0000_0000h
626
eSDHC Polarity Configuration Register 13.3.26/
1EE_0E80 32 R/W 0000_0000h
(DCFG_CCSR_SDHCPCR) 627
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 591
Device Configuration/Pin Control Memory Map
13.3.1 POR Status Register 1 (DCFG_CCSR_PORSR1)
PORSR1 captures the values of the device's POR configuration pins.
NOTE
The status of these bits depends on the sampling value driven
on the pad.
Address: 1EE_0000h base + 0h offset = 1EE_0000h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
IFC_TE
R RCW_SRC
Reserved Reserved
Reset n n n n n n n n n 1 1 n n 1 n n
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
ENG0
ENG1
ENG2
Reserved
Reset n n n n 1 1 1 1 n 1 1 1 1 1 1 1
DCFG_CCSR_PORSR1 field descriptions
Field Description
0–8 Reset Configuration Word Source. Indicates which Flash memory contains the RCW information.
RCW_SRC
Loaded with the value of cfg_rcw_src[0:8].
9–12 This field is reserved.
- Reserved
13 IFC External Transceive Enable Polarity Selection.
IFC_TE
Loaded with the value of the cfg_ifc_te pin at power-on reset.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
592 NXP Semiconductors
Chapter 13 Device Configuration and Pin Control
DCFG_CCSR_PORSR1 field descriptions (continued)
Field Description
0 Transceiver Enable polarity is configured active high
1 Transceiver Enable polarity is configured active low
14–15 This field is reserved.
- Reserved
16 Engineering Use
ENG0
Loaded with the value of the cfg_eng_use[0] pin at power-on reset.
0 Config pin was not set
1 Config pin was set
17 Engineering Use
ENG1
Loaded with the value of the cfg_eng_use[1] pin at power-on reset.
0 Config pin was not set
1 Config pin was set
18 Engineering Use
ENG2
Loaded with the value of the cfg_eng_use[2] pin at power-on reset.
0 Config pin was not set
1 Config pin was set
19–31 This field is reserved.
- Reserved
13.3.2 POR Status Register 2 (DCFG_CCSR_PORSR2)
PORSR2 captures the values of the device's POR configuration pins.
NOTE
The status of these bits depends on the sampling value driven
on the pad.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 593
Device Configuration/Pin Control Memory Map
Address: 1EE_0000h base + 4h offset = 1EE_0004h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DRAM_TYPE
R
Reserved Reserved
Reset n n n n n n n n 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DCFG_CCSR_PORSR2 field descriptions
Field Description
0–1 This field is reserved.
- reserved
2 DRAM Type Selector.
DRAM_TYPE
0 DDR4 technology (1.2 V)
1 DDR3L technology (1.35 V)
3–31 This field is reserved.
- Reserved
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
594 NXP Semiconductors
Chapter 13 Device Configuration and Pin Control
13.3.3 General-Purpose POR Configuration Register
(DCFG_CCSR_GPPORCR1)
GPPORCR1 stores the value sampled from the integrated Flash controller address/data
signals, IFC_AD[0:7], using sampling logic similar to that for the configuration pins It is
provided for customer use and always samples 8-bits, independent of the width of the
chip's flash controller's LAD bus. Software can use this value to inform the operating
system about initial system configuration. Typical interpretations include circuit board
type, board ID number, or a list of available peripherals.
Address: 1EE_0000h base + 20h offset = 1EE_0020h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R POR_CFG_VEC
Reserved
W
Reset * * * * * * * * 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
* Notes:
• POR_CFG_VEC field: Reset value supplied by cfg_gpinput[0:7].
DCFG_CCSR_GPPORCR1 field descriptions
Field Description
0–7 General-purpose POR configuration vector sampled from integrated Flash controller address/data signals,
POR_CFG_VEC IFC_AD[0:7] signals (uppermost 8-bits) at the negation of PORESET.
NOTE: Reset value supplied by cfg_gpinput[0:7].
8–31 This field is reserved.
- Reserved
13.3.4 Device Disable Register 1 (DCFG_CCSR_DEVDISR1)
A given application may not use all the peripherals on the device. In this case, it may be
desirable to disable unused peripherals. DEVDISR1 provides a mechanism for gating
clocks to IP blocks that are not used when running an application.
NOTE
IP blocks disabled by setting the corresponding bit in the
DEVDISR1 register must not be re-enabled.
NOTE
Power down for any module can be configured by
programming the DCFG_DEVDISR register. If any module is
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 595
Device Configuration/Pin Control Memory Map
powered down, then its data access as well as register access are
not allowed.
Address: 1EE_0000h base + 70h offset = 1EE_0070h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
Reserved
ESDHC
DMA1
DMA2
PBL Reserved Reserved USB3 USB2
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Reserved
SATA
USB1 Reserved SEC Reserved QE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DCFG_CCSR_DEVDISR1 field descriptions
Field Description
0 Pre-boot loader disable.
PBL
0 Module is enabled
1 Module is disabled
1 This field is reserved.
- Reserved
2 eSDHC controller disable.
ESDHC
0 Module is enabled
1 Module is disabled
3–7 This field is reserved.
- Reserved
8 DMA controller 1 disable.
DMA1
DMA1 here represents qDMA.
0 Module is enabled
1 Module is disabled
9 DMA controller 2 disable.
DMA2
DMA2 here represents eDMA.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
596 NXP Semiconductors
Chapter 13 Device Configuration and Pin Control
DCFG_CCSR_DEVDISR1 field descriptions (continued)
Field Description
0 Module is enabled
1 Module is disabled
10–13 This field is reserved.
- Reserved
14 USB controller 3 disable.
USB3
0 Module is enabled
1 Module is disabled
15 USB Controller 2 disable.
USB2
0 Module is enabled
1 Module is disabled
16 SATA disable.
SATA
0 Module is enabled
1 Module is disabled
17 USB controller 1 disable.
USB1
0 Module is enabled
1 Module is disabled
18–21 This field is reserved.
- Reserved
22 SEC module disable.
SEC
0 Module is enabled
1 Module is disabled
23–29 This field is reserved.
- Reserved
30 This field is reserved.
-
31 QUICC Engine disable.
QE
0 Module is enabled
1 Module is disabled
13.3.5 Device Disable Register 2 (DCFG_CCSR_DEVDISR2)
A given application may not use all the peripherals on the device. In this case, it may be
desirable to disable unused peripherals. DEVDISR2 provides a mechanism for gating
clocks to IP blocks that are not used when running an application.
NOTE
IP Blocks disabled by setting the corresponding bit in the
DEVDISR2 register must not be re-enabled.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 597
Device Configuration/Pin Control Memory Map
NOTE
Power down for any module can be configured by
programming the DCFG_DEVDISR register. If any module is
powered down, then its data access as well as register access are
not allowed.
Address: 1EE_0000h base + 74h offset = 1EE_0074h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
FMAN1_MAC1
FMAN1_MAC2
FMAN1_MAC3
FMAN1_MAC4
FMAN1_MAC5
FMAN1_MAC6
FMAN1_MAC9
Reserved
Reserved Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
FMAN1
Reserved Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DCFG_CCSR_DEVDISR2 field descriptions
Field Description
0 Frame manager 1, MAC1 disable.
FMAN1_MAC1
0 Module is enabled
1 Module is disabled
1 Frame manager 1, MAC2 disable.
FMAN1_MAC2
0 Module is enabled
1 Module is disabled
2 Frame manager 1, MAC3 disable.
FMAN1_MAC3
0 Module is enabled
1 Module is disabled
3 Frame manager 1, MAC4 disable.
FMAN1_MAC4
0 Module is enabled
1 Module is disabled
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
598 NXP Semiconductors
Chapter 13 Device Configuration and Pin Control
DCFG_CCSR_DEVDISR2 field descriptions (continued)
Field Description
4 Frame manager 1, MAC5 disable.
FMAN1_MAC5
0 Module is enabled
1 Module is disabled
5 Frame manager 1, MAC6 disable.
FMAN1_MAC6
0 Module is enabled
1 Module is disabled
6–7 This field is reserved.
- Reserved
8 Frame manager 1, MAC9 disable.
FMAN1_MAC9
0 Module is enabled
1 Module is disabled
9 This field is reserved.
- Reserved
10–23 This field is reserved.
- Reserved
24 Frame manager 1 disable.
FMAN1
0 Module is enabled
1 Module is disabled
25–31 This field is reserved.
- Reserved
13.3.6 Device Disable Register 3 (DCFG_CCSR_DEVDISR3)
A given application may not use all the peripherals on the device. In this case, it may be
desirable to disable unused peripherals. DEVDISR3 provides a mechanism for gating
clocks to IP blocks that are not used when running an application.
NOTE
IP Blocks disabled by setting the corresponding bit in the
DEVDISR3 register must not be re-enabled.
NOTE
Power down for any module can be configured by
programming the DCFG_DEVDISR register. If any module is
powered down, then its data access as well as register access are
not allowed.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 599
Device Configuration/Pin Control Memory Map
Address: 1EE_0000h base + 78h offset = 1EE_0078h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
QMAN
BMAN
Reserved Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DCFG_CCSR_DEVDISR3 field descriptions
Field Description
0–11 This field is reserved.
- Reserved
12 Queue manager disable.
QMAN
0 Module is enabled
1 Module is disabled
13 Buffer manager disable.
BMAN
0 Module is enabled
1 Module is disabled
14–31 This field is reserved.
- Reserved
13.3.7 Device Disable Register 4 (DCFG_CCSR_DEVDISR4)
A given application may not use all the peripherals on the device. In this case, it may be
desirable to disable unused peripherals. DEVDISR4 provides a mechanism for gating
clocks to IP blocks that are not used when running an application.
NOTE
IP Blocks disabled by setting the corresponding bit in the
DEVDISR4 register must not be re-enabled.
NOTE
Power down for any module can be configured by
programming the DCFG_DEVDISR register. If any module is
powered down, then its data access as well as register access are
not allowed.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
600 NXP Semiconductors
Chapter 13 Device Configuration and Pin Control
Address: 1EE_0000h base + 7Ch offset = 1EE_007Ch
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DUART1
DUART2
Reserved QSPI Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DCFG_CCSR_DEVDISR4 field descriptions
Field Description
0–1 This field is reserved.
- Reserved
2 DUART1 module disable.
DUART1
0 Module is enabled
1 Module is disabled
3 DUART2 module disable.
DUART2
0 Module is enabled
1 Module is disabled
4 QuadSPI module disable
QSPI
0 Module is enabled
1 Module is disabled
5–31 This field is reserved.
- Reserved
13.3.8 Device Disable Register 5 (DCFG_CCSR_DEVDISR5)
A given application may not use all the peripherals on the device. In this case, it may be
desirable to disable unused peripherals. DEVDISR5 provides a mechanism for gating
clocks to IP blocks that are not used when running an application.
NOTE
IP Blocks disabled by setting the corresponding bit in the
DEVDISR5 register must not be re-enabled.
NOTE
Power down for any module can be configured by
programming the DCFG_DEVDISR register. If any module is
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 601
Device Configuration/Pin Control Memory Map
powered down, then its data access as well as register access are
not allowed.
Address: 1EE_0000h base + 80h offset = 1EE_0080h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
LPUART4
LPUART1
LPUART2
OCRAM1
OCRAM2
Reserved
DDR Reserved Reserved IFC GPIO DBG Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
LPUART3
LPUART5
LPUART6
FlexTimer
Reserved
WDOG1
WDOG2
WDOG3
WDOG4
WDOG5
ICMMU
SPI1 IIC4 IIC3 IIC2 IIC1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DCFG_CCSR_DEVDISR5 field descriptions
Field Description
0 DDR Controller disable
DDR
0 Module is enabled
1 Module is disabled
1–2 This field is reserved.
- Reserved
3 Module disable
LPUART4
0 Module is enabled
1 Module is disabled
4–5 This field is reserved.
- Reserved
6 OCRAM1 disable
OCRAM1
0 Module is enabled
1 Module is disabled
7 OCRAM2 disable
OCRAM2
0 Module is enabled
1 Module is disabled
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
602 NXP Semiconductors
Chapter 13 Device Configuration and Pin Control
DCFG_CCSR_DEVDISR5 field descriptions (continued)
Field Description
8 Integrated Flash controller disable.
IFC
0 Module is enabled
1 Module is disabled
9 GPIO disable.
GPIO
NOTE: This field disables all GPIO modules.
0 Module is enabled
1 Module is disabled
10 Debug module disable.
DBG
0 Module is enabled
1 Module is disabled
11 This field is reserved.
- Reserved
12–13 This field is reserved.
- Reserved
14 LPUART1 disable
LPUART1
0 Module is enabled
1 Module is disabled
15 LPUART2 disable
LPUART2
0 Module is enabled
1 Module is disabled
16 LPUART3 disable
LPUART3
0 Module is enabled
1 Module is disabled
17 This field is reserved.
- Reserved
18 LPUART5 disable
LPUART5
0 Module is enabled
1 Module is disabled
19 LPUART6 disable
LPUART6
0 Module is enabled
1 Module is disabled
20 WDOG1 disable.
WDOG1
0 Module is enabled
1 Module is disabled
21 FlexTimer disable.
FlexTimer
0 Module is enabled
1 Module is disabled
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 603
Device Configuration/Pin Control Memory Map
DCFG_CCSR_DEVDISR5 field descriptions (continued)
Field Description
22 WDOG2 disable.
WDOG2
0 Module is enabled
1 Module is disabled
23 SPI1 disable.
SPI1
0 Module is enabled
1 Module is disabled
24 WDOG3 disable.
WDOG3
0 Module is enabled
1 Module is disabled
25 WDOG4 disable.
WDOG4
0 Module is enabled
1 Module is disabled
26 WDOG5 disable.
WDOG5
0 Module is enabled
1 Module is disabled
27 IIC4 disable.
IIC4
0 Module is enabled
1 Module is disabled
28 IIC3 disable.
IIC3
0 Module is enabled
1 Module is disabled
29 IIC2 disable.
IIC2
0 Module is enabled
1 Module is disabled
30 IIC1 disable.
IIC1
0 Module is enabled
1 Module is disabled
31 Interconnects and MMU disable.
ICMMU
0 Module is enabled
1 Module is disabled
13.3.9 Core Disable Register (DCFG_CCSR_COREDISR)
COREDISR provides a mechanism for gating clocks to any cores on the device that are
not used when running an application.
COREDISR register should only be configured in the following conditions:
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
604 NXP Semiconductors
Chapter 13 Device Configuration and Pin Control
• Before system ready, COREDISR register can be programmed by the external
debugger or Pre-Boot Initialization.
• After system ready, a COREDISR register bit can be programmed for the
corresponding core by the external debugger or embedded software while the core is
in boot-holdoff mode.
NOTE
Cores that have an interrupt pending will not be disabled by
COREDISR until the interrupt is cleared.
NOTE
Cores disabled by setting the corresponding bit in the
COREDISR register must not be re-enabled via software. The
only supported mechanism for re-enabling a Core disabled in
this manner is via power-on, hard reset, or core reset.
NOTE
The LSB, bit 31, is associated with Core 0.
Note that
• for dual core personality, COREDISR will be set by hardware
• If software sets COREDISR to disable the cores, it will not work as halting core
involves a software step (wfi execution)
Address: 1EE_0000h base + 94h offset = 1EE_0094h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
Reserved
Reserved CD3 CD2 CD1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 605
Device Configuration/Pin Control Memory Map
DCFG_CCSR_COREDISR field descriptions
Field Description
0–27 This field is reserved.
- Reserved
28 Core 3 Disable.
CD3
0 Selected Core is enabled
1 Selected Core is disabled
29 Core 2 Disable.
CD2
0 Selected Core is enabled
1 Selected Core is disabled
30 Core 1 Disable.
CD1
0 Selected Core is enabled
1 Selected Core is disabled
31 This field is reserved.
- Reserved, set to 0
13.3.10 System Version Register (DCFG_CCSR_SVR)
The SVR contains the system version number for the device. This value can also be read
though the SVR SPR of the Arm Cortex-A53 core.
Address: 1EE_0000h base + A4h offset = 1EE_00A4h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R MFR_ID SOC_DEV_ID VAR_PER MAJOR_REV MINOR_REV
W
Reset 1 0 0 0 0 1 1 1 1 0 0 1 0 0 1 0 0 0 0 0 n 0 0 n 0 0 0 1 0 0 0 1
DCFG_CCSR_SVR field descriptions
Field Description
0–3 Manufacturer ID
MFR_ID
4–15 Chip Device ID
SOC_DEV_ID
16–23 Various Personalities
VAR_PER
For 21x21 package:
0000_0000 LS1043A (Export controlled crypto hardware enabled)
0000_0001 LS1043A (Export controlled crypto hardware disabled)
0000_1000 LS1023A (Export controlled crypto hardware enabled)
0000_1001 LS1023A (Export controlled crypto hardware disabled)
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
606 NXP Semiconductors
Chapter 13 Device Configuration and Pin Control
DCFG_CCSR_SVR field descriptions (continued)
Field Description
24–27 Major Revision Number
MAJOR_REV
28–31 Minor Revision Number
MINOR_REV
For Si 1.1, the minor revision is 0x1.
For Si 1.0, the minor revision is 0x0.
13.3.11 Reset Control Register (DCFG_CCSR_RSTCR)
The RSTCR allows software to control reset functions.
Address: 1EE_0000h base + B0h offset = 1EE_00B0h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
RESET_REQ
Reserved
Reserved
Reserved Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DCFG_CCSR_RSTCR field descriptions
Field Description
0–26 This field is reserved.
- Reserved
27 This field is reserved.
- Reserved
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 607
Device Configuration/Pin Control Memory Map
DCFG_CCSR_RSTCR field descriptions (continued)
Field Description
28–29 This field is reserved.
- Reserved
30 Hardware reset request. External hardware may then decide to issue the desired reset signal
RESET_REQ (PORESET_B or HRESET_B) to the device.
0 No reset request initiated.
1 Hardware reset request initiated by software.
31 This field is reserved.
- Reserved
13.3.12 Reset Request Preboot Loader Status Register
(DCFG_CCSR_RSTRQPBLSR)
The RSTRQPBLSR contains status bits to record the reasons for RESET_REQ_B
assertion. It excludes core watchdog timer sources.
NOTE
This register's code is valid only when RSTRQSR[PBL_RR] is
set.
NOTE
ECC errors detected during NAND flash loading during RCW
and PBI phases are reported in RSTRQSR[IFC_RR]. See the
description of this bit for more details.
Address: 1EE_0000h base + B4h offset = 1EE_00B4h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R ERR_CODE
Reserved Reserved
W w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DCFG_CCSR_RSTRQPBLSR field descriptions
Field Description
0–7 This field is reserved.
- Reserved
8–14 7-bit PBL Error Code
ERR_CODE
7-bit encoded value reflects one of 128 possible PBL errors.
Write 1 to each bit to clear this field.
NOTE: See Error codes for details on the PBL error encodings.
15–31 This field is reserved.
- Reserved
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
608 NXP Semiconductors
Chapter 13 Device Configuration and Pin Control
13.3.13 Reset Request Mask Register (DCFG_CCSR_RSTRQMR1)
The RSTRQMR contains mask bits for optional masking of RESET_REQ_B sources to
prevent generation of such a reset request. It excludes core watchdog timer sources.
Address: 1EE_0000h base + C0h offset = 1EE_00C0h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CORE_WDOG3_RST_
CORE_WDOG4_RST_
CORE_WDOG5_RST_
ALTCBAR_MSK
Reserved
IFC_ PBL_ SFP_ SEC_
MSK
MSK
MSK
Reserved Reserved
MSK MSK MSK MSK
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
CORE_WDOG_RST_MSK
SRDS_RST_MSK
R
CCP_ERR_MSK
RPTOE_MSK
MBEE_MSK
SDC_MSK
Reserved
Reserved
Reset 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DCFG_CCSR_RSTRQMR1 field descriptions
Field Description
0 Core watchdog reset request mask.
CORE_WDOG3_
RST_MSK 0 Core watchdog reset request can cause a reset request
1 Core watchdog reset request cannot cause a reset request
1 Core watchdog reset request mask.
CORE_WDOG4_
RST_MSK 0 Core watchdog reset request can cause a reset request
1 Core watchdog reset request cannot cause a reset request
2 Core watchdog reset request mask.
CORE_WDOG5_
RST_MSK 0 Core watchdog reset request can cause a reset request
1 Core watchdog reset request cannot cause a reset request
3 This field is reserved.
- Reserved
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 609
Device Configuration/Pin Control Memory Map
DCFG_CCSR_RSTRQMR1 field descriptions (continued)
Field Description
4–8 This field is reserved.
- Reserved
9 Integrated Flash Controller reset request event mask
IFC_MSK
0 IFC error event can cause a reset request
1 IFC error event cannot cause a reset request
10–11 This field is reserved.
- Reserved
12 ALTCBAR violation by PBL reset request mask
ALTCBAR_MSK
0 ALTCBAR violation by PBL can cause a reset request
1 ALTCBAR violation by PBL cannot cause a reset request
13 PBL error reset request event mask.
PBL_MSK
0 PBL error event can cause a reset request
1 PBL error event cannot cause a reset request
14 Security Fuse Processor error during POR fuse process reset mask.
SFP_MSK
0 Security Fuse Processor error event can cause a reset request
1 Security Fuse Processor error event cannot cause a reset request
15 Security monitor reset request event mask
SEC_MSK
0 Security monitor reset request event mask can cause a reset request
1 Security monitor reset request event mask cannot cause a reset request
16 Security Debug Controller error reset request mask
SDC_MSK
0 SDC error event can cause a reset request
1 SDC error event cannot cause a reset request
17 Multi-bit ECC error reset request mask
MBEE_MSK
0 Multi-bit ECC error event can cause a reset request
1 Multi-bit ECC error event cannot cause a reset request
18 This field is reserved.
- Reserved
POR BIST error event can cause a reset request
19 RCPM Time Out reset request event mask
RPTOE_MSK
0 RCPM Time Out event can cause a reset request
1 RCPM Time Out event cannot cause a reset request
20 SerDes reset request event mask
SRDS_RST_
MSK 0 SerDes reset event can cause a reset request
1 SerDes reset event cannot cause a reset request
21 REP Error Alarm from CCP(REP) event mask.
CCP_ERR_MSK
0 REP Error Alarm from CCP event can cause a reset request
1 REP Error Alarm from CCP event cannot cause a reset request
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
610 NXP Semiconductors
Chapter 13 Device Configuration and Pin Control
DCFG_CCSR_RSTRQMR1 field descriptions (continued)
Field Description
22 Core watchdog reset request mask.
CORE_WDOG_
RST_MSK 0 Core watchdog reset request can cause a reset request
1 Core watchdog reset request cannot cause a reset request
23–31 This field is reserved.
- Reserved
13.3.14 Reset Request Status Register (DCFG_CCSR_RSTRQSR1)
The RSTRQSR contains status bits to record the reasons for RESET_REQ_B assertion.
The bits here are set independent of the RSTRQMR. This means if a reset reason occurs
and is masked by RSTRQMR, it will still be recorded in RSTRQSR.
NOTE
For the different sources captured in this register, some of these
can be serviced with either PORESET_B or HRESET_B and
some of these must be serviced with PORESET_B only.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 611
Device Configuration/Pin Control Memory Map
Address: 1EE_0000h base + C8h offset = 1EE_00C8h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CORE_WDOG3_RST_RR
CORE_WDOG4_RST_RR
CORE_WDOG5_RST_RR
ALTCBAR_RR
SEC_RR
SFP_RR
PBL_RR
IFC_RR
R
Reserved
Reserved Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
612 NXP Semiconductors
Chapter 13 Device Configuration and Pin Control
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
CORE_WDOG1_RST_RR
SRDS_RST_RR
CCP_ERR_RR
RPTOE_RR
MBEE_RR
SDC_RR
R
Reserved
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DCFG_CCSR_RSTRQSR1 field descriptions
Field Description
0 Core watchdog event reset request
CORE_WDOG3_
RST_RR 0 WDOG reset request from WDOG3 is not active
1 WDOG reset request from WDOG3 is active
1 Core watchdog event reset request
CORE_WDOG4_
RST_RR 0 WDOG reset request from WDOG4 is not active
1 WDOG reset request from WDOG4 is active
2 Core watchdog event reset request
CORE_WDOG5_
RST_RR 0 WDOG reset request from WDOG5 is not active
1 WDOG reset request from WDOG5 is active
3 This field is reserved.
- Reserved
4–8 This field is reserved.
- Reserved
9 Integrated Flash Controller reset request event
IFC_RR
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 613
Device Configuration/Pin Control Memory Map
DCFG_CCSR_RSTRQSR1 field descriptions (continued)
Field Description
This bit is set if an ECC error occured in NAND Flash preload for the RCW phase or the Preboot
Initialization phase
NOTE: After a PORESET, RCWSRn registers can be read. If RSTRQSR[IFC_RR] is set after a
PORESET and RCWSRn does not contain RCW values, then the failure occurred during RCW. If
the bit is set and RCWSRn contains valid values, then the failure occurred during PBI.
0 IFC reset event reset request event not active
1 IFC reset event reset request event active
10–11 This field is reserved.
- Reserved
12 ALTCBAR violation by PBL reset request
ALTCBAR_RR
0 ALTCBAR violation by PBL reset request event not active
1 ALTCBAR violation by PBL reset request event active
13 PBL error reset request requires device level PORESET_B or HRESET_B.
PBL_RR
0 PBL reset request event not active
1 PBL reset request event active
14 Security Fuse Processor error during POR fuse process caused reset request.
SFP_RR
Security Fuse Processor error requires device level PORESET._B
0 Security Fuse Processor reset request event not active
1 Security Fuse Processor reset request event active
15 Security Monitor detected security violation/tampering event during POR fuse process caused reset
SEC_RR request.
Security Monitor reached Hard Fail state and requires device level PORESET_B .
0 Security Monitor reset request event not active
1 Security Monitor reset request event active
16 Security Debug Controller reset request
SDC_RR
Security Debug Controller requires device level PORESET_B .
0 SDC reset request event not active
1 SDC reset request event active
17 Multi-bit ECC reset request
MBEE_RR
Platform internal memory multi-bit ECC error requires device level PORESET_B or HRESET_B.
Note: This bit is for multi-bit error in any of the SRAMs inside the chip including OCRAM and not for L1/L2
cache memories.
0 Multi-bit ECC error reset request event not active
1 Multi-bit ECC error reset request event active
18 This field is reserved.
- Reserved
19 RCPM Time Out reset request event
RPTOE_RR
RCPM Time Out event (for core halt, core stop, or core reset request) requires device level PORESET_B
or HRESET_B.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
614 NXP Semiconductors
Chapter 13 Device Configuration and Pin Control
DCFG_CCSR_RSTRQSR1 field descriptions (continued)
Field Description
0 RCPM Time Out event reset request event not active
1 RCPM Time Out event reset request event active
20 SerDes reset event. Occurs if any enabled SerDes PLL does not lock.
SRDS_RST_RR
0 SerDes reset request event not active
1 SerDes reset request event active
21 REP Error Alarm from CCP(REP) event reset request.
CCP_ERR_RR
22 Core watchdog event reset request.
CORE_WDOG1_
RST_RR 0 Core watchdog reset request from WDOG1 is not active
1 Core watchdog reset request from WDOG1 is active
23–31 This field is reserved.
- Reserved
13.3.15 Boot Release Register (DCFG_CCSR_BRR)
The BRR contains control bits for enabling boot for each core. On exiting HRESET or
PORESET, the RCW BOOT_HO field optionally allows for logical core 0 to be released
for booting or to remain in boot holdoff. All other cores remain in boot holdoff until their
corresponding bit is set.
This is configured by the Internal boot ROM (IBR)code based on the Core Disable
Register (DCFG_CCSR_COREDISR).
NOTE
The LSB, bit 31, is associated with Core 0.
NOTE
If a bit is changed from 1 to 0 outside of warm reset (at
runtime), results are boundedly undefined for that core.
Address: 1EE_0000h base + E4h offset = 1EE_00E4h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
W
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
Reserved CR3 CR2 CR1 CR0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 615
Device Configuration/Pin Control Memory Map
DCFG_CCSR_BRR field descriptions
Field Description
0–27 This field is reserved.
- Reserved
28 Core 3 Release.
CR3
0 Core is in Boot Holdoff and not released for Booting
1 Core released for Booting
29 Core 2 Release.
CR2
0 Core is in Boot Holdoff and not released for Booting
1 Core released for Booting
30 CR1
CR1
Core 1 Release.
0 Core is in Boot Holdoff and not released for Booting
1 Core released for Booting
31 CR0
CR0
Core 0 Release.
0 Core is in Boot Holdoff and not released for Booting
1 Core released for Booting
13.3.16 Reset Control Word Status Register n
(DCFG_CCSR_RCWSRn)
RCWSR contains the Reset Configuration Word (RCW) information written with values
read from flash memory by the device at power-on reset and read-only upon exiting reset.
NOTE
After a PORESET, RCWSRn registers can be read. If
RSTRQSR[IFC_RR] is set after a PORESET and RCWSRn
does not contain RCW values, then the failure occurred during
RCW. If the bit is set and RCWSRn contains valid values, then
the failure occurred during PBI.
Address: 1EE_0000h base + 100h offset + (4d × i), where i=0d to 15d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R RCW
W
Reset n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
616 NXP Semiconductors
Chapter 13 Device Configuration and Pin Control
DCFG_CCSR_RCWSRn field descriptions
Field Description
0–31 Read-only value of RCW bits (n-1)*32 : (n*32)-1 loaded in power-on reset's Reset Configuration stage.
RCW
13.3.17 Scratch Read / Write Register n
(DCFG_CCSR_SCRATCHRWn)
The SCRATCHRWn provides read / write scratch register locations available to the user.
NOTE
When performing secure boot, these registers are defined as
follows:
• SCRATCHRW1 - Pointer to ESBC Header (Primary Boot
Image)
• SCRATCHRW2 - Failure Code if Secure Boot Fails
(Primary Boot Image)
• SCRATCHRW3 - Pointer to ESBC Header (Alternate Boot
Image)
• SCRATCHRW4 - Failure Code if Secure Boot Fails
(Alternate Boot Image)
Address: 1EE_0000h base + 200h offset + (4d × i), where i=0d to 3d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
VAL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DCFG_CCSR_SCRATCHRWn field descriptions
Field Description
0–31 32-bit scratch contents
VAL
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 617
Device Configuration/Pin Control Memory Map
13.3.18 Scratch Read Register n (DCFG_CCSR_SCRATCHW1Rn)
The SCRATCHW1Rn provides scratch register locations available to the user. These are
write-once registers. After these have been written once, they can only be written after a
power-on or hard reset.
Address: 1EE_0000h base + 300h offset + (4d × i), where i=0d to 3d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
VAL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DCFG_CCSR_SCRATCHW1Rn field descriptions
Field Description
0–31 32-bit scratch contents
VAL
13.3.19 Core Reset Status Register n (DCFG_CCSR_CRSTSRn)
The CRSTSRn contains the reset status bits for each thread on the device.
In this register (one per physical core):
• Bits 0-23 reflect per-thread conditions for this specific core
• Bits 24-31 reflect device conditions which in turn affect this specific core
NOTE
The number of CRSTSRn registers is determined by the
number of physical cores.
Reset of this Register
A power-on reset of the device causes the following to occur:
• RST_PORST is set
• All other bits are cleared
A hard reset of the device causes the following to occur:
• RST_PORST remains unchanged (PORST resources are not affected by Hard Reset)
• RST_HRST is set
• All other bits are cleared
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
618 NXP Semiconductors
Chapter 13 Device Configuration and Pin Control
If an application prefers that RST_PORST is not set after hard reset, then a write-1-clear
must be done to CRSTSRn[RST_PORST] upon exiting power-on reset.
Ready Bit Functionality
This bit is cleared on a device power-on or hard reset. Upon completion of power-on or
hard reset processing, this bit may be automatically set for a core if none of the
conditions specified in the READY bit definition are true.
Address: 1EE_0000h base + 400h offset + (4d × i), where i=0d to 3d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Reserved Reserved Reserved Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 619
Device Configuration/Pin Control Memory Map
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
RST_PORST
RST_HRST
READY
R
Reserved
Reserved
W w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DCFG_CCSR_CRSTSRn field descriptions
Field Description
0–5 This field is reserved.
- Reserved
6–7 This field is reserved.
- Reserved
8–13 This field is reserved.
- Reserved
14–15 This field is reserved.
- Reserved
16–27 This field is reserved.
-
28 This field is reserved.
- Reserved
29 Core ready pin.
READY
Core is in the 'ready' state after device has successfully passed through the "System Ready" point and the
core is currently not in any of the following states:
This bit reflects what is driven on the READY_P0 external signal.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
620 NXP Semiconductors
Chapter 13 Device Configuration and Pin Control
DCFG_CCSR_CRSTSRn field descriptions (continued)
Field Description
0 Core 0 not ready
1 Core 0 ready
30 Core was reset due to an HRESET (note a PORESET causes an HRESET, but a PORESET will not
RST_HRST cause this bit to be set)
31 Core was reset due to a PORESET
RST_PORST
13.3.20 DMA Control Register (DCFG_CCSR_DMACR1)
The DMACR1 contains bits for allowing DMA transactions (qDMA) from internal
sources on the device.
Address: 1EE_0000h base + 608h offset = 1EE_0608h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
W
DMA1_0 Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DCFG_CCSR_DMACR1 field descriptions
Field Description
0–1 DMA 1, Channel 0.
DMA1_0
00 Reserved
01 Reserved
10 Reserved
11 DMA's Channel may be initiated by EPU
2–31 This field is reserved.
- Reserved
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 621
Device Configuration/Pin Control Memory Map
13.3.21 Topology Initiator Type n Register (DCFG_CCSR_TP_ITYPn)
Each Initiator Type Topology Register provides one entry of a 64 entry lookup table.
Address: 1EE_0000h base + 740h offset + (4d × i), where i=0d to 63d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R INIT_TYPE
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 n n n n n n n n
DCFG_CCSR_TP_ITYPn field descriptions
Field Description
0–23 This field is reserved.
- Reserved
24–31 Initiator Type.
INIT_TYPE
This field identifies the type of initiator (core or hardware accelerator) for this index. The lsb differentiates
between an enabled and a disabled instance of the initiator.
All encodings not listed below are reserved.
00h Simple initiatior
02h Arm Cortex A53 (disabled)
03h Arm Cortex A53 (enabled)
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
622 NXP Semiconductors
Chapter 13 Device Configuration and Pin Control
13.3.22 Core Cluster n Topology Register
(DCFG_CCSR_TP_CLUSTERn)
Each Topology Cluster Register (TP_CLUSTERn) contains four 6-bit fields, each of
which is an index used for an initiator type lookup in a 64 entry initiator table
implemented using the Topology Type Registers.
Address: 1EE_0000h base + 844h offset + (8d × i), where i=0d to 0d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R EOC IT_IDX_PC4 IT_IDX_PC3
Reserved
W
Reset n n n n n n n n 0 0 n n n n n n
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R IT_IDX_PC2 IT_IDX_PC1
Reserved Reserved
W
Reset 0 0 n n n n n n 0 0 n n n n n n
DCFG_CCSR_TP_CLUSTERn field descriptions
Field Description
0–1 End of Clusters - if the EOC field is non-zero, the register contains the information on the last cluster in the
EOC chip.
00 Not the last cluster
01,10,11 Last cluster in the chip
2–7 Initiator Type Index for this cluster's fourth initiator
IT_IDX_PC4
Provides a 6-bit index for accessing an entry stored in one of the TP_ITYPn registers. This index selects
which of the 64 TP_ITYPn registers contains the identification information for this initiator.
8–9 This field is reserved.
- Reserved
10–15 Initiator Type Index for this cluster third initiator
IT_IDX_PC3
Provides a 6-bit index for accessing an entry stored in one of the TP_ITYPn registers. This index selects
which of the 64 TP_ITYPn registers contains the identification information for this initiator.
16–17 This field is reserved.
- reserved
18–23 Initiator Type Index for this cluster second initiator
IT_IDX_PC2
Provides a 6-bit index for accessing an entry stored in one of the TP_ITYPn registers. This index selects
which of the 64 TP_ITYPn registers contains the identification information for this initiator.
24–25 This field is reserved.
- reserved
26–31 Initiator Type Index for this cluster first initiator
IT_IDX_PC1
Provides a 6-bit index for accessing an entry stored in one of the TP_ITYPn registers. This index selects
which of the 64 TP_ITYPn registers contains the identification information for this initiator.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 623
Device Configuration/Pin Control Memory Map
13.3.23 DDR Clock Disable Register (DCFG_CCSR_DDRCLKDR)
DDRCLKDR allows for specific, unused clocks of the DDR Controllers' interface to be
released to high impedance, thereby reducing power consumption.
Address: 1EE_0000h base + E60h offset = 1EE_0E60h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D1_MCK0_DIS
D1_MCK1_DIS
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DCFG_CCSR_DDRCLKDR field descriptions
Field Description
0 DDR Controller 1 clock 0 disable. The output is tri-stated, when disabled.
D1_MCK0_DIS
0 D1_MCK[0] is enabled
1 D1_MCK[0] is disabled
1 DDR Controller 1 clock 1 disable. The output is tri-stated, when disabled.
D1_MCK1_DIS
0 D1_MCK[1] is enabled
1 D1_MCK[1] is disabled
2–31 This field is reserved.
- Reserved
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
624 NXP Semiconductors
Chapter 13 Device Configuration and Pin Control
13.3.24 DDR Clock Disable Register (DCFG_CCSR_DDRCLKDR)
DDRCLKDR allows for specific, unused clocks of the DDR Controller interface to be
released to high impedance, thereby reducing power consumption.
Address: 1EE_0000h base + E60h offset = 1EE_0E60h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
D1_MCK1_DIS
D1_MCK0_DIS
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DCFG_CCSR_DDRCLKDR field descriptions
Field Description
0–29 This field is reserved.
-
30 DDR Controller 1 clock 1 disable. The output is tri-stated, when disabled.
D1_MCK1_DIS
0b - D1_MCK[1] is enabled
1b - D1_MCK[1] is disabled
31 DDR Controller 1 clock 0 disable. The output is tri-stated, when disabled.
D1_MCK0_DIS
0b - D1_MCK[0] is enabled
1b - D1_MCK[0] is disabled
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 625
Device Configuration/Pin Control Memory Map
13.3.25 IFC Clock Disable Register (DCFG_CCSR_IFCCLKDR)
The IFCCLKDR allows for specific, unused clocks of the IFC interface to be not driven/
high-impedance, thereby reducing power consumption.
Address: 1EE_0000h base + E68h offset = 1EE_0E68h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
IFC_CLK0_DIS
IFC_CLK1_DIS
Reserved
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DCFG_CCSR_IFCCLKDR field descriptions
Field Description
0–28 This field is reserved.
- Reserved
29 IFC clock 0 disable. The output is not driven and in a high impedance state, when disabled.
IFC_CLK0_DIS
0 IFC_CLK0 is enabled
1 IFC_CLK0 is disabled
30 IFC clock 1 disable. The output is not driven and in a high impedance state, when disabled.
IFC_CLK1_DIS
0 IFC_CLK1 is enabled
1 IFC_CLK1 is disabled
31 This field is reserved.
- Reserved
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
626 NXP Semiconductors
Chapter 13 Device Configuration and Pin Control
13.3.26 eSDHC Polarity Configuration Register
(DCFG_CCSR_SDHCPCR)
The SDHCPCR allows for specific polarity control of the eSDHC input signals.
Address: 1EE_0000h base + E80h offset = 1EE_0E80h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
WP_INV
CD_
Reserved
INV
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DCFG_CCSR_SDHCPCR field descriptions
Field Description
0 eSDHC Card Detect Invert
CD_INV
0 SDHC_CD signal to the eSDHC module has the same polarity as the I/O Pin.
1 SDHC_CD signal to the eSDHC module has inverted polarity in relation to the I/O Pin.
1 eSDHC Write Protect Invert
WP_INV
0 SDHC_WP signal to the eSDHC module has the same polarity as the I/O Pin.
1 SDHC_WP signal to the eSDHC module has inverted polarity in relation to the I/O Pin.
2–31 This field is reserved.
- Reserved
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 627
Device Configuration/Pin Control Memory Map
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
628 NXP Semiconductors
Chapter 14
Run Control and Power Management (RCPM)
14.1 Introduction
This chapter provides the specification and programming model for the RCPM.
14.1.1 Overview
The Run Control and Power Management (RCPM) module communicates with
embedded cores, coherency modules, and other device platform module to provide run
control and power management functionality. The device can be placed into a range of
low power states, via the RCPM (and its associated RCPM driver), to significantly reduce
dynamic power consumption at the processor core, cluster, and device level. The RCPM
also provides the functionality used to return processors, clusters, and device platform
module to full operation in response to wake-up events such as external signals, timers,
interrupts, and network traffic.
A complete whitepaper on QorIQ Power Management can be found at QorIQ Power
Management.
14.1.2 The RCPM module as implemented on the chip
This section provides details about how the RCPM module is integrated into this chip.
The RCPM module supports multithreaded cores; however, the A53 cores implemented
on chip are single-threaded. The following table describes the mapping of the referenced
RCPM threads and physical cores to the Arm Cortex-A53 cores:
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 629
Introduction
Table 14-1. RCPM/LS1043A thread and physical core n mapping
RCPM thread n LS1043A core RCPM LS1043A core
physical core
n
0 core 0 0 core 0
1 core 1 1 core 1
2 core 2 2 core 2
3 core 3 3 core 3
14.1.3 Power Management Features
• Software controlled power management, which minimizes power consumption of
blocks when they are idle.
• Software-controlled power management states
• Per core STANDBYWFI (PW15)
• Per device LPM20 and SWLPM20
• Per physical core-PH20
• Supports interrupt controller interrupt-based wake-up and the following wake-up
sources:
• Wake on internal timer event.
• Wake on internal and external interrupt event.
• Enter software-controlled power state through core
• Core power management:
• Independent power management control of each core
• STANDBYWFI (PW15) state where:
• Entry into PW15 mode core power management state via wait for interrupt
instruction execution by the core
• STANDBYWFI (PW15) state wake up source is captured in Table 14-4
• PH20 state where:
• Entry into PH20 core power management state via RCPM PCPH20SETR for
request to enter the core's PH20 state.
• Independent wake up from per thread:
• Unmasked interrupt request
• Unmasked critical interrupt
• Debug interrupt
• Cluster power management:
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
630 NXP Semiconductors
Chapter 14 Run Control and Power Management (RCPM)
• WFI instruction by all the cores would initiate L2 Cache of the cluster to go into
STANDBY mode.
• The entry and exit mode of cluster power management is captured in Modes
Entry and Exit for Power Management
• Device Power Management:
• LPM20 state where:
• All cores are in STANDBYWFI (PW15) state.
• All cores are in PH20 state.
• Platform clock is disabled.
• Entry into LPM20 via setting POWMGTCSR[LPM20_REQ] as well as WFI
Instruction execution from all the cores.
• LPM20 state wake up source is captured in Table 14-5
• SWLPM20 state where:
• All cores are in STANDBYWFI (PW15) state.
• Platform clock is disabled.
• Entry into SWLPM20 via WFI Instruction execution from all the cores.
• SWLPM20 state wake up source are the same as is captured in Table 14-5.
• Independent Device wake up from:
• Unmasked interrupt configured in GIC-400 and RCPM registers
• Unmasked critical interrupt
14.1.4 Power Management States
The RCPM module supports the following Power Management modes of operation:
• Power management states
• Core(s)
• Core(s) Full On state
• Core(s) in STANDBYWFI (PW15) state
• Core(s) in PH20Core(s) in PH20 state
• Device
• Device Full On state
• Device in LPM20 state
• Device in SWLPM20 state
• Reset modes
The different states available are summarized in Table 14-2 through Table 14-5.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 631
Introduction
14.1.4.1 Power Management State Summary
The following table summarizes the core power management states. For detailed
description of power management states, refer Modes Entry and Exit for Power
Management.
Table 14-2. Core and Cluster Power Management State Summary
Power Resumable 1 Services Device Clocks Core Clocks State Description
Management
Snoops Retained
State Name
Full On NA Y Y Y Y The core
referred to is
currently not in
the
STANDBYWFI
(PW15) state.
STANDBYWFI Y Y Y N Y The core
(PW15) referred to is
currently in the
STANDBYWFI
(PW15) state.
PH20 Y N Y N Y
1. A resumable power state in the core indicates that the core can exit from a power managed state and return to Full On
without the core(s) being reset.
Table 14-3 summarizes the device RCPM modes.
Table 14-3. Device Power Management State Summary
Power Resumable 1 Services Device Clocks Core Clocks Description
Management
Snoops
State Name
Full On NA Y Y Y Platform clock to all
modules is not
gated.
LPM20 Y N N N Platform clock to all
modules is gated
off.
SWLPM20 Y N N N (WFI) Platform clock to all
modules is gated
off.
1. A resumable power state for the device indicates that the device can exit from a power managed state and return to Full
On without the device being reset.
14.1.5 Modes Entry and Exit for Power Management
Table 14-4 summarizes the entry and exit for the core power management modes.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
632 NXP Semiconductors
Chapter 14 Run Control and Power Management (RCPM)
Table 14-4. Core and Cluster Power Management States: Entry and Exit
Power Entry via ... Exit via ...
Management
Temporary exit Permanent exit
State Name
STANDBYWFI • Core Executes WFI (wait for • A snoop request that • Core warm reset or any
(PW15) interrupt) instruction. must be serviced by the device-level reset
core L1 data cache. • Any interrupt request.1
• A cache or TLB • A core debug halt request.2
maintenance operation • Debug interrupt without
that must be serviced by masking
the core L1 instruction • Wake on IRQ[0-11]
cache, data cache, or • Wake on software interrupt
TLB. • Wake on peripheral
• A core debug halt interrupt
request. • Wake on HRESET
• An APB access to the • Wake on PORESET
debug or trace registers • Wake on debug halt
residing in the core • Wake on debug interrupt
power domain.
PH20 • Privileged software set The following core wake up
corresponding bit in RCPM events will unconditionally wake
PCPH20SETR to 1. up core from power management
state via core_wakeup_req
Core PH20 (PGSR) operation can be signal.
triggered by the following mechanism:
• GIC core warm reset
1. Set CPUECTLR[2:0] CPU request deassertion
retention control to a non-zero • Core debug halt request
value. Refer Arm® Cortex®-A53 • Debug interrupt without
Technical Reference Manual for masking
more information. • Wake on IRQ[0-11]
2. Set CPUECTLR[6] SMPEN to • Wake on peripheral
1.The cluster power interrupt
management controller uses the • Wake on HRESET
state of this bit to decide whether • Wake on PORESET
to put the core into retention • Wake on debug halt
(equals to one) or • Wake on debug interrupt
powerdown(equals to zero). • Wake on interrupt with
3. Write to generic timer control clearing PCPH20REQ in
register SYS_Counter_CNTCR register PCPH20CLRR
to enable the Arm counter • Wake on FlexTimer
CNTVALUEB[63:0]. interrupt, if programmed
4. Write to generic timer control • Wake on IIC interrupt, IIC
register SYS_Counter_CNTCR slave address matching, if
to enable the Arm counter programmed
CNTVALUEB[63:0] • Wake on UART interrupt,
5. Set the RETREQn bit of UART data reception, if
corresponding core in programmed
SCFG_RETREQCR register for • Wake on IRQ0 and IRQ2, if
RETENTION_REQ_EN at programmed
arm_cluster to be set.
6. Set the PC_PH20_REQ bit in
RCPM_PCPH20SETR register
through Software.
7. Execute WFI Instruction of the
Core.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 633
Introduction
Table 14-4. Core and Cluster Power Management States: Entry and Exit
Power Entry via ... Exit via ...
Management
Temporary exit Permanent exit
State Name
8. COP sends RETENTION_REQ
and waits for RETENTION
output from the core.
9. When RETENTION signal is
asserted at COP boundary, Core
state machine moves to PH20
state.
10. RCPM_PCPH20SR register
corresponding bit should get set.
1. Interrupts may still be masked in the GIC. Masking in the GIC prevents interrupt delivery to the core and therefore does not
cause an exit.
2. For a core debug halt request to cause an exit from power management mode, the core must be operating at a frequency
greater than the platform frequency.
NOTE
The power management states of A53 core can be achieved
with the software sequence only without the RCPM interaction.
The registers given below provides the different status of A53
core:
• TWAITSR0: Status shows core is in the WFI state
• POWMGTCSR: LPM20 request and status
Table 14-5 summarizes the entry and exit for the device power management modes.
Table 14-5. Device RCPM Mode: Entry and Exit for Power Management
Device Power Management State Entry via ... Exit via ...
Name
LPM20 LPM20 operation can be triggered by the • Wake on all FMan MACs - Magic
following mechanism: Packet, if programmed
• Wake on IIC1, if programmed
• Set CPUECTLR[2:0] CPU
• Wake on LPUART1, if
retention control to a non-zero
programmed
value.
• Wake on FlexTimer1, if
• Set CPUECTLR[6] SMPEN to 1.
programmed
The cluster power management
• Wake on GPIO, if programmed
controller uses the state of this bit
• Wake on FMan, if programmed
to decide whether to put the core
• Wake on IRQ pins
into retention (equals to one) or
• PORESET
powerdown(equals to zero).
• Write to generic timer CNCTR
register to enable the Arm counter
CNTVALUEB[63:0].
• Set the
SCFG_COREPMCR[WFIL2].
• Set the
SCFG_RETREQCR[RETREQn] of
corresponding core for
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
634 NXP Semiconductors
Chapter 14 Run Control and Power Management (RCPM)
Table 14-5. Device RCPM Mode: Entry and Exit for Power Management
Device Power Management State Entry via ... Exit via ...
Name
RETENTION_REQ_EN at
Arm_cluster to be set.
• Set
RCPM_POWMGTCSR[LPM20_R
EQ].
• Execute WFI instruction on each
core.
After these programming ASLEEP pin
should get asserted.
NOTE: When any core is in the WFI
state, the device cannot be
configured in the LPM20 state
until the core comes out of the
WFI state. To configure the
device in sleep state (LPM20)
when some cores are already in
the WFI state, the software
should first bring the cores out
of WFI through software-
generated interrupt. It should
then wait for the interrupt to be
cleared and the WFI status bits
to be cleared in the
SCFG_LPMCSR register before
following the LPM20 sequence
to put the device in sleep state.
NOTE: When cores(core) are in boot
hold-off state, the device cannot
be put in sleep state. To follow
the LPM20 sequence in such
cases, these cores should be
first brought out from the boot
hold-off states.
14.1.5.1 SWLPM20 Entry Sequence – System Software
The system software is responsible for performing the following actions:
1. Software quiesces all external devices/internal modules through configuration. This
ensures that no master or peripheral (for example I2C, UART, WDOG, FlexTimer,
and eSDHC) is active while the device is attempting to enter LPM20. For system
implementations running on Linux, this is typically covered by the Linux drivers of
these peripherals. However, if standard system software is not used, this process to
quiesce the device must be implemented.
2. The modules which are not to be powered down are listed in IPPDEXPCR. (This
action is typically performed by standard Linux).
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 635
Introduction
3. Redirect LPM20 wake-up conditions/interrupts to core 0. Note that for systems that
are running Linux, the kernel may already perform this function of redirecting all
interrupts to core 0. All of the secondary cores (other than the last active core, core 0)
will no longer be available after the next step.
4. Put the secondary cores (other than the last active core, core 0) into WFI state
through PSCI.
5. Wake from LPM20 due to PCI express events is only supported by a side band signal
which is connected to IRQ or GPIO only. Other LPM20 exit conditions are listed in
section Table 14-5.
6. The last core calls the PSCI function CPU_SUSPEND[system.power-down], which
implements the LPM20 sequence.
14.1.5.2 SWLPM20 Device Specific Entry and Exit Sequence
The detailed SWLPM20 entry and exit sequence for the device is as follows:
NOTE
The code must be executed at EL3.
1. Mask interrupts at the core (DAIF = 0x3C0).
2. Disable D-Cache. Clear C bit in SCTLR_EL3 (Arm core register).
3. Invalidate/cln L1 D-Cache.
4. Set WFIL2_EN in COREPMCR.
5. Write (32-bit) 0x80000000 to address 0x20170000.
6. Set IRQ bit in SCR_EL3.
7. Read (32-bit) IPPDEXPCR0 @ 0x01EE2140
• if IPPDEXPCR[3] = 1, exclusion_mask_1 = 0x00000080
• if IPPDEXPCR[19] = 1, exclusion_mask_2 |= 0x00000002
• if IPPDEXPCR[18] = 1, exclusion_mask_2 |= 0x00020000
• if IPPDEXPCR[17] = 1, exclusion_mask_2 |= 0x00000400
• if IPPDEXPCR[16] = 1, exclusion_mask_2 |= 0x02000000
• if IPPDEXPCR[6] = 1, exclusion_mask_2 |= 0x00400000
exclusion_mask_2 indicate those modules which are already disabled.
8. Write (32-bit) 0xA000C201 to address 0x20170008.
9. If exclusion_mask_1 is 0, write (32-bit) the value 0x00000080 to address
0x2017000C.
10. Write (32-bit) the value 0x000C0000 to address 0x20170010.
11. Write (32-bit) the value 0x38000000 to address 0x20170014.
12. Write (32-bit) the value (0x10A33BFC &~exclusion_mask_2) to address
0x20170028.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
636 NXP Semiconductors
Chapter 14 Run Control and Power Management (RCPM)
13. Read (32-bit) address 0x20170018. Poll this address until the value 0xA000C201 is
read.
14. If exclusion_mask_1 is 0, read/poll (32-bit) on address 0x2017001C until the value
0x00000080 is returned.
15. Read (32-bit) address 0x20170020. Poll this address until the value 0x000C0000 is
returned.
16. Read (32-bit) address 0x20170024. Poll this address until the value 0x38000000 is
returned.
17. Read (32-bit) address 0x2017002C. Poll this address until the value (0x10A33BFC
&~exclusion_mask_2) is returned .
exclusion_mask_2 indicate modules which are already disabled.
18. Save the value of register DEVDISR1 and write (32-bit) the new value of
0xA0C3C201 to address 0x01EE0070.
19. Save the value of register DEVDISR2 and write (32-bit) the new value of
(0xCC0C0080 &~exclusion_mask_1) to address 0x01EE0074.
exclusion_mask_2 indicates module which are already disabled.
20. Save the value of register DEVDISR3 and write (32-bit) the new value of
0xE00C0000 to address 0x01EE0078.
21. Save the value of register DEVDISR4 and write (32-bit) the new value of
0x38000000 to address 0x01EE007C.
22. Save the value of register DEVDISR5 and write (32-bit) the new value of
(0x10A33BFC &~exclusion_mask_2) to address 0x01EE0080.
23. Disable data pre-fetch in Arm core register CPUACTLR_EL1.
24. Set register DDR_TIMING_CFG_4 bits [2:0] = 0x2.
NOTE
The following sequence pre-fetches lines into the
instruction cache for execution. This is necessary because
DDR is going into self-refresh, and the clock to the DDR
controller will be stopped. The code is shown below.
// On input, the following registers are loaded with the specified values:
// w13 = original contents of DEVDISR1
// w14 = original contents of DEVDISR2
// w15 = original contents of DEVDISR3
// w16 = original contents of DEVDISR4
// w17 = original contents of DEVDISR5
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 637
Introduction
The general algorithm to shut down the DDR controller clock is provided below, this
is implemented in the AArch64 assembly language code:
• Load all instructions into the I-Cache so there are no fetches from DDR (D-
Cache has already been disabled).
• Put DDR into self-refresh.
• Request that the DDR controller interface complete all the transactions (quiesce).
• Poll until DDR controller interface is quiescent.
• Stop the clock to the DDR controller.
• Put the core into WFI.
• On exiting WFI, unwind the above.
• If retry count is exceeded while polling for the DDR controller interface to
quiesce; put DDR out of self refresh and exit with an error.
// 4Kb aligned - prevents taking a page fault in the middle
.align 12
mov x0, xzr // initialize x0=0 (cache prefetch control)
b touch_line_0 // prefetches first cache line
start_line_0:
mov x0, #1 // turn off cache line prefetch
mov x2, 0x80000000 // put ddr in self-refresh - start
ldr w3, [0x01080114]
rev w4, w3
orr w4, w4, w2
rev w3, w4
str w3, [0x01080114] // put ddr in self refresh - end
orr w3, w5, 0x80000000 // request ddr cntlr interface quiesce - start
rev w4, w3
str w4, [0x20170028] // request ddr cntlr interface quiesce - end
mov w3, 0x80000000
rev w3, w3
mov x2, 0x10000 // retry count for ddr cntlr interface polling
touch_line_0:
cbz x0, touch_line_1 // prefetches second cache line when x0=0
start_line_1:
ldr w1, [0x2017002C] // poll on ddr cntlr quiesce ack
tst w1, w3
b.ne 1f // ddr cntlr is quiescent, proceed
subs x2, x2, #1
b.gt start_line_1 // loop back and try again
rev w4, w5 // timeout error on reaching here
str w4, [0x20170028] // deassert the ddr cntlr quiesce request
mov x0, #-1 // load error code
b 2f // finish cleanup
1:
str w4, [0x01EE0080] // disable ddr cntrlr clk
wfi // power-down core
rev w4, w5
str w4, [0x01EE0080] // re-enable ddr cntlr clock
str w4, [0x20170028] // deassert the ddr cntlr quiesce request
nop
touch_line_1:
cbz x0, touch_line_2 // prefetches third cache line when x0=0
start_line_2:
ldr w1, [0x2017002C]
tst w1, w3
b.eq 2f
nop
b start_line_2
2:
mov x2, 0x80000000
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
638 NXP Semiconductors
Chapter 14 Run Control and Power Management (RCPM)
ldr w3, [0x01080114]
rev w4, w3
bic w4, w4, w2
rev w3, w4
mov x1, 0x10000 // ddr clock restart delay count
3:
subs x1, x1, #1
b.gt 3b // delay for ddr clock to restart
str w3, [0x01080114] // take ddr out-of self refresh
nop
touch_line_2:
cbz x0, touch_line_3 // prefetches fourth cache line when x0=0
start_line_3:
str w17, [0x01EE0080] // reload DEVDISR5
str w16, [0x01EE007C] // reload DEVDISR4
str w15, [0x01EE0078] // reload DEVDISR3
str w14, [0x01EE0074] // reload DEVDISR2
str w13, [0x01EE0070] // reload DEVDISR1
str wzr, [0x20170028] // deassert ip block quiesce request
str wzr, [0x20170014] // deassert ip block quiesce request
str wzr, [0x20170010] // deassert ip block quiesce request
str wzr, [0x2017000C] // deassert ip block quiesce request
str wzr, [0x20170008] // deassert ip block quiesce request
nop
nop
nop
nop
b continue_restart // ddr is now functional, can leave cache-only region
touch_line_3:
cbz x0, start_line_0 // begin executing SWLPM20 sequence from cache
// execute here after ddr is back up
continue_restart:
25. write (32-bit) 0x0 to address 0x20170000.
26. write (32-bit) 0x0 to address 0x0157042C (clear WFIL2_EN in COREPMCR).
14.1.6 Power Management States
This section provides functional explanation of the power management states
summarized in the previous sections.
The privileged software can place the device in one of the following power states:
• STANDBYWFI (PW15) state
• PH20 (core retention)
Table 14-6. Power state entry by register
State Register
core PH20 PCPH20SETR
• LPM20 (sleep)
• SWLPM20 (sleep)
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 639
Introduction
14.1.6.1 STANDBYWFI (PW15) State
In STANDBYWFI (PW15) state, the core internally gates clocks within the core,
significantly reducing the power consumption of the core. Snooping of the L1 and L2 are
still supported and thus the data in the data cache is kept coherent. Interrupts directed to
the Core are monitored by the GIC and cause core to exit from STANDBYWFI (PW15)
state to allow the core to recognize and process the interrupt. STANDBYWFI (PW15)
state is entered through execution of wait for interrupt instruction from the core.
The watchdog timer facilities are still enabled during STANDBYWFI (PW15) state.
14.1.6.2 PH20 State
Core PH20 state is core power gating with state retention.
14.1.6.3 LPM20 State
LPM20 is a device low power state. Prior entering LPM20, software is expected to
quiesce all external devices/internal IPs through configuration. RCPM hardware is
designed to implement sanity check for IPs idle status.
In LPM20 state, all cores and clusters are placed in their lowest power managed state -
PH20. All other device modules in chip are clock gated, except I2C, GPIO, IRQ, UART,
and FlexTimer so that only those modules which are required to wake up the device will
still have a running clock.
The following figure describes the sleep flow for the chip.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
640 NXP Semiconductors
Chapter 14 Run Control and Power Management (RCPM)
Normal Run Mode 0
S/W preparations 1
SW : Set LPM20 2 Any Interrupt after
this line will take the
flow back to 0
Core
SW : Core WFI step for each core 3
A53
4
STAND BY WFI / STAND_BY_WFI_L2
RETENTION Device and core PM SM started 5
7
SoC Glue
Core PM Requests
PW15, PH20
6
RETENTION_REQ THRD HALTED
Normal device PM operations :
8
stop/stop_ack for M, T, MT, RIO
Core PMSM : PH20_REQ
9
CORE PM
PH20 CORE PM
LPM20 10
Figure 14-1. Device LPM20 operation sequence
14.1.6.4 SWLPM20 State
SWLPM20 is a device low power state. Prior entering SWLPM20, software is expected
to quiesce all external devices/internal IPs through configuration. RCPM hardware is
designed to implement sanity check for IPs idle status.
In SWLPM20 state, all cores and clusters are placed in their lowest power managed state
- PW15. All other device modules in chip are clock gated, except GPIO, IRQ,
LPUART1, FlexTimer, DDR, FMAN_MAC3, and, FMAN_MAC4 so that only those
modules which are required to wake up the device will still have a running clock.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 641
External Signal Description
14.1.7 Reset modes
This section describes the relationship between power management states and reset
modes.
14.1.7.1 Power-On Reset and Hard Reset States
During power-on reset and hard reset, the following hardware structures are reset:
• All CCSR registers
• SoC power management state machine
• Core power management state machine
• Cluster power management state machine
14.2 External Signal Description
The table below provides the signal description of power management signals:
Table 14-7. RCPM Detailed Signal Descriptions
Signal I/ Description
O
ASLEEP O Asleep. After negation of PORESET, ASLEEP is asserted until the device completes its power-on reset
sequence and reaches its ready state.
State Asserted- Indicates that the device is either still in its power-on reset sequence or it has
Meaning reached a LPM20 (sleep) state after a power-down command is issued by software.
Negated- The device is not in LPM20 (sleep) state. (It has either awake from a power-down
state, or has completed the POR sequence.)
Timing Assertion- May occur at any time; may be asserted asynchronously to the input clocks.
Negation- Negates synchronously with SYSCLK when leaving power-on sequence; otherwise
negation is asynchronous.
RTC I Real Time Clock. Refer to the hardware specification of device for timing specification. The signal can be
optionally use to clock the global timers in the programmable interrupt controller.
Timing Assertion/Negation - See the hardware specification of device for specific timing information
for this signal.
14.3 RCPM Memory Map/Register Definition
This section identifies power management resources that are not included as part of a
processor core or platform IP.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
642 NXP Semiconductors
Chapter 14 Run Control and Power Management (RCPM)
RCPM memory map
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
1EE_204C Thread Wait status Register (RCPM_TWAITSR) 32 R 0000_0000h 14.3.1/643
1EE_20D0 Physical Core PH20 Status Register (RCPM_PCPH20SR) 32 R 0000_0000h 14.3.2/644
Physical Core PH20 Set Control Register
1EE_20D4 32 R/W 0000_0000h 14.3.3/644
(RCPM_PCPH20SETR)
Physical Core PH20 Clear Control Register
1EE_20D8 32 w1c 0000_0000h 14.3.4/645
(RCPM_PCPH20CLRR)
Physical Core PH20 Previous Status Register
1EE_20DC 32 R 0000_0000h 14.3.5/647
(RCPM_PCPH20PSR)
Power Management Control and Status Register
1EE_2130 32 R/W 0000_0000h 14.3.6/647
(RCPM_POWMGTCSR)
IP Powerdown Exception Control Register
1EE_2140 32 R/W 0000_0000h 14.3.7/649
(RCPM_IPPDEXPCR)
1EE_215C nIRQOUT interrupt mask register (RCPM_nIRQOUTR) 32 R/W 0000_0000h 14.3.8/651
1EE_216C nFIQOUT Interrupt Register (RCPM_nFIQOUTR) 32 R/W 0000_0000h 14.3.9/651
14.3.1 Thread Wait status Register (RCPM_TWAITSR)
This register is used for reporting wait status per core.
Address: 1EE_2000h base + 4Ch offset = 1EE_204Ch
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R T31_T0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RCPM_TWAITSR field descriptions
Field Description
0–31 Core STANDBYWFI (PW15) Status.
T31_T0
NOTE: Bit 31 corresponds to core 0, bit 30 corresponds to core 1, and so on.
0 Core is not in the STANDBYWFI (PW15) state
1 Core is in the STANDBYWFI (PW15) state
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 643
RCPM Memory Map/Register Definition
14.3.2 Physical Core PH20 Status Register (RCPM_PCPH20SR)
This register is used for reporting PH20 status per physical core.
Address: 1EE_2000h base + D0h offset = 1EE_20D0h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R PCn
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RCPM_PCPH20SR field descriptions
Field Description
0–31 Physical core PH20 status.
PCn
NOTE: Bit 31 corresponds to Core 0, bit 30 corresponds to Core 1, and so on.
0 Physical core is not in its PH20 state
1 Physical core is in its PH20 state
14.3.3 Physical Core PH20 Set Control Register
(RCPM_PCPH20SETR)
This register is used for requesting that a physical core be placed in the PH20 state. The
true value read from the register means there is a pending physical core PH20 request.
NOTE
The RCPM module as implemented on the chip describes the
cores that are implemented on the chip. In the following register
description, any bits associated with unimplemented cores are
reserved.
Address: 1EE_2000h base + D4h offset = 1EE_20D4h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
PC_PH20_REQ
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RCPM_PCPH20SETR field descriptions
Field Description
0–31 Write one to trigger physical core PH20 request. This bit is clear by interrupt event or write-one event on
PC_PH20_REQ PCPH20CLRRn register.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
644 NXP Semiconductors
Chapter 14 Run Control and Power Management (RCPM)
RCPM_PCPH20SETR field descriptions (continued)
Field Description
xxxxxxxx_xxxxxxxx_xxxxxxxx_xxxxxxx1 Request to put physical core 0 in PH20 state.
xxxxxxxx_xxxxxxxx_xxxxxxxx_xxxxxx1x Request to put physical core 1 in PH20 state.
xxxxxxxx_xxxxxxxx_xxxxxxxx_xxxxx1xx Request to put physical core 2 in PH20 state.
xxxxxxxx_xxxxxxxx_xxxxxxxx_xxxx1xxx Request to put physical core 3 in PH20 state.
xxxxxxxx_xxxxxxxx_xxxxxxxx_xxx1xxxx Request to put physical core 4 in PH20 state.
xxxxxxxx_xxxxxxxx_xxxxxxxx_xx1xxxxx Request to put physical core 5 in PH20 state.
xxxxxxxx_xxxxxxxx_xxxxxxxx_x1xxxxxx Request to put physical core 6 in PH20 state.
xxxxxxxx_xxxxxxxx_xxxxxxxx_1xxxxxxx Request to put physical core 7 in PH20 state.
xxxxxxxx_xxxxxxxx_xxxxxxx1_xxxxxxxx Request to put physical core 8 in PH20 state.
xxxxxxxx_xxxxxxxx_xxxxxx1x_xxxxxxxx Request to put physical core 9 in PH20 state.
xxxxxxxx_xxxxxxxx_xxxxx1xx_xxxxxxxx Request to put physical core 10 in PH20 state.
xxxxxxxx_xxxxxxxx_xxxx1xxx_xxxxxxxx Request to put physical core 11 in PH20 state.
xxxxxxxx_xxxxxxxx_xxx1xxxx_xxxxxxxx Request to put physical core 12 in PH20 state.
xxxxxxxx_xxxxxxxx_xx1xxxxx_xxxxxxxx Request to put physical core 13 in PH20 state.
xxxxxxxx_xxxxxxxx_x1xxxxxx_xxxxxxxx Request to put physical core 14 in PH20 state.
xxxxxxxx_xxxxxxxx_1xxxxxxx_xxxxxxxx Request to put physical core 15 in PH20 state.
xxxxxxxx_xxxxxxx1_xxxxxxxx_xxxxxxxx Request to put physical core 16 in PH20 state.
xxxxxxxx_xxxxxx1x_xxxxxxxx_xxxxxxxx Request to put physical core 17 in PH20 state.
xxxxxxxx_xxxxx1xx_xxxxxxxx_xxxxxxxx Request to put physical core 18 in PH20 state.
xxxxxxxx_xxxx1xxx_xxxxxxxx_xxxxxxxx Request to put physical core 19 in PH20 state.
xxxxxxxx_xxx1xxxx_xxxxxxxx_xxxxxxxx Request to put physical core 20 in PH20 state.
xxxxxxxx_xx1xxxxx_xxxxxxxx_xxxxxxxx Request to put physical core 21 in PH20 state.
xxxxxxxx_x1xxxxxx_xxxxxxxx_xxxxxxxx Request to put physical core 22 in PH20 state.
xxxxxxxx_1xxxxxxx_xxxxxxxx_xxxxxxxx Request to put physical core 23 in PH20 state.
xxxxxxx1_xxxxxxxx_xxxxxxxx_xxxxxxxx Request to put physical core 24 in PH20 state.
xxxxxx1x_xxxxxxxx_xxxxxxxx_xxxxxxxx Request to put physical core 25 in PH20 state.
xxxxx1xx_xxxxxxxx_xxxxxxxx_xxxxxxxx Request to put physical core 26 in PH20 state.
xxxx1xxx_xxxxxxxx_xxxxxxxx_xxxxxxxx Request to put physical core 27 in PH20 state.
xxx1xxxx_xxxxxxxx_xxxxxxxx_xxxxxxxx Request to put physical core 28 in PH20 state.
xx1xxxxx_xxxxxxxx_xxxxxxxx_xxxxxxxx Request to put physical core 29 in PH20 state.
x1xxxxxx_xxxxxxxx_xxxxxxxx_xxxxxxxx Request to put physical core 30 in PH20 state.
1xxxxxxx_xxxxxxxx_xxxxxxxx_xxxxxxxx Request to put physical core 31 in PH20 state.
14.3.4 Physical Core PH20 Clear Control Register
(RCPM_PCPH20CLRR)
This register is used for waking up the core placed in the PH20 state. The true value read
from the register only means there is a pending physical core PH20 request.
NOTE
The RCPM module as implemented on the chip describes the
cores that are implemented on the chip. In the following register
description, any bits associated with unimplemented cores are
reserved.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 645
RCPM Memory Map/Register Definition
Address: 1EE_2000h base + D8h offset = 1EE_20D8h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R CP_PH20_REQ
W w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RCPM_PCPH20CLRR field descriptions
Field Description
0–31 Write one to cancel physical core PH20 request. The bit is set by write-one-event to PCPH20SETR
CP_PH20_REQ register. This bit is also clear by interrupt event. The read true value of the register bit means there is
pending Physical Core PH20 request for that core.
xxxxxxxx_xxxxxxxx_xxxxxxxx_xxxxxxx1 core0 is receiving a PH20 request from PCPH20SETR
xxxxxxxx_xxxxxxxx_xxxxxxxx_xxxxxx1x core1 is receiving a PH20 request from PCPH20SETR
xxxxxxxx_xxxxxxxx_xxxxxxxx_xxxxx1xx core2 is receiving a PH20 request from PCPH20SETR
xxxxxxxx_xxxxxxxx_xxxxxxxx_xxxx1xxx core3 is receiving a PH20 request from PCPH20SETR
xxxxxxxx_xxxxxxxx_xxxxxxxx_xxx1xxxx core4 is receiving a PH20 request from PCPH20SETR
xxxxxxxx_xxxxxxxx_xxxxxxxx_xx1xxxxx core5 is receiving a PH20 request from PCPH20SETR
xxxxxxxx_xxxxxxxx_xxxxxxxx_x1xxxxxx core6 is receiving a PH20 request from PCPH20SETR
xxxxxxxx_xxxxxxxx_xxxxxxxx_1xxxxxxx core7 is receiving a PH20 request from PCPH20SETR
xxxxxxxx_xxxxxxxx_xxxxxxx1_xxxxxxxx core8 is receiving a PH20 request from PCPH20SETR
xxxxxxxx_xxxxxxxx_xxxxxx1x_xxxxxxxx core9 is receiving a PH20 request from PCPH20SETR
xxxxxxxx_xxxxxxxx_xxxxx1xx_xxxxxxxx core10 is receiving a PH20 request from PCPH20SETR
xxxxxxxx_xxxxxxxx_xxxx1xxx_xxxxxxxx core11 is receiving a PH20 request from PCPH20SETR
xxxxxxxx_xxxxxxxx_xxx1xxxx_xxxxxxxx core12 is receiving a PH20 request from PCPH20SETR
xxxxxxxx_xxxxxxxx_xx1xxxxx_xxxxxxxx core13 is receiving a PH20 request from PCPH20SETR
xxxxxxxx_xxxxxxxx_x1xxxxxx_xxxxxxxx core14 is receiving a PH20 request from PCPH20SETR
xxxxxxxx_xxxxxxxx_1xxxxxxx_xxxxxxxx core15 is receiving a PH20 request from PCPH20SETR
xxxxxxxx_xxxxxxx1_xxxxxxxx_xxxxxxxx core16 is receiving a PH20 request from PCPH20SETR
xxxxxxxx_xxxxxx1x_xxxxxxxx_xxxxxxxx core17 is receiving a PH20 request from PCPH20SETR
xxxxxxxx_xxxxx1xx_xxxxxxxx_xxxxxxxx core18 is receiving a PH20 request from PCPH20SETR
xxxxxxxx_xxxx1xxx_xxxxxxxx_xxxxxxxx core19 is receiving a PH20 request from PCPH20SETR
xxxxxxxx_xxx1xxxx_xxxxxxxx_xxxxxxxx core20 is receiving a PH20 request from PCPH20SETR
xxxxxxxx_xx1xxxxx_xxxxxxxx_xxxxxxxx core21 is receiving a PH20 request from PCPH20SETR
xxxxxxxx_x1xxxxxx_xxxxxxxx_xxxxxxxx core22 is receiving a PH20 request from PCPH20SETR
xxxxxxxx_1xxxxxxx_xxxxxxxx_xxxxxxxx core23 is receiving a PH20 request from PCPH20SETR
xxxxxxx1_xxxxxxxx_xxxxxxxx_xxxxxxxx core24 is receiving a PH20 request from PCPH20SETR
xxxxxx1x_xxxxxxxx_xxxxxxxx_xxxxxxxx core25 is receiving a PH20 request from PCPH20SETR
xxxxx1xx_xxxxxxxx_xxxxxxxx_xxxxxxxx core26 is receiving a PH20 request from PCPH20SETR
xxxx1xxx_xxxxxxxx_xxxxxxxx_xxxxxxxx core27 is receiving a PH20 request from PCPH20SETR
xxx1xxxx_xxxxxxxx_xxxxxxxx_xxxxxxxx core28 is receiving a PH20 request from PCPH20SETR
xx1xxxxx_xxxxxxxx_xxxxxxxx_xxxxxxxx core29 is receiving a PH20 request from PCPH20SETR
x1xxxxxx_xxxxxxxx_xxxxxxxx_xxxxxxxx core30 is receiving a PH20 request from PCPH20SETR
1xxxxxxx_xxxxxxxx_xxxxxxxx_xxxxxxxx core31 is receiving a PH20 request from PCPH20SETR
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
646 NXP Semiconductors
Chapter 14 Run Control and Power Management (RCPM)
14.3.5 Physical Core PH20 Previous Status Register
(RCPM_PCPH20PSR)
This register is used for reporting previous PH20 status per physical core. It is used by
software to know which power saving state it was in before wake up by interrupt.
Address: 1EE_2000h base + DCh offset = 1EE_20DCh
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R PC_P_PH20_n
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RCPM_PCPH20PSR field descriptions
Field Description
0–31 Physical core PH20 previous status. The bit is set when the corresponding PCPH20SR bit transitions from
PC_P_PH20_n 1 to 0 due to an interrupt.
NOTE: Bit 31 corresponds to Core 0, bit 30 corresponds to Core 1, and so on.
0 Physical core was not in the PH20 state before wake up by interrupt.
1 Physical core was in the PH20 state before wake up by interrupt.
14.3.6 Power Management Control and Status Register
(RCPM_POWMGTCSR)
This register is used for entering the chip's LPM state. In addition, it provides status
indicating successful entry into the corresponding power management state.
The following table describes this register's bit settings.
Address: 1EE_2000h base + 130h offset = 1EE_2130h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
LPM20_REQ
Reserved
SD_ Reserv
Reserved Reserved
PD ed
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 647
RCPM Memory Map/Register Definition
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
P_LPM20_ST
LPM20_ST
Reserved
Reserved
Reserved
Reserved Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RCPM_POWMGTCSR field descriptions
Field Description
0 SerDes and Protocol Converter Powerdown Control
SD_PD
0 SerDes and Protocol Converter are not powerdown in LPM state.
1 SerDes and Protocol Converter are powerdown in LPM state for further power saving. If this bit is set,
after system wake up from LPM state, SerDes has to go through the training sequence to return back
to function.
1–10 This field is reserved.
- Reserved
11 LPM20 State Request. This bit is clear by interrupt event.
LPM20_REQ
0 No request to put chip in LPM20 state
1 Request to place chip in LPM20 state.
12–13 This field is reserved.
- Reserved
14 This field is reserved.
- Reserved
15–21 This field is reserved.
- Reserved
22 LPM20 Status
LPM20_ST
0 Device is not attempting to reach LPM20 state
1 The chip is attempting to enter LPM20 state because POWMGTCSR[LPM20_REQ] is set.
23 Previous LPM20 Status. It is used by software to know which state the chip was in before being wake up.
P_LPM20_ST Before software set POWMGTCSR[LPM20_REQ], software w1c [P_LPM20_ST] bit is expected.
0 Device was not in LPM20 state before being wake up by interrupt.
1 Device was in LPM20 state before being wake up by interrupt.
The bit is set when LPM20_ST transitions from 1 to 0 due to an interrupt.
The bit is w1c.
24–28 This field is reserved.
- Reserved
29 This field is reserved.
- Reserved
30 This field is reserved.
- Reserved
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
648 NXP Semiconductors
Chapter 14 Run Control and Power Management (RCPM)
RCPM_POWMGTCSR field descriptions (continued)
Field Description
31 This field is reserved.
- Reserved
14.3.7 IP Powerdown Exception Control Register
(RCPM_IPPDEXPCR)
IPPDEXPCR provides a mechanism for excluding certain IP blocks from device LPM20
mode to make these IP blocks available as sources for wake-up events. For example,
• Wake on LAN (magic packet) - Requires excluding the Ethernet controller from
device LPM20 mode
• Wake on GPIO - Requires excluding the GPIO controller from device LPM20 mode
Address: 1EE_2000h base + 140h offset = 1EE_2140h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FlexTimer1
LPUART1
OCRAM1
MAC1_1
MAC1_2
MAC1_3
MAC1_4
MAC1_5
MAC1_6
MAC1_9
Reserved Reserved I2C1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
GPIO1
Reserved Reserved FM1 Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RCPM_IPPDEXPCR field descriptions
Field Description
0 Frame Manager 1 MAC1 powerdown exception
MAC1_1
0 Frame Manager 1 MAC1 powerdown during device LPM20
1 Frame Manager 1 MAC1 is not powerdown during device LPM20
1 Frame Manager 1 MAC2 powerdown exception
MAC1_2
0 Frame Manager 1 MAC2 powerdown during device LPM20
1 Frame Manager 1 MAC2 is not powerdown during device LPM20
2 Frame Manager 1 MAC3 powerdown exception
MAC1_3
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 649
RCPM Memory Map/Register Definition
RCPM_IPPDEXPCR field descriptions (continued)
Field Description
0 Frame Manager 1 MAC3 powerdown during device LPM20
1 Frame Manager 1 MAC3 is not powerdown during device LPM20
3 Frame Manager 1 MAC4 powerdown exception
MAC1_4
0 Frame Manager 1 MAC4 powerdown during device LPM20
1 Frame Manager 1 MAC4 is not powerdown during device LPM20
4 Frame Manager 1 MAC5 powerdown exception
MAC1_5
0 Frame Manager 1 MAC5 powerdown during device LPM20
1 Frame Manager 1 MAC5 is not powerdown during device LPM20
5 Frame Manager 1 MAC6 powerdown exception
MAC1_6
0 Frame Manager 1 MAC6 powerdown during device LPM20
1 Frame Manager 1 MAC6 is not powerdown during device LPM20
6–7 This field is reserved.
- Reserved
8 Frame Manager 1 MAC9 powerdown exception
MAC1_9
0 Frame Manager 1 MAC9 powerdown during device LPM20
1 Frame Manager 1 MAC9 is not powerdown during device LPM20
9–11 This field is reserved.
- Reserved
12 I2C1 powerdown exception
I2C1
0 I2C1 powerdown during device LPM20
1 I2C1 is not powerdown during device LPM20
13 LPUART1 powerdown exception
LPUART1
0 LPUART1 powerdown during device LPM20
1 LPUART1 is not powerdown during device LPM20
14 FlexTimer1 powerdown exception
FlexTimer1
0 FlexTimer1 powerdown during device LPM20
1 FlexTimer1 is not powerdown during device LPM20
15 OCRAM1 powerdown exception
OCRAM1
0 OCRAM 1 powerdown during device LPM20
1 OCRAM 1 is not powerdown during device LPM20
16–24 This field is reserved.
- Reserved
25 GPIO powerdown exception
GPIO1
0 GPIO powerdown during device LPM20
1 GPIO is not powerdown during device LPM20
26–27 This field is reserved.
- Reserved
28 Frame Manager 1 powerdown exception.
FM1
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
650 NXP Semiconductors
Chapter 14 Run Control and Power Management (RCPM)
RCPM_IPPDEXPCR field descriptions (continued)
Field Description
0 FM1 powerdown during device LPM20
1 FM1 is not powerdown during device LPM20
29–31 This field is reserved.
- Reserved
14.3.8 nIRQOUT interrupt mask register (RCPM_nIRQOUTR)
The register masks the nIRQOUT Interrupt from GIC-400 for Sleep/LPM20 mode.
Address: 1EE_2000h base + 15Ch offset = 1EE_215Ch
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
IM0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RCPM_nIRQOUTR field descriptions
Field Description
0–31 Interrupt mask core 0-31.
IM0
NOTE: Bit 31 corresponds to Core 0, bit 30 corresponds to Core 1, and so on.
14.3.9 nFIQOUT Interrupt Register (RCPM_nFIQOUTR)
The register masks the nFIQOUT interrupt from GIC-400 for Sleep/LPM20 mode. The
LPM20 FSM (and software sequence in case of SWLPM20) recognizes the
corresponding core interrupt from GIC-400 and initiates a wake-up sequence provided
the interrupt mask is not set.
Address: 1EE_2000h base + 16Ch offset = 1EE_216Ch
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
IM0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RCPM_nFIQOUTR field descriptions
Field Description
0–31 Interrupt mask core 0-31.
IM0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 651
RCPM functional description
RCPM_nFIQOUTR field descriptions (continued)
Field Description
NOTE: Bit 31 corresponds to Core 0, bit 30 corresponds to Core 1, and so on.
14.4 RCPM functional description
The RCPM supports minimizing the power consumption through software controlled
power management states - PH20for individual cores (STANDBYWFI (PW15)) and the
device (LPM20).
RCPM can handshake with various IP at the SoC level to gracefully stop the IP traffic
and direct the memory controller to put DDR into self-refresh mode (if enabled).
The RCPM allows several wake-up event sources to exit low power state (internal timer,
internal and external interrupts).
The wake-up events are mapped to interrupt controller interrupts to generate a wake-up
interrupt to the core. For information on operation entry or exit, refer Modes Entry and
Exit for Power Management.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
652 NXP Semiconductors
Chapter 15
QUICC Engine Block
15.1 Introduction
The QUICC Engine™ Block Reference Manual with Protocol Interworking (QEIWRM)
describes all the functional units of the QUICC Engine block and must be used in
conjunction with this device manual and this chapter.
The QEIWRM is a superset manual which includes some information not relevant to the
device. This chapter serves as both a general overview of the QUICC Engine block and a
guide to the specific implementation of the QUICC Engine block on the device.
• QUICC Engine block, gives a general overview of the QUICC Engine architecture
and communication peripherals.
• QUICC Engine implementation details, lists the chapters that do apply.
Implementation-specific details for some chapters follow.
15.2 QUICC Engine block
NOTE
Based on the microcode RAM package that is used, some of the
features listed below may not be applicable. See the table below
for the different features offered in each microcode
configuration.
The QUICC Engine is a versatile communications complex that integrates several
communications peripheral controllers. It provides on-chip system design for a variety of
applications, particularly in communications and networking systems. The QUICC
Engine has the following features:
• 32-bit RISC controller for flexible support of the communications peripherals
• Serial DMA channel for receive and transmit on all serial channels
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 653
QUICC Engine implementation details
• Universal communication controllers (UCCs) supporting the following protocols and
interfaces (not all of them simultaneously):
• HDLC and Transparent controllers up to 50 Mbit/s full-duplex; HDLC bus up to
10 Mbit/s
• UART and asynchronous HDLC
• BISYNC up to 2 Mbit/s
• UMCC
• TDM interfaces, with T1/E1/J1 serial interfaces
• 256 channels of HDLC/Transparent per UCC
• RAM-based microcode
The figure below shows the internal architecture and the interfaces provided by the
QUICC Engine block on the device. A RAM is used to store parameters for the RISC
engine. The instruction RAM is used to optionally run additional code.
QUICC Engine Block
TM
Accelerators One 32-bit RISCs Serial DMA
Baud Rate 16 K 24 K Interrupt
Generators IRAM MURAM Controller
UCC1 UCC3 UMCC
Time Slot Assigner
Communications Interfaces
Up to 2 E1/T1
(TDMA, TDMB)
Figure 15-1. QUICC Engine block architectural block diagram
15.3 QUICC Engine implementation details
The table below lists the chapters from the QUICC Engine™ Block Reference Manual
with Protocol Interworking (QEIWRM).
Not all chapters of the QEIWRM apply to this device and those that do apply may have
application differences. Use this overview section as a guide for these application
differences.
While using the QEIWRM, note this implementation-specific information in general:
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
654 NXP Semiconductors
Chapter 15 QUICC Engine Block
• Two UCCs available-UCC1 and UCC3
• Up to two TDM ports
• UMCC
The table below lists the chapters from the QUICC Engine Block Reference Manual with
Protocol Interworking (QEIWRM) and the chapters with implementation differences.
Table 15-1. QEIWRM chapters and implementation
Chapter Name Implementation
Part I, "Introduction"
System Interface Applies to this device
Refer System interface for implementation
Configuration Applies to this device
Refer Configuration for implementation
Multiplexing and Timers Applies to this device
Refer Multiplexing and timers for implementation
Part II, "Unified Communication Controllers (UCCs)"
Unified Communications Controllers (UCCs) Applies to this device
Refer Unified communications controllers (UCCs) for implementation
UCC for Fast Protocols Applies to this device
Refer UCC for fast protocols for implementation
UCC Ethernet Controller (UEC) Does not apply to this device
IEEE Standard 1588 Assist Does not apply to this device
UTOPIA POS Bus Controller (UPC) Does not apply to this device
ATM Adaptation Layer 2 Does not apply to this device
UCC POS Controller (UPOS) Does not apply to this device
ATM Controller AAL0, AAL1, and AAL5 Does not apply to this device
HDLC Controller Applies to this device
Refer HDLC controller for implementation
Transparent Controller Applies to this device
Refer Transparent controller for implementation
UCC for Slow Protocols Applies to this device
Refer UCC for slow protocols for implementation
UART Mode and Asynchronous HDLC Applies to this device
Refer UART mode and asynchronous HDLC for implementation
UCC UART PROFIBUS MODE Applies to this device.
Serial Peripheral Interface (SPI) Does not apply to this device
Universal Serial Bus Controller Does not apply to this device
BISYNC Mode Applies to this device
Refer BISYNC mode for implementation
Part III, "Time Division Multiplex Support (TDM)" 1
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 655
QUICC Engine implementation details
Table 15-1. QEIWRM chapters and implementation (continued)
Chapter Name Implementation
Serial Interface with Time-Slot Assigner Applies to this device
Refer Serial interface with time-slot assigner for implementation
Multi-Channel Controller (MCC) Does not apply to this device
Multi-Channel Controller on UCC (UMCC) Applies to this device
Refer Multi-channel controller on UCC (UMCC)
QUICC Multi-Channel Controller (QMC) Does not apply to this device
Point-to-Point Protocol (PPP) Does not apply to this device
Serial ATM Microcode Does not apply to this device
Inverse Multiplexing for ATM (IMA) Does not apply to this device
ATM AAL1 Circuit Emulation Service Does not apply to this device
Part IV, "Multiprotocol Interworking"
Frame Parse and Lookup Does not apply to this device
Interworking Introduction Does not apply to this device
Protocol Interworking Programming Model Does not apply to this device
Virtual Port Does not apply to this device
IP Reassembly Full Does not apply to this device
IPv4/UDP Header Compression Does not apply to this device
IPsec Microcode Package Does not apply to this device
Part V, "Switching Functionality"
Enhanced MSP Microcode Does not apply to this device
L2 Ethernet Switch Does not apply to this device
1. The TDM can only work with an external sync and external clock; other options are not supported.
The following subsections include device-specific details for the given chapters of the
QEIWRM.
15.3.1 System interface
Of the UCCs, only UCC1 and UCC3 are supported on the device.
The following features are not supported: USB, MCC, SPI2, Ethernet, and ATM.
On this device, only a system bus is supported; references to a secondary bus should be
disregarded. As such,
• In the "Bus Selection Mechanisms" subsection, references to the secondary bus
should be disregarded.
• In the "Serial DMA Status Register (SDSR)" subsection, the BER_2 bit is not
available and should be reserved.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
656 NXP Semiconductors
Chapter 15 QUICC Engine Block
• In the "Serial DMA Mode Register (SDMR)" subsection, BER_2_MSK and
SBER_2_MSK bits are not available and should be reserved.
• In the "Serial DMA Transfer Address Registers (SDTA1 and SDTA2)" and "Serial
DMA Transfer Communication Channel Number Registers (SDTM1 and SDTM2)"
subsections, references to the secondary bus should be disregarded.
15.3.1.1 System interface-data paths
In the "Data paths" subsection of the QEIWRM, use this Arm Cortex core information:
The figure below is a simplified block diagram that shows the data paths. The data paths
include a path from the SDMA system bus interface to targets connected to the Cache
coherent interconnect. block shown in the figure, is responsible for distribution of I/O
masters transactions to the various possible targets (such as the PCI Express or DDR
memory controller) based on the transaction's address. The SDMA channel must be
configured for big-endian byte ordering for accessing buffer data. The big-endian byte
ordering format is programmed in the receive and transmit bus mode registers associated
with the peripherals (UMCC). Refer to each protocol of these peripherals for
programming of this feature.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 657
QUICC Engine implementation details
Arm Cortex-A53
256 KB
L2
32 KB 32 KB cache
L1 L1
I-cache D-cache
Local bus Local bus Cache DDR External system
(32-bit data) memory SCFG_ALTCBAR coherent memory
interconnect DDR bus
controller controller
System bus
interface 1
QUICC EngineTM block
Multiuser
SDMA RISC
RAM
UCC1 UCC3
Figure 15-2. Data paths
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
658 NXP Semiconductors
Chapter 15 QUICC Engine Block
15.3.1.2 System interface-interrupt configuration
In the "Interrupt Configuration" subsection, use the figure below to show the QUICC
Engine interrupt structure.
UCC1
UCC3
QUICC Engine High
UCC1
QUICC Engine Low
UCC3
Interrupt
Controller
UMMC
SDMA
Figure 15-3. QUICC engine module interrupt structure
15.3.1.3 System interface-bus arbitration
The "Bus Arbitration" subsection should be disregarded.
15.3.2 Configuration
Of the UCCs, this device only supports UCC1 and UCC3.
The following features are not supported: USB, MCC, SPI2, Ethernet, and ATM.
15.3.2.1 Configuration-parameter RAM
For the device, replace the "Default Parameter RAM Base Addresses" table with the table
below.
Table 15-2. Default parameter RAM base addresses
Address Peripheral Size (Bytes)
0x3400 UCC1 (Rx and Tx) 256
0x3600 UCC3 (Rx and Tx) 256
0x3A00 TIMER 64
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 659
QUICC Engine implementation details
15.3.3 Multiplexing and timers
Of the UCCs, only UCC1 and UCC3 are supported; of the TDMs, only TDMA and
TDMB are supported.
USB, SPI, Ethernet, and ATM are not supported.
The following information applies:
• A bank of 5 external clocks CLK[8-12]
• Two internal clocks CLK[3,15]
• Four supported BRGs: BRG[1-4]
• Two UCCs: UCC1 and UCC3
• Two TDMs: TDMA and TDMB
15.3.3.1 Multiplexing and timers-NMSI configuration
For the device, replace the "Bank of Clocks" figure with the figure below.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
660 NXP Semiconductors
Chapter 15 QUICC Engine Block
BRG1 BRG2 BRG3 BRG4
BRGO1
BRGO2
BRGO3
BRGO4
RX
UCC1
TX
CLK08/CLK12
CLK09
Bank of Clock
Selection Logic CLK10
RX
UCC3
CLK11
TX
(Partially filled cross-switch logic programmed
in the CMX registers.)
RX TX RX TX
TDMA1 TDMB1
Figure 15-4. Bank of clocks
NOTE
1. CLK3 and CLK15 are connected in chip level to the
internal platform clock.
2. External CLK12 pin is connected internally to both CLK12
and CLK8 pins of QE.
In the "NMSI Configuration" subsection, refer to the tables below.
The table below shows the clock source options for the serial controllers and TDM
channels.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 661
QUICC Engine implementation details
Table 15-3. Clock source options-external clock signals
Clock External CLK Number
3 8 9 10 11 12 15
UCC1 Rx V V V V V
UCC1 Tx V V V V V
UCC3 Rx V V V V V
UCC3 Tx V V V V V
TDMA1 Rx V V
TDMA1 Tx V
TDMB1 Rx V
TDMB1 Tx V
QUICC Engine Timer V V
The table below shows the clock routing options using the internal clock generators.
Table 15-4. Clock source options-internal clock
Clock BRG clock number
1 2 3 4
UCC1 Rx V V
UCC1 Tx V V
UCC3 Rx V V
UCC3 Tx V V
TDMA1 Rx1 V V
TDMA1 Tx1 V V
TDMB1 Rx1 V V
TDMB1 Tx1 V V
1. TDM options are used only for internal loopback mode.
The table below shows the UART autobaud clock options.
Table 15-5. Clock source options-UART autobaud clock options
Clock BRG Clock Number for UART Autobaud
1 2 3 4
UCC1 Rx V
UCC1 Tx V
UCC3 Rx V
UCC3 Tx V
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
662 NXP Semiconductors
Chapter 15 QUICC Engine Block
15.3.3.2 Multiplexing and timers-baud-rate generators (BRGs), BRG
configuration registers 1-4 (BRGCn)
The table below describes the BRGCn fields.
Table 15-6. BRGCn field descriptions
Bits Name Description
0-13 - Reserved, should be cleared.
14 RST Reset BRG. Performs a software reset of the BRG identical to that of an external reset. A reset disables the
BRG and drives BRGO high. This is externally visible only if BRGO is connected to the corresponding
parallel I/O pin.
0 Enable the BRG.
1 Reset the BRG (software reset).
15 EN Enable BRG count. Used to dynamically stop the BRG from counting-useful for low-power modes.
0 Stop all clocks to the BRG.
1 Enable clocks to the BRG.
16-17 EXTC External clock source. Selects the BRG input clock.
00 The BRG input clock comes from the BRGCLK (internal clock generated from the QUICC Engine clock,
it is one-half of the QUICC Engine clock).
01 If BRG1, 2: The BRG input clock comes from the CLK3 pin (driven internally by platform/2 clock).
If BRG3, 4: The BRG input clock comes from the CLK9 pin.
10 If BRG1, 2: The BRG input clock comes from the CLK3 pin (driven internally by platform/2 clock).
If BRG3, 4: The BRG input clock comes from the CLK15 pin (driven internally by platform/2 clock).
11 Reserved
18 ATB Autobaud. Selects autobaud operation of the BRG on the corresponding RXD. ATB must remain zero until
the UCC receives the three Rx clocks. Then the user must set ATB to obtain the correct baud rate. After the
baud rate is obtained and locked, it is indicated by setting AB in the UART event register, see "UCC UART
Event Register (UCCE) and Mask Register (UCCM)," in QUICC Engine™ Block Reference Manual with
Protocol Interworking.
0 Normal operation of the BRG.
1 When RXD goes low, the BRG determines the length of the start bit and synchronizes the BRG to the
actual baud rate.
19-30 CD Clock divider. CD presets an internal 12-bit counter that is decremented at the DIV16 output rate. When the
counter reaches zero, it is reloaded with CD. CD = 0xFFF produces the minimum clock rate for BGRO
(divide by 4,096); CD = 0x000 produces the maximum rate (divide by 1). When dividing by an odd number,
the counter ensures a 50% duty cycle by asserting the terminal count; once on clock low and next on clock
high. The terminal count signals that the counter has expired and then toggles the clock.
0x000 Divide by 1 (maximum clock rate)
0x001 Divide by 2
...
0xFFF Divide by 4096 (minimum clock rate)
31 DIV16 Divide-by-16. Selects a divide-by-1 or divide-by-16 prescaler before reaching the clock divider.
0 Divide by 1.
1 Divide by 16.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 663
QUICC Engine implementation details
The table below shows the possible external clock sources for the BRGs.
Table 15-7. BRG external clock source options
BRG CLK
3 8 9 10 11 12 15
1 1
BRG1 V
BRG2 V
BRG3 V V
BRG4 V V
1. CLK3 and CLK15 are connected to the internal platform/2 clock.
15.3.4 Unified communications controllers (UCCs)
Of the UCCs, only UCC1 and UCC3 are supported.
The following features are not supported: USB, MCC, SPI, Ethernet, and ATM.
15.3.4.1 Unified communications controllers (UCCs)-UCC page base
address
Refer to the table below for the UCC base addresses.
Table 15-8. Parameter RAM-UCC default base addresses
Page Address 1 Peripheral Size (Bytes)
1 0x3400 UCC1 256
3 0x3600 UCC3 256
1. Offset from RAM_Base
15.3.5 HDLC controller
The ratio between the HDLC interface serial clock frequency and the QUICC Engine
clock frequency should be at least 1:3.
NOTE
The HDLC serial clock must not exceed the maximal frequency
as specified in the data sheet.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
664 NXP Semiconductors
Chapter 15 QUICC Engine Block
15.3.5.1 HDLC controller-introduction
It should be noted that GUMR[RTSM] should be set for the HDLC nibble mode.
15.3.6 Transparent controller
The chip does not support the automatic sync feature, so all references to this should be
disregarded.
The QUICC Engine frequency must be higher than the data bit-rate multiplied by 8/3.
The transparent protocol is supported on all UCCs, but octal mode is not supported.
UCC1 only supports 1-bit data (serial) mode, while UCC3 supports 1- and 4-bit data
modes.
15.3.7 UCC for fast protocols
Only a system bus is supported; references to a secondary bus should be disregarded.
As such,
• In the "Bus Mode Registers (RBMR and TBMR)" subsection of the QEIWRM, DTB
and BDB should be reserved.
15.3.8 UCC for slow protocols
Only a system bus is supported; references to a secondary bus should be disregarded.
As such,
• In the "Bus Mode Registers (RBMR and TBMR)" subsection of the QEIWRM, DTB
and BDB should be reserved.
15.3.9 UART mode and asynchronous HDLC
The ratio between the UART serial clock frequency and the QUICC Engine clock
frequency should be at least 1:16.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 665
QUICC Engine implementation details
15.3.10 BISYNC mode
The ratio between the BISYNC serial clock frequency and the QUICC Engine clock
frequency should be at least 1:7.
Generally, the BISYNC serial frequency is less than 20 MHz.
15.3.11 Serial interface with time-slot assigner
The two TDMs, TDMA and TDMB, only support 1-bit data (serial) mode.
The TDM can only work with an external sync and external clock; other options are not
supported. The external clock and external sync need to meet the timing specifications as
provided in data sheet.
This device supports TDM in a high-speed mode. To run in this mode, the QUICC
Engine platform to TDM interface frequency ratio should be 8:1, where a ratio of 400
MHz:50 MHz is recommended. The TDM maximum frequency is 50 MHz.
For the ISDN protocol, the maximum frequency supported is 25 MHz, with the condition
that the QUICC Engine platform to ISDN interface frequency ratio is 16:1. For example,
if the QUICC Engine platform frequency is 400 MHz, then the ISDN interface maximum
frequency is 25 MHz.
15.3.12 Multi-channel controller on UCC (UMCC)
UMCC is supported with only the HDLC and transparent modes. The SS7 mode is not
supported.
• The UMCC controller supports two TDM lines.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
666 NXP Semiconductors
Chapter 16
Data Path Acceleration Architecture (DPAA)
Overview and SoC DPAA Implementation
16.1 DPAA Introduction and Terms
The data path processing subsystem is an implementation of the QorIQ Data Path
Acceleration Architecture (DPAA).
The QorIQ LS1043A Data Path Acceleration Architecture (DPAA) Reference Manual
describes the superset of DPAA functionality. The chip implements a unique subset of
this functionality, as described in the LS1043A-Specific DPAA Implementation Details.
As shown in the following figure, the DPAA consists of a parse, classify, and distribute
module (PCD) and an accelerator module (FMan), along with these related network
interfaces:
• Multirate Ethernet MAC (mEMAC)
• hardware offload accelerators:
• SEC
• the infrastructure blocks that support these accelerators (QMan and BMan)
Each of these accelerators provides its own unique set of functionality, and thus each has
its own unique requirements for how software must program and interact with that
accelerator.
The DPAA's common infrastructure modules and the desire to be able to pass data
received from one accelerator to another led to some common requirements, restrictions,
and conventions. This chapter outlines requirements and conventions that are common to
multiple accelerators within the DPAA.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 667
DPAA Introduction and Terms
Frame Manager
Parse DMA
QMan
and
Classify
SEC
BMan
Buffer Buffer
7 multirate Ethernet MACs
Figure 16-1. QorIQ Data Path Acceleration Architecture
The following list describes common DPAA terms and definitions.
Buffer
Region of contiguous memory, allocated by software, may be managed by the DPAA
Buffer Manager (BMan).
Buffer pool
Set of buffers with common characteristics (mainly size, alignment, access control)
B B B
Frame
Contents of a single buffer or multiple buffers referenced by a table that hold data. For
example, packet payload, header, and other control information.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
668 NXP Semiconductors
Chapter 16 Data Path Acceleration Architecture (DPAA) Overview and SoC DPAA Implementation
B
F =
Frame queue (FQ)
FIFO of frames
FQ = F F
Work queue (WQ)
FIFO of frame queues (FQs)
WQ = FQ FQ
Channel
Set of eight work queues (WQs), with hardware provided prioritized access
0 FQ FQ
Chan = Priority
7 FQ FQ
Dedicated channel
Channel statically assigned to a particular end point from which that end point can
dequeue frames. End-point may be a CPU, FMan, or SEC.
Pool channel
A channel statically assigned to a group of end points from which any of the end
points may dequeue frames.
16.2 Data Formats Used in the DPAA
Data-to-be-processed is passed within the DPAA in distinct units known as “frames.”
The actual data is held in buffers in memory and a description of the frame is what is
passed within the DPAA.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 669
Data Formats Used in the DPAA
16.2.1 Frame Descriptor (FD)
A frame descriptor (FD) is the basic element queued by the QMan.
See the, "Frame Manager" chapter in the QorIQ LS1043A Data Path Acceleration
Architecture (DPAA) Reference Manual for a description of the QMan's usage of the FD.
The use and interpretation of some fields is specific to the producer or consumer of the
FD. Such usage is described in the chapter/section covering that module.
16.2.1.1 FD Format
Table 16-1. Frame Descriptor (FD)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
DD ICID BPID Reser EICID Reserved ADDR
ve
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
ADDR
64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95
FORMAT OFFSET LENGTH
LENGTH or CONGESTION WEIGHT
96 97 98 99 10 10 10 10 10 10 10 10 10 10 11 11 11 11 11 11 11 11 11 11 12 12 12 12 12 12 12 12
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7
STATUS/CMD
Table 16-2. FD Field Descriptions
FD Bits FD Name FD Field Description
0-1 DD Dynamic Debug marking code point
A frame with a non-zero debug code point can generate a trace event at various enqueue
and/or dequeue points within the QMan. Individual QMan users have different
mechanisms and criteria for setting non-zero DD values.
2-7 ICID Frame ICID (6 least significant bits of complete ICID)
The ICID is set when the FD is enqueued. It is used by a hardware module that
dequeues the FD as part of the memory access control mechanism supported by the
SMMU.
8-15 BPID Buffer Pool ID
The Buffer Pool ID is the number of the BMan buffer pool to which the buffer at ADDR
should be released, if it is to be released to BMan.
16-17 - Reserved
18-19 EICID Frame Extended ICID (2 most significant bits of complete ICID)
The complete 8-bit ICID value is a concatenation of {EICID, ICID}.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
670 NXP Semiconductors
Chapter 16 Data Path Acceleration Architecture (DPAA) Overview and SoC DPAA Implementation
Table 16-2. FD Field Descriptions (continued)
FD Bits FD Name FD Field Description
20-23 - Reserved
24-63 ADDR Address
The memory address of the start of the buffer holding the frame data or the buffer
containing the scatter/gather list describing the frame
64-66 FORMAT A coded value that defines the format of the OFFSET and LENGTH fields, and of the
frame referenced by this FD. See Frame Format Codes for a description of these codes.
Optional 67-7 OFFSET This field is valid only when FORMAT bits 65-66 are 00; otherwise, a frame offset value
5 of 0 is implied.
fields
Frame offset is the number of bytes from the frame address (ADDR) at which actual data
begins. Note that this field is not present in all FDs
76-9 LENGTH Total number of valid bytes of data in the frame. Note that this field is not present in all
5 FDs.
67-9 CONGESTION A value used by the QMan for certain congestion management/avoidance calculations.
5 WEIGHT Note that this field is not present in all FDs.
96-127 STATUS/CMD Status or Command
This field allows the sender of a frame to communicate some out-of-band information to
the receiver of the frame. For example, this field can be used to communicate a
command describing what processing is to be performed to a hardware accelerator or the
error/output status after a hardware accelerator has finished processing a frame.
16.2.2 Multi-Buffer Frames
The actual data in a frame is held in one or more memory buffers.
If multiple buffers are required, a scatter/gather table (also known as a block vector or IO
vector table) is used to describe the buffers in a multi-buffer frame. See Scatter/Gather
Entry Format for a description of this data structure.
16.2.2.1 Scatter/Gather Entry Format
The table below lists the Scatter/Gather Table Entry Format:
Table 16-3. Scatter/Gather Table Entry Format
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0 Reserved (must be 0) ADDR
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
1 ADDR
64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95
2 E F LENGTH
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 671
Data Formats Used in the DPAA
Table 16-3. Scatter/Gather Table Entry Format (continued)
96 97 98 99 10 10 10 10 10 10 10 10 10 10 11 11 11 11 11 11 11 11 11 11 12 12 12 12 12 12 12 12
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7
3 Reserved (must be 0) BPID Reserved OFFSET
(Must be
0)
Table 16-4. Scatter Gather Table Entry Field Description
Bits Name Description
0-23 - Reserved (must be 0)
24-63 ADDR Address of the buffer referenced by this table entry. This buffer may contain data or it may contain
another scatter/gather table.
64 E Extension bit. If set, this table entry points to a buffer that contains another scatter/gather table.
65 F Final bit. If set, this is the last table entry for this frame.
Note that the E (extension) bit takes precedence over the F (final) bit. If both are set, the F bit is ignored
and processing continues with the entries in the scatter/gather table in referenced buffer.
66-95 LENGTH Depending on the context, this field either specifies the number of valid bytes of data in the referenced
buffer or the size of the referenced buffer (in the case that empty buffers are being provided to an
accelerator).
Note that if the E (extension) bit is set, LENGTH is ignored.
96-103 - Reserved (must be 0)
104-111 BPID Buffer Pool ID: The number of the BMan buffer pool to which this buffer should be released, if it is
released to BMan.
112-114 - Reserved (must be 0)
115-127 OFFSET An offset in bytes from the ADDR at which valid data starts
Note that if the E (extension) bit is set, "valid data" is a scatter/gather table.
16.2.2.2 Multi-Buffer Frame Considerations
Important multi-buffer frame considerations are as follows:
• The first scatter/gather table in a multi-buffer frame is held in the buffer referenced
by the FD. In the case of a short, multi-buffer frame, the table starts at OFFSET bytes
from the beginning of the buffer.
• “Trees” or hierarchy are not supported, because for simple, multi-buffer frames,
processing never returns to the table in the original buffer.
• If the E bit is set, it indicates that the table entry points to another buffer containing
more table entries. When a scatter/gather table entry with the E bit set is encountered,
processing proceeds from the first entry in the new table found in the new buffer.
This new table may begin at some offset from the start of the buffer as defined by the
OFFSET field in the entry with the E bit set.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
672 NXP Semiconductors
Chapter 16 Data Path Acceleration Architecture (DPAA) Overview and SoC DPAA Implementation
• In simple, multi-buffer frames, the LENGTH field in a table entry with its E bit set
can be ignored.
• The E bit takes precedence over the F bit (that is, if both are set in an entry, the F bit
is ignored).
This figure shows a simplified representation of a "long" simple frame using a scatter/
gather table. Note that this diagram does not show the use of the Extension bit.
Frame Descriptor Scatter/ Gather List Buffers
D ICID ADDR
BPID 0 0 LENGTH
ADDR BPID
001 LENGTH OFFSET
Status/ Command ADDR
0 0 LENGTH
BPID
OFFSET
ADDR
0 1 LENGTH
BPID
OFFSET
Figure 16-2. Simplified Representation of a Long, Multi-Buffer, Simple Frame
16.2.2.3 Situations Where Multi-Frame Buffering Stops
Multi-buffer frame processing stops in the following situations:
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 673
Data Formats Used in the DPAA
• When the data referenced by an entry with the F bit is processed regardless of the
LENGTH indicated in the FD for the frame. In some cases, a mismatch (less data
found in the frame compared to the FD length) may be an error condition for the
accelerator module that is performing the processing, and it is reported as such.
• Processing also stops when the number of bytes specified by the overall length in the
frame's FD have been processed. In this case, it is not necessary to have encountered
an entry with the F bit set and it is not considered an error when this occurs.
16.2.3 Single-Buffer Frames
Most frame formats consist of a single delineated unit of data such as a single packet or
Protocol Data Unit (PDU).
For a single buffer, the FD[LENGTH] field represents the total amount of valid data in
the frame. The OFFSET represents the offset to the start of valid data.
For multiple buffers (used for scatter/gather), the FD[LENGTH] field still represents the
total amount of valid data in the frame, but the OFFSET represents the offset to the start
of the scatter/gather table in the first buffer.
16.2.4 Compound Frames
Frames may also consist of multiple, related, distinct units such as the encrypted form of
a packet along with the decrypted form of the same packet. These are known as
compound frames, which consist of two or more simple frames.
Each simple frame in a compound frame can in turn be stored in a single buffer or in
multiple buffers. Compound frames exist so that all of the related data can be passed in a
single unit within the DPAA. If an FD has a FORMAT code that identifies it as a
compound frame then the FD[CONGESTION WEIGHT] is used to by the QMan for
active queue management calculations such as WRED.
16.2.4.1 When to Use Compound Frames
Compound frames are used for the following purposes:
• To pass multiple, distinct pieces of data either to or from a hardware accelerator. For
instance, it may be required to pass frames containing both encrypted and decrypted
forms of a packet.
• To supply empty buffers to a hardware accelerator into which it may place its output.
In this case, it is not desirable to use the BMan. Any LENGTH and OFFSET fields
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
674 NXP Semiconductors
Chapter 16 Data Path Acceleration Architecture (DPAA) Overview and SoC DPAA Implementation
that refer to a specific buffer have special meaning; OFFSET specifies the byte offset
from ADDR where the accelerator should start storing data and LENGTH gives the
number of bytes of data which can be stored in the remainder of the buffer.
Consider the following when using compound frames:
• When multiple input or output frames are described by a compound frame, their
order is consumer-dependent.
• If a compound frame is used to pass empty buffers to a consumer for its output, those
buffers are in the first frame of the compound frame.
• If a module uses a compound frame to return the input frame as well as its output
frame, the output frame is the first frame of the compound frame and the input frame
is the second frame.
16.2.4.2 Compound Frame Considerations
Important compound frame considerations are as follows:
• Compound frames use the same scatter/gather table format as simple frames, but
with slightly different semantics for the fields in the table entries.
• The buffer referenced by FD[ADDR] of a compound frame must contain a scatter/
gather table (the compound scatter/gather table). A compound frame contains
FD[CONGESTION WEIGHT] but does not contain FD[LENGTH] or FD[OFFSET].
The compound scatter/gather table must start at FD[ADDR].
• Each entry in the compound scatter/gather table references a simple frame. ADDR,
LENGTH, BPID, and OFFSET fields in the compound scatter/gather table entry
replace the corresponding fields in an FD. A compound frame contains
FD[CONGESTION WEIGHT] but does not contain FD[LENGTH] or FD[OFFSET].
The compound scatter/gather table must start at FD[ADDR].
• The E bit is set if the simple frame occupies multiple buffers. The E bits in multiple
entries in the compound scatter/gather table may be set, because each simple frame in
the compound frame may occupy multiple buffers. In this case, the buffer at ADDR
contains a scatter/gather table.
• The scatter/gather table(s) that make up a simple frame that is part of a compound
frame follow the same semantics as described in Scatter/Gather Entry Format.
• There is no equivalent in the compound scatter/gather table for the FORMAT field in
the FD. The entries in a compound scatter/gather table cannot themselves be
compound frames; the E bit is used to indicate a multi-buffer frame, and the
LENGTH and OFFSET fields supported in the scatter/gather entry are a superset of
the fields in an FD.
• The F bit must be set in the last entry of a compound frame scatter/gather table.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 675
Data Formats Used in the DPAA
This figure shows a representation of a compound frame.
Compound Frame Compound Frame
Description Scatter/ Gather List
Buffer
D PID ADDR
or
BPID X 0 LENGTH Scatter/ Gather List
Containing Output
ADDR BPID
001 CongWght OFFSET
Status/ Command ADDR
Buffer
X 1 LENGTH or
Scatter/ Gather List
BPID Containing Input
OFFSET
Figure 16-3. Simplified Representation of a Compound Frame
16.2.5 Simple Frames
Simple frames can be either short or long. Regardless of the length of the frame, data is
stored in a single-buffer frame, whereas scatter/gather tables are stored in a multi-buffer
frame.
A short frame can be no more than (1 Mbyte - 1 byte)-long but the data (in the case of a
single buffer frame) or scatter/gather table (in the case of a multi-buffer frame) can be
stored starting at an offset from the beginning of the buffer referenced by the FD. Long
frames can be as much as (512 Mbytes - 1 byte)-long, but the data or scatter/gather table
must be stored starting at the beginning of the buffer referenced by the FD.
Because network data (packets) are typically much less than 64 Kbytes in size, the short
format is useful for most network processing needs.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
676 NXP Semiconductors
Chapter 16 Data Path Acceleration Architecture (DPAA) Overview and SoC DPAA Implementation
16.2.6 Frame Format Codes
This table defines the frame format codes and provides a brief description of the frame
format.
Table 16-5. Frame Format Codes
Value Mnemonic Definition Size of LENGTH, OFFSET, and
CONGESTION WEIGHT Fields
'000' Short single buffer simple frame Simple frame Single buffer, Offset and "small" 9b OFFSET, 20b LENGTH
length
'010' Long single buffer simple frame Simple frame, single buffer, "big" length 29b LENGTH
No OFFSET
'100' Short multi-buffer simple frame Simple frame, Scatter Gather table, Offset and 9b OFFSET, 20b LENGTH
"small" length
'110' Long multi-buffer simple frame Simple frame, Scatter Gather table, "big" length 29b LENGTH
No OFFSET
'001' Compound frame Compound Frame 29b
<CONGESTION WEIGHT>
No LENGTH or OFFSET
'011' NA Reserved Not defined
'101' NA Reserved Not defined
'111' NA Reserved Not defined
16.2.7 Frame Formats Supported by Accelerators
Hardware accelerators (FMan) support a subset of the DPAA frame formats.
This table summarizes the frame formats supported by various accelerators.
Table 16-6. Frame Format Support Matrix
Short, Single Long, Single Short Multi-Buffer Long Multi-Buffer Compound Frames
Buffer Buffer
Input Output Input Output Input Output Input Output Input Output
FMan Yes Yes No No SG table 1 SG table No No No No
limited to 16 limited to 16
entries. entries
E bit not E bit not
supported supported
SEC Yes Yes Yes Yes Yes SG table Yes SG table Yes Yes
limited to one limited to one
one buffer one buffer
E bit not E bit not
supported supported
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 677
Accessing Memory Using Isolation Context Identifier(ICID)
1. Scatter/Gather entry table
16.2.8 Special Values and Exceptions
The ADDR, BPID, and LENGTH fields can have special meanings under certain
conditions, as follows:
• FDs
• Compound frame scatter/gather tables
• Multi-buffer scatter/gather tables
Exceptions and special behaviors are as follows:
• When the LENGTH field that describes a specific buffer is zero, this indicates that
the buffer contains no data. If an accelerator finds a LENGTH of zero it should not
access (read or write) the memory at ADDR.
• The LENGTH field in a scatter/gather table entry of a simple multi-buffer frame with
its E (extension) bit set is an exception, because the value of this field is ignored.
• FDs, compound frame, or multi-buffer frame SG entries with ADDR/BPID/
LENGTH=0 encoding indicate that the FD or SG entry does not convey buffer
information, that is, the SG entry is unused and is therefore skipped during input
and/or output processing.
16.2.9 Releasing Buffers to the BMan
Accelerators only release buffers to the BMan that they have processed or, in the case of
a buffer with a zero LENGTH, that they have passed over during processing. Buffers
with a zero ADDR, BPID, and LENGTH are not released.
REQUIREMENT: Because processing stops when the frame’s total length of data is
processed or after the data referenced by a scatter/gather entry with its F (final) bit set is
processed, ensure that all buffers in a frame are released. For example, software must
ensure that there are no entries in a scatter/gather table for a multi-buffer frame that are
beyond the frame’s total length or described in entries after the entry with the F bit set.
16.3 Accessing Memory Using Isolation Context
Identifier(ICID)
The isolation context identifier(ICID) maps an incoming transaction from IO device to
one of the context and it maps to StreamID as described in Arm documentation.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
678 NXP Semiconductors
Chapter 16 Data Path Acceleration Architecture (DPAA) Overview and SoC DPAA Implementation
By using different ICIDs, a single hardware module can perform memory accesses on
behalf of different requestors with the mapping and access controls appropriate to that
requestor.
ICID Requirements
Some important ICID requirements are as follows:
• The requestor must communicate the ICID to the hardware blockmodule. In the
DPAA, this is done using the ICID. And, this is formed by concatenating ICID and
EICID from the FD with the latter used as the 2 most significant bits(msbs).
• Because ICID is in the FD, the module can use an ICID for each frame to access the
memory.
• Some hardware module may make different types of memory accesses as a result of
dequeuing a frame. For instance, they may access per queue context/state/descriptors
as well as reading and writing frame data. These modules use the same ICID from
FD for these different types of access.
• The ICID must be set by the hypervisor. For software portals, this is done by the
QMan from values configured for the portal to ensure that accesses by hardware
module on behalf of software are controlled. In other words, software running on a
core cannot get a hardware blockmodule to make accesses to memory, because it is
not permitted to make these accesses by setting the ICID value in an FD.
16.4 Packet Walk-Through Example
The following example walks a packet through a DPAA-enabled, QorIQ device to
illustrate how the DPAA offloads and accelerates packet forwarding while leaving key
decisions under software control:
1. Datapath processing begins when Ethernet frames arrive at a network interface,
assumed to be one of the Ethernet MACs within a Frame Manager (FMan).
Alternatively, packets can arrive across a peripheral bus from an external network
interface, in which case, the same packet walk-through stages can be applied with the
help of a CPU acting as an I/O processor.
2. After FMan receives the Ethernet frame, it requests one or more buffers from the
hardware Buffer Manager (BMan) to store the frame. BMan maintains pools of
buffers, each with software-defined characteristics, and FMan is initialized to request
a buffer from the most appropriate pool. If a sufficiently large buffer cannot be found
for the incoming frame, FMan stores the frame across several smaller buffers and
creates a scatter/gather list for these buffers.
3. FMan's configurable parsing and filing capabilities can perform initial classification,
sufficient to steer a packet toward a control processor, or toward one of the datapath
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 679
Packet Walk-Through Example
processors for flow-specific processing (or additional classification by means of
software). The steering of a packet towards a processor or a group of processors
could be also based on differentiating flows by means of the Quality of Service
attributes of the flow (for example, DSCP, IP precedence, or by user-defined
proprietary headers).
4. Steering is accomplished by FMan issuing an enqueue command to QMan with the
designated Frame Queue ID, along with frame parameters such as Frame Queue ID
and Color Marking. In this example FMan's initial classification causes it to select a
Frame Queue ID which the Queue Manager uses to steer the Frame Queue to the
dedicated channel of logical CPU#3, a CPU operating in a datapath role. Potentially,
the Frame Queue could be selected based on the QoS requirements of the flow with a
policing profile associated with the selection.
5. Continuing the example, QMan places the Frame Queue onto Work Queue#5 of
CPU#3's dedicated channel. The Frame Queue was queued to CPU#3 due to user
configuration decisions that all packets belonging to this specific flow should be
processed by CPU#3, possibly to take advantage of special processing instructions
locked in CPU#3's private cache, or due to user-defined load balancing. The Frame
Queue was placed in Work Queue#5 for QoS reasons, as the amount of traffic
processed from each Work Queue relative to other work queues is also user-
configurable. All Frame Queues on a Work Queue have equal priority, but the
amount of traffic that the CPU draws from each is user-configurable to allow fairness
and appropriate bandwidth allocation.
6. Once configured, QMan can take care of the packet/frame level scheduling
requirements of the CPU, that is, QMan would appropriately schedule the Work
Queue and Frame Queue within the Work Queue. QMan can be configured to
perform a stashing operation in response to a CPU (or co-processor) accessing a
Frame Queue.
7. CPU#3 performs protocol processing on the packet, including modification of the
packet data in the buffer. Any modifications which change the length of the packet
would be noted by means of changes to the frame. The CPU determines that the
packet requires IPsec ESP processing, and enqueues the frame back to the QMan
using the FQ ID associated with the packet's specific ESP tunnel.
8. The QMan uses this Frame Queue ID to determine that the next consumer of the
Frame Queue is the SEC, and places the Frame Queue onto Work Queue#5 of the
SEC's dedicated channel. The SEC pulls Frame Queues from the Work Queues in its
dedicated channel according to user-defined weights in a WFQ model.
9. The SEC dequeues and processes data from the Frame Queue, adding the tunnel IP
header, ESP header, IV, trailer, and HMAC, and writing encrypted data to either the
original buffers, or new buffers which the SEC requests from BMan. The SEC
updates the frame description (length change due to the addition of the headers,
trailers, and HMAC) and enqueues the FQ back to QMan using a configured FQ ID.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
680 NXP Semiconductors
Chapter 16 Data Path Acceleration Architecture (DPAA) Overview and SoC DPAA Implementation
In this case, the FQ ID causes the QMan to enqueue the FQ to Work Queue #5 of
logical CPU#4's dedicated channel. CPU#4 dequeues the FQ, determines the
outbound interface for the newly encrypted packet, updates the tunnel IP header, and
enqueues the frame back to QMan on a new FQ ID. This FQ ID causes the QMan to
enqueue the FQ to a channel serviced by FMan, which dequeues the FQ, transmits
one or more packets from that FQ out the appropriate mEMAC, and releases the
buffers back to BMan.
The processing pipeline used in this example is not required by the QorIQ DPAA. The
initial classification could have caused the packet to be steered toward a CPU dedicated
to fine-grained classification, or to a pool channel of CPUs, any of which could have
performed the operations described. CPU#3 could have added the ESP header and trailer
to the packet and sent it to the SEC for crypto-only processing. Following SEC
processing, the flow was steered to CPU#4, however it could have just as easily been
steered back to CPU#3, or to a pool channel. At any FQ ID transition, the relative priority
of the flow could have been elevated or reduced by enqueuing it to a different work
queue.
16.5 LS1043A-Specific DPAA Implementation Details
The QorIQ LS1043A Data Path Acceleration Architecture (DPAA) Reference Manual
describes the superset of DPAA functionality. The LS1043A implements a unique subset
of this functionality, as described in the following sections.
16.5.1 Queue Manager (QMan) Implementation
The QMan of the LS1043A is implemented as described in the QorIQ LS1043A Data
Path Acceleration Architecture (DPAA) Reference Manual with the following
implementation parameters:
• QMan block base address: 188_0000h
• 512 frame queue (FQ) cache
• 2-KB SFDRs
• 256 congestion groups
NOTE
The QMan is always a non-secure master. The security
protection (CSL6[24:16]) in the QMan/BMan portal path
should be configured as allow all access.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 681
LS1043A-Specific DPAA Implementation Details
16.5.2 Buffer Manager (BMan) Implementation
The BMan of the LS1043A is implemented as described in the QorIQ LS1043A Data
Path Acceleration Architecture (DPAA) Reference Manual with the following
implementation parameters:
• BMan block base address: 189_0000h
• 64 buffer pools
16.5.3 Frame Manager (FMan) Implementation
The FMan is implemented as described in the QorIQ LS1043A Data Path Acceleration
Architecture (DPAA) Reference Manual with the following implementation parameters:
• FMan block base address: 1A0_0000h
• Seven multirate Ethernet MACs
• Five 1G/100M/10M multirate Ethernet MACs
• One 2.5G/1G/100M/10M multirate Ethernet MAC
• One 10G/2.5G/100M/10M multirate Ethernet MAC
• • Block base addresses are as follows:
• FM1 mEMAC1: 1AE_0000h
• FM1 mEMAC2: 1AE_2000h
• FM1 mEMAC3: 1AE_4000h
• FM1 mEMAC4: 1AE_6000h
• FM1 mEMAC5: 1AE_8000h
• FM1 mEMAC6: 1AE_A000h
• FM1 mEMAC9: 1AF_0000h
• Supports 1 host command and 3 offline ports:
• Host command: 02h
• Offline port 3: 03h
• Offline port 4: 04h
• Offline port 5: 05h
• FM1 Dedicated MDIO1: 0x1AF_C000
• FM1 Dedicated MDIO2: 0x1AF_D000
• One FMan Controller complex
• 384-KB internal FMan memory
• 64-KB FMan Controller configuration data
• Up to 32 Keygen schemes
• Up to 256 Policer profiles
• Up to 84 entries in FMan DMA command queue
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
682 NXP Semiconductors
Chapter 16 Data Path Acceleration Architecture (DPAA) Overview and SoC DPAA Implementation
• Up to 64 TNUMs
• Up to 1 FMan debug flows
16.5.4 Security and Encryption Engine (SEC) Implementation
The Security and Encryption Engine of the LS1043A is implemented as described in the
QorIQ LS1043A Security (SEC) Reference Manual with the following implementation
parameters:
• SEC block base address: 170_0000
• 5 Gbps IPsec performance at Ethernet MTU-sized packets, when the cipher suite is
AES-128-CBC / HMAC-SHA-1
• Cryptographic Hardware Accelerators (CHAs) include:
• PKHA
• DESA
• AESA
• MDHA
• RNG4
• CRCA
• SNOWf8 and SNOWf9 (Snow)
• KFHA (Kasumi)
• ZUCA and ZUCE
NOTE
For read transactions to be coherent from SEC, both of the
registers should be configured:
• SCFG_SNPCNFGCR[SECRDSNP] (controls the
AxDomain port-connectivity)
• MCFGR[ARCACHE] (controls the AxCache port-
connectivity. For more information on MCFGR register,
refer security reference manual.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 683
LS1043A-Specific DPAA Implementation Details
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
684 NXP Semiconductors
Chapter 17
Secure Boot and Trust Architecture
17.1 Trust architecture objectives
The LS1043A supports the QorIQ Trust Architecture 2.1.
The objective of the trust architecture is to allow OEMs to prevent or strongly mitigate an
attacker's ability to achieve the following attacks:
• theft of functionality,
• theft of third-party data,
• and theft of uniqueness.
These attacks are against the OEM's complete system, including both hardware and
software. These systems operate in a wide variety of contexts. In addition, attackers have
a broad range of motivations and skill sets. It is beyond the scope of this document to
provide an exhaustive list of threats, mitigations, and contexts in which attacks might
occur.
Consequently, this section focuses on trust architecture claims. This approach allows the
OEM to assess how to best apply the trust architecture to mitigate attacks in a given
context.
17.2 Characteristics and claims
1. Trust architecture is "opt in."
• OEMs do not need to do anything to disable it. All trust features are enabled as
the result of conscious decisions to set fuses, program registers, and perform
code signing.
• TrustZone is not entirely opt-in, as Arm cores come out of reset in execution
level (EL) 3—TZ Secure World Supervisor level.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 685
Characteristics and claims
• Many SoC registers are only writeable when the CPU is executing in TZ
Secure World.
• Beyond basic configuration firmware which would be challenging to run
outside of TZ Secure World, running security services in TZ Secure World
is an OEM 'opt in' decision.
2. OEMs own all of the system's secrets.
• OEMs are not dependent on NXP to provision devices, and NXP is not required
to participate in the chain of trust for system manufacturing, deployment, or field
servicing.
• NXP is developing new software tools and services to support the chain of trust.
• Trust 2.1 devices do include an NXP provisioned portion of a split key. Use of
this split key is optional.
3. Trust architecture allows OEMs to define system security policies & configurations,
which cannot be changed or bypassed by attackers.
• Always perform secure boot
• Access control debug interfaces
• Detect hardware security violations
• Soft or Hard Fail reactions to security violations
4. Trust architecture protects against unauthorized modifications to developer software
and system configuration information (for example, device trees, certificates, and so
on).
• Protection consists of both prevention (secure boot) and after-the-fact detection
mechanisms (for example, runtime integrity checking).
• Secure boot detects unauthorized modifications and, when detected, prevents
the unauthorized code from executing on the device.
• Runtime integrity checking scans regions of memory for unauthorized
modifications to the contents.
5. Trust architecture allows OEMs to provision system permanent secrets, which are
protected against extraction or exposure.
• Permanent secrets continue across resets of the system, and are locked out in
response to security violations.
• Trust architecture 2.1 permanent secrets include:
• Debug Response Value (DRV)
• One-Time Programmable Master Key (OTPMK)
6. Trust architecture allows OEMs to provision system persistent secrets which survive
device resets under normal circumstances, but are capable of being cleared or
rendered unusable.
• Trust architecture 2.1 persistent secrets include:
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
686 NXP Semiconductors
Chapter 17 Secure Boot and Trust Architecture
• Battery backed Zeroizable Master Key (ZMK)
• Any cryptographic blobs created with the OTPMK and stored to NVRAM
prior to system reset
• Cryptographic blobs can be used to make factory installed keys, certificates, and
proprietary code into persistent secrets.
7. Trust architecture allows provisioning of system ephemeral secrets, which are
protected against extraction or exposure.
• Ephemeral secrets are cleared by a security violation or system reset.
• Trust architecture 2.1 ephemeral secrets include:
• Job Descriptor Key Encryption Keys (JDKEKs)
• Session keys negotiated during runtime, which are protected with the
JDKEKs
• Secrets owned by TZ Secure World trusted applications, and stored in
private on-chip or off-chip memory are also considered ephemeral.
8. Trust architecture provides high levels of separation between independent software
domains.
• The private resources of one domain must not be accessible by another domain.
• These independent software partitions can be treated as independent security
domains.
• Arm TrustZone adds "Secure World," another level of separation not found in
Power Architecture-based Trust Architecture devices.
9. Trust architecture 2.1 supports anti-rollback features
• Super Root Key revocation
• Monotonic Counter
17.3 Non-claims
It is also important for OEMs to understand the types of attacks that NXP does not claim
to prevent or strongly mitigate, so that mitigation can be taken at the system level if
necessary.
1. Stronger than the underlying crypto algorithms.
• Trust architecture's foundation rests on the strength of SHA-256, AES-256, and
RSA digital signatures. If these algorithms are found to be fundamentally
broken, most trust architecture claims are broken as well.
2. Preventing advanced physical attacks
• As noted earlier, NXP recognizes that the contents of the Security Fuse
Processor can be read by careful de-processing of the device. This attack
destroys the QorIQ Layerscape device, however cryptographic blobs protected
with the OTPMK could be recovered from system memory and decrypted.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 687
Non-claims
• Memories and registers locked out or zeroized upon detection of security
violations may be subject to memory remanence attacks.
• The SEC's PKHA implements timing equalization, and the AESA implements
differential power analysis resistance features; however, the effectiveness of
these features has not been independently evaluated. Other side channel attack
methods, against the SEC and CPUs, may be possible given sufficient
motivation.
• Operating the device outside of specified voltage, temperature, or frequency
ranges can lead to unexpected failure modes. NXP has attempted to make all
failure modes "fail safe," but the full range of possible glitches has not been
evaluated.
• Trust architecture incorporates tamper detection inputs, which OEMs can use to
alert the device to physical attacks. Without using the Zeroizable Master Key,
the highest consequence of a security violation is that the OTPMK may be
locked out. Assume that attackers are capable of bypassing external tamper
detection logic and rebooting the system with no hardware security violations
detected.
3. Providing absolute isolation between independent software domains/security
domains
• Trust architecture's support for strong partitioning is based on access control
mechanisms. If a resource is private to domain 1, domain 2 must not be able to
access that resource, directly or indirectly. This is different from absolute
isolation, in which domain 2 is unable to interfere with the operation of domain
1. From internal and external bus bandwidth consumption to unfiltered buffer
releases, NXP knows of many scenarios in which domain 2 can interfere with
domain 1.
• Note that NXP is working within the multicore for Avionics (MCFA) working
group to help bound the extent of this interference, including worst-case
execution-time analysis.
4. Operating as a single-edged sword
• Trust architecture is designed to constrain the conditions under which the system
can operate. Attackers can cause security violations for the purpose of shutting
down the system. Trust architecture offers configuration options allowing OEMs
to make trade-offs in security violation sensitivity and consequences, but it is
beyond the scope of a trust architecture device to "know" when trust is being
exploited to disrupt the system. Attackers in a position to trigger security
violations could be capable of causing other types of system failures.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
688 NXP Semiconductors
Chapter 17 Secure Boot and Trust Architecture
17.4 Related resources
QorIQ Trust Architecture is not a mandatory feature; it is opt in. To minimize the
information available to potential attackers, access to detailed Trust Architecture
reference material is restricted to vetted customers with active programs using Trust
Architecture. Contact your NXP Sales or Field Application Engineer to initiate the
admission process to the NXP QorIQ Trust Architecture User’s Group site.
The following table shows related resources that may be helpful.
Table 17-1. Related resources
Resource Purpose
An Introduction to the QorIQ Discusses the objectives of the trust architecture, and how it works. This white paper also
Platform's Trust Architecture includes logistical considerations.
(White Paper)
QorIQ Trust Architecture 2.1 User Primary technical reference for Trust Architecture hardware blocks, including register
Guide level detail, as well as procedural steps to enable secure boot and security violation
detection.
User Enablement for Secure Boot These documents are periodically updated as new features are added to the Code
Signing Tool and reference chain of trust. They can be found in the QorIQ device SDK,
and at www.nxp.com/infocenter: Software and Tools Information Center > QorIQ SDK
Documentation > Secure Boot.
NOTE: Some of these documents are for PBL-based products, some are for non-PBL-
based products. This chip is a PBL-based product.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 689
Related resources
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
690 NXP Semiconductors
Chapter 18
DDR Memory Controller
18.1 DDR Introduction
The DDR SDRAM controller controls processor and I/O interactions with system
memory. The memory system supports a wide range of memory devices. Built-in error
checking and correction (ECC) ensures very low bit-error rates for reliable high-
frequency operation. Dynamic power management and auto-precharge modes simplify
memory system design. A large set of special features, including ECC error injection,
support rapid system debug.
NOTE
In this chapter, the word 'bank' refers to a physical bank
specified by a chip select; 'logical bank' refers to one of the four
or eight sub-banks in each SDRAM chip. A sub-bank is
specified by the 2 or 3 bits on the bank address (MBA) pins
during a memory access.
Also, since DDR3 and DDR3L behave identically except for
voltage, all statements in this chapter that apply to DDR3 apply
equally to DDR3L. Accordingly, DDR3 and DDR3L are
collectively referred as 'DDR3 memory types' or 'DDR3 mode'.
This figure is a high-level block diagram of the DDR memory controller with its
associated interfaces.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 691
DDR Features
Figure 18-1. DDR Memory Controller Simplified Block Diagram
18.2 DDR Features
The DDR memory controller includes these distinctive features:
• Support for DDR standards:
• DDR3L
• DDR4
NOTE
The DDR controller is designed to support DDR4
SDRAMs that are compliant with JESD79-4 from
September 2012.
• Data bus widths supported:
• 32-/36-bit
• 16-/20-bit
• Programmable settings for meeting all SDRAM timing parameters
• The following SDRAM configurations are supported:
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
692 NXP Semiconductors
Chapter 18 DDR Memory Controller
• As many as four physical banks (chip selects), each bank independently
addressable
• 64-Mbit to 8-Gbit devices depending on internal device configuration
• 64-Mbit to 16-Gbit devices depending on internal device configuration
• Supports x8/x16 data ports
• Unbuffered DIMMs
• Chip select interleaving support
• Support for data mask signals and read-modify-write for sub-double-word writes.
Note that a read-modify-write sequence is only necessary when ECC is enabled.
• Support for double-bit error detection and single-bit error correction ECC (8-bit
check word across 64-bit data)
• Support for address parity for DDR4 discrete memories
• Open page management (dedicated entry for each logical bank)
• Automatic DRAM initialization sequence or software-controlled initialization
sequence
• Automatic DRAM data initialization
• Interrupt driven rapid clear of memory
• Write leveling supported
• Support for up to eight posted refreshes
• Memory controller clock frequency of two times the SDRAM clock with support for
sleep power management
• Support for error injection
18.2.1 DDR Modes of Operation
The DDR memory controller supports the following modes:
• Dynamic power management mode. The DDR memory controller can reduce power
consumption by negating the SDRAM CKE signal when no transactions are pending
to the SDRAM.
• Auto-precharge mode. Clearing DDR_SDRAM_INTERVAL[BSTOPRE] causes the
memory controller to issue an auto-precharge command with every read or write
transaction. Auto-precharge mode can be enabled for separate chip selects by setting
CS n_CONFIG[AP_ n_EN].
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 693
DDR External Signal Descriptions
18.3 DDR External Signal Descriptions
This section describes external signals of the DDR memory controller. It describes each
signal's behavior when the signal is asserted or negated and when the signal is an input or
an output.
18.3.1 DDR Signals Overview
Memory controller signals are grouped as follows:
• Memory interface signals
• Clock signals
This table shows how DDR memory controller external signals are grouped. The device
data sheet has a pinout diagram showing pin numbers. It also lists all electrical and
mechanical specifications.
NOTE
When ECC DRAM is present ECC should be enabled.
Table 18-1. DDR Memory Interface Signal Summary
Name Function/Description Reset Pins I/O
MAPAR_ERR_B Address parity error One 1 I
MAPAR_OUT Address parity out Zero 1 O
MDQ[0:31] Data bus All zeros 32 I/O
MDQS[0:3], MDQS8 Data strobes All zeros 5 I/O
MDQS[0:3]_B, MDQS8_B Complement data strobes All ones 5 I/O
MECC[0:3] Error checking and correcting All zeros 4 I/O
MCAS_B/MA15 Column address strobe One 1 O
MA15/MACT_B, Address bus All zeros 16 O
MA14/MBG1,
MA[13:0]
MBA2/MBG0, Logical bank address All zeros 3 O
MBA[1:0]
MCS[0:3]_B Chip selects All ones 4 O
MWE_B/MA14 Write enable One 1 O
MRAS_B/MA16 Row address strobe One 1 O
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
694 NXP Semiconductors
Chapter 18 DDR Memory Controller
Table 18-1. DDR Memory Interface Signal Summary (continued)
Name Function/Description Reset Pins I/O
MDM[0:3]/MDBI[0:3], Data mask All zeros 5 O
MDM8/MDBI8
MCK[0:1] DRAM clock outputs NUM_MCK All zeros 2 O
MCK[0:1]_B DRAM clock outputs (complement) All zeros 2 O
MCKE[0:1] DRAM clock enable All zeros 2 O
MODT[0:1] DRAM on-die termination All zeros 2 O
MDIC[0:1] Driver impedance calibration See chip datasheet for 2 I/O
more information
This table shows the memory address signal mappings for DDR3 memory types.
Table 18-2. Memory Address Signal Mappings for DDR3 Memory Types
Controller Signal Name (Outputs) DRAM/DIMM Signal Name (Inputs)
msb MA15 A15
MA14 A14
MA13 A13
MA12 A12
MA11 A11
MA10 A10 (AP for DDR)
MA9 A9
MA8 A8
MA7 A7
MA6 A6
MA5 A5
MA4 A4
MA3 A3
MA2 A2
MA1 A1
lsb MA0 A0
msb MBA2 BA2
MBA1 BA1
lsb MBA0 BA0
MRAS_B RAS_B
MCAS_B CAS_B
MWE_B WE_B
msb MCS0_B CS0_B
MCS1_B CS1_B
MCS2_B CS2_B
lsb MCS3_B CS3_B
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 695
DDR External Signal Descriptions
This table shows the memory address signal mappings for DDR4.
Table 18-3. Memory Address Signal Mappings for DDR4
Controller Signal Name (Outputs) DRAM/DIMM Signal Name (Inputs)
MA15/MACT_B ACT_n
MA14/MBG1 BG1
msb MA13 A13
MA12 A12
MA11 A11
MA10 A10 (AP for DDR)
MA9 A9
MA8 A8
MA7 A7
MA6 A6
MA5 A5
MA4 A4
MA3 A3
MA2 A2
MA1 A1
lsb MA0 A0
msb MBA2 BG0
MBA1 BA1
lsb MBA0 BA0
MRAS_B/MA16 RAS_n/A16
MCAS_B/MA15 CAS_n/A15
MWE_B/MA14 WE_n/A14
msb MCS0_B CS0_n
MCS1_B CS1_n
MCS2_B CS2_n
lsb MCS3_B CS3_n
MODT1 ODT1
MDM[0:3]/MDBI[0:3], DM_n[0:3]/DBI_n[0:3], DM_n[8]/DBI_n[8]
MDM8/MDBI8
MAPAR_ERR_B ALERT_n
MAPAR_OUT PAR
18.3.2 DDR Detailed Signal Descriptions
The following sections describe the DDR SDRAM controller input and output signals,
the meaning of their different states, and relative timing information for assertion and
negation.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
696 NXP Semiconductors
Chapter 18 DDR Memory Controller
18.3.2.1 Memory Interface Signals
This table describes the DDR controller memory interface signals.
Table 18-4. Memory Interface Signals-Detailed Signal Descriptions
Signal I/O Description
MDQ[0:31] I/O Data bus. Both input and output signals on the DDR memory controller.
O As outputs for the bidirectional data bus, these signals operate as described below.
State Asserted/Negated - Represent the value of data being driven by the DDR memory
Meaning controller.
Timing Assertion/Negation - Driven with valid data during writes to memory.
High impedance-No READ or WRITE command is in progress; data is not being driven by
the memory controller or the DRAM.
I As inputs for the bidirectional data bus, these signals operate as described below.
State Asserted/Negated - Represents the state of data being driven by the external DDR
Meaning SDRAMs.
Timing Assertion/Negation - The DDR SDRAM drives data during a READ transaction.
High impedance-No READ or WRITE command in progress; data is not being driven by the
memory controller or the DRAM.
MDQS[0:3], I/O Data strobes. Inputs with read data, outputs with write data. The data strobes must be differential.
MDQS8 O As outputs, the data strobes are driven by the DDR memory controller during a write transaction.
MDQS[0:3]_B, State Asserted/Negated - Driven high when positive capture data is transmitted and driven low
MDQS8_B Meaning when negative capture data is transmitted. Centered in the data "eye" for writes; coincident
with the data eye for reads. Treated as a clock. Data is valid when signals toggle. See DDR
SDRAM Interface Operation for byte lane assignments.
Timing Assertion/Negation - If a WRITE command is registered at clock edge n, data strobes at
the DRAM assert centered in the data eye on clock edge n + 1. See the JEDEC DDR
SDRAM specification for more information.
I As inputs, the data strobes are driven by the external DDR SDRAMs during a read transaction. The
data strobes are used by the memory controller to synchronize data latching.
State Asserted/Negated - Driven high when positive capture data is received and driven low
Meaning when negative capture data is received. Centered in the data eye for writes; coincident with
the data eye for reads. Treated as a clock. Data is valid when signals toggle. See DDR
SDRAM Interface Operation for byte lane assignments.
Timing Assertion/Negation - If a READ command is registered at clock edge n, and the latency is
programmed in TIMING_CFG_1[CASLAT] to be m clocks, data strobes at the DRAM
assert coincident with the data on clock edge n + m. See the JEDEC DDR SDRAM
specification for more information.
MECC[0:3] I/O Error checking and correcting codes. Input and output signals for the DDR controller's bidirectional
ECC bus.
O As normal mode outputs the ECC signals represent the state of ECC driven by the DDR controller on
writes.
State Asserted/Negated - Represents the state of ECC being driven by the DDR controller on
Meaning writes.
Timing Assertion/Negation - Same timing as MDQ
High impedance - Same timing as MDQ
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 697
DDR External Signal Descriptions
Table 18-4. Memory Interface Signals-Detailed Signal Descriptions (continued)
Signal I/O Description
I As inputs, the ECC signals represent the state of ECC driven by the SDRAM devices on reads.
State Asserted/Negated - Represents the state of ECC being driven by the DDR SDRAMs on
Meaning reads.
Timing Assertion/Negation - Same timing as MDQ
High impedance-Same timing as MDQ
MA15/MACT_B O Address bus. Memory controller outputs for the address to the DRAM. MAn carry the address bits for
the DDR memory interface comprising the row and column address bits. MA0 is the lsb of the address
MA14/MBG1
output from the memory controller.
MA[13:0]
In DDR4 mode: Some of these signals are used for other purposes:
• The activate signal (ACT_n) is driven on MA15/MACT_B. It is never an address signal.
• The BG1 signal is driven on MA14/MBG1. It is never an address signal.
In DDR3 mode, MA15/MACT_B and MA14/MBG1 are always address signals
In DDR4 mode: During activate command assertion, address signal 15 is driven on MCAS_B/MA15
and address signal 14 is driven on MWE_B/MA14.
State Asserted/Negated - Represents the address driven by the DDR memory controller.
Meaning Contains different portions of the address depending on the memory size and the DRAM
command being issued by the memory controller. See DDR SDRAM Address Multiplexing
for a complete description of the mapping of these signals.
Timing Assertion/Negation - The address is always driven when the memory controller is enabled.
It is valid when a transaction is driven to DRAM (when MCS_Bn is active).
High impedance - When the memory controller is disabled
MBA2/MBG0, O Logical bank address. Outputs that drive the logical (or internal) bank address pins of the SDRAM.
Each SDRAM supports four or eight addressable logical sub-banks. Bit zero of the memory
MBA[1:0]
controller's output bank address must be connected to bit zero of the SDRAM's input bank address.
MBA0, the least-significant bit of the bank address signals, is asserted during the mode register set
command to specify the extended mode register.
In DDR4 mode, MBA2 should be connected to BG0 on the DRAM.
State Asserted/Negated - Selects the DDR SDRAM logical (or internal) bank to be activated
Meaning during the row address phase and selects the SDRAM internal bank for the read or write
operation during the column address phase of the memory access. DDR SDRAM Address
Multiplexing describes the mapping of these signals in all cases.
Timing Assertion/Negation - Same timing as MAn
High impedance - Same timing as MAn
MCAS_B/MA15 O Column address strobe. Active-low SDRAM address multiplexing signal. MCAS_B is asserted for read
or write transactions and for mode register set, refresh, self-refrsh and precharge commands in DDR3
mode .
Note that in DDR3 mode this signal is only used as MCASB: MA15 has a dedicated signal in DDR3
mode.
In DDR4 mode: This signal is multiplexed with MA15. During activate command assertion, MA15 is
driven on this pin; see MAn for details of state meaning and timing. At all other times, the pin is driven
as MCAS_B, with state meaning and timing as shown below.
State Asserted - Indicates that a valid SDRAM column address is on the address bus for read
Meaning and write transactions. Refer to the JEDEC DDR SDRAM specifications for more
information on the states required on MCAS_B for various other SDRAM commands.
Negated - The column address is not guaranteed to be valid.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
698 NXP Semiconductors
Chapter 18 DDR Memory Controller
Table 18-4. Memory Interface Signals-Detailed Signal Descriptions (continued)
Signal I/O Description
Timing Assertion/Negation - Assertion and negation timing is directed by the values described in
DDR SDRAM timing configuration 0 (TIMING_CFG_0), DDR SDRAM timing configuration
1 (TIMING_CFG_1), DDR SDRAM timing configuration 2 (TIMING_CFG_2), and DDR
SDRAM timing configuration 3 (TIMING_CFG_3)
High impedance - MCAS_B is always driven unless the memory controller is disabled.
MRAS_B/MA16 O Row address strobe. Active-low SDRAM address multiplexing signal. Asserted for activate, refresh,
self-refresh and precharge commands in DDR3 mode.
Note that in DDR3 mode this signal is only used as MRAS_B.
In DDR4 mode: This signal is multiplexed with MA16. During activate command assertion, MA16 is
driven on this pin; see MAn for details of state meaning and timing. At all other times, the pin is driven
as MRAS_B, with state meaning and timing as shown below.
State Asserted - Indicates that a valid SDRAM row address is on the address bus for read and
Meaning write transactions. Refer to the JEDEC DDR SDRAM specifications for more information on
the states required on MRAS_B for various other SDRAM commands.
Negated - The row address is not guaranteed to be valid.
Timing Assertion/Negation - Assertion and negation timing is directed by the values described in
DDR SDRAM timing configuration 0 (TIMING_CFG_0) , DDR SDRAM timing configuration
1 (TIMING_CFG_1), DDR SDRAM timing configuration 2 (TIMING_CFG_2), and DDR
SDRAM timing configuration 3 (TIMING_CFG_3)
High impedance - MRAS_B is always driven unless the memory controller is disabled.
MCS[0:3]_B O Chip selects. Four chip selects supported by the memory controller.
State Asserted - Selects a physical SDRAM bank to perform a memory operation as described in
Meaning Chip select a memory bounds (CS0_BNDS - CS3_BNDS), and Chip select a configuration
(CS0_CONFIG - CS3_CONFIG). The DDR controller asserts one of the
MCS_B[0:3]signals to begin a memory cycle.
Negated - Indicates no SDRAM action during the current cycle.
Timing Assertion/Negation - Asserted to signal any new transaction to the SDRAM. The
transaction must adhere to the timing constraints set in TIMING_CFG_0-TIMING_CFG_3.
High impedance - Always driven unless the memory controller is disabled.
MWE_B/MA14 O Write enable. Asserted when a write transaction is issued to the SDRAM. This is also used for mode
register set commands and precharge commands in DDR3 mode .
Note that in DDR3 mode this signal is only used as MWE_B: MA14 has a dedicated signal in DDR3
mode.
In DDR4 mode: This signal is multiplexed with MA14. During activate command assertion, MA14 is
driven on this pin; see MAn for details of state meaning and timing. At all other times, the pin is driven
as MWE_B, with state meaning and timing as shown below.
State Asserted - Indicates a memory write operation. Refer to the JEDEC DDR SDRAM
Meaning specifications for more information on the states required on MWE_B for various other
SDRAM commands.
Negated - Indicates a memory read operation.
Timing Assertion/Negation - Similar timing as MRAS_B and MCAS_B. Used for write commands.
High impedance - MWE_B is always driven unless the memory controller is disabled.
MDM[0:3]/ I/O These signals are multiplexed in DDR4. They can be either DDR SDRAM data output masks or data
MDBI[0:3], bus inversion signals. (See DDR SDRAM control configuration 3 (DDR_SDRAM_CFG_3) for more
MDM8/MDBI8 information.) .As data masks MDMn, these signals mask unwanted bytes of data transferred during a
write. They are needed to support sub-burst-size transactions (such as single-byte writes) on SDRAM
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 699
DDR External Signal Descriptions
Table 18-4. Memory Interface Signals-Detailed Signal Descriptions (continued)
Signal I/O Description
where all I/O occurs in multi-byte bursts. MDM0 corresponds to the most significant byte (MSB) and
MDM3 corresponds to the LSB, while MDM8 corresponds to the ECC byte. DDR SDRAM Interface
Operation shows byte lane encodings.
Note that in DDR3 mode these signals are only used as MDMn: data bus inversion is a DDR4-only
feature.
As DDR SDRAM data bus inversion signals DBIn_n, these signals indicate that all the data bits of the
byte lane are inverted on the data bus during a read or write transaction. When used for this purpose,
the signals are I/Os.
O As outputs, these signals operate as described below.
State Asserted-As masks, prevent writing to DDR SDRAM. Asserted when data is written to
Meaning DRAM if the corresponding byte(s) should be masked for the write. Note that the MDMn
signals are active-high for the DDR controller. MDMn is part of the DDR command
encoding. As DBIs, indicate bus signal inversion per byte lane; asserted by the controller
during a write cycle. Note that the DBIn_n signals are active-low for both the DRAM and
DDR controller.
Negated-As masks, allow the corresponding byte to be read from or written to the SDRAM.
As DBIs, signal DRAMs or the DDR controller to invert all DQx in that byte lane before
storing data.
Timing Assertion/Negation-Same timing as MDQx as outputs.
High impedance-Always driven unless the memory controller is disabled.
I As inputs, these signals operate as described below.
State Asserted-As DBIs, indicate bus signal inversion per byte lane; asserted by the DRAMs
Meaning during a read cycle. Note that the DBIn_n signals are active-low for both the DRAM and
DDR controller.
Negated-As DBIs, signal DRAMs or the DDR controller to invert all DQx in that byte lane
before storing data.
Timing Assertion/Negation-Same timing as MDQx as inputs.
High impedance-Always driven unless the memory controller is disabled.
MODT[0:1] O On-Die termination. Memory controller outputs for the ODT to the DRAM. MODT represents the on-
die termination for the associated data, data masks, ECC, and data strobes. The MODT signal should
be connected to the same rank of memory as the corresponding MCK/MCK_B pair.
State Asserted/Negated - Represents the ODT driven by the DDR memory controller.
Meaning
Timing Assertion/Negation - Driven in accordance with JEDEC DRAM specifications for on-die
termination timings. It is configured through the CSn _CONFIG[ODT_RD_CFG] and CSn
_CONFIG[ODT_WR_CFG] fields.
High impedance - Always driven.
MDIC[0:1] I/O Driver impedance calibration. The proper value and connection of the MDIC resistor are specified in
the corresponding device data sheetdocument. See DDR Control Driver Register 1 (DDRCDR_1) for
more information on these signals.
State Used for automatic calibration of the DDR IOs
Meaning
Timing Driven for four DRAM cycles at a time while the DDR controller is executing the automatic
driver compensation
MAPAR_ERR_B I Address parity error. Reflects whether an address parity error has been detected by the DRAM. This
signal is active low. MAPAR_ERR_B is used in DDR4 mode.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
700 NXP Semiconductors
Chapter 18 DDR Memory Controller
Table 18-4. Memory Interface Signals-Detailed Signal Descriptions (continued)
Signal I/O Description
State Asserted - An error has been detected.
Meaning
Negated - An error has not been detected.
Timing Assertion/Negation- In DDR4 mode: Driven by DRAM ALERT_n pin a period of time after
parity error has been detected by the DRAM.
MAPAR_OUT O Address parity out. Driven by the memory controller as the parity bit calculated across the address
and command bits. Even parity is used, and parity is not calculated for the MCKE[0:3], MODT[0:3], or
MCS_B[0:3] signals. MAPAR_OUT can be used with any DDR4 DRAM.
State Asserted-The parity bit is high.
Meaning
Negated-The parity bit is low.
Timing Assertion/Negation-In DDR3 mode: Will be issued one DRAM cycle after the chip select for
each command. In DDR4 mode: Will be issued at the same cycle as the chip select.
18.3.2.2 Clock Interface Signals
This table contains the detailed descriptions of the clock signals of the DDR controller.
Table 18-5. Clock Signals - Detailed Signal Descriptions
Signal I/O Description
MCK[0:1], O DRAM clock output and complement.
MCK_B[0:1] State Asserted/Negated - The JEDEC DDR SDRAM specifications require true and complement
Meaning clocks. A clock edge is seen by the SDRAM when the true and complement cross.
Timing Assertion/Negation - Timing is controlled by the DDR_CLK_CNTL register at offset 0x130.
MCKE[0:1] O Clock enable. Output signal used as the clock enable to the SDRAM. MCKEn can be negated to stop
clocking the DDR SDRAM. The MCKE signal should be connected to the same rank of memory as the
corresponding MCK/MCK_B pair.
State Asserted - Clocking to the SDRAM is enabled.
Meaning
Negated - Clocking to the SDRAM is disabled and the SDRAM should ignore signal
transitions on MCK or MCK_B. MCK/MCK_B are don't cares while MCKEn is negated.
Timing Assertion/Negation - Asserted when DDR_SDRAM_CFG[MEM_EN] is set. Can be negated
when entering dynamic power management or self refresh. Will be asserted again when
exiting dynamic power management or self refresh.
High impedance-Always driven.
18.4 DDR register descriptions
This table shows the register memory map for the DDR memory controller.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 701
DDR register descriptions
18.4.1 DDR Memory map
ddr_ctlr base address: 108_0000h
Offset Register Width Access Reset value
(In bits)
0h Chip select 0 memory bounds (CS0_BNDS) 32 RW 0000_0000h
8h Chip select 1 memory bounds (CS1_BNDS) 32 RW 0000_0000h
10h Chip select 2 memory bounds (CS2_BNDS) 32 RW 0000_0000h
18h Chip select 3 memory bounds (CS3_BNDS) 32 RW 0000_0000h
80h - 8Ch Chip select a configuration (CS0_CONFIG - CS3_CONFIG) 32 RW 0000_0000h
100h DDR SDRAM timing configuration 3 (TIMING_CFG_3) 32 RW 0000_0000h
104h DDR SDRAM timing configuration 0 (TIMING_CFG_0) 32 RW 0011_0005h
108h DDR SDRAM timing configuration 1 (TIMING_CFG_1) 32 RW 0000_0000h
10Ch DDR SDRAM timing configuration 2 (TIMING_CFG_2) 32 RW 0000_0000h
110h DDR SDRAM control configuration (DDR_SDRAM_CFG) 32 RW 0700_0000h
114h DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) 32 RW 0000_0000h
118h DDR SDRAM mode configuration (DDR_SDRAM_MODE) 32 RW 0000_0000h
11Ch DDR SDRAM mode configuration 2 (DDR_SDRAM_MODE_2) 32 RW 0000_0000h
120h DDR SDRAM mode control (DDR_SDRAM_MD_CNTL) 32 RW 0000_0000h
124h DDR SDRAM interval configuration (DDR_SDRAM_INTERVAL) 32 RW 0000_0000h
128h DDR SDRAM data initialization (DDR_DATA_INIT) 32 RW 0000_0000h
130h DDR SDRAM clock control (DDR_SDRAM_CLK_CNTL) 32 RW 0200_0000h
148h DDR training initialization address (DDR_INIT_ADDR) 32 RW 0000_0000h
14Ch DDR training initialization extended address (DDR_INIT_EXT_ADD 32 RW 0000_0000h
RESS)
160h DDR SDRAM timing configuration 4 (TIMING_CFG_4) 32 RW 0000_0000h
164h DDR SDRAM timing configuration 5 (TIMING_CFG_5) 32 RW 0000_0000h
168h DDR SDRAM timing configuration 6 (TIMING_CFG_6) 32 RW 0000_0000h
16Ch DDR SDRAM timing configuration 7 (TIMING_CFG_7) 32 RW 0000_0000h
170h DDR ZQ calibration control (DDR_ZQ_CNTL) 32 RW 0000_0000h
174h DDR write leveling control (DDR_WRLVL_CNTL) 32 RW 0000_0000h
17Ch DDR Self Refresh Counter (DDR_SR_CNTR) 32 RW 0000_0000h
180h DDR Register Control Words 1 (DDR_SDRAM_RCW_1) 32 RW 0000_0000h
184h DDR Register Control Words 2 (DDR_SDRAM_RCW_2) 32 RW 0000_0000h
190h DDR write leveling control 2 (DDR_WRLVL_CNTL_2) 32 RW 0000_0000h
194h DDR write leveling control 3 (DDR_WRLVL_CNTL_3) 32 RW 0000_0000h
1A0h DDR Register Control Words 3 (DDR_SDRAM_RCW_3) 32 RW 0000_0000h
1A4h DDR Register Control Words 4 (DDR_SDRAM_RCW_4) 32 RW 0000_0000h
1A8h DDR Register Control Words 5 (DDR_SDRAM_RCW_5) 32 RW 0000_0000h
1ACh DDR Register Control Words 6 (DDR_SDRAM_RCW_6) 32 RW 0000_0000h
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
702 NXP Semiconductors
Chapter 18 DDR Memory Controller
Offset Register Width Access Reset value
(In bits)
200h DDR SDRAM mode configuration 3 (DDR_SDRAM_MODE_3) 32 RW 0000_0000h
204h DDR SDRAM mode configuration 4 (DDR_SDRAM_MODE_4) 32 RW 0000_0000h
208h DDR SDRAM mode configuration 5 (DDR_SDRAM_MODE_5) 32 RW 0000_0000h
20Ch DDR SDRAM mode configuration 6 (DDR_SDRAM_MODE_6) 32 RW 0000_0000h
210h DDR SDRAM mode configuration 7 (DDR_SDRAM_MODE_7) 32 RW 0000_0000h
214h DDR SDRAM mode configuration 8 (DDR_SDRAM_MODE_8) 32 RW 0000_0000h
220h DDR SDRAM mode configuration 9 (DDR_SDRAM_MODE_9) 32 RW 0000_0000h
224h DDR SDRAM mode configuration 10 (DDR_SDRAM_MODE_10) 32 RW 0000_0000h
228h DDR SDRAM mode configuration 11 (DDR_SDRAM_MODE_11) 32 RW 0000_0000h
22Ch DDR SDRAM mode configuration 12 (DDR_SDRAM_MODE_12) 32 RW 0000_0000h
230h DDR SDRAM mode configuration 13 (DDR_SDRAM_MODE_13) 32 RW 0000_0000h
234h DDR SDRAM mode configuration 14 (DDR_SDRAM_MODE_14) 32 RW 0000_0000h
238h DDR SDRAM mode configuration 15 (DDR_SDRAM_MODE_15) 32 RW 0000_0000h
23Ch DDR SDRAM mode configuration 16 (DDR_SDRAM_MODE_16) 32 RW 0000_0000h
250h DDR SDRAM timing configuration 8 (TIMING_CFG_8) 32 RW 0000_0000h
260h DDR SDRAM control configuration 3 (DDR_SDRAM_CFG_3) 32 RW 0000_0000h
400h DQ mapping register 0 (DDR_DQ_MAP0) 32 RW 0000_0000h
404h DQ mapping register 1 (DDR_DQ_MAP1) 32 RW 0000_0000h
408h DQ mapping register 2 (DDR_DQ_MAP2) 32 RW 0000_0000h
40Ch DQ mapping register 3 (DDR_DQ_MAP3) 32 RW 0000_0000h
B20h DDR Debug Status Register 1 (DDRDSR_1) 32 RO 0000_8080h
B24h DDR Debug Status Register 2 (DDRDSR_2) 32 RW 8000_0000h
B28h DDR Control Driver Register 1 (DDRCDR_1) 32 RW 0000_8080h
B2Ch DDR Control Driver Register 2 (DDRCDR_2) 32 RW 0800_0000h
BF8h DDR IP block revision 1 (DDR_IP_REV1) 32 RO 0002_0501h
BFCh DDR IP block revision 2 (DDR_IP_REV2) 32 RO 0000_0000h
D00h DDR Memory Test Control Register (DDR_MTCR) 32 RW 0000_0000h
D20h - D44h DDR Memory Test Pattern n Register (DDR_MTP1 - DDR_MTP10) 32 RW 0000_0000h
D60h DDR Memory Test Start Extended Address (DDR_MT_ST_EXT_AD 32 RW 0000_0000h
DR)
D64h DDR Memory Test Start Address (DDR_MT_ST_ADDR) 32 RW 0000_0000h
D68h DDR Memory Test End Extended Address (DDR_MT_END_EXT_A 32 RW 0000_0000h
DDR)
D6Ch DDR Memory Test End Address (DDR_MT_END_ADDR) 32 RW 0000_0000h
E00h Memory data path error injection mask high (DATA_ERR_INJECT_ 32 RW 0000_0000h
HI)
E04h Memory data path error injection mask low (DATA_ERR_INJECT_ 32 RW 0000_0000h
LO)
E08h Memory data path error injection mask ECC (ECC_ERR_INJECT) 32 RW 0000_0000h
E20h Memory data path read capture high (CAPTURE_DATA_HI) 32 RW 0000_0000h
E24h Memory data path read capture low (CAPTURE_DATA_LO) 32 RW 0000_0000h
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 703
DDR register descriptions
Offset Register Width Access Reset value
(In bits)
E28h Memory data path read capture ECC (CAPTURE_ECC) 32 RW 0000_0000h
E40h Memory error detect (ERR_DETECT) 32 W1C 0000_0000h
E44h Memory error disable (ERR_DISABLE) 32 RW 0000_0000h
E48h Memory error interrupt enable (ERR_INT_EN) 32 RW 0000_0000h
E4Ch Memory error attributes capture (CAPTURE_ATTRIBUTES) 32 RW 0000_0000h
E50h Memory error address capture (CAPTURE_ADDRESS) 32 RW 0000_0000h
E54h Memory error extended address capture (CAPTURE_EXT_ADDR 32 RW 0000_0000h
ESS)
E58h Single-Bit ECC memory error management (ERR_SBE) 32 RW 0000_0000h
18.4.2 Chip select a memory bounds (CS0_BNDS - CS3_BNDS)
18.4.2.1 Offset
Register Offset
CS0_BNDS 0h
CS1_BNDS 8h
CS2_BNDS 10h
CS3_BNDS 18h
18.4.2.2 Function
The chip select bounds registers (CSn_BNDS) define the starting and ending address of
the memory space that corresponds to the individual chip selects. Note that the size
specified in CSn_BNDS should equal the size of physical DRAM. Also, note that EAn
must be greater than or equal to SAn.
If chip select interleaving is enabled, all fields in the lower interleaved chip select will be
used, and the other chip selects' bounds registers will be unused. For example, if chip
selects 0 and 1 are interleaved, all fields in CS0_BNDS will be used, and all fields in
CS1_BNDS will be unused.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
704 NXP Semiconductors
Chapter 18 DDR Memory Controller
18.4.2.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
SA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
EA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.4.2.4 Fields
Field Function
0-15 Starting Address.
SA Starting address for chip select (bank) n.This value is compared against the 16 msbs of the 40-bit
address.
16-31 Ending Address.
EA Ending address for chip select (bank)n. This value is compared against the 16 msbs of the 40-bit
address.
18.4.3 Chip select a configuration (CS0_CONFIG - CS3_CONFIG)
18.4.3.1 Offset
Register Offset
CS0_CONFIG 80h
CS1_CONFIG 84h
CS2_CONFIG 88h
CS3_CONFIG 8Ch
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 705
DDR register descriptions
18.4.3.2 Function
The chip select configuration (CSn_CONFIG) registers enable the DDR chip selects and
set the number of row and column bits used for each chip select. These registers should
be loaded with the correct number of row and column bits for each SDRAM. Because
CSn_CONFIG[ROW_BITS_CS_n, COL_BITS_CS_n] establish address multiplexing,
the user should take great care to set these values correctly.
If chip select interleaving is enabled, then all fields in the lower interleaved chip select
will be used, and the other registers' fields will be unused, with the exception of the
ODT_RD_CFG and ODT_WR_CFG fields. For example, if chip selects 0 and 1 are
interleaved, all fields in CS0_CONFIG will be used, but only the ODT_RD_CFG and
ODT_WR_CFG fields in CS1_CONFIG will be used.
18.4.3.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
ODT_WR_CFG
ODT_RD_CFG
Reserved
Reserved
AP_EN
CS_E
W
N
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
ROW_BITS_CS
COL_BITS_CS
BA_BITS_CS
BG_BITS_C
Reserved
Reserved
Reserved
W
S
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.4.3.4 Fields
Field Function
0 Chip Select Enable.
CS_EN Chip select nenable
0b - Chip select nis not active
1b - Chip select nis active and assumes the state set in CSn_BNDS.
1-7 Reserved.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
706 NXP Semiconductors
Chapter 18 DDR Memory Controller
Field Function
—
8 Auto Precharge Enable.
AP_EN Chip select nauto-precharge enable
0b - Chip select will only be auto-precharged if global auto-precharge mode is enabled
(DDR_SDRAM_INTERVAL[BSTOPRE] = 0).
1b - Chip select will always issue an auto-precharge for read and write transactions.
9-11 On-Die Termination Read Config.
ODT_RD_CFG ODT for reads configuration. Note that CAS latency plus additive latency must be at least 3 cycles for
ODT_RD_CFG to be enabled.
000b - Never assert ODT for reads
001b - Assert ODT only during reads to CSa
010b - Assert ODT only during reads to other chip selects
011b - Assert ODT only during reads to other DIMM modules. It is assumed that CS0 and CS1 are
on the same DIMM module, whereas CS2 and CS3 are on a separate DIMM module.
100b - Assert ODT for all reads
101b - Assert ODT only during transactions to same DIMM
110b - Assert ODT only during transactions to own CS and other DIMM.
111b - Assert ODT only during transactions to other CS in same DIMM.
12 Reserved.
—
13-15 On-Die Termination Write Config.
ODT_WR_CFG ODT for writes configuration. Note that write latency plus additive latency must be at least 3 cycles for
ODT _WR_CFG to be enabled.
000b - Never assert ODT for writes
001b - Assert ODT only during writes to CSn
010b - Assert ODT only during writes to other chip selects
011b - Assert ODT only during writes to other DIMM modules. It is assumed that CS0 and CS1 are
on the same DIMM module, whereas CS2 and CS3 are on a separate DIMM module.
100b - Assert ODT for all writes
101b - Assert ODT only during transactions to same DIMM
110b - Assert ODT only during transactions to own CS and other DIMM.
111b - Assert ODT only during transactions to other CS in same DIMM.
16-17 Bank Address Bits.
BA_BITS_CS Number of bank bits for SDRAM on chip selectn. These bits correspond to the sub-bank bits driven on
MBAn. Note that if DDR4 is used, this must be set to 00, as 8 sub-banks are not supported when also
using bank groups.
00b - 2 logical bank bits
01b - Reserved
10b - Reserved
11b - Reserved
18-20 Reserved.
—
21-23 Row Bits.
ROW_BITS_CS Number of row bits for SDRAM on chip selectn.
000b - 12 row bits
001b - 13 row bits
010b - 14 row bits
011b - 15 row bits
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 707
DDR register descriptions
Field Function
100b - 16 row bits
101b - 17 row bits
110b - 18 row bits
111b - Reserved
24-25 Reserved.
—
26-27 Bank Group Bits.
BG_BITS_CS Number of bank group bits for SDRAM on chip selectn. In addition, it is illegal to use BA_BITS_CS_n
equal to 01 if DDR4 bank groups are used.
00b - 0 bank group bits
01b - 1 bank group bit
10b - 2 bank group bits
11b - Reserved
28 Reserved.
—
29-31 Column Bits.
COL_BITS_CS Number of column bits for SDRAM on chip selectn. The decoding is as follows:
000b - 8 column bits
001b - 9 column bits
010b - 10 column bits
011b - 11 column bits
100b - Reserved
101b - Reserved
110b - Reserved
111b - Reserved
18.4.4 DDR SDRAM timing configuration 3 (TIMING_CFG_3)
18.4.4.1 Offset
Register Offset
TIMING_CFG_3 100h
18.4.4.2 Function
DDR SDRAM timing configuration register 3 sets the extended refresh recovery time,
which is combined with TIMING_CFG_1[REFREC] to determine the full refresh
recovery time.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
708 NXP Semiconductors
Chapter 18 DDR Memory Controller
18.4.4.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
EXT_PRETOACT
EXT_ACTTOPRE
EXT_ACTTORW
EXT_REFRE
Reserved
Reserved
Reserved
W
C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R EXT_ADD_LAT
EXT_CASLAT
EXT_WRRE
CNTL_ADJ
Reserved
Reserved
Reserved
Reserved
W
Reset 0 0 0 0 0 0 0 C 0 0 0 0 0 0 0 0 0
18.4.4.4 Fields
Field Function
0-2 Reserved.
—
3 Extended Precharge to Activate.
EXT_PRETOAC Extended precharge-to-activate interval (tRP). Determines the number of clock cycles from a precharge
T command until an activate or refresh command is allowed. This field is concatenated with
TIMING_CFG_1[PRETOACT] to obtain a 5-bit value for the total precharge to activate time.
0b - 0 clocks
1b - 16 clocks
4-5 Reserved.
—
6-7 Extended Activate to Precharge.
EXT_ACTTOPR Extended Activate to precharge interval ( tR A S ). Determines the number of clock cycles from an activate
E command until a precharge command is allowed. This field is concatenated with
TIMING_CFG_1[ACTTOPRE] to obtain a 6-bit value for the total activate to precharge. Note that a 6-bit
value of 00_0000 is the same as a 6-bit value of 01_0000. Both values represent 16 cycles.
00b - 0 clocks
01b - 16 clocks
10b - 32 clocks
11b - 48 clocks
8 Reserved.
—
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 709
DDR register descriptions
Field Function
9 Extended Activate to Read/Write.
EXT_ACTTOR Extended activate to read/write interval for SDRAM (tRCD). Controls the number of clock cycles from an
W activate command until a read or write command is allowed. This field is concatenated with
TIMING_CFG_1[ACTTORW] to obtain a 5-bit value for the total activate to read/write time.
10-15 Extended Refresh Recovery.
EXT_REFREC Extended refresh recovery time ( tRFC). Controls the number of clock cycles from a refresh command until
an activate command is allowed. This field is concatenated with TIMING_CFG_1[REFREC] to obtain a
10-bit value for the total refresh recovery. Note that hardware adds an additional 8 clock cycles to the
final, 10-bit value of the refresh recovery, such that tRFC is calculated as follows: tRFC = {EXT_REFREC ||
REFREC} + 8. (Settings greater than 101111b are reserved.)
All values of less than 0b110000 are legal; in this case the number of cycles is [setting] × 16. Sample
values are shown below. Settings of 0b110000 or greater are reserved.
000000b - 0 clocks
000001b - 16 clocks
000010b - 32 clocks
101110b - 736 clocks
101111b - 752 clocks
110000-111111b - Reserved
16-17 Reserved.
—
18-19 Extended CAS Latency.
EXT_CASLAT Number of clock cycles between registration of a READ command by the SDRAM and the availability of
the first output data. If a READ command is registered at clock edge n and the latency is m clocks, data is
available nominally coincident with clock edge n + m. This field is concatenated with
TIMING_CFG_1[CASLAT] to obtain a 5-bit value for the total CAS latency. Note that the value of this field
is added to the programmed value in TIMING_CFG_1[CASLAT]. The largest total CAS latency supported
is 20 clocks.
00b - 0 clocks
01b - 8 clocks
10b - 16 clocks
11b - Reserved
20 Reserved
—
21 Extended Additive Latency.
EXT_ADD_LAT The additive latency must be set to a value less than TIMING_CFG_1[ACTTORW]. Note that the value of
this field is added to the programmed value in TIMING_CFG_2[ADD_LAT]. The largest total additive
latency supported is 19 clocks.
0b - 0 clocks
1b - 16 clocks
22 Reserved.
—
23 Extended Write Recovery.
EXT_WRREC Extended last data to precharge minimum interval (tWR). Determines the number of clock cycles from the
last data associated with a write command until a precharge command is allowed. If
DDR_SDRAM_CFG_2[OBC_CFG] is set, then this field needs to be programmed to (tWR + 2 cycles).
This field is concatenated with TIMING_CFG_1[WRREC] to obtain a 5-bit value for the total write
recovery time.
0b - 0 clocks
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
710 NXP Semiconductors
Chapter 18 DDR Memory Controller
Field Function
1b - 16 clocks
24-28 Reserved.
—
29-31 Control Adjust.
CNTL_ADJ Controls the amount of delay to add to the lightly loaded control signals with respect to all other DRAM
address and command signals. The signals affected by this field are MODTn, MCSn_B, and MCKEn.
000b - MODTn, MCSn_B, and MCKEn will be launched aligned with the other DRAM address and
control signals.
001b - MODTn, MCSn_B, and MCKEn will be launched 1/4 DDR clock cycle later than the other
DRAM address and control signals.
010b - MODTn, MCSn_B, and MCKEn will be launched 1/2 DDR clock cycle later than the other
DRAM address and control signals.
011b - MODTn, MCSn_B, and MCKEn will be launched 3/4 DDR clock cycle later than the other
DRAM address and control signals.
100b - MODTn, MCSn_B, and MCKEn will be launched 1 DDR clock cycle later than the other
DRAM address and control signals.
101b - MODTn, MCSn_B, and MCKEn will be launched 5/4 DDR clock cycles later than the other
DRAM address and control signals.
110b - Reserved
111b - Reserved
18.4.5 DDR SDRAM timing configuration 0 (TIMING_CFG_0)
18.4.5.1 Offset
Register Offset
TIMING_CFG_0 104h
18.4.5.2 Function
DDR SDRAM timing configuration register 0 sets the number of clock cycles between
various SDRAM control commands.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 711
DDR register descriptions
18.4.5.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
RWT WRT RRT WWT ACT_PD_EXIT PRE_PD_EXIT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
EXT_PRE_PD_EXI
MRS_CYC
Reserved
W
T
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
18.4.5.4 Fields
Field Function
0-1 Read-to-write Turnaround.
RWT Specifies how many extra cycles will be added between a read to write turnaround. If 0 clocks is chosen,
then the DDR controller will use a fixed number based on the CAS latency and write latency. Choosing a
value other than 0 adds extra cycles past this default calculation. As a default the DDR controller will
determine the read-to-write turnaround as CL - WL + BL/2 + 2. In this equation, CL is the CAS latency
rounded up to the next integer, WL is the programmed write latency, and BL is the burst length. This field
is concatenated with TIMING_CFG_4[EXT_RWT] to obtain a 4-bit value for the total read-to-write
turnaround
00b - 0 clocks
01b - 1 clock
10b - 2 clocks
11b - 3 clocks
2-3 Write-to-read Turnaround.
WRT Specifies how many extra cycles will be added between a write to read turnaround. If 0 clocks is chosen,
then the DDR controller will use a fixed number based on the, read latency, and write latency. Choosing a
value other than 0 adds extra cycles past this default calculation. As a default, the DDR controller will
determine the write-to-read turnaround as WL - CL + BL/2 + 1. In this equation, CL is the CAS latency
rounded down to the next integer, WL is the programmed write latency, and BL is the burst length. This
field is concatenated with TIMING_CFG_4[EXT_WRT] to obtain a 3-bit value for the total write-to-read
turnaround
00b - 0 clocks
01b - 1 clock
10b - 2 clocks
11b - 3 clocks
4-5 Read-to-read Turnaround.
RRT
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
712 NXP Semiconductors
Chapter 18 DDR Memory Controller
Field Function
Specifies how many extra cycles will be added between reads to different chip selects. As a default, 3
cycles will be required between read commands to different chip selects. Extra cycles may be added with
this field. Note: If 8-beat bursts are enabled, then 5 cycles will be the default. This field is concatenated
with TIMING_CFG_4[EXT_RRT] to obtain a 3-bit value for the total read-to-read turnaround.
00b - 0 clocks
01b - 1 clock
10b - 2 clocks
11b - 3 clocks
6-7 Write-to-write Turnaround.
WWT Specifies how many extra cycles will be added between writes to different chip selects. As a default, 2
cycles will be required between write commands to different chip selects. Extra cycles may be added with
this field. Note: If 8-beat bursts are enabled, then 4 cycles will be the default. This field is concatenated
with TIMING_CFG_4[EXT_WWT] to obtain a 3-bit value for the total write-to-write turnaround
00b - 0 clocks
01b - 1 clock
10b - 2 clocks
11b - 3 clocks
8-11 Active Powerdown Exit.
ACT_PD_EXIT Active powerdown exit timing (tXP). Specifies how many clock cycles to wait after exiting active
powerdown before issuing any command.
0000b - Reserved
0001b - 1 clock
0010b - 2 clocks
0011b - 3 clocks
0100b - 4 clocks
0101b - 5 clocks
0110b - 6 clocks
0111b - 7 clocks
1000b - 8 clocks
1001b - 9 clocks
1010b - 10 clocks
1011b - 11 clocks
1100b - 12 clocks
1101b - 13 clocks
1110b - 14 clocks
1111b - 15 clocks
12-15 Precharge Powerdown Exit.
PRE_PD_EXIT Precharge powerdown exit timing (tXP). Specifies how many clock cycles to wait after exiting precharge
powerdown before issuing any command. This field is concatenated with
TIMING_CFG_0[EXT_PRE_PD_EXIT] to obtain a 6-bit value for the total precharge powerdown exit
timing.
0000b - Reserved
0001b - 1 clock
0010b - 2 clocks
0011b - 3 clocks
0100b - 4 clocks
0101b - 5 clocks
0110b - 6 clocks
0111b - 7 clocks
1000b - 8 clocks
1001b - 9 clocks
1010b - 10 clocks
1011b - 11 clocks
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 713
DDR register descriptions
Field Function
1100b - 12 clocks
1101b - 13 clocks
1110b - 14 clocks
1111b - 15 clocks
16-17 Extended Precharge Powerdown Exit.
EXT_PRE_PD_ Extended precharge powerdown exit timing (tXP). Specifies how many clock cycles to wait after exiting
EXIT precharge powerdown before issuing any command. Note the decoding for this field is not a straight
decode. This field is concatenated with TIMING_CFG_0[PRE_PD_EXIT] to obtain a 6-bit value for the
total precharge powerdown exit timing.
00b - 0 clocks
01b - 16 clocks
10b - 32 clocks
11b - 48 clocks
18-26
—
27-31 Mode Register Set Cycle Time.
MRS_CYC Mode register set cycle time (tMRD, tMOD). Specifies the number of cycles that must pass after a Mode
Register Set command until any other command. This should be set to the greater of tMRD and tMOD). If
command/address latency (CAL) mode is used for DDR4, then this field should be set to the greater of
tMRD_CAL and tMOD_CAL). In addition, this field should be programmed higher than
TIMING_CFG_7[CS_TO_CMD] if using CAL mode.
00000b - Reserved
00001b - 1 clock
00010b - 2 clocks
00011b - 3 clocks
00100b - 4 clocks
00101b - 5 clocks
00110b - 6 clocks
00111b - 7 clocks
01000b - 8 clocks
01001b - 9 clocks
01010b - 10 clocks
01011b - 11 clocks
01100b - 12 clocks
01101b - 13 clocks
01110b - 14 clocks
01111b - 15 clocks
10000b - 16 clocks
10001b - 17 clocks
10010b - 18 clocks
10011b - 19 clocks
10100b - 20 clocks
10101b - 21 clocks
10110b - 22 clocks
10111b - 23 clocks
11000b - 24 clocks
11001b - 25 clocks
11010b - 26 clocks
11011b - 27 clocks
11100b - 28 clocks
11101b - 29 clocks
11110b - 30 clocks
11111b - 31 clocks
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
714 NXP Semiconductors
Chapter 18 DDR Memory Controller
18.4.6 DDR SDRAM timing configuration 1 (TIMING_CFG_1)
18.4.6.1 Offset
Register Offset
TIMING_CFG_1 108h
18.4.6.2 Function
DDR SDRAM timing configuration register 1 sets the number of clock cycles between
various SDRAM control commands.
18.4.6.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
PRETOACT
ACTTOPRE
ACTTORW
CASLAT
RSRV
W
D
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
REFREC WRREC ACTTOACT WRTORD
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.4.6.4 Fields
Field Function
0-3 Precharge-to-Activate.
PRETOACT Precharge-to-activate interval (tRP). Determines the number of clock cycles from a precharge command
until an activate or refresh command is allowed. This field is concatenated with
TIMING_CFG_3[EXT_PRETOACT] to obtain a 5-bit value for the total precharge to activate time.
0000b - Reserved
0001b - 1 clock
0010b - 2 clocks
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 715
DDR register descriptions
Field Function
0011b - 3 clocks
0100b - 4 clocks
0101b - 5 clocks
0110b - 6 clocks
0111b - 7 clocks
1000b - 8 clocks
1001b - 9 clocks
1010b - 10 clocks
1011b - 11 clocks
1100b - 12 clocks
1101b - 13 clocks
1110b - 14 clocks
1111b - 15 clocks
4-7 Activate-to-Precharge.
ACTTOPRE Activate to precharge interval (tRAS). Determines the number of clock cycles from an activate command
until a precharge command is allowed. This field is concatenated with
TIMING_CFG_3[EXT_ACTTOPRE] to obtain a 6-bit value for the total activate to precharge time. Note
that the decode of 0000-0011 is equal to 16-19 clocks when TIMING_CFG_3[EXT_ACTTOPRE] = 00,
but it is equal to 0-3 clocks when TIMING_CFG_3[EXT_ACTTOPRE] = 01, 10, or 11.
0000b - 16 clocks
0001b - 17 clocks
0010b - 18 clocks
0011b - 19 clocks
0100b - 4 clock
0101b - 5 clocks
0110b - 6 clocks
0111b - 7 clocks
1000b - 8 clocks
1001b - 9 clocks
1010b - 10 clocks
1011b - 11 clocks
1100b - 12 clocks
1101b - 13 clocks
1110b - 14 clocks
1111b - 15 clocks
8-11 Activate-to-Read/Write.
ACTTORW Activate to read/write interval for SDRAM (tRCD). Controls the number of clock cycles from an activate
command until a read or write command is allowed. This field is concatenated with
TIMING_CFG_3[EXT_ACTTORW] to obtain a 5-bit value for the total activate to read/write time.
0000b - Reserved
0001b - 1 clock
0010b - 2 clocks
0011b - 3 clocks
0100b - 4 clocks
0101b - 5 clocks
0110b - 6 clocks
0111b - 7 clocks
1000b - 8 clocks
1001b - 9 clocks
1010b - 10 clocks
1011b - 11 clocks
1100b - 12 clocks
1101b - 13 clocks
1110b - 14 clocks
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
716 NXP Semiconductors
Chapter 18 DDR Memory Controller
Field Function
1111b - 15 clocks
12-14 CAS Latency.
CASLAT Number of clock cycles between registration of a READ command by the SDRAM and the availability of
the first output data. If a READ command is registered at clock edge n and the latency is m clocks, data is
available nominally coincident with clock edge n + m. This field is concatenated with
TIMING_CFG_3[EXT_CASLAT] to obtain a 5-bit value for the total CAS latency. This value must be
programmed at initialization as described in DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_
2)) Note that the largest total CAS latency supported is 20 clocks.
000b - 1 clock
001b - 2 clocks
010b - 3 clocks
011b - 4 clocks
100b - 5 clocks
101b - 6 clocks
110b - 7 clocks
111b - 8 clocks
15 Reserved.
RSRVD This bit is reserved, but it is readable and writeable.
16-19 Refresh recovery.
REFREC Refresh recovery time (tRFC). Controls the number of clock cycles from a refresh command until an
activate command is allowed. This field is concatenated with TIMING_CFG_3[EXTREFREC] to obtain a
10-bit value for the total refresh recovery. Note that hardware adds an additional 8 clock cycles to the
final, 10-bit value of the refresh recovery, such that tRFC is calculated as follows: tRFC = {EXT_REFREC ||
REFREC} + 8.
0000b - 8 clocks
0001b - 9 clocks
0010b - 10 clocks
0011b - 11 clocks
1111b - 23 clocks
20-23 Write recovery.
WRREC Last data to precharge minimum interval (tWR). Determines the number of clock cycles from the last data
associated with a write command until a precharge command is allowed. If
DDR_SDRAM_CFG_2[OBC_CFG] is set, then this field needs to be programmed to (tWR + 2 cycles).
This field is concatenated with TIMING_CFG_3[EXT_WRREC] to obtain a 5-bit value for the total write
recovery time.
0000b - Reserved
0001b - 1 clock
0010b - 2 clocks
0011b - 3 clocks
0100b - 4 clocks
0101b - 5 clocks
0110b - 6 clocks
0111b - 7 clocks
1000b - 8 clocks
1001b - 9 clocks
1010b - 10 clocks
1011b - 11 clocks
1100b - 12 clocks
1101b - 13 clocks
1110b - 14 clocks
1111b - 15 clocks
24-27 Activate-to-activate.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 717
DDR register descriptions
Field Function
ACTTOACT Activate-to-activate interval (tRRD). Number of clock cycles from an activate command until another
activate command is allowed for a different logical bank in the same physical bank (chip select).
0000b - Reserved
0001b - 1 clock
0010b - 2 clocks
0011b - 3 clocks
0100b - 4 clocks
0101b - 5 clocks
0110b - 6 clocks
0111b - 7 clocks
1000b - 8 clocks
1001b - 9 clocks
1010b - 10 clocks
1011b - 11 clocks
1100b - 12 clocks
1101b - 13 clocks
1110b - 14 clocks
1111b - 15 clocks
28-31 Write-to-read.
WRTORD Last write data pair to read command issue interval (tWTR). Number of clock cycles between the last write
data pair and the subsequent read command to the same physical bank. If
DDR_SDRAM_CFG_2[OBC_CFG] is set, then this field needs to be programmed to (tWTR + 2 cycles).
0000b - Reserved
0001b - 1 clock
0010b - 2 clocks
0011b - 3 clocks
0100b - 4 clocks
0101b - 5 clocks
0110b - 6 clocks
0111b - 7 clocks
1000b - 8 clocks
1001b - 9 clocks
1010b - 10 clocks
1011b - 11 clocks
1100b - 12 clocks
1101b - 13 clocks
1110b - 14 clocks
1111b - 15 clocks
18.4.7 DDR SDRAM timing configuration 2 (TIMING_CFG_2)
18.4.7.1 Offset
Register Offset
TIMING_CFG_2 10Ch
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
718 NXP Semiconductors
Chapter 18 DDR Memory Controller
18.4.7.2 Function
DDR SDRAM timing configuration 2 sets the clock delay to data for writes.
18.4.7.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
EXT_WR_LAT
RD_TO_PR
ADD_LAT
WR_LAT
Reserved
Reserved
W
E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
WR_DATA_DELAY
FOUR_ACT
RD_TO_PR
CKE_PL
W
S
E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.4.7.4 Fields
Field Function
0-3 Additive Latency.
ADD_LAT The additive latency must be set to a value less than TIMING_CFG_1[ACTTORW]. This field is added to
TIMING_CFG_3]EXT_ADD_LAT]. The maximum total additive latency supported is 19 clocks.
0000b - 0 clocks
0001b - 1 clock
0010b - 2 clocks
0011b - 3 clocks
0100b - 4 clocks
0101b - 5 clocks
0110b - 6 clocks
0111b - 7 clocks
1000b - 8 clocks
1001b - 9 clocks
1010b - 10 clocks
1011b - 11 clocks
1100b - 12 clocks
1101b - 13 clocks
1110b - 14 clocks
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 719
DDR register descriptions
Field Function
1111b - Reserved
4-8 Reserved.
—
9-12 Write Latency.
WR_LAT Note that the total write latency is equal to WR_LAT + ADD_LAT. Note that the total write latency must be
at least 6 cycles if using unbuffered DIMMs in 1T timing mode. Note that this field is added to
TIMING_CFG_2[EXT_WR_LAT]. The maximum write latency supported before adding the additive
latency is 18 clocks. Note that values of 0b0000 to 0b0101 are reserved unless
TIMING_CFG_2[EXT_WR_LAT] is programmed to a non-zero value.
0000b - 0 clocks
0001b - 1 clock
0010b - 2 clocks
0011b - 3 clocks
0100b - 4 clocks
0101b - 5 clocks
0110b - 6 clocks
0111b - 7 clocks
1000b - 8 clocks
1001b - 9 clocks
1010b - 10 clocks
1011b - 11 clocks
1100b - 12 clocks
1101b - 13 clocks
1110b - 14 clocks
1111b - 15 clocks
13 Extended Write Latency.
EXT_WR_LAT Note that the value of this field is added to the programmed value in TIMING_CFG_2[WR_LAT]. The
largest total write latency supported before adding the additive latency is 18 clocks.
0b - 0 clocks
1b - 16 clocks
14 Reserved.
—
15-18 Read-to-Precharge.
RD_TO_PRE Read to precharge (tRTP). If DDR_SDRAM_CFG_2[OBC_CFG] is set, then this field needs to be
programmed to (tRTP + 2 cycles).
0000b - Reserved
0001b - 1 clock
0010b - 2 clocks
0011b - 3 clocks
0100b - 4 clocks
0101b - 5 clocks
0110b - 6 clocks
0111b - 7 clocks
1000b - 8 clocks
1001b - 9 clocks
1010b - 10 clocks
1011b - 11 clocks
1100b - 12 clocks
1101b - 13 clocks
1110b - 14 clocks
1111b - 15 clocks
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
720 NXP Semiconductors
Chapter 18 DDR Memory Controller
Field Function
19-22 Write Data Delay.
WR_DATA_DEL Write command to write data strobe timing adjustment. Controls the amount of delay applied to the data
AY and data strobes for writes. See DDR SDRAM Write Timing Adjustments for details. The write preamble
will be driven high for 1/2 DRAM cycle, and then it will be driven low for 1/2 DRAM cycle.
0000b - 0 clock delay
0001b - 2 clock delay
0010b - 1/4 clock delay
0011b - 9/4 clock delay
0100b - 1/2 clock delay
0101b - 5/2 clock delay
0110b - 3/4 clock delay
0111b - Reserved
1000b - 1 clock delay
1001b - Reserved
1010b - 5/4 clock delay
1011b - Reserved
1100b - 3/2 clock delay
1101b - Reserved
1110b - 7/4 clock delay
1111b - Reserved
23-25 CKE Pulse.
CKE_PLS Minimum CKE pulse width (tCKE). This field is concatenated with TIMING_CFG_3[EXT_CKE_PLS] to
obtain a 4-bit value for the total minimum CKE pulse width.
000b - 8 clocks
001b - 1 clock
010b - 2 clocks
011b - 3 clocks
100b - 4 clocks
101b - 5 clocks
110b - 6 clocks
111b - 7 clocks
26-31 Four Activate.
FOUR_ACT Window for four activates (tFAW).
NOTE: If tFAW requires FOUR_ACT to be set higher than the supported values, then
TIMING_CFG_1[ACTTOACT] should be programmed to avoid a tFAW violation. This can be done
by programming -> TIMING_CFG_1[ACTTOACT] = rounded_up[max(tRRD{_S}, tFAW/4)].
000000b - Reserved
000001b - 1 cycle
000010b - 2 cycles
000011b - 3 cycles
000100b - 4 cycles
011111b - 31 cycles
100000b - 32 cycles
18.4.8 DDR SDRAM control configuration (DDR_SDRAM_CFG)
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 721
DDR register descriptions
18.4.8.1 Offset
Register Offset
DDR_SDRAM_CFG 110h
18.4.8.2 Function
The DDR SDRAM control configuration register enables the interface logic and specifies
certain operating features such as self refreshing, error checking and correcting, and
dynamic power management.
18.4.8.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
SDRAM_TYPE
DYN_PWR
MEM_EN
Reserved
Reserved
Reserved
Reserved
T3_EN
ECC_E
DBW
SRE
BE_
W
N
8
N
Reset 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
BA_INTLV_CTL
ACC_ECC_EN
MEM_HALT
Reserved
T2_EN
HS
BI
W
E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.4.8.4 Fields
Field Function
0 Memory Controller Enable.
0b - SDRAM interface logic is disabled.
MEM_EN
1b - SDRAM interface logic is enabled. Must not be set until all other memory configuration
parameters have been appropriately configured by initialization code.
1 Self Refresh Enable.
SREN
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
722 NXP Semiconductors
Chapter 18 DDR Memory Controller
Field Function
0b - SDRAM self refresh is disabled during sleep. Whenever self-refresh is disabled, the system is
responsible for preserving the integrity of SDRAM during sleep.
1b - SDRAM self refresh is enabled during sleep.
2 ECC Enable.
ECC_EN Note that uncorrectable read errors may cause an interrupt.
NOTE: If this bit is set to 1, DDR_SDRAM_CFG[ACC_ECC_EN] must be set to 1 as well.
0b - No ECC errors are reported. No ECC interrupts are generated.
1b - ECC is enabled.
3 Reserved.
—
4 Reserved.
—
5-7 SDRAM Type.
SDRAM_TYPE Type of SDRAM device to be used. This field will be used when issuing the automatic hardware
initialization sequence to DRAM via Mode Register Set and Extended Mode Register Set commands.
Default value is 111.
000-100 Reserved
101 DDR4 SDRAM
110 Reserved
111 DDR3-type SDRAM
8-9 Reserved.
—
10 Dynamic Power Management.
0b - Dynamic power management mode is disabled.
DYN_PWR
1b - Dynamic power management mode is enabled. If there is no ongoing memory activity, the
SDRAM CKE signal is negated.
11-12 DRAM Data Bus Width.
00b - Reserved
DBW
01b - 32-bit bus is used.
10b - 16-bit bus is used.
11b - Reserved
13 8-Beat Burst Enable.
0b - 4-beat bursts are used on the DRAM interface. This is only supported if
BE_8
DDR_SDRAM_CFG_2[OBC_CFG] is also set.
1b - 8-beat bursts are used on the DRAM interface.
14 Reserved.
—
15 3T Timing Enable.
T3_EN This field cannot be set if DDR_SDRAM_CFG[T2_EN] is also set. This field cannot be used with a 32-bit
bus or a 16-bit bus if 4-beat bursts are used.
NOTE: 3T timing may not be used with 4-beat bursts, unless DDR_SDRAM_CFG_2[OBC_CFG] is set.
0b - 1T timing is enabled if T2_EN is cleared. The DRAM command/address are held for only 1
cycle on the DRAM bus.
1b - 3T timing is enabled. The DRAM command/address are held for 3 full cycles on the DRAM bus
for every DRAM transaction. However, the chip select is only held for the third cycle.
16 2T Timing Enable.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 723
DDR register descriptions
Field Function
T2_EN This field should not be set if DDR_SDRAM_CFG[T3_EN] is set.
0b - 1T timing is enabled if T3_EN is cleared. The DRAM command/address are held for only 1
cycle on the DRAM bus.
1b - 2T timing is enabled. The DRAM command/address are held for 2 full cycles on the DRAM bus
for every DRAM transaction. However, the chip select is only held for the second cycle.
17-23 Bank (chip select) interleaving control.
BA_INTLV_CTL Set this field only when using bank interleaving.
('x' denotes a don't care bit value. All unlisted field values are reserved.)
0000000 No external memory banks are interleaved
1000000 External memory banks 0 and 1 are interleaved
0100000 External memory banks 2 and 3 are interleaved
1100000 External memory banks 0 and 1 are interleaved together and banks 2 and 3 are interleaved
together
xx00100 External memory banks 0 through 3 are all interleaved together
24-27 Reserved.
—
28 Half-Strength Enable.
HSE Sets I/O driver impedance to calibrate to half strength. This calibrated impedance will be used by the
MDIC, address/command, data, and clock impedance values, but only if automatic hardware calibration is
enabled and the corresponding group's software override is disabled in the DDR control driver register(s)
described in DDR Control Driver Register 1 (DDRCDR_1) and DDR Control Driver Register 2 (DDRCDR_
2)
0b - I/O driver impedance will be calibrated to full strength.
1b - I/O driver impedance will be calibrated to half strength.
29 Accumulated ECC enable.
ACC_ECC_EN This can be used to save ECC pins/wires when using a DDR data bus width smaller than 64-bits. In this
mode, the 8-bit ECC code will be transmitted/received across several beats, and it will be used to check
64-bits of data once 8-bits of ECC are accumulated. Note that using this mode guarantees that all single-
bit ECC errors are corrected and detected for every 64-bits of data, and every 2-bit ECC error is detected
for 64-bits of data. Unused ECC bits are driven high by the memory controller during write bursts if
ACC_ECC_EN is set.
NOTE: This bit must be set to 1 when ECC is enabled.
0b - Accumulated ECC is disabled
1b - Accumulated ECC is enabled
30 Memory Controller Halt.
MEM_HALT DDR memory controller halt. When this bit is set, the memory controller will not accept any new data
read/write transactions to DDR SDRAM until the bit is cleared again. This can be used when bypassing
initialization and forcing MODE REGISTER SET commands through software.
0b - DDR controller will accept new transactions.
1b - DDR controller will finish any remaining transactions, and then it will remain halted until this bit
is cleared by software.
31 Bypass Initialization.
BI See DDR training initialization address (DDR_INIT_ADDR) for details on avoiding ECC errors in this
mode.
0b - DDR controller will cycle through initialization routine based on SDRAM_TYPE
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
724 NXP Semiconductors
Chapter 18 DDR Memory Controller
Field Function
1b - Initialization routine will be bypassed. Software is responsible for initializing memory through
DDR_SDRAM_MD_CNTL register. If software is initializing memory, then the MEM_HALT bit can
be set to prevent the DDR controller from issuing transactions during the initialization sequence.
Note that the DDR controller will not issue a DLL reset to the DRAMs when bypassing the
initialization routine, regardless of the value of DDR_SDRAM_CFG[DLL_RST_DIS]. If a DLL reset
is required, then the controller should be forced to enter and exit self refresh after the controller is
enabled.
18.4.9 DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_
2)
18.4.9.1 Offset
Register Offset
DDR_SDRAM_CFG_2 114h
18.4.9.2 Function
The DDR SDRAM control configuration register 2 provides more control configuration
for the DDR controller.
18.4.9.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
ODT_CFG
Reserved
Reserved
Reserved
FRC_S
W
R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
UNQ_MRS_EN
DDR_SLOW
SPARE_CNF
OBC_CFG
NUM_PR
Reserved
Reserved
Reserved
CD_DIS
QD_EN
MD_EN
AP_EN
D_INIT
W
G
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 725
DDR register descriptions
18.4.9.4 Fields
Field Function
0 Force Self Refresh.
0b - DDR controller will operate in normal mode.
FRC_SR
1b - DDR controller will enter self-refresh mode.
1 Reserved
—
2-8 Reserved.
—
9-10 ODT configuration.
ODT_CFG This field defines how ODT will be driven to the on-chip IOs. See DDR Control Driver Register 1 (DDRC
DR_1) and DDR Control Driver Register 2 (DDRCDR_2) which define the termination value that will be
used.
00b - Never assert ODT to internal IOs
01b - Reserved
10b - Assert ODT to internal IOs only during reads to DRAM
11b - Reserved
11-15 Reserved.
—
16-19 Number of posted refreshes.
NUM_PR This will determine how many posted refreshes, if any, can be issued at one time. Note that if posted
refreshes are used, then this field, along with DDR_SDRAM_INTERVAL[REFINT], must be programmed
such that the maximum tras specification cannot be violated.
Patterns not shown are reserved.
0000b - Reserved
0001b - 1 refresh will be issued at a time
0010b - 2 refreshes will be issued at a time
0011b - 3 refreshes will be issued at a time
1000b - 8 refreshes will be issued at a time
20 DDR Slow Frequency.
DDR_SLOW Indicates to the controller if it will be run at a lower frequency.
0b - The DDR controller will be run at data rates of 1250 MT/s or higher.
1b - The DDR controller will be run at data rates of less than 1250 MT/s.
21 Reserved
—
22 Quad-Rank Enable.
QD_EN Determines if a quad-ranked DIMM is used. This bit should also be set if quad-stacked discrete memory
chips are used.
0b - Quad-ranked DIMMs are not used.
1b - Quad-ranked DIMMs are used.
23 Unique MRS Enable.
UNQ_MRS_EN
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
726 NXP Semiconductors
Chapter 18 DDR Memory Controller
Field Function
Determines if the DDR_SDRAM_MODE_{3:8} and DDR_SDRAM_MODE_{11:16} registers will be used
when initializing the memories for chip selects 1, 2, and 3. These can be used to provide unique values to
the Mode Registers of the DRAM to allow different termination values for each rank.
24
—
25 On-The-Fly Burst Chop Configuration.
OBC_CFG Determines if on-the-fly Burst Chop will be used. If on-the-fly Burst Chop mode is not used, then 8-beat
burst mode should be used. DDR_SDRAM_CFG[BE_8] should be cleared for on-the-fly Burst Chop
mode.
0b - On-the-fly Burst Chop mode is disabled. Fixed burst lengths as defined in
DDR_SDRAM_CFG[BE_8] are used.
1b - On-the-fly Burst Chop mode will be used. DDR_SDRAM_CFG[BE_8] should be cleared for on-
the-fly Burst Chop mode. DDR_SDRAM_CFG[DBW] should also be programmed for 64-bit bus or
32-bit bus.
26 Address Parity Enable.
AP_EN Determines if address parity will be generated and checked for the address and control signals . If
address parity is used, the MAPAR_OUT and MAPAR_ERR_B pins will be used to drive the parity bit and
to receive errors from the open-drain parity error signal. Even parity will be used, and parity will be
generated for the MA[15:0], MBA[2:0], MRAS_B, MCAS_B, MWE_B signals. Parity will not be generated
for the MODTn, MCSn_B, and MCKEn signals. Note that address parity should not be used for non-zero
values of TIMING_CFG_3[CNTL_ADJ].
0b - Address parity will not be used
1b - Address parity will be used
27 DRAM data initialization.
D_INIT This bit is set by software, and it is cleared by hardware. If software sets this bit before the memory
controller is enabled, the controller will automatically initialize DRAM after it is enabled. This bit will be
automatically cleared by hardware once the initialization is completed. This data initialization bit should
only be set when the controller is idle.
0b - There is not data initialization in progress, and no data initialization is scheduled
1b - The memory controller will initialize memory once it is enabled. This bit will remain asserted
until the initialization is complete. The value in DDR_DATA_INIT register will be used to initialize
memory.
28 Spare Config Bits.
SPARE_CNFG This field is currently unused.
29 Reserved
—
30 Corrupted Data Disable.
CD_DIS If this bit is set, then the corrupted data feature will be disabled. When the corrupted data feature is
enabled, the DDR controller will inverted the generated ECC code for any beat of data which is known to
have corrupted data. When a read to the corrupted data is later generated, the ERR_DETECT[CDE] error
will be set if error reporting is enabled.
0b - Corrupted data is enabled
1b - Corrupted data is disabled
31 Mirrored DIMM Enable.
MD_EN Some DIMMs will be mirrored, where certain MA and MBA pins are mirrored on one side of the DIMM.
When this bit is set, the controller will know to swap these signals before transmitting to the DRAM. The
controller will assume that CS1 and CS3 are the 'mirrored' ranks of memory.
The following signals are mirrored for DDR3:
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 727
DDR register descriptions
Field Function
• MBA[0] vs. MBA[1]
• MA[3] vs. MA[4]
• MA[5] vs. MA[6]
• MA[7] vs. MA[8]
The following signals are mirrored for DDR4:
• MBA[0] vs. MBA[1]
• MA[3] vs. MA[4]
• MA[5] vs. MA[6]
• MA[7] vs. MA[8]
• MA[11] vs. MA[13]
• MBG0 vs. MBG1 (if 2 bank group bits are used)
Note that MBG0 is the same as MBA[2] from the DDR controller. If using mirrored DIMMs for DDR4
mode, then CS0 and CS1 must be programmed to use the same number of bank group bits in
CSa_CONFIG[BG_BITS_CSa]. CS2 and CS3 must also be programmed to use the same number of
bank group bits.
0b - Mirrored DIMMs are not used
1b - Mirrored DIMMs are used
18.4.10 DDR SDRAM mode configuration (DDR_SDRAM_MODE)
18.4.10.1 Offset
Register Offset
DDR_SDRAM_MODE 118h
18.4.10.2 Function
The DDR SDRAM mode configuration register sets the values loaded into the DDR's
mode registers.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
728 NXP Semiconductors
Chapter 18 DDR Memory Controller
18.4.10.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
ESDMODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
SDMODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.4.10.4 Fields
Field Function
0-15 Extended SDRAM mode.
ESDMODE Specifies the initial value loaded into the DDR SDRAM extended mode register. The range and meaning
of legal values is specified by the DDR SDRAM manufacturer.
When this value is driven onto the address bus (during the DDR SDRAM initialization sequence), MA[0]
presents the lsb of ESDMODE, which, in the big-endian convention shown here, corresponds to
ESDMODE[15]. The msb of the SDRAM extended mode register value must be stored at ESDMODE[0].
The value programmed into this field is also used for writing MR1 during write leveling for DDR3 memory
types, although the bits specifically related to the write leveling scheme are handled automatically by the
DDR controller. Even if DDR_SDRAM_CFG[BI] is set, this field is still used during write leveling. The
write leveling enable bit should be cleared by software in this field.
16-31 SDRAM mode.
SDMODE Specifies the initial value loaded into the DDR SDRAM mode register. The range of legal values is
specified by the DDR SDRAM manufacturer.
When this value is driven onto the address bus (during DDR SDRAM initialization), MA[0] presents the
lsb of SDMODE, which, in the big-endian convention, corresponds to SDMODE[15]. The msb of the
SDRAM mode register value must be stored at SDMODE[0]. Because the memory controller forces
SDMODE[7] to certain values depending on the state of the initialization sequence, (for resetting the
SDRAM's DLL) the corresponding bits of this field are ignored by the memory controller. Note that
SDMODE[7] is mapped to MA[8].
18.4.11 DDR SDRAM mode configuration 2 (DDR_SDRAM_MO
DE_2)
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 729
DDR register descriptions
18.4.11.1 Offset
Register Offset
DDR_SDRAM_MODE_2 11Ch
18.4.11.2 Function
The DDR SDRAM mode 2 configuration register sets the values loaded into the DDR's
extended mode 2 and 3 registers.
18.4.11.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
ESDMODE2
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
ESDMODE3
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.4.11.4 Fields
Field Function
0-15 Extended SDRAM mode 2.
ESDMODE2 Specifies the initial value loaded into the DDR SDRAM extended 2 mode register. The range and
meaning of legal values is specified by the DDR SDRAM manufacturer.
When this value is driven onto the address bus (during the DDR SDRAM initialization sequence), MA[0]
presents the lsb bit of ESDMODE2, which, in the big-endian convention shown here, corresponds to
ESDMODE2[15]. The msb of the SDRAM extended mode 2 register value must be stored at
ESDMODE2[0].
16-31 Extended SDRAM mode 3.
ESDMODE3 Specifies the initial value loaded into the DDR SDRAM extended 3 mode register. The range of legal
values of legal values is specified by the DDR SDRAM manufacturer.
When this value is driven onto the address bus (during DDR SDRAM initialization), MA[0] presents the
lsb of ESDMODE3, which, in the big-endian convention shown here, corresponds to ESDMODE3[15].
The msb of the SDRAM extended mode 3 register value must be stored at ESDMODE3[0].
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
730 NXP Semiconductors
Chapter 18 DDR Memory Controller
18.4.12 DDR SDRAM mode control (DDR_SDRAM_MD_CNTL)
18.4.12.1 Offset
Register Offset
DDR_SDRAM_MD_CNT 120h
L
18.4.12.2 Function
The DDR SDRAM mode control register allows the user to carry out the following tasks:
Issue a mode register set command to a particular chip select
Issue an immediate refresh to a particular chip select
Issue an immediate precharge or precharge all command to a particular chip select
Force the CKE signals to a specific value
Note that MD_EN, SET_REF, and SET_PRE are mutually exclusive; only one of these
fields can be set at a time.
This table shows how DDR_SDRAM_MD_CNTL fields should be set for each of the
tasks described above.
Table 18-6. Settings of DDR_SDRAM_MD_CNTL Fields
Field Mode Register Set Refresh Precharge Clock Enable Signals Control
MD_EN 1 0 0 -
SET_REF 0 1 0 -
SET_PRE 0 0 1 -
CS_SEL Chooses chip select (CS) -
MD_SEL Select mode register. - Selects logical bank and -
bank group
MD_VALUE Value written to mode register - Only bit 7 is significant. -
CKE_CNTL 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 731
DDR register descriptions
18.4.12.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CKE_CNTL
MD_VALUE
SET_RE
Reserved
Reserved
SET_PR
MD_EN
CS_SE
MD_SE
W
L
E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
MD_VALUE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.4.12.4 Fields
Field Function
0 Mode enable.
MD_EN Setting this bit specifies that valid data in MD_VALUE is ready to be written to DRAM as one of the
following commands:
• MODE REGISTER SET
• EXTENDED MODE REGISTER SET
• EXTENDED MODE REGISTER SET 2
• EXTENDED MODE REGISTER SET 3
The specific command to be executed is selected by setting MD_SEL. In addition, the chip select must be
chosen by setting CS_SEL.MD_EN is set by software and cleared by hardware once the command has
been issued.
0b - Indicates that no mode register set command needs to be issued.
1b - Indicates that valid data contained in the register is ready to be issued as a mode register set
command.
1-3 Select chip select.
CS_SEL Specifies the chip select that will be driven active due to any command forced by software in
DDR_SDRAM_MD_CNTL.
000b - Chip select 0 is active
001b - Chip select 1 is active
010b - Chip select 2 is active
011b - Chip select 3 is active
100b - Chip select 0 and chip select 1 are active
101b - Chip select 2and chip select 3 are active
110b - Reserved
111b - Reserved
4-7 Mode register select.
MD_SEL MD_SEL specifies one of the following:
• During a mode select command, selects the SDRAM mode register to be changed
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
732 NXP Semiconductors
Chapter 18 DDR Memory Controller
Field Function
• During a precharge command, selects the SDRAM logical bank to be precharged. A precharge all
command ignores this field.
• During a refresh command, this field is ignored.
In DDR3 mode, MD_SEL[1:3] contains the value that will be presented onto the memory bank address
pins (MBAn) of the DDR controller. In DDR4 mode, MD_SEL[0:1] will represent the value on MBG[1:0],
and MD_SEL[2:3] will represent the value on MBA[1:0].
0000b - MR
0001b - EMR
0010b - EMR2
0011b - EMR3
8 Set refresh.
SET_REF Forces an immediate refresh to be issued to the chip select specified by
DDR_SDRAM_MD_CNTL[CS_SEL]. This bit will be set by software and cleared by hardware once the
command has been issued.
0b - Indicates that no refresh command needs to be issued.
1b - Indicates that a refresh command is ready to be issued.
9 Set precharge.
SET_PRE Forces a precharge or precharge all to be issued to the chip select specified by
DDR_SDRAM_MD_CNTL[CS_SEL]. This bit will be set by software and cleared by hardware once the
command has been issued.
0b - Indicates that no precharge all command needs to be issued.
1b - Indicates that a precharge all command is ready to be issued.
10-11 Clock enable control.
CKE_CNTL Allows software to globally clear or set the all CKE signals issued to DRAM. Once software has forced
the value driven on CKE, that value will continue to be forced until software clears the CKE_CNTL bits. At
that time, the DDR controller will continue to drive the CKE signals to the same value forced by software
until another event causes the CKE signals to change (that is, self refresh entry/exit, power down entry/
exit).
00b - CKE signals are not forced by software.
01b - CKE signals are forced to a low value by software.
10b - CKE signals are forced to a high value by software.
11b - Reserved
12 Reserved
—
13 Reserved.
—
14-31 Mode register value.
MD_VALUE This field, which specifies the value that will be presented on the memory address pins of the DDR
controller during a mode register set command, is significant only when this register is used to issue a
mode register set command or a precharge or precharge all command. Note that the 2 most significant
bits of this register are implemented for future use, but they will not currently affect the MRS commands
to the DRAM, as A[17:16] of the DRAMs MR registers are reserved.
For a mode register set command, this field contains the data to be written to the selected mode register.
For a precharge command, only bit five is significant:
000000000000000000b - Issue a precharge command; MD_SEL selects the logical bank to be
precharged
000000000000000001b - Issue a precharge all command; all logical banks are precharged
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 733
DDR register descriptions
18.4.13 DDR SDRAM interval configuration (DDR_SDRAM_IN
TERVAL)
18.4.13.1 Offset
Register Offset
DDR_SDRAM_INTERV 124h
AL
18.4.13.2 Function
The DDR SDRAM interval configuration register sets the number of DRAM clock cycles
between bank refreshes issued to the DDR SDRAMs. In addition, the number of DRAM
cycles that a page is maintained after it is accessed is provided here.
18.4.13.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
REFINT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
Reserved
BSTOPR
W
E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.4.13.4 Fields
Field Function
0-15 Refresh interval.
REFINT
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
734 NXP Semiconductors
Chapter 18 DDR Memory Controller
Field Function
Represents the number of memory bus clock cycles between refresh cycles. Depending on
DDR_SDRAM_CFG_2[NUM_PR], some number of rows are refreshed in each DDR SDRAM physical
bank during each refresh cycle. The value for REFINT depends on the specific SDRAMs used and the
interface clock frequency. Refreshes will not be issued when the REFINT is set to all 0s. This field is
concatenated with TIMING_CFG_4[EXT_REFINT] to obtain a 17-bit value for the total refresh interval.
16-17 Reserved.
—
18-31 Precharge interval.
BSTOPRE Sets the duration (in memory bus clocks) that a page is retained after a DDR SDRAM access. If
BSTOPRE is zero, the DDR memory controller uses auto-precharge read and write commands rather
than operating in page mode. This is called global auto-precharge mode.
18.4.14 DDR SDRAM data initialization (DDR_DATA_INIT)
18.4.14.1 Offset
Register Offset
DDR_DATA_INIT 128h
18.4.14.2 Function
The DDR SDRAM data initialization register provides the value that will be used to
initialize memory if DDR_SDRAM_CFG2[D_INIT] is set.
18.4.14.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
INIT_VALUE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
INIT_VALUE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 735
DDR register descriptions
18.4.14.4 Fields
Field Function
0-31 Initialization value.
INIT_VALUE Represents the value that DRAM will be initialized with if DDR_SDRAM_CFG2[D_INIT] is set.
18.4.15 DDR SDRAM clock control (DDR_SDRAM_CLK_CNTL)
18.4.15.1 Offset
Register Offset
DDR_SDRAM_CLK_CN 130h
TL
18.4.15.2 Function
The DDR SDRAM clock control configuration register provides a 1/8-cycle clock
adjustment.
18.4.15.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
Reserved CLK_ADJUST Reserved
W
Reset 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
736 NXP Semiconductors
Chapter 18 DDR Memory Controller
18.4.15.4 Fields
Field Function
0-4 Reserved.
—
5-9 Clock Adjust.
CLK_ADJUST 00000 Clock is launched aligned with address/command
00001 Clock is launched 1/16 applied cycle after address/command
00010 Clock is launched 1/8 applied cycle after address/command
00011 Clock is launched 3/16 applied cycle after address/command
00100 Clock is launched 1/4 applied cycle after address/command
00101 Clock is launched 5/16 applied cycle after address/command
00110 Clock is launched 3/8 applied cycle after address/command
00111 Clock is launched 7/16 applied cycle after address/command
01000 Clock is launched 1/2 applied cycle after address/command
01001 Clock is launched 9/16 applied cycle after address/command
01010 Clock is launched 5/8 applied cycle after address/command
01011 Clock is launched 11/16 applied cycle after address/command
01100 Clock is launched 3/4 applied cycle after address/command
01101 Clock is launched 13/16 applied cycle after address/command
01110 Clock is launched 7/8 applied cycle after address/command
01111 Clock is launched 15/16 applied cycle after address/command
10000 Clock is launched 1 applied cycle after address/command
10010-11110 Reserved
10-31 Reserved.
—
18.4.16 DDR training initialization address (DDR_INIT_ADDR)
18.4.16.1 Offset
Register Offset
DDR_INIT_ADDR 148h
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 737
DDR register descriptions
18.4.16.2 Function
The DDR SDRAM initialization address register provides the address that will be used
for the data strobe to data skew adjustment and automatic CAS_B to preamble calibration
after POR.
When the default value is used (that is, address 0x0), all chip selects are considered for
the training. If DDR_INIT_ADDR is set to any value other than the default value of
address zero, then only the first chip select will be trained. When multiple chip selects are
used and DQS/DQ skew is not common between chip selects/ranks, then the default
address value of 0x0 is be recommended to obtain the best timing margins.
After the skew adjustment, this address will contain bad ECC data. This is not important
at POR, as all of memory should be subsequently initialized if ECC is enabled (either by
software or through the use of DDR_SDRAM_CFG_2[D_INIT]).
If an HRESET_B has been issued after the DRAM is in self-refresh mode, however,
memory is not initialized, so this address should be written to using an 8- or 32-byte
transaction to avoid possible ECC errors if this address could later be accessed.
18.4.16.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
INIT_ADDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
INIT_ADDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.4.16.4 Fields
Field Function
0-31 Initialization address.
INIT_ADDR Represents the address that will be used for the data strobe to data skew adjustment and automatic CAS
to preamble calibration at POR. This address will be written to during the initialization sequence.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
738 NXP Semiconductors
Chapter 18 DDR Memory Controller
18.4.17 DDR training initialization extended address (DDR_INIT_
EXT_ADDRESS)
18.4.17.1 Offset
Register Offset
DDR_INIT_EXT_ADD 14Ch
RESS
18.4.17.2 Function
The DDR SDRAM initialization extended address register provides the extended address
that will be used for the data strobe to data skew adjustment and automatic CAS_B to
preamble calibration after POR.
18.4.17.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
UIA Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
Reserved INIT_EXT_ADDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.4.17.4 Fields
Field Function
0 Use initialization address.
0b - Use the default address for training sequence as calculated by the controller. This will be the
UIA
first valid address in each enabled chip select.
1b - Use the initialization address programmed in DDR_INIT_ADDR and DDR_INIT_EXT_ADDR.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 739
DDR register descriptions
Field Function
1-23 Reserved.
—
24-31 Initialization extended address.
INIT_EXT_ADD Represents the extended address that will be used for the data strobe to data skew adjustment and
R automatic CAS_B to preamble calibration at POR. This extended address will be written to during the
initialization sequence.
18.4.18 DDR SDRAM timing configuration 4 (TIMING_CFG_4)
18.4.18.1 Offset
Register Offset
TIMING_CFG_4 160h
18.4.18.2 Function
The DDR SDRAM timing configuration 4 register provides additional timing fields.
18.4.18.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
RWT WRT RRT WWT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
EXT_REFIN
EXT_WWT
DLL_LOCK
EXT_RWT
EXT_WRT
Reserved
Reserved
Reserved
Reserved
Reserved
EXT_RR
W
T
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
740 NXP Semiconductors
Chapter 18 DDR Memory Controller
18.4.18.4 Fields
Field Function
0-3 Read-to-write turnaround for same chip select.
RWT Specifies how many cycles will be added between a read to write turnaround for transactions to the same
chip select. If a value of 0000 is chosen, then the DDR controller will use the value used for transactions
to different chip selects, as defined in TIMING_CFG_0[RWT]. This field can be used to improve
performance when operating in burst-chop mode by forcing transactions to the same chip select to use
extra cycles, while transaction to different chip selects can utilize the tri-state time on the DRAM interface.
Regardless of the value that is set in this field, the value defined by TIMING_CFG_0[RWT] will also be
met before issuing a write command.
0000b - Default
0001b - 1 clock
0010b - 2 clocks
0011b - 3 clocks
0100b - 4 clocks
0101b - 5 clocks
0110b - 6 clocks
0111b - 7 clocks
1000b - 8 clocks
1001b - 9 clocks
1010b - 10 clocks
1011b - 11 clocks
1100b - 12 clocks
1101b - 13 clocks
1110b - 14 clocks
1111b - 15 clocks
4-7 Write-to-read turnaround for same chip select.
WRT Specifies how many cycles will be added between a write to read turnaround for transactions to the same
chip select. If a value of 0000 is chosen, then the DDR controller will use the value used for transactions
to different chip selects, as defined in TIMING_CFG_0[WRT]. This field can be used to improve
performance when operating in burst-chop mode by forcing transactions to the same chip select to use
extra cycles, while transaction to different chip selects can utilize the tri-state time on the DRAM interface.
Regardless of the value that is set in this field, the value defined by TIMING_CFG_0[WRT] will also be
met before issuing a read command.
0000b - Default
0001b - 1 clock
0010b - 2 clocks
0011b - 3 clocks
0100b - 4 clocks
0101b - 5 clocks
0110b - 6 clocks
0111b - 7 clocks
1000b - 8 clocks
1001b - 9 clocks
1010b - 10 clocks
1011b - 11 clocks
1100b - 12 clocks
1101b - 13 clocks
1110b - 14 clocks
1111b - 15 clocks
8-11 Read-to-read turnaround for same chip select.
RRT
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 741
DDR register descriptions
Field Function
Specifies how many cycles will be added between reads to the same chip select. If a value of 0000 is
chosen, then 2 cycles will be required between read commands to the same chip select if 4-beat bursts
are used (4 cycles will be required if 8-beat bursts are used). Note that fixed 4-beat bursts are not
supported. However, this field may be used to add extra cycles when burst-chop mode is used, and the
DDR controller must wait 4 cycles for read-to-read transactions to the same chip select.
0000b - BL/2 clocks
0001b - BL/2 + 1 clock
0010b - BL/2 + 2 clocks
0011b - BL/2 + 3 clocks
0100b - BL/2 + 4 clocks
0101b - BL/2 + 5 clocks
0110b - BL/2 + 6 clocks
0111b - BL/2 + 7 clocks
1000b - BL/2 + 8 clocks
1001b - BL/2 + 9 clocks
1010b - BL/2 + 10 clocks
1011b - BL/2 + 11 clocks
1100b - BL/2 + 12 clocks
1101b - BL/2 + 13 clocks
1110b - BL/2 + 14 clocks
1111b - BL/2 + 15 clocks
12-15 Write-to-write turnaround for same chip select.
WWT Specifies how many cycles will be added between writes to the same chip select. If a value of 0000 is
chosen, then 2 cycles will be required between write commands to the same chip select if 4-beat bursts
are used (4 cycles will be required if 8-beat bursts are used). Note that fixed 4-beat bursts are not
supported. However, this field may be used to add extra cycles when burst-chop mode is used, and the
DDR controller must wait 4 cycles for write-to-write transactions to the same chip select.
0000b - BL/2 clocks
0001b - BL/2 + 1 clock
0010b - BL/2 + 2 clocks
0011b - BL/2 + 3 clocks
0100b - BL/2 + 4 clocks
0101b - BL/2 + 5 clocks
0110b - BL/2 + 6 clocks
0111b - BL/2 + 7 clocks
1000b - BL/2 + 8 clocks
1001b - BL/2 + 9 clocks
1010b - BL/2 + 10 clocks
1011b - BL/2 + 11 clocks
1100b - BL/2 + 12 clocks
1101b - BL/2 + 13 clocks
1110b - BL/2 + 14 clocks
1111b - BL/2 + 15 clocks
16-17 Extended read-to-write turnaround (tRTW).
EXT_RWT Specifies how many extra cycles will be added between a read to write turnaround. If 0 clocks is chosen,
then the DDR controller will use a fixed number based on the CAS latency and write latency. Choosing a
value other than 0 adds extra cycles past this default calculation. As a default the DDR controller will
determine the read-to-write turnaround as CL - WL + BL/2 + 2. In this equation, CL is the CAS latency
rounded up to the next integer, WL is the programmed write latency, and BL is the burst length. This field
is concatenated with TIMING_CFG_0[RWT] to obtain a 4-bit value for the total read-to-write turnaround
00b - 0 clocks
01b - 1 clock
10b - 2 clocks
11b - 3 clocks
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
742 NXP Semiconductors
Chapter 18 DDR Memory Controller
Field Function
18 Reserved.
—
19 Extended write-to-read turnaround.
EXT_WRT Specifies how many extra cycles will be added between a write to read turnaround. If 0 clocks is chosen,
then the DDR controller will use a fixed number based on the, read latency, and write latency. Choosing a
value other than 0 adds extra cycles past this default calculation. As a default, the DDR controller will
determine the write-to-read turnaround as WL - CL + BL/2 + 1. In this equation, CL is the CAS latency
rounded down to the next integer, WL is the programmed write latency, and BL is the burst length. This
field is concatenated with TIMING_CFG_0[WRT] to obtain a 3-bit value for the total write-to-read
turnaround
0b - 0 clocks
1b - 4 clocks
20 Reserved.
—
21 Extended read-to-read turnaround.
EXT_RRT Specifies how many extra cycles will be added between reads to different chip selects. As a default, 3
cycles will be required between read commands to different chip selects. Extra cycles may be added with
this field. Note: If 8-beat bursts are enabled, then 5 cycles will be the default. This field is concatenated
with TIMING_CFG_0[RRT] to obtain a 3-bit value for the total read-to-read turnaround
0b - 0 clocks
1b - 4 clocks
22 Reserved.
—
23 Extended write-to-write turnaround.
EXT_WWT Specifies how many extra cycles will be added between writes to different chip selects. As a default, 2
cycles will be required between write commands to different chip selects. Extra cycles may be added with
this field. Note: If 8-beat bursts are enabled, then 4 cycles will be the default. This field is concatenated
with TIMING_CFG_0[WWT] to obtain a 3-bit value for the total write-to-write turnaround
0b - 0 clocks
1b - 4 clocks
24-26 Reserved.
—
27 Extended Refresh Interval.
EXT_REFINT Represents the number of memory bus clock cycles between refresh cycles. Depending on
DDR_SDRAM_CFG_2[NUM_PR], some number of rows are refreshed in each DDR SDRAM physical
bank during each refresh cycle. The value for REFINT depends on the specific SDRAMs used and the
interface clock frequency. Refreshes will not be issued when the REFINT is set to all 0s. This field is
concatenated with DDR_SDRAM_INTERVAL[REFINT] to obtain a 17-bit value for the total refresh
interval.
0b - 0 clocks
1b - 65,536 clocks
28-29 Reserved.
—
30-31 DDR SDRAM DLL Lock Time.
DLL_LOCK
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 743
DDR register descriptions
Field Function
This provides the number of cycles that it will take for the DRAMs DLL to lock at POR and after exiting
self refresh. The controller will wait the specified number of cycles before issuing any commands after
exiting POR or self refresh.
00b - 200 clocks
01b - 512 clocks
10b - 1024 clocks
11b - Reserved
18.4.19 DDR SDRAM timing configuration 5 (TIMING_CFG_5)
18.4.19.1 Offset
Register Offset
TIMING_CFG_5 164h
18.4.19.2 Function
The DDR SDRAM timing configuration 5 register provides additional timing fields.
18.4.19.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
RODT_OFF
WODT_ON
RODT_ON
Reserved
Reserved
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
WODT_OFF
WODT_ON
Reserved
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
744 NXP Semiconductors
Chapter 18 DDR Memory Controller
18.4.19.4 Fields
Field Function
0-2 Reserved.
—
3-7 Read to ODT on.
RODT_ON Specifies the number of cycles that will pass from when a read command is placed on the DRAM bus
until the assertion of the relevant ODT signal(s). The default case (00000) provides a decode of [CASLAT
- WR_LAT] to provide the expected default. If 2T timing is used, an extra cycle will automatically be
added to the value selected in this field.
Patterns not shown are reserved.
00000b - CASLAT - WR_LAT
00001b - 0 clocks
00010b - 1 clock
00011b - 2 clocks
01100b - 11 clocks
8 Reserved.
—
9-11 Read to ODT off.
RODT_OFF Specifies the number of cycles that the relevant ODT signal(s) will remain asserted for each read
transaction. The default case (000) will leave the ODT signal(s) asserted for 4 DRAM cycles.
000b - 4 clocks
001b - 1 clock
010b - 2 clocks
011b - 3 clocks
100b - 4 clocks
101b - 5 clocks
110b - 6 clocks
111b - 7 clocks
12-14 Reserved.
—
15-19 Write to ODT on.
WODT_ON Specifies the number of cycles that will pass from when a write command is placed on the DRAM bus
until the assertion of the relevant ODT signal(s). The default case (00000) provides a decode of 0 cycles
to provide the expected default. If 2T timing is used, an extra cycle will automatically be added to the
value selected in this field.
Patterns not shown are reserved.
00000b - 0 clocks
00001b - 0 clocks
00010b - 1 clock
00011b - 2 clocks
00110b - 5 clocks
20 Reserved.
—
21-23 Write to ODT off.
WODT_OFF Specifies the number of cycles that the relevant ODT signal(s) will remain asserted for each write
transaction. The default case (000) will leave the ODT signal(s) asserted for 4 DRAM cycles.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 745
DDR register descriptions
Field Function
000b - 4 clocks
001b - 1 clock
010b - 2 clocks
011b - 3 clocks
100b - 4 clocks
101b - 5 clocks
110b - 6 clocks
111b - 7 clocks
24-31 Reserved.
—
18.4.20 DDR SDRAM timing configuration 6 (TIMING_CFG_6)
18.4.20.1 Offset
Register Offset
TIMING_CFG_6 168h
18.4.20.2 Function
The DDR SDRAM timing configuration 6 register provides additional timing fields.
If setting TIMING_CFG_6[HS_CASLAT] or TIMING_CFG_6[HS_WRLAT] to a non-
zero value, then the additive latency must be programmed to 0 clocks.
If setting TIMING_CFG_6[HS_WRLAT] to a non-zero value, then
TIMING_CFG_5[WODT_ON] should be programmed to 0 clocks.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
746 NXP Semiconductors
Chapter 18 DDR Memory Controller
18.4.20.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
HS_CASLAT
HS_WRLAT
HS_WRRE
Reserved
Reserved
W
C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
HS_WRRE
Reserved
Reserved
Reserved
Reserved
W
C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.4.20.4 Fields
Field Function
0-2 Reserved.
—
3-7 Half-Speed CAS Latency.
HS_CASLAT MCAS_B latency from READ command while DDR controller is operating at half frequency. Number of
clock cycles between registration of a READ command by the SDRAM and the availability of the first
output data. If a READ command is registered at clock edge n and the latency is m clocks, data is
available nominally coincident with clock edge n + m. If a non-zero field of this register is used, then the
additive latency (TIMING_CFG_2[ADD_LAT] must be programmed to 0 clocks).
Patterns not shown are reserved.
00000b - Use full speed value
00101b - 5 clocks
00110b - 6 clocks
00111b - 7 clocks
01000b - 8 clocks
01001b - 9 clocks
01010b - 10 clocks
01011b - 11 clocks
01100b - 12 clocks
01101b - 13 clocks
01110b - 14 clocks
01111b - 15 clocks
10000b - 16 clocks
10001b - 17 clocks
10010b - 18 clocks
10011b - 19 clocks
10100b - 20 clocks
8-12 Half-Speed Write Latency.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 747
DDR register descriptions
Field Function
HS_WRLAT Write latency while DDR controller is operating at half frequency. Note that the total write latency is equal
to WR_LAT + ADD_LAT. Note that the total write latency must be at least 6 cycles if using unbuffered
DIMMs in 1T timing mode. Note that this is not a straight decode, as bit 13 of this register sets the msb of
the WR_LAT field. If using a non-zero value for this field, then TIMING_CFG_5[WODT_ON] must be set
to 0 clocks to ensure ODT is driven correctly for writes.
Patterns not shown are reserved.
00000b - Use full speed value
00001b - 16 clocks
00011b - 17 clocks
00101b - 18 clocks
01010b - 5 clocks
01100b - 6 clocks
01110b - 7 clocks
13-14 Reserved.
—
15-19 Half-Speed Write Recovery.
HS_WRREC Last data to precharge minimum interval (tWR) while DDR controller is operating at half frequency.
Determines the number of clock cycles from the last data associated with a write command until a
precharge command is allowed. If DDR_SDRAM_CFG_2[OBC_CFG] is set, then this field needs to be
programmed to (tWR + 2 cycles).
00000b - Use full speed value.
00001b - 1 clock
00010b - 2 clocks
00011b - 3 clocks
00100b - 4 clocks
00101b - 5 clocks
00110b - 6 clocks
00111b - 7 clocks
01000b - 8 clocks
01001b - 9 clocks
01010b - 10 clocks
01011b - 11 clocks
01100b - 12 clocks
01101b - 13 clocks
01110b - 14 clocks
01111b - 15 clocks
10000b - 16 clocks
10001b - 17 clocks
10010b - 18 clocks
10011b - 19 clocks
10100b - 20 clocks
10101b - 21 clocks
10110b - 22 clocks
10111b - 23 clocks
11000b - 24 clocks
11001b - 25 clocks
11010b - 26 clocks
11011b - 27 clocks
11100b - 28 clocks
11101b - 29 clocks
11110b - 30 clocks
11111b - 31 clocks
20 Reserved.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
748 NXP Semiconductors
Chapter 18 DDR Memory Controller
Field Function
—
21-25 Reserved.
—
26 Reserved.
—
27-31 Reserved.
—
18.4.21 DDR SDRAM timing configuration 7 (TIMING_CFG_7)
18.4.21.1 Offset
Register Offset
TIMING_CFG_7 16Ch
18.4.21.2 Function
The DDR SDRAM timing configuration 7 register provides additional timing fields
required.
18.4.21.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
PAR_LAT
Reserved
CKE_RS
CKSR
CKSR
W
E
X
T
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
Reserved CS_TO_CMD Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 749
DDR register descriptions
18.4.21.4 Fields
Field Function
0-1 Reserved.
—
2-3 CKE Reset Time.
CKE_RST CKE reset time (tXPR). Specifies the number of cycles the DDR controller must wait after asserting CKE
after RESET until the first MRS command. This field is also used to determine tXS when exiting self
refresh. Therefore, this should be programmed to the maximum of (tXPR, tXS) if they are different for a
particular memory.
00b - 200 clocks
01b - 256 clocks
10b - 512 clocks
11b - 1024 clocks
4-7 Clock After Self Refresh Entry.
CKSRE Valid clock after Self Refresh entry (tCKSRE). Specifies the number of cycles the DDR controller must drive
valid MCK/MCK_B after entering self refresh before the clocks are allowed to stop.
TIMING_CFG_7[CS_TO_CMD] should also be added to tCKSRE to obtain the final value for this field.
0000b - 15 clocks
0001b - 6 clocks
0010b - 7 clocks
0011b - 8 clocks
0100b - 9 clocks
0101b - 10 clocks
0110b - 11 clocks
0111b - 12 clocks
1000b - 13 clocks
1001b - 14 clocks
1010b - 15 clocks
1011b - 16 clocks
1100b - 17 clocks
1101b - 18 clocks
1110b - 19 clocks
1111b - 32 clocks
8-11 Clock After Self Refresh Exit.
CKSRX Valid clock after Self Refresh exit (tCKSRX). Specifies the number of cycles the DDR controller must drive
valid MCK/MCK_B after exiting self refresh before the clocks are allowed to stop.
0000b - 15 clocks
0001b - 6 clocks
0010b - 7 clocks
0011b - 8 clocks
0100b - 9 clocks
0101b - 10 clocks
0110b - 11 clocks
0111b - 12 clocks
1000b - 13 clocks
1001b - 14 clocks
1010b - 15 clocks
1011b - 16 clocks
1100b - 17 clocks
1101b - 18 clocks
1110b - 19 clocks
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
750 NXP Semiconductors
Chapter 18 DDR Memory Controller
Field Function
1111b - 27 clocks
12-15 Parity latency.
PAR_LAT Specifies the number of cycles to be used for the parity latency for DDR4 memories. For DDR3 memory
types, this should be disabled.
Patterns not shown are reserved.
0000b - Disabled
0001b - 1 clock
0010b - 2 clocks
0011b - 3 clocks
0100b - 4 clocks
0101b - 5 clocks
0110b - 6 clocks
0111b - 7 clocks
1000b - 8 clocks
16-23 Reserved.
—
24-27 Chip select to command latency.
CS_TO_CMD Specifies the number of cycles from a chip select until the command is launched. This should only be
used with DDR4. The DDR controller will automatically apply this latency after it has written the MR4
register during DDR4 SDRAM initialization. It will also be enabled when the controller is enabled if
DDR_SDRAM_CFG[BI] is set. However, if software is going to use the DDR_SDRAM_MD_CNTL register
to intialize the DRAM's MR registers instead of allowing for automatic calibration, then this field cannot be
set until software has properly programmed the DDR4 MR4 register to enable CAL mode.
Patterns not shown are reserved.
0000b - Disabled
0001b - 1 clock
0010b - 2 clocks
0011b - 3 clocks
0100b - 4 clocks
0101b - 5 clocks
0110b - 6 clocks
0111b - 7 clocks
1000b - 8 clocks
28-31 Reserved.
—
18.4.22 DDR ZQ calibration control (DDR_ZQ_CNTL)
18.4.22.1 Offset
Register Offset
DDR_ZQ_CNTL 170h
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 751
DDR register descriptions
18.4.22.2 Function
The DDR ZQ Calibration Control register provides the enable and controls required for
ZQ calibration.
There is a limitation for various DRAM timing parameters when ZQ calibration is used.
The factors involved in this limitation are DDR_ZQ_CNTL[ZQOPER],
DDR_ZQ_CNTL[ZQCS], TIMING_CFG_1[PRETOACT], TIMING_CFG_1[REFREC],
DDR_SDRAM_INTERVAL[REFINT], and the number of chip selects enabled. If the
following condition is true:
[((DDR_ZQ_CNTL[ZQOPER] + DDR_ZQ_CNTL[ZQCS])* (# enabled chip selects)) +
TIMING_CFG_1[PRETOACT] +
TIMING_CFG_1[REFREC] + 2tCK] > (DDR_SDRAM_INTERVAL[REFINT]),
then it is possible that one refresh will be skipped when the controller is exiting self
refresh. If this is an issue, then posted refreshes could be used to extend the refresh
interval. Another alternative is to use the DDR_SDRAM_MD_CNTL register to force an
extra refresh to each chip select after exiting self refresh mode. However, timing
parameters for most devices/frequencies will not allow for a refresh to be missed.
18.4.22.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
ZQOPER
Reserved
Reserved
ZQ_EN
ZQINIT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
Reserved ZQCS Reserved ZQCS_INT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.4.22.4 Fields
Field Function
0 ZQ Calibration Enable.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
752 NXP Semiconductors
Chapter 18 DDR Memory Controller
Field Function
ZQ_EN This bit determines if ZQ calibrating will be used.
0b - ZQ Calibration will not be used.
1b - ZQ Calibration will be used. A ZQCL command will be issued by the DDR controller after POR
and anytime the DDR controller is exiting self refresh. A ZQCS command will be issued every 32
refresh sequences to account for VT variations.
1-3 Reserved.
—
4-7 ZQ Calibration Initialization Time.
ZQINIT POR ZQ Calibration Time (tZQinit). Determines the number of cycles that must be allowed for DRAM ZQ
calibration at POR. Each chip select will be calibrated separately, and this time must elapse after the
ZQCL command is issued for each chip select before a separate command may be issued.
Patterns not shown are reserved.
0111b - 128 clocks
1000b - 256 clocks
1001b - 512 clocks
1010b - 1024 clocks
8-11 Reserved.
—
12-15 ZQ Calibration Operation Time.
ZQOPER Normal Operation Full Calibration Time (tZQoper). Determines the number of cycles that must be allowed
for DRAM ZQ calibration when exiting self refresh. Each chip select will be calibrated separately, and this
time must elapse after the ZQCL command is issued for each chip select before a separate command
may be issued.
Patterns not shown are reserved.
0111b - 128 clocks
1000b - 256 clocks
1001b - 512 clocks
1010b - 1024 clocks
16-19 Reserved.
—
20-23 ZQ Calibration Short Time.
ZQCS Normal Operation Short Calibration Time (tZQCS). Determines the number of cycles that must be allowed
for DRAM ZQ calibration during dynamic calibration which is issued every ZQCS_INT refresh sequences.
Each chip select will be calibrated separately, and this time must elapse after the ZQCS command is
issued for each chip select before a separate command may be issued.
Patterns not shown are reserved.
0000b - 1 clock
0001b - 2 clocks
0010b - 4 clocks
0011b - 8 clocks
0100b - 16 clocks
0101b - 32 clocks
0110b - 64 clocks
0111b - 128 clocks
1000b - 256 clocks
1001b - 512 clocks
24-27 Reserved.
—
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 753
DDR register descriptions
Field Function
28-31 ZQCS Interval.
ZQCS_INT Determines the number of refresh sequences that will pass between each ZQCS calibration.
0000b - 32 refresh sequences
0001b - 64 refresh sequences
0010b - 128 refresh sequences
0011b - 256 refresh sequences
0100b - 512 refresh sequences
0101b - 1024 refresh sequences
0110b - 2048 refresh sequences
0111b - 4096 refresh sequences
1000b - 8192 refresh sequences
1001b - 16384 refresh sequences
1010b - 32768 refresh sequences
1011b - Reserved
1100b - Reserved
1101b - Reserved
1110b - Reserved
1111b - ZQCS calibration disabled
18.4.23 DDR write leveling control (DDR_WRLVL_CNTL)
18.4.23.1 Offset
Register Offset
DDR_WRLVL_CNTL 174h
18.4.23.2 Function
The DDR Write Leveling Control register provides controls for write leveling.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
754 NXP Semiconductors
Chapter 18 DDR Memory Controller
18.4.23.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
WRLVL_DONE
WRLVL_DQSEN
WRLVL_ODTEN
WRLVL_MRD
WRLVL_EN
Reserved
Reserved
Reserved
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
WRLVL_START
WRLVL_SMPL
WRLVL_WLR
Reserved
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.4.23.4 Fields
Field Function
0 Write Leveling Enable.
WRLVL_EN This bit determines if write leveling will be used. If this bit is set, then the DDR controller will perform write
leveling immediately after initializing the DRAM.
0b - Write leveling will not be used
1b - Write leveling will be used
1 Write Leveling Done.
WRLVL_DONE This bit will be set by hardware once write leveling has been completed. This is a read-only bit, and it will
only clear after a reset to the part has been issued.
0b - Write leveling has not completed
1b - Write leveling has completed
2-4 Reserved.
—
5-7 Write Leveling MRD.
WRLVL_MRD First DQS pulse rising edge after margining mode is programmed (tWL_MRD). Determines how many
cycles to wait after margining mode has been programmed before the first DQS pulse may be issued.
This field is only relevant when DDR_WRLVL_CNTL[WRLVL_EN] is set.
000b - 1 clock
001b - 2 clocks
010b - 4 clocks
011b - 8 clocks
100b - 16 clocks
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 755
DDR register descriptions
Field Function
101b - 32 clocks
110b - 64 clocks
111b - 128 clocks
8 Reserved.
—
9-11 Write Leveling ODT Enable.
WRLVL_ODTE ODT delay after margining mode is programmed (tWL_ODTEN). Determines how many cycles to wait after
N margining mode has been programmed.until ODT may be asserted.This field is only relevant when
DDR_WRLVL_CNTL[WRLVL_EN] is set.
000b - 1 clock
001b - 2 clocks
010b - 4 clocks
011b - 8 clocks
100b - 16 clocks
101b - 32 clocks
110b - 64 clocks
111b - 128 clocks
12 Reserved.
—
13-15 Write Leveling DQS Enable.
WRLVL_DQSE DQS/DQS_B delay after margining mode is programmed (tWL_DQSEN). Determines how many cycles to
N wait after margining mode has been programmed.until DQS may be actively driven. This field is only
relevant when DDR_WRLVL_CNTL[WRLVL_EN] is set.
000b - 1 clock
001b - 2 clocks
010b - 4 clocks
011b - 8 clocks
100b - 16 clocks
101b - 32 clocks
110b - 64 clocks
111b - 128 clocks
16-19 Write leveling sample time.
WRLVL_SMPL Determines the number of cycles that must pass before the data signals are sampled after a DQS pulse
during margining mode. This field should be programmed at least 6 cycles higher than tWLO to allow
enough time for propagation delay and sampling of the prime data bits. This field is only relevant when
DDR_WRLVL_CNTL[WRLVL_EN] is set.
0000b - 32 clocks
0001b - 1 clock
0010b - 2 clocks
0011b - 3 clocks
0100b - 4 clocks
0101b - 5 clocks
0110b - 6 clocks
0111b - 7 clocks
1000b - 8 clocks
1001b - 9 clocks
1010b - 10 clocks
1011b - 11 clocks
1100b - 12 clocks
1101b - 13 clocks
1110b - 14 clocks
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
756 NXP Semiconductors
Chapter 18 DDR Memory Controller
Field Function
1111b - 15 clocks
20 Reserved.
—
21-23 Write leveling repetition time.
WRLVL_WLR Determines the number of cycles that must pass between DQS pulses during write leveling. This field is
only relevant when DDR_WRLVL_CNTL[WRLVL_EN] is set.
000b - 1 clock
001b - 2 clocks
010b - 4 clocks
011b - 8 clocks
100b - 16 clocks
101b - 32 clocks
110b - 64 clocks
111b - 128 clocks
24-26 Reserved.
—
27-31 Write Leveling Start for DQS[0].
WRLVL_START Determines the value to use for the DQS_ADJUST for the first sample when write leveling is enabled.
00000b - 0 clock delay
00001b - 1/8 clock delay
00010b - 1/4 clock delay
00011b - 3/8 clock delay
00100b - 1/2 clock delay
00101b - 5/8 clock delay
00110b - 3/4 clock delay
00111b - 7/8 c'lock delay
01000b - 1 clock delay
01001b - 9/8 clock delay
01010b - 5/4 clock delay
01011b - 11/8 clock delay
01100b - 3/2 clock delay
01101b - 13/8 clock delay
01110b - 7/4 clock delay
01111b - 15/8 clock delay
10000b - 2 clock delay
10001b - 17/8 clock delay
10010b - 9/4 clock delay
10011b - 19/8 clock delay
10100b - 5/2 clock delay
10101b - 21/8 clock delay
10110b - 16/4 clock delay
10111b - 23/8 clock delay
11000b - 3 clock delay
11001b - 25/8 clock delay
11010b - 13/4 clock delay
11011b - 27/8 clock delay
11100b - 7/2 clock delay
11101b - 29/8 clock delay
11110b - 15/4 clock delay
11111b - 31/8 clock delay
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 757
DDR register descriptions
18.4.24 DDR Self Refresh Counter (DDR_SR_CNTR)
18.4.24.1 Offset
Register Offset
DDR_SR_CNTR 17Ch
18.4.24.2 Function
The DDR Self Refresh Counter register can be programmed to force the DDR controller
to enter self refresh after a predefined period of idle time.
18.4.24.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
Reserved SR_IT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.4.24.4 Fields
Field Function
0-11 Reserved.
—
12-15 Self Refresh Idle Threshold.
SR_IT Defines the number of DRAM cycles that must pass while the DDR controller is idle before it will enter
self refresh. Anytime a transaction is issued to the DDR controller, it will reset its internal counter. When a
new transaction is received by the DDR controller, it will exit self refresh and reset its internal counter. If
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
758 NXP Semiconductors
Chapter 18 DDR Memory Controller
Field Function
this field is zero, then the described power savings feature will be disabled. In addition, if a non-zero
value is programmed into this field, then the DDR controller will exit self refresh anytime a transaction is
issued to the DDR controller, regardless of the reason self refresh was initially entered.
Patterns not shown are reserved.
0000b - Automatic self refresh entry disabled
0001b - 2^10 DRAM clocks
0010b - 2^12 DRAM clocks
0011b - 2^14 DRAM clocks
0100b - 2^16 DRAM clocks
0101b - 2^18 DRAM clocks
0110b - 2^20 DRAM clocks
0111b - 2^22 DRAM clocks
1000b - 2^24 DRAM clocks
1001b - 2^26 DRAM clocks
1010b - 2^28 DRAM clocks
1011b - 2^30 DRAM clocks
16-31 Reserved.
—
18.4.25 DDR Register Control Words 1 (DDR_SDRAM_RCW_1)
18.4.25.1 Offset
Register Offset
DDR_SDRAM_RCW_1 180h
18.4.25.2 Function
The DDR Register Control Word 1 register should be programmed with the intended
values of the register control words if DDR_SDRAM_CFG[RCW_EN] is set. Each 4-bit
field represents the value that will be placed on MBA[1], MBA[0], MA[4], and MA[3] in
DDR3 mode during register control word writes. Each 4-bit field represents the value that
will be placed on MA[3:0] in DDR4 mode during register control word writes.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 759
DDR register descriptions
18.4.25.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
RCW0 RCW1 RCW2 RCW3
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
RCW4 RCW5 RCW6 RCW7
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.4.25.4 Fields
Field Function
0-3 Register Control Word 0.
RCW0 Represents the value that will be used during writes to register control word 0.
4-7 Register Control Word 1.
RCW1 Represents the value that will be used during writes to register control word 1.
8-11 Register Control Word 2.
RCW2 Represents the value that will be used during writes to register control word 2.
12-15 Register Control Word 3.
RCW3 Represents the value that will be used during writes to register control word 3.
16-19 Register Control Word 4.
RCW4 Represents the value that will be used during writes to register control word 4.
20-23 Register Control Word 5.
RCW5 Represents the value that will be used during writes to register control word 5.
24-27 Register Control Word 6.
RCW6 Represents the value that will be used during writes to register control word 6.
28-31 Register Control Word 7.
RCW7 Represents the value that will be used during writes to register control word 7.
18.4.26 DDR Register Control Words 2 (DDR_SDRAM_RCW_2)
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
760 NXP Semiconductors
Chapter 18 DDR Memory Controller
18.4.26.1 Offset
Register Offset
DDR_SDRAM_RCW_2 184h
18.4.26.2 Function
The DDR Register Control Word 2 register should be programmed with the intended
values of the register control words if DDR_SDRAM_CFG[RCW_EN] is set. Each 4-bit
field represents the value that will be placed on MBA[1], MBA[0], MA[4], and MA[3] in
DDR3 mode during register control word writes. Each 4-bit field represents the value that
will be placed on MA[3:0] in DDR4 mode during register control word writes.
t
18.4.26.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
RCW8 RCW9 RCW10 RCW11
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
RCW12 RCW13 RCW14 RCW15
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.4.26.4 Fields
Field Function
0-3 Register Control Word 8.
RCW8 Represents the value that will be used during writes to register control word 8.
4-7 Register Control Word 9.
RCW9 Represents the value that will be used during writes to register control word 9.
8-11 Register Control Word 10.
RCW10 Represents the value that will be used during writes to register control word 10.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 761
DDR register descriptions
Field Function
12-15 Register Control Word 11.
RCW11 Represents the value that will be used during writes to register control word 11.
16-19 Register Control Word 12.
RCW12 Represents the value that will be used during writes to register control word 12.
20-23 Register Control Word 13.
RCW13 Represents the value that will be used during writes to register control word 13.
24-27 Register Control Word 14.
RCW14 Represents the value that will be used during writes to register control word 14.
28-31 Register Control Word 15.
RCW15 Represents the value that will be used during writes to register control word 15.
18.4.27 DDR write leveling control 2 (DDR_WRLVL_CNTL_2)
18.4.27.1 Offset
Register Offset
DDR_WRLVL_CNTL_2 190h
18.4.27.2 Function
The DDR Write Leveling Control 2 register provides controls for write leveling. This
register specifically defines the starting points for the individual data strobes.
Note: For each field WRLVL_START_n, a setting of 0000 is not recommended; it
disables the per-byte write level start time selection. It is recommended to select proper
individual delay for each byte lane based on board skews.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
762 NXP Semiconductors
Chapter 18 DDR Memory Controller
18.4.27.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
Reserved WRLVL_START_1 Reserved WRLVL_START_2
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
Reserved WRLVL_START_3 Reserved WRLVL_START_4
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.4.27.4 Fields
Field Function
0-2 Reserved.
—
3-7 Write leveling start time for DQS[1].
WRLVL_START Determines the value to use for the DQS_ADJUST for the first sample when write leveling is enabled.
_1
00000b - Use value from DDR_WRLVL_CNTL[WRLVL_START]
00001b - 1/8 clock delay
00010b - 1/4 clock delay
00011b - 3/8 clock delay
00100b - 1/2 clock delay
00101b - 5/8 clock delay
00110b - 3/4 clock delay
00111b - 7/8 c'lock delay
01000b - 1 clock delay
01001b - 9/8 clock delay
01010b - 5/4 clock delay
01011b - 11/8 clock delay
01100b - 3/2 clock delay
01101b - 13/8 clock delay
01110b - 7/4 clock delay
01111b - 15/8 clock delay
10000b - 2 clock delay
10001b - 17/8 clock delay
10010b - 9/4 clock delay
10011b - 19/8 clock delay
10100b - 5/2 clock delay
10101b - 21/8 clock delay
10110b - 16/4 clock delay
10111b - 23/8 clock delay
11000b - 3 clock delay
11001b - 25/8 clock delay
11010b - 13/4 clock delay
11011b - 27/8 clock delay
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 763
DDR register descriptions
Field Function
11100b - 7/2 clock delay
11101b - 29/8 clock delay
11110b - 15/4 clock delay
11111b - 31/8 clock delay
8-10 Reserved.
—
11-15 Write leveling start time for DQS[2].
WRLVL_START Determines the value to use for the DQS_ADJUST for the first sample when write leveling is enabled.
_2
00000b - Use value from DDR_WRLVL_CNTL[WRLVL_START]
00001b - 1/8 clock delay
00010b - 1/4 clock delay
00011b - 3/8 clock delay
00100b - 1/2 clock delay
00101b - 5/8 clock delay
00110b - 3/4 clock delay
00111b - 7/8 c'lock delay
01000b - 1 clock delay
01001b - 9/8 clock delay
01010b - 5/4 clock delay
01011b - 11/8 clock delay
01100b - 3/2 clock delay
01101b - 13/8 clock delay
01110b - 7/4 clock delay
01111b - 15/8 clock delay
10000b - 2 clock delay
10001b - 17/8 clock delay
10010b - 9/4 clock delay
10011b - 19/8 clock delay
10100b - 5/2 clock delay
10101b - 21/8 clock delay
10110b - 16/4 clock delay
10111b - 23/8 clock delay
11000b - 3 clock delay
11001b - 25/8 clock delay
11010b - 13/4 clock delay
11011b - 27/8 clock delay
11100b - 7/2 clock delay
11101b - 29/8 clock delay
11110b - 15/4 clock delay
11111b - 31/8 clock delay
16-18 Reserved.
—
19-23 Write leveling start time for DQS[3].
WRLVL_START Determines the value to use for the DQS_ADJUST for the first sample when write leveling is enabled.
_3
00000b - Use value from DDR_WRLVL_CNTL[WRLVL_START]
00001b - 1/8 clock delay
00010b - 1/4 clock delay
00011b - 3/8 clock delay
00100b - 1/2 clock delay
00101b - 5/8 clock delay
00110b - 3/4 clock delay
00111b - 7/8 c'lock delay
01000b - 1 clock delay
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
764 NXP Semiconductors
Chapter 18 DDR Memory Controller
Field Function
01001b - 9/8 clock delay
01010b - 5/4 clock delay
01011b - 11/8 clock delay
01100b - 3/2 clock delay
01101b - 13/8 clock delay
01110b - 7/4 clock delay
01111b - 15/8 clock delay
10000b - 2 clock delay
10001b - 17/8 clock delay
10010b - 9/4 clock delay
10011b - 19/8 clock delay
10100b - 5/2 clock delay
10101b - 21/8 clock delay
10110b - 16/4 clock delay
10111b - 23/8 clock delay
11000b - 3 clock delay
11001b - 25/8 clock delay
11010b - 13/4 clock delay
11011b - 27/8 clock delay
11100b - 7/2 clock delay
11101b - 29/8 clock delay
11110b - 15/4 clock delay
11111b - 31/8 clock delay
24-26 Reserved.
—
27-31 Write leveling start time for DQS[4].
WRLVL_START Determines the value to use for the DQS_ADJUST for the first sample when write leveling is enabled.
_4
00000b - Use value from DDR_WRLVL_CNTL[WRLVL_START]
00001b - 1/8 clock delay
00010b - 1/4 clock delay
00011b - 3/8 clock delay
00100b - 1/2 clock delay
00101b - 5/8 clock delay
00110b - 3/4 clock delay
00111b - 7/8 c'lock delay
01000b - 1 clock delay
01001b - 9/8 clock delay
01010b - 5/4 clock delay
01011b - 11/8 clock delay
01100b - 3/2 clock delay
01101b - 13/8 clock delay
01110b - 7/4 clock delay
01111b - 15/8 clock delay
10000b - 2 clock delay
10001b - 17/8 clock delay
10010b - 9/4 clock delay
10011b - 19/8 clock delay
10100b - 5/2 clock delay
10101b - 21/8 clock delay
10110b - 16/4 clock delay
10111b - 23/8 clock delay
11000b - 3 clock delay
11001b - 25/8 clock delay
11010b - 13/4 clock delay
11011b - 27/8 clock delay
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 765
DDR register descriptions
Field Function
11100b - 7/2 clock delay
11101b - 29/8 clock delay
11110b - 15/4 clock delay
11111b - 31/8 clock delay
18.4.28 DDR write leveling control 3 (DDR_WRLVL_CNTL_3)
18.4.28.1 Offset
Register Offset
DDR_WRLVL_CNTL_3 194h
18.4.28.2 Function
The DDR Write Leveling Control 3 register provides controls for write leveling. This
register specifically defines the starting points for the individual data strobes.
Note: For each field WRLVL_START_n, a setting of 0000 is not recommended; it
disables the per-byte write level start time selection. It is recommended to select proper
individual delay for each byte lane based on board skews.
18.4.28.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
Reserved WRLVL_START_5 Reserved WRLVL_START_6
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
Reserved WRLVL_START_7 Reserved WRLVL_START_8
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
766 NXP Semiconductors
Chapter 18 DDR Memory Controller
18.4.28.4 Fields
Field Function
0-2 Reserved.
—
3-7 Write leveling start time for DQS[5].
WRLVL_START Determines the value to use for the DQS_ADJUST for the first sample when write leveling is enabled.
_5
00000b - Use value from DDR_WRLVL_CNTL[WRLVL_START]
00001b - 1/8 clock delay
00010b - 1/4 clock delay
00011b - 3/8 clock delay
00100b - 1/2 clock delay
00101b - 5/8 clock delay
00110b - 3/4 clock delay
00111b - 7/8 c'lock delay
01000b - 1 clock delay
01001b - 9/8 clock delay
01010b - 5/4 clock delay
01011b - 11/8 clock delay
01100b - 3/2 clock delay
01101b - 13/8 clock delay
01110b - 7/4 clock delay
01111b - 15/8 clock delay
10000b - 2 clock delay
10001b - 17/8 clock delay
10010b - 9/4 clock delay
10011b - 19/8 clock delay
10100b - 5/2 clock delay
10101b - 21/8 clock delay
10110b - 16/4 clock delay
10111b - 23/8 clock delay
11000b - 3 clock delay
11001b - 25/8 clock delay
11010b - 13/4 clock delay
11011b - 27/8 clock delay
11100b - 7/2 clock delay
11101b - 29/8 clock delay
11110b - 15/4 clock delay
11111b - 31/8 clock delay
8-10 Reserved.
—
11-15 Write leveling start time for DQS[6].
WRLVL_START Determines the value to use for the DQS_ADJUST for the first sample when write leveling is enabled.
_6
00000b - Use value from DDR_WRLVL_CNTL[WRLVL_START]
00001b - 1/8 clock delay
00010b - 1/4 clock delay
00011b - 3/8 clock delay
00100b - 1/2 clock delay
00101b - 5/8 clock delay
00110b - 3/4 clock delay
00111b - 7/8 c'lock delay
01000b - 1 clock delay
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 767
DDR register descriptions
Field Function
01001b - 9/8 clock delay
01010b - 5/4 clock delay
01011b - 11/8 clock delay
01100b - 3/2 clock delay
01101b - 13/8 clock delay
01110b - 7/4 clock delay
01111b - 15/8 clock delay
10000b - 2 clock delay
10001b - 17/8 clock delay
10010b - 9/4 clock delay
10011b - 19/8 clock delay
10100b - 5/2 clock delay
10101b - 21/8 clock delay
10110b - 16/4 clock delay
10111b - 23/8 clock delay
11000b - 3 clock delay
11001b - 25/8 clock delay
11010b - 13/4 clock delay
11011b - 27/8 clock delay
11100b - 7/2 clock delay
11101b - 29/8 clock delay
11110b - 15/4 clock delay
11111b - 31/8 clock delay
16-18 Reserved.
—
19-23 Write leveling start time for DQS[7].
WRLVL_START Determines the value to use for the DQS_ADJUST for the first sample when write leveling is enabled.
_7
00000b - Use value from DDR_WRLVL_CNTL[WRLVL_START]
00001b - 1/8 clock delay
00010b - 1/4 clock delay
00011b - 3/8 clock delay
00100b - 1/2 clock delay
00101b - 5/8 clock delay
00110b - 3/4 clock delay
00111b - 7/8 c'lock delay
01000b - 1 clock delay
01001b - 9/8 clock delay
01010b - 5/4 clock delay
01011b - 11/8 clock delay
01100b - 3/2 clock delay
01101b - 13/8 clock delay
01110b - 7/4 clock delay
01111b - 15/8 clock delay
10000b - 2 clock delay
10001b - 17/8 clock delay
10010b - 9/4 clock delay
10011b - 19/8 clock delay
10100b - 5/2 clock delay
10101b - 21/8 clock delay
10110b - 16/4 clock delay
10111b - 23/8 clock delay
11000b - 3 clock delay
11001b - 25/8 clock delay
11010b - 13/4 clock delay
11011b - 27/8 clock delay
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
768 NXP Semiconductors
Chapter 18 DDR Memory Controller
Field Function
11100b - 7/2 clock delay
11101b - 29/8 clock delay
11110b - 15/4 clock delay
11111b - 31/8 clock delay
24-26 Reserved.
—
27-31 Write leveling start time for DQS[8].
WRLVL_START Determines the value to use for the DQS_ADJUST for the first sample when write leveling is enabled.
_8
00000b - Use value from DDR_WRLVL_CNTL[WRLVL_START]
00001b - 1/8 clock delay
00010b - 1/4 clock delay
00011b - 3/8 clock delay
00100b - 1/2 clock delay
00101b - 5/8 clock delay
00110b - 3/4 clock delay
00111b - 7/8 c'lock delay
01000b - 1 clock delay
01001b - 9/8 clock delay
01010b - 5/4 clock delay
01011b - 11/8 clock delay
01100b - 3/2 clock delay
01101b - 13/8 clock delay
01110b - 7/4 clock delay
01111b - 15/8 clock delay
10000b - 2 clock delay
10001b - 17/8 clock delay
10010b - 9/4 clock delay
10011b - 19/8 clock delay
10100b - 5/2 clock delay
10101b - 21/8 clock delay
10110b - 16/4 clock delay
10111b - 23/8 clock delay
11000b - 3 clock delay
11001b - 25/8 clock delay
11010b - 13/4 clock delay
11011b - 27/8 clock delay
11100b - 7/2 clock delay
11101b - 29/8 clock delay
11110b - 15/4 clock delay
11111b - 31/8 clock delay
18.4.29 DDR Register Control Words 3 (DDR_SDRAM_RCW_3)
18.4.29.1 Offset
Register Offset
DDR_SDRAM_RCW_3 1A0h
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 769
DDR register descriptions
18.4.29.2 Function
The DDR Register Control Word 3 register should be programmed with the intended
values of the register control words if DDR_SDRAM_CFG[RCW_EN] is set. Each 8-bit
field represents the value that will be placed on MA[7:0], during register control word
writes. This register is only used for DDR4 mode.
18.4.29.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
RCW1X RCW2X
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
RCW3X RCW4X
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.4.29.4 Fields
Field Function
0-7 Register Control Word 1X.
RCW1X Represents the value that will be placed on MA[7:0] during writes to register control word 1X for DDR4.
8-15 Register Control Word 2X.
RCW2X Represents the value that will be placed on MA[7:0] during writes to register control word 2X for DDR4.
16-23 Register Control Word 3X.
RCW3X Represents the value that will be placed on MA[7:0] during writes to register control word 3X for DDR4.
24-31 Register Control Word 4X.
RCW4X Represents the value that will be placed on MA[7:0] during writes to register control word 4X for DDR4.
18.4.30 DDR Register Control Words 4 (DDR_SDRAM_RCW_4)
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
770 NXP Semiconductors
Chapter 18 DDR Memory Controller
18.4.30.1 Offset
Register Offset
DDR_SDRAM_RCW_4 1A4h
18.4.30.2 Function
The DDR Register Control Word 4 register should be programmed with the intended
values of the register control words if DDR_SDRAM_CFG[RCW_EN] is set. Each 8-bit
field represents the value that will be placed on MA[7:0], during register control word
writes. This register is only used for DDR4 mode.
18.4.30.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
RCW5X RCW6X
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
RCW7X RCW8X
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.4.30.4 Fields
Field Function
0-7 Register Control Word 5X.
RCW5X Represents the value that will be placed on MA[7:0] during writes to register control word 5X for DDR4.
8-15 Register Control Word 6X.
RCW6X Represents the value that will be placed on MA[7:0] during writes to register control word 6X for DDR4.
16-23 Register Control Word 7X.
RCW7X Represents the value that will be placed on MA[7:0] during writes to register control word 7X for DDR4.
24-31 Register Control Word 8X.
RCW8X Represents the value that will be placed on MA[7:0] during writes to register control word 8X for DDR4.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 771
DDR register descriptions
18.4.31 DDR Register Control Words 5 (DDR_SDRAM_RCW_5)
18.4.31.1 Offset
Register Offset
DDR_SDRAM_RCW_5 1A8h
18.4.31.2 Function
The DDR Register Control Word 5 register should be programmed with the intended
values of the register control words if DDR_SDRAM_CFG[RCW_EN] is set. Each 8-bit
field represents the value that will be placed on MA[7:0], during register control word
writes. This register is only used for DDR4 mode.
t
18.4.31.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
RCW9X RCW10X
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
RCW11X RCW12X
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.4.31.4 Fields
Field Function
0-7 Register Control Word 9X.
RCW9X Represents the value that will be placed on MA[7:0] during writes to register control word 9X for DDR4.
8-15 Register Control Word 10X.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
772 NXP Semiconductors
Chapter 18 DDR Memory Controller
Field Function
RCW10X Represents the value that will be placed on MA[7:0] during writes to register control word 10X for DDR4.
16-23 Register Control Word 11X.
RCW11X Represents the value that will be placed on MA[7:0] during writes to register control word 11X for DDR4.
24-31 Register Control Word 12X.
RCW12X Represents the value that will be placed on MA[7:0] during writes to register control word 12X for DDR4.
18.4.32 DDR Register Control Words 6 (DDR_SDRAM_RCW_6)
18.4.32.1 Offset
Register Offset
DDR_SDRAM_RCW_6 1ACh
18.4.32.2 Function
The DDR Register Control Word 6 register should be programmed with the intended
values of the register control words if DDR_SDRAM_CFG[RCW_EN] is set. Each 8-bit
field represents the value that will be placed on MA[7:0], during register control word
writes. This register is only used for DDR4 mode.
18.4.32.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
RCW13X RCW14X
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
RCW15X SPARE_CNFG
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 773
DDR register descriptions
18.4.32.4 Fields
Field Function
0-7 Register Control Word 13X.
RCW13X Represents the value that will be placed on MA[7:0] during writes to register control word 13X for DDR4.
8-15 Register Control Word 14X.
RCW14X Represents the value that will be placed on MA[7:0] during writes to register control word 14X for DDR4.
16-23 Register Control Word 15X.
RCW15X Represents the value that will be placed on MA[7:0] during writes to register control word 15X for DDR4.
24-31 Spare Config Bits.
SPARE_CNFG This field is currently unused.
18.4.33 DDR SDRAM mode configuration 3 (DDR_SDRAM_MO
DE_3)
18.4.33.1 Offset
Register Offset
DDR_SDRAM_MODE_3 200h
18.4.33.2 Function
The DDR SDRAM mode configuration register sets the values loaded into the DDR's
mode registers. This register is used specifically for chip select 1 if
DDR_SDRAM_CFG_2[UNQ_MRS_EN] is set.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
774 NXP Semiconductors
Chapter 18 DDR Memory Controller
18.4.33.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
ESDMODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
SDMODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.4.33.4 Fields
Field Function
0-15 Extended SDRAM mode.
ESDMODE Specifies the initial value loaded into the DDR SDRAM extended mode register for chip select 1 if
DDR_SDRAM_CFG_2[UNQ_MRS_EN] is set. The range and meaning of legal values is specified by the
DDR SDRAM manufacturer.
When this value is driven onto the address bus (during the DDR SDRAM initialization sequence), MA[0]
presents the lsb of ESDMODE, which, in the big-endian convention shown here, corresponds to
ESDMODE[15]. The msb of the SDRAM extended mode register value must be stored at ESDMODE[0].
The value programmed into this field is also used for writing MR1 during write leveling, although the bits
specifically related to the write leveling scheme are handled automatically by the DDR controller. Even if
DDR_SDRAM_CFG[BI] is set, this field is still used during write leveling. The write leveling enable bit
should be cleared by software in this field.
16-31 SDRAM mode.
SDMODE Specifies the initial value loaded into the DDR SDRAM mode register for chip select 1 if
DDR_SDRAM_CFG_2[UNQ_MRS_EN] is set. The range of legal values is specified by the DDR SDRAM
manufacturer.
When this value is driven onto the address bus (during DDR SDRAM initialization), MA[0] presents the
lsb of SDMODE, which, in the big-endian convention shown here corresponds to SDMODE[15]. The msb
of the SDRAM mode register value must be stored at SDMODE[0]. Because the memory controller forces
SDMODE[7] to certain values depending on the state of the initialization sequence, (for resetting the
SDRAM's DLL) the corresponding bits of this field are ignored by the memory controller. Note that
SDMODE[7] is mapped to MA[8].
18.4.34 DDR SDRAM mode configuration 4 (DDR_SDRAM_MO
DE_4)
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 775
DDR register descriptions
18.4.34.1 Offset
Register Offset
DDR_SDRAM_MODE_4 204h
18.4.34.2 Function
The DDR SDRAM mode 4 configuration register sets the values loaded into the DDR's
extended mode 2 and 3 registers. This register is used specifically for chip select 1 if
DDR_SDRAM_CFG_2[UNQ_MRS_EN] is set.
18.4.34.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
ESDMODE2
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
ESDMODE3
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.4.34.4 Fields
Field Function
0-15 Extended SDRAM mode 2.
ESDMODE2 Specifies the initial value loaded into the DDR SDRAM extended 2 mode register for chip select 1 if
DDR_SDRAM_CFG_2[UNQ_MRS_EN] is set. The range and meaning of legal values is specified by the
DDR SDRAM manufacturer.
When this value is driven onto the address bus (during the DDR SDRAM initialization sequence), MA[0]
presents the lsb bit of ESDMODE2, which, in the big-endian convention shown here, corresponds to
ESDMODE2[15]. The msb of the SDRAM extended mode 2 register value must be stored at
ESDMODE2[0].
16-31 Extended SDRAM mode 3.
ESDMODE3 Specifies the initial value loaded into the DDR SDRAM extended 3 mode register for chip select 1 if
DDR_SDRAM_CFG_2[UNQ_MRS_EN] is set. The range of legal values of legal values is specified by
the DDR SDRAM manufacturer.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
776 NXP Semiconductors
Chapter 18 DDR Memory Controller
Field Function
When this value is driven onto the address bus (during DDR SDRAM initialization), MA[0] presents the
lsb of ESDMODE3, which, in the big-endian convention shown here, corresponds to ESDMODE3[15].
The msb of the SDRAM extended mode 3 register value must be stored at ESDMODE3[0].
18.4.35 DDR SDRAM mode configuration 5 (DDR_SDRAM_MO
DE_5)
18.4.35.1 Offset
Register Offset
DDR_SDRAM_MODE_5 208h
18.4.35.2 Function
The DDR SDRAM mode configuration register sets the values loaded into the DDR's
mode registers. This register is used specifically for chip select 2 if
DDR_SDRAM_CFG_2[UNQ_MRS_EN] is set.
18.4.35.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
ESDMODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
SDMODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 777
DDR register descriptions
18.4.35.4 Fields
Field Function
0-15 Extended SDRAM mode.
ESDMODE Specifies the initial value loaded into the DDR SDRAM extended mode register for chip select 2 if
DDR_SDRAM_CFG_2[UNQ_MRS_EN] is set. The range and meaning of legal values is specified by the
DDR SDRAM manufacturer.
When this value is driven onto the address bus (during the DDR SDRAM initialization sequence), MA[0]
presents the lsb of ESDMODE, which, in the big-endian convention, corresponds to ESDMODE[15]. The
msb of the SDRAM extended mode register value must be stored at ESDMODE[0]. The value
programmed into this field is also used for writing MR1 during write leveling, although the bits specifically
related to the write leveling scheme are handled automatically by the DDR controller. Even if
DDR_SDRAM_CFG[BI] is set, this field is still used during write leveling. The write leveling enable bit
should be cleared by software in this field.
16-31 SDRAM mode.
SDMODE Specifies the initial value loaded into the DDR SDRAM mode register for chip select 2 if
DDR_SDRAM_CFG_2[UNQ_MRS_EN] is set. The range of legal values is specified by the DDR SDRAM
manufacturer.
When this value is driven onto the address bus (during DDR SDRAM initialization), MA[0] presents the
lsb of SDMODE, which, in the big-endian convention, corresponds to SDMODE[15]. The msb of the
SDRAM mode register value must be stored at SDMODE[0]. Because the memory controller forces
SDMODE[7] to certain values depending on the state of the initialization sequence, (for resetting the
SDRAM's DLL) the corresponding bits of this field are ignored by the memory controller. Note that
SDMODE[7] is mapped to MA[8].
18.4.36 DDR SDRAM mode configuration 6 (DDR_SDRAM_MO
DE_6)
18.4.36.1 Offset
Register Offset
DDR_SDRAM_MODE_6 20Ch
18.4.36.2 Function
The DDR SDRAM mode 6 configuration register sets the values loaded into the DDR's
extended mode 2 and 3 registers. This register is used specifically for chip select 2 if
DDR_SDRAM_CFG_2[UNQ_MRS_EN] is set.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
778 NXP Semiconductors
Chapter 18 DDR Memory Controller
18.4.36.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
ESDMODE2
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
ESDMODE3
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.4.36.4 Fields
Field Function
0-15 Extended SDRAM mode 2.
ESDMODE2 Specifies the initial value loaded into the DDR SDRAM extended 2 mode register for chip select 2 if
DDR_SDRAM_CFG_2[UNQ_MRS_EN] is set. The range and meaning of legal values is specified by the
DDR SDRAM manufacturer.
When this value is driven onto the address bus (during the DDR SDRAM initialization sequence), MA[0]
presents the lsb bit of ESDMODE2, which, in the big-endian convention, corresponds to ESDMODE2[15].
The msb of the SDRAM extended mode 2 register value must be stored at ESDMODE2[0].
16-31 Extended SDRAM mode 3.
ESDMODE3 Specifies the initial value loaded into the DDR SDRAM extended 3 mode register for chip select 2 if
DDR_SDRAM_CFG_2[UNQ_MRS_EN] is set. The range of legal values of legal values is specified by
the DDR SDRAM manufacturer.
When this value is driven onto the address bus (during DDR SDRAM initialization), MA[0] presents the
lsb of ESDMODE3, which, in the big-endian convention, corresponds to ESDMODE3[15]. The msb of the
SDRAM extended mode 3 register value must be stored at ESDMODE3[0].
18.4.37 DDR SDRAM mode configuration 7 (DDR_SDRAM_MO
DE_7)
18.4.37.1 Offset
Register Offset
DDR_SDRAM_MODE_7 210h
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 779
DDR register descriptions
18.4.37.2 Function
The DDR SDRAM mode configuration register sets the values loaded into the DDR's
mode registers. This register is used specifically for chip select 3 if
DDR_SDRAM_CFG_2[UNQ_MRS_EN] is set.
18.4.37.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
ESDMODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
SDMODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.4.37.4 Fields
Field Function
0-15 Extended SDRAM mode.
ESDMODE Specifies the initial value loaded into the DDR SDRAM extended mode register for chip select 3 if
DDR_SDRAM_CFG_2[UNQ_MRS_EN] is set. The range and meaning of legal values is specified by the
DDR SDRAM manufacturer.
When this value is driven onto the address bus (during the DDR SDRAM initialization sequence), MA[0]
presents the lsb of ESDMODE, which, in the big-endian convention, corresponds to ESDMODE[15]. The
msb of the SDRAM extended mode register value must be stored at ESDMODE[0]. The value
programmed into this field is also used for writing MR1 during write leveling, although the bits specifically
related to the write leveling scheme are handled automatically by the DDR controller. Even if
DDR_SDRAM_CFG[BI] is set, this field is still used during write leveling. The write leveling enable bit
should be cleared by software in this field.
16-31 SDRAM mode.
SDMODE Specifies the initial value loaded into the DDR SDRAM mode register for chip select 3 if
DDR_SDRAM_CFG_2[UNQ_MRS_EN] is set. The range of legal values is specified by the DDR SDRAM
manufacturer.
When this value is driven onto the address bus (during DDR SDRAM initialization), MA[0] presents the
lsb of SDMODE, which, in the big-endian convention, corresponds to SDMODE[15]. The msb of the
SDRAM mode register value must be stored at SDMODE[0]. Because the memory controller forces
SDMODE[7] to certain values depending on the state of the initialization sequence, (for resetting the
SDRAM's DLL) the corresponding bits of this field are ignored by the memory controller. Note that
SDMODE[7] is mapped to MA[8].
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
780 NXP Semiconductors
Chapter 18 DDR Memory Controller
18.4.38 DDR SDRAM mode configuration 8 (DDR_SDRAM_MO
DE_8)
18.4.38.1 Offset
Register Offset
DDR_SDRAM_MODE_8 214h
18.4.38.2 Function
The DDR SDRAM mode 8 configuration register sets the values loaded into the DDR's
extended mode 2 and 3 registers. This register is used specifically for chip select 3 if
DDR_SDRAM_CFG_2[UNQ_MRS_EN] is set.
18.4.38.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
ESDMODE2
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
ESDMODE3
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.4.38.4 Fields
Field Function
0-15 Extended SDRAM mode 2.
ESDMODE2 Specifies the initial value loaded into the DDR SDRAM extended 2 mode register for chip select 3 if
DDR_SDRAM_CFG_2[UNQ_MRS_EN] is set. The range and meaning of legal values is specified by the
DDR SDRAM manufacturer.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 781
DDR register descriptions
Field Function
When this value is driven onto the address bus (during the DDR SDRAM initialization sequence), MA[0]
presents the lsb bit of ESDMODE2, which, in the big-endian convention, corresponds to ESDMODE2[15].
The msb of the SDRAM extended mode 2 register value must be stored at ESDMODE2[0].
16-31 Extended SDRAM mode 3.
ESDMODE3 Specifies the initial value loaded into the DDR SDRAM extended 3 mode register for chip select 3 if
DDR_SDRAM_CFG_2[UNQ_MRS_EN] is set. The range of legal values of legal values is specified by
the DDR SDRAM manufacturer.
When this value is driven onto the address bus (during DDR SDRAM initialization), MA[0] presents the
lsb of ESDMODE3, which, in the big-endian convention, corresponds to ESDMODE3[15]. The msb of the
SDRAM extended mode 3 register value must be stored at ESDMODE3[0].
18.4.39 DDR SDRAM mode configuration 9 (DDR_SDRAM_MO
DE_9)
18.4.39.1 Offset
Register Offset
DDR_SDRAM_MODE_9 220h
18.4.39.2 Function
The DDR SDRAM mode configuration register sets the values loaded into the DDR's
mode registers.
18.4.39.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
ESDMODE4
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
ESDMODE5
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
782 NXP Semiconductors
Chapter 18 DDR Memory Controller
18.4.39.4 Fields
Field Function
0-15 Extended SDRAM mode 4.
ESDMODE4 Specifies the initial value loaded into the DDR SDRAM MR4 register if using DDR4 memories. The range
and meaning of legal values is specified by the DDR SDRAM manufacturer. When this value is driven
onto the address bus (during the DDR SDRAM initialization sequence), MA[0] presents the lsb bit of
ESDMODE4, which, in the big-endian convention, corresponds to ESDMODE4[15]. The msb of the
SDRAM MR4 value must be stored at ESDMODE4[0].
16-31 Extended SDRAM mode 5.
ESDMODE5 Specifies the initial value loaded into the DDR SDRAM MR5 register if using DDR4 memories. The range
and meaning of legal values is specified by the DDR SDRAM manufacturer. When this value is driven
onto the address bus (during the DDR SDRAM initialization sequence), MA[0] presents the lsb bit of
ESDMODE5, which, in the big-endian convention, corresponds to ESDMODE5[15]. The msb of the
SDRAM MR5 value must be stored at ESDMODE5[0].
18.4.40 DDR SDRAM mode configuration 10 (DDR_SDRAM_MO
DE_10)
18.4.40.1 Offset
Register Offset
DDR_SDRAM_MODE_1 224h
0
18.4.40.2 Function
The DDR SDRAM mode 10 configuration register sets the values loaded into the DDR's
extended mode 6and 7 registers.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 783
DDR register descriptions
18.4.40.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
ESDMODE6
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
ESDMODE7
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.4.40.4 Fields
Field Function
0-15 Extended SDRAM mode 6.
ESDMODE6 Specifies the initial value loaded into the DDR SDRAM MR6 register if using DDR4 memories. The range
and meaning of legal values is specified by the DDR SDRAM manufacturer. When this value is driven
onto the address bus (during the DDR SDRAM initialization sequence), MA[0] presents the lsb bit of
ESDMODE6, which, in the big-endian convention, corresponds to ESDMODE6[15]. The msb of the
SDRAM MR6 value must be stored at ESDMODE6[0].
16-31 Extended SDRAM mode 7.
ESDMODE7 Specifies the initial value loaded into the DDR SDRAM MR7 register if using DDR4 memories. The range
and meaning of legal values is specified by the DDR SDRAM manufacturer. When this value is driven
onto the address bus (during the DDR SDRAM initialization sequence), MA[0] presents the lsb bit of
ESDMODE7, which, in the big-endian convention, corresponds to ESDMODE7[15]. The msb of the
SDRAM MR7 value must be stored at ESDMODE7[0].
18.4.41 DDR SDRAM mode configuration 11 (DDR_SDRAM_MO
DE_11)
18.4.41.1 Offset
Register Offset
DDR_SDRAM_MODE_1 228h
1
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
784 NXP Semiconductors
Chapter 18 DDR Memory Controller
18.4.41.2 Function
The DDR SDRAM mode configuration register sets the values loaded into the DDR's
mode registers. This register is used specifically for chip select 1 if
DDR_SDRAM_CFG_2[UNQ_MRS_EN] is set.
18.4.41.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
ESDMODE4
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
ESDMODE5
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.4.41.4 Fields
Field Function
0-15 Extended SDRAM mode 4.
ESDMODE4 Specifies the initial value loaded into the DDR SDRAM MR4 register for chip select 1 if
DDR_SDRAM_CFG_2[UNQ_MRS_EN] is set. This is only used with DDR4 memories. The range and
meaning of legal values is specified by the DDR SDRAM manufacturer. When this value is driven onto
the address bus (during the DDR SDRAM initialization sequence), MA[0] presents the lsb bit of
ESDMODE4, which, in the big-endian convention, corresponds to ESDMODE4[15]. The msb of the
SDRAM MR4 value must be stored at ESDMODE4[0].
16-31 Extended SDRAM mode 5.
ESDMODE5 Specifies the initial value loaded into the DDR SDRAM MR5 register for chip select 1 if
DDR_SDRAM_CFG_2[UNQ_MRS_EN] is set. This is only used with DDR4 memories. The range and
meaning of legal values is specified by the DDR SDRAM manufacturer. When this value is driven onto
the address bus (during the DDR SDRAM initialization sequence), MA[0] presents the lsb bit of
ESDMODE5, which, in the big-endian convention, corresponds to ESDMODE5[15]. The msb of the
SDRAM MR5 value must be stored at ESDMODE5[0].
18.4.42 DDR SDRAM mode configuration 12 (DDR_SDRAM_MO
DE_12)
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 785
DDR register descriptions
18.4.42.1 Offset
Register Offset
DDR_SDRAM_MODE_1 22Ch
2
18.4.42.2 Function
The DDR SDRAM mode 12 configuration register sets the values loaded into the DDR's
extended mode 6 and 7 registers. This register is used specifically for chip select 1 if
DDR_SDRAM_CFG_2[UNQ_MRS_EN] is set.
18.4.42.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
ESDMODE6
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
ESDMODE7
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.4.42.4 Fields
Field Function
0-15 Extended SDRAM mode 6.
ESDMODE6 Specifies the initial value loaded into the DDR SDRAM MR6 register for chip select 1 if
DDR_SDRAM_CFG_2[UNQ_MRS_EN] is set. This is only used with DDR4 memories. The range and
meaning of legal values is specified by the DDR SDRAM manufacturer. When this value is driven onto
the address bus (during the DDR SDRAM initialization sequence), MA[0] presents the lsb bit of
ESDMODE6, which, in the big-endian convention, corresponds to ESDMODE6[15]. The msb of the
SDRAM MR6 value must be stored at ESDMODE6[0].
16-31 Extended SDRAM mode 7.
ESDMODE7 Specifies the initial value loaded into the DDR SDRAM MR7 register for chip select 1 if
DDR_SDRAM_CFG_2[UNQ_MRS_EN] is set. This is only used with DDR4 memories. The range and
meaning of legal values is specified by the DDR SDRAM manufacturer. When this value is driven onto
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
786 NXP Semiconductors
Chapter 18 DDR Memory Controller
Field Function
the address bus (during the DDR SDRAM initialization sequence), MA[0] presents the lsb bit of
ESDMODE7, which, in the big-endian convention, corresponds to ESDMODE7[15]. The msb of the
SDRAM MR7 value must be stored at ESDMODE7[0].
18.4.43 DDR SDRAM mode configuration 13 (DDR_SDRAM_MO
DE_13)
18.4.43.1 Offset
Register Offset
DDR_SDRAM_MODE_1 230h
3
18.4.43.2 Function
The DDR SDRAM mode configuration register sets the values loaded into the DDR's
mode registers. This register is used specifically for chip select 2 if
DDR_SDRAM_CFG_2[UNQ_MRS_EN] is set.
18.4.43.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
ESDMODE4
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
ESDMODE5
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 787
DDR register descriptions
18.4.43.4 Fields
Field Function
0-15 Extended SDRAM mode 4.
ESDMODE4 Specifies the initial value loaded into the DDR SDRAM MR4 register for chip select 1 if
DDR_SDRAM_CFG_2[UNQ_MRS_EN] is set. This is only used with DDR4 memories. The range and
meaning of legal values is specified by the DDR SDRAM manufacturer. When this value is driven onto
the address bus (during the DDR SDRAM initialization sequence), MA[0] presents the lsb bit of
ESDMODE4, which, in the big-endian convention corresponds to ESDMODE4[15]. The msb of the
SDRAM MR4 value must be stored at ESDMODE4[0].
16-31 Extended SDRAM mode 5.
ESDMODE5 Specifies the initial value loaded into the DDR SDRAM MR5 register for chip select 1 if
DDR_SDRAM_CFG_2[UNQ_MRS_EN] is set. This is only used with DDR4 memories. The range and
meaning of legal values is specified by the DDR SDRAM manufacturer. When this value is driven onto
the address bus (during the DDR SDRAM initialization sequence), MA[0] presents the lsb bit of
ESDMODE5, which, in the big-endian convention corresponds to ESDMODE5[15]. The msb of the
SDRAM MR5 value must be stored at ESDMODE5[0].
18.4.44 DDR SDRAM mode configuration 14 (DDR_SDRAM_MO
DE_14)
18.4.44.1 Offset
Register Offset
DDR_SDRAM_MODE_1 234h
4
18.4.44.2 Function
The DDR SDRAM mode 14 configuration register sets the values loaded into the DDR's
extended mode 6 and 7 registers. This register is used specifically for chip select 2 if
DDR_SDRAM_CFG_2[UNQ_MRS_EN] is set.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
788 NXP Semiconductors
Chapter 18 DDR Memory Controller
18.4.44.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
ESDMODE6
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
ESDMODE7
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.4.44.4 Fields
Field Function
0-15 Extended SDRAM mode 6.
ESDMODE6 Specifies the initial value loaded into the DDR SDRAM MR6 register for chip select 1 if
DDR_SDRAM_CFG_2[UNQ_MRS_EN] is set. This is only used with DDR4 memories. The range and
meaning of legal values is specified by the DDR SDRAM manufacturer. When this value is driven onto
the address bus (during the DDR SDRAM initialization sequence), MA[0] presents the lsb bit of
ESDMODE6, which, in the big-endian convention, corresponds to ESDMODE6[15]. The msb of the
SDRAM MR6 value must be stored at ESDMODE6[0].
16-31 Extended SDRAM mode 7.
ESDMODE7 Specifies the initial value loaded into the DDR SDRAM MR7 register for chip select 1 if
DDR_SDRAM_CFG_2[UNQ_MRS_EN] is set. This is only used with DDR4 memories. The range and
meaning of legal values is specified by the DDR SDRAM manufacturer. When this value is driven onto
the address bus (during the DDR SDRAM initialization sequence), MA[0] presents the lsb bit of
ESDMODE7, which, in the big-endian convention, corresponds to ESDMODE7[15]. The msb of the
SDRAM MR7 value must be stored at ESDMODE7[0].
18.4.45 DDR SDRAM mode configuration 15 (DDR_SDRAM_MO
DE_15)
18.4.45.1 Offset
Register Offset
DDR_SDRAM_MODE_1 238h
5
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 789
DDR register descriptions
18.4.45.2 Function
The DDR SDRAM mode configuration register sets the values loaded into the DDR's
mode registers. This register is used specifically for chip select 3 if
DDR_SDRAM_CFG_2[UNQ_MRS_EN] is set.
18.4.45.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
ESDMODE4
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
ESDMODE5
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.4.45.4 Fields
Field Function
0-15 Extended SDRAM mode 4.
ESDMODE4 Specifies the initial value loaded into the DDR SDRAM MR4 register for chip select 1 if
DDR_SDRAM_CFG_2[UNQ_MRS_EN] is set. This is only used with DDR4 memories. The range and
meaning of legal values is specified by the DDR SDRAM manufacturer. When this value is driven onto
the address bus (during the DDR SDRAM initialization sequence), MA[0] presents the lsb bit of
ESDMODE4, which, in the big-endian convention, corresponds to ESDMODE4[15]. The msb of the
SDRAM MR4 value must be stored at ESDMODE4[0].
16-31 Extended SDRAM mode 5.
ESDMODE5 Specifies the initial value loaded into the DDR SDRAM MR5 register for chip select 1 if
DDR_SDRAM_CFG_2[UNQ_MRS_EN] is set. This is only used with DDR4 memories. The range and
meaning of legal values is specified by the DDR SDRAM manufacturer. When this value is driven onto
the address bus (during the DDR SDRAM initialization sequence), MA[0] presents the lsb bit of
ESDMODE5, which, in the big-endian convention, corresponds to ESDMODE5[15]. The msb of the
SDRAM MR5 value must be stored at ESDMODE5[0].
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
790 NXP Semiconductors
Chapter 18 DDR Memory Controller
18.4.46 DDR SDRAM mode configuration 16 (DDR_SDRAM_MO
DE_16)
18.4.46.1 Offset
Register Offset
DDR_SDRAM_MODE_1 23Ch
6
18.4.46.2 Function
The DDR SDRAM mode 16 configuration register sets the values loaded into the DDR's
extended mode 6 and 7 registers. This register is used specifically for chip select 3 if
DDR_SDRAM_CFG_2[UNQ_MRS_EN] is set.
18.4.46.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
ESDMODE6
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
ESDMODE7
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.4.46.4 Fields
Field Function
0-15 Extended SDRAM mode 6.
ESDMODE6 Specifies the initial value loaded into the DDR SDRAM MR6 register for chip select 1 if
DDR_SDRAM_CFG_2[UNQ_MRS_EN] is set. This is only used with DDR4 memories. The range and
meaning of legal values is specified by the DDR SDRAM manufacturer. When this value is driven onto
the address bus (during the DDR SDRAM initialization sequence), MA[0] presents the lsb bit of
ESDMODE6, which, in the big-endian convention, corresponds to ESDMODE6[15]. The msb of the
SDRAM MR6 value must be stored at ESDMODE6[0].
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 791
DDR register descriptions
Field Function
16-31 Extended SDRAM mode 7.
ESDMODE7 Specifies the initial value loaded into the DDR SDRAM MR7 register for chip select 1 if
DDR_SDRAM_CFG_2[UNQ_MRS_EN] is set. This is only used with DDR4 memories. The range and
meaning of legal values is specified by the DDR SDRAM manufacturer. When this value is driven onto
the address bus (during the DDR SDRAM initialization sequence), MA[0] presents the lsb bit of
ESDMODE7, which, in the big-endian convention, corresponds to ESDMODE7[15]. The msb of the
SDRAM MR7 value must be stored at ESDMODE7[0].
18.4.47 DDR SDRAM timing configuration 8 (TIMING_CFG_8)
18.4.47.1 Offset
Register Offset
TIMING_CFG_8 250h
18.4.47.2 Function
The DDR SDRAM timing configuration 8 register provides additional timing fields
required to support DDR4 memories.
18.4.47.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
RWT_BG WRT_BG RRT_BG WWT_BG
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
ACTTOACT_BG WRTORD_BG Reserved PRE_ALL_REC
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
792 NXP Semiconductors
Chapter 18 DDR Memory Controller
18.4.47.4 Fields
Field Function
0-3 Read-to-write turnaround for same chip select and same bank group.
RWT_BG Specifies how many cycles will be added between a read to write turnaround for transactions to the same
bank group. If a value of 0000 is chosen, then the DDR controller will use the value used for transactions
to different chip selects, as defined in TIMING_CFG_0[RWT]. This field can be used to improve
performance when operating in burst-chop mode by forcing transactions to the same chip select to use
extra cycles, while transaction to different chip selects can utilize the tri-state time on the DRAM interface.
Regardless of the value that is set in this field, the value defined by TIMING_CFG_0[RWT] will also be
met before issuing a write command. This field should be set to 0000 for DDR3.
0000b - Default
0001b - 1 clock
0010b - 2 clocks
0011b - 3 clocks
0100b - 4 clocks
0101b - 5 clocks
0110b - 6 clocks
0111b - 7 clocks
1000b - 8 clocks
1001b - 9 clocks
1010b - 10 clocks
1011b - 11 clocks
1100b - 12 clocks
1101b - 13 clocks
1110b - 14 clocks
1111b - 15 clocks
4-7 Write-to-read turnaround for same chip select and same bank group.
WRT_BG Specifies how many cycles will be added between a write to read turnaround for transactions to the same
bank group. If a value of 0000 is chosen, then the DDR controller will use the value used for transactions
to different chip selects, as defined in TIMING_CFG_0[WRT]. This field can be used to improve
performance when operating in burst-chop mode by forcing transactions to the same chip select to use
extra cycles, while transaction to different chip selects can utilize the tri-state time on the DRAM interface.
Regardless of the value that is set in this field, the value defined by TIMING_CFG_0[WRT] will also be
met before issuing a read command. This field should be programmed to 0000 for DDR3 mode.
0000b - Default
0001b - 1 clock
0010b - 2 clocks
0011b - 3 clocks
0100b - 4 clocks
0101b - 5 clocks
0110b - 6 clocks
0111b - 7 clocks
1000b - 8 clocks
1001b - 9 clocks
1010b - 10 clocks
1011b - 11 clocks
1100b - 12 clocks
1101b - 13 clocks
1110b - 14 clocks
1111b - 15 clocks
8-11 Read-to-read turnaround for same chip select and same bank group.
RRT_BG
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 793
DDR register descriptions
Field Function
Specifies how many cycles will be added between reads to the same bank group. If a value of 0000 is
chosen, then 2 cycles will be required between read commands to the same chip select if 4-beat bursts
are used (4 cycles will be required if 8-beat bursts are used). Note that fixed 4-beat bursts are not
supported. However, this field may be used to add extra cycles when burst-chop mode is used, and the
DDR controller must wait 4 cycles for read-to-read transactions to the same chip select. This field should
be programmed to 0000 for DDR3 mode.
0000b - BL/2 clocks
0001b - BL/2 + 1 clock
0010b - BL/2 + 2 clocks
0011b - BL/2 + 3 clocks
0100b - BL/2 + 4 clocks
0101b - BL/2 + 5 clocks
0110b - BL/2 + 6 clocks
0111b - BL/2 + 7 clocks
1000b - BL/2 + 8 clocks
1001b - BL/2 + 9 clocks
1010b - BL/2 + 10 clocks
1011b - BL/2 + 11 clocks
1100b - BL/2 + 12 clocks
1101b - BL/2 + 13 clocks
1110b - BL/2 + 14 clocks
1111b - BL/2 + 15 clocks
12-15 Write-to-write turnaround for same chip select and same bank group.
WWT_BG Specifies how many cycles will be added between writes to the same bank group. If a value of 0000 is
chosen, then 2 cycles will be required between write commands to the same bank group if 4-beat bursts
are used (4 cycles will be required if 8-beat bursts are used). Note that fixed 4-beat bursts are not
supported. However, this field may be used to add extra cycles when burst-chop mode is used, and the
DDR controller must wait 4 cycles for write-to-write transactions to the same chip select. This field should
be programmed to 0000 for DDR3 mode.
0000b - BL/2 clocks
0001b - BL/2 + 1 clock
0010b - BL/2 + 2 clocks
0011b - BL/2 + 3 clocks
0100b - BL/2 + 4 clocks
0101b - BL/2 + 5 clocks
0110b - BL/2 + 6 clocks
0111b - BL/2 + 7 clocks
1000b - BL/2 + 8 clocks
1001b - BL/2 + 9 clocks
1010b - BL/2 + 10 clocks
1011b - BL/2 + 11 clocks
1100b - BL/2 + 12 clocks
1101b - BL/2 + 13 clocks
1110b - BL/2 + 14 clocks
1111b - BL/2 + 15 clocks
16-19 Activate-To-Activate Same Bank Group.
ACTTOACT_BG Activate-to-activate interval for the same bank group(tRRD_L). Number of clock cycles from an activate
command until another activate command is allowed for a different logical bank in the same physical
bank (chip select). Bank groups are only used for DDR4. This field should be programmed to 0000 for
DDR3 mode.
0000b - ACTTOACT_BG is unused
0001b - 1 clock
0010b - 2 clocks
0011b - 3 clocks
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
794 NXP Semiconductors
Chapter 18 DDR Memory Controller
Field Function
0100b - 4 clocks
0101b - 5 clocks
0110b - 6 clocks
0111b - 7 clocks
1000b - 8 clocks
1001b - 9 clocks
1010b - 10 clocks
1011b - 11 clocks
1100b - 12 clocks
1101b - 13 clocks
1110b - 14 clocks
1111b - 15 clocks
20-23 Write-To-Read Same Bank Group.
WRTORD_BG Last write data pair to read command issue interval for the same bank group(tWTR_L). Number of clock
cycles between the last write data pair and the subsequent read command to the same physical bank. If
DDR_SDRAM_CFG_2[OBC_CFG] is set, then this field needs to be programmed to (tWTR + 2 cycles).
Bank groups are only used for DDR4. This field should be programmed to 0000 for DDR3 mode.
0000b - WRTORD_BG timing is unused
0001b - 1 clock
0010b - 2 clocks
0011b - 3 clocks
0100b - 4 clocks
0101b - 5 clocks
0110b - 6 clocks
0111b - 7 clocks
1000b - 8 clocks
1001b - 9 clocks
1010b - 10 clocks
1011b - 11 clocks
1100b - 12 clocks
1101b - 13 clocks
1110b - 14 clocks
1111b - 15 clocks
24-26 Reserved.
—
27-31 Precharge all-to-activate interval.
PRE_ALL_REC Determines the number of clock cycles from a precharge all command until an activate or refresh
command is allowed.
00000b - Use TIMING_CFG_1[PRETOACT]
00001b - 1 clock
00010b - 2 clocks
00011b - 3 clocks
00100b - 4 clocks
00101b - 5 clocks
00110b - 6 clocks
00111b - 7 clocks
01000b - 8 clocks
01001b - 9 clocks
01010b - 10 clocks
01011b - 11 clocks
01100b - 12 clocks
01101b - 13 clocks
01110b - 14 clocks
01111b - 15 clocks
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 795
DDR register descriptions
Field Function
10000b - 16 clocks
10001b - 17 clocks
10010b - 18 clocks
10011b - 19 clocks
10100b - 20 clocks
10101b - 21 clocks
10110b - 22 clocks
10111b - 23 clocks
11000b - 24 clocks
11001b - 25 clocks
11010b - 26 clocks
11011b - 27 clocks
11100b - 28 clocks
11101b - 29 clocks
11110b - 30 clocks
11111b - 31 clocks
18.4.48 DDR SDRAM control configuration 3 (DDR_SDRAM_CF
G_3)
18.4.48.1 Offset
Register Offset
DDR_SDRAM_CFG_3 260h
18.4.48.2 Function
The DDR SDRAM control configuration register 3 provides more control configuration
for the DDR controller.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
796 NXP Semiconductors
Chapter 18 DDR Memory Controller
18.4.48.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
ECC_SCRUB_INT
DDRC_RST
ECC_FIX_E
Reserved
Reserved
Reserved
Reserved
Reserved
W
N
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
DIS_MRS_PAR
REF_MOD
DM_CFG
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
W
E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.4.48.4 Fields
Field Function
0 DDR controller reset.
DDRC_RST This bit should be set by software if the DDR controller should be reset. This will reset all state machines
and internal FIFOs. This bit will not reset the DDR controller's configuration registers. Before setting this
bit, DDR_SDRAM_CFG[MEM_EN] should be cleared. Note that this bit is self-clearing. Software should
poll for this bit to clear before re-enabling the DDR controllerr.
0b - DDR controller is operating in normal mode.
1b - DDR controller is reset.
1 ECC fixing enable.
ECC_FIX_EN The DDR controller supports ECC fixing in memory. In this mode, the DDR controller will automatically fix
any detected single-bit errors by issuing a new transaction to read the address with the failing bit,
correcting the bit, and writing the data back to memory. The single-bit error will still be counted in the
ERR_SBE register for this case, but the controller will automatically fix the error. Note that during the
'read back', the single-bit error will not be double counted in the ERR_SBE register. In addition, the DDR
controller will periodically issue a read to memory at the interval defined by ECC_SCRUB_INT. If a
single-bit error is detected during a periodic read, it will be fixed. In this case, the error will be reported as
an SSBE in the ERR_SBE register. If a multi-bit eror is detected, then it will be reported in the
ERR_DETECT register. Also note that if a subsequent single-bit error is detected at the same address
while a first error is being fixed, then the second error will not be reported. Also, after a first SBE is
detected, no other SBEs will be fixed until the first SBE has been fixed in memory.This bit should only be
set if DDR_SDRAM_CFG[ECC_EN] is also set.
NOTE: Scrubbing cannot be enabled until after the controller has cleared
DDR_SDRAM_CFG_2[D_INIT].
0b - ECC scrubbing is disabled.
1b - ECC scrubbing is enabled.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 797
DDR register descriptions
Field Function
2-3 Reserved.
—
4-7 ECC scrubbing interval.
ECC_SCRUB_I This field defines how frequent the DDR controller will inject reads to test ECC if ECC_FIX_EN is set.
NT Note that reads will only be injected immediately after a refresh sequence. If a single-bit error is detected,
then the controller will fix the error in memory. If a multi-bit error is detected, then the controller will report
the error in the ERR_DETECT register. When issuing reads, the DDR controller will move sequentially
throughout the DRAM address space by automatically incrementing an internal address counter.
Note that the maximum amount memory supported would be 4 ranks of 16 Gbit x8 devices utilizing a 64-
bit bus, which provides a total of 64 GBytes of memory. Since 64-bytes of data are scrubbed for each
read, this will require 1G total reads to scrub the entire memory contents. Assuming a refresh interval of
7.8 microseconds, this will take approximately 2.35 hours to cycle through the entire memory array. If less
memory is used, then this time will take less. The scrubbing interval can be increased to improve
performance so the reads are not issued as frequently.
NOTE: Scrubbing cannot be enabled until after the controller has cleared
DDR_SDRAM_CFG_2[D_INIT].
0000b - Periodic reads for ECC scrubbing will not be issued.
0001b - A read will be issued every refresh sequence.
0010b - A read will be issued every 2 refresh sequences.
0011b - A read will be issued every 4 refresh sequences.
0100b - A read will be issued every 8 refresh sequences.
0101b - A read will be issued every 16 refresh sequences.
0110b - A read will be issued every 32 refresh sequences.
0111b - A read will be issued every 64 refresh sequences.
1000b - A read will be issued every 128 refresh sequences.
1001b - A read will be issued every 256 refresh sequences.
1010b - A read will be issued every 512 refresh sequences.
1011b - A read will be issued every 1024 refresh sequences.
1100b - A read will be issued every 2048 refresh sequences.
1101b - A read will be issued every 4096 refresh sequences.
1110b - A read will be issued every 8192 refresh sequences.
1111b - A read will be issued every 16,384 refresh sequences.
8-11 Reserved.
—
12 Reserved.
—
13 Reserved.
—
14-15 Reserved.
—
16-17 Reserved.
—
18-19 Data mask config.
DM_CFG Determines how the MDM pins will be utilized for the DDR controller.
00b - Normal data masks will be used based on DDR_SDRAM_CFG[SDRAM_TYPE].
01b - Reserved.
10b - Data bus inversion (DBI) will be used by utilizing the MDM pins.
11b - Neither data mask or data bus inversion will be used. The MDM pins will be held low for
DDR3 by the controller.The MDM pins will be held high for DDR4 by the controller.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
798 NXP Semiconductors
Chapter 18 DDR Memory Controller
Field Function
20-21 Reserved.
—
22-23 Refresh Mode.
REF_MODE This field allows programming for fine granularity refresh defined by DDR4 specifications. The fine
granularity refresh mode is supported by allowing full programmability of the
DDR_SDRAM_CFG_2[NUM_PR] and DDR_SDRAM_INTERVAL[REFINT] timings. However, this field is
required to notify the controller how many refreshes to issue when exitting self refresh. If fine granularity
refresh mode will be used, then it must enabled after the DDR controller has been enabled, per the
DRAM requirement to use 1x mode during initial MRS commands. Therefore, software must issue the
required MRS commands via DDR_SDRAM_MD_CNTL register to allow the DRAM to enter fine
granularity refresh mode. On-the-fly fine granularity refresh mode is not supported.
00b - Fine granularity refresh disabled.
01b - 2x fine granularity refresh mode.
10b - 4x fine granularity refresh mode.
11b - Reserved
24-25 Reserved.
—
26-27 Reserved.
—
28 Reserved.
—
29 Reserved.
—
30 Reserved.
—
31 Disable MRS on Parity Error.
DIS_MRS_PAR This bit controls the automatic MR command that may be issued upon a parity error. This bit should be
set if using parity.
If using parity with discrete devices, MR5 should be set to automatically re-enable parity checking after an
error.
0b - Issue an MR command to clear the parity error in the DRAM when a parity error is observed. If
parity is enabled when using DDR4 memories, then this bit must be set. In this case, software is
responsible for clearing the DRAM's mode register parity error bit if required. However, the DRAM
should be configured for persistent parity errors by setting MR5[A9] when initializing the DDR
controller to program the DRAM Mode Registers. This will ensure that the DDR4 DRAM will
continue to check parity errors until software can clear a previous parity error.
1b - Do not issue an MR command to clear the parity error on the DRAM. Software is responsible
for clearing parity errors if required via the DDR_SDRAM_MD_CNTL register.
18.4.49 DQ mapping register 0 (DDR_DQ_MAP0)
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 799
DDR register descriptions
18.4.49.1 Offset
Register Offset
DDR_DQ_MAP0 400h
18.4.49.2 Function
DQ_MAP0-DQ_MAP3 should be programmed to reflect how the DQ bits are swizzled
on the DIMMs. Note that if a board has further swizzling within the nibbles of the DQ
signals, then that needs to be accounted for when programming these fields. In addition,
if multiple modules are used in the system, they must use the same raw card design (such
that the swizzling is identical between DIMMs).
For each of the DQ mapping fields, the encodings are shown in the accompanying table.
These bitfields apply to nibbles of data; therefore, they must normally be set in pairs. (For
example, DQ_0_3 and DQ_4_7 must be set together.)
Table 18-7. Bitfield settings for each byte lane
Setting DQ0 DQ1 DQ2 DQ3
DQ4 DQ5 DQ6 DQ7
0x00 0 1 2 3
0x01 0 1 2 3
0x02 0 1 3 2
0x03 0 2 1 3
0x04 0 2 3 1
0x05 0 3 1 2
0x06 0 3 2 1
0x07 1 0 2 3
0x08 1 0 3 2
0x09 1 2 0 3
0x0a 1 2 3 0
0x0b 1 3 0 2
0x0c 1 3 2 0
0x0d 2 0 1 3
0x0e 2 0 3 1
0x0f 2 1 0 3
0x10 2 1 3 0
0x11 2 3 0 1
0x12 2 3 1 0
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
800 NXP Semiconductors
Chapter 18 DDR Memory Controller
Table 18-7. Bitfield settings for each byte lane (continued)
Setting DQ0 DQ1 DQ2 DQ3
DQ4 DQ5 DQ6 DQ7
0x13 3 0 1 2
0x14 3 0 2 1
0x15 3 1 0 2
0x16 3 1 2 0
0x17 3 2 0 1
0x18 3 2 1 0
0x21 4 5 6 7
0x22 4 5 7 6
0x23 4 6 5 7
0x24 4 6 7 5
0x25 4 7 5 6
0x26 4 7 6 5
0x27 5 4 6 7
0x28 5 4 7 6
0x29 5 6 4 7
0x2a 5 6 7 4
0x2b 5 7 4 6
0x2c 5 7 6 4
0x2d 6 4 5 7
0x2e 6 4 7 5
0x2f 6 5 4 7
0x30 6 5 7 4
0x31 6 7 4 5
0x32 6 7 5 4
0x33 7 4 5 6
0x34 7 4 6 5
0x35 7 5 4 6
0x36 7 5 6 4
0x37 7 6 4 5
0x38 7 6 5 4
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 801
DDR register descriptions
18.4.49.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
DQ_0_3 DQ_4_7 DQ_8_11
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
RESERVE
DQ_12_15
DQ_16_19
DQ_8_11
D
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.4.49.4 Fields
Field Function
0-5 DQ[0:3] Mapping.
DQ_0_3 See Table 18-7 and the text describing this register for settings.
6-11 DQ[4:7] Mapping.
DQ_4_7 See Table 18-7 and the text describing this register for settings.
12-17 DQ[8:11] Mapping.
DQ_8_11 See Table 18-7 and the text describing this register for settings.
18-23 DQ[12:15] Mapping.
DQ_12_15 See Table 18-7 and the text describing this register for settings.
24-29 DQ[16:19] Mapping.
DQ_16_19 See Table 18-7 and the text describing this register for settings.
30-31 Reserved.
RESERVED These bits are writeable, but they are unused.
18.4.50 DQ mapping register 1 (DDR_DQ_MAP1)
18.4.50.1 Offset
Register Offset
DDR_DQ_MAP1 404h
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
802 NXP Semiconductors
Chapter 18 DDR Memory Controller
18.4.50.2 Function
DQ_MAP0-DQ_MAP3 should be programmed to reflect how the DQ bits are swizzled
on the DIMMs. See further details at DQ mapping register 0 (DDR_DQ_MAP0).
18.4.50.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
DQ_20_23 DQ_24_27 DQ_28_31
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
RESERVE
DQ_28_31
DQ_32_35
W DQ_36_39
D
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.4.50.4 Fields
Field Function
0-5 DQ[20:23] Mapping.
DQ_20_23 See the table and description in DQ mapping register 0 (DDR_DQ_MAP0) for settings.
6-11 DQ[24:27] Mapping.
DQ_24_27 See the table and description in DQ mapping register 0 (DDR_DQ_MAP0) for settings.
12-17 DQ[28:31] Mapping.
DQ_28_31 See the table and description in DQ mapping register 0 (DDR_DQ_MAP0) for settings.
18-23 DQ[32:35] Mapping.
DQ_32_35 See the table and description in DQ mapping register 0 (DDR_DQ_MAP0) for settings.
24-29 DQ[36:39] Mapping.
DQ_36_39 See the table and description in DQ mapping register 0 (DDR_DQ_MAP0) for settings.
30-31 Reserved.
RESERVED These bits are writeable, but they are unused.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 803
DDR register descriptions
18.4.51 DQ mapping register 2 (DDR_DQ_MAP2)
18.4.51.1 Offset
Register Offset
DDR_DQ_MAP2 408h
18.4.51.2 Function
DQ_MAP0-DQ_MAP3 should be programmed to reflect how the DQ bits are swizzled
on the DIMMs. See further details at DQ mapping register 0 (DDR_DQ_MAP0).
18.4.51.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
DQ_40_43 DQ_44_47 DQ_48_51
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
RESERVE
DQ_48_51
DQ_52_55
DQ_56_59
D
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.4.51.4 Fields
Field Function
0-5 DQ[40:43] Mapping.
DQ_40_43 See the table and description in DQ mapping register 0 (DDR_DQ_MAP0) for settings.
6-11 DQ[44:47] Mapping.
DQ_44_47 See the table and description in DQ mapping register 0 (DDR_DQ_MAP0) for settings.
12-17 DQ[48:51] Mapping.
DQ_48_51 See the table and description in DQ mapping register 0 (DDR_DQ_MAP0) for settings.
18-23 DQ[52:55] Maping.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
804 NXP Semiconductors
Chapter 18 DDR Memory Controller
Field Function
DQ_52_55 See the table and description in DQ mapping register 0 (DDR_DQ_MAP0) for settings.
24-29 DQ[56:59] Mapping.
DQ_56_59 See the table and description in DQ mapping register 0 (DDR_DQ_MAP0) for settings.
30-31 Reserved.
RESERVED These bits are writeable, but they are unused.
18.4.52 DQ mapping register 3 (DDR_DQ_MAP3)
18.4.52.1 Offset
Register Offset
DDR_DQ_MAP3 40Ch
18.4.52.2 Function
DQ_MAP0-DQ_MAP3 should be programmed to reflect how the DQ bits are swizzled
on the DIMMs. See further details at DQ mapping register 0 (DDR_DQ_MAP0).
18.4.52.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
DQ_60_63 ECC_0_3 ECC_4_7
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
ECC_4_7
Reserved
OR
W
S
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 805
DDR register descriptions
18.4.52.4 Fields
Field Function
0-5 DQ[60:63] Mapping.
DQ_60_63 See the table and description in DQ mapping register 0 (DDR_DQ_MAP0) for settings.
6-11 ECC[0:3] Mapping.
ECC_0_3 See the table and description in DQ mapping register 0 (DDR_DQ_MAP0) for settings.
12-17 ECC[4:7] Mapping.
ECC_4_7 See the table and description in DQ mapping register 0 (DDR_DQ_MAP0) for settings.
18-30 Reserved
—
31 Odd rank swizzle.
ORS If this bit is cleared, then CS1 and CS3 follow the same swizzling as CS0 and CS2. If this bit is set, then
CS1 and CS3 are further swizzled by swapping bits 0 vs 1, 2 vs 3, 4 vs 5, and 6 vs 7 within each byte.
18.4.53 DDR Debug Status Register 1 (DDRDSR_1)
18.4.53.1 Offset
Register Offset
DDRDSR_1 B20h
18.4.53.2 Function
The DDRDSR_1 register contains the current settings of the driver impedance for the
command/control and data.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
806 NXP Semiconductors
Chapter 18 DDR Memory Controller
18.4.53.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R CZ DZ
Reserved Reserved
W
Reset 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
18.4.53.4 Fields
Field Function
0-15 Reserved.
—
16 Command Impedance.
CZ Current setting of driver command impedance
17-23 Reserved.
—
24 Data Impedance.
DZ Current setting of driver data impedance
25-31 Reserved.
—
18.4.54 DDR Debug Status Register 2 (DDRDSR_2)
18.4.54.1 Offset
Register Offset
DDRDSR_2 B24h
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 807
DDR register descriptions
18.4.54.2 Function
The DDRDSR_2 register contains the current settings of the driver impedance for the
DDR drivers for clocks.
18.4.54.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
Reserved
CLKZ
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
W1C RPD_END
RPD_S
R
Reserved
T
W1C
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.4.54.4 Fields
Field Function
0 Clock Impedance.
CLKZ Current setting of driver clock impedance
1-29 Reserved.
—
30 Rapid clear of memory start.
RPD_ST See DDR Rapid Clear of Memory for more information.
0b - The rapid clear of memory function has not been started.
1b - The rapid clear of memory function has started. During the rapid clear of memory, writes to the
DDR memory mapped registers will not affect the register contents. This bit is cleared by software
writing a 1.
31 Rapid clear of memory end.
RPD_END See DDR Rapid Clear of Memory for more information.
0b - The rapid clear of memory function has not ended.
1b - The rapid clear of memory function has completed. This bit is cleared by software writing a 1.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
808 NXP Semiconductors
Chapter 18 DDR Memory Controller
18.4.55 DDR Control Driver Register 1 (DDRCDR_1)
18.4.55.1 Offset
Register Offset
DDRCDR_1 B28h
18.4.55.2 Function
DDRCDR_1 sets the hardware DDR driver calibration enable, the ODT termination
value for IOs, and the software override enables for address/command and data bus
signals. The combined DDRCDR_1[ODT] and DDRCDR_2[ODT] set the on-die-
termination values in the memory controller for the data bus signals. Hardware DDR
driver calibration must be enabled by setting DDRCDR_1[DHC_EN]. MDIC pins are
required to be connected to proper calibration resistors. The proper value and connection
of the MDIC resistor are specified in the corresponding device data sheet document.
The global half-strength override field DDR_SDRAM_CFG[HSE] or software overrides
in DDRCDR_1 or DDRCDR_2 registers determine whether the DDR drivers calibrate to
full-strength or half-strength. The software overrides in DDRCDR_1 or DDRCDR_2
registers take precedence over the DDR_SDRAM_CFG[HSE] setting.
NOTE
All driver calibration related registers should be set 500 μs
before the DDR controller is enabled (that is, before
DDR_SDRAM_CFG[MEM_EN] is set).
This table lists the valid impedance override values. Note that the drivers may be
calibrated to either full-strength or half-strength.
Table 18-8. Valid Impedance Override Values
Driver impedance Impedance Override Value
Highest 0
Lowest 1
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 809
DDR register descriptions
18.4.55.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DSO_C_EN
DSO_D_EN
DHC_EN
Reserved
ODT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
DSO_CZ
DSO_DZ
Reserved
Reserved
W
Reset 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
18.4.55.4 Fields
Field Function
0 Driver Hardware Calibration Enable.
DHC_EN DDR driver hardware compensation enable. If this bit is set to enable automatic hardware compensation,
then 200 microseconds should pass after setting this bit, and before setting
DDR_SDRAM_CFG[MEM_EN].
1-11 Reserved
— These bits are writeable, but they are unused.
12-13 On-Die-Termination.
ODT ODT termination value for IOs. This is combined with DDRCDR_2[ODT] to determine the termination
value. Below is the termination based on concatenating these two fields.
Note that the order of concatenation is from left to right
DDRCDR_1[ODT], DDRCDR_2[ODT]
Bits [0:0] of the following values are defined at DDRCDR_2.ODT.
000b - Termination is disabled
001b - 120 Ω (DDR3) 100 Ω (DDR4)
010b - 200 Ω (DDR3) 120 Ω (DDR4)
011b - 75 Ω (DDR3) 80 Ω (DDR4)
100b - Reserved (DDR3) 60 Ω (DDR4)
101b - 60 Ω (DDR3) 40 Ω (DDR4)
110b - Reserved (DDR3) 50 Ω (DDR4)
111b - 46 Ω (DDR3) 30 Ω (DDR4)
14 Override Enable for Command Impedance.
DSO_C_EN Driver software override enable for address/command
15 Override Enable for Data Impedance.
DSO_D_EN Driver software override enable for data
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
810 NXP Semiconductors
Chapter 18 DDR Memory Controller
Field Function
16 Override for Command Impedance.
DSO_CZ DDR driver software command impedance override
17-23 Reserved.
— These bits are writeable, but they are unused.
24 Override For Data Impedance.
DSO_DZ Driver software data impedance override
25-31 Reserved.
— These bits are writeable, but they are unused.
18.4.56 DDR Control Driver Register 2 (DDRCDR_2)
18.4.56.1 Offset
Register Offset
DDRCDR_2 B2Ch
18.4.56.2 Function
The DDRCDR_2 sets the driver software override enable for clocks, and the DDR clocks
driver P/N impedance.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 811
DDR register descriptions
18.4.56.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
DSO_CLK_EN
DSO_CLKZ
Reserved
Reserved
Reserved
W
Reset 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
VREF_DRAM_RANGE
VREF_OVRD_VAL
VREF_TRAIN_EN
VREF_OVRD_EN
Reserved
Reserved
ODT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.4.56.4 Fields
Field Function
0 Override Enable for Clock Impedance.
DSO_CLK_EN Driver software override enable for clocks
1-3 Reserved.
—
4 Override Value for Clock Impedance.
DSO_CLKZ Driver software clocks impedance override
5-11 Reserved.
—
12-15 Reserved.
—
16 Internal VRef Override Enable.
VREF_OVRD_E If DDR4 mode is used, then an internal VRef is generated an used for the data bus. By default, this
N internal VRef value will be trained. However, the training can be disabled by this override.
0b - Internal VRef will be trained if DDR4 mode is used.
1b - Internal VRef will be defined by the VREF_OVRD_VAL field of this register.
17 Reserved.
—
18-23 Internal VRef Override Value.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
812 NXP Semiconductors
Chapter 18 DDR Memory Controller
Field Function
VREF_OVRD_V This field defines the override value to use for the internal VRef if VREF_OVRD_EN is set. The values
AL below are targetted percentages of GVdd for the internal VRef. However, it is highly recommended to
leave the VREF_OVRD_EN bit cleared to allow VRef to be trained for the best read margins.
000000b - 37%
000001b - 38%
000010b - 39%
111110b - 99%
111111b - 100%
24 DRAM VRef Train Enable
VREF_TRAIN_E In addition to the internal VRef training, the DRAM's VRef may also be trained. This bit can be set to
N automatically enable DRAM VRef training. This bit should be cleared for DDR3 mode.
0b - DRAM VRef will not be trained.
1b - DRAM VRef will be trained.
25 VRef DRAM Range.
VREF_DRAM_R If using DRAM VRef training, this bit will specify whether Range 1 or Range 2 will be trained.
ANGE
0b - DRAM VRef Range 1 will be used for training.
1b - DRAM VRef Range 2 will be used for training.
26-30 Reserved.
—
31 On-Die Termination
ODT ODT termination value for IOs. This is combined with DDRCDR_1[ODT] to determine the termination
value. Below is the termination based on concatenating these two fields.
Note that the order of concatenation is (from left to right)
DDRCDR_1[ODT], DDRCDR_2[ODT]
Bits [18:19] of the following values are defined at DDRCDR_1.ODT.
000b - Termination is disabled
001b - 120 Ω (DDR3) 100 Ω (DDR4)
010b - 200 Ω (DDR3) 120 Ω (DDR4)
011b - 75 Ω (DDR3) 80 Ω (DDR4)
100b - Reserved (DDR3) 60 Ω (DDR4)
101b - 60 Ω (DDR3) 40 Ω (DDR4)
110b - Reserved (DDR3) 50 Ω (DDR4)
111b - 46 Ω (DDR3) 30 Ω (DDR4)
18.4.57 DDR IP block revision 1 (DDR_IP_REV1)
18.4.57.1 Offset
Register Offset
DDR_IP_REV1 BF8h
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 813
DDR register descriptions
18.4.57.2 Function
The DDR IP block revision 1 register provides read-only fields with the IP block ID,
along with major and minor revision information.
18.4.57.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R IP_ID
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R IP_MJ IP_MN
W
Reset 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1
18.4.57.4 Fields
Field Function
0-15 IP block ID.
IP_ID For the DDR controller, this value is 0x0002.
16-23 Major revision.
IP_MJ This is currently set to 0x05.
24-31 Minor revision.
IP_MN This is currently set to 8'd1.
18.4.58 DDR IP block revision 2 (DDR_IP_REV2)
18.4.58.1 Offset
Register Offset
DDR_IP_REV2 BFCh
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
814 NXP Semiconductors
Chapter 18 DDR Memory Controller
18.4.58.2 Function
The DDR IP block revision 2 register provides read-only fields with the IP block
integration and configuration options.
18.4.58.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R IP_INT
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R IP_CFG
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.4.58.4 Fields
Field Function
0-7 Reserved.
—
8-15 IP Block Integration Options.
IP_INT
16-23 Reserved.
—
24-31 IP Block Configuration Options.
IP_CFG
18.4.59 DDR Memory Test Control Register (DDR_MTCR)
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 815
DDR register descriptions
18.4.59.1 Offset
Register Offset
DDR_MTCR D00h
18.4.59.2 Function
The DDR Memory Test Control Register provides the enable and controls for an
automatic memory test.
18.4.59.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MT_TRNARND
Reserved
MT_TYP
Reserved
MT_EN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
MT_ADDR_EN
MT_STAT
Reserved
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.4.59.4 Fields
Field Function
0 Memory Test Enable.
MT_EN This bit can be set by software to enable the memory test. Based on the value of MT_TYP, the controller
will either issue writes only, reads only, or it will issue writes and reads.The memory controller will issue
transactions throughout all of memory, as defined by the CSn_CONFIG and CSn_BNDS registers. The
memory controller will check the data during this test. In addition, the ERR_DETECT register should be
read by software if ECC is enabled after the memory test to ensure there were no ECC errors. If an ECC
error is detected, the error capture registers will hold the address, data, and attributes captured for the
first fail. If there is no ECC error and the test failed (for a data miscompare), then the capture registers will
hold information for the transaction that caused the first data miscompare. Note that transactions with
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
816 NXP Semiconductors
Chapter 18 DDR Memory Controller
Field Function
ECC errors will take priority in the capture registers. Hardware will clear MT_EN after the memory test is
complete. This bit can be set before DDR_SDRAM_CFG[MEM_EN] is set, or it can be set again after the
memory controller has been enabled.
0b - Memory test has been disabled.
1b - Memory test has been enabled. Hardware will clear this bit when it is complete.
1-5 Reserved.
—
6-7 Memory Test Type.
MT_TYP This field will determine if the memory test will issue writes only, reads only, or both writes and reads.
Note that the 'read only' test should not be used unless memory has already been initialized.
00b - Memory test will issue writes and reads.
01b - Memory test will issue writes only.
10b - Memory test will issue reads only.
11b - Reserved
8-11 Reserved.
—
12-15 Memory Test Turnaround.
MT_TRNARND This field determines how many writes will be issued during the memory test before the reads to the
same addresses will be issued. This can be used to allow longer streams of writes/reads, and it can be
used to test the write->read and read->write turnarounds in a stressful manner. This field is only relevant
if MT_TYP is set to 2'b00.
0000b - Entire memory will be written before read transactions are issued.
0001b - Total write/read streams will be 1 transaction each.
0010b - Total write/read streams will be 2 transactions each.
0011b - Total write/read streams will be 4 transactions each.
0100-1111b - Reserved
16-21 Reserved.
—
22 Memory Test Address Range Enable.
MT_ADDR_EN If this bit is set, then the address range defined in the DDR_MT_ST_EXT_ADDR, DDR_MT_ST_ADDR,
DDR_MT_END_EXT_ADDR, and DDR-MT_END_ADDR registers will be used.
Please note the following restrictions when using this field to limit the address range to be tested: For any
individual test, neither the starting address (DDR_MT_ST_EXT_ADDR || DDR_MT_ST_ADDR) nor the
ending address (DDR_MT_END_EXT_ADDR || DDR_MT_END_ADDR) can be less than that used
during the previous test. In addition, this field cannot be set if MTCR[MT_TRNARND] is set to 0b0000.
0b - Full memory range defined by CSa_BNDS registers will be used for the memory test.
1b - Memory range defined by DDR_MT_ST_EXT_ADDR, DDR_MT_ST_ADDR,
DDR_MT_END_EXT_ADDR, and DDR_MT_END_ADDR is used.
23-30 Reserved.
—
31 Memory Test Status.
MT_STAT After hardware clears MT_EN, this bit will be set if there was a fail. If there is a fail during the memory test
(that is, a data miscompare), then this bit will be set at the same time that MT_EN is cleared. Software
can clear this bit after it has been set.
0b - No fail has been detected.
1b - A data miscompare was detected during the memory test.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 817
DDR register descriptions
18.4.60 DDR Memory Test Pattern n Register (DDR_MTP1 - DDR_
MTP10)
18.4.60.1 Offset
For a = 1 to 10:
Register Offset
DDR_MTPa D1Ch + (a × 4h)
18.4.60.2 Function
The DDR memory test pattern n register provides the data pattern that will be written
during the nth set of 32-bits of each 40-byte memory test pattern. This is used when
DDR_MTCR[MT_EN] is set to enable the memory write/read test.
NOTE
Memory test read compares data that is written in this register.
18.4.60.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
DDR_PATT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
DDR_PATT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.4.60.4 Fields
Field Function
0-31 DDR Pattern.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
818 NXP Semiconductors
Chapter 18 DDR Memory Controller
Field Function
DDR_PATT This 32-bit pattern will be used during the memory test if enabled via DDR_MTCR[MT_EN]. This memory
test will write/read a programmable 40-byte pattern. The 10 DDR_MTPn registers will create the 40-byte
pattern that is used.
18.4.61 DDR Memory Test Start Extended Address (DDR_MT_S
T_EXT_ADDR)
18.4.61.1 Offset
Register Offset
DDR_MT_ST_EXT_AD D60h
DR
18.4.61.2 Function
The DDR memory test start extended address register provides the extended address that
will be used with DDR_MTCR[MT_ADDR_EN] is set.
18.4.61.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
Reserved MT_ST_EXT_ADDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 819
DDR register descriptions
18.4.61.4 Fields
Field Function
0-23 Reserved.
—
24-31 Memory Test Start Extended Address.
MT_ST_EXT_A This field represents the starting extended address that will be used when MTCR[MT_ADDR_EN] is set.
DDR
Please note the following restriction when using DDR_MTCR[MT_ADDR_EN] to limit the address range
to be tested: For any individual test, neither the starting address (DDR_MT_ST_EXT_ADDR ||
DDR_MT_ST_ADDR) nor the ending address (DDR_MT_END_EXT_ADDR || DDR_MT_END_ADDR)
can be less than that used during the previous test.
18.4.62 DDR Memory Test Start Address (DDR_MT_ST_ADDR)
18.4.62.1 Offset
Register Offset
DDR_MT_ST_ADDR D64h
18.4.62.2 Function
The DDR memory test start address register provides the address that will be used with
DDR_MTCR[MT_ADDR_EN] is set.
18.4.62.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
MT_ST_ADDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
MT_ST_ADDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
820 NXP Semiconductors
Chapter 18 DDR Memory Controller
18.4.62.4 Fields
Field Function
0-31 Memory Test Start Address.
MT_ST_ADDR This field represents the starting address that will be used when MTCR[MT_ADDR_EN] is set.
Please note the following restriction when using DDR_MTCR[MT_ADDR_EN] to limit the address range
to be tested: For any individual test, neither the starting address (DDR_MT_ST_EXT_ADDR ||
DDR_MT_ST_ADDR) nor the ending address (DDR_MT_END_EXT_ADDR || DDR_MT_END_ADDR)
can be less than that used during the previous test.
18.4.63 DDR Memory Test End Extended Address (DDR_MT_E
ND_EXT_ADDR)
18.4.63.1 Offset
Register Offset
DDR_MT_END_EXT_A D68h
DDR
18.4.63.2 Function
The DDR memory test end extended address register provides the extended address that
will be used with DDR_MTCR[MT_ADDR_EN] is set.
18.4.63.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
Reserved MT_END_EXT_ADDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 821
DDR register descriptions
18.4.63.4 Fields
Field Function
0-23 Reserved.
—
24-31 Memory Test End Extended Address.
MT_END_EXT_ This field represents the ending extended address that will be used when MTCR[MT_ADDR_EN] is set.
ADDR
Please note the following restriction when using DDR_MTCR[MT_ADDR_EN] to limit the address range
to be tested: For any individual test, neither the starting address (DDR_MT_ST_EXT_ADDR ||
DDR_MT_ST_ADDR) nor the ending address (DDR_MT_END_EXT_ADDR || DDR_MT_END_ADDR)
can be less than that used during the previous test.
18.4.64 DDR Memory Test End Address (DDR_MT_END_ADDR)
18.4.64.1 Offset
Register Offset
DDR_MT_END_ADDR D6Ch
18.4.64.2 Function
The DDR memory test end address register provides the address that will be used with
DDR_MTCR[MT_ADDR_EN] is set.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
822 NXP Semiconductors
Chapter 18 DDR Memory Controller
18.4.64.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
MT_END_ADDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
MT_END_ADDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.4.64.4 Fields
Field Function
0-31 Memory Test End Address.
MT_END_ADDR This field represents the ending address that will be used when MTCR[MT_ADDR_EN] is set.
Please note the following restriction when using DDR_MTCR[MT_ADDR_EN] to limit the address range
to be tested: For any individual test, neither the starting address (DDR_MT_ST_EXT_ADDR ||
DDR_MT_ST_ADDR) nor the ending address (DDR_MT_END_EXT_ADDR || DDR_MT_END_ADDR)
can be less than that used during the previous test.
18.4.65 Memory data path error injection mask high (DATA_ERR
_INJECT_HI)
18.4.65.1 Offset
Register Offset
DATA_ERR_INJECT_HI E00h
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 823
DDR register descriptions
18.4.65.2 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
EIMH
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
EIMH
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.4.65.3 Fields
Field Function
0-31 Error injection mask high data path.
EIMH Used to test ECC by forcing errors on the high word of the data path. Setting a bit causes the
corresponding data path bit to be inverted on memory bus writes.
18.4.66 Memory data path error injection mask low (DATA_ERR_
INJECT_LO)
18.4.66.1 Offset
Register Offset
DATA_ERR_INJECT_LO E04h
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
824 NXP Semiconductors
Chapter 18 DDR Memory Controller
18.4.66.2 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
EIML
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
EIML
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.4.66.3 Fields
Field Function
0-31 Error injection mask low data path.
EIML Used to test ECC by forcing errors on the low word of the data path. Setting a bit causes the
corresponding data path bit to be inverted on memory bus writes.
18.4.67 Memory data path error injection mask ECC (ECC_ERR_
INJECT)
18.4.67.1 Offset
Register Offset
ECC_ERR_INJECT E08h
18.4.67.2 Function
The memory data path error injection mask ECC register sets the ECC mask, enables
errors to be written to ECC memory, and allows the ECC byte to mirror the most
significant data byte. In addition, a single address parity error may be injected through
this register.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 825
DDR register descriptions
18.4.67.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
Reserved
Reserved
Reserved
Reserved
APIEN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
Reserved
EMB
EIE
EEI
W
M
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.4.67.4 Fields
Field Function
0 Reserved.
—
1-3 Reserved.
—
4-11 Reserved.
—
12-14 Reserved.
—
15 Address parity error injection enable.
APIEN This bit will be cleared by hardware after a single address parity error has been injected.
0b - Address parity error injection disabled.
1b - Address parity error injection enabled.
16-21 Reserved.
—
22 ECC Mirror Byte.
0b - Mirror byte functionality disabled.
EMB
1b - Mirror the most significant data path byte onto the ECC byte.
23 Error Injection Enable.
0b - Error injection disabled.
EIEN
1b - Error injection enabled. This applies to the data mask bits, the ECC mask bits, and the ECC
mirror bit. Note that error injection should not be enabled until the memory controller has been
enabled via DDR_SDRAM_CFG[MEM_EN].
24-31 ECC error injection mask.
EEIM Setting a mask bit causes the corresponding ECC bit to be inverted on memory bus writes.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
826 NXP Semiconductors
Chapter 18 DDR Memory Controller
18.4.68 Memory data path read capture high (CAPTURE_DATA_
HI)
18.4.68.1 Offset
Register Offset
CAPTURE_DATA_HI E20h
18.4.68.2 Function
The memory data path read capture high register stores the high word of the read data
path during error capture.
18.4.68.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
ECHD
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
ECHD
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.4.68.4 Fields
Field Function
0-31 Error capture high data path.
ECHD Captures the high word of the data path when errors are detected.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 827
DDR register descriptions
18.4.69 Memory data path read capture low (CAPTURE_DATA_
LO)
18.4.69.1 Offset
Register Offset
CAPTURE_DATA_LO E24h
18.4.69.2 Function
The memory data path read capture low register stores the low word of the read data path
during error capture.
18.4.69.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
ECLD
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
ECLD
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.4.69.4 Fields
Field Function
0-31 Error capture low data path.
ECLD Captures the low word of the data path when errors are detected.
18.4.70 Memory data path read capture ECC (CAPTURE_ECC)
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
828 NXP Semiconductors
Chapter 18 DDR Memory Controller
18.4.70.1 Offset
Register Offset
CAPTURE_ECC E28h
18.4.70.2 Function
The memory data path read capture ECC register stores the ECC syndrome bits that were
on the data bus when an error was detected.
18.4.70.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
ECE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
ECE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.4.70.4 Fields
Field Function
0-31 Error capture ECC.
ECE Captures the ECC bits on the data path whenever errors are detected.
32-bit mode:
• 0:7 should be ignored
• 8:15 8-bit ECC for the 32 bits in beats 0, 2, 4, 6 in 32-bit bus mode
• 16:23 should be ignored
• 24:31 8-bit ECC for the 32 bits in beats 1, 3, 5, 7 in 32-bit bus mode
16-bit mode:
• 0:7 8-bit ECC for the 16 bits in beats 0 and 4
• 8:15 8-bit ECC for the 16 bits in beats 1 and 5
• 16:23 8-bit ECC for the 16 bits in beats 2 and 6
• 24:31 8-bit ECC for the 16 bits in beats 3 and 7
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 829
DDR register descriptions
18.4.71 Memory error detect (ERR_DETECT)
18.4.71.1 Offset
Register Offset
ERR_DETECT E40h
18.4.71.2 Function
The memory error detect register stores the detection bits for multiple memory errors,
single- and multiple-bit ECC errors, and memory select errors. It is a read/write register.
A bit can be cleared by writing a one to the bit. System software can determine the type
of memory error by examining the contents of this register. If an error is disabled with
ERR_DISABLE, the corresponding error is never detected or captured in
ERR_DETECT.
18.4.71.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
W1C MME
R
Reserved
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
W1C CDE
W1C MBE
W1C ACE
W1C SSB
R
SB
W1C MS
Reserved
Reserved
Reserved
Reserved
W1C AP
E
E
E
E
W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
830 NXP Semiconductors
Chapter 18 DDR Memory Controller
18.4.71.4 Fields
Field Function
0 Multiple memory errors.
MME This bit is cleared by software writing a 1.
0b - Multiple memory errors of the same type were not detected.
1b - Multiple memory errors of the same type were detected.
1-14 Reserved.
—
15-18 Reserved.
—
19 Scrubbed single-bit ECC error.
SSBE This bit is cleared by software writing a 1.
0b - The number of scrubbed single-bit ECC errors detected has not crossed the threshold set in
ERR_SBE[SBET].
1b - The number of scrubbed single-bit ECC errors detected crossed the threshold set in
ERR_SBE[SBET].
20-22 Reserved.
—
23 Address parity error.
APE This bit is cleared by software writing a 1.
0b - An address parity error has not been detected.
1b - An address parity error has been detected.
24 Automatic calibration error.
ACE This bit is cleared by software writing a 1.
0b - An automatic calibration error has not been detected.
1b - An automatic calibration error has been detected.
25-26 Reserved.
—
27 Corrupted data error.
CDE This bit is cleared by software writing a 1.
0b - A corrupted data error has not been detected.
1b - A corrupted data error has been detected. This bit will be set if the actual ECC is inverted from
the expected ECC during a read command. The memory controller will intentionally invert the ECC
code if DDR_SDRAM_CFG_2[CD_DIS] is cleared when corrupted data is written to memory. The
ERR_DETECT[MBE] bit will also be set when a corrupted data error is detected. Note it is also
possible for a 2-bit data error to cause the ECC code to become inverted, which would either mask
a corrupted data error or cause a normal multi-bit error to also appear as a corrupted data error.
28 Multiple-bit error.
MBE This bit is cleared by software writing a 1.
0b - A multiple-bit error has not been detected.
1b - A multiple-bit error has been detected.
29 Single-bit ECC error.
SBE This bit is cleared by software writing a 1.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 831
DDR register descriptions
Field Function
0b - The number of single-bit ECC errors detected has not crossed the threshold set in
ERR_SBE[SBET].
1b - The number of single-bit ECC errors detected crossed the threshold set in ERR_SBE[SBET].
30 Reserved.
—
31 Memory select error.
MSE This bit is cleared by software writing a 1.
0b - A memory select error has not been detected.
1b - A memory select error has been detected.
18.4.72 Memory error disable (ERR_DISABLE)
18.4.72.1 Offset
Register Offset
ERR_DISABLE E44h
18.4.72.2 Function
The memory error disable register allows selective disabling of the DDR controller's
error detection circuitry. Disabled errors are not detected or reported.
18.4.72.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
Reserved
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
Reserved
Reserved
Reserved
Reserved
MSED
CDED
MBED
APED
ACED
SSBE
SBE
W
D
D
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
832 NXP Semiconductors
Chapter 18 DDR Memory Controller
18.4.72.4 Fields
Field Function
0-14 Reserved.
—
15-18 Reserved.
—
19 Scrubbed single-bit ECC error disable.
SSBED Note that if this bit is set, then single-bit ECC errors will not be automatically fixed by hardware, even if
ECC scrubbing is enabled.
0b - Scrubbed single-bit ECC errors are enabled.
1b - Scrubbed single-bit ECC errors are disabled.
20-22 Reserved.
—
23 Address parity error disable.
0b - Address parity errors are detected if DDR_SDRAM_CFG_2[AP_EN] is set. They are reported if
APED
ERR_INT_EN[APEE] is set.
1b - Address parity errors are not detected or reported.
24 Automatic calibration error disable.
0b - Automatic calibration errors are enabled.
ACED
1b - Automatic calibration errors are disabled.
25-26 Reserved.
—
27 Corrupted data error disable.
0b - Corrupted data error checking is enabled.
CDED
1b - Corrupted data error checking is disabled.
28 Multiple-bit ECC error disable.
0b - Multiple-bit ECC errors are detected if DDR_SDRAM_CFG[ECC_EN] is set. They are reported
MBED
if ERR_INT_EN[MBEE] is set. See Error Management for more information.MBED must be zero
and ERR_INT_EN[MBEE] and ECC_EN must be one to ensure that an interrupt is generated.
1b - Multiple-bit ECC errors are not detected or reported.
29 Single-bit ECC error disable.
SBED Note that if this bit is set, then single-bit ECC errors will not be automatically fixed by hardware, even if
ECC fixing is enabled.
0b - Single-bit ECC errors are enabled.
1b - Single-bit ECC errors are disabled.
30 Reserved
—
31 Memory select error disable.
0b - Memory select errors are enabled.
MSED
1b - Memory select errors are disabled.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 833
DDR register descriptions
18.4.73 Memory error interrupt enable (ERR_INT_EN)
18.4.73.1 Offset
Register Offset
ERR_INT_EN E48h
18.4.73.2 Function
The memory error interrupt enable register enables ECC interrupts or memory select
error interrupts. When an enabled interrupt condition occurs, the internal int_B signal is
asserted to the programmable interrupt controller (PIC).
18.4.73.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
Reserved
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
Reserved
Reserved
Reserved
Reserved
SSBE
SBE
MSE
CDE
MBE
APE
ACE
W
E
E
E
E
E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.4.73.4 Fields
Field Function
0-14 Reserved.
—
15-18 Reserved.
—
19 Scrubbed single-bit ECC error interrupt enable.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
834 NXP Semiconductors
Chapter 18 DDR Memory Controller
Field Function
SSBEE 0b - Scrubbed single-bit ECC errors cannot generate interrupts.
1b - Scrubbed single-bit ECC errors generate interrupts.
20-22 Reserved.
—
23 Address parity error interrupt enable.
0b - Address parity errors cannot generate interrupts.
APEE
1b - Address parity errors generate interrupts.
24 Automatic calibration error interrupt enable.
0b - Automatic calibration errors cannot generate interrupts.
ACEE
1b - Automatic calibration errors generate interrupts.
25-26 Reserved.
—
27 Corrupted data error interrupt enable.
0b - Corrupted data errors cannot generate interrupts.
CDEE
1b - Corrupted data errors generate interrupts.
28 Multiple-bit ECC error interrupt enable.
MBEE See Error Management for more information. Note that uncorrectable read errors may cause an interrupt.
ERR_DISABLE[MBED] must be zero and MBEE and DDR_SDRAM_CFG[ECC_EN] must be set to
ensure that an interrupt is generated.
0b - Multiple-bit ECC errors cannot generate interrupts.
1b - Multiple-bit ECC errors generate interrupts.
29 Single-bit ECC error interrupt enable.
0b - Single-bit ECC errors cannot generate interrupts.
SBEE
1b - Single-bit ECC errors generate interrupts.
30 Reserved
—
31 Memory select error interrupt enable.
0b - Memory select errors do not cause interrupts.
MSEE
1b - Memory select errors generate interrupts.
18.4.74 Memory error attributes capture (CAPTURE_ATTRIBUT
ES)
18.4.74.1 Offset
Register Offset
CAPTURE_ATTRIBUT E4Ch
ES
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 835
DDR register descriptions
18.4.74.2 Function
The memory error attributes capture register sets attributes for errors including type, size,
source, and others.
18.4.74.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
Reserved
Reserved
BNUM
TSIZ
TSR
W
C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
Reserved
Reserved
TTYP
VLD
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.4.74.4 Fields
Field Function
0 Reserved.
—
1-3 Data beat number.
BNUM Captures the doubleword number for the detected error. Relevant only for ECC errors.
4 Reserved.
—
5-7 Transaction size for the error.
TSIZ Captures the transaction size in double words.
000b - 8 double words
001b - 1 double word
010b - 2 double words
011b - 3 double words
100b - 4 double words
101b - 5 double word
110b - 6 double words
111b - 7 double words
8-15 Transaction source for the error.
TSRC See the Global Source and Target IDs section in the Memory Map chapter for the defined encoding.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
836 NXP Semiconductors
Chapter 18 DDR Memory Controller
Field Function
16-17 Reserved.
—
18-19 Transaction type for the error.
00b - Reserved
TTYP
01b - Write
10b - Read
11b - Read-modify-write
20-30 Reserved.
—
31 Valid.
VLD Set as soon as valid information is captured in the error capture registers.
18.4.75 Memory error address capture (CAPTURE_ADDRESS)
18.4.75.1 Offset
Register Offset
CAPTURE_ADDRESS E50h
18.4.75.2 Function
The memory error address capture register holds the 32 lsbs of a transaction when a DDR
ECC error is detected.
18.4.75.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
CADDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
CADDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 837
DDR register descriptions
18.4.75.4 Fields
Field Function
0-31 Captured address.
CADDR Captures the 32 lsbs of the transaction address when an error is detected.
18.4.76 Memory error extended address capture (CAPTURE_
EXT_ADDRESS)
18.4.76.1 Offset
Register Offset
CAPTURE_EXT_ADDR E54h
ESS
18.4.76.2 Function
The memory error extended address capture register holds the four most significant
transaction bits when an error is detected.
18.4.76.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
Reserved CEADDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
838 NXP Semiconductors
Chapter 18 DDR Memory Controller
18.4.76.4 Fields
Field Function
0-23 Reserved.
—
24-31 Captured extended address.
CEADDR Captures the 8 msbs of the transaction address when an error is detected
18.4.77 Single-Bit ECC memory error management (ERR_SBE)
18.4.77.1 Offset
Register Offset
ERR_SBE E58h
18.4.77.2 Function
The single-bit ECC memory error management register stores the threshold value for
reporting single-bit errors and the number of single-bit errors counted since the last error
report. When the counter field reaches the threshold, it wraps back to the reset value (0).
If necessary, software must clear the counter after it has managed the error.
18.4.77.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
SSBET SBET
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
SSBEC SBEC
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 839
DDR Functional Description
18.4.77.4 Fields
Field Function
0-7 Scrubbed single-bit error threshold.
SSBET Establishes the number of single-bit errors that must be detected and fixed during ECC scrubbing before
an error condition is reported.
8-15 Single-bit error threshold.
SBET Establishes the number of single-bit errors that must be detected before an error condition is reported.
16-23 Scrubbed single-bit error counter.
SSBEC Indicates the number of scrubbed single-bit errors detected and fixed in memory since the last error
report. This counter is incremented only if a single-bit error is detected during the ECC interval scrubbing.
If single-bit error reporting is enabled, an error is reported and an interrupt is generated when this value
equals SSBET. SSBEC is automatically cleared when the threshold value is reached.
24-31 Single-bit error counter.
SBEC Indicates the number of single-bit errors detected and corrected since the last error report. If single-bit
error reporting is enabled, an error is reported and an interrupt is generated when this value equals
SBET. SBEC is automatically cleared when the threshold value is reached.
18.5 DDR Functional Description
The DDR SDRAM controller controls processor and I/O interactions with system
memory. The memory system allows a wide range of memory devices to be mapped to
any arbitrary chip select, and support is provided for unbuffered DIMMs.
The figure below is a high-level block diagram of the DDR memory controller. Requests
are received from the internal mastering device and the address is decoded to generate the
physical bank, logical bank, row, and column addresses. The transaction is compared
with values in the row open table to determine if the address maps to an open page. If the
transaction does not map to an open page, an active command is issued.
Programmable parameters allow for a variety of memory organizations and timings.
Optional error checking and correcting (ECC) protection is provided for the DDR
SDRAM data bus. Using ECC, the DDR memory controller detects and corrects all
single-bit errors within the data bus, detects all double-bit errors within the data bus, and
detects all errors within a nibble. The controller allows as many as 64 pages to be open
simultaneously. The amount of time (in clock cycles) the pages remain open is
programmable with DDR_SDRAM_INTERVAL[BSTOPRE].
NOTE
When ECC DRAM is present ECC should be enabled.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
840 NXP Semiconductors
Chapter 18 DDR Memory Controller
DDR SDRAM
Request from Memory Array
master Row
Address Address MA[n]
Open
Address from Decode Control MBA[n]
Table
master
DDR SDRAM
Memory Control
MCS[n]
MCAS_B
SDRAM MRAS_B
Control MWE_B
MDM[n]
EN MCKE[n]
To Error Error DQ MODT[n]
Signals ECC
Management
Delay chain Data Strobes
MDQS[n]
Data from DQ MDQS[n]_B
POS
SDRAM
FIFO
NEG Data Signals
FIFO MDQ[n]
MECC[n]
RMW EN
DQ
Data from ECC
master Clocks
SDRAM MCK[n]_B
Control
MCK[n]
Figure 18-2. DDR Memory Controller Block Diagram
Read and write accesses to memory are burst oriented; accesses start at a selected
location and continue for a programmed number of higher locations (4 or 8) in a
programmed sequence. Accesses to closed pages start with the registration of an
ACTIVE command followed by a READ or WRITE. (Accessing open pages does not
require an ACTIVE command.) The address bits registered coincident with the activate
command specifies the logical bank and row to be accessed. The address coincident with
the READ or WRITE command specify the logical bank and starting column for the burst
access.
The data interface is source synchronous, meaning whatever sources the data also
provides a clocking signal to synchronize data reception. These bidirectional data strobes
( MDQS[0:3], MDQS8) are inputs to the controller during reads and outputs during
writes. The DDR SDRAM specification requires the data strobe signals to be centered
within the data tenure during writes and to be offset by the controller to the center of the
data tenure during reads. This delay is implemented in the controller for both reads and
writes.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 841
DDR Functional Description
When ECC is enabled, 1 clock cycle is added to the read path to check ECC and correct
single-bit errors. ECC generation does not add a cycle to the write path.
The address and command interface is also source synchronous, although 1/16 cycle
adjustments are provided for adjusting the clock alignment.
This figure shows an example DDR SDRAM configuration with four physical banks each
comprised of four 8M x 8 DDR modules for a total of 256 Mbytes of system memory.
One of the nine modules is used for the memory's ECC checking function. Certain
address and control lines may require buffering. Analysis of the device's AC timing
specifications, desired memory operating frequency, capacitive loads, and board routing
loads can assist the system designer in deciding signal buffering requirements. The DDR
memory controller drives 16 address pins, but in this example the DDR SDRAM devices
use only 12 bits.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
842 NXP Semiconductors
Chapter 18 DDR Memory Controller
Figure 18-3. Example 256-Mbyte DDR SDRAM Configuration
Error Management explains how the DDR memory controller handles errors.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 843
DDR Functional Description
18.5.1 DDR SDRAM Interface Operation
The DDR memory controller supports many different DDR SDRAM configurations; see
Supported DDR SDRAM Organizations for details. SDRAMs with different sizes can be
used in the same system. Sixteen multiplexed address signals and three logical bank
select signals support numerous device densities. Four chip select (CS_B) signals support
up to two DIMMs of memory. The DDR SDRAM physical banks can be built from
standard memory modules or directly-attached memory devices. The data path to
individual physical banks is 32 bits wide, 36 bits with ECC. The controller supports
physical bank sizes of up to 16 Gbytes. The physical banks can be constructed using x 8,
x16, or x32 (with 1 DQS per data byte) memory devices. Five data qualifier (DQM)
signals provide byte selection for memory accesses.
NOTE
An 8-bit DDR SDRAM device has a DQM signal and eight
data signals (DQ[0:7]). A 16-bit DDR SDRAM device has two
DQM signals associated with specific halves of the 16 data
signals (DQ[0:7] and DQ[8:15]).
When ECC is enabled, all memory accesses are performed on double-word boundaries
(that is, all DQM signals are set simultaneously). However, when ECC is disabled, the
memory system uses the DQM signals for byte lane selection when using x8 or x16
devices.
This table shows the relationships between data byte lanes, MDMn, MDQSn, and MDQn
when DDR SDRAM memories are used with x8 or x16 devices.
Table 18-9. Byte Lane to Data Relationship for x8 and x16 devices
Data Byte Lane Data Bus Mask Data Bus Strobe Data Bus
0 (MSB) MDM[0] MDQS[0]/MDQS_B[0] MDQ[0:7]
1 MDM[1] MDQS[1]/MDQS_B[1] MDQ[8:15]
2 MDM[2] MDQS[2]/MDQS_B[2] MDQ[16:23]
3 (LSB) MDM[3] MDQS[3]/MDQS_B[3] MDQ[24:31]
8 (ECC) MDM8 MDQS8/MDQS8_B MECC[0:3]
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
844 NXP Semiconductors
Chapter 18 DDR Memory Controller
18.5.1.1 Supported DDR SDRAM Organizations
These tables describe DDR SDRAM device configurations supported by the DDR
memory controller.
Table 18-10. Supported SDRAM Device Configurations, DDR3 Memory Types
SDRAM Device Device Configuration Row x Column x Sub- 32-Bit Bank Size Four Banks of
bank Bits Memory
512 Mbits 64 Mbits x 8 13 x 10 x 3 256 Mbytes 1 Gbyte
512 Mbits 32 Mbits x 16 12 x 10 x 3 128 Mbytes 512 Mbytes
1 Gbits 128 Mbits x 8 14 x 10 x 3 512 Mbytes 2 Gbytes
1 Gbits 64 Mbits x 16 13 x 10 x 3 256 Mbytes 1 Gbyte
2 Gbits 256 Mbits x 8 15 x 10 x 3 1 Gbyte 4 Gbytes
2 Gbits 128 Mbits x 16 14 x 10 x 3 512 Mbytes 2 Gbytes
4 Gbits 512 Mbits x 8 16 x 10 x 3 2 Gbytes 8 Gbytes
4 Gbits 256 Mbits x 16 15 x 10 x 3 1 Gbyte 4 Gbytes
Table 18-11. Supported SDRAM Device Configurations, DDR4
SDRAM Device Device Configuration Row x Column x Sub- 32-Bit Bank Size Four Banks of
bank x Bank Group Memory
Bits
2 Gbits 256 Mbits x 8 14 x 10 x 2 x 2 1 Gbyte 4 Gbytes
2 Gbits 128 Mbits x 16 14 x 10 x 2 x 1 512 Mbytes 2 Gbytes
4 Gbits 512 Mbits x 8 15 x 10 x 2 x 2 2 Gbytes 8 Gbytes
4 Gbits 256 Mbits x 16 15 x 10 x 2 x 1 1 Gbyte 4 Gbytes
8 Gbits 1 Gbit x 8 16 x 10 x 2 x 2 4 Gbytes 16 Gbytes
8 Gbits 512 Mbits x 16 16 x 10 x 2 x 1 2 Gbytes 8 Gbytes
16 Gbits 2 Gbits x 8 17 x 10 x 2 x 2 8 Gbytes 32 Gbytes
16 Gbits 1 Gbit x 16 17 x 10 x 2 x 1 4 Gbytes 16 Gbytes
If a transaction request is issued to the DDR memory controller and the address does not
lie within any of the programmed address ranges for an enabled chip select, a memory
select error is flagged. Errors are described in detail in Error Management
By using a memory-polling algorithm at power-on reset or by querying the JEDEC serial
presence detect capability of memory modules, system firmware uses the memory-
boundary registers to configure the DDR memory controller to map the size of each bank
in memory. The memory controller uses its bank map to assert the appropriate MCSn_B
signal for memory accesses according to the provided bank starting and ending addresses.
The memory banks are not required to be mapped to a contiguous address space.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 845
DDR Functional Description
18.5.2 DDR SDRAM Address Multiplexing
The following tables show the address bit encodings for each DDR SDRAM
configuration. The address presented at the memory controller signals MA[17:0] use
MA[17] as the msb and MA[0] as the lsb. Also, MA[10] is used as the auto-precharge bit
for reads and writes, so the column address can never use MA[10].
Table 18-12. Address Multiplexing using DDR3 Memory Types for 32-Bit Data Bus with
Interleaving and Partial Array Self Refresh Disabled
Row Address from Core Master
msb
lsb
x
8 9 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 38-3
Col
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 9
MRAS_ 1 1 1 1 1 10 9 8 7 6 5 4 3 2 1 0
16 x 10 x 3
B 5 4 3 2 1
MBA 2 1 0
MCAS_ 9 8 7 6 5 4 3 2 1 0
B
MRAS_ 1 1 1 1 10 9 8 7 6 5 4 3 2 1 0
15 x 10 x 3
B 4 3 2 1
MBA 2 1 0
MCAS_ 9 8 7 6 5 4 3 2 1 0
B
MRAS_ 1 1 1 10 9 8 7 6 5 4 3 2 1 0
14 x 10 x 3
B 3 2 1
MBA 2 1 0
MCAS_ 9 8 7 6 5 4 3 2 1 0
B
MRAS_ 1 1 10 9 8 7 6 5 4 3 2 1 0
13 x 10 x 3
B 2 1
MBA 2 1 0
MCAS_ 9 8 7 6 5 4 3 2 1 0
B
MRAS_ 1 10 9 8 7 6 5 4 3 2 1 0
12 x 10 x 3
B 1
MBA 2 1 0
MCAS_ 9 8 7 6 5 4 3 2 1 0
B
Chip select interleaving is supported for the memory controller, and is programmed in
DDR_SDRAM_CFG[BA_INTLV_CTL]. Interleaving is supported between chip selects
0 and 1 or chip selects 2 and 3. In addition, interleaving between all four chip selects can
be enabled. When interleaving is enabled, the chip selects being interleaved must use the
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
846 NXP Semiconductors
Chapter 18 DDR Memory Controller
same size of memory. If two chip selects are interleaved, then 1 extra bit in the address
decode is used for the interleaving to determine which chip select to access. If four chip
selects are interleaved, then two extra bits are required in the address decode.
The following table illustrates examples of address decode when interleaving between
two chip selects.
Table 18-13. Example of Address Multiplexing for 32/64-Bit Data Bus Interleaving Between
Two Banks with Partial Array Self Refresh Disabled
Row ms Address from Core Master lsb
b
x
8 9 1 1 1 1 1 1 1 1 1 1 2 2 2 23 24 2 2 2 2 2 3 3 3 3 3 3 3 37-3
Col
0 1 2 3 4 5 6 7 8 9 0 1 2 5 6 7 8 9 0 1 2 3 4 5 6 9
1 1 1 1 9 8 7 6 5 4 3 2 1 0 CS
MCAS_B MBA MRAS_B MCAS_B MBA MRAS_B
14 x 10 x 3
3 2 1 0 SEL
2 1 0
9 8 7 6 5 4 3 2 1 0
1 1 1 9 8 7 6 5 4 3 2 1 0 CS
13 x 10 x 3
2 1 0 SEL
2 1 0
9 8 7 6 5 4 3 2 1 0
Table 18-14. Example of Address Multiplexing for 32/64-Bit Data Bus Interleaving Between
Two Banks
m Address from Core Master lsb
s
b
Row x Col 6 7 8 9 1 1 1 1 1 1 1 1 1 1 20 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 37-3
0 1 2 3 4 5 6 7 8 9 1 2 3 5 6 7 8 9 0 1 2 3 4 5 6 9
Row x Col 3 3 3 2 2 2 2 2 2 2 2 2 2 1 18 1 1 1 1 1 1 1 1 9 8 7 6 5 4 3 2-0
2 1 0 9 8 7 6 5 4 3 2 1 0 9 7 6 5 4 3 2 1 0
1 1 1 1 9 8 7 6 5 4 3 2 1 0
CS_SE MACT_B
14 x 10 x 3
3 2 1 0
0
L
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 847
DDR Functional Description
Table 18-14. Example of Address Multiplexing for 32/64-Bit Data Bus Interleaving Between
Two Banks (continued)
m Address from Core Master lsb
s
b
Row x Col 6 7 8 9 1 1 1 1 1 1 1 1 1 1 20 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 37-3
0 1 2 3 4 5 6 7 8 9 1 2 3 5 6 7 8 9 0 1 2 3 4 5 6 9
Row x Col 3 3 3 2 2 2 2 2 2 2 2 2 2 1 18 1 1 1 1 1 1 1 1 9 8 7 6 5 4 3 2-0
2 1 0 9 8 7 6 5 4 3 2 1 0 9 7 6 5 4 3 2 1 0
1 0
MCAS_B MBA MBG CS_SE MACT_B MCAS_B MBA MBG
1 0
9 8 7 6 5 4 3 2 1 0
1 1 1 9 8 7 6 5 4 3 2 1 0
13 x 10 x 3
2 1 0
0
L
1 0
1 0
9 8 7 6 5 4 3 2 1 0
Partial Array Self Refresh (PASR) can be enabled for any chip select using the
CSn_CONFIG_2[PASR_CFG] fields. If PASR is enabled for a given chip select, then the
sub-bank and row decode will be swapped, and the sub-bank will be decoded as the most
significant portion of the DRAM address, as shown in this table.
Table 18-15. Address Multiplexing with Partial Array Self Refresh Enabled
Row ms Address from Core Master lsb
b
x
8 9 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 38-3
Col
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 9
1 1 13 1 1 1 9 8 7 6 5 4 3 2 1 0
MBA MRAS_B
16 x 10 x 3
5 4 2 1 0
2 1 0
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
848 NXP Semiconductors
Chapter 18 DDR Memory Controller
Table 18-15. Address Multiplexing with Partial Array Self Refresh Enabled (continued)
Row ms Address from Core Master lsb
b
x
8 9 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 38-3
Col
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 9
9 8 7 6 5 4 3 2 1 0
MCAS_B MBA MRAS_B MCAS_B MBA MRAS_B MCAS_B MBA MRAS_B MCAS_B MBA MRAS_B MCAS_B
1 13 1 1 1 9 8 7 6 5 4 3 2 1 0
15 x 10 x 3
4 2 1 0
2 1 0
9 8 7 6 5 4 3 2 1 0
13 1 1 1 9 8 7 6 5 4 3 2 1 0
14 x 10 x 3
2 1 0
2 1 0
9 8 7 6 5 4 3 2 1 0
1 1 1 9 8 7 6 5 4 3 2 1 0
13 x 10 x 3
2 1 0
2 1 0
9 8 7 6 5 4 3 2 1 0
1 1 9 8 7 6 5 4 3 2 1 0
12 x 10 x 3
1 0
2 1 0
9 8 7 6 5 4 3 2 1 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 849
DDR Functional Description
18.5.3 DDR SDRAM Write Timing Adjustments
The DDR memory controller facilitates system design flexibility by providing a write
timing adjustment calculated by write leveling for data and DQS. The DDR SDRAM
specification requires DQS be received no sooner than 75% of an SDRAM clock period-
and no later than 125% of a clock period-from the capturing clock edge of the command/
address at the SDRAM. The write leveling calibration is used to meet this timing
requirement for a variety of system configurations, ranging from a system with one
DIMM to a fully populated system with two DIMMs. DDR_WRLVL_CNTL is used to
set up and enable write leveling.
18.5.4 DDR SDRAM Refresh
The DDR memory controller supports auto-refresh and self-refresh. Auto refresh is used
during normal operation and is controlled by the DDR_SDRAM_INTERVAL[REFINT]
value; self-refresh is used only when the DDR memory controller is set to enter a sleep
power management state. The REFINT value, which represents the number of memory
bus clock cycles between refresh cycles, must allow for possible outstanding transactions
to complete before a refresh request is sent to the memory after the REFINT value is
reached. If a memory transaction is in progress when the refresh interval is reached, the
refresh cycle waits for the transaction to complete. In the worst case, the refresh cycle
must wait the number of bus clock cycles required by the longest programmed access. To
ensure that the latency caused by a memory transaction does not violate the device
refresh period, it is recommended that the programmed value of REFINT be less than that
required by the SDRAM.
When a refresh cycle is required, the DDR memory controller does the following:
1. Completes all current memory requests.
2. Closes all open pages with a PRECHARGE-ALL command to each DDR SDRAM
bank with an open page (as indicated by the row open table).
3. Issues one or more auto-refresh commands to each DDR SDRAM bank (as identified
by its chip select) to refresh one row in each logical bank of the selected physical
bank.
The auto-refresh commands are staggered across the four possible banks to reduce the
system's instantaneous power requirements. Two sets of auto refresh commands will be
issued on consecutive cycles when the memory is fully populated with two DIMMs. The
initial PRECHARGE-ALL commands are also staggered in two groups for convenience.
It is important to note that when entering self-refresh mode, only one refresh command is
issued simultaneously to all physical banks. For this entire refresh sequence, no cycle
optimization occurs for the usual case where fewer than four banks are installed. After
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
850 NXP Semiconductors
Chapter 18 DDR Memory Controller
the refresh sequence completes, any pending memory request is initiated after an inactive
period specified by TIMING_CFG_1 [REFREC] and TIMING_CFG_3[EXT_REFREC].
In addition, posted refreshes are supported to allow the refresh interval to be set to a
larger value.
18.5.4.1 DDR SDRAM Refresh Timing
Refresh timing for the DDR SDRAM is controlled by the programmable timing
parameter TIMING_CFG_1 [REFREC], which specifies the number of memory bus
clock cycles from the refresh command until a logical bank activate command is allowed.
The DDR memory controller implements bank staggering for refreshes, as shown in this
figure (TIMING_CFG_1 [REFREC] = 10 in this example).
Figure 18-4. DDR SDRAM Bank Staggered Auto Refresh Timing
System software is responsible for optimal configuration of TIMING_CFG_1 [REFREC]
and TIMING_CFG_3[EXT_REFREC] at reset. Configuration must be completed before
DDR SDRAM accesses are attempted.
18.5.4.2 DDR SDRAM Refresh and Power-Saving Modes
In full-on mode, the DDR memory controller supplies the normal auto refresh to
SDRAM. In sleep mode, the DDR memory controller can be configured to take
advantage of self-refreshing SDRAMs or to provide no refresh support. Self-refresh
support is enabled with the SREN memory control parameter.
This table summarizes the refresh types available in each power-saving mode.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 851
DDR Functional Description
Table 18-16. DDR SDRAM Power-Saving Modes Refresh Configuration
Power Saving Mode Refresh Type SREN
Sleep Self 1
None -
Note that in the absence of refresh support, system software must preserve DDR SDRAM
data (such as by copying the data to disk) before entering the power-saving mode.
The dynamic power-saving mode uses the CKE DDR SDRAM pin to dynamically power
down when there is no system memory activity. The CKE pin is negated when both of
the following conditions are met:
• No memory refreshes are scheduled
• No memory accesses are scheduled
CKE is reasserted when a new access or refresh is scheduled or the dynamic power mode
is disabled. This mode is controlled with DDR_SDRAM_CFG[DYN_PWR_MGMT].
Dynamic power management mode offers tight control of the memory system's power
consumption by trading power for performance through the use of CKE. Powering up the
DDR SDRAM when a new memory reference is scheduled causes an access latency
penalty, depending on whether active or precharge powerdown is used, along with the
settings of TIMING_CFG_0[ACT_PD_EXIT] and TIMING_CFG_0[PRE_PD_EXIT].
18.5.5 DDR Data Beat Ordering
Transfers to and from memory are always performed in four- or eight-beat bursts. For
transfer sizes other than four or eight beats, the data transfers are still operated as four- or
eight-beat bursts. If ECC is enabled and either the access is not doubleword aligned or the
size is not a multiple of a doubleword, a full read-modify-write is performed for a write
to SDRAM. If ECC is disabled or both the access is doubleword aligned with a size that
is a multiple of a doubleword, the data masks ((MDM[0:3], MDM8) can be used to
prevent the writing of unwanted data to SDRAM. The DDR memory controller also uses
data masks to prevent all unintended full double words from writing to SDRAM. For
example, if a write transaction is desired with a size of one double word (8 bytes), then
the remaining Seven beats of data are not written to DRAM.
All writes for DDR3/DDR4 mode will be aligned to beat 0 of the DRAM.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
852 NXP Semiconductors
Chapter 18 DDR Memory Controller
18.5.6 Page Mode and Logical Bank Retention
The DDR memory controller supports an open/closed page mode with an allowable open
page for each logical bank (and bank group for DDR4) of DRAM used. In closed page
mode for DDR SDRAMs, the DDR memory controller uses the SDRAM auto-precharge
feature, which allows the controller to indicate that the page must be automatically closed
by the DDR SDRAM after the READ or WRITE access. This is performed by using
MA[10] of the address during the COMMAND phase of the access to enable auto-
precharge. Auto-precharge is non-persistent in that it is either enabled or disabled for
each individual READ or WRITE command. It can, however, be enabled or disabled
separately for each chip select.
When the DDR memory controller operates in open page mode, it retains the currently
active SDRAM page by not issuing a precharge command. The page remains opens until
one of the following conditions occurs:
• Refresh interval is met.
• The user-programmable DDR_SDRAM_INTERVAL[BSTOPRE] value is exceeded.
• There is a logical bank row collision with another transaction that must be issued.
Page mode can dramatically reduce access latencies for page hits. Depending on the
memory system design and timing parameters, using page mode can save two to three
clock cycles for subsequent burst accesses that hit in an active page. Also, better
performance can be obtained by using more banks, especially in systems which use many
different channels. Page mode is disabled by clearing
DDR_SDRAM_INTERVAL[BSTOPRE] or setting CS n_CONFIG[AP_ nEN].
18.5.7 Error Checking and Correcting (ECC)
The DDR memory controller supports error checking and correcting (ECC) for the data
path between the core master and system memory. The memory detects all double-bit
errors, detects all multi-bit errors within a nibble, and corrects all single-bit errors. Other
errors may be detected, but are not guaranteed to be corrected or detected. Double-bit
errors are always reported when error reporting is enabled. When a single-bit error
occurs, the single-bit error counter register is incremented, and its value compared to the
single-bit error trigger register. An error is reported when these values are equal. The
single-bit error registers can be programmed such that minor memory faults are corrected
and ignored, but a catastrophic memory failure generates an interrupt.
For writes that are smaller than 64 bits, the DDR memory controller performs a double-
word read from system memory of the address for the write (checking for errors), and
merges the write data with the data read from memory. Then, a new ECC code is
generated for the merged double word. The data and ECC code is then written to
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 853
DDR Functional Description
memory. If a multi-bit error is detected on the read, the transaction completes the read-
modify-write to keep the DDR memory controller from hanging. However, the corrupt
data is masked on the write, so the original contents in SDRAM remain unchanged.
The DDR controller also supports ECC scrubbing, which is enabled via
DDR_SDRAM_CFG_3[ECC_SCRUB_EN]. In this mode, all single-bit errors detected
will be fixed by hardware. In addition, DDR_SDRAM_CFG_3[ECC_SCRUB_INT] can
be programmed to enable periodic reads by the DDR controller to search for and fix
single-bit errors.
The syndrome encodings for the ECC code are shown in these tables.
Table 18-17. DDR SDRAM ECC Syndrome Encoding
Data Bit Syndrome Bit Data Bit Syndrome Bit
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
0 • • • 32 • • •
1 • • • 33 • • •
2 • • • 34 • • •
3 • • • 35 • • •
4 • • • 36 • • •
5 • • • 37 • • •
6 • • • 38 • • • • •
7 • • • 39 • • • • •
8 • • • 40 • • •
9 • • • 41 • • •
10 • • • 42 • • • • •
11 • • • 43 • • • • •
12 • • • • • 44 • • • • •
13 • • • • • 45 • • • • •
14 • • • • • 46 • • • • •
15 • • • • • 47 • • • • •
16 • • • 48 • • •
17 • • • 49 • • •
18 • • • 50 • • •
19 • • • 51 • • •
20 • • • 52 • • •
21 • • • 53 • • •
22 • • • 54 • • •
23 • • • • • 55 • • •
24 • • • 56 • • •
25 • • • 57 • • •
26 • • • 58 • • •
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
854 NXP Semiconductors
Chapter 18 DDR Memory Controller
Table 18-17. DDR SDRAM ECC Syndrome Encoding
(continued)
Data Bit Syndrome Bit Data Bit Syndrome Bit
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
27 • • • • • 59 • • •
28 • • • • • 60 • • •
29 • • • • • 61 • • • • •
30 • • • • • 62 • • • • •
31 • • • • • 63 • • • • •
Table 18-18. DDR SDRAM ECC Syndrome Encoding (Check Bits)
Check Bit Syndrome Bit
0 1 2 3 4 5 6 7
0 •
1 •
2 •
3 •
4 •
5 •
6 •
7 •
18.5.8 Error Management
The DDR memory controller detects four different kinds of errors: training, single-bit,
multi-bit, and memory select errors. The following discussion assumes all the relevant
error detection, correction, and reporting functions are enabled as described in Memory
error interrupt enable (ERR_INT_EN), Memory error disable (ERR_DISABLE), and
Memory error detect (ERR_DETECT)
Single-bit errors are counted and reported based on the ERR_SBE value. When a single-
bit error is detected, the DDR memory controller does the following:
• Corrects the data
• Increments the single-bit error counter ERR_SBE[SBEC]
• Generates a critical interrupt if the counter value ERR_SBE[SBEC] equals the
programmable threshold ERR_SBE[SBET]
• Completes the transaction normally
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 855
DDR Functional Description
If a multi-bit error is detected for a read, the DDR memory controller logs the error and
generates the machine check or critical interrupt (if enabled, as described in Memory
error disable (ERR_DISABLE)). Another error the DDR memory controller detects is a
memory select error, which causes the DDR memory controller to log the error and
generate a critical interrupt (if enabled, as described in Memory error detect (ERR_DETE
CT)). This error is detected if the address from the memory request does not fall into any
of the enabled, programmed chip select address ranges. For all memory select errors, the
DDR memory controller does not issue any transactions onto the pins after the first read
has returned data strobes. If the DDR memory controller is not using sample points, then
a dummy transaction is issued to DDR SDRAM with the first enabled chip select. In this
case, the source port on the pins is forced to 0x1F to show the transaction is not real.
Table 18-19 shows the errors with their descriptions. The final error the memory
controller detects is the automatic calibration error. This error is set if the memory
controller detects an error during its training sequence.
Table 18-19. Memory Controller Errors
Category Error Descriptions Action Detect Register
Notification Single-bit ECC The number of ECC errors has reached the The error is The error control
threshold threshold specified in the ERR_SBE. reported via regular register only logs
or critical interrupt if read versus write,
enabled. not full type
Access Error Multi-bit ECC A multi-bit ECC error is detected during a read, The error is
error or read-modify-write memory operation. reported via
machine check or
Memory select Read, or write, address does not fall within the
critical interrupt if
error address range of any of the memory banks.
enabled.
18.5.9 DDR Rapid Clear of Memory
Upon Hard Fail condition, the security monitor drives an interrupt to the DDR controller
indicating the memory needs to be cleared, the DDR controller will clear all of memory
defined by the CSn_BNDS registers for all enabled chip selects. DDRDSR_2[RPD_ST]
will be set once the DDR controller begins clearing memory. At this time, writes to the
DDR CCSR space are not allowed to modify the register values. Once the rapid clear of
memory sequence is complete, writes to the DDR registers may proceed. The
DDRDSR_2[RPD_EN] bit is provided so software can determine when the rapid clear of
memory sequence is complete and can therefore update registers again. Software can
clear the RPD_ST and RPD_EN bits after the rapid memory clear is complete.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
856 NXP Semiconductors
Chapter 18 DDR Memory Controller
18.6 Initialization/Application Information
At system reset or start-up, initialization software (boot code) must set up the
programmable parameters in the memory interface configuration registers. See DDR
register descriptions for more detailed descriptions of the configuration registers. These
parameters are shown in this table.
Table 18-20. Memory Interface Configuration Register Initialization Parameters
Name Description Parameter Section/Page
CS n_BNDS Chip select memory bounds SA Chip select a memory bounds
(CS0_BNDS - CS3_BNDS)
EA
CS n_CONFIG Chip select configuration CS_EN Chip select a configuration
(CS0_CONFIG - CS3_CONF
AP_EN
IG)
ODT_RD_CFG
ODT_WR_CFG
BA_BITS_CS
ROW_BITS_CS
BG_BITS_CS
COL_BITS_CS
TIMING_CFG_3 Extended timing parameters EXT_PRETOACT DDR SDRAM timing
for fields in TIMING_CFG_1 configuration 3 (TIMING_C
EXT_ACTTOPRE
FG_3)
EXT_ACTTORW
EXT_REFREC
EXT_CASLAT
EXT_WRREC
CNTL_ADJ
TIMING_CFG_0 Timing configuration RWT DDR SDRAM timing
configuration 0 (TIMING_C
WRT
FG_0)
RRT
WWT
ACT_PD_EXIT
PRE_PD_EXIT
MRS_CYC
TIMING_CFG_1 Timing configuration PRETOACT DDR SDRAM timing
configuration 1 (TIMING_C
ACTTOPRE
FG_1)
ACTTORW
CASLAT
REFREC
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 857
Initialization/Application Information
Table 18-20. Memory Interface Configuration Register Initialization Parameters (continued)
Name Description Parameter Section/Page
WRREC
ACTTOACT
WRTORD
TIMING_CFG_2 Timing configuration ADD_LAT DDR SDRAM timing
configuration 2 (TIMING_C
WR_LAT
FG_2)
RD_TO_PRE
CKE_PLS
FOUR_ACT
DDR_SDRAM_CFG Control configuration SREN DDR SDRAM control
configuration (DDR_SDRAM_
ECC_EN
CFG)
SDRAM_TYPE
DYN_PWR
BE_8
DBW
T2_EN
T3_EN
BA_INTLV_CTL
HSE
BI
DDR_SDRAM_CFG_2 Control configuration ODT_CFG DDR SDRAM control
configuration 2 (DDR_SDRA
NUM_PR
M_CFG_2)
OBC_CFG
AP_EN
D_INIT
RCW_EN
MD_EN
DDR_SDRAM_MODE Mode configuration ESDMODE DDR SDRAM mode
configuration (DDR_SDRAM_
SDMODE
MODE)
DDR_SDRAM_MODE_2 Mode configuration ESDMODE2 DDR SDRAM mode
configuration 2 (DDR_SDRA
ESDMODE3
M_MODE_2)
DDR_SDRAM_INTERVAL Interval configuration REFINT DDR SDRAM interval
configuration (DDR_SDRAM_
BSTOPRE
INTERVAL)
DDR_DATA_INIT Data initialization INIT_VALUE DDR SDRAM data
configuration register initialization (DDR_DATA_INI
T)
DDR_SDRAM_CLK_CNTL Clock adjust CLK_ADJUST DDR SDRAM clock control
(DDR_SDRAM_CLK_CNTL)
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
858 NXP Semiconductors
Chapter 18 DDR Memory Controller
Table 18-20. Memory Interface Configuration Register Initialization Parameters (continued)
Name Description Parameter Section/Page
DDR_INIT_ADDR Initialization address INIT_ADDR DDR training initialization
address (DDR_INIT_ADDR)
DDR_INIT_EXT_ADDRESS Extended initialization INIT_EXT_ADDR DDR training initialization
address extended address (DDR_INIT
_EXT_ADDRESS)
TIMING_CFG_4 Timing configuration RWT DDR SDRAM timing
configuration 4 (TIMING_C
WRT
FG_4)
RRT
WWT
EXT_RWT
EXT_WRT
EXT_RRT
EXT_WWT
EXT_REFINT
DLL_LOCK
TIMING_CFG_5 Timing configuration RODT_ON DDR SDRAM timing
configuration 5 (TIMING_C
RODT_OFF
FG_5)
WODT_ON
WODT_OFF
TIMING_CFG_6 Timing configuration HS_CASLAT DDR SDRAM timing
configuration 6 (TIMING_C
HS_WRLAT
FG_6)
HS_WRREC
TIMING_CFG_7 Timing configuration CKE_RST DDR SDRAM timing
configuration 7 (TIMING_C
CKSRE
FG_7)
CKSRX
PAR_LAT
CS_TO_CMD
TIMING_CFG_8 Timing configuration RWT_BG DDR SDRAM timing
configuration 8 (TIMING_C
WRT_BG
FG_8)
RRT_BG
WWT_BG
ACTTOACT_BG
WRTORD_BG
PRE_ALL_REC
DDR_ZQ_CNTL ZQ calibration control ZQ_EN DDR ZQ calibration control
(DDR_ZQ_CNTL)
ZQINIT
ZQOPER
ZQCS
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 859
Initialization/Application Information
Table 18-20. Memory Interface Configuration Register Initialization Parameters (continued)
Name Description Parameter Section/Page
DDR_WRLVL_CNTL Write leveling control WRLVL_EN DDR write leveling control
(DDR_WRLVL_CNTL)
WRLVL_MRD
WRLVL_ODTEN
WRLVL_DQSEN
WRLVL_SMPL
WRLVL_WLR
WRLVL_START
DDR_WRLVL_CNTL_2 Write leveling control WRLVL_START_1 DDR write leveling control 2
(DDR_WRLVL_CNTL_2)
WRLVL_START_2
WRLVL_START_3
WRLVL_START_4
DDR_WRLVL_CNTL_3 Write leveling control WRLVL_START_5 DDR write leveling control 3
(DDR_WRLVL_CNTL_3)
WRLVL_START_6
WRLVL_START_7
WRLVL_START_8
DDR_SR_CNTR Self refresh control SR_IT DDR Self Refresh Counter
(DDR_SR_CNTR)
DDR_SDRAM_RCW_1 Register control words RCW0 DDR Register Control Words
configuration 1 (DDR_SDRAM_RCW_1)
RCW1
RCW2
RCW3
RCW4
RCW5
RCW6
RCW7
DDR_SDRAM_RCW_2 Register control words RCW8 DDR Register Control Words
configuration 2 (DDR_SDRAM_RCW_2)
RCW9
RCW10
RCW11
RCW12
RCW13
RCW14
RCW15
DDR_SDRAM_CFG_3 Control configuration DDRC_RST DDR SDRAM control
configuration 3 (DDR_SDRA
ECC_FIX_EN
M_CFG_3)
ECC_SCRUB_INT
DM_CFG
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
860 NXP Semiconductors
Chapter 18 DDR Memory Controller
Table 18-20. Memory Interface Configuration Register Initialization Parameters (continued)
Name Description Parameter Section/Page
DDRCDR_1 Driver control DHC_EN DDR Control Driver Register 1
(DDRCDR_1)
ODT
DSO_C_EN
DSO_D_EN
DSO_CZ
DSO_DZ
DDRCDR_2 Driver control DSO_CLK_EN DDR Control Driver Register 2
(DDRCDR_2)
DSO_CLKZ
18.6.1 Programming Summary
Depending on the memory type used, certain fields must be programmed differently.
This table illustrates the differences in certain fields for DDR3 memory types. Note: This
table does not list all fields that must be programmed.
Table 18-21. Programming Summary, DDR3 memory types
Parameter Description Summary Section
APn _EN Chip Select nAuto Can be used to place chip select nin auto precharge mode Chip select a
Precharge Enable configuration
(CS0_CONFIG
- CS3_CONF
IG)
ODT_RD_CFG Chip Select ODT Read Can be enabled to assert ODT if desired. This could be set Chip select a
Configuration differently depending on system topology. However, configuration
systems with only 1 chip select will typically not use ODT (CS0_CONFIG
when issuing reads to the memory. - CS3_CONF
IG)
ODT_WR_CFG Chip Select ODT Write Can be enabled to assert ODT if desired. This could be set Chip select a
Configuration differently depending on system topology. However, ODT configuration
will typically be set to assert for the chip select that is (CS0_CONFIG
getting written to (value would be set to 001). - CS3_CONF
IG)
PRETOACT Precharge to Activate Should be set according to the specifications for the DDR SDRAM
Timing memory used (tRP) timing
configuration 1
(TIMING_C
FG_1)
ACTTOPRE Activate to Precharge Should be set, along with the Extended Activate to DDR SDRAM
Timing Precharge Timing, according to the specifications for the timing
memory used (tRAS) configuration 1
(TIMING_C
FG_1)
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 861
Initialization/Application Information
Table 18-21. Programming Summary, DDR3 memory types (continued)
Parameter Description Summary Section
ACTTORW Activate to Read/Write Should be set according to the specifications for the DDR SDRAM
Timing memory used (tRCD) timing
configuration 1
(TIMING_C
FG_1)
CASLAT CAS Latency Should be set, along with the Extended CAS Latency, to DDR SDRAM
the desired CAS latency timing
configuration 1
(TIMING_C
FG_1)
REFREC Refresh Recovery Should be set, along with the Extended Refresh Recovery, DDR SDRAM
to the specifications for the memory used (TRFC) timing
configuration 1
(TIMING_C
FG_1)
WRREC Write Recovery Should be set according to the specifications for the DDR SDRAM
memory used (tWR). timing
configuration 1
If DDR_SDRAM_CFG_2[OBC_CFG] is set, then this
(TIMING_C
should be programmed to tWR + 2 DRAM cycles.
FG_1)
ACTTOACT Activate A to Activate B Should be set according to the specifications for the DDR SDRAM
memory used (tRRD) timing
configuration 1
(TIMING_C
FG_1)
WRTORD Write to Read Timing Should be set according to the specifications for the DDR SDRAM
memory used (tWTR) timing
configuration 1
If DDR_SDRAM_CFG_2[OBC_CFG] is set, then this
(TIMING_C
should be programmed to tWTR + 2 DRAM cycles.
FG_1)
ADD_LAT Additive Latency Should be set to the desired additive latency. This must be DDR SDRAM
set to a value less than TIMING_CFG_1[ACTTORW] timing
configuration 2
(TIMING_C
FG_2)
WR_LAT Write Latency Should be set to the desired write latency. The minimum DDR SDRAM
WR_LAT that can be used in 1T timing mode is 5 cycles if timing
DDR_RATE=0 configuration 2
(TIMING_C
FG_2)
RD_TO_PRE Read to Precharge Timing Should be set according to the specifications for the DDR SDRAM
memory used (tRTP). Time between read and precharge for timing
non-zero value of additive latency (AL) is a minimum of AL configuration 2
+ tRTP cycles. If DDR_SDRAM_CFG_2[OBC_CFG] is set, (TIMING_C
then this should be programmed to tRTP + 2 DRAM cycles. FG_2)
CKE_PLS Minimum CKE Pulse Width Should be set according to the specifications for the DDR SDRAM
memory used (tCKE) timing
configuration 2
(TIMING_C
FG_2)
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
862 NXP Semiconductors
Chapter 18 DDR Memory Controller
Table 18-21. Programming Summary, DDR3 memory types (continued)
Parameter Description Summary Section
FOUR_ACT Four Activate Window Should be set according to the specifications for the DDR SDRAM
memory used (tFAW). timing
configuration 2
(TIMING_C
FG_2)
BE_8 8-beat burst enable Set to 1 for fixed 8-beat burst mode. Set to 0 for on-the-fly DDR SDRAM
burst chop mode and ensure control
DDR_SDRAM_CFG_2[OBC_CFG] = 1. If this bit is set to 0, configuration
then other requirements in TIMING_CFG_4 will be needed (DDR_SDRA
to ensure tCCD is met. M_CFG)
T2_EN 2T Timing Enable In heavily loaded systems, this can be set to 1 to gain extra DDR SDRAM
timing margin on the interface at the cost of address/ control
command bandwidth. configuration
(DDR_SDRA
M_CFG)
ODT_CFG ODT Configuration Can be set for termination at the IOs according to system DDR SDRAM
topology. Typically, if ODT is enabled, then the internal IOs control
should be set up for termination only during reads to configuration 2
DRAM. (DDR_SDRA
M_CFG_2)
OBC_CFG On-The-Fly Burst Chop Can be set to 1 if on-the-fly burst chop will be used. This DDR SDRAM
Configuration feature can only be used if a 64-bit data bus is used. control
configuration 2
(DDR_SDRA
M_CFG_2)
RWT Read-to-write turnaround This can be used to force a longer read-to-write turnaround DDR SDRAM
for same chip select (in time when accessing the same chip select. This is useful timing
TIMING_CFG_4) for burst chop mode, as there are some timing configuration 4
requirements to the same chip select that still must be met. (TIMING_C
FG_4)
WRT Write-to-read turnaround This could be used to force a certain turnaround time DDR SDRAM
for same chip select (in between a write and read to the same chip select. This is timing
TIMING_CFG_4) useful for burst chop mode. However, it is expected that configuration 4
TIMING_CFG_1[WRTORD] will be programmed (TIMING_C
appropriately such that TIMING_CFG_4[WRT] can be set FG_4)
to 0000.
RRT Read-to-read turnaround Should typically be set to 0010 in burst chop mode (on-the- DDR SDRAM
for same chip select (in fly or fixed). timing
TIMING_CFG_4) configuration 4
(TIMING_C
FG_4)
WWT Write-to-write turnaround Should typically be set to 0010 in burst chop mode (on-the- DDR SDRAM
for same chip select (in fly or fixed). timing
TIMING_CFG_4) configuration 4
(TIMING_C
FG_4)
ZQ_EN ZQ Calibration Enable Should be set to 1. The other fields in DDR_ZQ_CNTL DDR SDRAM
should also be programmed appropriately based on the timing
DRAM specifications. configuration 7
(TIMING_C
FG_7)
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 863
Initialization/Application Information
Table 18-21. Programming Summary, DDR3 memory types (continued)
Parameter Description Summary Section
WRLVL_EN Write Leveling Enable Can be set to 1 if write leveling is desired. Otherwise the DDR write
value used in TIMING_CFG_2[WR_DATA_DELAY] will be leveling control
used to shift all bytes during writes to DRAM. If write (DDR_WRLV
leveling will be used, all other fields in DDR_WRLVL_CNTL L_CNTL)
should be programmed appropriately based on the DRAM
specifications.
BSTOPRE Burst To Precharge Interval Can be set to any value, depending on the application. Auto DDR SDRAM
precharge can be enabled by setting this field to all 0s. interval
configuration
(DDR_SDRA
M_INTERVAL)
This table illustrates the differences in certain fields for DDR4 memory types. Note: This
table does not list all fields that must be programmed.
Table 18-22. Programming Summary, DDR4 memory types
Parameter Description Summary Section
APn _EN Chip Select nAuto Can be used to place chip select nin auto precharge mode Chip select a
Precharge Enable configuration
(CS0_CONFIG
- CS3_CONF
IG)
ODT_RD_CFG Chip Select ODT Read Can be enabled to assert ODT if desired. This could be set Chip select a
Configuration differently depending on system topology. However, configuration
systems with only 1 chip select will typically not use ODT (CS0_CONFIG
when issuing reads to the memory. - CS3_CONF
IG)
ODT_WR_CFG Chip Select ODT Write Can be enabled to assert ODT if desired. This could be set Chip select a
Configuration differently depending on system topology. However, ODT configuration
will typically be set to assert for the chip select that is (CS0_CONFIG
getting written to (value would be set to 001). - CS3_CONF
IG)
PRETOACT Precharge to Activate Should be set according to the specifications for the DDR SDRAM
Timing memory used (tRP) timing
configuration 1
(TIMING_C
FG_1)
ACTTOPRE Activate to Precharge Should be set, along with the Extended Activate to DDR SDRAM
Timing Precharge Timing, according to the specifications for the timing
memory used (tRAS) configuration 1
(TIMING_C
FG_1)
ACTTORW Activate to Read/Write Should be set according to the specifications for the DDR SDRAM
Timing memory used (tRCD) timing
configuration 1
(TIMING_C
FG_1)
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
864 NXP Semiconductors
Chapter 18 DDR Memory Controller
Table 18-22. Programming Summary, DDR4 memory types (continued)
Parameter Description Summary Section
CASLAT CAS Latency Should be set, along with the Extended CAS Latency, to DDR SDRAM
the desired CAS latency timing
configuration 1
(TIMING_C
FG_1)
REFREC Refresh Recovery Should be set, along with the Extended Refresh Recovery, DDR SDRAM
to the specifications for the memory used (TRFC) timing
configuration 1
(TIMING_C
FG_1)
WRREC Write Recovery Should be set according to the specifications for the DDR SDRAM
memory used (tWR). timing
configuration 1
If DDR_SDRAM_CFG_2[OBC_CFG] is set, then this
(TIMING_C
should be programmed to tWR + 2 DRAM cycles.
FG_1)
ACTTOACT Activate A to Activate B Should be set according to the specifications for the DDR SDRAM
memory used (tRRD) timing
configuration 1
(TIMING_C
FG_1)
WRTORD Write to Read Timing Should be set according to the specifications for the DDR SDRAM
memory used (tWTR) timing
configuration 1
If DDR_SDRAM_CFG_2[OBC_CFG] is set, then this
(TIMING_C
should be programmed to tWTR + 2 DRAM cycles.
FG_1)
ADD_LAT Additive Latency Should be set to the desired additive latency. This must be DDR SDRAM
set to a value less than TIMING_CFG_1[ACTTORW] timing
configuration 2
(TIMING_C
FG_2)
WR_LAT Write Latency Should be set to the desired write latency. The minimum DDR SDRAM
WR_LAT that can be used in 1T timing mode is 5 cycles if timing
DDR_RATE=0 configuration 2
(TIMING_C
FG_2)
RD_TO_PRE Read to Precharge Timing Should be set according to the specifications for the DDR SDRAM
memory used (tRTP). Time between read and precharge for timing
non-zero value of additive latency (AL) is a minimum of AL configuration 2
+ tRTP cycles. If DDR_SDRAM_CFG_2[OBC_CFG] is set, (TIMING_C
then this should be programmed to tRTP + 2 DRAM cycles. FG_2)
CKE_PLS Minimum CKE Pulse Width Should be set according to the specifications for the DDR SDRAM
memory used (tCKE) timing
configuration 2
(TIMING_C
FG_2)
FOUR_ACT Four Activate Window Should be set according to the specifications for the DDR SDRAM
memory used (tFAW). timing
configuration 2
(TIMING_C
FG_2)
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 865
Initialization/Application Information
Table 18-22. Programming Summary, DDR4 memory types (continued)
Parameter Description Summary Section
BE_8 8-beat burst enable Set to 1 for fixed 8-beat burst mode. Set to 0 for on-the-fly DDR SDRAM
burst chop mode and ensure control
DDR_SDRAM_CFG_2[OBC_CFG] = 1. If this bit is set to 0, configuration
then other requirements in TIMING_CFG_4 will be needed (DDR_SDRA
to ensure tCCD is met. M_CFG)
T2_EN 2T Timing Enable In heavily loaded systems, this can be set to 1 to gain extra DDR SDRAM
timing margin on the interface at the cost of address/ control
command bandwidth. configuration
(DDR_SDRA
M_CFG)
ODT_CFG ODT Configuration Can be set for termination at the IOs according to system DDR SDRAM
topology. Typically, if ODT is enabled, then the internal IOs control
should be set up for termination only during reads to configuration 2
DRAM. (DDR_SDRA
M_CFG_2)
OBC_CFG On-The-Fly Burst Chop Can be set to 1 if on-the-fly burst chop will be used. This DDR SDRAM
Configuration feature can only be used if a 64-bit data bus is used. control
configuration 2
(DDR_SDRA
M_CFG_2)
RWT Read-to-write turnaround This can be used to force a longer read-to-write turnaround DDR SDRAM
for same chip select (in time when accessing the same chip select. This is useful timing
TIMING_CFG_4) for burst chop mode, as there are some timing configuration 4
requirements to the same chip select that still must be met. (TIMING_C
FG_4)
WRT Write-to-read turnaround This could be used to force a certain turnaround time DDR SDRAM
for same chip select (in between a write and read to the same chip select. This is timing
TIMING_CFG_4) useful for burst chop mode. However, it is expected that configuration 4
TIMING_CFG_1[WRTORD] will be programmed (TIMING_C
appropriately such that TIMING_CFG_4[WRT] can be set FG_4)
to 0000.
RRT Read-to-read turnaround Should typically be set to 0010 in burst chop mode (on-the- DDR SDRAM
for same chip select (in fly or fixed). timing
TIMING_CFG_4) configuration 4
(TIMING_C
FG_4)
WWT Write-to-write turnaround Should typically be set to 0010 in burst chop mode (on-the- DDR SDRAM
for same chip select (in fly or fixed). timing
TIMING_CFG_4) configuration 4
(TIMING_C
FG_4)
ZQ_EN ZQ Calibration Enable Should be set to 1. The other fields in DDR_ZQ_CNTL DDR SDRAM
should also be programmed appropriately based on the timing
DRAM specifications. configuration 7
(TIMING_C
FG_7)
WRLVL_EN Write Leveling Enable Should be set to 1 as write leveling is recommended. All DDR write
other fields in DDR_WRLVL_CNTL, leveling control
DDR_WRLVL_CNTRL_2, and DDR_WRLVL_CNTL_3 (DDR_WRLV
should be programmed appropriately based on the DRAM L_CNTL)
specifications and board layout specifics.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
866 NXP Semiconductors
Chapter 18 DDR Memory Controller
Table 18-22. Programming Summary, DDR4 memory types (continued)
Parameter Description Summary Section
BSTOPRE Burst To Precharge Interval Can be set to any value, depending on the application. Auto DDR SDRAM
precharge can be enabled by setting this field to all 0s. interval
configuration
(DDR_SDRA
M_INTERVAL)
18.6.2 DDR SDRAM Initialization Sequence
After configuration of all parameters is complete, system software must set
DDR_SDRAM_CFG[MEM_EN] to enable the memory interface. Note that 500 μs must
elapse after DRAM clocks are stable (after DDRCDR_1[DHC_EN] is set,
DDR_SDRAM_CLK_CNTL[CLK_ADJUST] is set, and any chip select is enabled)
before MEM_EN can be set. A delay loop in the initialization code may be necessary if
software is enabling the memory controller. If DDR_SDRAM_CFG[BI] is not set, the
DDR memory controller will conduct an automatic initialization sequence to the memory,
which will follow the memory specifications. If the bypass initialization mode is used,
then software can initialize the memory through the DDR_SDRAM_MD_CNTL register.
18.6.3 Using Forced Self-Refresh Mode to Implement a Battery-
Backed RAM System
This section describes the options offered by this device to support battery-backed main
memory.
18.6.3.1 Software Based Self-Refresh Scheme
The DDR controller also has a software-programmable bit,
DDR_SDRAM_CFG_2[FRC_SR], that immediately puts main memory into self-refresh
mode. See DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) for a
description of this register.
It is expected that a critical interrupt routine triggered by an external voltage sensing
device will have time to set this bit.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 867
Initialization/Application Information
18.6.3.2 Bypassing Re-initialization During Battery-Backed Operation
The DDR controller offers an initialization bypass feature (DDR_SDRAM_CFG[BI]),
which system designers may use to prevent re-initialization of main memory during
system power-on following an abnormal shutdown. See DDR SDRAM control
configuration (DDR_SDRAM_CFG) for information on this bit and DDR training
initialization address (DDR_INIT_ADDR) for a discussion of avoiding possible ECC
errors in this mode.
Note that when this mode is used, the controller will wait a user-programmable number
of cycles before issuing any command after the assertion of MCKEn; this number is set
in TIMING_CFG_4[DLL_LOCK].
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
868 NXP Semiconductors
Chapter 19
Direct Memory Access Multiplexer (DMAMUX)
19.1 The DMAMUX module as implemented on the chip
This section provides details about how the DMAMUX module is implemented on the
chip.
19.1.1 LS1043A DMAMUX module integration
The following table describes the DMAMUX module integration into this chip:
Table 19-1. DMAMUX module integration
Module Base address
DMAMUX1 2C1_0000
DMAMUX2 2C2_0000
The remainder of this chapter refers to a single DMAMUX module. Notes are included to
indicate variations for multiple instantiations.
19.1.2 LS1043A DMAMUX module special consideration
19.1.2.1 eDMA and DMAMUX
The device contains one eDMA and two DMAMUX modules.
The eDMA module implements the following parameter settings in the chip:
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 869
The DMAMUX module as implemented on the chip
Table 19-2. LS1043A eDMA parameter settings
eDMA parameters LS1043A parameter value
Stop mode support Refers to LPM20 low power mode of the
chip
Debug mode support No
19.1.2.1.1 eDMA and DMAMUX channel assignment
The table below provides the channel assignments of eDMA and DMAMUX:
Table 19-3. eDMA and DMAMUX channel assignment
eDMA channel assignment Parameter value
15-0 DMAMUX1
31-16 DMAMUX2
63-32 Reserved
19.1.2.1.2 DMAMUX settings
The table below provides the DMAMUX settings used in the chip:
Table 19-4. DMAMUX settings
DMAMUX settings DMAMUX1 DMAMUX2
NUMBER_OF_DMA_CHANNELS 16 16
NUMBER_OF_PERIPHERAL_SLOTS 62 62
19.1.2.1.3 DMAMUX request sources
This device includes a DMA request multiplexer that allows up to 64 DMA request
signals to be mapped to any of the 16 DMA channels.
As shown in the figure below, request from MUX1 can be mapped to any of the first 16
DMA channels and from MUX2, to any of the lower 16 DMA channels.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
870 NXP Semiconductors
Chapter 19 Direct Memory Access Multiplexer (DMAMUX)
Ch0
Ch1
Ch2 16
DMAMUX1
Ch63
DMA
Ch0
Ch1
Ch2
DMAMUX2
16
Ch63
Figure 19-1. DMA Request MUX/DMA Structure
The table below provides the source mapping for DMAMUX1 and DMAMUX2:
Table 19-5. DMA-Channel-MUX peripheral mapping
DMA- DMA-CH-MUX1 DMA-CH-MUX2
Channel-
MUX
peripheral
no.
1 Reserved Reserved
2 Reserved Reserved
3 FlexTimer6[0] Reserved
4 FlexTimer6[1] Reserved
5 FlexTimer6[2] Reserved
6 FlexTimer6[3] Reserved
7 FlexTimer6[4] Reserved
8 FlexTimer6[5] Reserved
9 FlexTimer6[6] Reserved
10 FlexTimer6[7] Reserved
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 871
The DMAMUX module as implemented on the chip
Table 19-5. DMA-Channel-MUX peripheral mapping (continued)
DMA- DMA-CH-MUX1 DMA-CH-MUX2
Channel-
MUX
peripheral
no.
11 FlexTimer5[0] Reserved
12 FlexTimer5[1] Reserved
13 FlexTimer5[2] Reserved
14 FlexTimer5[3] Reserved
15 FlexTimer5[4] Reserved
16 FlexTimer5[5] Reserved
17 FlexTimer5[6] Reserved
18 FlexTimer5[7] FlexTimer7[7]
19 FlexTimer4[0] QSPI rfdf
20 FlexTimer4[1] Reserved
21 FlexTimer4[2] Reserved
22 FlexTimer4[3] LPUART6 Rx
23 FlexTimer4[4] LPUART6 Tx
24 FlexTimer4[5] LPUART5 Rx
25 FlexTimer4[6] LPUART5 Tx
26 FlexTimer4[7] LPUART4 Rx
27 FlexTimer3[0] LPUART4 Tx
28 FlexTimer3[1] LPUART3 Rx
29 FlexTimer3[2] LPUART3 Tx
30 FlexTimer3[3] LPUART2 Rx
31 FlexTimer3[4] LPUART2 Tx
32 FlexTimer3[5] LPUART1 Rx
33 FlexTimer3[6] LPUART1 Tx
34 FlexTimer3[7] IIC3 Rx
35 FlexTimer2[0] IIC3 Tx
36 FlexTimer2[1] IIC2 Rx
37 FlexTimer2[2] IIC2 Tx
38 FlexTimer2[3] IIC1 Rx
39 FlexTimer2[4] IIC1 Tx
40 FlexTimer2[5] IIC4 Rx
41 FlexTimer2[6] IIC4 Tx
42 FlexTimer2[7] Reserved
43 FlexTimer1[0] Reserved
44 FlexTimer1[1] Reserved
45 FlexTimer1[2] Reserved
46 FlexTimer1[3] Reserved
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
872 NXP Semiconductors
Chapter 19 Direct Memory Access Multiplexer (DMAMUX)
Table 19-5. DMA-Channel-MUX peripheral mapping (continued)
DMA- DMA-CH-MUX1 DMA-CH-MUX2
Channel-
MUX
peripheral
no.
47 FlexTimer1[4] Reserved
48 FlexTimer1[5] FlexTimer8[0]
49 FlexTimer1[6] FlexTimer8[1]
50 FlexTimer1[7] FlexTimer8[2]
51 Reserved FlexTimer8[3]
52 Reserved FlexTimer8[4]
53 Reserved FlexTimer8[5]
54 Reserved FlexTimer8[6]
55 SPI2 FlexTimer8[7]
56 SPI2 RFDF FlexTimer7[0]
57 SPI2 CMD FlexTimer7[1]
58 SPI2 TF FlexTimer7[2]
59 SPI1 FlexTimer7[3]
60 SPI1 RFDF FlexTimer7[4]
61 SPI1 CMD FlexTimer7[5]
62 SPI1 TF FlexTimer7[6]
63 ALWAYS_ENABLED_SOURCE ALWAYS_ENABLED_SOURCE
19.2 Introduction
19.2.1 Overview
The Direct Memory Access Multiplexer (DMAMUX) routes DMA sources, called slots,
to any of the 16 DMA channels. This process is illustrated in the following figure.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 873
Introduction
DMA channel #0
Source #1 DMAMUX
DMA channel #1
Source #2
Source #3
Source #x
Always #1
Always #y
DMA channel #n
Figure 19-2. DMAMUX block diagram
19.2.2 Features
The DMAMUX module provides these features:
• Up to 62 peripheral slots and up to one always-on slots can be routed to 16 channels.
• 16 independently selectable DMA channel routers.
• Each channel router can be assigned to one of the possible peripheral DMA slots or
to one of the always-on slots.
19.2.3 Modes of operation
The following operating modes are available:
• Disabled mode
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
874 NXP Semiconductors
Chapter 19 Direct Memory Access Multiplexer (DMAMUX)
In this mode, the DMA channel is disabled. Because disabling and enabling of DMA
channels is done primarily via the DMA configuration registers, this mode is used
mainly as the reset state for a DMA channel in the DMA channel MUX. It may also
be used to temporarily suspend a DMA channel while reconfiguration of the system
takes place.
• Normal mode
In this mode, a DMA source is routed directly to the specified DMA channel. The
operation of the DMAMUX in this mode is completely transparent to the system.
19.3 External signal description
The DMAMUX has no external pins.
19.4 Memory map/register definition
This section provides a detailed description of all memory-mapped registers in the
DMAMUX.
DMAMUX memory map
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
2C1_0000 Channel Configuration register (DMAMUX1_CHCFG0) 8 R/W 00h 19.4.1/876
2C1_0001 Channel Configuration register (DMAMUX1_CHCFG1) 8 R/W 00h 19.4.1/876
2C1_0002 Channel Configuration register (DMAMUX1_CHCFG2) 8 R/W 00h 19.4.1/876
2C1_0003 Channel Configuration register (DMAMUX1_CHCFG3) 8 R/W 00h 19.4.1/876
2C1_0004 Channel Configuration register (DMAMUX1_CHCFG4) 8 R/W 00h 19.4.1/876
2C1_0005 Channel Configuration register (DMAMUX1_CHCFG5) 8 R/W 00h 19.4.1/876
2C1_0006 Channel Configuration register (DMAMUX1_CHCFG6) 8 R/W 00h 19.4.1/876
2C1_0007 Channel Configuration register (DMAMUX1_CHCFG7) 8 R/W 00h 19.4.1/876
2C1_0008 Channel Configuration register (DMAMUX1_CHCFG8) 8 R/W 00h 19.4.1/876
2C1_0009 Channel Configuration register (DMAMUX1_CHCFG9) 8 R/W 00h 19.4.1/876
2C1_000A Channel Configuration register (DMAMUX1_CHCFG10) 8 R/W 00h 19.4.1/876
2C1_000B Channel Configuration register (DMAMUX1_CHCFG11) 8 R/W 00h 19.4.1/876
2C1_000C Channel Configuration register (DMAMUX1_CHCFG12) 8 R/W 00h 19.4.1/876
2C1_000D Channel Configuration register (DMAMUX1_CHCFG13) 8 R/W 00h 19.4.1/876
2C1_000E Channel Configuration register (DMAMUX1_CHCFG14) 8 R/W 00h 19.4.1/876
2C1_000F Channel Configuration register (DMAMUX1_CHCFG15) 8 R/W 00h 19.4.1/876
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 875
Memory map/register definition
DMAMUX memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
2C2_0000 Channel Configuration register (DMAMUX2_CHCFG0) 8 R/W 00h 19.4.1/876
2C2_0001 Channel Configuration register (DMAMUX2_CHCFG1) 8 R/W 00h 19.4.1/876
2C2_0002 Channel Configuration register (DMAMUX2_CHCFG2) 8 R/W 00h 19.4.1/876
2C2_0003 Channel Configuration register (DMAMUX2_CHCFG3) 8 R/W 00h 19.4.1/876
2C2_0004 Channel Configuration register (DMAMUX2_CHCFG4) 8 R/W 00h 19.4.1/876
2C2_0005 Channel Configuration register (DMAMUX2_CHCFG5) 8 R/W 00h 19.4.1/876
2C2_0006 Channel Configuration register (DMAMUX2_CHCFG6) 8 R/W 00h 19.4.1/876
2C2_0007 Channel Configuration register (DMAMUX2_CHCFG7) 8 R/W 00h 19.4.1/876
2C2_0008 Channel Configuration register (DMAMUX2_CHCFG8) 8 R/W 00h 19.4.1/876
2C2_0009 Channel Configuration register (DMAMUX2_CHCFG9) 8 R/W 00h 19.4.1/876
2C2_000A Channel Configuration register (DMAMUX2_CHCFG10) 8 R/W 00h 19.4.1/876
2C2_000B Channel Configuration register (DMAMUX2_CHCFG11) 8 R/W 00h 19.4.1/876
2C2_000C Channel Configuration register (DMAMUX2_CHCFG12) 8 R/W 00h 19.4.1/876
2C2_000D Channel Configuration register (DMAMUX2_CHCFG13) 8 R/W 00h 19.4.1/876
2C2_000E Channel Configuration register (DMAMUX2_CHCFG14) 8 R/W 00h 19.4.1/876
2C2_000F Channel Configuration register (DMAMUX2_CHCFG15) 8 R/W 00h 19.4.1/876
19.4.1 Channel Configuration register (DMAMUXx_CHCFGn)
Each of the DMA channels can be independently enabled/disabled and associated with
one of the DMA slots (peripheral slots or always-on slots) in the system.
NOTE
Setting multiple CHCFG registers with the same source value
will result in unpredictable behavior. This is true, even if a
channel is disabled (ENBL==0).
Before changing the source settings, a DMA channel must be
disabled via CHCFGn[ENBL].
Address: Base address + 0h offset + (1d × i), where i=0d to 15d
Bit 0 1 2 3 4 5 6 7
Read ENBL Reserved SOURCE
Write
Reset 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
876 NXP Semiconductors
Chapter 19 Direct Memory Access Multiplexer (DMAMUX)
DMAMUXx_CHCFGn field descriptions
Field Description
0 DMA Channel Enable
ENBL
Enables the DMA channel.
0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA
has separate channel enables/disables, which should be used to disable or reconfigure a DMA
channel.
1 DMA channel is enabled
1 This field is reserved.
Reserved This read/write field does not affect the functionality of the device and should not be used.
2–7 DMA Channel Source (Slot)
SOURCE
Specifies which DMA source, if any, is routed to a particular DMA channel. See the chip-specific
DMAMUX information for details about the peripherals and their slot numbers.
19.5 Functional description
The primary purpose of the DMAMUX is to provide flexibility in the system's use of the
available DMA channels.
As such, configuration of the DMAMUX is intended to be a static procedure done during
execution of the system boot code. However, if the procedure outlined in Enabling and
configuring sources is followed, the configuration of the DMAMUX may be changed
during the normal operation of the system.
The DMAMUX channels implement only the normal routing functionality.
19.5.1 Always-enabled DMA sources
In addition to the peripherals that can be used as DMA sources, there are one additional
DMA sources that are always enabled. Unlike the peripheral DMA sources, where the
peripheral controls the flow of data during DMA transfers, the sources that are always
enabled provide no such "throttling" of the data transfers. These sources are most useful
in the following cases:
• Performing DMA transfers to/from GPIO—Moving data from/to one or more GPIO
pins.
• Performing DMA transfers from memory to memory—Moving data from memory to
memory, typically as fast as possible, sometimes with software activation.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 877
Initialization/application information
• Performing DMA transfers from memory to the external bus, or vice-versa—Similar
to memory to memory transfers, this is typically done as quickly as possible.
• Any DMA transfer that requires software activation—Any DMA transfer that should
be explicitly started by software.
In cases where software should initiate the start of a DMA transfer, an always-enabled
DMA source can be used to provide maximum flexibility. When activating a DMA
channel via software, subsequent executions of the minor loop require that a new start
event be sent. This can either be a new software activation, or a transfer request from the
DMA channel MUX. The options for doing this are:
• Transfer all data in a single minor loop.
By configuring the DMA to transfer all of the data in a single minor loop (that is,
major loop counter = 1), no reactivation of the channel is necessary. The
disadvantage to this option is the reduced granularity in determining the load that the
DMA transfer will impose on the system. For this option, the DMA channel must be
disabled in the DMA channel MUX.
• Use explicit software reactivation.
In this option, the DMA is configured to transfer the data using both minor and major
loops, but the processor is required to reactivate the channel by writing to the DMA
registers after every minor loop. For this option, the DMA channel must be disabled
in the DMA channel MUX.
• Use an always-enabled DMA source.
In this option, the DMA is configured to transfer the data using both minor and major
loops, and the DMA channel MUX does the channel reactivation. For this option, the
DMA channel should be enabled and pointing to an "always enabled" source.
19.6 Initialization/application information
This section provides instructions for initializing the DMA channel MUX.
19.6.1 Reset
The reset state of each individual bit is shown in Memory map/register definition. In
summary, after reset, all channels are disabled and must be explicitly enabled before use.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
878 NXP Semiconductors
Chapter 19 Direct Memory Access Multiplexer (DMAMUX)
19.6.2 Enabling and configuring sources
To enable a source, the following steps can be used:
1. Determine with which DMA channel the source will be associated.
2. Clear the CHCFG[ENBL] field of the DMA channel.
3. Ensure that the DMA channel is properly configured in the DMA. The DMA channel
may be enabled at this point.
4. Select the source to be routed to the DMA channel. Write to the corresponding
CHCFG register, ensuring that CHCFG[ENBL] is set.
To configure source #5 transmit for use with DMA channel 1, as an example, the
following steps can be used:
1. Write 0x00 to CHCFG1.
2. Configure channel 1 in the DMA, including enabling the channel.
3. Write 0x85 to CHCFG1.
The following code example illustrates steps 1 and 3 above:
In File registers.h:
#define DMAMUX_BASE_ADDR 0x40021000/* Example only ! */
/* Following example assumes char is 8-bits */
volatile unsigned char *CHCFG0 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0000);
volatile unsigned char *CHCFG1 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0001);
volatile unsigned char *CHCFG2 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0002);
volatile unsigned char *CHCFG3 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0003);
volatile unsigned char *CHCFG4 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0004);
volatile unsigned char *CHCFG5 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0005);
volatile unsigned char *CHCFG6 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0006);
volatile unsigned char *CHCFG7 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0007);
volatile unsigned char *CHCFG8 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0008);
volatile unsigned char *CHCFG9 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0009);
volatile unsigned char *CHCFG10= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000A);
volatile unsigned char *CHCFG11= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000B);
volatile unsigned char *CHCFG12= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000C);
volatile unsigned char *CHCFG13= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000D);
volatile unsigned char *CHCFG14= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000E);
volatile unsigned char *CHCFG15= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000F);
In File main.c:
#include "registers.h"
:
:
*CHCFG1 = 0x00;
*CHCFG1 = 0x85;
To disable a source:
A particular DMA source may be disabled by not writing the corresponding source value
into any of the CHCFG registers. Additionally, some module-specific configuration may
be necessary. See the appropriate section for more details.
To switch the source of a DMA channel:
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 879
Initialization/application information
1. Disable the DMA channel in the DMA and reconfigure the channel for the new
source.
2. Clear the CHCFG[ENBL] bit of the DMA channel.
3. Select the source to be routed to the DMA channel. Write to the corresponding
CHCFG register, ensuring that the CHCFG[ENBL] field is set.
To switch DMA channel 8 from source #5 transmit to source #7 transmit:
1. In the DMA configuration registers, disable DMA channel 8 and reconfigure it to
handle the transfers to peripheral slot 7. This example assumes channel 8 doesn't
have triggering capability.
2. Write 0x00 to CHCFG8.
3. Write 0x87 to CHCFG8.
The following code example illustrates steps 2 and 3 above:
In File registers.h:
#define DMAMUX_BASE_ADDR 0x40021000/* Example only ! */
/* Following example assumes char is 8-bits */
volatile unsigned char *CHCFG0 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0000);
volatile unsigned char *CHCFG1 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0001);
volatile unsigned char *CHCFG2 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0002);
volatile unsigned char *CHCFG3 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0003);
volatile unsigned char *CHCFG4 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0004);
volatile unsigned char *CHCFG5 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0005);
volatile unsigned char *CHCFG6 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0006);
volatile unsigned char *CHCFG7 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0007);
volatile unsigned char *CHCFG8 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0008);
volatile unsigned char *CHCFG9 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0009);
volatile unsigned char *CHCFG10= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000A);
volatile unsigned char *CHCFG11= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000B);
volatile unsigned char *CHCFG12= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000C);
volatile unsigned char *CHCFG13= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000D);
volatile unsigned char *CHCFG14= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000E);
volatile unsigned char *CHCFG15= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000F);
In File main.c:
#include "registers.h"
:
:
*CHCFG8 = 0x00;
*CHCFG8 = 0x87;
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
880 NXP Semiconductors
Chapter 20
DUART
20.1 The DUART module as implemented on the chip
This section provides details about how the DUART module is integrated into this chip.
The chip implements two DUART modules. DUART1 contains UART1 and UART2 and
DUART2 contains UART3 and UART4.
Table 20-1. DUART module as implemented on chip
Module name Module base address
DUART1 0x21C_0000
DUART2 0x21D_0000
20.2 Overview
This chapter describes the dual universal asynchronous receiver/transmitters (DUART). It
describes the functional operation, the initialization sequence, and the programming
details for the dual UART registers and features.
The dual UART consists of two universal asynchronous receiver/transmitters
(UARTs).The UARTs act independently; all references to UART refer to one of these
receiver/transmitters. Each UART is clocked by the platform clock. The dual UART
programming model is compatible with the PC16552D.
The UART interface is point to point, meaning that only two UART devices are attached
to the connecting signals. As shown in the figure below, each UART module consists of
the following:
• Receive and transmit buffers
• Clear to send (CTS_B) input port and request to send (RTS_B) output port for data
flow control
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 881
Overview
• 16-bit counter for baud rate generation
• Interrupt control logic
Data
SIN
Receive Buffer
Address Bus
UART Module Internal Bus
Control SOUT
Logic Transmit Buffer
Control
CTS_B
int
int Interrupt Input Port
Control
RTS_B
Output Port
HRESET_B
platform clock 16-Bit Counter/
Baud Rate Generator
Figure 20-1. UART block diagram
20.2.1 Features
The DUART includes these distinctive features:
• Full-duplex operation
• Programming model compatible with original PC16450 UART and PC16550D
(improved version of PC16450 that also operates in FIFO mode)
• PC16450 register reset values
• Configurable FIFO mode for both transmitter and receiver, providing 64-byte FIFOs
• Serial data encapsulation and decapsulation with standard asynchronous
communication bits (START, STOP, and parity)
• Maskable transmit, receive, line status, and modem status interrupts
• Software-programmable baud generators that divide the platform clock by 1 to (216 -
1) and generate a 16x clock for the transmitter and receiver engines
• Clear to send (CTS_B and ready to send (RTS_B) modem control functions
• Auto flow for clear to send (CTS_B) and ready to send (RTS_B) modem control
functions
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
882 NXP Semiconductors
Chapter 20 DUART
• Software-selectable serial interface data format (data length, parity, 1/1.5/2 STOP bit,
baud rate)
• Line and modem status registers
• Line-break detection and generation
• Internal diagnostic support, local loopback, and break functions
• Prioritized interrupt reporting
• Overrun, parity, and framing error detection
20.2.2 Modes of operation
The communication channel provides a full-duplex asynchronous receiver and transmitter
using an operating frequency derived from the platform clock.
The transmitter accepts parallel data from a write to the transmitter holding register
(UTHR). In FIFO mode, the data is placed directly into an internal transmitter shift
register of the transmitter FIFO. The transmitter converts the data to a serial bit stream
inserting the appropriate start, stop, and optional parity bits. Finally, it outputs a
composite serial data stream on the channel transmitter serial data output signal (SOUT).
The transmitter status may be polled or interrupt driven.
The receiver accepts serial data bits on the channel receiver serial data input signal (SIN),
converts it to parallel format, checks for a start bit, parity (if any), stop bits, and transfers
the assembled character (with start, stop, parity bits removed) from the receiver buffer (or
FIFO) in response to a read of the UART's receiver buffer register (URBR). The receiver
status may be polled or interrupt driven.
20.3 DUART external signal descriptions
The DUART signals are described in the table below.
NOTE
Although the actual device signal names are prepended with the
UART_ prefix as shown in the table, the abbreviated signal
names are often used throughout this chapter.
Table 20-2. DUART signals-detailed signal descriptions
Signal I/O Description
UARTn_SIN I Serial data in. Data is received on the receivers of UARTn through the respective serial data input
signal, with the least-significant bit received first. Note that UART3_SIN is not available when
UART1 is configured for CTS_B mode and UART4_SIN is not available when UART2 is configured
for CTS_B mode.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 883
DUART register descriptions
Table 20-2. DUART signals-detailed signal descriptions (continued)
Signal I/O Description
State Asserted/Negated-Represents the data being received on the UART interface.
meaning
Timing Assertion/Negation-An internal logic sample signal, rxcnt, uses the frequency of the
baud-rate generator to sample the data on SIN.
UARTn_SOUT O Serial data out. The serial data output signals for the UARTn are set ('mark' condition) when the
transmitter is disabled, operating in the local loopback mode, or idle. Data is shifted out on these
signals, with the least significant bit transmitted first. Note that UART3_SOUT is not available when
UART1 is configured for RTS_B mode and UART4_SOUT is not available when UART2 is
configured for RTS_B mode.
State Asserted/Negated-Represents the data being transmitted on the respective UART
meaning interface.
Timing Assertion/Negation- An internal logic sample signal, rxcnt, uses the frequency of the
baud-rate generator to update and drive the data on SOUT.
UARTn_CTS_B I Clear to send. These active-low inputs are the clear-to-send inputs. They are connected to the
respective RTS_B outputs of the other UART devices on the bus. They can be programmed to
generate an interrupt on change-of-state of the signal. Note that UART1_CTS_B is not available
when UART3 is configured for SIN mode and UART2_CTS_B is not available when UART4 is
configured for SIN mode.
State Asserted/Negated-Represent the clear to send condition for their respective UART.
meaning
Timing Assertion/Negation-Sampled at the rising edge of every platform clock.
UARTn_RTS_B O Request to send. UARTn_RTS_B are active-low output signals that can be programmed to be
negated and asserted by either the receiver or transmitter. When connected to the clear-to-send
(CTS_B) input of a transmitter, this signal can be used to control serial data flow. Note that
UART1_RTS_B is not available when UART3 is configured for SOUT mode and UART2_RTS_B is
not available when UART4 is configured for SOUT mode.
State Asserted/Negated-Represents the data being transmitted on the respective UART
meaning interface.
Timing Assertion/Negation-Updated and driven at the rising edge of every platform clock.
20.4 DUART register descriptions
The table below lists the DUART registers and their offsets. It lists the address, name,
and a cross-reference to the complete description of each register.
The UARTs on the device are identical, except that the registers for each UART are
located at different offsets. Throughout this chapter, the registers are described by a
singular acronym: for example, LCR represents the line control register for each UART
(see "The DUART module as implemented on the chip" section for the number of
UARTs supported on chip).
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
884 NXP Semiconductors
Chapter 20 DUART
The registers in each UART interface are used for configuration, control, and status. The
divisor latch access bit, ULCR[DLAB], is used to access the divisor latch least- and
most-significant bit registers and the alternate function register. Refer to UART line
control register (ULCR1 - ULCR2) , for more information on ULCR[DLAB].
All the DUART registers are one-byte wide. Reads and writes to these registers must be
byte-wide operations. The table below provides a register summary with references to the
section and page that contains detailed information about each register. Undefined byte
address spaces within offset 0x000-0xFFF are reserved.
20.4.1 DUART Memory map
DUART1 base address: 21C_0000h
DUART2 base address: 21D_0000h
Offset Register Width Access Reset value
(In bits)
500h UART divisor least significant byte register (UDLB1) 8 RW 00h
500h UART receiver buffer register (URBR1) 8 RO 00h
500h UART transmitter holding register (UTHR1) 8 WO 00h
501h UART divisor most significant byte register (UDMB1) 8 RW 00h
501h UART interrupt enable register (UIER1) 8 RW 00h
502h UART alternate function register (UAFR1) 8 RW 00h
502h UART FIFO control register (UFCR1) 8 WO 00h
502h UART interrupt ID register (UIIR1) 8 RO 01h
503h UART line control register (ULCR1) 8 RW 00h
504h UART modem control register (UMCR1) 8 RW 00h
505h UART line status register (ULSR1) 8 RO 60h
506h UART modem status register (UMSR1) 8 RO 00h
507h UART scratch register (USCR1) 8 RW 00h
510h UART DMA status register (UDSR1) 8 RO 01h
600h UART divisor least significant byte register (UDLB2) 8 RW 00h
600h UART receiver buffer register (URBR2) 8 RO 00h
600h UART transmitter holding register (UTHR2) 8 WO 00h
601h UART divisor most significant byte register (UDMB2) 8 RW 00h
601h UART interrupt enable register (UIER2) 8 RW 00h
602h UART alternate function register (UAFR2) 8 RW 00h
602h UART FIFO control register (UFCR2) 8 WO 00h
602h UART interrupt ID register (UIIR2) 8 RO 01h
603h UART line control register (ULCR2) 8 RW 00h
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 885
DUART register descriptions
Offset Register Width Access Reset value
(In bits)
604h UART modem control register (UMCR2) 8 RW 00h
605h UART line status register (ULSR2) 8 RO 60h
606h UART modem status register (UMSR2) 8 RO 00h
607h UART scratch register (USCR2) 8 RW 00h
610h UART DMA status register (UDSR2) 8 RO 01h
20.4.2 UART divisor least significant byte register (UDLB1 -
UDLB2)
20.4.2.1 Offset
For a = 1 to 2:
Register Offset
UDLBa 400h + (a × 100h)
20.4.2.2 Function
This register is accessible when ULCR[DLAB] = 1.
The divisor least significant byte register (UDLB) is concatenated with the divisor most
significant byte register (UDMB) to create the divisor used to divide the input clock into
the DUART. The output frequency of the baud generator is 16 times the baud rate;
therefore the desired baud rate = platform clock frequency ÷ (16 x [UDMB||UDLB]).
Equivalently, [UDMB||UDLB:0b0000] = platform clock frequency ÷ desired baud rate.
Baud rates that can be generated by specific input clock frequencies are shown in the
table below.
The following table shows examples of baud rate generation based on common input
clock frequencies. Many other target baud rates are also possible.
NOTE
Because only integer values can be used as divisors, the actual
baud rate differs slightly from the desired (target) baud rate; for
this reason, both target and actual baud rates are given, along
with the percentage of error.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
886 NXP Semiconductors
Chapter 20 DUART
Table 20-3. Baud Rate Examples
Target Baud Rate Divisor Platform Clock Actual Baud Rate Percent Error
(Decimal) Frequency (MHz) (Decimal) (Decimal)
Decimal Hex
9,600 1953 07A1 300 9600.61444 0.0064
19,200 977 03D1 300 19,191.40225 0.0448
38,400 488 01E8 300 38,422.13115 0.0576
57,600 326 0146 300 57,515.33742 0.1470
115,200 163 00A3 300 115,030.67485 0.1470
230,400 81 0051 300 231,481.48148 0.4694
9,600 2170 87A 333 9600.61444 0.0064
19,200 1085 43D 333 19,201.22888 0.0064
38,400 543 21F 333 38,367.09638 0.0858
57,600 362 16A 333 57,550.64457 0.0857
115,200 181 B5 333 115,101.28913 0.0857
230,400 90 5A 333 231,481.48148 0.4694
9,600 2604 0A2C 400 9600.61444 0.0064
19,200 1302 0516 400 19,201.22888 0.0064
38,400 651 028B 400 38,402.45776 0.0064
57,600 434 01B2 400 57,603.68664 0.0064
115,200 217 00D9 400 115,207.37327 0.0064
230,400 109 006D 400 229,357.79817 0.4523
20.4.2.3 Diagram
Bits 0 1 2 3 4 5 6 7
R
UDLB
W
Reset 0 0 0 0 0 0 0 0
20.4.2.4 Fields
Field Function
0-7 Divisor least significant byte. This is concatenated with UDMB.
UDLB
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 887
DUART register descriptions
20.4.3 UART receiver buffer register (URBR1 - URBR2)
20.4.3.1 Offset
For a = 1 to 2:
Register Offset
URBRa 400h + (a × 100h)
20.4.3.2 Function
This register is accessible when ULCR[DLAB] = 0.
These registers contain the data received from the transmitter on the UART buses. In
FIFO mode, when read, they return the first byte received. For FIFO status information,
refer to the UDSR[RXRDY] description.
Except for the case when there is an overrun, URBR returns the data in the order it was
received from the transmitter. Refer to the ULSR[OE] description, UART line status
register (ULSR1 - ULSR2) . Note that these registers have same offset as the UTHRs.
20.4.3.3 Diagram
Bits 0 1 2 3 4 5 6 7
R DATA
W
Reset 0 0 0 0 0 0 0 0
20.4.3.4 Fields
Field Function
0-7 Data received from the transmitter on the UART bus (read only)
DATA
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
888 NXP Semiconductors
Chapter 20 DUART
20.4.4 UART transmitter holding register (UTHR1 - UTHR2)
20.4.4.1 Offset
For a = 1 to 2:
Register Offset
UTHRa 400h + (a × 100h)
20.4.4.2 Function
This register is accessible when ULCR[DLAB] = 0.
A write to these 8-bit registers causes the UART devices to transfer 5-8 data bits on the
UART bus in the format set up in the ULCR (line control register). In FIFO mode, data
written to UTHR is placed into the FIFO. The data written to UTHR is the data sent onto
the UART bus, and the first byte written to UTHR is the first byte onto the bus.
UDSR[TXRDY_B] indicates when the FIFO is full. See UART DMA status register
(UDSR1 - UDSR2) for more details.
20.4.4.3 Diagram
Bits 0 1 2 3 4 5 6 7
R
W DATA
Reset 0 0 0 0 0 0 0 0
20.4.4.4 Fields
Field Function
0-7 Data that is written to UTHR (write only)
DATA
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 889
DUART register descriptions
20.4.5 UART divisor most significant byte register (UDMB1 -
UDMB2)
20.4.5.1 Offset
For a = 1 to 2:
Register Offset
UDMBa 401h + (a × 100h)
20.4.5.2 Function
This register is accessible when ULCR[DLAB] = 1.
The divisor least significant byte register (UDLB) is concatenated with the divisor most
significant byte register (UDMB) to create the divisor used to divide the input clock into
the DUART. The output frequency of the baud generator is 16 times the baud rate;
therefore the desired baud rate = platform clock frequency ÷ (16 x [UDMB||UDLB]).
Equivalently, [UDMB||UDLB:0b0000] = platform clock frequency ÷ desired baud rate.
Baud rates that can be generated by specific input clock frequencies are shown in UART
divisor least significant byte register (UDLB1 - UDLB2).
20.4.5.3 Diagram
Bits 0 1 2 3 4 5 6 7
R
UDMB
W
Reset 0 0 0 0 0 0 0 0
20.4.5.4 Fields
Field Function
0-7 Divisor most significant byte
UDMB
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
890 NXP Semiconductors
Chapter 20 DUART
20.4.6 UART interrupt enable register (UIER1 - UIER2)
20.4.6.1 Offset
For a = 1 to 2:
Register Offset
UIERa 401h + (a × 100h)
20.4.6.2 Function
This register is accessible when ULCR[DLAB] = 0.
The UIER gives the user the ability to mask specific UART interrupts to the
programmable interrupt controller (PIC).
20.4.6.3 Diagram
Bits 0 1 2 3 4 5 6 7
R
Reserved
ETHRE
ERDAI
ERLS
EMS
W
I
Reset 0 0 0 0 0 0 0 0
20.4.6.4 Fields
Field Function
0-3 Reserved.
—
4 Enable modem status interrupt.
EMSI 0b - Mask interrupts caused by UMSR[DCTS] being set
1b - Enable and assert interrupts when the clear-to-send bit in the UART modem status register
(UMSR) changes state
5 Enable receiver line status interrupt.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 891
DUART register descriptions
Field Function
ERLSI 0b - Mask interrupts when ULSR's overrun, parity error, framing error or break interrupt bits are set
1b - Enable and assert interrupts when ULSR's overrun, parity error, framing error or break
interrupt bits are set
6 Enable transmitter holding register empty interrupt.
ETHREI 0b - Mask interrupt when ULSR[THRE] is set
1b - Enable and assert interrupts when ULSR[THRE] is set
7 Enable received data available interrupt.
ERDAI 0b - Mask interrupt when new receive data is available or receive data time out has occurred
1b - Enable and assert interrupts when a new data character is received from the external device
and/or a time-out interrupt occurs in the FIFO mode
20.4.7 UART alternate function register (UAFR1 - UAFR2)
20.4.7.1 Offset
For a = 1 to 2:
Register Offset
UAFRa 402h + (a × 100h)
20.4.7.2 Function
This register is accessible when ULCR[DLAB] = 1.
The UAFRs give software the ability to gate off the baud clock and write to each UARTn
registers simultaneously with the same write operation.
20.4.7.3 Diagram
Bits 0 1 2 3 4 5 6 7
R
Reserved BO CW
W
Reset 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
892 NXP Semiconductors
Chapter 20 DUART
20.4.7.4 Fields
Field Function
0-5 Reserved.
—
6 Baud clock select.
BO 0b - The baud clock is not gated off.
1b - The baud clock is gated off.
7 Concurrent write enable.
CW 0b - Disables writing to each UARTn
1b - Enables concurrent writes to corresponding UART registers. A write to a register in UARTn is
also a write to the corresponding register in UARTn+1 and vice versa for each DUART where n
refers to the number of UART controller. The user needs to ensure that the ULCR[DLAB] of each
UART is in the same state before executing a concurrent write to register addresses 0xm00, 0xm01
and 0xm02, where m is the base address of the corresponding UART.
20.4.8 UART FIFO control register (UFCR1 - UFCR2)
20.4.8.1 Offset
For a = 1 to 2:
Register Offset
UFCRa 402h + (a × 100h)
20.4.8.2 Function
This register is accessible when ULCR[DLAB] = 0.
The UFCR, a write-only register, is used to enable and clear the receiver and transmitter
FIFOs, set a receiver FIFO trigger level to control the received data available interrupt,
and select the type of DMA signaling.
When the UFCR bits are written, the FIFO enable bit must also be set or else the UFCR
bits are not programmed. When changing from FIFO mode to 16450 mode (non-FIFO
mode) and vice versa, data is automatically cleared from the FIFOs.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 893
DUART register descriptions
After all the bytes in the receiver FIFO are cleared, the receiver internal shift register is
not cleared. Similarly, the bytes are cleared in the transmitter FIFO, but the transmitter
internal shift register is not cleared. Both TFR and RFR are self-clearing bits.
20.4.8.3 Diagram
Bits 0 1 2 3 4 5 6 7
Reserved
EN64
DMS
RTL
RF
FE
TF
R
N
Reset 0 0 0 0 0 0 0 0
20.4.8.4 Fields
Field Function
0-1 Receiver trigger level. A received data available interrupt occurs when UIER[ERDAI] is set and the
number of bytes in the receiver FIFO equals the designated interrupt trigger level as follows:
RTL
00b - 1 byte, if EN64 1 byte
01b - 4 bytes, if EN64 16 bytes
10b - 8 bytes, if EN64 32 bytes
11b - 14 bytes, if EN64 56 bytes
2 Enable 64-byte FIFO
EN64 0b - Disables the 64-byte FIFOs
1b - Enables the 64-byte FIFOs
3 Reserved
—
4 DMA mode select. See DMA mode select for more information.
DMS 0b - UDSR[RXRDY] and UDSR[TXRDY] bits are in mode 0.
1b - UDSR[RXRDY] and UDSR[TXRDY] bits are in mode 1 if UFCR[FEN] = 1.
5 Transmitter FIFO reset
TFR 0b - No action
1b - Clears all bytes in the transmitter FIFO and resets the FIFO counter/pointer to 0
6 Receiver FIFO reset
RFR 0b - No action
1b - Clears all bytes in the receiver FIFO and resets the FIFO counter/pointer to 0
7 FIFO enable
FEN 0b - FIFOs are disabled and cleared
1b - Enables the transmitter and receiver FIFOs
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
894 NXP Semiconductors
Chapter 20 DUART
20.4.9 UART interrupt ID register (UIIR1 - UIIR2)
20.4.9.1 Offset
For a = 1 to 2:
Register Offset
UIIRa 402h + (a × 100h)
20.4.9.2 Function
This register is accessible when ULCR[DLAB] = 0.
The UIIRs indicate when an interrupt is pending from the corresponding UART and what
type of interrupt is active. They also indicate if the FIFOs are enabled.
The DUART prioritizes interrupts into four levels and records these in the corresponding
UIIR. The four levels of interrupt conditions in order of priority are:
1. Receiver line status
2. Received data ready/character time-out
3. Transmitter holding register empty
4. Modem status
When the UIIR is read, the associated DUART serial channel freezes all interrupts and
indicates the highest priority pending interrupt. While this read transaction is occurring,
the associated DUART serial channel records new interrupts, but does not change the
contents of UIIR until the read access is complete.
Table 20-4. UIIR IID Bits Summary
IID Bits IID[3-0] Priority Interrupt Type Interrupt Description How To Reset
Interrupt
Level
0b0001 - - - -
0b0110 Highest Receiver line status Overrun error, parity Read the line status
error, framing error, or register.
break interrupt
0b0100 Second Received data available Receiver data available Read the receiver
or trigger level reached buffer register or
in FIFO mode interrupt is
automatically reset if
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 895
DUART register descriptions
Table 20-4. UIIR IID Bits Summary (continued)
IID Bits IID[3-0] Priority Interrupt Type Interrupt Description How To Reset
Interrupt
Level
the number of bytes in
the receiver FIFO drops
below the trigger level.
0b1100 Second Character time-out No characters have Read the receiver
been removed from or buffer register.
input to the receiver
FIFO during the last 4
character times and
there is at least one
character in the
receiver FIFO during
this time.
0b0010 Third UTHR empty Transmitter holding Read the UIIR or write
register is empty to the UTHR.
0b0000 Fourth Modem status CTS_B input value Read the UMSR.
changed since last read
of UMSR
20.4.9.3 Diagram
Bits 0 1 2 3 4 5 6 7
FE64
IID3
IID2
IID1
IID0
R
Reserved
E
F
Reset 0 0 0 0 0 0 0 1
20.4.9.4 Fields
Field Function
0-1 FIFOs enabled. Reflects the setting of UFCR[FEN]
FE
2 64-byte FIFOs enabled. Reflects the setting of UFCR[EN64].
FE64 0b - 64-byte FIFOs disabled
1b - 64-byte FIFOs enabled
3 Reserved
—
4 Interrupt ID bits identify the highest priority interrupt that is pending as indicated in the table above. IID3 is
set along with IID2 only when a timeout interrupt is pending for FIFO mode.
IID3
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
896 NXP Semiconductors
Chapter 20 DUART
Field Function
5 Interrupt ID bits identify the highest priority interrupt that is pending as indicated in the table above.
IID2
6 Interrupt ID bits identify the highest priority interrupt that is pending as indicated in the table above.
IID1
7 IID0 indicates when an interrupt is pending.
IID0 0b - The UART has an active interrupt ready to be serviced.
1b - No interrupt is pending.
20.4.10 UART line control register (ULCR1 - ULCR2)
20.4.10.1 Offset
For a = 1 to 2:
Register Offset
ULCRa 403h + (a × 100h)
20.4.10.2 Function
This register is accessible when ULCR[DLAB] = x.
The ULCRs specify the data format for the UART bus and set the divisor latch access bit
ULCR[DLAB], which controls the ability to access the divisor latch least and most
significant bit registers and the alternate function register.
After initializing the ULCR, the software should not re-write the ULCR when valid
transfers on the UART bus are active. The software should not re-write the ULCR until
the last STOP bit has been received and there are no new characters being transferred on
the bus.
The stick parity bit, ULCR[SP], assigns a set parity value for the parity bit time slot sent
on the UART bus. The set value is defined as mark parity (logic 1) or space parity (logic
0). ULCR[PEN] and ULCR[EPS] help determine the set parity value. See the table below
for more information. ULCR[NSTB], defines the number of STOP bits to be sent at the
end of the data transfer. The receiver only checks the first STOP bit, regardless of the
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 897
DUART register descriptions
number of STOP bits selected. The word length select bits (1 and 0) define the number of
data bits that are transmitted or received as a serial character. The word length does not
include START, parity, and STOP bits.
Table 20-5. Parity Selection Using ULCR[PEN], ULCR[SP], and
ULCR[EPS]
PEN SP EPS Parity Selected
0 0 0 No parity
0 0 1 No parity
0 1 0 No parity
0 1 1 No parity
1 0 0 Odd parity
1 0 1 Even parity
1 1 0 Mark parity
1 1 1 Space parity
20.4.10.3 Diagram
Bits 0 1 2 3 4 5 6 7
R
DLAB
NST
EP
WL
PE
S
B
S
P
W
S
S
B
Reset 0 0 0 0 0 0 0 0
20.4.10.4 Fields
Field Function
0 Divisor latch access bit.
DLAB 0b - Access to all registers except UDLB, UAFR, and UDMB
1b - Ability to access divisor latch least and most significant byte registers and alternate function
register (UAFR)
1 Set break.
SB 0b - Send normal UTHR data onto the serial output (SOUT) signal
1b - Force logic 0 to be on the SOUT signal. Data in the UTHR is not affected
2 Stick parity.
SP 0b - Stick parity is disabled.
1b - If PEN = 1 and EPS = 1, space parity is selected. And if PEN = 1 and EPS = 0, mark parity is
selected.
3 Even parity select. See the table above for more information.
EPS 0b - If PEN = 1 and SP = 0, odd parity is selected.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
898 NXP Semiconductors
Chapter 20 DUART
Field Function
1b - If PEN = 1 and SP = 0, even parity is selected.
4 Parity enable.
PEN 0b - No parity generation and checking
1b - Generate parity bit as a transmitter, and check parity as a receiver
5 Number of STOP bits.
NSTB 0b - One STOP bit is generated in the transmitted data.
1b - When a 5-bit data length is selected, 1½ STOP bits are generated. When either a 6-, 7-, or 8-
bit word length is selected, two STOP bits are generated.
6-7 Word length select. Number of bits that comprise the character length. The word length select values are
as follows:
WLS
00b - 5 bits
01b - 6 bits
10b - 7 bits
11b - 8 bits
20.4.11 UART modem control register (UMCR1 - UMCR2)
20.4.11.1 Offset
For a = 1 to 2:
Register Offset
UMCRa 404h + (a × 100h)
20.4.11.2 Function
This register is accessible when ULCR[DLAB] = x.
The UMCRs control the interface with the external peripheral device on the UART bus.
20.4.11.3 Diagram
Bits 0 1 2 3 4 5 6 7
R
Reserved
Reserved
Reserved
LOOP
RT
AF
W
E
Reset 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 899
DUART register descriptions
20.4.11.4 Fields
Field Function
0-1 Reserved.
—
2 Auto Flow Control Enable
AFE Setting this bit to 1 enables the UART's autflow.
RTS AFE Auto-flow configuration:
0b - When RTS is either 0 or 1, both Auto-RTS and Auto-CTS are disabled.
1b - When RTS is 0, only Auto-CTS is enabled. When RTS is 1, both Auto-CTS and Auto-RTS are
enabled.
3 Local loopback mode.
LOOP 0b - Normal operation
1b - Functionally, the data written to UTHR can be read from URBR of the same UART , and
UMCR[RTS] is tied to UMSR[CTS] .
4-5 Reserved.
—
6 Ready to send.
RTS 0b - Negates corresponding RTS_B output
1b - Assert corresponding RTS_B output. Informs external modem or peripheral that the UART is
ready for sending/receiving data
7 Reserved.
—
20.4.12 UART line status register (ULSR1 - ULSR2)
20.4.12.1 Offset
For a = 1 to 2:
Register Offset
ULSRa 405h + (a × 100h)
20.4.12.2 Function
This register is accessible when ULCR[DLAB] = x.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
900 NXP Semiconductors
Chapter 20 DUART
The ULSRs are read-only registers that monitor the status of the data transfer on the
UART buses. To isolate the status bits from the proper character received through the
UART bus, software should read the ULSR and then the URBR.
20.4.12.3 Diagram
Bits 0 TEMT 1 2 3 4 5 6 7
THR
DR
R
RF
BI
E
F
P
E
O
E
E
E
W
Reset 0 1 1 0 0 0 0 0
20.4.12.4 Fields
Field Function
0 Receiver FIFO error.
RFE 0b - This bit is cleared when there are no errors in the receiver FIFO or on a read of the ULSR with
no remaining receiver FIFO errors.
1b - Set to one when one of the characters in the receiver FIFO encounters an error (framing,
parity, or break interrupt)
1 Transmitter empty.
TEMT 0b - Either or both the UTHR or the internal transmitter shift register has a data character. In FIFO
mode, a data character is in the transmitter FIFO or the internal transmitter shift register.
1b - Both the UTHR and the internal transmitter shift register are empty. In FIFO mode, both the
transmitter FIFO and the internal transmitter shift register are empty.
2 Transmitter holding register empty.
THRE 0b - The UTHR is not empty.
1b - A data character has transferred from the UTHR into the internal transmitter shift register. In
FIFO mode, the transmitter FIFO contains no data character.
3 Break interrupt.
BI NOTE: For a single break signal, BI and DR are set multiple times, approximately once every character
period. The BI and DR bits continue to be set each character period after they are cleared. This
continues for the entire duration of the break signal. To accommodate this behavior, read URBR,
which returns zeros and clears DR. Then delay one character period and read URBR again.
Note that at the end of the break signal, a random character may be falsely detected and
received in the URBR, with ULSR[DR] being set.
0b - This bit is cleared when the ULSR is read or when a valid data transfer is detected (that is,
STOP bit is received).
1b - Received data of logic 0 for more than START bit + Data bits + Parity bit + one STOP bits
length of time. A new character is not loaded until SIN returns to the mark state (logic 1) and a valid
START is detected. In FIFO mode, a zero character is encountered in the FIFO (the zero character
is at the top of the FIFO). In FIFO mode, only one zero character is stored.
4 Framing error.
FE
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 901
DUART register descriptions
Field Function
0b - This bit is cleared when ULSR is read or when a new character is loaded into the URBR from
the receiver shift register.
1b - Invalid STOP bit for receive data (only the first STOP bit is checked). In FIFO mode, this bit is
set when the character that detected a framing error is encountered in the FIFO (that is the
character at the top of the FIFO). An attempt to resynchronize occurs after a framing error. The
UART assumes that the framing error (due to a logic 0 being read when a logic 1 (STOP) was
expected) was due to a STOP bit overlapping with the next START bit, so it assumes this logic 0
sample is a true START bit and then receives the following new data.
5 Parity error.
PE 0b - This bit is cleared when ULSR is read or when a new character is loaded into the URBR.
1b - Unexpected parity value encountered when receiving data. In FIFO mode, the character with
the error is at the top of the FIFO .
6 Overrun error.
OE 0b - This bit is cleared when ULSR is read.
1b - Before the URBR is read, the URBR was overwritten with a new character. The old character
is loss. In FIFO mode, the receiver FIFO is full (regardless of the receiver FIFO trigger level setting)
and a new character has been received into the internal receiver shift register. The old character
was overwritten by the new character. Data in the receiver FIFO was not overwritten.
7 Data ready.
DR 0b - This bit is cleared when URBR is read or when all of the data in the receiver FIFO is read.
1b - A character has been received in the URBR or the receiver FIFO.
20.4.13 UART modem status register (UMSR1 - UMSR2)
20.4.13.1 Offset
For a = 1 to 2:
Register Offset
UMSRa 406h + (a × 100h)
20.4.13.2 Function
This register is accessible when ULCR[DLAB] = x.
The UMSRs track the status of the modem (or external peripheral device) clear to send
( CTS_B ) signal for the corresponding UART .
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
902 NXP Semiconductors
Chapter 20 DUART
20.4.13.3 Diagram
Bits 0 1 2 3 4 5 6 7
DCTS
CTS
Reserved
Reserved
R
W
Reset 0 0 0 0 0 0 0 0
20.4.13.4 Fields
Field Function
0-2 Reserved.
—
3 Clear to send. Represents the inverted value of the CTS_B input pin from the external peripheral device
CTS 0b - Corresponding UARTn_CTS_B is negated
1b - Corresponding UARTn_CTS_B is asserted. The modem or peripheral device is ready for data
transfers.
4-6 Reserved.
—
7 Clear to send.
DCTS 0b - No change on the corresponding UARTn_CTS_B signal since the last read of UMSR[CTS]
1b - The UARTn_CTS_B value has changed, since the last read of UMSR[CTS]. Causes an
interrupt if UIER[EMSI] is set to detect this condition
20.4.14 UART scratch register (USCR1 - USCR2)
20.4.14.1 Offset
For a = 1 to 2:
Register Offset
USCRa 407h + (a × 100h)
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 903
DUART register descriptions
20.4.14.2 Function
This register is accessible when ULCR[DLAB] = x.
The USCR registers are for debugging software or the DUART hardware. The USCRs do
not affect the operation of the DUART.
20.4.14.3 Diagram
Bits 0 1 2 3 4 5 6 7
R
DATA
W
Reset 0 0 0 0 0 0 0 0
20.4.14.4 Fields
Field Function
0-7 Data
DATA
20.4.15 UART DMA status register (UDSR1 - UDSR2)
20.4.15.1 Offset
For a = 1 to 2:
Register Offset
UDSRa 410h + (a × 100h)
20.4.15.2 Function
This register is accessible when ULCR[DLAB] = x.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
904 NXP Semiconductors
Chapter 20 DUART
The DMA status registers (UDSRs) are read-only registers that return transmitter and
receiver FIFO status. UDSRs also provide the ability to assist DMA data operations to
and from the FIFOs.
Table 20-6. UDSR[TXRDY] Set Conditions
DMS FEN DMA Mode Meaning
0 0 0 TXRDY is set after the first
character is loaded into the
0 1 0
transmitter FIFO or UTHR.
1 0 0
1 1 1 TXRDY is set when the
transmitter FIFO is full.
Table 20-7. UDSR[TXRDY] Cleared Conditions
DMS FEN DMA Mode Meaning
0 0 0 TXRDY is cleared when there
are no characters in the
0 1 0
transmitter FIFO or UTHR.
1 0 0
1 1 1 TXRDY is cleared when there
are no characters in the
transmitter FIFO or UTHR.
TXRDY remains clear when
the transmitter FIFO is not yet
full.
Table 20-8. UDSR[RXRDY] Set Conditions
DMS FEN DMA Mode Meaning
0 0 0 RXRDY is set when there are
no characters in the receiver
0 1 0
FIFO or URBR.
1 0 0
1 1 1 RXRDY is set when the
trigger level has not been
reached and there has been
no time out.
Table 20-9. UDSR[RXRDY] Cleared Conditions
DMS FEN DMA Mode Meaning
0 0 0 RXRDY is cleared when there
is at least one character in the
0 1 0
receiver FIFO or URBR.
1 0 0
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 905
Functional description
Table 20-9. UDSR[RXRDY] Cleared Conditions (continued)
DMS FEN DMA Mode Meaning
1 1 1 RXRDY is cleared when the
trigger level or a time-out has
been reached. RXRDY
remains cleared until the
receiver FIFO is empty.
20.4.15.3 Diagram
Bits 0 1 2 3 4 5 6 7
TXRDY
RXRD
Reserved
Y
W
Reset 0 0 0 0 0 0 0 1
20.4.15.4 Fields
Field Function
0-5 Reserved
—
6 Transmitter ready. This read-only bit reflects the status of the transmitter FIFO or the UTHR. The status
depends on the DMA mode selected, which is determined by the DMS and FEN bits in the UFCR.
TXRDY
0b - This bit is cleared, as shown in Table 20-7 .
1b - This bit is set, as shown in Table 20-6 .
7 Receiver ready. This read-only bit reflects the status of the receiver FIFO or URBR. The status depends
on the DMA mode selected, which is determined by the DMS and FEN bits in the UFCR.
RXRDY
0b - This bit is cleared, as shown in Table 20-9 .
1b - This bit is set, as shown in Table 20-8 .
20.5 Functional description
The following sections provide the function of the DUART controller.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
906 NXP Semiconductors
Chapter 20 DUART
20.5.1 Serial interface
The UART bus is a serial, full-duplex, point-to-point bus as shown in the following
figure. Therefore, only two devices are attached to the same signals and there is no need
for address or arbitration bus cycles.
rxcnt 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10
SOUT1 D6 D5 D4 D3 D2 D1 D0 PTY D6 D5 D4 D3 D2 D1 D0 PTY
Data bits Data bits
START STOP Bits START STOP Bits
Optional Optional
Even/odd parity even/odd parity
Two 7-bit data transmissions with parity and 2-bit STOP transactions
Figure 20-2. UART bus interface transaction protocol example
A standard UART bus transfer is composed of either three or four parts:
• START bit
• Data transfer bits (least-significant bit is first data bit on the bus)
• Parity bit (optional)
• STOP bits
An internal logic sample signal, rxcnt, uses the frequency of the baud-rate generator to
drive the bits on SOUT.
The following sections describe the four components of the serial interface, the baud-rate
generator, local loopback mode, different errors, and FIFO mode.
20.5.1.1 START bit
A write to the transmitter holding register (UTHR) generates a START bit on the SOUT
signal.
Figure 20-2 shows that the START bit is defined as a logic 0. The START bit denotes the
beginning of a new data transfer which is limited to the bit length programmed in the
UART line control register (ULCR). When the bus is idle, SOUT is high.
20.5.1.2 Data transfer
Each data transfer contains 5-8 bits of data.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 907
Functional description
The ULCR data bit length for the transmitter and receiver UART devices must agree
before a transfer begins; otherwise, a parity or framing error may occur. A transfer begins
when UTHR is written. At that time a START bit is generated followed by 5-8 of the data
bits previously written to the UTHR. The data bits are driven from the least significant to
the most significant bits. After the parity and STOP bits, a new data transfer can begin if
new data is written to the UTHR.
20.5.1.3 Parity bit
The user has the option of using even, odd, no parity, or stick parity.
See UART line control register (ULCR1 - ULCR2). Both the receiver and transmitter
parity definition must agree before attempting to transfer data. When receiving data, a
parity error can occur if an unexpected parity value is detected. See UART line status
register (ULSR1 - ULSR2).
20.5.1.4 STOP bit
The transmitter device ends the write transfer by generating a STOP bit.
The STOP bit is always high. The length of the STOP bit(s) can be programmed in the
ULCR. Both the receiver and transmitter STOP bit length must agree before attempting
to transfer data. A framing error can occur if an invalid STOP bit is detected.
20.5.2 Baud-rate generator logic
Each UART contains an independent programmable baud-rate generator, that is capable
of taking the platform clock frequencyas input and dividing the input by any divisor from
1 to 216 - 1.
The baud rate is defined as the number of bits per second that can be sent over the UART
bus. The formula for calculating baud rate is as follows:
Baud rate = (1/16) x (platform clock frequency ÷ divisor value)
Therefore, the output frequency of the baud-rate generator is 16 times the baud rate.
The divisor value is determined by the following two 8-bit registers to form a 16-bit
binary number:
• UART divisor most significant byte register (UDMB)
• UART divisor least significant byte register (UDLB)
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
908 NXP Semiconductors
Chapter 20 DUART
Upon loading either of the divisor latches, a 16-bit baud-rate counter is loaded.
The divisor latches must be loaded during initialization to ensure proper operation of the
baud-rate generator. Both UART devices on the same bus must be programmed for the
same baud-rate before starting a transfer.
The baud clock can be passed to the performance monitor by enabling the UAFR[BO]
bit. This can be used to determine baud rate errors.
20.5.3 Local loopback mode
Local loopback mode is provided for diagnostic testing.
The data written to UTHR can be read from the receiver buffer register (URBR) of the
same UART. In this mode, the modem control register UMCR[RTS] is internally tied to
the modem status register UMSR[CTS]. The transmitter SOUT is set to a logic 1 and the
receiver SIN is disconnected. The output of the transmitter shift register is looped back
into the receiver shift register input. The CTS_B (input signal) is disconnected, RTS_B is
internally connected to CTS_B, and the RTS_B (output signal) becomes inactive. In this
diagnostic mode, data that is transmitted is immediately received. In local loopback
mode, the transmit and receive data paths of the DUART can be verified.
NOTE
In local loopback mode, the transmit/receive interrupts are fully
operational and can be controlled by the interrupt enable
register (UIER).
20.5.4 Errors
The following sections describe framing, parity, and overrun errors which may occur
while data is transferred on the UART bus.
Each of the error bits are usually cleared, as described below, when the line status register
(ULSR) is read.
20.5.4.1 Framing error
When an invalid STOP bit is detected, a framing error occurs and ULSR[FE] is set.
Note that only the first STOP bit is checked. In FIFO mode, ULSR[FE] is set when the
character at the top of the FIFO detects a framing error. An attempt to re-synchronize
occurs after a framing error. The UART assumes that the framing error (due to a logic 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 909
Functional description
being read when a logic 1 (STOP) was expected) was due to a STOP bit overlapping with
the next START bit. ULSR[FE] is cleared when ULSR is read or when a new character is
loaded into the URBR from the receiver shift register.
20.5.4.2 Parity error
A parity error occurs, and ULSR[PE] is set, when unexpected parity values are
encountered while receiving data.
In FIFO mode, ULSR[PE] is set when the character with the error is at the top of the
FIFO. ULSR[PE] is cleared when ULSR is read or when a new character is loaded into
the URBR.
20.5.4.3 Overrun error
When a new (overwriting character) STOP bit is detected and the old character is lost, an
overrun error occurs and ULSR[OE] is set.
In FIFO mode, ULSR[OE] is set after the receiver FIFO is full (despite the receiver FIFO
trigger level setting) and a new character has been received into the internal receiver shift
register. Data in the FIFO is not overwritten; only the shift register data is overwritten.
Therefore, the interrupt occurs immediately. ULSR[OE] is cleared when ULSR is read.
20.5.5 FIFO mode
The UARTs use an alternate mode (FIFO mode) to relieve the processor core from
excessive software overhead.
The FIFO control register (UFCR) is used to enable and clear the receiver and transmitter
FIFOs and set the FIFO receiver trigger level UFCR[RTL] to control the received data
available interrupt UIER[ERDAI].
The UFCR also selects the type of DMA signaling. The UDSR[RXRDY] indicates the
status of the receiver FIFO. The DMA status registers (UDSR[TXRDY]) indicate when
the transmitter FIFO is full. When in FIFO mode, data written to UTHR is placed into the
transmitter FIFO. The first byte written to UTHR is the first byte onto the UART bus.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
910 NXP Semiconductors
Chapter 20 DUART
20.5.5.1 FIFO interrupts
In FIFO mode, the UIER[ERDAI] is set when a time-out interrupt occurs. When a
receive data time-out occurs there is a maskable interrupt condition (through
UIER[ERDAI]). See UART interrupt enable register (UIER1 - UIER2) for more details
on interrupt enables.
The interrupt ID register (UIIR) indicates if the FIFOs are enabled. The interrupt ID3 bit
UIIR[IID3] is only set for FIFO mode interrupts. The character time-out interrupt occurs
when no characters have been removed from or input to the receiver FIFO during the last
four character times and there is at least one character in the receiver FIFO during this
time. The character time-out interrupt (controlled by UIIR[IIDn]) is cleared when the
URBR is read. See UART interrupt ID register (UIIR1 - UIIR2) for more information.
The UIIR[FE] bit indicates if FIFO mode is enabled.
20.5.5.2 Interrupt control logic
An interrupt is active when DUART interrupt ID register bit 7 (UIIR[IID0]), is cleared.
The interrupt enable register (UIER) is used to mask specific interrupt types. See UART
interrupt enable register (UIER1 - UIER2) for more details.
When the interrupts are disabled in UIER, polling software cannot use UIIR[IID0] to
determine whether the UART is ready for service. The software must monitor the
appropriate bits in the line status (ULSR) and/or the modem status registers (UMSR).
UIIR[IID0] can be used for polling if the interrupts are enabled in UIER.
20.6 Initialization/Application information
The following requirements must be met for DUART accesses:
• All DUART registers must be mapped to a cache-inhibited and guarded area. (That
is, the WIMG setting in the MMU needs to be 0b01X1.)
• All DUART registers are 1 byte wide. Reads and writes to these registers must be
byte-wide operations.
A system reset puts the DUART registers to a default state. Before the interface can
transfer serial data, the following initialization steps are recommended:
1. Update the programmable interrupt controller (PIC) DUART channel interrupt vector
source registers.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 911
Initialization/Application information
2. Set data attributes and control bits in the ULCR, UFCR, UAFR, UMCR, UDLB, and
UDMB.
3. Set the data attributes and control bits of the external modem or peripheral device.
4. Set the interrupt enable register (UIER).
5. To start a write transfer, write to the UTHR.
6. Poll UIIR, if the interrupts generated by the DUART are masked.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
912 NXP Semiconductors
Chapter 21
Enhanced Direct Memory Access (eDMA)
21.1 Overview
The Enhanced direct memory access (eDMA) is a general purpose DMA which can be
used for data transfer between slow peripherals (SPI, I2C, QSPI, FlexTimer, LPUART)
and DDR memory.
21.2 Introduction
The enhanced direct memory access (eDMA) controller is a second-generation module
capable of performing complex data transfers with minimal intervention from a host
processor. The hardware microarchitecture includes:
• A DMA engine that performs:
• Source address and destination address calculations
• Data-movement operations
• Local memory containing transfer control descriptors for each of the 32 channels
21.2.1 eDMA system block diagram
Figure 21-1 illustrates the components of the eDMA system, including the eDMA
module ("engine").
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 913
Introduction
eDMA system Write Address
Write Data
0
1
2
Internal Peripheral Bus
To/From Crossbar Switch
Transfer Control
Descriptor (TCD) n-1
64
eDMA e ngine
Program Model/
Read Data
Channel Arbitration
Read Data
Address Path
Control
Data Path
Write Data
Address
eDMA Peripheral
eDMA Done
Request
Figure 21-1. eDMA system block diagram
21.2.2 Block parts
The eDMA module is partitioned into two major modules: the eDMA engine and the
transfer-control descriptor local memory.
The eDMA engine is further partitioned into four submodules:
Table 21-1. eDMA engine submodules
Submodule Function
Address path This block implements registered versions of two channel transfer control descriptors, channel x
and channel y, and manages all master bus-address calculations. All the channels provide the
same functionality. This structure allows data transfers associated with one channel to be
preempted after the completion of a read/write sequence if a higher priority channel activation is
asserted while the first channel is active. After a channel is activated, it runs until the minor loop is
completed, unless preempted by a higher priority channel. This provides a mechanism (enabled
by DCHPRIn[ECP]) where a large data move operation can be preempted to minimize the time
another channel is blocked from execution.
When any channel is selected to execute, the contents of its TCD are read from local memory and
loaded into the address path channel x registers for a normal start and into channel y registers for
a preemption start. After the minor loop completes execution, the address path hardware writes
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
914 NXP Semiconductors
Chapter 21 Enhanced Direct Memory Access (eDMA)
Table 21-1. eDMA engine submodules (continued)
Submodule Function
the new values for the TCDn_{SADDR, DADDR, CITER} back to local memory. If the major
iteration count is exhausted, additional processing is performed, including the final address pointer
updates, reloading the TCDn_CITER field, and a possible fetch of the next TCDn from memory as
part of a scatter/gather operation.
Data path This block implements the bus master read/write datapath. It includes a data buffer and the
necessary multiplex logic to support any required data alignment. The internal read data bus is the
primary input, and the internal write data bus is the primary output.
The address and data path modules directly support the 2-stage pipelined internal bus. The
address path module represents the 1st stage of the bus pipeline (address phase), while the data
path module implements the 2nd stage of the pipeline (data phase).
Program model/channel This block implements the first section of the eDMA programming model as well as the channel
arbitration arbitration logic. The programming model registers are connected to the internal peripheral bus.
The eDMA peripheral request inputs and interrupt request outputs are also connected to this block
(via control logic).
Control This block provides all the control functions for the eDMA engine. For data transfers where the
source and destination sizes are equal, the eDMA engine performs a series of source read/
destination write operations until the number of bytes specified in the minor loop byte count has
moved. For descriptors where the sizes are not equal, multiple accesses of the smaller size data
are required for each reference of the larger size. As an example, if the source size references 16-
bit data and the destination is 32-bit data, two reads are performed, then one 32-bit write.
The transfer-control descriptor local memory is further partitioned into:
Table 21-2. Transfer control descriptor memory
Submodule Description
Memory controller This logic implements the required dual-ported controller, managing accesses from the eDMA
engine as well as references from the internal peripheral bus. As noted earlier, in the event of
simultaneous accesses, the eDMA engine is given priority and the peripheral transaction is
stalled.
Memory array TCD storage for each channel's transfer profile.
21.2.3 Features
The eDMA is a highly programmable data-transfer engine optimized to minimize any
required intervention from the host processor. It is intended for use in applications where
the data size to be transferred is statically known and not defined within the transferred
data itself. The eDMA module features:
• All data movement via dual-address transfers: read from source, write to destination
• Programmable source and destination addresses and transfer size
• Support for enhanced addressing modes
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 915
Modes of operation
• 32-channel implementation that performs complex data transfers with minimal
intervention from a host processor
• Internal data buffer, used as temporary storage to support 16- and 32-byte
transfers
• Connections to the crossbar switch for bus mastering the data movement
• Transfer control descriptor (TCD) organized to support two-deep, nested transfer
operations
• 32-byte TCD stored in local memory for each channel
• An inner data transfer loop defined by a minor byte transfer count
• An outer data transfer loop defined by a major iteration count
• Channel activation via one of three methods:
• Explicit software initiation
• Initiation via a channel-to-channel linking mechanism for continuous transfers
• Peripheral-paced hardware requests, one per channel
• Fixed-priority and round-robin channel arbitration
• Channel completion reported via programmable interrupt requests
• One interrupt per channel, which can be asserted at completion of major iteration
count
• Programmable error terminations per channel and logically summed together to
form one error interrupt to the interrupt controller
• Programmable support for scatter/gather DMA processing
• Support for complex data structures
In the discussion of this module, n is used to reference the channel number.
21.3 Modes of operation
The eDMA operates in the following modes:
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
916 NXP Semiconductors
Chapter 21 Enhanced Direct Memory Access (eDMA)
Table 21-3. Modes of operation
Mode Description
Normal In Normal mode, the eDMA transfers data between a source and a destination. The source and
destination can be a memory block or an I/O block capable of operation with the eDMA.
A service request initiates a transfer of a specific number of bytes (NBYTES) as specified in the
transfer control descriptor (TCD). The minor loop is the sequence of read-write operations that
transfers these NBYTES per service request. Each service request executes one iteration of the
major loop, which transfers NBYTES of data.
Debug DMA operation is configurable in Debug mode via the control register:
• If CR[EDBG] is cleared, the DMA continues to operate.
• If CR[EDBG] is set, the eDMA stops transferring data. If Debug mode is entered while a
channel is active, the eDMA continues operation until the channel retires.
21.4 Memory map/register definition
The eDMA's programming model is partitioned into two regions:
• The first region defines a number of registers providing control functions
• The second region corresponds to the local transfer control descriptor (TCD)
memory
21.4.1 TCD memory
Each channel requires a 32-byte transfer control descriptor for defining the desired data
movement operation. The channel descriptors are stored in the local memory in
sequential order: channel 0, channel 1, ... channel 31. Each TCDn definition is presented
as 11 registers of 16 or 32 bits.
21.4.2 TCD initialization
Prior to activating a channel, you must initialize its TCD with the appropriate transfer
profile.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 917
Memory map/register definition
21.4.3 TCD structure
DMA Basics: TCD Structure
• One DMA engine has a number of channels to react to DMA requests
• Each channel has its own TCD
Word
Offset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0x1000 SADDR
0x1004 SMOD SSIZE DMOD DSIZE SOFF
0x1008 NBYTES1
DMLOE1
SMLOE1
0x1008 MLOFF or NBYTES1 NBYTES1
0x100C SLAST
0x1010 DADDR
CITER.E_LINK
0x1014 CITER or DOFF
CITER.LINKCH CITER
0x1018 DLAST_SGA
MAJOR.E_LINK
BITER.E_LINK
INT_HALF
INT_MAJ
ACTIVE
D_REQ
START
DONE
E_SG
BITER or
0x101C BITER.LINKCH BITER BWC MAJOR LINKCH
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
1 The fields implemented in Word 2 depend on whether EDMA_CR[EMLM] bit is set to 0 or 1.
21.4.4 Reserved memory and bit fields
• Reading reserved bits in a register returns the value of zero.
• Writes to reserved bits in a register are ignored.
• Reading or writing a reserved memory location generates a bus error.
21.4.5 Endianness
This module's memory map uses big-endian ordering. This means:
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
918 NXP Semiconductors
Chapter 21 Enhanced Direct Memory Access (eDMA)
• For 8-bit registers, the lower address byte is read as the most significant byte.
• For 16-bit registers, the lower address word is read as the most significant word.
The following figure provides examples of this.
Example 1: 8-bit register structure Example 2: 16-bit register structure
Address Register Data Address Register Data
00h AAh 00h AABBh
01h BBh 02h CCDDh
02h CCh
03h DDh
For this structure, an 8-bit read of For this structure, a 16-bit read of
address 00h will yield DDh. address 00h will yield CCDDh.
Figure 21-2. Examples of big-endian register access results
DMA memory map
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
2C0_0000 Control Register (DMA_CR) 32 R/W 0000_0400h 21.4.6/945
2C0_0004 Error Status Register (DMA_ES) 32 R 0000_0000h 21.4.7/948
2C0_000C Enable Request Register (DMA_ERQ) 32 R/W 0000_0000h 21.4.8/950
2C0_0014 Enable Error Interrupt Register (DMA_EEI) 32 R/W 0000_0000h 21.4.9/954
W
21.4.10/
2C0_0018 Clear Enable Error Interrupt Register (DMA_CEEI) 8 (always 00h
957
reads 0)
W
21.4.11/
2C0_0019 Set Enable Error Interrupt Register (DMA_SEEI) 8 (always 00h
958
reads 0)
W
21.4.12/
2C0_001A Clear Enable Request Register (DMA_CERQ) 8 (always 00h
959
reads 0)
W
21.4.13/
2C0_001B Set Enable Request Register (DMA_SERQ) 8 (always 00h
960
reads 0)
W
21.4.14/
2C0_001C Clear DONE Status Bit Register (DMA_CDNE) 8 (always 00h
961
reads 0)
W
21.4.15/
2C0_001D Set START Bit Register (DMA_SSRT) 8 (always 00h
962
reads 0)
W
21.4.16/
2C0_001E Clear Error Register (DMA_CERR) 8 (always 00h
963
reads 0)
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 919
Memory map/register definition
DMA memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
W
21.4.17/
2C0_001F Clear Interrupt Request Register (DMA_CINT) 8 (always 00h
964
reads 0)
21.4.18/
2C0_0024 Interrupt Request Register (DMA_INT) 32 R/W 0000_0000h
965
21.4.19/
2C0_002C Error Register (DMA_ERR) 32 R/W 0000_0000h
968
21.4.20/
2C0_0034 Hardware Request Status Register (DMA_HRS) 32 R 0000_0000h
972
21.4.21/
2C0_0100 Channel n Priority Register (DMA_DCHPRI3) 8 R/W See section
978
21.4.21/
2C0_0101 Channel n Priority Register (DMA_DCHPRI2) 8 R/W See section
978
21.4.21/
2C0_0102 Channel n Priority Register (DMA_DCHPRI1) 8 R/W See section
978
21.4.21/
2C0_0103 Channel n Priority Register (DMA_DCHPRI0) 8 R/W See section
978
21.4.21/
2C0_0104 Channel n Priority Register (DMA_DCHPRI7) 8 R/W See section
978
21.4.21/
2C0_0105 Channel n Priority Register (DMA_DCHPRI6) 8 R/W See section
978
21.4.21/
2C0_0106 Channel n Priority Register (DMA_DCHPRI5) 8 R/W See section
978
21.4.21/
2C0_0107 Channel n Priority Register (DMA_DCHPRI4) 8 R/W See section
978
21.4.21/
2C0_0108 Channel n Priority Register (DMA_DCHPRI11) 8 R/W See section
978
21.4.21/
2C0_0109 Channel n Priority Register (DMA_DCHPRI10) 8 R/W See section
978
21.4.21/
2C0_010A Channel n Priority Register (DMA_DCHPRI9) 8 R/W See section
978
21.4.21/
2C0_010B Channel n Priority Register (DMA_DCHPRI8) 8 R/W See section
978
21.4.21/
2C0_010C Channel n Priority Register (DMA_DCHPRI15) 8 R/W See section
978
21.4.21/
2C0_010D Channel n Priority Register (DMA_DCHPRI14) 8 R/W See section
978
21.4.21/
2C0_010E Channel n Priority Register (DMA_DCHPRI13) 8 R/W See section
978
21.4.21/
2C0_010F Channel n Priority Register (DMA_DCHPRI12) 8 R/W See section
978
21.4.21/
2C0_0110 Channel n Priority Register (DMA_DCHPRI19) 8 R/W See section
978
21.4.21/
2C0_0111 Channel n Priority Register (DMA_DCHPRI18) 8 R/W See section
978
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
920 NXP Semiconductors
Chapter 21 Enhanced Direct Memory Access (eDMA)
DMA memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
21.4.21/
2C0_0112 Channel n Priority Register (DMA_DCHPRI17) 8 R/W See section
978
21.4.21/
2C0_0113 Channel n Priority Register (DMA_DCHPRI16) 8 R/W See section
978
21.4.21/
2C0_0114 Channel n Priority Register (DMA_DCHPRI23) 8 R/W See section
978
21.4.21/
2C0_0115 Channel n Priority Register (DMA_DCHPRI22) 8 R/W See section
978
21.4.21/
2C0_0116 Channel n Priority Register (DMA_DCHPRI21) 8 R/W See section
978
21.4.21/
2C0_0117 Channel n Priority Register (DMA_DCHPRI20) 8 R/W See section
978
21.4.21/
2C0_0118 Channel n Priority Register (DMA_DCHPRI27) 8 R/W See section
978
21.4.21/
2C0_0119 Channel n Priority Register (DMA_DCHPRI26) 8 R/W See section
978
21.4.21/
2C0_011A Channel n Priority Register (DMA_DCHPRI25) 8 R/W See section
978
21.4.21/
2C0_011B Channel n Priority Register (DMA_DCHPRI24) 8 R/W See section
978
21.4.21/
2C0_011C Channel n Priority Register (DMA_DCHPRI31) 8 R/W See section
978
21.4.21/
2C0_011D Channel n Priority Register (DMA_DCHPRI30) 8 R/W See section
978
21.4.21/
2C0_011E Channel n Priority Register (DMA_DCHPRI29) 8 R/W See section
978
21.4.21/
2C0_011F Channel n Priority Register (DMA_DCHPRI28) 8 R/W See section
978
21.4.22/
2C0_1000 TCD Source Address (DMA_TCD0_SADDR) 32 R/W Undefined
979
21.4.23/
2C0_1004 TCD Signed Source Address Offset (DMA_TCD0_SOFF) 16 R/W Undefined
980
21.4.24/
2C0_1006 TCD Transfer Attributes (DMA_TCD0_ATTR) 16 R/W Undefined
980
TCD Minor Byte Count (Minor Loop Mapping Disabled) 21.4.25/
2C0_1008 32 R/W Undefined
(DMA_TCD0_NBYTES_MLNO) 981
TCD Signed Minor Loop Offset (Minor Loop Mapping
21.4.26/
2C0_1008 Enabled and Offset Disabled) 32 R/W Undefined
982
(DMA_TCD0_NBYTES_MLOFFNO)
TCD Signed Minor Loop Offset (Minor Loop Mapping and 21.4.27/
2C0_1008 32 R/W Undefined
Offset Enabled) (DMA_TCD0_NBYTES_MLOFFYES) 983
TCD Last Source Address Adjustment 21.4.28/
2C0_100C 32 R/W Undefined
(DMA_TCD0_SLAST) 985
21.4.29/
2C0_1010 TCD Destination Address (DMA_TCD0_DADDR) 32 R/W Undefined
985
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 921
Memory map/register definition
DMA memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
TCD Signed Destination Address Offset 21.4.30/
2C0_1014 16 R/W Undefined
(DMA_TCD0_DOFF) 986
TCD Current Minor Loop Link, Major Loop Count (Channel 21.4.31/
2C0_1016 16 R/W Undefined
Linking Enabled) (DMA_TCD0_CITER_ELINKYES) 986
21.4.32/
2C0_1016 DMA_TCD0_CITER_ELINKNO 16 R/W Undefined
987
TCD Last Destination Address Adjustment/Scatter Gather 21.4.33/
2C0_1018 32 R/W Undefined
Address (DMA_TCD0_DLASTSGA) 988
21.4.34/
2C0_101C TCD Control and Status (DMA_TCD0_CSR) 16 R/W Undefined
989
TCD Beginning Minor Loop Link, Major Loop Count
21.4.35/
2C0_101E (Channel Linking Enabled) 16 R/W Undefined
991
(DMA_TCD0_BITER_ELINKYES)
TCD Beginning Minor Loop Link, Major Loop Count 21.4.36/
2C0_101E 16 R/W Undefined
(Channel Linking Disabled) (DMA_TCD0_BITER_ELINKNO) 992
21.4.22/
2C0_1020 TCD Source Address (DMA_TCD1_SADDR) 32 R/W Undefined
979
21.4.23/
2C0_1024 TCD Signed Source Address Offset (DMA_TCD1_SOFF) 16 R/W Undefined
980
21.4.24/
2C0_1026 TCD Transfer Attributes (DMA_TCD1_ATTR) 16 R/W Undefined
980
TCD Minor Byte Count (Minor Loop Mapping Disabled) 21.4.25/
2C0_1028 32 R/W Undefined
(DMA_TCD1_NBYTES_MLNO) 981
TCD Signed Minor Loop Offset (Minor Loop Mapping
21.4.26/
2C0_1028 Enabled and Offset Disabled) 32 R/W Undefined
982
(DMA_TCD1_NBYTES_MLOFFNO)
TCD Signed Minor Loop Offset (Minor Loop Mapping and 21.4.27/
2C0_1028 32 R/W Undefined
Offset Enabled) (DMA_TCD1_NBYTES_MLOFFYES) 983
TCD Last Source Address Adjustment 21.4.28/
2C0_102C 32 R/W Undefined
(DMA_TCD1_SLAST) 985
21.4.29/
2C0_1030 TCD Destination Address (DMA_TCD1_DADDR) 32 R/W Undefined
985
TCD Signed Destination Address Offset 21.4.30/
2C0_1034 16 R/W Undefined
(DMA_TCD1_DOFF) 986
TCD Current Minor Loop Link, Major Loop Count (Channel 21.4.31/
2C0_1036 16 R/W Undefined
Linking Enabled) (DMA_TCD1_CITER_ELINKYES) 986
21.4.32/
2C0_1036 DMA_TCD1_CITER_ELINKNO 16 R/W Undefined
987
TCD Last Destination Address Adjustment/Scatter Gather 21.4.33/
2C0_1038 32 R/W Undefined
Address (DMA_TCD1_DLASTSGA) 988
21.4.34/
2C0_103C TCD Control and Status (DMA_TCD1_CSR) 16 R/W Undefined
989
TCD Beginning Minor Loop Link, Major Loop Count
21.4.35/
2C0_103E (Channel Linking Enabled) 16 R/W Undefined
991
(DMA_TCD1_BITER_ELINKYES)
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
922 NXP Semiconductors
Chapter 21 Enhanced Direct Memory Access (eDMA)
DMA memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
TCD Beginning Minor Loop Link, Major Loop Count 21.4.36/
2C0_103E 16 R/W Undefined
(Channel Linking Disabled) (DMA_TCD1_BITER_ELINKNO) 992
21.4.22/
2C0_1040 TCD Source Address (DMA_TCD2_SADDR) 32 R/W Undefined
979
21.4.23/
2C0_1044 TCD Signed Source Address Offset (DMA_TCD2_SOFF) 16 R/W Undefined
980
21.4.24/
2C0_1046 TCD Transfer Attributes (DMA_TCD2_ATTR) 16 R/W Undefined
980
TCD Minor Byte Count (Minor Loop Mapping Disabled) 21.4.25/
2C0_1048 32 R/W Undefined
(DMA_TCD2_NBYTES_MLNO) 981
TCD Signed Minor Loop Offset (Minor Loop Mapping
21.4.26/
2C0_1048 Enabled and Offset Disabled) 32 R/W Undefined
982
(DMA_TCD2_NBYTES_MLOFFNO)
TCD Signed Minor Loop Offset (Minor Loop Mapping and 21.4.27/
2C0_1048 32 R/W Undefined
Offset Enabled) (DMA_TCD2_NBYTES_MLOFFYES) 983
TCD Last Source Address Adjustment 21.4.28/
2C0_104C 32 R/W Undefined
(DMA_TCD2_SLAST) 985
21.4.29/
2C0_1050 TCD Destination Address (DMA_TCD2_DADDR) 32 R/W Undefined
985
TCD Signed Destination Address Offset 21.4.30/
2C0_1054 16 R/W Undefined
(DMA_TCD2_DOFF) 986
TCD Current Minor Loop Link, Major Loop Count (Channel 21.4.31/
2C0_1056 16 R/W Undefined
Linking Enabled) (DMA_TCD2_CITER_ELINKYES) 986
21.4.32/
2C0_1056 DMA_TCD2_CITER_ELINKNO 16 R/W Undefined
987
TCD Last Destination Address Adjustment/Scatter Gather 21.4.33/
2C0_1058 32 R/W Undefined
Address (DMA_TCD2_DLASTSGA) 988
21.4.34/
2C0_105C TCD Control and Status (DMA_TCD2_CSR) 16 R/W Undefined
989
TCD Beginning Minor Loop Link, Major Loop Count
21.4.35/
2C0_105E (Channel Linking Enabled) 16 R/W Undefined
991
(DMA_TCD2_BITER_ELINKYES)
TCD Beginning Minor Loop Link, Major Loop Count 21.4.36/
2C0_105E 16 R/W Undefined
(Channel Linking Disabled) (DMA_TCD2_BITER_ELINKNO) 992
21.4.22/
2C0_1060 TCD Source Address (DMA_TCD3_SADDR) 32 R/W Undefined
979
21.4.23/
2C0_1064 TCD Signed Source Address Offset (DMA_TCD3_SOFF) 16 R/W Undefined
980
21.4.24/
2C0_1066 TCD Transfer Attributes (DMA_TCD3_ATTR) 16 R/W Undefined
980
TCD Minor Byte Count (Minor Loop Mapping Disabled) 21.4.25/
2C0_1068 32 R/W Undefined
(DMA_TCD3_NBYTES_MLNO) 981
TCD Signed Minor Loop Offset (Minor Loop Mapping
21.4.26/
2C0_1068 Enabled and Offset Disabled) 32 R/W Undefined
982
(DMA_TCD3_NBYTES_MLOFFNO)
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 923
Memory map/register definition
DMA memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
TCD Signed Minor Loop Offset (Minor Loop Mapping and 21.4.27/
2C0_1068 32 R/W Undefined
Offset Enabled) (DMA_TCD3_NBYTES_MLOFFYES) 983
TCD Last Source Address Adjustment 21.4.28/
2C0_106C 32 R/W Undefined
(DMA_TCD3_SLAST) 985
21.4.29/
2C0_1070 TCD Destination Address (DMA_TCD3_DADDR) 32 R/W Undefined
985
TCD Signed Destination Address Offset 21.4.30/
2C0_1074 16 R/W Undefined
(DMA_TCD3_DOFF) 986
TCD Current Minor Loop Link, Major Loop Count (Channel 21.4.31/
2C0_1076 16 R/W Undefined
Linking Enabled) (DMA_TCD3_CITER_ELINKYES) 986
21.4.32/
2C0_1076 DMA_TCD3_CITER_ELINKNO 16 R/W Undefined
987
TCD Last Destination Address Adjustment/Scatter Gather 21.4.33/
2C0_1078 32 R/W Undefined
Address (DMA_TCD3_DLASTSGA) 988
21.4.34/
2C0_107C TCD Control and Status (DMA_TCD3_CSR) 16 R/W Undefined
989
TCD Beginning Minor Loop Link, Major Loop Count
21.4.35/
2C0_107E (Channel Linking Enabled) 16 R/W Undefined
991
(DMA_TCD3_BITER_ELINKYES)
TCD Beginning Minor Loop Link, Major Loop Count 21.4.36/
2C0_107E 16 R/W Undefined
(Channel Linking Disabled) (DMA_TCD3_BITER_ELINKNO) 992
21.4.22/
2C0_1080 TCD Source Address (DMA_TCD4_SADDR) 32 R/W Undefined
979
21.4.23/
2C0_1084 TCD Signed Source Address Offset (DMA_TCD4_SOFF) 16 R/W Undefined
980
21.4.24/
2C0_1086 TCD Transfer Attributes (DMA_TCD4_ATTR) 16 R/W Undefined
980
TCD Minor Byte Count (Minor Loop Mapping Disabled) 21.4.25/
2C0_1088 32 R/W Undefined
(DMA_TCD4_NBYTES_MLNO) 981
TCD Signed Minor Loop Offset (Minor Loop Mapping
21.4.26/
2C0_1088 Enabled and Offset Disabled) 32 R/W Undefined
982
(DMA_TCD4_NBYTES_MLOFFNO)
TCD Signed Minor Loop Offset (Minor Loop Mapping and 21.4.27/
2C0_1088 32 R/W Undefined
Offset Enabled) (DMA_TCD4_NBYTES_MLOFFYES) 983
TCD Last Source Address Adjustment 21.4.28/
2C0_108C 32 R/W Undefined
(DMA_TCD4_SLAST) 985
21.4.29/
2C0_1090 TCD Destination Address (DMA_TCD4_DADDR) 32 R/W Undefined
985
TCD Signed Destination Address Offset 21.4.30/
2C0_1094 16 R/W Undefined
(DMA_TCD4_DOFF) 986
TCD Current Minor Loop Link, Major Loop Count (Channel 21.4.31/
2C0_1096 16 R/W Undefined
Linking Enabled) (DMA_TCD4_CITER_ELINKYES) 986
21.4.32/
2C0_1096 DMA_TCD4_CITER_ELINKNO 16 R/W Undefined
987
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
924 NXP Semiconductors
Chapter 21 Enhanced Direct Memory Access (eDMA)
DMA memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
TCD Last Destination Address Adjustment/Scatter Gather 21.4.33/
2C0_1098 32 R/W Undefined
Address (DMA_TCD4_DLASTSGA) 988
21.4.34/
2C0_109C TCD Control and Status (DMA_TCD4_CSR) 16 R/W Undefined
989
TCD Beginning Minor Loop Link, Major Loop Count
21.4.35/
2C0_109E (Channel Linking Enabled) 16 R/W Undefined
991
(DMA_TCD4_BITER_ELINKYES)
TCD Beginning Minor Loop Link, Major Loop Count 21.4.36/
2C0_109E 16 R/W Undefined
(Channel Linking Disabled) (DMA_TCD4_BITER_ELINKNO) 992
21.4.22/
2C0_10A0 TCD Source Address (DMA_TCD5_SADDR) 32 R/W Undefined
979
21.4.23/
2C0_10A4 TCD Signed Source Address Offset (DMA_TCD5_SOFF) 16 R/W Undefined
980
21.4.24/
2C0_10A6 TCD Transfer Attributes (DMA_TCD5_ATTR) 16 R/W Undefined
980
TCD Minor Byte Count (Minor Loop Mapping Disabled) 21.4.25/
2C0_10A8 32 R/W Undefined
(DMA_TCD5_NBYTES_MLNO) 981
TCD Signed Minor Loop Offset (Minor Loop Mapping
21.4.26/
2C0_10A8 Enabled and Offset Disabled) 32 R/W Undefined
982
(DMA_TCD5_NBYTES_MLOFFNO)
TCD Signed Minor Loop Offset (Minor Loop Mapping and 21.4.27/
2C0_10A8 32 R/W Undefined
Offset Enabled) (DMA_TCD5_NBYTES_MLOFFYES) 983
TCD Last Source Address Adjustment 21.4.28/
2C0_10AC 32 R/W Undefined
(DMA_TCD5_SLAST) 985
21.4.29/
2C0_10B0 TCD Destination Address (DMA_TCD5_DADDR) 32 R/W Undefined
985
TCD Signed Destination Address Offset 21.4.30/
2C0_10B4 16 R/W Undefined
(DMA_TCD5_DOFF) 986
TCD Current Minor Loop Link, Major Loop Count (Channel 21.4.31/
2C0_10B6 16 R/W Undefined
Linking Enabled) (DMA_TCD5_CITER_ELINKYES) 986
21.4.32/
2C0_10B6 DMA_TCD5_CITER_ELINKNO 16 R/W Undefined
987
TCD Last Destination Address Adjustment/Scatter Gather 21.4.33/
2C0_10B8 32 R/W Undefined
Address (DMA_TCD5_DLASTSGA) 988
21.4.34/
2C0_10BC TCD Control and Status (DMA_TCD5_CSR) 16 R/W Undefined
989
TCD Beginning Minor Loop Link, Major Loop Count
21.4.35/
2C0_10BE (Channel Linking Enabled) 16 R/W Undefined
991
(DMA_TCD5_BITER_ELINKYES)
TCD Beginning Minor Loop Link, Major Loop Count 21.4.36/
2C0_10BE 16 R/W Undefined
(Channel Linking Disabled) (DMA_TCD5_BITER_ELINKNO) 992
21.4.22/
2C0_10C0 TCD Source Address (DMA_TCD6_SADDR) 32 R/W Undefined
979
21.4.23/
2C0_10C4 TCD Signed Source Address Offset (DMA_TCD6_SOFF) 16 R/W Undefined
980
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 925
Memory map/register definition
DMA memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
21.4.24/
2C0_10C6 TCD Transfer Attributes (DMA_TCD6_ATTR) 16 R/W Undefined
980
TCD Minor Byte Count (Minor Loop Mapping Disabled) 21.4.25/
2C0_10C8 32 R/W Undefined
(DMA_TCD6_NBYTES_MLNO) 981
TCD Signed Minor Loop Offset (Minor Loop Mapping
21.4.26/
2C0_10C8 Enabled and Offset Disabled) 32 R/W Undefined
982
(DMA_TCD6_NBYTES_MLOFFNO)
TCD Signed Minor Loop Offset (Minor Loop Mapping and 21.4.27/
2C0_10C8 32 R/W Undefined
Offset Enabled) (DMA_TCD6_NBYTES_MLOFFYES) 983
TCD Last Source Address Adjustment 21.4.28/
2C0_10CC 32 R/W Undefined
(DMA_TCD6_SLAST) 985
21.4.29/
2C0_10D0 TCD Destination Address (DMA_TCD6_DADDR) 32 R/W Undefined
985
TCD Signed Destination Address Offset 21.4.30/
2C0_10D4 16 R/W Undefined
(DMA_TCD6_DOFF) 986
TCD Current Minor Loop Link, Major Loop Count (Channel 21.4.31/
2C0_10D6 16 R/W Undefined
Linking Enabled) (DMA_TCD6_CITER_ELINKYES) 986
21.4.32/
2C0_10D6 DMA_TCD6_CITER_ELINKNO 16 R/W Undefined
987
TCD Last Destination Address Adjustment/Scatter Gather 21.4.33/
2C0_10D8 32 R/W Undefined
Address (DMA_TCD6_DLASTSGA) 988
21.4.34/
2C0_10DC TCD Control and Status (DMA_TCD6_CSR) 16 R/W Undefined
989
TCD Beginning Minor Loop Link, Major Loop Count
21.4.35/
2C0_10DE (Channel Linking Enabled) 16 R/W Undefined
991
(DMA_TCD6_BITER_ELINKYES)
TCD Beginning Minor Loop Link, Major Loop Count 21.4.36/
2C0_10DE 16 R/W Undefined
(Channel Linking Disabled) (DMA_TCD6_BITER_ELINKNO) 992
21.4.22/
2C0_10E0 TCD Source Address (DMA_TCD7_SADDR) 32 R/W Undefined
979
21.4.23/
2C0_10E4 TCD Signed Source Address Offset (DMA_TCD7_SOFF) 16 R/W Undefined
980
21.4.24/
2C0_10E6 TCD Transfer Attributes (DMA_TCD7_ATTR) 16 R/W Undefined
980
TCD Minor Byte Count (Minor Loop Mapping Disabled) 21.4.25/
2C0_10E8 32 R/W Undefined
(DMA_TCD7_NBYTES_MLNO) 981
TCD Signed Minor Loop Offset (Minor Loop Mapping
21.4.26/
2C0_10E8 Enabled and Offset Disabled) 32 R/W Undefined
982
(DMA_TCD7_NBYTES_MLOFFNO)
TCD Signed Minor Loop Offset (Minor Loop Mapping and 21.4.27/
2C0_10E8 32 R/W Undefined
Offset Enabled) (DMA_TCD7_NBYTES_MLOFFYES) 983
TCD Last Source Address Adjustment 21.4.28/
2C0_10EC 32 R/W Undefined
(DMA_TCD7_SLAST) 985
21.4.29/
2C0_10F0 TCD Destination Address (DMA_TCD7_DADDR) 32 R/W Undefined
985
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
926 NXP Semiconductors
Chapter 21 Enhanced Direct Memory Access (eDMA)
DMA memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
TCD Signed Destination Address Offset 21.4.30/
2C0_10F4 16 R/W Undefined
(DMA_TCD7_DOFF) 986
TCD Current Minor Loop Link, Major Loop Count (Channel 21.4.31/
2C0_10F6 16 R/W Undefined
Linking Enabled) (DMA_TCD7_CITER_ELINKYES) 986
21.4.32/
2C0_10F6 DMA_TCD7_CITER_ELINKNO 16 R/W Undefined
987
TCD Last Destination Address Adjustment/Scatter Gather 21.4.33/
2C0_10F8 32 R/W Undefined
Address (DMA_TCD7_DLASTSGA) 988
21.4.34/
2C0_10FC TCD Control and Status (DMA_TCD7_CSR) 16 R/W Undefined
989
TCD Beginning Minor Loop Link, Major Loop Count
21.4.35/
2C0_10FE (Channel Linking Enabled) 16 R/W Undefined
991
(DMA_TCD7_BITER_ELINKYES)
TCD Beginning Minor Loop Link, Major Loop Count 21.4.36/
2C0_10FE 16 R/W Undefined
(Channel Linking Disabled) (DMA_TCD7_BITER_ELINKNO) 992
21.4.22/
2C0_1100 TCD Source Address (DMA_TCD8_SADDR) 32 R/W Undefined
979
21.4.23/
2C0_1104 TCD Signed Source Address Offset (DMA_TCD8_SOFF) 16 R/W Undefined
980
21.4.24/
2C0_1106 TCD Transfer Attributes (DMA_TCD8_ATTR) 16 R/W Undefined
980
TCD Minor Byte Count (Minor Loop Mapping Disabled) 21.4.25/
2C0_1108 32 R/W Undefined
(DMA_TCD8_NBYTES_MLNO) 981
TCD Signed Minor Loop Offset (Minor Loop Mapping
21.4.26/
2C0_1108 Enabled and Offset Disabled) 32 R/W Undefined
982
(DMA_TCD8_NBYTES_MLOFFNO)
TCD Signed Minor Loop Offset (Minor Loop Mapping and 21.4.27/
2C0_1108 32 R/W Undefined
Offset Enabled) (DMA_TCD8_NBYTES_MLOFFYES) 983
TCD Last Source Address Adjustment 21.4.28/
2C0_110C 32 R/W Undefined
(DMA_TCD8_SLAST) 985
21.4.29/
2C0_1110 TCD Destination Address (DMA_TCD8_DADDR) 32 R/W Undefined
985
TCD Signed Destination Address Offset 21.4.30/
2C0_1114 16 R/W Undefined
(DMA_TCD8_DOFF) 986
TCD Current Minor Loop Link, Major Loop Count (Channel 21.4.31/
2C0_1116 16 R/W Undefined
Linking Enabled) (DMA_TCD8_CITER_ELINKYES) 986
21.4.32/
2C0_1116 DMA_TCD8_CITER_ELINKNO 16 R/W Undefined
987
TCD Last Destination Address Adjustment/Scatter Gather 21.4.33/
2C0_1118 32 R/W Undefined
Address (DMA_TCD8_DLASTSGA) 988
21.4.34/
2C0_111C TCD Control and Status (DMA_TCD8_CSR) 16 R/W Undefined
989
TCD Beginning Minor Loop Link, Major Loop Count
21.4.35/
2C0_111E (Channel Linking Enabled) 16 R/W Undefined
991
(DMA_TCD8_BITER_ELINKYES)
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 927
Memory map/register definition
DMA memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
TCD Beginning Minor Loop Link, Major Loop Count 21.4.36/
2C0_111E 16 R/W Undefined
(Channel Linking Disabled) (DMA_TCD8_BITER_ELINKNO) 992
21.4.22/
2C0_1120 TCD Source Address (DMA_TCD9_SADDR) 32 R/W Undefined
979
21.4.23/
2C0_1124 TCD Signed Source Address Offset (DMA_TCD9_SOFF) 16 R/W Undefined
980
21.4.24/
2C0_1126 TCD Transfer Attributes (DMA_TCD9_ATTR) 16 R/W Undefined
980
TCD Minor Byte Count (Minor Loop Mapping Disabled) 21.4.25/
2C0_1128 32 R/W Undefined
(DMA_TCD9_NBYTES_MLNO) 981
TCD Signed Minor Loop Offset (Minor Loop Mapping
21.4.26/
2C0_1128 Enabled and Offset Disabled) 32 R/W Undefined
982
(DMA_TCD9_NBYTES_MLOFFNO)
TCD Signed Minor Loop Offset (Minor Loop Mapping and 21.4.27/
2C0_1128 32 R/W Undefined
Offset Enabled) (DMA_TCD9_NBYTES_MLOFFYES) 983
TCD Last Source Address Adjustment 21.4.28/
2C0_112C 32 R/W Undefined
(DMA_TCD9_SLAST) 985
21.4.29/
2C0_1130 TCD Destination Address (DMA_TCD9_DADDR) 32 R/W Undefined
985
TCD Signed Destination Address Offset 21.4.30/
2C0_1134 16 R/W Undefined
(DMA_TCD9_DOFF) 986
TCD Current Minor Loop Link, Major Loop Count (Channel 21.4.31/
2C0_1136 16 R/W Undefined
Linking Enabled) (DMA_TCD9_CITER_ELINKYES) 986
21.4.32/
2C0_1136 DMA_TCD9_CITER_ELINKNO 16 R/W Undefined
987
TCD Last Destination Address Adjustment/Scatter Gather 21.4.33/
2C0_1138 32 R/W Undefined
Address (DMA_TCD9_DLASTSGA) 988
21.4.34/
2C0_113C TCD Control and Status (DMA_TCD9_CSR) 16 R/W Undefined
989
TCD Beginning Minor Loop Link, Major Loop Count
21.4.35/
2C0_113E (Channel Linking Enabled) 16 R/W Undefined
991
(DMA_TCD9_BITER_ELINKYES)
TCD Beginning Minor Loop Link, Major Loop Count 21.4.36/
2C0_113E 16 R/W Undefined
(Channel Linking Disabled) (DMA_TCD9_BITER_ELINKNO) 992
21.4.22/
2C0_1140 TCD Source Address (DMA_TCD10_SADDR) 32 R/W Undefined
979
21.4.23/
2C0_1144 TCD Signed Source Address Offset (DMA_TCD10_SOFF) 16 R/W Undefined
980
21.4.24/
2C0_1146 TCD Transfer Attributes (DMA_TCD10_ATTR) 16 R/W Undefined
980
TCD Minor Byte Count (Minor Loop Mapping Disabled) 21.4.25/
2C0_1148 32 R/W Undefined
(DMA_TCD10_NBYTES_MLNO) 981
TCD Signed Minor Loop Offset (Minor Loop Mapping
21.4.26/
2C0_1148 Enabled and Offset Disabled) 32 R/W Undefined
982
(DMA_TCD10_NBYTES_MLOFFNO)
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
928 NXP Semiconductors
Chapter 21 Enhanced Direct Memory Access (eDMA)
DMA memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
TCD Signed Minor Loop Offset (Minor Loop Mapping and 21.4.27/
2C0_1148 32 R/W Undefined
Offset Enabled) (DMA_TCD10_NBYTES_MLOFFYES) 983
TCD Last Source Address Adjustment 21.4.28/
2C0_114C 32 R/W Undefined
(DMA_TCD10_SLAST) 985
21.4.29/
2C0_1150 TCD Destination Address (DMA_TCD10_DADDR) 32 R/W Undefined
985
TCD Signed Destination Address Offset 21.4.30/
2C0_1154 16 R/W Undefined
(DMA_TCD10_DOFF) 986
TCD Current Minor Loop Link, Major Loop Count (Channel 21.4.31/
2C0_1156 16 R/W Undefined
Linking Enabled) (DMA_TCD10_CITER_ELINKYES) 986
21.4.32/
2C0_1156 DMA_TCD10_CITER_ELINKNO 16 R/W Undefined
987
TCD Last Destination Address Adjustment/Scatter Gather 21.4.33/
2C0_1158 32 R/W Undefined
Address (DMA_TCD10_DLASTSGA) 988
21.4.34/
2C0_115C TCD Control and Status (DMA_TCD10_CSR) 16 R/W Undefined
989
TCD Beginning Minor Loop Link, Major Loop Count
21.4.35/
2C0_115E (Channel Linking Enabled) 16 R/W Undefined
991
(DMA_TCD10_BITER_ELINKYES)
TCD Beginning Minor Loop Link, Major Loop Count
21.4.36/
2C0_115E (Channel Linking Disabled) 16 R/W Undefined
992
(DMA_TCD10_BITER_ELINKNO)
21.4.22/
2C0_1160 TCD Source Address (DMA_TCD11_SADDR) 32 R/W Undefined
979
21.4.23/
2C0_1164 TCD Signed Source Address Offset (DMA_TCD11_SOFF) 16 R/W Undefined
980
21.4.24/
2C0_1166 TCD Transfer Attributes (DMA_TCD11_ATTR) 16 R/W Undefined
980
TCD Minor Byte Count (Minor Loop Mapping Disabled) 21.4.25/
2C0_1168 32 R/W Undefined
(DMA_TCD11_NBYTES_MLNO) 981
TCD Signed Minor Loop Offset (Minor Loop Mapping
21.4.26/
2C0_1168 Enabled and Offset Disabled) 32 R/W Undefined
982
(DMA_TCD11_NBYTES_MLOFFNO)
TCD Signed Minor Loop Offset (Minor Loop Mapping and 21.4.27/
2C0_1168 32 R/W Undefined
Offset Enabled) (DMA_TCD11_NBYTES_MLOFFYES) 983
TCD Last Source Address Adjustment 21.4.28/
2C0_116C 32 R/W Undefined
(DMA_TCD11_SLAST) 985
21.4.29/
2C0_1170 TCD Destination Address (DMA_TCD11_DADDR) 32 R/W Undefined
985
TCD Signed Destination Address Offset 21.4.30/
2C0_1174 16 R/W Undefined
(DMA_TCD11_DOFF) 986
TCD Current Minor Loop Link, Major Loop Count (Channel 21.4.31/
2C0_1176 16 R/W Undefined
Linking Enabled) (DMA_TCD11_CITER_ELINKYES) 986
21.4.32/
2C0_1176 DMA_TCD11_CITER_ELINKNO 16 R/W Undefined
987
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 929
Memory map/register definition
DMA memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
TCD Last Destination Address Adjustment/Scatter Gather 21.4.33/
2C0_1178 32 R/W Undefined
Address (DMA_TCD11_DLASTSGA) 988
21.4.34/
2C0_117C TCD Control and Status (DMA_TCD11_CSR) 16 R/W Undefined
989
TCD Beginning Minor Loop Link, Major Loop Count
21.4.35/
2C0_117E (Channel Linking Enabled) 16 R/W Undefined
991
(DMA_TCD11_BITER_ELINKYES)
TCD Beginning Minor Loop Link, Major Loop Count
21.4.36/
2C0_117E (Channel Linking Disabled) 16 R/W Undefined
992
(DMA_TCD11_BITER_ELINKNO)
21.4.22/
2C0_1180 TCD Source Address (DMA_TCD12_SADDR) 32 R/W Undefined
979
21.4.23/
2C0_1184 TCD Signed Source Address Offset (DMA_TCD12_SOFF) 16 R/W Undefined
980
21.4.24/
2C0_1186 TCD Transfer Attributes (DMA_TCD12_ATTR) 16 R/W Undefined
980
TCD Minor Byte Count (Minor Loop Mapping Disabled) 21.4.25/
2C0_1188 32 R/W Undefined
(DMA_TCD12_NBYTES_MLNO) 981
TCD Signed Minor Loop Offset (Minor Loop Mapping
21.4.26/
2C0_1188 Enabled and Offset Disabled) 32 R/W Undefined
982
(DMA_TCD12_NBYTES_MLOFFNO)
TCD Signed Minor Loop Offset (Minor Loop Mapping and 21.4.27/
2C0_1188 32 R/W Undefined
Offset Enabled) (DMA_TCD12_NBYTES_MLOFFYES) 983
TCD Last Source Address Adjustment 21.4.28/
2C0_118C 32 R/W Undefined
(DMA_TCD12_SLAST) 985
21.4.29/
2C0_1190 TCD Destination Address (DMA_TCD12_DADDR) 32 R/W Undefined
985
TCD Signed Destination Address Offset 21.4.30/
2C0_1194 16 R/W Undefined
(DMA_TCD12_DOFF) 986
TCD Current Minor Loop Link, Major Loop Count (Channel 21.4.31/
2C0_1196 16 R/W Undefined
Linking Enabled) (DMA_TCD12_CITER_ELINKYES) 986
21.4.32/
2C0_1196 DMA_TCD12_CITER_ELINKNO 16 R/W Undefined
987
TCD Last Destination Address Adjustment/Scatter Gather 21.4.33/
2C0_1198 32 R/W Undefined
Address (DMA_TCD12_DLASTSGA) 988
21.4.34/
2C0_119C TCD Control and Status (DMA_TCD12_CSR) 16 R/W Undefined
989
TCD Beginning Minor Loop Link, Major Loop Count
21.4.35/
2C0_119E (Channel Linking Enabled) 16 R/W Undefined
991
(DMA_TCD12_BITER_ELINKYES)
TCD Beginning Minor Loop Link, Major Loop Count
21.4.36/
2C0_119E (Channel Linking Disabled) 16 R/W Undefined
992
(DMA_TCD12_BITER_ELINKNO)
21.4.22/
2C0_11A0 TCD Source Address (DMA_TCD13_SADDR) 32 R/W Undefined
979
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
930 NXP Semiconductors
Chapter 21 Enhanced Direct Memory Access (eDMA)
DMA memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
21.4.23/
2C0_11A4 TCD Signed Source Address Offset (DMA_TCD13_SOFF) 16 R/W Undefined
980
21.4.24/
2C0_11A6 TCD Transfer Attributes (DMA_TCD13_ATTR) 16 R/W Undefined
980
TCD Minor Byte Count (Minor Loop Mapping Disabled) 21.4.25/
2C0_11A8 32 R/W Undefined
(DMA_TCD13_NBYTES_MLNO) 981
TCD Signed Minor Loop Offset (Minor Loop Mapping
21.4.26/
2C0_11A8 Enabled and Offset Disabled) 32 R/W Undefined
982
(DMA_TCD13_NBYTES_MLOFFNO)
TCD Signed Minor Loop Offset (Minor Loop Mapping and 21.4.27/
2C0_11A8 32 R/W Undefined
Offset Enabled) (DMA_TCD13_NBYTES_MLOFFYES) 983
TCD Last Source Address Adjustment 21.4.28/
2C0_11AC 32 R/W Undefined
(DMA_TCD13_SLAST) 985
21.4.29/
2C0_11B0 TCD Destination Address (DMA_TCD13_DADDR) 32 R/W Undefined
985
TCD Signed Destination Address Offset 21.4.30/
2C0_11B4 16 R/W Undefined
(DMA_TCD13_DOFF) 986
TCD Current Minor Loop Link, Major Loop Count (Channel 21.4.31/
2C0_11B6 16 R/W Undefined
Linking Enabled) (DMA_TCD13_CITER_ELINKYES) 986
21.4.32/
2C0_11B6 DMA_TCD13_CITER_ELINKNO 16 R/W Undefined
987
TCD Last Destination Address Adjustment/Scatter Gather 21.4.33/
2C0_11B8 32 R/W Undefined
Address (DMA_TCD13_DLASTSGA) 988
21.4.34/
2C0_11BC TCD Control and Status (DMA_TCD13_CSR) 16 R/W Undefined
989
TCD Beginning Minor Loop Link, Major Loop Count
21.4.35/
2C0_11BE (Channel Linking Enabled) 16 R/W Undefined
991
(DMA_TCD13_BITER_ELINKYES)
TCD Beginning Minor Loop Link, Major Loop Count
21.4.36/
2C0_11BE (Channel Linking Disabled) 16 R/W Undefined
992
(DMA_TCD13_BITER_ELINKNO)
21.4.22/
2C0_11C0 TCD Source Address (DMA_TCD14_SADDR) 32 R/W Undefined
979
21.4.23/
2C0_11C4 TCD Signed Source Address Offset (DMA_TCD14_SOFF) 16 R/W Undefined
980
21.4.24/
2C0_11C6 TCD Transfer Attributes (DMA_TCD14_ATTR) 16 R/W Undefined
980
TCD Minor Byte Count (Minor Loop Mapping Disabled) 21.4.25/
2C0_11C8 32 R/W Undefined
(DMA_TCD14_NBYTES_MLNO) 981
TCD Signed Minor Loop Offset (Minor Loop Mapping
21.4.26/
2C0_11C8 Enabled and Offset Disabled) 32 R/W Undefined
982
(DMA_TCD14_NBYTES_MLOFFNO)
TCD Signed Minor Loop Offset (Minor Loop Mapping and 21.4.27/
2C0_11C8 32 R/W Undefined
Offset Enabled) (DMA_TCD14_NBYTES_MLOFFYES) 983
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 931
Memory map/register definition
DMA memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
TCD Last Source Address Adjustment 21.4.28/
2C0_11CC 32 R/W Undefined
(DMA_TCD14_SLAST) 985
21.4.29/
2C0_11D0 TCD Destination Address (DMA_TCD14_DADDR) 32 R/W Undefined
985
TCD Signed Destination Address Offset 21.4.30/
2C0_11D4 16 R/W Undefined
(DMA_TCD14_DOFF) 986
TCD Current Minor Loop Link, Major Loop Count (Channel 21.4.31/
2C0_11D6 16 R/W Undefined
Linking Enabled) (DMA_TCD14_CITER_ELINKYES) 986
21.4.32/
2C0_11D6 DMA_TCD14_CITER_ELINKNO 16 R/W Undefined
987
TCD Last Destination Address Adjustment/Scatter Gather 21.4.33/
2C0_11D8 32 R/W Undefined
Address (DMA_TCD14_DLASTSGA) 988
21.4.34/
2C0_11DC TCD Control and Status (DMA_TCD14_CSR) 16 R/W Undefined
989
TCD Beginning Minor Loop Link, Major Loop Count
21.4.35/
2C0_11DE (Channel Linking Enabled) 16 R/W Undefined
991
(DMA_TCD14_BITER_ELINKYES)
TCD Beginning Minor Loop Link, Major Loop Count
21.4.36/
2C0_11DE (Channel Linking Disabled) 16 R/W Undefined
992
(DMA_TCD14_BITER_ELINKNO)
21.4.22/
2C0_11E0 TCD Source Address (DMA_TCD15_SADDR) 32 R/W Undefined
979
21.4.23/
2C0_11E4 TCD Signed Source Address Offset (DMA_TCD15_SOFF) 16 R/W Undefined
980
21.4.24/
2C0_11E6 TCD Transfer Attributes (DMA_TCD15_ATTR) 16 R/W Undefined
980
TCD Minor Byte Count (Minor Loop Mapping Disabled) 21.4.25/
2C0_11E8 32 R/W Undefined
(DMA_TCD15_NBYTES_MLNO) 981
TCD Signed Minor Loop Offset (Minor Loop Mapping
21.4.26/
2C0_11E8 Enabled and Offset Disabled) 32 R/W Undefined
982
(DMA_TCD15_NBYTES_MLOFFNO)
TCD Signed Minor Loop Offset (Minor Loop Mapping and 21.4.27/
2C0_11E8 32 R/W Undefined
Offset Enabled) (DMA_TCD15_NBYTES_MLOFFYES) 983
TCD Last Source Address Adjustment 21.4.28/
2C0_11EC 32 R/W Undefined
(DMA_TCD15_SLAST) 985
21.4.29/
2C0_11F0 TCD Destination Address (DMA_TCD15_DADDR) 32 R/W Undefined
985
TCD Signed Destination Address Offset 21.4.30/
2C0_11F4 16 R/W Undefined
(DMA_TCD15_DOFF) 986
TCD Current Minor Loop Link, Major Loop Count (Channel 21.4.31/
2C0_11F6 16 R/W Undefined
Linking Enabled) (DMA_TCD15_CITER_ELINKYES) 986
21.4.32/
2C0_11F6 DMA_TCD15_CITER_ELINKNO 16 R/W Undefined
987
TCD Last Destination Address Adjustment/Scatter Gather 21.4.33/
2C0_11F8 32 R/W Undefined
Address (DMA_TCD15_DLASTSGA) 988
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
932 NXP Semiconductors
Chapter 21 Enhanced Direct Memory Access (eDMA)
DMA memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
21.4.34/
2C0_11FC TCD Control and Status (DMA_TCD15_CSR) 16 R/W Undefined
989
TCD Beginning Minor Loop Link, Major Loop Count
21.4.35/
2C0_11FE (Channel Linking Enabled) 16 R/W Undefined
991
(DMA_TCD15_BITER_ELINKYES)
TCD Beginning Minor Loop Link, Major Loop Count
21.4.36/
2C0_11FE (Channel Linking Disabled) 16 R/W Undefined
992
(DMA_TCD15_BITER_ELINKNO)
21.4.22/
2C0_1200 TCD Source Address (DMA_TCD16_SADDR) 32 R/W Undefined
979
21.4.23/
2C0_1204 TCD Signed Source Address Offset (DMA_TCD16_SOFF) 16 R/W Undefined
980
21.4.24/
2C0_1206 TCD Transfer Attributes (DMA_TCD16_ATTR) 16 R/W Undefined
980
TCD Minor Byte Count (Minor Loop Mapping Disabled) 21.4.25/
2C0_1208 32 R/W Undefined
(DMA_TCD16_NBYTES_MLNO) 981
TCD Signed Minor Loop Offset (Minor Loop Mapping
21.4.26/
2C0_1208 Enabled and Offset Disabled) 32 R/W Undefined
982
(DMA_TCD16_NBYTES_MLOFFNO)
TCD Signed Minor Loop Offset (Minor Loop Mapping and 21.4.27/
2C0_1208 32 R/W Undefined
Offset Enabled) (DMA_TCD16_NBYTES_MLOFFYES) 983
TCD Last Source Address Adjustment 21.4.28/
2C0_120C 32 R/W Undefined
(DMA_TCD16_SLAST) 985
21.4.29/
2C0_1210 TCD Destination Address (DMA_TCD16_DADDR) 32 R/W Undefined
985
TCD Signed Destination Address Offset 21.4.30/
2C0_1214 16 R/W Undefined
(DMA_TCD16_DOFF) 986
TCD Current Minor Loop Link, Major Loop Count (Channel 21.4.31/
2C0_1216 16 R/W Undefined
Linking Enabled) (DMA_TCD16_CITER_ELINKYES) 986
21.4.32/
2C0_1216 DMA_TCD16_CITER_ELINKNO 16 R/W Undefined
987
TCD Last Destination Address Adjustment/Scatter Gather 21.4.33/
2C0_1218 32 R/W Undefined
Address (DMA_TCD16_DLASTSGA) 988
21.4.34/
2C0_121C TCD Control and Status (DMA_TCD16_CSR) 16 R/W Undefined
989
TCD Beginning Minor Loop Link, Major Loop Count
21.4.35/
2C0_121E (Channel Linking Enabled) 16 R/W Undefined
991
(DMA_TCD16_BITER_ELINKYES)
TCD Beginning Minor Loop Link, Major Loop Count
21.4.36/
2C0_121E (Channel Linking Disabled) 16 R/W Undefined
992
(DMA_TCD16_BITER_ELINKNO)
21.4.22/
2C0_1220 TCD Source Address (DMA_TCD17_SADDR) 32 R/W Undefined
979
21.4.23/
2C0_1224 TCD Signed Source Address Offset (DMA_TCD17_SOFF) 16 R/W Undefined
980
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 933
Memory map/register definition
DMA memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
21.4.24/
2C0_1226 TCD Transfer Attributes (DMA_TCD17_ATTR) 16 R/W Undefined
980
TCD Minor Byte Count (Minor Loop Mapping Disabled) 21.4.25/
2C0_1228 32 R/W Undefined
(DMA_TCD17_NBYTES_MLNO) 981
TCD Signed Minor Loop Offset (Minor Loop Mapping
21.4.26/
2C0_1228 Enabled and Offset Disabled) 32 R/W Undefined
982
(DMA_TCD17_NBYTES_MLOFFNO)
TCD Signed Minor Loop Offset (Minor Loop Mapping and 21.4.27/
2C0_1228 32 R/W Undefined
Offset Enabled) (DMA_TCD17_NBYTES_MLOFFYES) 983
TCD Last Source Address Adjustment 21.4.28/
2C0_122C 32 R/W Undefined
(DMA_TCD17_SLAST) 985
21.4.29/
2C0_1230 TCD Destination Address (DMA_TCD17_DADDR) 32 R/W Undefined
985
TCD Signed Destination Address Offset 21.4.30/
2C0_1234 16 R/W Undefined
(DMA_TCD17_DOFF) 986
TCD Current Minor Loop Link, Major Loop Count (Channel 21.4.31/
2C0_1236 16 R/W Undefined
Linking Enabled) (DMA_TCD17_CITER_ELINKYES) 986
21.4.32/
2C0_1236 DMA_TCD17_CITER_ELINKNO 16 R/W Undefined
987
TCD Last Destination Address Adjustment/Scatter Gather 21.4.33/
2C0_1238 32 R/W Undefined
Address (DMA_TCD17_DLASTSGA) 988
21.4.34/
2C0_123C TCD Control and Status (DMA_TCD17_CSR) 16 R/W Undefined
989
TCD Beginning Minor Loop Link, Major Loop Count
21.4.35/
2C0_123E (Channel Linking Enabled) 16 R/W Undefined
991
(DMA_TCD17_BITER_ELINKYES)
TCD Beginning Minor Loop Link, Major Loop Count
21.4.36/
2C0_123E (Channel Linking Disabled) 16 R/W Undefined
992
(DMA_TCD17_BITER_ELINKNO)
21.4.22/
2C0_1240 TCD Source Address (DMA_TCD18_SADDR) 32 R/W Undefined
979
21.4.23/
2C0_1244 TCD Signed Source Address Offset (DMA_TCD18_SOFF) 16 R/W Undefined
980
21.4.24/
2C0_1246 TCD Transfer Attributes (DMA_TCD18_ATTR) 16 R/W Undefined
980
TCD Minor Byte Count (Minor Loop Mapping Disabled) 21.4.25/
2C0_1248 32 R/W Undefined
(DMA_TCD18_NBYTES_MLNO) 981
TCD Signed Minor Loop Offset (Minor Loop Mapping
21.4.26/
2C0_1248 Enabled and Offset Disabled) 32 R/W Undefined
982
(DMA_TCD18_NBYTES_MLOFFNO)
TCD Signed Minor Loop Offset (Minor Loop Mapping and 21.4.27/
2C0_1248 32 R/W Undefined
Offset Enabled) (DMA_TCD18_NBYTES_MLOFFYES) 983
TCD Last Source Address Adjustment 21.4.28/
2C0_124C 32 R/W Undefined
(DMA_TCD18_SLAST) 985
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
934 NXP Semiconductors
Chapter 21 Enhanced Direct Memory Access (eDMA)
DMA memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
21.4.29/
2C0_1250 TCD Destination Address (DMA_TCD18_DADDR) 32 R/W Undefined
985
TCD Signed Destination Address Offset 21.4.30/
2C0_1254 16 R/W Undefined
(DMA_TCD18_DOFF) 986
TCD Current Minor Loop Link, Major Loop Count (Channel 21.4.31/
2C0_1256 16 R/W Undefined
Linking Enabled) (DMA_TCD18_CITER_ELINKYES) 986
21.4.32/
2C0_1256 DMA_TCD18_CITER_ELINKNO 16 R/W Undefined
987
TCD Last Destination Address Adjustment/Scatter Gather 21.4.33/
2C0_1258 32 R/W Undefined
Address (DMA_TCD18_DLASTSGA) 988
21.4.34/
2C0_125C TCD Control and Status (DMA_TCD18_CSR) 16 R/W Undefined
989
TCD Beginning Minor Loop Link, Major Loop Count
21.4.35/
2C0_125E (Channel Linking Enabled) 16 R/W Undefined
991
(DMA_TCD18_BITER_ELINKYES)
TCD Beginning Minor Loop Link, Major Loop Count
21.4.36/
2C0_125E (Channel Linking Disabled) 16 R/W Undefined
992
(DMA_TCD18_BITER_ELINKNO)
21.4.22/
2C0_1260 TCD Source Address (DMA_TCD19_SADDR) 32 R/W Undefined
979
21.4.23/
2C0_1264 TCD Signed Source Address Offset (DMA_TCD19_SOFF) 16 R/W Undefined
980
21.4.24/
2C0_1266 TCD Transfer Attributes (DMA_TCD19_ATTR) 16 R/W Undefined
980
TCD Minor Byte Count (Minor Loop Mapping Disabled) 21.4.25/
2C0_1268 32 R/W Undefined
(DMA_TCD19_NBYTES_MLNO) 981
TCD Signed Minor Loop Offset (Minor Loop Mapping
21.4.26/
2C0_1268 Enabled and Offset Disabled) 32 R/W Undefined
982
(DMA_TCD19_NBYTES_MLOFFNO)
TCD Signed Minor Loop Offset (Minor Loop Mapping and 21.4.27/
2C0_1268 32 R/W Undefined
Offset Enabled) (DMA_TCD19_NBYTES_MLOFFYES) 983
TCD Last Source Address Adjustment 21.4.28/
2C0_126C 32 R/W Undefined
(DMA_TCD19_SLAST) 985
21.4.29/
2C0_1270 TCD Destination Address (DMA_TCD19_DADDR) 32 R/W Undefined
985
TCD Signed Destination Address Offset 21.4.30/
2C0_1274 16 R/W Undefined
(DMA_TCD19_DOFF) 986
TCD Current Minor Loop Link, Major Loop Count (Channel 21.4.31/
2C0_1276 16 R/W Undefined
Linking Enabled) (DMA_TCD19_CITER_ELINKYES) 986
21.4.32/
2C0_1276 DMA_TCD19_CITER_ELINKNO 16 R/W Undefined
987
TCD Last Destination Address Adjustment/Scatter Gather 21.4.33/
2C0_1278 32 R/W Undefined
Address (DMA_TCD19_DLASTSGA) 988
21.4.34/
2C0_127C TCD Control and Status (DMA_TCD19_CSR) 16 R/W Undefined
989
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 935
Memory map/register definition
DMA memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
TCD Beginning Minor Loop Link, Major Loop Count
21.4.35/
2C0_127E (Channel Linking Enabled) 16 R/W Undefined
991
(DMA_TCD19_BITER_ELINKYES)
TCD Beginning Minor Loop Link, Major Loop Count
21.4.36/
2C0_127E (Channel Linking Disabled) 16 R/W Undefined
992
(DMA_TCD19_BITER_ELINKNO)
21.4.22/
2C0_1280 TCD Source Address (DMA_TCD20_SADDR) 32 R/W Undefined
979
21.4.23/
2C0_1284 TCD Signed Source Address Offset (DMA_TCD20_SOFF) 16 R/W Undefined
980
21.4.24/
2C0_1286 TCD Transfer Attributes (DMA_TCD20_ATTR) 16 R/W Undefined
980
TCD Minor Byte Count (Minor Loop Mapping Disabled) 21.4.25/
2C0_1288 32 R/W Undefined
(DMA_TCD20_NBYTES_MLNO) 981
TCD Signed Minor Loop Offset (Minor Loop Mapping
21.4.26/
2C0_1288 Enabled and Offset Disabled) 32 R/W Undefined
982
(DMA_TCD20_NBYTES_MLOFFNO)
TCD Signed Minor Loop Offset (Minor Loop Mapping and 21.4.27/
2C0_1288 32 R/W Undefined
Offset Enabled) (DMA_TCD20_NBYTES_MLOFFYES) 983
TCD Last Source Address Adjustment 21.4.28/
2C0_128C 32 R/W Undefined
(DMA_TCD20_SLAST) 985
21.4.29/
2C0_1290 TCD Destination Address (DMA_TCD20_DADDR) 32 R/W Undefined
985
TCD Signed Destination Address Offset 21.4.30/
2C0_1294 16 R/W Undefined
(DMA_TCD20_DOFF) 986
TCD Current Minor Loop Link, Major Loop Count (Channel 21.4.31/
2C0_1296 16 R/W Undefined
Linking Enabled) (DMA_TCD20_CITER_ELINKYES) 986
21.4.32/
2C0_1296 DMA_TCD20_CITER_ELINKNO 16 R/W Undefined
987
TCD Last Destination Address Adjustment/Scatter Gather 21.4.33/
2C0_1298 32 R/W Undefined
Address (DMA_TCD20_DLASTSGA) 988
21.4.34/
2C0_129C TCD Control and Status (DMA_TCD20_CSR) 16 R/W Undefined
989
TCD Beginning Minor Loop Link, Major Loop Count
21.4.35/
2C0_129E (Channel Linking Enabled) 16 R/W Undefined
991
(DMA_TCD20_BITER_ELINKYES)
TCD Beginning Minor Loop Link, Major Loop Count
21.4.36/
2C0_129E (Channel Linking Disabled) 16 R/W Undefined
992
(DMA_TCD20_BITER_ELINKNO)
21.4.22/
2C0_12A0 TCD Source Address (DMA_TCD21_SADDR) 32 R/W Undefined
979
21.4.23/
2C0_12A4 TCD Signed Source Address Offset (DMA_TCD21_SOFF) 16 R/W Undefined
980
21.4.24/
2C0_12A6 TCD Transfer Attributes (DMA_TCD21_ATTR) 16 R/W Undefined
980
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
936 NXP Semiconductors
Chapter 21 Enhanced Direct Memory Access (eDMA)
DMA memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
TCD Minor Byte Count (Minor Loop Mapping Disabled) 21.4.25/
2C0_12A8 32 R/W Undefined
(DMA_TCD21_NBYTES_MLNO) 981
TCD Signed Minor Loop Offset (Minor Loop Mapping
21.4.26/
2C0_12A8 Enabled and Offset Disabled) 32 R/W Undefined
982
(DMA_TCD21_NBYTES_MLOFFNO)
TCD Signed Minor Loop Offset (Minor Loop Mapping and 21.4.27/
2C0_12A8 32 R/W Undefined
Offset Enabled) (DMA_TCD21_NBYTES_MLOFFYES) 983
TCD Last Source Address Adjustment 21.4.28/
2C0_12AC 32 R/W Undefined
(DMA_TCD21_SLAST) 985
21.4.29/
2C0_12B0 TCD Destination Address (DMA_TCD21_DADDR) 32 R/W Undefined
985
TCD Signed Destination Address Offset 21.4.30/
2C0_12B4 16 R/W Undefined
(DMA_TCD21_DOFF) 986
TCD Current Minor Loop Link, Major Loop Count (Channel 21.4.31/
2C0_12B6 16 R/W Undefined
Linking Enabled) (DMA_TCD21_CITER_ELINKYES) 986
21.4.32/
2C0_12B6 DMA_TCD21_CITER_ELINKNO 16 R/W Undefined
987
TCD Last Destination Address Adjustment/Scatter Gather 21.4.33/
2C0_12B8 32 R/W Undefined
Address (DMA_TCD21_DLASTSGA) 988
21.4.34/
2C0_12BC TCD Control and Status (DMA_TCD21_CSR) 16 R/W Undefined
989
TCD Beginning Minor Loop Link, Major Loop Count
21.4.35/
2C0_12BE (Channel Linking Enabled) 16 R/W Undefined
991
(DMA_TCD21_BITER_ELINKYES)
TCD Beginning Minor Loop Link, Major Loop Count
21.4.36/
2C0_12BE (Channel Linking Disabled) 16 R/W Undefined
992
(DMA_TCD21_BITER_ELINKNO)
21.4.22/
2C0_12C0 TCD Source Address (DMA_TCD22_SADDR) 32 R/W Undefined
979
21.4.23/
2C0_12C4 TCD Signed Source Address Offset (DMA_TCD22_SOFF) 16 R/W Undefined
980
21.4.24/
2C0_12C6 TCD Transfer Attributes (DMA_TCD22_ATTR) 16 R/W Undefined
980
TCD Minor Byte Count (Minor Loop Mapping Disabled) 21.4.25/
2C0_12C8 32 R/W Undefined
(DMA_TCD22_NBYTES_MLNO) 981
TCD Signed Minor Loop Offset (Minor Loop Mapping
21.4.26/
2C0_12C8 Enabled and Offset Disabled) 32 R/W Undefined
982
(DMA_TCD22_NBYTES_MLOFFNO)
TCD Signed Minor Loop Offset (Minor Loop Mapping and 21.4.27/
2C0_12C8 32 R/W Undefined
Offset Enabled) (DMA_TCD22_NBYTES_MLOFFYES) 983
TCD Last Source Address Adjustment 21.4.28/
2C0_12CC 32 R/W Undefined
(DMA_TCD22_SLAST) 985
21.4.29/
2C0_12D0 TCD Destination Address (DMA_TCD22_DADDR) 32 R/W Undefined
985
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 937
Memory map/register definition
DMA memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
TCD Signed Destination Address Offset 21.4.30/
2C0_12D4 16 R/W Undefined
(DMA_TCD22_DOFF) 986
TCD Current Minor Loop Link, Major Loop Count (Channel 21.4.31/
2C0_12D6 16 R/W Undefined
Linking Enabled) (DMA_TCD22_CITER_ELINKYES) 986
21.4.32/
2C0_12D6 DMA_TCD22_CITER_ELINKNO 16 R/W Undefined
987
TCD Last Destination Address Adjustment/Scatter Gather 21.4.33/
2C0_12D8 32 R/W Undefined
Address (DMA_TCD22_DLASTSGA) 988
21.4.34/
2C0_12DC TCD Control and Status (DMA_TCD22_CSR) 16 R/W Undefined
989
TCD Beginning Minor Loop Link, Major Loop Count
21.4.35/
2C0_12DE (Channel Linking Enabled) 16 R/W Undefined
991
(DMA_TCD22_BITER_ELINKYES)
TCD Beginning Minor Loop Link, Major Loop Count
21.4.36/
2C0_12DE (Channel Linking Disabled) 16 R/W Undefined
992
(DMA_TCD22_BITER_ELINKNO)
21.4.22/
2C0_12E0 TCD Source Address (DMA_TCD23_SADDR) 32 R/W Undefined
979
21.4.23/
2C0_12E4 TCD Signed Source Address Offset (DMA_TCD23_SOFF) 16 R/W Undefined
980
21.4.24/
2C0_12E6 TCD Transfer Attributes (DMA_TCD23_ATTR) 16 R/W Undefined
980
TCD Minor Byte Count (Minor Loop Mapping Disabled) 21.4.25/
2C0_12E8 32 R/W Undefined
(DMA_TCD23_NBYTES_MLNO) 981
TCD Signed Minor Loop Offset (Minor Loop Mapping
21.4.26/
2C0_12E8 Enabled and Offset Disabled) 32 R/W Undefined
982
(DMA_TCD23_NBYTES_MLOFFNO)
TCD Signed Minor Loop Offset (Minor Loop Mapping and 21.4.27/
2C0_12E8 32 R/W Undefined
Offset Enabled) (DMA_TCD23_NBYTES_MLOFFYES) 983
TCD Last Source Address Adjustment 21.4.28/
2C0_12EC 32 R/W Undefined
(DMA_TCD23_SLAST) 985
21.4.29/
2C0_12F0 TCD Destination Address (DMA_TCD23_DADDR) 32 R/W Undefined
985
TCD Signed Destination Address Offset 21.4.30/
2C0_12F4 16 R/W Undefined
(DMA_TCD23_DOFF) 986
TCD Current Minor Loop Link, Major Loop Count (Channel 21.4.31/
2C0_12F6 16 R/W Undefined
Linking Enabled) (DMA_TCD23_CITER_ELINKYES) 986
21.4.32/
2C0_12F6 DMA_TCD23_CITER_ELINKNO 16 R/W Undefined
987
TCD Last Destination Address Adjustment/Scatter Gather 21.4.33/
2C0_12F8 32 R/W Undefined
Address (DMA_TCD23_DLASTSGA) 988
21.4.34/
2C0_12FC TCD Control and Status (DMA_TCD23_CSR) 16 R/W Undefined
989
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
938 NXP Semiconductors
Chapter 21 Enhanced Direct Memory Access (eDMA)
DMA memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
TCD Beginning Minor Loop Link, Major Loop Count
21.4.35/
2C0_12FE (Channel Linking Enabled) 16 R/W Undefined
991
(DMA_TCD23_BITER_ELINKYES)
TCD Beginning Minor Loop Link, Major Loop Count
21.4.36/
2C0_12FE (Channel Linking Disabled) 16 R/W Undefined
992
(DMA_TCD23_BITER_ELINKNO)
21.4.22/
2C0_1300 TCD Source Address (DMA_TCD24_SADDR) 32 R/W Undefined
979
21.4.23/
2C0_1304 TCD Signed Source Address Offset (DMA_TCD24_SOFF) 16 R/W Undefined
980
21.4.24/
2C0_1306 TCD Transfer Attributes (DMA_TCD24_ATTR) 16 R/W Undefined
980
TCD Minor Byte Count (Minor Loop Mapping Disabled) 21.4.25/
2C0_1308 32 R/W Undefined
(DMA_TCD24_NBYTES_MLNO) 981
TCD Signed Minor Loop Offset (Minor Loop Mapping
21.4.26/
2C0_1308 Enabled and Offset Disabled) 32 R/W Undefined
982
(DMA_TCD24_NBYTES_MLOFFNO)
TCD Signed Minor Loop Offset (Minor Loop Mapping and 21.4.27/
2C0_1308 32 R/W Undefined
Offset Enabled) (DMA_TCD24_NBYTES_MLOFFYES) 983
TCD Last Source Address Adjustment 21.4.28/
2C0_130C 32 R/W Undefined
(DMA_TCD24_SLAST) 985
21.4.29/
2C0_1310 TCD Destination Address (DMA_TCD24_DADDR) 32 R/W Undefined
985
TCD Signed Destination Address Offset 21.4.30/
2C0_1314 16 R/W Undefined
(DMA_TCD24_DOFF) 986
TCD Current Minor Loop Link, Major Loop Count (Channel 21.4.31/
2C0_1316 16 R/W Undefined
Linking Enabled) (DMA_TCD24_CITER_ELINKYES) 986
21.4.32/
2C0_1316 DMA_TCD24_CITER_ELINKNO 16 R/W Undefined
987
TCD Last Destination Address Adjustment/Scatter Gather 21.4.33/
2C0_1318 32 R/W Undefined
Address (DMA_TCD24_DLASTSGA) 988
21.4.34/
2C0_131C TCD Control and Status (DMA_TCD24_CSR) 16 R/W Undefined
989
TCD Beginning Minor Loop Link, Major Loop Count
21.4.35/
2C0_131E (Channel Linking Enabled) 16 R/W Undefined
991
(DMA_TCD24_BITER_ELINKYES)
TCD Beginning Minor Loop Link, Major Loop Count
21.4.36/
2C0_131E (Channel Linking Disabled) 16 R/W Undefined
992
(DMA_TCD24_BITER_ELINKNO)
21.4.22/
2C0_1320 TCD Source Address (DMA_TCD25_SADDR) 32 R/W Undefined
979
21.4.23/
2C0_1324 TCD Signed Source Address Offset (DMA_TCD25_SOFF) 16 R/W Undefined
980
21.4.24/
2C0_1326 TCD Transfer Attributes (DMA_TCD25_ATTR) 16 R/W Undefined
980
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 939
Memory map/register definition
DMA memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
TCD Minor Byte Count (Minor Loop Mapping Disabled) 21.4.25/
2C0_1328 32 R/W Undefined
(DMA_TCD25_NBYTES_MLNO) 981
TCD Signed Minor Loop Offset (Minor Loop Mapping
21.4.26/
2C0_1328 Enabled and Offset Disabled) 32 R/W Undefined
982
(DMA_TCD25_NBYTES_MLOFFNO)
TCD Signed Minor Loop Offset (Minor Loop Mapping and 21.4.27/
2C0_1328 32 R/W Undefined
Offset Enabled) (DMA_TCD25_NBYTES_MLOFFYES) 983
TCD Last Source Address Adjustment 21.4.28/
2C0_132C 32 R/W Undefined
(DMA_TCD25_SLAST) 985
21.4.29/
2C0_1330 TCD Destination Address (DMA_TCD25_DADDR) 32 R/W Undefined
985
TCD Signed Destination Address Offset 21.4.30/
2C0_1334 16 R/W Undefined
(DMA_TCD25_DOFF) 986
TCD Current Minor Loop Link, Major Loop Count (Channel 21.4.31/
2C0_1336 16 R/W Undefined
Linking Enabled) (DMA_TCD25_CITER_ELINKYES) 986
21.4.32/
2C0_1336 DMA_TCD25_CITER_ELINKNO 16 R/W Undefined
987
TCD Last Destination Address Adjustment/Scatter Gather 21.4.33/
2C0_1338 32 R/W Undefined
Address (DMA_TCD25_DLASTSGA) 988
21.4.34/
2C0_133C TCD Control and Status (DMA_TCD25_CSR) 16 R/W Undefined
989
TCD Beginning Minor Loop Link, Major Loop Count
21.4.35/
2C0_133E (Channel Linking Enabled) 16 R/W Undefined
991
(DMA_TCD25_BITER_ELINKYES)
TCD Beginning Minor Loop Link, Major Loop Count
21.4.36/
2C0_133E (Channel Linking Disabled) 16 R/W Undefined
992
(DMA_TCD25_BITER_ELINKNO)
21.4.22/
2C0_1340 TCD Source Address (DMA_TCD26_SADDR) 32 R/W Undefined
979
21.4.23/
2C0_1344 TCD Signed Source Address Offset (DMA_TCD26_SOFF) 16 R/W Undefined
980
21.4.24/
2C0_1346 TCD Transfer Attributes (DMA_TCD26_ATTR) 16 R/W Undefined
980
TCD Minor Byte Count (Minor Loop Mapping Disabled) 21.4.25/
2C0_1348 32 R/W Undefined
(DMA_TCD26_NBYTES_MLNO) 981
TCD Signed Minor Loop Offset (Minor Loop Mapping
21.4.26/
2C0_1348 Enabled and Offset Disabled) 32 R/W Undefined
982
(DMA_TCD26_NBYTES_MLOFFNO)
TCD Signed Minor Loop Offset (Minor Loop Mapping and 21.4.27/
2C0_1348 32 R/W Undefined
Offset Enabled) (DMA_TCD26_NBYTES_MLOFFYES) 983
TCD Last Source Address Adjustment 21.4.28/
2C0_134C 32 R/W Undefined
(DMA_TCD26_SLAST) 985
21.4.29/
2C0_1350 TCD Destination Address (DMA_TCD26_DADDR) 32 R/W Undefined
985
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
940 NXP Semiconductors
Chapter 21 Enhanced Direct Memory Access (eDMA)
DMA memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
TCD Signed Destination Address Offset 21.4.30/
2C0_1354 16 R/W Undefined
(DMA_TCD26_DOFF) 986
TCD Current Minor Loop Link, Major Loop Count (Channel 21.4.31/
2C0_1356 16 R/W Undefined
Linking Enabled) (DMA_TCD26_CITER_ELINKYES) 986
21.4.32/
2C0_1356 DMA_TCD26_CITER_ELINKNO 16 R/W Undefined
987
TCD Last Destination Address Adjustment/Scatter Gather 21.4.33/
2C0_1358 32 R/W Undefined
Address (DMA_TCD26_DLASTSGA) 988
21.4.34/
2C0_135C TCD Control and Status (DMA_TCD26_CSR) 16 R/W Undefined
989
TCD Beginning Minor Loop Link, Major Loop Count
21.4.35/
2C0_135E (Channel Linking Enabled) 16 R/W Undefined
991
(DMA_TCD26_BITER_ELINKYES)
TCD Beginning Minor Loop Link, Major Loop Count
21.4.36/
2C0_135E (Channel Linking Disabled) 16 R/W Undefined
992
(DMA_TCD26_BITER_ELINKNO)
21.4.22/
2C0_1360 TCD Source Address (DMA_TCD27_SADDR) 32 R/W Undefined
979
21.4.23/
2C0_1364 TCD Signed Source Address Offset (DMA_TCD27_SOFF) 16 R/W Undefined
980
21.4.24/
2C0_1366 TCD Transfer Attributes (DMA_TCD27_ATTR) 16 R/W Undefined
980
TCD Minor Byte Count (Minor Loop Mapping Disabled) 21.4.25/
2C0_1368 32 R/W Undefined
(DMA_TCD27_NBYTES_MLNO) 981
TCD Signed Minor Loop Offset (Minor Loop Mapping
21.4.26/
2C0_1368 Enabled and Offset Disabled) 32 R/W Undefined
982
(DMA_TCD27_NBYTES_MLOFFNO)
TCD Signed Minor Loop Offset (Minor Loop Mapping and 21.4.27/
2C0_1368 32 R/W Undefined
Offset Enabled) (DMA_TCD27_NBYTES_MLOFFYES) 983
TCD Last Source Address Adjustment 21.4.28/
2C0_136C 32 R/W Undefined
(DMA_TCD27_SLAST) 985
21.4.29/
2C0_1370 TCD Destination Address (DMA_TCD27_DADDR) 32 R/W Undefined
985
TCD Signed Destination Address Offset 21.4.30/
2C0_1374 16 R/W Undefined
(DMA_TCD27_DOFF) 986
TCD Current Minor Loop Link, Major Loop Count (Channel 21.4.31/
2C0_1376 16 R/W Undefined
Linking Enabled) (DMA_TCD27_CITER_ELINKYES) 986
21.4.32/
2C0_1376 DMA_TCD27_CITER_ELINKNO 16 R/W Undefined
987
TCD Last Destination Address Adjustment/Scatter Gather 21.4.33/
2C0_1378 32 R/W Undefined
Address (DMA_TCD27_DLASTSGA) 988
21.4.34/
2C0_137C TCD Control and Status (DMA_TCD27_CSR) 16 R/W Undefined
989
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 941
Memory map/register definition
DMA memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
TCD Beginning Minor Loop Link, Major Loop Count
21.4.35/
2C0_137E (Channel Linking Enabled) 16 R/W Undefined
991
(DMA_TCD27_BITER_ELINKYES)
TCD Beginning Minor Loop Link, Major Loop Count
21.4.36/
2C0_137E (Channel Linking Disabled) 16 R/W Undefined
992
(DMA_TCD27_BITER_ELINKNO)
21.4.22/
2C0_1380 TCD Source Address (DMA_TCD28_SADDR) 32 R/W Undefined
979
21.4.23/
2C0_1384 TCD Signed Source Address Offset (DMA_TCD28_SOFF) 16 R/W Undefined
980
21.4.24/
2C0_1386 TCD Transfer Attributes (DMA_TCD28_ATTR) 16 R/W Undefined
980
TCD Minor Byte Count (Minor Loop Mapping Disabled) 21.4.25/
2C0_1388 32 R/W Undefined
(DMA_TCD28_NBYTES_MLNO) 981
TCD Signed Minor Loop Offset (Minor Loop Mapping
21.4.26/
2C0_1388 Enabled and Offset Disabled) 32 R/W Undefined
982
(DMA_TCD28_NBYTES_MLOFFNO)
TCD Signed Minor Loop Offset (Minor Loop Mapping and 21.4.27/
2C0_1388 32 R/W Undefined
Offset Enabled) (DMA_TCD28_NBYTES_MLOFFYES) 983
TCD Last Source Address Adjustment 21.4.28/
2C0_138C 32 R/W Undefined
(DMA_TCD28_SLAST) 985
21.4.29/
2C0_1390 TCD Destination Address (DMA_TCD28_DADDR) 32 R/W Undefined
985
TCD Signed Destination Address Offset 21.4.30/
2C0_1394 16 R/W Undefined
(DMA_TCD28_DOFF) 986
TCD Current Minor Loop Link, Major Loop Count (Channel 21.4.31/
2C0_1396 16 R/W Undefined
Linking Enabled) (DMA_TCD28_CITER_ELINKYES) 986
21.4.32/
2C0_1396 DMA_TCD28_CITER_ELINKNO 16 R/W Undefined
987
TCD Last Destination Address Adjustment/Scatter Gather 21.4.33/
2C0_1398 32 R/W Undefined
Address (DMA_TCD28_DLASTSGA) 988
21.4.34/
2C0_139C TCD Control and Status (DMA_TCD28_CSR) 16 R/W Undefined
989
TCD Beginning Minor Loop Link, Major Loop Count
21.4.35/
2C0_139E (Channel Linking Enabled) 16 R/W Undefined
991
(DMA_TCD28_BITER_ELINKYES)
TCD Beginning Minor Loop Link, Major Loop Count
21.4.36/
2C0_139E (Channel Linking Disabled) 16 R/W Undefined
992
(DMA_TCD28_BITER_ELINKNO)
21.4.22/
2C0_13A0 TCD Source Address (DMA_TCD29_SADDR) 32 R/W Undefined
979
21.4.23/
2C0_13A4 TCD Signed Source Address Offset (DMA_TCD29_SOFF) 16 R/W Undefined
980
21.4.24/
2C0_13A6 TCD Transfer Attributes (DMA_TCD29_ATTR) 16 R/W Undefined
980
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
942 NXP Semiconductors
Chapter 21 Enhanced Direct Memory Access (eDMA)
DMA memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
TCD Minor Byte Count (Minor Loop Mapping Disabled) 21.4.25/
2C0_13A8 32 R/W Undefined
(DMA_TCD29_NBYTES_MLNO) 981
TCD Signed Minor Loop Offset (Minor Loop Mapping
21.4.26/
2C0_13A8 Enabled and Offset Disabled) 32 R/W Undefined
982
(DMA_TCD29_NBYTES_MLOFFNO)
TCD Signed Minor Loop Offset (Minor Loop Mapping and 21.4.27/
2C0_13A8 32 R/W Undefined
Offset Enabled) (DMA_TCD29_NBYTES_MLOFFYES) 983
TCD Last Source Address Adjustment 21.4.28/
2C0_13AC 32 R/W Undefined
(DMA_TCD29_SLAST) 985
21.4.29/
2C0_13B0 TCD Destination Address (DMA_TCD29_DADDR) 32 R/W Undefined
985
TCD Signed Destination Address Offset 21.4.30/
2C0_13B4 16 R/W Undefined
(DMA_TCD29_DOFF) 986
TCD Current Minor Loop Link, Major Loop Count (Channel 21.4.31/
2C0_13B6 16 R/W Undefined
Linking Enabled) (DMA_TCD29_CITER_ELINKYES) 986
21.4.32/
2C0_13B6 DMA_TCD29_CITER_ELINKNO 16 R/W Undefined
987
TCD Last Destination Address Adjustment/Scatter Gather 21.4.33/
2C0_13B8 32 R/W Undefined
Address (DMA_TCD29_DLASTSGA) 988
21.4.34/
2C0_13BC TCD Control and Status (DMA_TCD29_CSR) 16 R/W Undefined
989
TCD Beginning Minor Loop Link, Major Loop Count
21.4.35/
2C0_13BE (Channel Linking Enabled) 16 R/W Undefined
991
(DMA_TCD29_BITER_ELINKYES)
TCD Beginning Minor Loop Link, Major Loop Count
21.4.36/
2C0_13BE (Channel Linking Disabled) 16 R/W Undefined
992
(DMA_TCD29_BITER_ELINKNO)
21.4.22/
2C0_13C0 TCD Source Address (DMA_TCD30_SADDR) 32 R/W Undefined
979
21.4.23/
2C0_13C4 TCD Signed Source Address Offset (DMA_TCD30_SOFF) 16 R/W Undefined
980
21.4.24/
2C0_13C6 TCD Transfer Attributes (DMA_TCD30_ATTR) 16 R/W Undefined
980
TCD Minor Byte Count (Minor Loop Mapping Disabled) 21.4.25/
2C0_13C8 32 R/W Undefined
(DMA_TCD30_NBYTES_MLNO) 981
TCD Signed Minor Loop Offset (Minor Loop Mapping
21.4.26/
2C0_13C8 Enabled and Offset Disabled) 32 R/W Undefined
982
(DMA_TCD30_NBYTES_MLOFFNO)
TCD Signed Minor Loop Offset (Minor Loop Mapping and 21.4.27/
2C0_13C8 32 R/W Undefined
Offset Enabled) (DMA_TCD30_NBYTES_MLOFFYES) 983
TCD Last Source Address Adjustment 21.4.28/
2C0_13CC 32 R/W Undefined
(DMA_TCD30_SLAST) 985
21.4.29/
2C0_13D0 TCD Destination Address (DMA_TCD30_DADDR) 32 R/W Undefined
985
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 943
Memory map/register definition
DMA memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
TCD Signed Destination Address Offset 21.4.30/
2C0_13D4 16 R/W Undefined
(DMA_TCD30_DOFF) 986
TCD Current Minor Loop Link, Major Loop Count (Channel 21.4.31/
2C0_13D6 16 R/W Undefined
Linking Enabled) (DMA_TCD30_CITER_ELINKYES) 986
21.4.32/
2C0_13D6 DMA_TCD30_CITER_ELINKNO 16 R/W Undefined
987
TCD Last Destination Address Adjustment/Scatter Gather 21.4.33/
2C0_13D8 32 R/W Undefined
Address (DMA_TCD30_DLASTSGA) 988
21.4.34/
2C0_13DC TCD Control and Status (DMA_TCD30_CSR) 16 R/W Undefined
989
TCD Beginning Minor Loop Link, Major Loop Count
21.4.35/
2C0_13DE (Channel Linking Enabled) 16 R/W Undefined
991
(DMA_TCD30_BITER_ELINKYES)
TCD Beginning Minor Loop Link, Major Loop Count
21.4.36/
2C0_13DE (Channel Linking Disabled) 16 R/W Undefined
992
(DMA_TCD30_BITER_ELINKNO)
21.4.22/
2C0_13E0 TCD Source Address (DMA_TCD31_SADDR) 32 R/W Undefined
979
21.4.23/
2C0_13E4 TCD Signed Source Address Offset (DMA_TCD31_SOFF) 16 R/W Undefined
980
21.4.24/
2C0_13E6 TCD Transfer Attributes (DMA_TCD31_ATTR) 16 R/W Undefined
980
TCD Minor Byte Count (Minor Loop Mapping Disabled) 21.4.25/
2C0_13E8 32 R/W Undefined
(DMA_TCD31_NBYTES_MLNO) 981
TCD Signed Minor Loop Offset (Minor Loop Mapping
21.4.26/
2C0_13E8 Enabled and Offset Disabled) 32 R/W Undefined
982
(DMA_TCD31_NBYTES_MLOFFNO)
TCD Signed Minor Loop Offset (Minor Loop Mapping and 21.4.27/
2C0_13E8 32 R/W Undefined
Offset Enabled) (DMA_TCD31_NBYTES_MLOFFYES) 983
TCD Last Source Address Adjustment 21.4.28/
2C0_13EC 32 R/W Undefined
(DMA_TCD31_SLAST) 985
21.4.29/
2C0_13F0 TCD Destination Address (DMA_TCD31_DADDR) 32 R/W Undefined
985
TCD Signed Destination Address Offset 21.4.30/
2C0_13F4 16 R/W Undefined
(DMA_TCD31_DOFF) 986
TCD Current Minor Loop Link, Major Loop Count (Channel 21.4.31/
2C0_13F6 16 R/W Undefined
Linking Enabled) (DMA_TCD31_CITER_ELINKYES) 986
21.4.32/
2C0_13F6 DMA_TCD31_CITER_ELINKNO 16 R/W Undefined
987
TCD Last Destination Address Adjustment/Scatter Gather 21.4.33/
2C0_13F8 32 R/W Undefined
Address (DMA_TCD31_DLASTSGA) 988
21.4.34/
2C0_13FC TCD Control and Status (DMA_TCD31_CSR) 16 R/W Undefined
989
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
944 NXP Semiconductors
Chapter 21 Enhanced Direct Memory Access (eDMA)
DMA memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
TCD Beginning Minor Loop Link, Major Loop Count
21.4.35/
2C0_13FE (Channel Linking Enabled) 16 R/W Undefined
991
(DMA_TCD31_BITER_ELINKYES)
TCD Beginning Minor Loop Link, Major Loop Count
21.4.36/
2C0_13FE (Channel Linking Disabled) 16 R/W Undefined
992
(DMA_TCD31_BITER_ELINKNO)
21.4.6 Control Register (DMA_CR)
The CR defines the basic operating configuration of the DMA. The DMA arbitrates
channel service requests in two groups of 16 channels each:
• Group 1 contains channels 31-16
• Group 0 contains channels 15-0
Arbitration within a group can be configured to use either a fixed-priority or a round-
robin scheme. For fixed-priority arbitration, the highest priority channel requesting
service is selected to execute. The channel priority registers assign the priorities; see the
DCHPRIn registers. For round-robin arbitration, the channel priorities are ignored and
channels within each group are cycled through (from high to low channel number)
without regard to priority.
NOTE
For correct operation, writes to the CR register must be
performed only when the DMA channels are inactive; that is,
when TCDn_CSR[ACTIVE] bits are cleared.
The group priorities operate in a similar fashion. In group fixed priority arbitration mode,
channel service requests in the highest priority group are executed first, where priority
level 1 is the highest and priority level 0 is the lowest. The group priorities are assigned
in the GRPnPRI fields of the DMA Control Register (CR). All group priorities must have
unique values prior to any channel service requests occurring; otherwise, a configuration
error will be reported. For group round robin arbitration, the group priorities are ignored
and the groups are cycled through (from high to low group number) without regard to
priority.
Minor loop offsets are address offset values added to the final source address
(TCDn_SADDR) or destination address (TCDn_DADDR) upon minor loop completion.
When minor loop offsets are enabled, the minor loop offset (MLOFF) is added to the
final source address (TCDn_SADDR), to the final destination address (TCDn_DADDR),
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 945
Memory map/register definition
or to both prior to the addresses being written back into the TCD. If the major loop is
complete, the minor loop offset is ignored and the major loop address offsets
(TCDn_SLAST and TCDn_DLAST_SGA) are used to compute the next TCDn_SADDR
and TCDn_DADDR values.
When minor loop mapping is enabled (EMLM is 1), TCDn word2 is redefined. A portion
of TCDn word2 is used to specify multiple fields: a source enable bit (SMLOE) to
specify the minor loop offset should be applied to the source address (TCDn_SADDR)
upon minor loop completion, a destination enable bit (DMLOE) to specify the minor loop
offset should be applied to the destination address (TCDn_DADDR) upon minor loop
completion, and the sign extended minor loop offset value (MLOFF). The same offset
value (MLOFF) is used for both source and destination minor loop offsets. When either
minor loop offset is enabled (SMLOE set or DMLOE set), the NBYTES field is reduced
to 10 bits. When both minor loop offsets are disabled (SMLOE cleared and DMLOE
cleared), the NBYTES field is a 30-bit vector.
When minor loop mapping is disabled (EMLM is 0), all 32 bits of TCDn word2 are
assigned to the NBYTES field.
Address: 2C0_0000h base + 0h offset = 2C0_0000h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0
CX ECX
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0
GRP1PRI
GRP0PRI
Reserved
EMLM
ERGA
EDBG
ERCA
HALT
CLM HOE
W
Reset 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
DMA_CR field descriptions
Field Description
0–13 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
14 Cancel Transfer
CX
0 Normal operation
1 Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The
cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after
the cancel has been honored. This cancel retires the channel normally as if the minor loop was
completed.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
946 NXP Semiconductors
Chapter 21 Enhanced Direct Memory Access (eDMA)
DMA_CR field descriptions (continued)
Field Description
15 Error Cancel Transfer
ECX
0 Normal operation
1 Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and
force the minor loop to finish. The cancel takes effect after the last write of the current read/write
sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer,
ECX treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and
generating an optional error interrupt.
16–20 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
21 Channel Group 1 Priority
GRP1PRI
Group 1 priority level when fixed priority group arbitration is enabled.
22 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
23 Channel Group 0 Priority
GRP0PRI
Group 0 priority level when fixed priority group arbitration is enabled.
24 Enable Minor Loop Mapping
EMLM
0 Disabled. TCDn.word2 is defined as a 32-bit NBYTES field.
1 Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES
field. The individual enable fields allow the minor loop offset to be applied to the source address, the
destination address, or both. The NBYTES field is reduced when either offset is enabled.
25 Continuous Link Mode
CLM
NOTE: Do not use continuous link mode with a channel linking to itself if there is only one minor loop
iteration per service request, e.g., if the channel’s NBYTES value is the same as either the source
or destination size. The same data transfer profile can be achieved by simply increasing the
NBYTES value, which provides more efficient, faster processing.
0 A minor loop channel link made to itself goes through channel arbitration before being activated again.
1 A minor loop channel link made to itself does not go through channel arbitration before being activated
again. Upon minor loop completion, the channel activates again if that channel has a minor loop
channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and
restarts the next minor loop.
26 Halt DMA Operations
HALT
0 Normal operation
1 Stall the start of any new channels. Executing channels are allowed to complete. Channel execution
resumes when this bit is cleared.
27 Halt On Error
HOE
0 Normal operation
1 Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit
is cleared.
28 Enable Round Robin Group Arbitration
ERGA
0 Fixed priority arbitration is used for selection among the groups.
1 Round robin arbitration is used for selection among the groups.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 947
Memory map/register definition
DMA_CR field descriptions (continued)
Field Description
29 Enable Round Robin Channel Arbitration
ERCA
0 Fixed priority arbitration is used for channel selection within each group.
1 Round robin arbitration is used for channel selection within each group.
30 Enable Debug
EDBG
0 When in debug mode, the DMA continues to operate.
1 When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to
complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared.
31 This field is reserved.
Reserved Reserved
21.4.7 Error Status Register (DMA_ES)
The ES provides information concerning the last recorded channel error. Channel errors
can be caused by:
• A configuration error, that is:
• An illegal setting in the transfer-control descriptor, or
• An illegal priority register setting in fixed-arbitration
• An error termination to a bus master read or write cycle
• A cancel transfer with error bit that will be set when a transfer is canceled via the
corresponding cancel transfer control bit
See Fault reporting and handling for more details.
Address: 2C0_0000h base + 4h offset = 2C0_0004h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R VLD 0 ECX
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R GPE CPE 0 ERRCHN SAE SOE DAE DOE NCE SGE SBE DBE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_ES field descriptions
Field Description
0 Logical OR of all ERR status bits
VLD
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
948 NXP Semiconductors
Chapter 21 Enhanced Direct Memory Access (eDMA)
DMA_ES field descriptions (continued)
Field Description
0 No ERR bits are set.
1 At least one ERR bit is set indicating a valid error exists that has not been cleared.
1–14 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
15 Transfer Canceled
ECX
0 No canceled transfers
1 The last recorded entry was a canceled transfer by the error cancel transfer input
16 Group Priority Error
GPE
0 No group priority error
1 The last recorded error was a configuration error among the group priorities. All group priorities are not
unique.
17 Channel Priority Error
CPE
0 No channel priority error
1 The last recorded error was a configuration error in the channel priorities within a group. Channel
priorities within a group are not unique.
18 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
19–23 Error Channel Number or Canceled Channel Number
ERRCHN
The channel number of the last recorded error, excluding GPE and CPE errors, or last recorded error
canceled transfer.
24 Source Address Error
SAE
0 No source address configuration error.
1 The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR
is inconsistent with TCDn_ATTR[SSIZE].
25 Source Offset Error
SOE
0 No source offset configuration error
1 The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is
inconsistent with TCDn_ATTR[SSIZE].
26 Destination Address Error
DAE
0 No destination address configuration error
1 The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR
is inconsistent with TCDn_ATTR[DSIZE].
27 Destination Offset Error
DOE
0 No destination offset configuration error
1 The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is
inconsistent with TCDn_ATTR[DSIZE].
28 NBYTES/CITER Configuration Error
NCE
0 No NBYTES/CITER configuration error
1 The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER
fields.
• TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 949
Memory map/register definition
DMA_ES field descriptions (continued)
Field Description
• TCDn_CITER[CITER] is equal to zero, or
• TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]
29 Scatter/Gather Configuration Error
SGE
0 No scatter/gather configuration error
1 The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is
checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG]
is enabled. TCDn_DLASTSGA is not on a 32 byte boundary.
30 Source Bus Error
SBE
0 No source bus error
1 The last recorded error was a bus error on a source read
31 Destination Bus Error
DBE
0 No destination bus error
1 The last recorded error was a bus error on a destination write
21.4.8 Enable Request Register (DMA_ERQ)
The ERQ register provides a bit map for the 32 channels to enable the request signal for
each channel. The state of any given channel enable is directly affected by writes to this
register; it is also affected by writes to the SERQ and CERQ registers. These registers are
provided so the request enable for a single channel can easily be modified without
needing to perform a read-modify-write sequence to the ERQ.
DMA request input signals and this enable request flag must be asserted before a
channel’s hardware service request is accepted. The state of the DMA enable request flag
does not affect a channel service request made explicitly through software or a linked
channel request.
NOTE
Disable a channel’s hardware service request at the source
before clearing the channel’s ERQ bit.
Address: 2C0_0000h base + Ch offset = 2C0_000Ch
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
ERQ31
ERQ30
ERQ29
ERQ28
ERQ27
ERQ26
ERQ25
ERQ24
ERQ23
ERQ22
ERQ21
ERQ20
ERQ19
ERQ18
ERQ17
ERQ16
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
950 NXP Semiconductors
Chapter 21 Enhanced Direct Memory Access (eDMA)
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
ERQ15
ERQ14
ERQ13
ERQ12
ERQ11
ERQ10
ERQ9 ERQ8 ERQ7 ERQ6 ERQ5 ERQ4 ERQ3 ERQ2 ERQ1 ERQ0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_ERQ field descriptions
Field Description
0 Enable DMA Request 31
ERQ31
0 The DMA request signal for the corresponding channel is disabled
1 The DMA request signal for the corresponding channel is enabled
1 Enable DMA Request 30
ERQ30
0 The DMA request signal for the corresponding channel is disabled
1 The DMA request signal for the corresponding channel is enabled
2 Enable DMA Request 29
ERQ29
0 The DMA request signal for the corresponding channel is disabled
1 The DMA request signal for the corresponding channel is enabled
3 Enable DMA Request 28
ERQ28
0 The DMA request signal for the corresponding channel is disabled
1 The DMA request signal for the corresponding channel is enabled
4 Enable DMA Request 27
ERQ27
0 The DMA request signal for the corresponding channel is disabled
1 The DMA request signal for the corresponding channel is enabled
5 Enable DMA Request 26
ERQ26
0 The DMA request signal for the corresponding channel is disabled
1 The DMA request signal for the corresponding channel is enabled
6 Enable DMA Request 25
ERQ25
0 The DMA request signal for the corresponding channel is disabled
1 The DMA request signal for the corresponding channel is enabled
7 Enable DMA Request 24
ERQ24
0 The DMA request signal for the corresponding channel is disabled
1 The DMA request signal for the corresponding channel is enabled
8 Enable DMA Request 23
ERQ23
0 The DMA request signal for the corresponding channel is disabled
1 The DMA request signal for the corresponding channel is enabled
9 Enable DMA Request 22
ERQ22
0 The DMA request signal for the corresponding channel is disabled
1 The DMA request signal for the corresponding channel is enabled
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 951
Memory map/register definition
DMA_ERQ field descriptions (continued)
Field Description
10 Enable DMA Request 21
ERQ21
0 The DMA request signal for the corresponding channel is disabled
1 The DMA request signal for the corresponding channel is enabled
11 Enable DMA Request 20
ERQ20
0 The DMA request signal for the corresponding channel is disabled
1 The DMA request signal for the corresponding channel is enabled
12 Enable DMA Request 19
ERQ19
0 The DMA request signal for the corresponding channel is disabled
1 The DMA request signal for the corresponding channel is enabled
13 Enable DMA Request 18
ERQ18
0 The DMA request signal for the corresponding channel is disabled
1 The DMA request signal for the corresponding channel is enabled
14 Enable DMA Request 17
ERQ17
0 The DMA request signal for the corresponding channel is disabled
1 The DMA request signal for the corresponding channel is enabled
15 Enable DMA Request 16
ERQ16
0 The DMA request signal for the corresponding channel is disabled
1 The DMA request signal for the corresponding channel is enabled
16 Enable DMA Request 15
ERQ15
0 The DMA request signal for the corresponding channel is disabled
1 The DMA request signal for the corresponding channel is enabled
17 Enable DMA Request 14
ERQ14
0 The DMA request signal for the corresponding channel is disabled
1 The DMA request signal for the corresponding channel is enabled
18 Enable DMA Request 13
ERQ13
0 The DMA request signal for the corresponding channel is disabled
1 The DMA request signal for the corresponding channel is enabled
19 Enable DMA Request 12
ERQ12
0 The DMA request signal for the corresponding channel is disabled
1 The DMA request signal for the corresponding channel is enabled
20 Enable DMA Request 11
ERQ11
0 The DMA request signal for the corresponding channel is disabled
1 The DMA request signal for the corresponding channel is enabled
21 Enable DMA Request 10
ERQ10
0 The DMA request signal for the corresponding channel is disabled
1 The DMA request signal for the corresponding channel is enabled
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
952 NXP Semiconductors
Chapter 21 Enhanced Direct Memory Access (eDMA)
DMA_ERQ field descriptions (continued)
Field Description
22 Enable DMA Request 9
ERQ9
0 The DMA request signal for the corresponding channel is disabled
1 The DMA request signal for the corresponding channel is enabled
23 Enable DMA Request 8
ERQ8
0 The DMA request signal for the corresponding channel is disabled
1 The DMA request signal for the corresponding channel is enabled
24 Enable DMA Request 7
ERQ7
0 The DMA request signal for the corresponding channel is disabled
1 The DMA request signal for the corresponding channel is enabled
25 Enable DMA Request 6
ERQ6
0 The DMA request signal for the corresponding channel is disabled
1 The DMA request signal for the corresponding channel is enabled
26 Enable DMA Request 5
ERQ5
0 The DMA request signal for the corresponding channel is disabled
1 The DMA request signal for the corresponding channel is enabled
27 Enable DMA Request 4
ERQ4
0 The DMA request signal for the corresponding channel is disabled
1 The DMA request signal for the corresponding channel is enabled
28 Enable DMA Request 3
ERQ3
0 The DMA request signal for the corresponding channel is disabled
1 The DMA request signal for the corresponding channel is enabled
29 Enable DMA Request 2
ERQ2
0 The DMA request signal for the corresponding channel is disabled
1 The DMA request signal for the corresponding channel is enabled
30 Enable DMA Request 1
ERQ1
0 The DMA request signal for the corresponding channel is disabled
1 The DMA request signal for the corresponding channel is enabled
31 Enable DMA Request 0
ERQ0
0 The DMA request signal for the corresponding channel is disabled
1 The DMA request signal for the corresponding channel is enabled
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 953
Memory map/register definition
21.4.9 Enable Error Interrupt Register (DMA_EEI)
The EEI register provides a bit map for the 32 channels to enable the error interrupt
signal for each channel. The state of any given channel’s error interrupt enable is directly
affected by writes to this register; it is also affected by writes to the SEEI and CEEI.
These registers are provided so that the error interrupt enable for a single channel can
easily be modified without the need to perform a read-modify-write sequence to the EEI
register.
The DMA error indicator and the error interrupt enable flag must be asserted before an
error interrupt request for a given channel is asserted to the interrupt controller.
Address: 2C0_0000h base + 14h offset = 2C0_0014h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
EEI31
EEI30
EEI29
EEI28
EEI27
EEI26
EEI25
EEI24
EEI23
EEI22
EEI21
EEI20
EEI19
EEI18
EEI17
EEI16
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
EEI15
EEI14
EEI13
EEI12
EEI11
EEI10
EEI9 EEI8 EEI7 EEI6 EEI5 EEI4 EEI3 EEI2 EEI1 EEI0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_EEI field descriptions
Field Description
0 Enable Error Interrupt 31
EEI31
0 The error signal for corresponding channel does not generate an error interrupt
1 The assertion of the error signal for corresponding channel generates an error interrupt request
1 Enable Error Interrupt 30
EEI30
0 The error signal for corresponding channel does not generate an error interrupt
1 The assertion of the error signal for corresponding channel generates an error interrupt request
2 Enable Error Interrupt 29
EEI29
0 The error signal for corresponding channel does not generate an error interrupt
1 The assertion of the error signal for corresponding channel generates an error interrupt request
3 Enable Error Interrupt 28
EEI28
0 The error signal for corresponding channel does not generate an error interrupt
1 The assertion of the error signal for corresponding channel generates an error interrupt request
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
954 NXP Semiconductors
Chapter 21 Enhanced Direct Memory Access (eDMA)
DMA_EEI field descriptions (continued)
Field Description
4 Enable Error Interrupt 27
EEI27
0 The error signal for corresponding channel does not generate an error interrupt
1 The assertion of the error signal for corresponding channel generates an error interrupt request
5 Enable Error Interrupt 26
EEI26
0 The error signal for corresponding channel does not generate an error interrupt
1 The assertion of the error signal for corresponding channel generates an error interrupt request
6 Enable Error Interrupt 25
EEI25
0 The error signal for corresponding channel does not generate an error interrupt
1 The assertion of the error signal for corresponding channel generates an error interrupt request
7 Enable Error Interrupt 24
EEI24
0 The error signal for corresponding channel does not generate an error interrupt
1 The assertion of the error signal for corresponding channel generates an error interrupt request
8 Enable Error Interrupt 23
EEI23
0 The error signal for corresponding channel does not generate an error interrupt
1 The assertion of the error signal for corresponding channel generates an error interrupt request
9 Enable Error Interrupt 22
EEI22
0 The error signal for corresponding channel does not generate an error interrupt
1 The assertion of the error signal for corresponding channel generates an error interrupt request
10 Enable Error Interrupt 21
EEI21
0 The error signal for corresponding channel does not generate an error interrupt
1 The assertion of the error signal for corresponding channel generates an error interrupt request
11 Enable Error Interrupt 20
EEI20
0 The error signal for corresponding channel does not generate an error interrupt
1 The assertion of the error signal for corresponding channel generates an error interrupt request
12 Enable Error Interrupt 19
EEI19
0 The error signal for corresponding channel does not generate an error interrupt
1 The assertion of the error signal for corresponding channel generates an error interrupt request
13 Enable Error Interrupt 18
EEI18
0 The error signal for corresponding channel does not generate an error interrupt
1 The assertion of the error signal for corresponding channel generates an error interrupt request
14 Enable Error Interrupt 17
EEI17
0 The error signal for corresponding channel does not generate an error interrupt
1 The assertion of the error signal for corresponding channel generates an error interrupt request
15 Enable Error Interrupt 16
EEI16
0 The error signal for corresponding channel does not generate an error interrupt
1 The assertion of the error signal for corresponding channel generates an error interrupt request
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 955
Memory map/register definition
DMA_EEI field descriptions (continued)
Field Description
16 Enable Error Interrupt 15
EEI15
0 The error signal for corresponding channel does not generate an error interrupt
1 The assertion of the error signal for corresponding channel generates an error interrupt request
17 Enable Error Interrupt 14
EEI14
0 The error signal for corresponding channel does not generate an error interrupt
1 The assertion of the error signal for corresponding channel generates an error interrupt request
18 Enable Error Interrupt 13
EEI13
0 The error signal for corresponding channel does not generate an error interrupt
1 The assertion of the error signal for corresponding channel generates an error interrupt request
19 Enable Error Interrupt 12
EEI12
0 The error signal for corresponding channel does not generate an error interrupt
1 The assertion of the error signal for corresponding channel generates an error interrupt request
20 Enable Error Interrupt 11
EEI11
0 The error signal for corresponding channel does not generate an error interrupt
1 The assertion of the error signal for corresponding channel generates an error interrupt request
21 Enable Error Interrupt 10
EEI10
0 The error signal for corresponding channel does not generate an error interrupt
1 The assertion of the error signal for corresponding channel generates an error interrupt request
22 Enable Error Interrupt 9
EEI9
0 The error signal for corresponding channel does not generate an error interrupt
1 The assertion of the error signal for corresponding channel generates an error interrupt request
23 Enable Error Interrupt 8
EEI8
0 The error signal for corresponding channel does not generate an error interrupt
1 The assertion of the error signal for corresponding channel generates an error interrupt request
24 Enable Error Interrupt 7
EEI7
0 The error signal for corresponding channel does not generate an error interrupt
1 The assertion of the error signal for corresponding channel generates an error interrupt request
25 Enable Error Interrupt 6
EEI6
0 The error signal for corresponding channel does not generate an error interrupt
1 The assertion of the error signal for corresponding channel generates an error interrupt request
26 Enable Error Interrupt 5
EEI5
0 The error signal for corresponding channel does not generate an error interrupt
1 The assertion of the error signal for corresponding channel generates an error interrupt request
27 Enable Error Interrupt 4
EEI4
0 The error signal for corresponding channel does not generate an error interrupt
1 The assertion of the error signal for corresponding channel generates an error interrupt request
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
956 NXP Semiconductors
Chapter 21 Enhanced Direct Memory Access (eDMA)
DMA_EEI field descriptions (continued)
Field Description
28 Enable Error Interrupt 3
EEI3
0 The error signal for corresponding channel does not generate an error interrupt
1 The assertion of the error signal for corresponding channel generates an error interrupt request
29 Enable Error Interrupt 2
EEI2
0 The error signal for corresponding channel does not generate an error interrupt
1 The assertion of the error signal for corresponding channel generates an error interrupt request
30 Enable Error Interrupt 1
EEI1
0 The error signal for corresponding channel does not generate an error interrupt
1 The assertion of the error signal for corresponding channel generates an error interrupt request
31 Enable Error Interrupt 0
EEI0
0 The error signal for corresponding channel does not generate an error interrupt
1 The assertion of the error signal for corresponding channel generates an error interrupt request
21.4.10 Clear Enable Error Interrupt Register (DMA_CEEI)
The CEEI provides a simple memory-mapped mechanism to clear a given bit in the EEI
to disable the error interrupt for a given channel. The data value on a register write causes
the corresponding bit in the EEI to be cleared. Setting the CAEE bit provides a global
clear function, forcing the EEI contents to be cleared, disabling all DMA request inputs.
If the NOP bit is set, the command is ignored. This allows you to write multiple-byte
registers as a 32-bit word. Reads of this register return all zeroes.
Address: 2C0_0000h base + 18h offset = 2C0_0018h
Bit 0 1 2 3 4 5 6 7
Read 0 0 0
Write NOP CAEE 0 CEEI
Reset 0 0 0 0 0 0 0 0
DMA_CEEI field descriptions
Field Description
0 No Op enable
NOP
0 Normal operation
1 No operation, ignore the other bits in this register
1 Clear All Enable Error Interrupts
CAEE
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 957
Memory map/register definition
DMA_CEEI field descriptions (continued)
Field Description
0 Clear only the EEI bit specified in the CEEI field
1 Clear all bits in EEI
2 This field is reserved.
Reserved
3–7 Clear Enable Error Interrupt
CEEI
Clears the corresponding bit in EEI
21.4.11 Set Enable Error Interrupt Register (DMA_SEEI)
The SEEI provides a simple memory-mapped mechanism to set a given bit in the EEI to
enable the error interrupt for a given channel. The data value on a register write causes
the corresponding bit in the EEI to be set. Setting the SAEE bit provides a global set
function, forcing the entire EEI contents to be set. If the NOP bit is set, the command is
ignored. This allows you to write multiple-byte registers as a 32-bit word. Reads of this
register return all zeroes.
Address: 2C0_0000h base + 19h offset = 2C0_0019h
Bit 0 1 2 3 4 5 6 7
Read 0 0 0
Write NOP SAEE 0 SEEI
Reset 0 0 0 0 0 0 0 0
DMA_SEEI field descriptions
Field Description
0 No Op enable
NOP
0 Normal operation
1 No operation, ignore the other bits in this register
1 Sets All Enable Error Interrupts
SAEE
0 Set only the EEI bit specified in the SEEI field.
1 Sets all bits in EEI
2 This field is reserved.
Reserved
3–7 Set Enable Error Interrupt
SEEI
Sets the corresponding bit in EEI
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
958 NXP Semiconductors
Chapter 21 Enhanced Direct Memory Access (eDMA)
21.4.12 Clear Enable Request Register (DMA_CERQ)
The CERQ provides a simple memory-mapped mechanism to clear a given bit in the
ERQ to disable the DMA request for a given channel. The data value on a register write
causes the corresponding bit in the ERQ to be cleared. Setting the CAER bit provides a
global clear function, forcing the entire contents of the ERQ to be cleared, disabling all
DMA request inputs. If NOP is set, the command is ignored. This allows you to write
multiple-byte registers as a 32-bit word. Reads of this register return all zeroes.
NOTE
Disable a channel’s hardware service request at the source
before clearing the channel’s ERQ bit.
Address: 2C0_0000h base + 1Ah offset = 2C0_001Ah
Bit 0 1 2 3 4 5 6 7
Read 0 0 0
Write NOP CAER 0 CERQ
Reset 0 0 0 0 0 0 0 0
DMA_CERQ field descriptions
Field Description
0 No Op enable
NOP
0 Normal operation
1 No operation, ignore the other bits in this register
1 Clear All Enable Requests
CAER
0 Clear only the ERQ bit specified in the CERQ field
1 Clear all bits in ERQ
2 This field is reserved.
Reserved
3–7 Clear Enable Request
CERQ
Clears the corresponding bit in ERQ.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 959
Memory map/register definition
21.4.13 Set Enable Request Register (DMA_SERQ)
The SERQ provides a simple memory-mapped mechanism to set a given bit in the ERQ
to enable the DMA request for a given channel. The data value on a register write causes
the corresponding bit in the ERQ to be set. Setting the SAER bit provides a global set
function, forcing the entire contents of ERQ to be set. If the NOP bit is set, the command
is ignored. This allows you to write multiple-byte registers as a 32-bit word. Reads of this
register return all zeroes.
Address: 2C0_0000h base + 1Bh offset = 2C0_001Bh
Bit 0 1 2 3 4 5 6 7
Read 0 0 0
Write NOP SAER 0 SERQ
Reset 0 0 0 0 0 0 0 0
DMA_SERQ field descriptions
Field Description
0 No Op enable
NOP
0 Normal operation
1 No operation, ignore the other bits in this register
1 Set All Enable Requests
SAER
0 Set only the ERQ bit specified in the SERQ field
1 Set all bits in ERQ
2 This field is reserved.
Reserved
3–7 Set Enable Request
SERQ
Sets the corresponding bit in ERQ.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
960 NXP Semiconductors
Chapter 21 Enhanced Direct Memory Access (eDMA)
21.4.14 Clear DONE Status Bit Register (DMA_CDNE)
The CDNE provides a simple memory-mapped mechanism to clear the DONE bit in the
TCD of the given channel. The data value on a register write causes the DONE bit in the
corresponding transfer control descriptor to be cleared. Setting the CADN bit provides a
global clear function, forcing all DONE bits to be cleared. If the NOP bit is set, the
command is ignored. This allows you to write multiple-byte registers as a 32-bit word.
Reads of this register return all zeroes.
Address: 2C0_0000h base + 1Ch offset = 2C0_001Ch
Bit 0 1 2 3 4 5 6 7
Read 0 0 0
Write NOP CADN 0 CDNE
Reset 0 0 0 0 0 0 0 0
DMA_CDNE field descriptions
Field Description
0 No Op enable
NOP
0 Normal operation
1 No operation, ignore the other bits in this register
1 Clears All DONE Bits
CADN
0 Clears only the TCDn_CSR[DONE] bit specified in the CDNE field
1 Clears all bits in TCDn_CSR[DONE]
2 This field is reserved.
Reserved
3–7 Clear DONE Bit
CDNE
Clears the corresponding bit in TCDn_CSR[DONE]
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 961
Memory map/register definition
21.4.15 Set START Bit Register (DMA_SSRT)
The SSRT provides a simple memory-mapped mechanism to set the START bit in the
TCD of the given channel. The data value on a register write causes the START bit in the
corresponding transfer control descriptor to be set. Setting the SAST bit provides a global
set function, forcing all START bits to be set. If the NOP bit is set, the command is
ignored. This allows you to write multiple-byte registers as a 32-bit word. Reads of this
register return all zeroes.
Address: 2C0_0000h base + 1Dh offset = 2C0_001Dh
Bit 0 1 2 3 4 5 6 7
Read 0 0 0
Write NOP SAST 0 SSRT
Reset 0 0 0 0 0 0 0 0
DMA_SSRT field descriptions
Field Description
0 No Op enable
NOP
0 Normal operation
1 No operation, ignore the other bits in this register
1 Set All START Bits (activates all channels)
SAST
0 Set only the TCDn_CSR[START] bit specified in the SSRT field
1 Set all bits in TCDn_CSR[START]
2 This field is reserved.
Reserved
3–7 Set START Bit
SSRT
Sets the corresponding bit in TCDn_CSR[START]
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
962 NXP Semiconductors
Chapter 21 Enhanced Direct Memory Access (eDMA)
21.4.16 Clear Error Register (DMA_CERR)
The CERR provides a simple memory-mapped mechanism to clear a given bit in the ERR
to disable the error condition flag for a given channel. The given value on a register write
causes the corresponding bit in the ERR to be cleared. Setting the CAEI bit provides a
global clear function, forcing the ERR contents to be cleared, clearing all channel error
indicators. If the NOP bit is set, the command is ignored. This allows you to write
multiple-byte registers as a 32-bit word. Reads of this register return all zeroes.
Address: 2C0_0000h base + 1Eh offset = 2C0_001Eh
Bit 0 1 2 3 4 5 6 7
Read 0 0 0
Write NOP CAEI 0 CERR
Reset 0 0 0 0 0 0 0 0
DMA_CERR field descriptions
Field Description
0 No Op enable
NOP
0 Normal operation
1 No operation, ignore the other bits in this register
1 Clear All Error Indicators
CAEI
0 Clear only the ERR bit specified in the CERR field
1 Clear all bits in ERR
2 This field is reserved.
Reserved
3–7 Clear Error Indicator
CERR
Clears the corresponding bit in ERR
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 963
Memory map/register definition
21.4.17 Clear Interrupt Request Register (DMA_CINT)
The CINT provides a simple, memory-mapped mechanism to clear a given bit in the INT
to disable the interrupt request for a given channel. The given value on a register write
causes the corresponding bit in the INT to be cleared. Setting the CAIR bit provides a
global clear function, forcing the entire contents of the INT to be cleared, disabling all
DMA interrupt requests. If the NOP bit is set, the command is ignored. This allows you
to write multiple-byte registers as a 32-bit word. Reads of this register return all zeroes.
Address: 2C0_0000h base + 1Fh offset = 2C0_001Fh
Bit 0 1 2 3 4 5 6 7
Read 0 0 0
Write NOP CAIR 0 CINT
Reset 0 0 0 0 0 0 0 0
DMA_CINT field descriptions
Field Description
0 No Op enable
NOP
0 Normal operation
1 No operation, ignore the other bits in this register
1 Clear All Interrupt Requests
CAIR
0 Clear only the INT bit specified in the CINT field
1 Clear all bits in INT
2 This field is reserved.
Reserved
3–7 Clear Interrupt Request
CINT
Clears the corresponding bit in INT
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
964 NXP Semiconductors
Chapter 21 Enhanced Direct Memory Access (eDMA)
21.4.18 Interrupt Request Register (DMA_INT)
The INT register provides a bit map for the 32 channels signaling the presence of an
interrupt request for each channel. Depending on the appropriate bit setting in the
transfer-control descriptors, the eDMA engine generates an interrupt on data transfer
completion. The outputs of this register are directly routed to the interrupt controller.
During the interrupt-service routine associated with any given channel, it is the
software’s responsibility to clear the appropriate bit, negating the interrupt request.
Typically, a write to the CINT register in the interrupt service routine is used for this
purpose.
The state of any given channel’s interrupt request is directly affected by writes to this
register; it is also affected by writes to the CINT register. On writes to INT, a 1 in any bit
position clears the corresponding channel’s interrupt request. A zero in any bit position
has no affect on the corresponding channel’s current interrupt status. The CINT register is
provided so the interrupt request for a single channel can easily be cleared without the
need to perform a read-modify-write sequence to the INT register.
Address: 2C0_0000h base + 24h offset = 2C0_0024h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
INT31
INT30
INT29
INT28
INT27
INT26
INT25
INT24
INT23
INT22
INT21
INT20
INT19
INT18
INT17
INT16
R
W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
INT15
INT14
INT13
INT12
INT11
INT10
INT9
INT8
INT7
INT6
INT5
INT4
INT3
INT2
INT1
INT0
R
W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_INT field descriptions
Field Description
0 Interrupt Request 31
INT31
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 965
Memory map/register definition
DMA_INT field descriptions (continued)
Field Description
0 The interrupt request for corresponding channel is cleared
1 The interrupt request for corresponding channel is active
1 Interrupt Request 30
INT30
0 The interrupt request for corresponding channel is cleared
1 The interrupt request for corresponding channel is active
2 Interrupt Request 29
INT29
0 The interrupt request for corresponding channel is cleared
1 The interrupt request for corresponding channel is active
3 Interrupt Request 28
INT28
0 The interrupt request for corresponding channel is cleared
1 The interrupt request for corresponding channel is active
4 Interrupt Request 27
INT27
0 The interrupt request for corresponding channel is cleared
1 The interrupt request for corresponding channel is active
5 Interrupt Request 26
INT26
0 The interrupt request for corresponding channel is cleared
1 The interrupt request for corresponding channel is active
6 Interrupt Request 25
INT25
0 The interrupt request for corresponding channel is cleared
1 The interrupt request for corresponding channel is active
7 Interrupt Request 24
INT24
0 The interrupt request for corresponding channel is cleared
1 The interrupt request for corresponding channel is active
8 Interrupt Request 23
INT23
0 The interrupt request for corresponding channel is cleared
1 The interrupt request for corresponding channel is active
9 Interrupt Request 22
INT22
0 The interrupt request for corresponding channel is cleared
1 The interrupt request for corresponding channel is active
10 Interrupt Request 21
INT21
0 The interrupt request for corresponding channel is cleared
1 The interrupt request for corresponding channel is active
11 Interrupt Request 20
INT20
0 The interrupt request for corresponding channel is cleared
1 The interrupt request for corresponding channel is active
12 Interrupt Request 19
INT19
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
966 NXP Semiconductors
Chapter 21 Enhanced Direct Memory Access (eDMA)
DMA_INT field descriptions (continued)
Field Description
0 The interrupt request for corresponding channel is cleared
1 The interrupt request for corresponding channel is active
13 Interrupt Request 18
INT18
0 The interrupt request for corresponding channel is cleared
1 The interrupt request for corresponding channel is active
14 Interrupt Request 17
INT17
0 The interrupt request for corresponding channel is cleared
1 The interrupt request for corresponding channel is active
15 Interrupt Request 16
INT16
0 The interrupt request for corresponding channel is cleared
1 The interrupt request for corresponding channel is active
16 Interrupt Request 15
INT15
0 The interrupt request for corresponding channel is cleared
1 The interrupt request for corresponding channel is active
17 Interrupt Request 14
INT14
0 The interrupt request for corresponding channel is cleared
1 The interrupt request for corresponding channel is active
18 Interrupt Request 13
INT13
0 The interrupt request for corresponding channel is cleared
1 The interrupt request for corresponding channel is active
19 Interrupt Request 12
INT12
0 The interrupt request for corresponding channel is cleared
1 The interrupt request for corresponding channel is active
20 Interrupt Request 11
INT11
0 The interrupt request for corresponding channel is cleared
1 The interrupt request for corresponding channel is active
21 Interrupt Request 10
INT10
0 The interrupt request for corresponding channel is cleared
1 The interrupt request for corresponding channel is active
22 Interrupt Request 9
INT9
0 The interrupt request for corresponding channel is cleared
1 The interrupt request for corresponding channel is active
23 Interrupt Request 8
INT8
0 The interrupt request for corresponding channel is cleared
1 The interrupt request for corresponding channel is active
24 Interrupt Request 7
INT7
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 967
Memory map/register definition
DMA_INT field descriptions (continued)
Field Description
0 The interrupt request for corresponding channel is cleared
1 The interrupt request for corresponding channel is active
25 Interrupt Request 6
INT6
0 The interrupt request for corresponding channel is cleared
1 The interrupt request for corresponding channel is active
26 Interrupt Request 5
INT5
0 The interrupt request for corresponding channel is cleared
1 The interrupt request for corresponding channel is active
27 Interrupt Request 4
INT4
0 The interrupt request for corresponding channel is cleared
1 The interrupt request for corresponding channel is active
28 Interrupt Request 3
INT3
0 The interrupt request for corresponding channel is cleared
1 The interrupt request for corresponding channel is active
29 Interrupt Request 2
INT2
0 The interrupt request for corresponding channel is cleared
1 The interrupt request for corresponding channel is active
30 Interrupt Request 1
INT1
0 The interrupt request for corresponding channel is cleared
1 The interrupt request for corresponding channel is active
31 Interrupt Request 0
INT0
0 The interrupt request for corresponding channel is cleared
1 The interrupt request for corresponding channel is active
21.4.19 Error Register (DMA_ERR)
The ERR provides a bit map for the 32 channels, signaling the presence of an error for
each channel. The eDMA engine signals the occurrence of an error condition by setting
the appropriate bit in this register. The outputs of this register are enabled by the contents
of the EEI, then logically summed across groups of 16 and 32 channels to form several
group error interrupt requests, which are then routed to the interrupt controller. During
the execution of the interrupt-service routine associated with any DMA errors, it is
software’s responsibility to clear the appropriate bit, negating the error-interrupt request.
Typically, a write to the CERR in the interrupt-service routine is used for this purpose.
The normal DMA channel completion indicators (setting the transfer control descriptor
DONE flag and the possible assertion of an interrupt request) are not affected when an
error is detected.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
968 NXP Semiconductors
Chapter 21 Enhanced Direct Memory Access (eDMA)
The contents of this register can also be polled because a non-zero value indicates the
presence of a channel error regardless of the state of the EEI. The state of any given
channel’s error indicators is affected by writes to this register; it is also affected by writes
to the CERR. On writes to the ERR, a one in any bit position clears the corresponding
channel’s error status. A zero in any bit position has no affect on the corresponding
channel’s current error status. The CERR is provided so the error indicator for a single
channel can easily be cleared.
Address: 2C0_0000h base + 2Ch offset = 2C0_002Ch
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
ERR31
ERR30
ERR29
ERR28
ERR27
ERR26
ERR25
ERR24
ERR23
ERR22
ERR21
ERR20
ERR19
ERR18
ERR17
ERR16
R
W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
ERR15
ERR14
ERR13
ERR12
ERR11
ERR10
ERR9
ERR8
ERR7
ERR6
ERR5
ERR4
ERR3
ERR2
ERR1
ERR0
R
W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_ERR field descriptions
Field Description
0 Error In Channel 31
ERR31
0 An error in this channel has not occurred
1 An error in this channel has occurred
1 Error In Channel 30
ERR30
0 An error in this channel has not occurred
1 An error in this channel has occurred
2 Error In Channel 29
ERR29
0 An error in this channel has not occurred
1 An error in this channel has occurred
3 Error In Channel 28
ERR28
0 An error in this channel has not occurred
1 An error in this channel has occurred
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 969
Memory map/register definition
DMA_ERR field descriptions (continued)
Field Description
4 Error In Channel 27
ERR27
0 An error in this channel has not occurred
1 An error in this channel has occurred
5 Error In Channel 26
ERR26
0 An error in this channel has not occurred
1 An error in this channel has occurred
6 Error In Channel 25
ERR25
0 An error in this channel has not occurred
1 An error in this channel has occurred
7 Error In Channel 24
ERR24
0 An error in this channel has not occurred
1 An error in this channel has occurred
8 Error In Channel 23
ERR23
0 An error in this channel has not occurred
1 An error in this channel has occurred
9 Error In Channel 22
ERR22
0 An error in this channel has not occurred
1 An error in this channel has occurred
10 Error In Channel 21
ERR21
0 An error in this channel has not occurred
1 An error in this channel has occurred
11 Error In Channel 20
ERR20
0 An error in this channel has not occurred
1 An error in this channel has occurred
12 Error In Channel 19
ERR19
0 An error in this channel has not occurred
1 An error in this channel has occurred
13 Error In Channel 18
ERR18
0 An error in this channel has not occurred
1 An error in this channel has occurred
14 Error In Channel 17
ERR17
0 An error in this channel has not occurred
1 An error in this channel has occurred
15 Error In Channel 16
ERR16
0 An error in this channel has not occurred
1 An error in this channel has occurred
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
970 NXP Semiconductors
Chapter 21 Enhanced Direct Memory Access (eDMA)
DMA_ERR field descriptions (continued)
Field Description
16 Error In Channel 15
ERR15
0 An error in this channel has not occurred
1 An error in this channel has occurred
17 Error In Channel 14
ERR14
0 An error in this channel has not occurred
1 An error in this channel has occurred
18 Error In Channel 13
ERR13
0 An error in this channel has not occurred
1 An error in this channel has occurred
19 Error In Channel 12
ERR12
0 An error in this channel has not occurred
1 An error in this channel has occurred
20 Error In Channel 11
ERR11
0 An error in this channel has not occurred
1 An error in this channel has occurred
21 Error In Channel 10
ERR10
0 An error in this channel has not occurred
1 An error in this channel has occurred
22 Error In Channel 9
ERR9
0 An error in this channel has not occurred
1 An error in this channel has occurred
23 Error In Channel 8
ERR8
0 An error in this channel has not occurred
1 An error in this channel has occurred
24 Error In Channel 7
ERR7
0 An error in this channel has not occurred
1 An error in this channel has occurred
25 Error In Channel 6
ERR6
0 An error in this channel has not occurred
1 An error in this channel has occurred
26 Error In Channel 5
ERR5
0 An error in this channel has not occurred
1 An error in this channel has occurred
27 Error In Channel 4
ERR4
0 An error in this channel has not occurred
1 An error in this channel has occurred
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 971
Memory map/register definition
DMA_ERR field descriptions (continued)
Field Description
28 Error In Channel 3
ERR3
0 An error in this channel has not occurred
1 An error in this channel has occurred
29 Error In Channel 2
ERR2
0 An error in this channel has not occurred
1 An error in this channel has occurred
30 Error In Channel 1
ERR1
0 An error in this channel has not occurred
1 An error in this channel has occurred
31 Error In Channel 0
ERR0
0 An error in this channel has not occurred
1 An error in this channel has occurred
21.4.20 Hardware Request Status Register (DMA_HRS)
The HRS register provides a bit map for the DMA channels, signaling the presence of a
hardware request for each channel. The hardware request status bits reflect the current
state of the register and qualified (via the ERQ fields) DMA request signals as seen by
the DMA’s arbitration logic. This view into the hardware request signals may be used for
debug purposes.
NOTE
These bits reflect the state of the request as seen by the
arbitration logic. Therefore, this status is affected by the ERQ
bits.
Address: 2C0_0000h base + 34h offset = 2C0_0034h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
HRS31
HRS30
HRS29
HRS28
HRS27
HRS26
HRS25
HRS24
HRS23
HRS22
HRS21
HRS20
HRS19
HRS18
HRS17
HRS16
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
972 NXP Semiconductors
Chapter 21 Enhanced Direct Memory Access (eDMA)
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
HRS15
HRS14
HRS13
HRS12
HRS11
HRS10
HRS9
HRS8
HRS7
HRS6
HRS5
HRS4
HRS3
HRS2
HRS1
HRS0
R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_HRS field descriptions
Field Description
0 Hardware Request Status Channel 31
HRS31
The HRS bit for its respective channel remains asserted for the period when a Hardware Request is
Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically
cleared by hardware.
0 A hardware service request for channel 31 is not present
1 A hardware service request for channel 31 is present
1 Hardware Request Status Channel 30
HRS30
The HRS bit for its respective channel remains asserted for the period when a Hardware Request is
Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically
cleared by hardware.
0 A hardware service request for channel 30 is not present
1 A hardware service request for for channel 30 is present
2 Hardware Request Status Channel 29
HRS29
The HRS bit for its respective channel remains asserted for the period when a Hardware Request is
Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically
cleared by hardware.
0 A hardware service request for channel 29 is not preset
1 A hardware service request for channel 29 is present
3 Hardware Request Status Channel 28
HRS28
The HRS bit for its respective channel remains asserted for the period when a Hardware Request is
Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically
cleared by hardware.
0 A hardware service request for channel 28 is not present
1 A hardware service request for channel 28 is present
4 Hardware Request Status Channel 27
HRS27
The HRS bit for its respective channel remains asserted for the period when a Hardware Request is
Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically
cleared by hardware.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 973
Memory map/register definition
DMA_HRS field descriptions (continued)
Field Description
0 A hardware service request for channel 27 is not present
1 A hardware service request for channel 27 is present
5 Hardware Request Status Channel 26
HRS26
The HRS bit for its respective channel remains asserted for the period when a Hardware Request is
Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically
cleared by hardware.
0 A hardware service request for channel 26 is not present
1 A hardware service request for channel 26 is present
6 Hardware Request Status Channel 25
HRS25
The HRS bit for its respective channel remains asserted for the period when a Hardware Request is
Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically
cleared by hardware.
0 A hardware service request for channel 25 is not present
1 A hardware service request for channel 25 is present
7 Hardware Request Status Channel 24
HRS24
The HRS bit for its respective channel remains asserted for the period when a Hardware Request is
Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically
cleared by hardware.
0 A hardware service request for channel 24 is not present
1 A hardware service request for channel 24 is present
8 Hardware Request Status Channel 23
HRS23
The HRS bit for its respective channel remains asserted for the period when a Hardware Request is
Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically
cleared by hardware.
0 A hardware service request for channel 23 is not present
1 A hardware service request for channel 23 is present
9 Hardware Request Status Channel 22
HRS22
The HRS bit for its respective channel remains asserted for the period when a Hardware Request is
Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically
cleared by hardware.
0 A hardware service request for channel 22 is not present
1 A hardware service request for channel 22 is present
10 Hardware Request Status Channel 21
HRS21
The HRS bit for its respective channel remains asserted for the period when a Hardware Request is
Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically
cleared by hardware.
0 A hardware service request for channel 21 is not present
1 A hardware service request for channel 21 is present
11 Hardware Request Status Channel 20
HRS20
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
974 NXP Semiconductors
Chapter 21 Enhanced Direct Memory Access (eDMA)
DMA_HRS field descriptions (continued)
Field Description
The HRS bit for its respective channel remains asserted for the period when a Hardware Request is
Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically
cleared by hardware.
0 A hardware service request for channel 20 is not present
1 A hardware service request for channel 20 is present
12 Hardware Request Status Channel 19
HRS19
The HRS bit for its respective channel remains asserted for the period when a Hardware Request is
Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically
cleared by hardware.
0 A hardware service request for channel 19 is not present
1 A hardware service request for channel 19 is present
13 Hardware Request Status Channel 18
HRS18
The HRS bit for its respective channel remains asserted for the period when a Hardware Request is
Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically
cleared by hardware.
0 A hardware service request for channel 18 is not present
1 A hardware service request for channel 18 is present
14 Hardware Request Status Channel 17
HRS17
The HRS bit for its respective channel remains asserted for the period when a Hardware Request is
Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically
cleared by hardware.
0 A hardware service request for channel 17 is not present
1 A hardware service request for channel 17 is present
15 Hardware Request Status Channel 16
HRS16
The HRS bit for its respective channel remains asserted for the period when a Hardware Request is
Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically
cleared by hardware.
0 A hardware service request for channel 16 is not present
1 A hardware service request for channel 16 is present
16 Hardware Request Status Channel 15
HRS15
The HRS bit for its respective channel remains asserted for the period when a Hardware Request is
Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically
cleared by hardware.
0 A hardware service request for channel 15 is not present
1 A hardware service request for channel 15 is present
17 Hardware Request Status Channel 14
HRS14
The HRS bit for its respective channel remains asserted for the period when a Hardware Request is
Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically
cleared by hardware.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 975
Memory map/register definition
DMA_HRS field descriptions (continued)
Field Description
0 A hardware service request for channel 14 is not present
1 A hardware service request for channel 14 is present
18 Hardware Request Status Channel 13
HRS13
The HRS bit for its respective channel remains asserted for the period when a Hardware Request is
Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically
cleared by hardware.
0 A hardware service request for channel 13 is not present
1 A hardware service request for channel 13 is present
19 Hardware Request Status Channel 12
HRS12
The HRS bit for its respective channel remains asserted for the period when a Hardware Request is
Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically
cleared by hardware.
0 A hardware service request for channel 12 is not present
1 A hardware service request for channel 12 is present
20 Hardware Request Status Channel 11
HRS11
The HRS bit for its respective channel remains asserted for the period when a Hardware Request is
Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically
cleared by hardware.
0 A hardware service request for channel 11 is not present
1 A hardware service request for channel 11 is present
21 Hardware Request Status Channel 10
HRS10
The HRS bit for its respective channel remains asserted for the period when a Hardware Request is
Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically
cleared by hardware.
0 A hardware service request for channel 10 is not present
1 A hardware service request for channel 10 is present
22 Hardware Request Status Channel 9
HRS9
The HRS bit for its respective channel remains asserted for the period when a Hardware Request is
Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically
cleared by hardware.
0 A hardware service request for channel 9 is not present
1 A hardware service request for channel 9 is present
23 Hardware Request Status Channel 8
HRS8
The HRS bit for its respective channel remains asserted for the period when a Hardware Request is
Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically
cleared by hardware.
0 A hardware service request for channel 8 is not present
1 A hardware service request for channel 8 is present
24 Hardware Request Status Channel 7
HRS7
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
976 NXP Semiconductors
Chapter 21 Enhanced Direct Memory Access (eDMA)
DMA_HRS field descriptions (continued)
Field Description
The HRS bit for its respective channel remains asserted for the period when a Hardware Request is
Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically
cleared by hardware.
0 A hardware service request for channel 7 is not present
1 A hardware service request for channel 7 is present
25 Hardware Request Status Channel 6
HRS6
The HRS bit for its respective channel remains asserted for the period when a Hardware Request is
Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically
cleared by hardware.
0 A hardware service request for channel 6 is not present
1 A hardware service request for channel 6 is present
26 Hardware Request Status Channel 5
HRS5
The HRS bit for its respective channel remains asserted for the period when a Hardware Request is
Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically
cleared by hardware.
0 A hardware service request for channel 5 is not present
1 A hardware service request for channel 5 is present
27 Hardware Request Status Channel 4
HRS4
The HRS bit for its respective channel remains asserted for the period when a Hardware Request is
Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically
cleared by hardware.
0 A hardware service request for channel 4 is not present
1 A hardware service request for channel 4 is present
28 Hardware Request Status Channel 3
HRS3
The HRS bit for its respective channel remains asserted for the period when a Hardware Request is
Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically
cleared by hardware.
0 A hardware service request for channel 3 is not present
1 A hardware service request for channel 3 is present
29 Hardware Request Status Channel 2
HRS2
The HRS bit for its respective channel remains asserted for the period when a Hardware Request is
Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically
cleared by hardware.
0 A hardware service request for channel 2 is not present
1 A hardware service request for channel 2 is present
30 Hardware Request Status Channel 1
HRS1
The HRS bit for its respective channel remains asserted for the period when a Hardware Request is
Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically
cleared by hardware.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 977
Memory map/register definition
DMA_HRS field descriptions (continued)
Field Description
0 A hardware service request for channel 1 is not present
1 A hardware service request for channel 1 is present
31 Hardware Request Status Channel 0
HRS0
The HRS bit for its respective channel remains asserted for the period when a Hardware Request is
Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically
cleared by hardware.
0 A hardware service request for channel 0 is not present
1 A hardware service request for channel 0 is present
21.4.21 Channel n Priority Register (DMA_DCHPRIn)
When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the contents of these
registers define the unique priorities associated with each channel within a group. The
channel priorities are evaluated by numeric value; for example, 0 is the lowest priority, 1
is the next higher priority, then 2, 3, etc. Software must program the channel priorities
with unique values; otherwise, a configuration error is reported. The range of the priority
value is limited to the values of 0 through 15. When read, the GRPPRI bits of the
DCHPRIn register reflect the current priority level of the group of channels in which the
corresponding channel resides. GRPPRI bits are not affected by writes to the DCHPRIn
registers. The group priority is assigned in the DMA control register.
Address: 2C0_0000h base + 100h offset + (1d × i), where i=0d to 31d
Bit 0 1 2 3 4 5 6 7
Read GRPPRI
ECP DPA CHPRI
Write
Reset 0 0 * * * * * *
* Notes:
• CHPRI field: See bit field description.
• GRPPRI field: See bit field description.
DMA_DCHPRIn field descriptions
Field Description
0 Enable Channel Preemption.
ECP
0 Channel n cannot be suspended by a higher priority channel’s service request.
1 Channel n can be temporarily suspended by the service request of a higher priority channel.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
978 NXP Semiconductors
Chapter 21 Enhanced Direct Memory Access (eDMA)
DMA_DCHPRIn field descriptions (continued)
Field Description
1 Disable Preempt Ability.
DPA
0 Channel n can suspend a lower priority channel.
1 Channel n cannot suspend any channel, regardless of channel priority.
2–3 Channel n Current Group Priority
GRPPRI
Group priority assigned to this channel group when fixed-priority arbitration is enabled. This field is read-
only; writes are ignored.
NOTE: Reset value for the group and channel priority fields, GRPPRI and CHPRI, is equal to the
corresponding channel number for each priority register, that is, DCHPRI31[GRPPRI] = 0b01 and
DCHPRI31[CHPRI] equals 0b1111.
4–7 Channel n Arbitration Priority
CHPRI
Channel priority when fixed-priority arbitration is enabled
NOTE: Reset value for the group and channel priority fields, GRPPRI and CHPRI, is equal to the
corresponding channel number for each priority register, that is, DCHPRI31[GRPPRI] = 0b01 and
DCHPRI31[CHPRI] = 0b01111.
21.4.22 TCD Source Address (DMA_TCDn_SADDR)
Address: 2C0_0000h base + 1000h offset + (32d × i), where i=0d to 31d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
SADDR
Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
* Notes:
• x = Undefined at reset.
DMA_TCDn_SADDR field descriptions
Field Description
0–31 Source Address
SADDR
Memory address pointing to the source data.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 979
Memory map/register definition
21.4.23 TCD Signed Source Address Offset (DMA_TCDn_SOFF)
Address: 2C0_0000h base + 1004h offset + (32d × i), where i=0d to 31d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Read SOFF
Write
Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
* Notes:
• x = Undefined at reset.
DMA_TCDn_SOFF field descriptions
Field Description
0–15 Source address signed offset
SOFF
Sign-extended offset applied to the current source address to form the next-state value as each source
read is completed.
21.4.24 TCD Transfer Attributes (DMA_TCDn_ATTR)
Address: 2C0_0000h base + 1006h offset + (32d × i), where i=0d to 31d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Read SMOD SSIZE DMOD DSIZE
Write
Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
* Notes:
• x = Undefined at reset.
DMA_TCDn_ATTR field descriptions
Field Description
0–4 Source Address Modulo
SMOD
0 Source address modulo feature is disabled
≠0 This value defines a specific address range specified to be the value after SADDR + SOFF
calculation is performed on the original register value. Setting this field provides the ability to
implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue
should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value
for the queue, freezing the desired number of upper address bits. The value programmed into this
field specifies the number of lower address bits allowed to change. For a circular queue application,
the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD
function constraining the addresses to a 0-modulo-size range.
5–7 Source data transfer size
SSIZE
NOTE: Using a Reserved value causes a configuration error.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
980 NXP Semiconductors
Chapter 21 Enhanced Direct Memory Access (eDMA)
DMA_TCDn_ATTR field descriptions (continued)
Field Description
The eDMA defaults to privileged data access for all transactions.
000 8-bit
001 16-bit
010 32-bit
011 64-bit
100 Reserved
101 32-byte burst (4 beats of 64 bits)
110 Reserved
111 Reserved
8–12 Destination Address Modulo
DMOD
See the SMOD definition
13–15 Destination data transfer size
DSIZE
See the SSIZE definition
21.4.25 TCD Minor Byte Count (Minor Loop Mapping Disabled)
(DMA_TCDn_NBYTES_MLNO)
This register, or one of the next two registers (TCD_NBYTES_MLOFFNO,
TCD_NBYTES_MLOFFYES), defines the number of bytes to transfer per request.
Which register to use depends on whether minor loop mapping is disabled, enabled but
not used for this channel, or enabled and used.
TCD word 2 is defined as follows if:
• Minor loop mapping is disabled (CR[EMLM] = 0)
If minor loop mapping is enabled, see the TCD_NBYTES_MLOFFNO and
TCD_NBYTES_MLOFFYES register descriptions for the definition of TCD word 2.
Address: 2C0_0000h base + 1008h offset + (32d × i), where i=0d to 31d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
NBYTES
Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
* Notes:
• x = Undefined at reset.
DMA_TCDn_NBYTES_MLNO field descriptions
Field Description
0–31 Minor Byte Transfer Count
NBYTES
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 981
Memory map/register definition
DMA_TCDn_NBYTES_MLNO field descriptions (continued)
Field Description
Number of bytes to be transferred in each service request of the channel. As a channel activates, the
appropriate TCD contents load into the eDMA engine, and the appropriate reads and writes perform until
the minor byte transfer count has transferred. This is an indivisible operation and cannot be halted. It can,
however, be stalled by using the bandwidth control field, or via preemption. After the minor count is
exhausted, the SADDR and DADDR values are written back into the TCD memory, the major iteration
count is decremented and restored to the TCD memory. If the major iteration count is completed,
additional processing is performed.
NOTE: An NBYTES value of 0x0000_0000 is interpreted as a 4 GB transfer.
21.4.26 TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled
and Offset Disabled) (DMA_TCDn_NBYTES_MLOFFNO)
One of three registers (this register, TCD_NBYTES_MLNO, or
TCD_NBYTES_MLOFFYES), defines the number of bytes to transfer per request.
Which register to use depends on whether minor loop mapping is disabled, enabled but
not used for this channel, or enabled and used.
TCD word 2 is defined as follows if:
• Minor loop mapping is enabled (CR[EMLM] = 1) and
• SMLOE = 0 and DMLOE = 0
If minor loop mapping is enabled and SMLOE or DMLOE is set, then refer to the
TCD_NBYTES_MLOFFYES register description. If minor loop mapping is disabled,
then refer to the TCD_NBYTES_MLNO register description.
Address: 2C0_0000h base + 1008h offset + (32d × i), where i=0d to 31d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
DMLOE
SMLOE
NBYTES
W
Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
NBYTES
W
Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
* Notes:
• x = Undefined at reset.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
982 NXP Semiconductors
Chapter 21 Enhanced Direct Memory Access (eDMA)
DMA_TCDn_NBYTES_MLOFFNO field descriptions
Field Description
0 Source Minor Loop Offset Enable
SMLOE
Selects whether the minor loop offset is applied to the source address upon minor loop completion.
0 The minor loop offset is not applied to the SADDR
1 The minor loop offset is applied to the SADDR
1 Destination Minor Loop Offset enable
DMLOE
Selects whether the minor loop offset is applied to the destination address upon minor loop completion.
0 The minor loop offset is not applied to the DADDR
1 The minor loop offset is applied to the DADDR
2–31 Minor Byte Transfer Count
NBYTES
Number of bytes to be transferred in each service request of the channel.
As a channel activates, the appropriate TCD contents load into the eDMA engine, and the appropriate
reads and writes perform until the minor byte transfer count has transferred. This is an indivisible operation
and cannot be halted. It can, however, be stalled by using the bandwidth control field, or via preemption.
After the minor count is exhausted, the SADDR and DADDR values are written back into the TCD
memory, the major iteration count is decremented and restored to the TCD memory. If the major iteration
count is completed, additional processing is performed.
21.4.27 TCD Signed Minor Loop Offset (Minor Loop Mapping and
Offset Enabled) (DMA_TCDn_NBYTES_MLOFFYES)
One of three registers (this register, TCD_NBYTES_MLNO, or
TCD_NBYTES_MLOFFNO), defines the number of bytes to transfer per request. Which
register to use depends on whether minor loop mapping is disabled, enabled but not used
for this channel, or enabled and used.
TCD word 2 is defined as follows if:
• Minor loop mapping is enabled (CR[EMLM] = 1) and
• Minor loop offset is enabled (SMLOE or DMLOE = 1)
If minor loop mapping is enabled and SMLOE and DMLOE are cleared, then refer to the
TCD_NBYTES_MLOFFNO register description. If minor loop mapping is disabled, then
refer to the TCD_NBYTES_MLNO register description.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 983
Memory map/register definition
Address: 2C0_0000h base + 1008h offset + (32d × i), where i=0d to 31d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DMLOE
SMLOE
MLOFF
W
Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
MLOFF NBYTES
W
Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
* Notes:
• x = Undefined at reset.
DMA_TCDn_NBYTES_MLOFFYES field descriptions
Field Description
0 Source Minor Loop Offset Enable
SMLOE
Selects whether the minor loop offset is applied to the source address upon minor loop completion.
0 The minor loop offset is not applied to the SADDR
1 The minor loop offset is applied to the SADDR
1 Destination Minor Loop Offset enable
DMLOE
Selects whether the minor loop offset is applied to the destination address upon minor loop completion.
0 The minor loop offset is not applied to the DADDR
1 The minor loop offset is applied to the DADDR
2–21 If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or
MLOFF destination address to form the next-state value after the minor loop completes.
22–31 Minor Byte Transfer Count
NBYTES
Number of bytes to be transferred in each service request of the channel.
As a channel activates, the appropriate TCD contents load into the eDMA engine, and the appropriate
reads and writes perform until the minor byte transfer count has transferred. This is an indivisible operation
and cannot be halted. It can, however, be stalled by using the bandwidth control field, or via preemption.
After the minor count is exhausted, the SADDR and DADDR values are written back into the TCD
memory, the major iteration count is decremented and restored to the TCD memory. If the major iteration
count is completed, additional processing is performed.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
984 NXP Semiconductors
Chapter 21 Enhanced Direct Memory Access (eDMA)
21.4.28 TCD Last Source Address Adjustment (DMA_TCDn_SLAST)
Address: 2C0_0000h base + 100Ch offset + (32d × i), where i=0d to 31d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
SLAST
Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
* Notes:
• x = Undefined at reset.
DMA_TCDn_SLAST field descriptions
Field Description
0–31 Last Source Address Adjustment
SLAST
Adjustment value added to the source address at the completion of the major iteration count. This value
can be applied to restore the source address to the initial value, or adjust the address to reference the
next data structure.
This register uses two's complement notation; the overflow bit is discarded.
21.4.29 TCD Destination Address (DMA_TCDn_DADDR)
Address: 2C0_0000h base + 1010h offset + (32d × i), where i=0d to 31d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
DADDR
Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
* Notes:
• x = Undefined at reset.
DMA_TCDn_DADDR field descriptions
Field Description
0–31 Destination Address
DADDR
Memory address pointing to the destination data.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 985
Memory map/register definition
21.4.30 TCD Signed Destination Address Offset (DMA_TCDn_DOFF)
Address: 2C0_0000h base + 1014h offset + (32d × i), where i=0d to 31d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Read DOFF
Write
Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
* Notes:
• x = Undefined at reset.
DMA_TCDn_DOFF field descriptions
Field Description
0–15 Destination Address Signed Offset
DOFF
Sign-extended offset applied to the current destination address to form the next-state value as each
destination write is completed.
21.4.31 TCD Current Minor Loop Link, Major Loop Count (Channel
Linking Enabled) (DMA_TCDn_CITER_ELINKYES)
If TCDn_CITER[ELINK] is set, the TCDn_CITER register is defined as follows.
Address: 2C0_0000h base + 1016h offset + (32d × i), where i=0d to 31d
Bit 0 1 2 3 4 5 6 7
Read
ELINK LINKCH CITER
Write 0
Reset x* x* x* x* x* x* x* x*
Bit 8 9 10 11 12 13 14 15
Read CITER
Write
Reset x* x* x* x* x* x* x* x*
* Notes:
• x = Undefined at reset.
DMA_TCDn_CITER_ELINKYES field descriptions
Field Description
0 Enable channel-to-channel linking on minor-loop complete
ELINK
As the channel completes the minor loop, this flag enables linking to another channel, defined by the
LINKCH field. The link target channel initiates a channel service request via an internal mechanism that
sets the TCDn_CSR[START] bit of the specified channel.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
986 NXP Semiconductors
Chapter 21 Enhanced Direct Memory Access (eDMA)
DMA_TCDn_CITER_ELINKYES field descriptions (continued)
Field Description
If channel linking is disabled, the CITER value is extended to 15 bits in place of a link channel number. If
the major loop is exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel
linking.
NOTE: This bit must be equal to the BITER[ELINK] bit; otherwise, a configuration error is reported.
0 The channel-to-channel linking is disabled
1 The channel-to-channel linking is enabled
1 This field is reserved.
Reserved
2–6 Minor Loop Link Channel Number
LINKCH
If channel-to-channel linking is enabled (ELINK = 1), then after the minor loop is exhausted, the eDMA
engine initiates a channel service request to the channel defined by this field by setting that channel’s
TCDn_CSR[START] bit.
7–15 Current Major Iteration Count
CITER
This 9-bit (ELINK = 1) or 15-bit (ELINK = 0) count represents the current major loop count for the channel.
It is decremented each time the minor loop is completed and updated in the transfer control descriptor
memory. After the major iteration count is exhausted, the channel performs a number of operations, for
example, final source and destination address calculations, optionally generating an interrupt to signal
channel completion before reloading the CITER field from the Beginning Iteration Count (BITER) field.
NOTE: When the CITER field is initially loaded by software, it must be set to the same value as that
contained in the BITER field.
NOTE: If the channel is configured to execute a single service request, the initial values of BITER and
CITER should be 0x0001.
21.4.32 TCD Current Minor Loop Link, Major Loop Count (Channel
Linking Disabled) (DMA_TCDn_CITER_ELINKNO)
If TCDn_CITER[ELINK] is cleared, the TCDn_CITER register is defined as follows.
Address: 2C0_0000h base + 1016h offset + (32d × i), where i=0d to 31d
Bit 0 1 2 3 4 5 6 7
Read ELINK CITER
Write
Reset x* x* x* x* x* x* x* x*
Bit 8 9 10 11 12 13 14 15
Read CITER
Write
Reset x* x* x* x* x* x* x* x*
* Notes:
• x = Undefined at reset.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 987
Memory map/register definition
DMA_TCDn_CITER_ELINKNO field descriptions
Field Description
0 Enable channel-to-channel linking on minor-loop complete
ELINK
As the channel completes the minor loop, this flag enables linking to another channel, defined by the
LINKCH field. The link target channel initiates a channel service request via an internal mechanism that
sets the TCDn_CSR[START] bit of the specified channel.
If channel linking is disabled, the CITER value is extended to 15 bits in place of a link channel number. If
the major loop is exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel
linking.
NOTE: This bit must be equal to the BITER[ELINK] bit; otherwise, a configuration error is reported.
0 The channel-to-channel linking is disabled
1 The channel-to-channel linking is enabled
1–15 Current Major Iteration Count
CITER
This 9-bit (ELINK = 1) or 15-bit (ELINK = 0) count represents the current major loop count for the channel.
It is decremented each time the minor loop is completed and updated in the transfer control descriptor
memory. After the major iteration count is exhausted, the channel performs a number of operations, for
example, final source and destination address calculations, optionally generating an interrupt to signal
channel completion before reloading the CITER field from the Beginning Iteration Count (BITER) field.
NOTE: When the CITER field is initially loaded by software, it must be set to the same value as that
contained in the BITER field.
NOTE: If the channel is configured to execute a single service request, the initial values of BITER and
CITER should be 0x0001.
21.4.33 TCD Last Destination Address Adjustment/Scatter Gather
Address (DMA_TCDn_DLASTSGA)
Address: 2C0_0000h base + 1018h offset + (32d × i), where i=0d to 31d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
DLASTSGA
Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
* Notes:
• x = Undefined at reset.
DMA_TCDn_DLASTSGA field descriptions
Field Description
0–31 Destination last address adjustment or the memory address for the next transfer control descriptor to be
DLASTSGA loaded into this channel (scatter/gather).
If (TCDn_CSR[ESG] = 0) then:
• Adjustment value added to the destination address at the completion of the major iteration count.
This value can apply to restore the destination address to the initial value or adjust the address to
reference the next data structure.
• This field uses two's complement notation for the final destination address adjustment.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
988 NXP Semiconductors
Chapter 21 Enhanced Direct Memory Access (eDMA)
DMA_TCDn_DLASTSGA field descriptions (continued)
Field Description
Otherwise:
• This address points to the beginning of a 0-modulo-32-byte region containing the next transfer
control descriptor to be loaded into this channel. This channel reload is performed as the major
iteration count completes. The scatter/gather address must be 0-modulo-32-byte, otherwise a
configuration error is reported.
21.4.34 TCD Control and Status (DMA_TCDn_CSR)
Address: 2C0_0000h base + 101Ch offset + (32d × i), where i=0d to 31d
Bit 0 1 2 3 4 5 6 7
Read
BWC MAJORLINKCH
Write 0
Reset x* x* x* x* x* x* x* x*
Bit 8 9 10 11 12 13 14 15
Read ACTIVE MAJORELI
DONE ESG DREQ INTHALF INTMAJOR START
Write NK
Reset x* x* x* x* x* x* x* x*
* Notes:
• x = Undefined at reset.
DMA_TCDn_CSR field descriptions
Field Description
0–1 Bandwidth Control
BWC
Throttles the amount of bus bandwidth consumed by the eDMA. Generally, as the eDMA processes the
minor loop, it continuously generates read/write sequences until the minor count is exhausted. This field
forces the eDMA to stall after the completion of each read/write access to control the bus request
bandwidth seen by the crossbar switch.
NOTE: If the source and destination sizes are equal, this field is ignored between the first and second
transfers and after the last write of each minor loop. This behavior is a side effect of reducing
start-up latency.
00 No eDMA engine stalls.
10 eDMA engine stalls for 4 cycles after each R/W.
11 eDMA engine stalls for 8 cycles after each R/W.
2 This field is reserved.
Reserved
3–7 Major Loop Link Channel Number
MAJORLINKCH
If (MAJORELINK = 0) then:
• No channel-to-channel linking, or chaining, is performed after the major loop counter is exhausted.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 989
Memory map/register definition
DMA_TCDn_CSR field descriptions (continued)
Field Description
Otherwise:
• After the major loop counter is exhausted, the eDMA engine initiates a channel service request at
the channel defined by this field by setting that channel’s TCDn_CSR[START] bit.
8 Channel Done
DONE
This flag indicates the eDMA has completed the major loop. The eDMA engine sets it as the CITER count
reaches zero. The software clears it, or the hardware when the channel is activated.
The access of this field is W0C, write-zero-to-clear.
NOTE: This bit must be cleared to write the MAJORELINK or ESG bits.
9 Channel Active
ACTIVE
This flag signals the channel is currently in execution. It is set when channel service begins, and is cleared
by the eDMA as the minor loop completes or when any error condition is detected.
10 Enable channel-to-channel linking on major loop complete
MAJORELINK
As the channel completes the major loop, this flag enables the linking to another channel, defined by
MAJORLINKCH. The link target channel initiates a channel service request via an internal mechanism that
sets the TCDn_CSR[START] bit of the specified channel.
NOTE: To support the dynamic linking coherency model, this field is forced to zero when written to while
the TCDn_CSR[DONE] bit is set.
0 The channel-to-channel linking is disabled.
1 The channel-to-channel linking is enabled.
11 Enable Scatter/Gather Processing
ESG
As the channel completes the major loop, this flag enables scatter/gather processing in the current
channel. If enabled, the eDMA engine uses DLASTSGA as a memory pointer to a 0-modulo-32 address
containing a 32-byte data structure loaded as the transfer control descriptor into the local memory.
NOTE: To support the dynamic scatter/gather coherency model, this field is forced to zero when written
to while the TCDn_CSR[DONE] bit is set.
0 The current channel’s TCD is normal format.
1 The current channel’s TCD specifies a scatter gather format. The DLASTSGA field provides a memory
pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
12 Disable Request
DREQ
If this flag is set, the eDMA hardware automatically clears the corresponding ERQ bit when the current
major iteration count reaches zero.
0 The channel’s ERQ bit is not affected.
1 The channel’s ERQ bit is cleared when the major loop is complete.
13 Enable an interrupt when major counter is half complete.
INTHALF
If this flag is set, the channel generates an interrupt request by setting the appropriate bit in the INT
register when the current major iteration count reaches the halfway point. Specifically, the comparison
performed by the eDMA engine is (CITER == (BITER >> 1)). This halfway point interrupt request is
provided to support double-buffered, also known as ping-pong, schemes or other types of data movement
where the processor needs an early indication of the transfer’s progress.
NOTE: If BITER = 1, do not use INTHALF. Use INTMAJOR instead.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
990 NXP Semiconductors
Chapter 21 Enhanced Direct Memory Access (eDMA)
DMA_TCDn_CSR field descriptions (continued)
Field Description
0 The half-point interrupt is disabled.
1 The half-point interrupt is enabled.
14 Enable an interrupt when major iteration count completes.
INTMAJOR
If this flag is set, the channel generates an interrupt request by setting the appropriate bit in the INT when
the current major iteration count reaches zero.
0 The end-of-major loop interrupt is disabled.
1 The end-of-major loop interrupt is enabled.
15 Channel Start
START
If this flag is set, the channel is requesting service. The eDMA hardware automatically clears this flag after
the channel begins execution.
0 The channel is not explicitly started.
1 The channel is explicitly started via a software initiated service request.
21.4.35 TCD Beginning Minor Loop Link, Major Loop Count (Channel
Linking Enabled) (DMA_TCDn_BITER_ELINKYES)
If the TCDn_BITER[ELINK] bit is set, the TCDn_BITER register is defined as follows.
Address: 2C0_0000h base + 101Eh offset + (32d × i), where i=0d to 31d
Bit 0 1 2 3 4 5 6 7
Read
ELINK LINKCH BITER
Write 0
Reset x* x* x* x* x* x* x* x*
Bit 8 9 10 11 12 13 14 15
Read BITER
Write
Reset x* x* x* x* x* x* x* x*
* Notes:
• x = Undefined at reset.
DMA_TCDn_BITER_ELINKYES field descriptions
Field Description
0 Enables channel-to-channel linking on minor loop complete
ELINK
As the channel completes the minor loop, this flag enables the linking to another channel, defined by
BITER[LINKCH]. The link target channel initiates a channel service request via an internal mechanism that
sets the TCDn_CSR[START] bit of the specified channel. If channel linking disables, the BITER value
extends to 15 bits in place of a link channel number. If the major loop is exhausted, this link mechanism is
suppressed in favor of the MAJORELINK channel linking.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 991
Memory map/register definition
DMA_TCDn_BITER_ELINKYES field descriptions (continued)
Field Description
NOTE: When the software loads the TCD, this field must be set equal to the corresponding CITER field;
otherwise, a configuration error is reported. As the major iteration count is exhausted, the
contents of this field are reloaded into the CITER field.
0 The channel-to-channel linking is disabled
1 The channel-to-channel linking is enabled
1 This field is reserved.
Reserved
2–6 Link Channel Number
LINKCH
If channel-to-channel linking is enabled (ELINK = 1), then after the minor loop is exhausted, the eDMA
engine initiates a channel service request at the channel defined by this field by setting that channel’s
TCDn_CSR[START] bit.
NOTE: When the software loads the TCD, this field must be set equal to the corresponding CITER field;
otherwise, a configuration error is reported. As the major iteration count is exhausted, the
contents of this field are reloaded into the CITER field.
7–15 Starting major iteration count
BITER
As the transfer control descriptor is first loaded by software, this 9-bit (ELINK = 1) or 15-bit (ELINK = 0)
field must be equal to the value in the CITER field. As the major iteration count is exhausted, the contents
of this field are reloaded into the CITER field.
NOTE: When the software loads the TCD, this field must be set equal to the corresponding CITER field;
otherwise, a configuration error is reported. As the major iteration count is exhausted, the
contents of this field are reloaded into the CITER field. If the channel is configured to execute a
single service request, the initial values of BITER and CITER should be 0x0001.
21.4.36 TCD Beginning Minor Loop Link, Major Loop Count (Channel
Linking Disabled) (DMA_TCDn_BITER_ELINKNO)
If the TCDn_BITER[ELINK] bit is cleared, the TCDn_BITER register is defined as
follows.
Address: 2C0_0000h base + 101Eh offset + (32d × i), where i=0d to 31d
Bit 0 1 2 3 4 5 6 7
Read ELINK BITER
Write
Reset x* x* x* x* x* x* x* x*
Bit 8 9 10 11 12 13 14 15
Read BITER
Write
Reset x* x* x* x* x* x* x* x*
* Notes:
• x = Undefined at reset.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
992 NXP Semiconductors
Chapter 21 Enhanced Direct Memory Access (eDMA)
DMA_TCDn_BITER_ELINKNO field descriptions
Field Description
0 Enables channel-to-channel linking on minor loop complete
ELINK
As the channel completes the minor loop, this flag enables the linking to another channel, defined by
BITER[LINKCH]. The link target channel initiates a channel service request via an internal mechanism that
sets the TCDn_CSR[START] bit of the specified channel. If channel linking is disabled, the BITER value
extends to 15 bits in place of a link channel number. If the major loop is exhausted, this link mechanism is
suppressed in favor of the MAJORELINK channel linking.
NOTE: When the software loads the TCD, this field must be set equal to the corresponding CITER field;
otherwise, a configuration error is reported. As the major iteration count is exhausted, the
contents of this field are reloaded into the CITER field.
0 The channel-to-channel linking is disabled
1 The channel-to-channel linking is enabled
1–15 Starting Major Iteration Count
BITER
As the transfer control descriptor is first loaded by software, this 9-bit (ELINK = 1) or 15-bit (ELINK = 0)
field must be equal to the value in the CITER field. As the major iteration count is exhausted, the contents
of this field are reloaded into the CITER field.
NOTE: When the software loads the TCD, this field must be set equal to the corresponding CITER field;
otherwise, a configuration error is reported. As the major iteration count is exhausted, the
contents of this field is reloaded into the CITER field. If the channel is configured to execute a
single service request, the initial values of BITER and CITER should be 0x0001.
21.5 Functional description
The operation of the eDMA is described in the following subsections.
21.5.1 eDMA basic data flow
The basic flow of a data transfer can be partitioned into three segments.
As shown in the following diagram, the first segment involves the channel activation:
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 993
Functional description
eDMA
Write Address
Write Data
0
1
2
Internal Peripheral Bus
Transfer
To/From Crossbar Switch
Control
Descriptor (TCD) n-1
64
eDMA Engine
Program Model/
Read Data
Channel Arbitration
Read Data
Address Path
Control
Data Path
Write Data
Address
eDMA Peripheral
eDMA Done
Request
Figure 21-3. eDMA operation, part 1
This example uses the assertion of the eDMA peripheral request signal to request service
for channel n. Channel activation via software and the TCDn_CSR[START] bit follows
the same basic flow as peripheral requests. The eDMA request input signal is registered
internally and then routed through the eDMA engine: first through the control module,
then into the program model and channel arbitration. In the next cycle, the channel
arbitration performs, using the fixed-priority or round-robin algorithm. After arbitration is
complete, the activated channel number is sent through the address path and converted
into the required address to access the local memory for TCDn. Next, the TCD memory
is accessed and the required descriptor read from the local memory and loaded into the
eDMA engine address path channel x or y registers. The TCD memory is 64 bits wide to
minimize the time needed to fetch the activated channel descriptor and load it into the
address path channel x or y registers.
The following diagram illustrates the second part of the basic data flow:
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
994 NXP Semiconductors
Chapter 21 Enhanced Direct Memory Access (eDMA)
eDMA
Write Address
Write Data
0
1
2
Internal Peripheral Bus
Transfer
To/From Crossbar Switch
Control
Descriptor (TCD) n-1
64
eDMA Engine
Program Model/
Read Data
Channel Arbitration
Read Data
Address Path
Control
Data Path
Write Data
Address
eDMA Peripheral
eDMA Done
Request
Figure 21-4. eDMA operation, part 2
The modules associated with the data transfer (address path, data path, and control)
sequence through the required source reads and destination writes to perform the actual
data movement. The source reads are initiated and the fetched data is temporarily stored
in the data path block until it is gated onto the internal bus during the destination write.
This source read/destination write processing continues until the minor byte count has
transferred.
After the minor byte count has moved, the final phase of the basic data flow is performed.
In this segment, the address path logic performs the required updates to certain fields in
the appropriate TCD, for example, SADDR, DADDR, CITER. If the major iteration
count is exhausted, additional operations are performed. These include the final address
adjustments and reloading of the BITER field into the CITER. Assertion of an optional
interrupt request also occurs at this time, as does a possible fetch of a new TCD from
memory using the scatter/gather address pointer included in the descriptor (if scatter/
gather is enabled). The updates to the TCD memory and the assertion of an interrupt
request are shown in the following diagram.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 995
Functional description
eDMA
Write Address
Write Data
0
1
2
Internal Peripheral Bus
Transfer
To/From Crossbar Switch
Control
Descriptor (TCD) n-1
64
eDMA En g in e
Program Model/
Read Data
Channel Arbitration
Read Data
Address Path
Control
Data Path
Write Data
Address
eDMA Peripheral
eDMA Done
Request
Figure 21-5. eDMA operation, part 3
21.5.2 Fault reporting and handling
Channel errors are reported in the Error Status register (DMAx_ES) and can be caused
by:
• A configuration error, which is an illegal setting in the transfer-control descriptor or
an illegal priority register setting in Fixed-Arbitration mode, or
• An error termination to a bus master read or write cycle
A configuration error is reported when the starting source or destination address, source
or destination offsets, minor loop byte count, or the transfer size represent an inconsistent
state. Each of these possible causes are detailed below:
• The addresses and offsets must be aligned on 0-modulo-transfer-size boundaries.
• The minor loop byte count must be a multiple of the source and destination transfer
sizes.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
996 NXP Semiconductors
Chapter 21 Enhanced Direct Memory Access (eDMA)
• All source reads and destination writes must be configured to the natural boundary of
the programmed transfer size respectively.
• In fixed arbitration mode, a configuration error is caused by any two channel
priorities being equal. All channel priority levels must be unique when fixed
arbitration mode is enabled.
NOTE
When two channels have the same priority, a channel
priority error exists and will be reported in the Error Status
register. However, the channel number will not be reported
in the Error Status register. When all of the channel
priorities within a group are not unique, the channel
number selected by arbitration is undetermined.
To aid in Channel Priority Error (CPE) debug, set the Halt
On Error bit in the DMA’s Control Register. If all of the
channel priorities within a group are not unique, the DMA
will be halted after the CPE error is recorded. The DMA
will remain halted and will not process any channel service
requests. Once all of the channel priorities are set to unique
numbers, the DMA may be enabled again by clearing the
Halt bit.
• If a scatter/gather operation is enabled upon channel completion, a configuration
error is reported if the scatter/gather address (DLAST_SGA) is not aligned on a 32-
byte boundary.
• If minor loop channel linking is enabled upon channel completion, a configuration
error is reported when the link is attempted if the TCDn_CITER[E_LINK] bit does
not equal the TCDn_BITER[E_LINK] bit.
If enabled, all configuration error conditions, except the scatter/gather and minor-loop
link errors, report as the channel activates and asserts an error interrupt request. A scatter/
gather configuration error is reported when the scatter/gather operation begins at major
loop completion when properly enabled. A minor loop channel link configuration error is
reported when the link operation is serviced at minor loop completion.
If a system bus read or write is terminated with an error, the data transfer is stopped and
the appropriate bus error flag set. In this case, the state of the channel's transfer control
descriptor is updated by the eDMA engine with the current source address, destination
address, and current iteration count at the point of the fault. When a system bus error
occurs, the channel terminates after the next transfer. Due to pipeline effect, the next
transfer is already in progress when the bus error is received by the eDMA. If a bus error
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 997
Functional description
occurs on the last read prior to beginning the write sequence, the write executes using the
data captured during the bus error. If a bus error occurs on the last write prior to
switching to the next read sequence, the read sequence executes before the channel
terminates due to the destination bus error.
A transfer may be cancelled by software with the CR[CX] bit. When a cancel transfer
request is recognized, the DMA engine stops processing the channel. The current read-
write sequence is allowed to finish. If the cancel occurs on the last read-write sequence of
a major or minor loop, the cancel request is discarded and the channel retires normally.
The error cancel transfer is the same as a cancel transfer except the Error Status register
(DMAx_ES) is updated with the cancelled channel number and ECX is set. The TCD of a
cancelled channel contains the source and destination addresses of the last transfer saved
in the TCD. If the channel needs to be restarted, you must re-initialize the TCD because
the aforementioned fields no longer represent the original parameters. When a transfer is
cancelled by the error cancel transfer mechanism, the channel number is loaded into
DMA_ES[ERRCHN] and ECX and VLD are set. In addition, an error interrupt may be
generated if enabled.
NOTE
The cancel transfer request allows the user to stop a large data
transfer in the event the full data transfer is no longer needed.
The cancel transfer bit does not abort the channel. It simply
stops the transferring of data and then retires the channel
through its normal shutdown sequence. The application
software must handle the context of the cancel. If an interrupt is
desired (or not), then the interrupt should be enabled (or
disabled) before the cancel request. The application software
must clean up the transfer control descriptor since the full
transfer did not occur.
The occurrence of any error causes the eDMA engine to stop normal processing of the
active channel immediately (it goes to its error processing states and the transaction to the
system bus still has pipeline effect), and the appropriate channel bit in the eDMA error
register is asserted. At the same time, the details of the error condition are loaded into the
Error Status register (DMAx_ES). The major loop complete indicators, setting the
transfer control descriptor DONE flag and the possible assertion of an interrupt request,
are not affected when an error is detected. After the error status has been updated, the
eDMA engine continues operating by servicing the next appropriate channel. A channel
that experiences an error condition is not automatically disabled. If a channel is
terminated by an error and then issues another service request before the error is fixed,
that channel executes and terminates with the same error condition.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
998 NXP Semiconductors
Chapter 21 Enhanced Direct Memory Access (eDMA)
21.5.3 Channel preemption
Channel preemption is enabled on a per-channel basis by setting the DCHPRIn[ECP] bit.
Channel preemption allows the executing channel’s data transfers to temporarily suspend
in favor of starting a higher priority channel. After the preempting channel has completed
all its minor loop data transfers, the preempted channel is restored and resumes
execution. After the restored channel completes one read/write sequence, it is again
eligible for preemption. If any higher priority channel is requesting service, the restored
channel is suspended and the higher priority channel is serviced. Nested preemption, that
is, attempting to preempt a preempting channel, is not supported. After a preempting
channel begins execution, it cannot be preempted. Preemption is available only when
fixed arbitration is selected.
A channel’s ability to preempt another channel can be disabled by setting
DCHPRIn[DPA]. When a channel’s preempt ability is disabled, that channel cannot
suspend a lower priority channel’s data transfer, regardless of the lower priority channel’s
ECP setting. This allows for a pool of low priority, large data-moving channels to be
defined. These low priority channels can be configured to not preempt each other, thus
preventing a low priority channel from consuming the preempt slot normally available to
a true, high priority channel.
21.6 Initialization/application information
The following sections discuss initialization of the eDMA and programming
considerations.
21.6.1 eDMA initialization
To initialize the eDMA:
1. Write to the CR if a configuration other than the default is desired.
2. Write the channel priority levels to the DCHPRIn registers if a configuration other
than the default is desired.
3. Enable error interrupts in the EEI register if so desired.
4. Write the 32-byte TCD for each channel that may request service.
5. Enable any hardware service requests via the ERQ register.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 999
Initialization/application information
6. Request channel service via either:
• Software: setting the TCDn_CSR[START]
• Hardware: slave device asserting its eDMA peripheral request signal
After any channel requests service, a channel is selected for execution based on the
arbitration and priority levels written into the programmer's model. The eDMA engine
reads the entire TCD, including the TCD control and status fields, as shown in the
following table, for the selected channel into its internal address path module.
As the TCD is read, the first transfer is initiated on the internal bus, unless a
configuration error is detected. Transfers from the source, as defined by TCDn_SADDR,
to the destination, as defined by TCDn_DADDR, continue until the number of bytes
specified by TCDn_NBYTES are transferred.
When the transfer is complete, the eDMA engine's local TCDn_SADDR,
TCDn_DADDR, and TCDn_CITER are written back to the main TCD memory and any
minor loop channel linking is performed, if enabled. If the major loop is exhausted,
further post processing executes, such as interrupts, major loop channel linking, and
scatter/gather operations, if enabled.
Table 21-4. TCD Control and Status fields
TCDn_CSR field
Description
name
START Control bit to start channel explicitly when using a software initiated DMA service (Automatically
cleared by hardware)
ACTIVE Status bit indicating the channel is currently in execution
DONE Status bit indicating major loop completion (cleared by software when using a software initiated
DMA service)
D_REQ Control bit to disable DMA request at end of major loop completion when using a hardware initiated
DMA service
BWC Control bits for throttling bandwidth control of a channel
E_SG Control bit to enable scatter-gather feature
INT_HALF Control bit to enable interrupt when major loop is half complete
INT_MAJ Control bit to enable interrupt when major loop completes
The following figure shows how each DMA request initiates one minor-loop transfer, or
iteration, without CPU intervention. DMA arbitration can occur after each minor loop,
and one level of minor loop DMA preemption is allowed. The number of minor loops in
a major loop is specified by the beginning iteration count (BITER).
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1000 NXP Semiconductors
Chapter 21 Enhanced Direct Memory Access (eDMA)
Current major
loop iteration
Source or destination memory count (CITER)
DMA request
Minor loop
3
DMA request
Minor loop
Major loop
2
DMA request
Minor loop
1
Figure 21-6. Example of multiple loop iterations
The following figure lists the memory array terms and how the TCD settings interrelate.
xADDR: (Starting address) xSIZE: (size of one
data transfer) Minor loop
(NBYTES in
minor loop, Offset (xOFF): number of bytes added to
often the same current address after each transfer
value as xSIZE) (often the same value as xSIZE)
Each DMA source (S) and
destination (D) has its own:
Address (xADDR)
Size (xSIZE)
Minor loop Offset (xOFF)
Modulo (xMOD)
Last Address Adjustment (xLAST)
where x = S or D
Peripheral queues typically
have size and offset equal
to NBYTES.
Last minor loop
xLAST: Number of bytes added to
current address after major loop
(typically used to loop back)
Figure 21-7. Memory array terms
21.6.2 Programming errors
The eDMA performs various tests on the transfer control descriptor to verify consistency
in the descriptor data. Most programming errors are reported on a per channel basis with
the exception of channel priority error (ES[CPE]).
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1001
Initialization/application information
For all error types other than group or channel priority errors, the channel number
causing the error is recorded in the Error Status register (DMAx_ES). If the error source
is not removed before the next activation of the problem channel, the error is detected and
recorded again.
Channel priority errors are identified within a group once that group has been selected as
the active group. For example:
1. The eDMA is configured for fixed group and fixed channel arbitration modes.
2. Group 1 is the highest priority and all channels are unique in that group.
3. Group 0 is the next highest priority and has two channels with the same priority
level.
4. If Group 1 has any service requests, those requests will be executed.
5. After all of Group 1 requests have completed, Group 0 will be the next active group.
6. If Group 0 has a service request, then an undefined channel in Group 0 will be
selected and a channel priority error will occur.
7. This repeats until the all of Group 0 requests have been removed or a higher priority
Group 1 request comes in.
In this sequence, for item 2, the eDMA acknowledge lines will assert only if the selected
channel is requesting service via the eDMA peripheral request signal. If interrupts are
enabled for all channels, the user will get an error interrupt, but the channel number for
the ERR register and the error interrupt request line may be wrong because they reflect
the selected channel. A group priority error is global and any request in any group will
cause a group priority error.
If priority levels are not unique, when any channel requests service, a channel priority
error is reported. The highest channel/group priority with an active request is selected,
but the lowest numbered channel with that priority is selected by arbitration and executed
by the eDMA engine. The hardware service request handshake signals, error interrupts,
and error reporting is associated with the selected channel.
21.6.3 Arbitration mode considerations
This section discusses arbitration considerations for the eDMA.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1002 NXP Semiconductors
Chapter 21 Enhanced Direct Memory Access (eDMA)
21.6.3.1 Fixed group arbitration, Fixed channel arbitration
In this mode, the channel service request from the highest priority channel in the highest
priority group is selected to execute. If the eDMA is programmed so that the channels
within one group use "fixed" priorities, and that group is assigned the highest "fixed"
priority of all groups, that group can take all the bandwidth of the eDMA controller. That
is, no other groups will be serviced if there is always at least one DMA request pending
on a channel in the highest priority group when the controller arbitrates the next DMA
request. The advantage of this scenario is that latency can be small for channels that need
to be serviced quickly. Preemption is available in this scenario only.
21.6.3.2 Fixed group arbitration, Round-robin channel arbitration
The highest priority group with a request will be serviced. Lower priority groups will be
serviced if no pending requests exist in the higher priority groups.
Within each group, channels are serviced starting with the highest channel number and
rotating through to the lowest channel number without regard to the channel priority
levels assigned within the group.
This scenario could cause the same bandwidth consumption problem as indicated in
Fixed group arbitration, Fixed channel arbitration, but all the channels in the highest
priority group will be serviced. Service latency will be short on the highest priority group,
but could potentially be very much longer as the group priority decreases.
21.6.4 Performing DMA transfers
This section presents examples on how to perform DMA transfers with the eDMA.
21.6.4.1 Single request
To perform a simple transfer of n bytes of data with one activation, set the major loop to
one (TCDn_CITER = TCDn_BITER = 1). The data transfer begins after the channel
service request is acknowledged and the channel is selected to execute. After the transfer
is complete, the TCDn_CSR[DONE] bit is set and an interrupt generates if properly
enabled.
For example, the following TCD entry is configured to transfer 16 bytes of data. The
eDMA is programmed for one iteration of the major loop transferring 16 bytes per
iteration. The source memory has a byte wide memory port located at 0x1000. The
destination memory has a 32-bit port located at 0x2000. The address offsets are
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1003
Initialization/application information
programmed in increments to match the transfer size: one byte for the source and four
bytes for the destination. The final source and destination addresses are adjusted to return
to their beginning values.
TCDn_CITER = TCDn_BITER = 1
TCDn_NBYTES = 16
TCDn_SADDR = 0x1000
TCDn_SOFF = 1
TCDn_ATTR[SSIZE] = 0
TCDn_SLAST = -16
TCDn_DADDR = 0x2000
TCDn_DOFF = 4
TCDn_ATTR[DSIZE] = 2
TCDn_DLAST_SGA= –16
TCDn_CSR[INT_MAJ] = 1
TCDn_CSR[START] = 1 (Should be written last after all other fields have been initialized)
All other TCDn fields = 0
This generates the following event sequence:
1. User write to the TCDn_CSR[START] bit requests channel service.
2. The channel is selected by arbitration for servicing.
3. eDMA engine writes: TCDn_CSR[DONE] = 0, TCDn_CSR[START] = 0,
TCDn_CSR[ACTIVE] = 1.
4. eDMA engine reads: channel TCD data from local memory to internal register file.
5. The source-to-destination transfers are executed as follows:
a. Read byte from location 0x1000, read byte from location 0x1001, read byte from
0x1002, read byte from 0x1003.
b. Write 32-bits to location 0x2000 → first iteration of the minor loop.
c. Read byte from location 0x1004, read byte from location 0x1005, read byte from
0x1006, read byte from 0x1007.
d. Write 32-bits to location 0x2004 → second iteration of the minor loop.
e. Read byte from location 0x1008, read byte from location 0x1009, read byte from
0x100A, read byte from 0x100B.
f. Write 32-bits to location 0x2008 → third iteration of the minor loop.
g. Read byte from location 0x100C, read byte from location 0x100D, read byte
from 0x100E, read byte from 0x100F.
h. Write 32-bits to location 0x200C → last iteration of the minor loop → major loop
complete.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1004 NXP Semiconductors
Chapter 21 Enhanced Direct Memory Access (eDMA)
6. The eDMA engine writes: TCDn_SADDR = 0x1000, TCDn_DADDR = 0x2000,
TCDn_CITER = 1 (TCDn_BITER).
7. The eDMA engine writes: TCDn_CSR[ACTIVE] = 0, TCDn_CSR[DONE] = 1,
INT[n] = 1.
8. The channel retires and the eDMA goes idle or services the next channel.
21.6.4.2 Multiple requests
The following example transfers 32 bytes via two hardware requests, but is otherwise the
same as the previous example. The only fields that change are the major loop iteration
count and the final address offsets. The eDMA is programmed for two iterations of the
major loop transferring 16 bytes per iteration. After the channel's hardware requests are
enabled in the ERQ register, the slave device initiates channel service requests.
TCDn_CITER = TCDn_BITER = 2
TCDn_SLAST = –32
TCDn_DLAST_SGA = –32
This would generate the following sequence of events:
1. First hardware, that is, eDMA peripheral, request for channel service.
2. The channel is selected by arbitration for servicing.
3. eDMA engine writes: TCDn_CSR[DONE] = 0, TCDn_CSR[START] = 0,
TCDn_CSR[ACTIVE] = 1.
4. eDMA engine reads: channel TCDn data from local memory to internal register file.
5. The source to destination transfers are executed as follows:
a. Read byte from location 0x1000, read byte from location 0x1001, read byte from
0x1002, read byte from 0x1003.
b. Write 32-bits to location 0x2000 → first iteration of the minor loop.
c. Read byte from location 0x1004, read byte from location 0x1005, read byte from
0x1006, read byte from 0x1007.
d. Write 32-bits to location 0x2004 → second iteration of the minor loop.
e. Read byte from location 0x1008, read byte from location 0x1009, read byte from
0x100A, read byte from 0x100B.
f. Write 32-bits to location 0x2008 → third iteration of the minor loop.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1005
Initialization/application information
g. Read byte from location 0x100C, read byte from location 0x100D, read byte
from 0x100E, read byte from 0x100F.
h. Write 32-bits to location 0x200C → last iteration of the minor loop.
6. eDMA engine writes: TCDn_SADDR = 0x1010, TCDn_DADDR = 0x2010,
TCDn_CITER = 1.
7. eDMA engine writes: TCDn_CSR[ACTIVE] = 0.
8. The channel retires → one iteration of the major loop. The eDMA goes idle or
services the next channel.
9. Second hardware, that is, eDMA peripheral, requests channel service.
10. The channel is selected by arbitration for servicing.
11. eDMA engine writes: TCDn_CSR[DONE] = 0, TCDn_CSR[START] = 0,
TCDn_CSR[ACTIVE] = 1.
12. eDMA engine reads: channel TCD data from local memory to internal register file.
13. The source to destination transfers are executed as follows:
a. Read byte from location 0x1010, read byte from location 0x1011, read byte from
0x1012, read byte from 0x1013.
b. Write 32-bits to location 0x2010 → first iteration of the minor loop.
c. Read byte from location 0x1014, read byte from location 0x1015, read byte from
0x1016, read byte from 0x1017.
d. Write 32-bits to location 0x2014 → second iteration of the minor loop.
e. Read byte from location 0x1018, read byte from location 0x1019, read byte from
0x101A, read byte from 0x101B.
f. Write 32-bits to location 0x2018 → third iteration of the minor loop.
g. Read byte from location 0x101C, read byte from location 0x101D, read byte
from 0x101E, read byte from 0x101F.
h. Write 32-bits to location 0x201C → last iteration of the minor loop → major loop
complete.
14. eDMA engine writes: TCDn_SADDR = 0x1000, TCDn_DADDR = 0x2000,
TCDn_CITER = 2 (TCDn_BITER).
15. eDMA engine writes: TCDn_CSR[ACTIVE] = 0, TCDn_CSR[DONE] = 1, INT[n] =
1.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1006 NXP Semiconductors
Chapter 21 Enhanced Direct Memory Access (eDMA)
16. The channel retires → major loop complete. The eDMA goes idle or services the next
channel.
21.6.4.3 Using the modulo feature
The modulo feature of the eDMA provides the ability to implement a circular data queue
in which the size of the queue is a power of 2. MOD is a 5-bit field for the source and
destination in the TCD, and it specifies which lower address bits increment from their
original value after the address+offset calculation. All upper address bits remain the same
as in the original value. A setting of 0 for this field disables the modulo feature.
The following table shows how the transfer addresses are specified based on the setting
of the MOD field. Here a circular buffer is created where the address wraps to the
original value while the 28 upper address bits (0x1234567x) retain their original value. In
this example the source address is set to 0x12345670, the offset is set to 4 bytes and the
MOD field is set to 4, allowing for a 24 byte (16-byte) size queue.
Table 21-5. Modulo example
Transfer Number Address
1 0x12345670
2 0x12345674
3 0x12345678
4 0x1234567C
5 0x12345670
6 0x12345674
21.6.5 Monitoring transfer descriptor status
This section discusses how to monitor eDMA status.
21.6.5.1 Testing for minor loop completion
There are two methods to test for minor loop completion when using software initiated
service requests. The first is to read the TCDn_CITER field and test for a change.
Another method may be extracted from the sequence shown below. The second method is
to test the TCDn_CSR[START] bit and the TCDn_CSR[ACTIVE] bit. The minor-loop-
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1007
Initialization/application information
complete condition is indicated by both bits reading zero after the TCDn_CSR[START]
was set. Polling the TCDn_CSR[ACTIVE] bit may be inconclusive, because the active
status may be missed if the channel execution is short in duration.
The TCD status bits execute the following sequence for a software activated channel:
TCDn_CSR bits
Stage State
START ACTIVE DONE
1 1 0 0 Channel service request via software
2 0 1 0 Channel is executing
3a 0 0 0 Channel has completed the minor loop and is idle
3b 0 0 1 Channel has completed the major loop and is idle
The best method to test for minor-loop completion when using hardware, that is,
peripheral, initiated service requests is to read the TCDn_CITER field and test for a
change. The hardware request and acknowledge handshake signals are not visible in the
programmer's model.
The TCD status bits execute the following sequence for a hardware-activated channel:
TCDn_CSR bits
Stage State
START ACTIVE DONE
Channel service request via hardware (peripheral
1 0 0 0
request asserted)
2 0 1 0 Channel is executing
3a 0 0 0 Channel has completed the minor loop and is idle
3b 0 0 1 Channel has completed the major loop and is idle
For both activation types, the major-loop-complete status is explicitly indicated via the
TCDn_CSR[DONE] bit.
The TCDn_CSR[START] bit is cleared automatically when the channel begins execution
regardless of how the channel activates.
21.6.5.2 Reading the transfer descriptors of active channels
The eDMA reads back the true TCDn_SADDR, TCDn_DADDR, and TCDn_NBYTES
values if read while a channel executes. The true values of the SADDR, DADDR, and
NBYTES are the values the eDMA engine currently uses in its internal register file and
not the values in the TCD local memory for that channel. The addresses, SADDR and
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1008 NXP Semiconductors
Chapter 21 Enhanced Direct Memory Access (eDMA)
DADDR, and NBYTES, which decrement to zero as the transfer progresses, can give an
indication of the progress of the transfer. All other values are read back from the TCD
local memory.
21.6.5.3 Checking channel preemption status
Preemption is available only when fixed arbitration is selected for both group and
channel arbitration modes. A preemptive situation is one in which a preempt-enabled
channel runs and a higher priority request becomes active. When the eDMA engine is not
operating in fixed group, fixed channel arbitration mode, the determination of the actively
running relative priority outstanding requests become undefined. Channel and/or group
priorities are treated as equal, that is, constantly rotating, when Round-Robin Arbitration
mode is selected.
The TCDn_CSR[ACTIVE] bit for the preempted channel remains asserted throughout
the preemption. The preempted channel is temporarily suspended while the preempting
channel executes one major loop iteration. If two TCDn_CSR[ACTIVE] bits are set
simultaneously in the global TCD map, a higher priority channel is actively preempting a
lower priority channel.
21.6.6 Channel Linking
Channel linking (or chaining) is a mechanism where one channel sets the
TCDn_CSR[START] bit of another channel (or itself), therefore initiating a service
request for that channel. When properly enabled, the EDMA engine automatically
performs this operation at the major or minor loop completion.
The minor loop channel linking occurs at the completion of the minor loop (or one
iteration of the major loop). The TCDn_CITER[E_LINK] field determines whether a
minor loop link is requested. When enabled, the channel link is made after each iteration
of the major loop except for the last. When the major loop is exhausted, only the major
loop channel link fields are used to determine if a channel link should be made. For
example, the initial fields of:
TCDn_CITER[E_LINK] = 1
TCDn_CITER[LINKCH] = 0xC
TCDn_CITER[CITER] value = 0x4
TCDn_CSR[MAJOR_E_LINK] = 1
TCDn_CSR[MAJOR_LINKCH] = 0x7
executes as:
1. Minor loop done → set TCD12_CSR[START] bit
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1009
Initialization/application information
2. Minor loop done → set TCD12_CSR[START] bit
3. Minor loop done → set TCD12_CSR[START] bit
4. Minor loop done, major loop done→ set TCD7_CSR[START] bit
When minor loop linking is enabled (TCDn_CITER[E_LINK] = 1), the
TCDn_CITER[CITER] field uses a nine bit vector to form the current iteration count.
When minor loop linking is disabled (TCDn_CITER[E_LINK] = 0), the
TCDn_CITER[CITER] field uses a 15-bit vector to form the current iteration count. The
bits associated with the TCDn_CITER[LINKCH] field are concatenated onto the CITER
value to increase the range of the CITER.
Note
The TCDn_CITER[E_LINK] bit and the
TCDn_BITER[E_LINK] bit must equal or a configuration error
is reported. The CITER and BITER vector widths must be
equal to calculate the major loop, half-way done interrupt point.
The following table summarizes how a DMA channel can link to another DMA channel,
i.e, use another channel's TCD, at the end of a loop.
Table 21-6. Channel Linking Parameters
Desired Link
TCD Control Field Name Description
Behavior
Enable channel-to-channel linking on minor loop completion (current
Link at end of CITER[E_LINK]
iteration)
Minor Loop
CITER[LINKCH] Link channel number when linking at end of minor loop (current iteration)
Link at end of CSR[MAJOR_E_LINK] Enable channel-to-channel linking on major loop completion
Major Loop CSR[MAJOR_LINKCH] Link channel number when linking at end of major loop
21.6.7 Dynamic programming
This section provides recommended methods to change the programming model during
channel execution.
21.6.7.1 Dynamically changing the channel priority
The following two options are recommended for dynamically changing channel priority
levels:
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1010 NXP Semiconductors
Chapter 21 Enhanced Direct Memory Access (eDMA)
1. Switch to Round-Robin Channel Arbitration mode, change the channel priorities,
then switch back to Fixed Arbitration mode,
2. Disable all the channels, change the channel priorities, then enable the appropriate
channels.
21.6.7.2 Dynamic channel linking
Dynamic channel linking is the process of setting the TCD.major.e_link bit during
channel execution (see the diagram in TCD structure). This bit is read from the TCD
local memory at the end of channel execution, thus allowing the user to enable the feature
during channel execution.
Because the user is allowed to change the configuration during execution, a coherency
model is needed. Consider the scenario where the user attempts to execute a dynamic
channel link by enabling the TCD.major.e_link bit at the same time the eDMA engine is
retiring the channel. The TCD.major.e_link would be set in the programmer’s model, but
it would be unclear whether the actual link was made before the channel retired.
The following coherency model is recommended when executing a dynamic channel link
request.
1. Write 1 to the TCD.major.e_link bit.
2. Read back the TCD.major.e_link bit.
3. Test the TCD.major.e_link request status:
• If TCD.major.e_link = 1, the dynamic link attempt was successful.
• If TCD.major.e_link = 0, the attempted dynamic link did not succeed (the
channel was already retiring).
For this request, the TCD local memory controller forces the TCD.major.e_link bit to
zero on any writes to a channel’s TCD.word7 after that channel’s TCD.done bit is set,
indicating the major loop is complete.
NOTE
The user must clear the TCD.done bit before writing the
TCD.major.e_link bit. The TCD.done bit is cleared
automatically by the eDMA engine after a channel begins
execution.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1011
Initialization/application information
21.6.7.3 Dynamic scatter/gather
Scatter/gather is the process of automatically loading a new TCD into a channel. It allows
a DMA channel to use multiple TCDs; this enables a DMA channel to scatter the DMA
data to multiple destinations or gather it from multiple sources.When scatter/gather is
enabled and the channel has finished its major loop, a new TCD is fetched from system
memory and loaded into that channel’s descriptor location in eDMA programmer’s
model, thus replacing the current descriptor.
Because the user is allowed to change the configuration during execution, a coherency
model is needed. Consider the scenario where the user attempts to execute a dynamic
scatter/gather operation by enabling the TCD.e_sg bit at the same time the eDMA engine
is retiring the channel. The TCD.e_sg would be set in the programmer’s model, but it
would be unclear whether the actual scatter/gather request was honored before the
channel retired.
Two methods for this coherency model are shown in the following subsections. Method 1
has the advantage of reading the major.linkch field and the e_sg bit with a single read.
For both dynamic channel linking and scatter/gather requests, the TCD local memory
controller forces the TCD.major.e_link and TCD.e_sg bits to zero on any writes to a
channel’s TCD.word7 if that channel’s TCD.done bit is set indicating the major loop is
complete.
NOTE
The user must clear the TCD.done bit before writing the
TCD.major.e_link or TCD.e_sg bits. The TCD.done bit is
cleared automatically by the eDMA engine after a channel
begins execution.
21.6.7.3.1 Method 1 (channel not using major loop channel linking)
For a channel not using major loop channel linking, the coherency model described here
may be used for a dynamic scatter/gather request.
When the TCD.major.e_link bit is zero, the TCD.major.linkch field is not used by the
eDMA. In this case, the TCD.major.linkch bits may be used for other purposes. This
method uses the TCD.major.linkch field as a TCD indentification (ID).
1. When the descriptors are built, write a unique TCD ID in the TCD.major.linkch field
for each TCD associated with a channel using dynamic scatter/gather.
2. Write 1b to the TCD.d_req bit.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1012 NXP Semiconductors
Chapter 21 Enhanced Direct Memory Access (eDMA)
Should a dynamic scatter/gather attempt fail, setting the TCD.d_req bit will prevent a
future hardware activation of this channel. This stops the channel from executing
with a destination address (daddr) that was calculated using a scatter/gather address
(written in the next step) instead of a dlast final offest value.
3. Write the TCD.dlast_sga field with the scatter/gather address.
4. Write 1b to the TCD.e_sg bit.
5. Read back the 16 bit TCD control/status field.
6. Test the TCD.e_sg request status and TCD.major.linkch value:
If e_sg = 1b, the dynamic link attempt was successful.
If e_sg = 0b and the major.linkch (ID) did not change, the attempted dynamic link
did not succeed (the channel was already retiring).
If e_sg = 0b and the major.linkch (ID) changed, the dynamic link attempt was
successful (the new TCD’s e_sg value cleared the e_sg bit).
21.6.7.3.2 Method 2 (channel using major loop channel linking)
For a channel using major loop channel linking, the coherency model described here may
be used for a dynamic scatter/gather request. This method uses the TCD.dlast_sga field as
a TCD indentification (ID).
1. Write 1b to the TCD.d_req bit.
Should a dynamic scatter/gather attempt fail, setting the d_req bit will prevent a
future hardware activation of this channel. This stops the channel from executing
with a destination address (daddr) that was calculated using a scatter/gather address
(written in the next step) instead of a dlast final offest value.
2. Write theTCD.dlast_sga field with the scatter/gather address.
3. Write 1b to the TCD.e_sg bit.
4. Read back the TCD.e_sg bit.
5. Test the TCD.e_sg request status:
If e_sg = 1b, the dynamic link attempt was successful.
If e_sg = 0b, read the 32 bit TCD dlast_sga field.
If e_sg = 0b and the dlast_sga did not change, the attempted dynamic link did not
succeed (the channel was already retiring).
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1013
Initialization/application information
If e_sg = 0b and the dlast_sga changed, the dynamic link attempt was successful (the
new TCD’s e_sg value cleared the e_sg bit).
21.6.8 Suspend/resume a DMA channel with active hardware
service requests
The DMA allows the user to move data from memory or peripheral registers to another
location in memory or peripheral registers without CPU interaction. Once the DMA and
peripherals have been configured and are active, it is rare to suspend a peripheral’s
service request dynamically. In this scenario, there are certain restrictions to disabling a
DMA hardware service request. For coherency, a specific procedure must be followed.
This section provides guidance on how to coherently suspend and resume a Direct
Memory Access (DMA) channel when the DMA is triggered by a slave module such as
the Serial Peripheral Interface (DSPI), ADC, or other module.
21.6.8.1 Suspend an active DMA channel
To suspend an active DMA channel:
1. Stop the DMA service request at the peripheral first. Confirm it has been disabled by
reading back the appropriate register in the peripheral.
2. Check Hardware Request Status Register (DMA_HRS) to ensure there is no service
request to the DMA channel being suspended. Then disable the hardware service
request by clearing the ERQ bit on the appropriate DMA channel.
21.6.8.2 Resume a DMA channel
To resume a DMA channel:
1. Enable the DMA service request on the appropriate channel by setting its ERQ bit.
2. Enable the DMA service request at the peripheral.
For example, assume a DSPI module is set as a master for transmitting data via a DMA
service request when the DSPI_TXFIFO has an empty slot. The DMA will transfer the
next command and data to the TXFIFO upon the request. If the user needs to suspend the
DMA/DSPI transfer loop, perform the following steps:
1. Disable the DMA service request at the source by writing 0 to
DSPI_RSER[TFFF_RE] . Confirm that DSPI_RSER[TFFF_RE] is 0.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1014 NXP Semiconductors
Chapter 21 Enhanced Direct Memory Access (eDMA)
2. Ensure there is no DMA service request from the DSPI by verifying that
DMA_HRS[HRSn] is 0 for the appropriate channel. If no service request is present,
disable the DMA channel by clearing the channel’s ERQ bit. If a service request is
present, wait until the request has been processed and the HRS bit reads zero.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1015
Initialization/application information
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1016 NXP Semiconductors
Chapter 22
Enhanced Secured Digital Host Controller
22.1 Overview
The enhanced secured digital host controller (eSDHC) provides interface between the
host system and the SD/SDIO/MMC cards, as depicted in the figure below.
The eSDHC acts as a bridge, passing host bus transactions to the SD/SDIO/MMC cards
by sending commands and performing data accesses to/from the cards.
It handles the SD/SDIO/MMC protocols at the transmission level.
Different types of cards supported by the eSDHC are described below:
• MultiMediaCard (MMC)
MMC is a universal low-cost data storage and communication medium designed to
cover a wide area of applications, including mobile video and gaming, which are
available from either pre-loaded MMC cards or downloadable from cellular phones,
WLAN, or other wireless networks. Old MMC cards are based on a seven-pin serial
bus with a single data pin, while the new high-speed MMC communication is based
on advanced 11-pin serial bus designed to operate in a low voltage range.
• Secure digital (SD) card
The secure digital (SD) card is an evolution over the old MMC technology. It is
specifically designed to meet the security, capacity, performance, and environmental
requirements inherent in the emerging audio and video consumer electronic devices.
The physical form factor, pin assignments, and data transfer protocol are forward-
compatible with the old MMC. The chip supports SDXC card.
• SDIO
Under the SD protocol, the SD cards can be categorized as a memory card, I/O card,
or combo card. The memory card invokes a copyright protection mechanism that
complies with the security of the SDMI standard. The I/O card provides high-speed
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1017
Overview
data I/O with low power consumption for mobile electronic devices. The combo card
has both memory and I/O functions. For the sake of simplicity, the following figure
does not show cards with reduced sizes.
In addition, the chip also supports the embedded devices, such as and eSDIO. Note that
all references to SDIO are also applicable to eSDIO.
The eSDHC acts as a bridge, passing host bus transactions to MMC/SD/SDIO cards by
sending commands and performing data accesses to or from the cards. It handles the
MMC/SD/SDIO protocol at the transmission level. The figure below shows connection of
the eSDHC.
eSDHC
Host Controller
MMC/SD/SDIO
Transceiver
Card
Card Slot
DMA Interface Register Bus
Power
Supply
CoreNet Register Bus
Figure 22-1. System connection of the eSDHC
The figure below is a high-level block diagram of eSDHC.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1018 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
Clock and reset Clock and reset
SD monitor
Register
Register bank
interface SD interface and control unit
SD data_in Async
FIFO
SD response Tuning
Block
System interface and control unit SD bus
System
control Transfer SD
control command
System
interface
DMA Buffer SD data
SD data_out
control FIFO
Buffer
RAM
Figure 22-2. Enhanced secure digital host controller block diagram
22.1.1 eSDHC features summary
The features of the eSDHC module include the following:
• Conforms to the SD Host controller standard specification version 3.0, including test
event register support
• Compatible with the eMMC system specification version 4.5
• Compatible with the SD memory card specification version 3.01, and supports the
high capacity SD memory card
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1019
Overview
• Compatible with the SDIO card specification version 3.0
• Designed to work with SD memory, SDIO, SD combo, MMC, and their variants,
such as mini and micro.
• MMCHC (MMC high capacity) support
• Supports 1- or 4-bit SD and SDIO modes, 1- or 4- or 8-bit MMC modes
• Supports single-block and multi-block read, and write data transfer
• Supports block sizes of 1-2048 bytes
• Supports the mechanical write protect detection. In the case where write protect is
enabled, the host will not initiate any write data command to the card
• Supports card detection from SDHC_CD_B
• Supports both synchronous and asynchronous abort
• Supports pause during the data transfer at block gap
• Supports SDIO read wait and suspend resume operations
• Supports Auto CMD12 and Auto CMD23 for multi-block transfer
• Host can initiate command that does not use data lines, while data transfer is in
progress
• Allows card to interrupt the host in 1 bit and 4 bit SDIO modes, also supports
interrupt period
• Embodies a configurable 128 x 32 bit FIFO for read/write data
• Supports SDMA, ADMA1, and ADMA2 capabilities
• Host will send 80 idle SD clock cycles to card, which are needed during card power-
up, if bit INITA in the system control register (SYSCTL) is set
• Supports SDIO asynchronous interrupt
• Supports clock divider with finer granularity, that is, with values 1,2,3....1024 or
1,2,4,8...2048
• Supports standard, high and extended capacity card types
• Supports SD UHS-1 speed modes: SDR12, SDR25, SDR50, SDR104, DDR50
• Supports MMC high speed, HS200 and DDR mode
22.1.2 Modes and operations
22.1.2.1 Data transfer modes
The eSDHC can select the following modes for data transfer:
• SD 1 bit
• SD 4 bit
• MMC 1 bit
• MMC 4 bit
• MMC 8 bit
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1020 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
• Identification mode
• MMC full speed mode
• MMC high speed mode
• SD/SDIO full speed mode
• SD/SDIO high speed mode
• SD/SDIO UHS-1 SDR12 mode
• SD/SDIO UHS-1 SDR25 mode
• SD/SDIO UHS-1 SDR50 mode
• SD/SDIO UHS-1 SDR104 mode
• SD/SDIO UHS-1 DDR50 mode
• MMC HS200 mode
• MMC DDR mode
NOTE
For the maximum supported speed of the modes, refer chip-
specific datasheet.
22.2 External signals
22.2.1 External signals overview
The eSDHC has the following associated I/O signals:
• SDHC_CLK is an internally generated clock signal that drives the SD/SDIO/MMC
card.
• SDHC_CLK_SYNC_OUT has same frequency as SDHC_CLK. It should be sent out
on board for loop back from close to external card.
• SDHC_CLK_SYNC_IN has same frequency as SDHC_CLK. It is loopback input
from close to card on board.
• SDHC_CMD I/O sends commands to and receives responses from the card.
• SDHC_DAT[7:0] performs data transfers between the eSDHC and the card. If the
eSDHC is desired to support a 4 bit data transfer, DAT[7:4] can also be optional and
tied high.
• SDHC_CD_B and SDHC_WP are card detection and write protection signals from
the socket.
• SDHC_CMD_DIR is an output signal used to control the direction of CMD line in an
external voltage translator.
• SDHC_DAT0_DIR is an output signal used to control the direction of DAT0 line in
an external voltage translator.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1021
External signals
• SDHC_DAT123_DIR is an output signal used to control the direction of DAT1-
DAT3 lines in an external voltage translator.
• SDHC_VS is an output signal used to control the voltage of external SD bus supply.
22.2.2 eSDHC signal descriptions
The following table describes eSDHC signals.
Table 22-1. Signal properties
Name Port Function Reset state Pull up
SDHC_CLK O Clock for SD/SDIO/MMC card or eMMC device 0 N/A
SDHC_CLK_SYNC_OU O Clock to loopback from close to card 0 N/A
T
SDHC_CLK_SYNC_IN I Clock looped back from card 0 N/A
SDHC_CMD I/O CMD line connect to card 1 Pull up
SDHC_CMD_DIR O CMD line direction control 0 N/A
SDHC_DAT7 I/O DAT7 line in 8-bit mode 1 Pull up
Not used in other modes
SDHC_DAT6 I/O DAT6 line in 8-bit mode 1 Pull up
Not used in other modes
SDHC_DAT5 I/O DAT5 line in 8-bit mode 1 Pull up
Not used in other modes
SDHC_DAT4 I/O DAT4 line in 8-bit mode 1 Pull up
Not used in other modes
SDHC_DAT3 I/O DAT3 line in 4/8-bit mode 0 Pull up. Do
not use
DAT3 pin as
a CD pin.
SDHC_DAT2 I/O DAT2 line or read wait in 4/8-bit mode 1 Pull up
Read wait in 1-bit mode
SDHC_DAT1 I/O DAT1 line in 4/8-bit mode 1 Pull up
Also used to detect interrupt in 1/4-bit mode
SDHC_DAT0 I/O DAT0 line in all modes 1 Pull up
Also used to detect busy state
SDHC_DAT0_DIR O DAT0 line direction control 0 N/A
SDHC_CD_B I Card detection pin N/A N/A
If not used tie high
SDHC_WP I Card write protect detect N/A N/A
If not used tie low
SDHC_VS O Control the voltage on SD pads to be high voltage (around 0 N/A
3.0V) or low voltage (around 1.8V). '0' stands for high voltage
range
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1022 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
Table 22-1. Signal properties (continued)
Name Port Function Reset state Pull up
Optional output
SDHC_DAT123_DIR O DAT1-DAT3 lines direction control 0 N/A
22.3 eSDHC register descriptions
The table below shows the memory-mapped registers of the eSDHC module and lists the
offset, name, and a cross-reference to the complete description of each register. These
register only support 32-bit accesses.
22.3.1 eSDHC Memory map
eSDHC base address: 156_0000h
Offset Register Width Access Reset value
(In bits)
0h SDMA system address register/Block attributes 2 (DSADDR_BLKAT 32 RW 0000_0000h
TR2)
4h Block attributes register (BLKATTR) 32 RW 0000_0000h
8h Command argument register (CMDARG) 32 RW 0000_0000h
Ch Transfer type register (XFERTYP) 32 RW 0000_0000h
10h Command response 0 register (CMDRSP0) 32 RO 0000_0000h
14h Command response 1 register (CMDRSP1) 32 RO 0000_0000h
18h Command response 2 register (CMDRSP2) 32 RO 0000_0000h
1Ch Command Response 3 register (CMDRSP3) 32 RO 0000_0000h
20h Buffer data port register (DATPORT) 32 RW 0000_0000h
24h Present state register (PRSSTAT) 32 RO See
description.
28h Protocol control register (PROCTL) 32 RW 0000_0020h
2Ch System Control Register when ESDHCCTL[CRS=0] (SYSCTL_E 32 RW 0000_8038h
SDHCCTL_CRS_0)
2Ch System Control Register when ESDHCCTL[CRS=1] (SYSCTL_E 32 RW See
SDHCCTL_CRS_1) description.
30h Interrupt status register (IRQSTAT) 32 W1C 0000_0000h
34h Interrupt status enable register (IRQSTATEN) 32 RW 377F_11FFh
38h Interrupt signal enable register (IRQSIGEN) 32 RW 0400_1000h
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1023
eSDHC register descriptions
Offset Register Width Access Reset value
(In bits)
3Ch Auto CMD Error Status Register / System Control 2 Register (AUTO 32 RW 0000_0000h
CERR_SYSCTL2)
40h Host controller capabilities register (HOSTCAPBLT) 32 RO See
description.
44h Watermark level register (WML) 32 RW 0010_0010h
50h Force event register (FEVT) 32 WO 0000_0000h
54h ADMA error status register (ADMAES) 32 RO 0000_0000h
58h ADMA system address register (ADSADDR) 32 RW 0000_0000h
FCh Host controller version register (HOSTVER) 32 RO 0000_2102h
104h DMA error address register (DMAERRADDR) 32 RO 0000_0000h
10Ch DMA error attribute register (DMAERRATTR) 32 RO 0000_0000h
114h Host controller capabilities register 2 (HOSTCAPBLT2) 32 RO See
description.
120h Tuning block control register (TBCTL) 32 RW See
description.
124h Tuning block status register (TBSTAT) 32 RW 0000_0000h
128h Tuning block pointer register (TBPTR) 32 RW 0000_0000h
140h SD direction control register (SDDIRCTL) 32 RW 0000_0001h
144h SD Clock Control Register (SDCLKCTL) 32 RW 0000_0000h
40Ch eSDHC control register (ESDHCCTL) 32 RW 0000_0000h
22.3.2 SDMA system address register/Block attributes 2 (DSAD
DR_BLKATTR2)
22.3.2.1 Offset
Register Offset
DSADDR_BLKATTR2 0h
22.3.2.2 Function
The DSADDR contains the physical system memory address used for single DMA
transfers or second argument for Auto CMD23.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1024 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
22.3.2.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
DS_ADDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
DS_ADDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
22.3.2.4 Fields
Field Function
0-31 DMA system address / Block attributes 2
DS_ADDR This register contains the physical system memory address used for DMA transfers or second argument
for Auto CMD23.
SDMA system address:
This register contains the 32-bit system memory address for a single DMA (SDMA) transfer. When the
eSDHC stops a DMA transfer, this register points to the system address of the next contiguous data
position. It can be accessed only when no transaction is executing (that is, after a transaction has
stopped). The host driver should initialize this register before starting a every DMA transaction. After DMA
has stopped, the system address of the next contiguous data position can be read from this register.
The eSDHC DMA does not support a virtual memory system. It only supports continuous physical
memory access.
Block attributes 2:
This register is used with Auto CMD23 to set 32-bit block count value to the argument of CMD23 while
executing Auto CMD23.
If Auto CMD23 is used with ADMA, the full 32-bit block count value can be used.
If Auto CMD23 is used without ADMA, the available block count value is limited by 16-bit Block Count
field in Block Attributes register. 65536 blocks is the maximum value available in this case.
22.3.3 Block attributes register (BLKATTR)
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1025
eSDHC register descriptions
22.3.3.1 Offset
Register Offset
BLKATTR 4h
22.3.3.2 Function
The BLKATTR is used to configure the number of data blocks and the number of bytes
in each block.
22.3.3.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
BLKCNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
Reserved BLKSIZE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
22.3.3.4 Fields
Field Function
0-15 Blocks count for current transfer.
BLKCNT • This register is enabled when XFERTYP[BCEN] is set to 1 and is valid only for multiple block
transfers. The host driver should set this register to a value between 1 and the maximum block
count. The eSDHC decrements the block count after each block transfer and stops when the count
reaches zero. Setting the block count to 0 results in no data blocks being transferred.
• This register should be accessed only when no transaction is executing (that is, after transactions
are stopped). During data transfer, read operations on this register may return an invalid value and
write operations are ignored.
• When saving transfer content as a result of a suspend command, the number of blocks yet to be
transferred can be determined by reading this register. The reading of this register should be
applied after transfer is paused by stop at block gap operation and before sending the command
marked as suspend. This is because when suspend command is sent out, eSDHC will regard the
current transfer is aborted and change BLKCNT back to its original value instead of keeping the
dynamical indicator of remained block count.
• When restoring transfer content prior to issuing a resume command, the host driver should restore
the previously saved block count.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1026 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
Field Function
0000000000000000b - Stop count
0000000000000001b - 1 block
0000000000000010b - 2 blocks
1111111111111111b - 65535 blocks
16-19 Reserved.
—
20-31 Transfer block size. This register specifies the block size for block data transfers. Values ranging from 1
byte up to the maximum buffer size can be set. It can be accessed only when no transaction is executing
BLKSIZE
(that is, after a transaction has stopped). Read operations during transfers may return an invalid value,
and write operations will be ignored.
000000000000b - No data transfer
000000000001b - 1 byte
000000000010b - 2 bytes
000000000011b - 3 bytes
000000000100b - 4 bytes
000111111111b - 511 bytes
001000000000b - 512 bytes
100000000000b - 2048 bytes
22.3.4 Command argument register (CMDARG)
22.3.4.1 Offset
Register Offset
CMDARG 8h
22.3.4.2 Function
The CMDARG contains the SD/MMC command argument.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1027
eSDHC register descriptions
22.3.4.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
CMDARG
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
CMDARG
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
22.3.4.4 Fields
Field Function
0-31 Command argument. The SD/MMC command argument is specified as bits 39-8 of the command format
in the SD or MMC Specification. This register is write protected when PRSSTAT[CIHB] is set.
CMDARG
22.3.5 Transfer type register (XFERTYP)
22.3.5.1 Offset
Register Offset
XFERTYP Ch
22.3.5.2 Function
The host driver should set the XFERTYP to issue any new command. To prevent data
loss, the eSDHC prevents writing to the bits, that are involved in the data transfer of this
register, when data transfer is active: MBSEL, DTDSEL, AC12EN, BCEN, and
DMAEN.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1028 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
The host driver should check PRSSTAT[CDIHB] and PRSSTAT[CIHB] before writing
to this register. When PRSSTAT[CDIHB] is set, any attempt to send a command with
data by writing to this register is ignored; when PRSSTAT[CIHB] is set, any write to this
register is ignored.
On sending commands with data transfer, it is mandatory that the block size is non-zero.
Besides, block count must also be non-zero, or indicated as single block transfer
(XFERTYP[MSBSEL] is '0' when written), or block count is disabled
(XFERTYP[BCEN] is '0' when written), otherwise eSDHC will ignore the sending of this
command and do nothing. For write commands, with all above restrictions, it is also
mandatory that the write protect switch is not active (PRSSTAT[WPS] is '1), otherwise
eSDHC will also ignore the command.
If the commands with write data transfer does not receive the response in 64 clock cycles,
that is, response time-out, eSDHC will regard the external device does not accept the
command and will not initiate the data transfer on SD bus. In this scenario, the driver
should perform error recovery and issue the command again to re-try the transfer.
It is also possible that for some reason the card responds to the read data command but
eSDHC does not receive the response, and if it is a DMA (SDMA or ADMA ) read
operation, the external system memory is over-written by the DMA with data sent back
from the card.
Table 22-2. Transfer Type Register Setting for Various Transfer Types
Multi-/Single Block Select Block Count Enable Block Count Function
0 Don't Care Don't Care Single Transfer
1 0 Don't Care Infinite Transfer
1 1 Positive Number Multiple Transfer
1 1 Zero No Data Transfer
The table below shows the relationship between the command index check enable and the
command CRC check enable, in regards to the response type bits as well as the name of
the response type.
Table 22-3. Relationship Between Parameters and the Name of the Response Type
Response type Index Check Enable CRC Check Enable Name of Response Type
00 0 0 No Response
01 0 1 R2
10 0 0 R3, R4
10 1 1 R1, R5, R6, R7
11 1 1 R1b, R5b
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1029
eSDHC register descriptions
• In the SDIO Specification, response type notation for R5b is not defined. R5 includes
R5b in the SDIO Specification. But R5b is defined in this specification to specify
that the eSDHC checks the busy status after receiving a response. For example,
usually CMD52 is used with R5, but the I/O abort command should be used with
R5b.
• The CRC field for R3 and R4 is expected to be all 1 bits. The CRC check should be
disabled for these response types.
22.3.5.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CMDTYP
Reserved
Reserved
CMDINX
CCCEN
CICEN
RSPTY
DPSE
W
P
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
Reserved
DMAEN
MSBSE
DTDSE
BCEN
ACEN
W
L
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
22.3.5.4 Fields
Field Function
0-1 Reserved.
—
2-7 Command index
CMDINX Command index. These bits should be set to the command number that is specified in bits 45-40 of the
command format in the SD Memory Card Physical Layer Specification and SDIO Card Specification .
8-9 Command Type
CMDTYP Command Type. There are three types of special commands: suspend, resume, and abort. These bits
should be set to 00b for all other commands.
• Suspend command: If the suspend command succeeds, the eSDHC should assume that the card
bus has been released and that it is possible to issue the next command which uses the DAT line.
Since eSDHC does not monitor the content of command response, it does not know if the suspend
command succeeded or not. It is the host driver's responsibility to check the status of the suspend
command and send another command marked as Suspend to inform the eSDHC that a suspend
command was successfully issued. Refer to Suspend resume for more details. After the start bit of
command is sent, the eSDHC de-asserts read wait for read transactions and stops checking busy
for write transactions. In 4-bit mode, the interrupt cycle starts. If the suspend command fails, the
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1030 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
Field Function
eSDHC will maintain its current state, and the host driver should restart the transfer by setting
PROCTL[CREQ].
• Resume command: The host driver re-starts the data transfer by restoring the registers saved
before sending the suspend command and then sends the resume command.
• Abort command: If this command is set when executing a read transfer, the eSDHC will stop write
to the buffer after end bit of abort command is sent. If this command is set when executing a write
transfer, the eSDHC will stop driving the DAT line. After issuing the abort command, the host driver
should issue a software reset (abort transaction).
00b - Normal other commands
01b - Suspend CMD52 for writing bus suspend in CCCR
10b - Resume CMD52 for writing function select in CCCR
11b - Abort CMD12, CMD52 for writing I/O abort in CCCR
10 Data present select. This bit is set to 1 to indicate that data is present and should be transferred using the
DAT line. It is set to 0 for the following:
DPSEL
• Commands using only the CMD line (for example, CMD52)
• Commands with no data transfer, but using the busy signal on DAT[0] line (R1b or R5b, for
example, CMD38)
NOTE: In resume command, this bit should be set, and other bits in this register should be set the same
as when the transfer was initially launched. When the write protect switch is on (that is,
PRSSTAT[WPS] is active as '0'), any command with a write operation will be ignored. That is to
say, when this bit is set, while XFRTYP[DTDSEL] is 0, writes to the transfer type register
(XFRTYP) are ignored.
0b - No data present
1b - Data present
11 Command index check enable. If this bit is set to 1, the eSDHC checks the Index field in the response to
see if it has the same value as the command index. If it is not, it is reported as a command index error. If
CICEN
this bit is set to 0, the Index field is not checked.
0b - Disable
1b - Enable
12 Command CRC check enable
CCCEN Command CRC check enable. If this bit is set to 1, the eSDHC should check the CRC field in the
response. If an error is detected, it is reported as a command CRC error. If this bit is set to 0, the CRC
field is not checked. The number of bits checked by the CRC field value changes according to the length
of the response. (Refer to RSPTYP[1:0] and Table 22-3.)
0b - Disable
1b - Enable
13 Reserved.
—
14-15 Response type select.
RSPTYP 00b - No response
01b - Response length 136
10b - Response length 48
11b - Response length 48, check busy after response
16-25 Reserved.
—
26 Multi-/single-block select
MSBSEL Multi-/single-block select. This bit enables multiple block DAT line data transfers. For any other
commands, this bit should be set to 0. If this bit is 0, it is not necessary to set the block count register.
(Refer to Table 22-2.)
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1031
eSDHC register descriptions
Field Function
0b - Single block
1b - Multiple blocks
27 Data transfer direction select. This bit defines the direction of DAT line data transfers. The bit is set to 1
by the host driver to transfer data from the SD card to the eSDHC and is set to 0 for all other commands.
DTDSEL
0b - Write (host to card)
1b - Read (card to host)
28-29 Auto CMD12 enable
ACEN Auto CMD12 enable. Multiple block transfers for memory require a CMD12 to stop the transaction. When
this bit is set to 1, the eSDHC will issue a CMD12 automatically when the last block transfer has
completed. The host driver should not set this bit to issue commands that do not require CMD12 to stop a
multiple block data transfer. In particular, secure commands defined in File security specification do not
require CMD12. In single block transfer, the eSDHC will ignore this bit whether if it is set or not.
Auto CMD23 Enable. When this bit is set to 10b, the eSDHC will issue a CMD23 automatically before
issuing a command specified in the transfer type register. The following conditions are required to use
Auto CMD23:
• A memory card that supports CMD23 (For SD card, SCR[33]=1)
• If DMA is used, it shall be ADMA
• Only when CMD18 or CMD25 is issued
NOTE: eSDHC does not check command index
Auto CMD23 can be issued with or without ADMA, by writing Transfer Type register, eSDHC issues a
CMD23 first and then issues a command specified by Transfer Type register. If response errors of
CMD23 are detected, the second command is not issued. A CMD23 error is indicated in the Auto CMD
Error Status register.
32-bit block count value for CMD23 is set to DMA System Address / Argument 2 register.
00b - Auto CMD Disable
01b - Auto CMD12 Enable
10b - Auto CMD23 Enable
11b - Reserved
30 Block count enable. This bit is used to enable the block count register, which is only relevant for multiple
block transfers. When this bit is 0, the internal counter for block is disabled, which is useful in executing
BCEN
an infinite transfer.
If ADMA data transfer is more than 65535 blocks, this bit shall be set to 0. In this case, data transfer
length is designated by Descriptor Table.
0b - Disable
1b - Enable
31 DMA enable
DMAEN DMA enable. This bit enables DMA functionality. If this bit is set to 1, a DMA operation should begin when
the host driver sets the DPSEL bit of this register. Whether the single DMA or ADMA is active depends on
PROCTL[DMAS].
0b - Disable
1b - Enable
22.3.6 Command response 0 register (CMDRSP0)
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1032 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
22.3.6.1 Offset
Register Offset
CMDRSP0 10h
22.3.6.2 Function
The CMDRSP0 is used to store part 0 of the response bits from the card.
22.3.6.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R CMDRSP0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R CMDRSP0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
22.3.6.4 Fields
Field Function
0-31 Command response 0
CMDRSP0 Command response 0. Refer to Command Response 3 register (CMDRSP3) for the mapping of
command responses from the SD bus to this register for each response type.
22.3.7 Command response 1 register (CMDRSP1)
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1033
eSDHC register descriptions
22.3.7.1 Offset
Register Offset
CMDRSP1 14h
22.3.7.2 Function
The CMDRSP1 is used to store part 1 of the response bits from the card.
22.3.7.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R CMDRSP1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R CMDRSP1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
22.3.7.4 Fields
Field Function
0-31 Command response 1
CMDRSP1 Command response 1. Refer to Command Response 3 register (CMDRSP3) for the mapping of
command responses from the SD bus to this register for each response type.
22.3.8 Command response 2 register (CMDRSP2)
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1034 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
22.3.8.1 Offset
Register Offset
CMDRSP2 18h
22.3.8.2 Function
The CMDRSP2 is used to store part 2 of the response bits from the card.
22.3.8.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R CMDRSP2
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R CMDRSP2
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
22.3.8.4 Fields
Field Function
0-31 Command response 2
CMDRSP2 Command response 2. Refer to Command Response 3 register (CMDRSP3) for the mapping of
command responses from the SD bus to this register for each response type.
22.3.9 Command Response 3 register (CMDRSP3)
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1035
eSDHC register descriptions
22.3.9.1 Offset
Register Offset
CMDRSP3 1Ch
22.3.9.2 Function
The CMDRSP3 is used to store part 3 of the response bits from the card.
Table below describes the mapping of command responses from the SD bus to command
response registers for each response type. In the table, R n refers to a bit range within the
response data as transmitted on the SD bus.
Table 22-4. Response bit definition for each response type
Response type Meaning of response Response field Response register
R1,R1b (normal response) Card Status R[39:8] CMDRSP0
R1b (Auto CMD12 response) Card Status for Auto CMD12 R[39:8] CMDRSP3
R2 (CID, CSD register) CID/CSD register [127:8] R[127:8] {CMDRSP3[8:31],
CMDRSP2,
CMDRSP1,
CMDRSP0}
R3 (OCR register) OCR register for memory R[39:8] CMDRSP0
R4 (OCR register) OCR register for I/O R[39:8] CMDRSP0
R5, R5b SDIO response R[39:8] CMDRSP0
R6 (Publish RCA) New Published RCA[31:16] and card R[39:9] CMDRSP0
status[15:0]
This table shows the following:
Most responses with a length of 48 (R[47:0]) have 32-bits of the response data (R[39:8])
stored in the CMDRSP0 register. Responses of type R1b (Auto CMD12 responses) have
response data bits (R[39:8]) stored in the CMDRSP3 register. Responses with length 136
(R[135:0]) have 120-bits of the response data (R[127:8]) stored in the CMDRSP0, 1, 2,
and 3 registers.
To be able to read the response status efficiently, the eSDHC only stores part of the
response data in the command response registers (CMDRSP n ). This enables the host
driver to efficiently read 32-bits of response data in one read cycle on a 32-bit bus
system. Parts of the response, the index field and the CRC, are checked by the eSDHC
(as specified by the command index check enable and the command CRC check enable
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1036 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
bits in the transfer type register, XFERTYP) and generate an error interrupt if any error is
detected. The bit range for the CRC check depends on the response length. If the
response length is 48, the eSDHC checks R[47:1], and if the response length is 136 the
eSDHC checks R[119:1].
Since eSDHC may have a multiple block data transfer executing concurrently with a
CMD_wo_DAT command, it stores the Auto CMD12 response in the CMDRSP3
register. The CMD_wo_DAT response is stored in CMDRSP0. This allows the eSDHC
to avoid overwriting the Auto CMD12 response with the CMD_wo_DAT and vice versa.
When the eSDHC modifies part of the command response registers (CMDRSP n ), as
shown in the table above, it preserves the unmodified bits.
22.3.9.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R CMDRSP3
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R CMDRSP3
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
22.3.9.4 Fields
Field Function
0-31 Command response 3
CMDRSP3 Command response 3. Refer to Command Response 3 register (CMDRSP3) for the mapping of
command responses from the SD bus to this register for each response type.
22.3.10 Buffer data port register (DATPORT)
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1037
eSDHC register descriptions
22.3.10.1 Offset
Register Offset
DATPORT 20h
22.3.10.2 Function
The DATPORT is a 32-bit data port register used to access the internal buffer. Byte
access is not allowed.
22.3.10.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
DATCONT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
DATCONT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
22.3.10.4 Fields
Field Function
0-31 Data content. The buffer data port register is for 32-bit data access by the CPU. When the DMA is
enabled, any write to this register is ignored, and any read from this register always yields zeros.
DATCONT
22.3.11 Present state register (PRSSTAT)
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1038 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
22.3.11.1 Offset
Register Offset
PRSSTAT 24h
22.3.11.2 Function
The host driver can get the status of the eSDHC from the PRSSTAT, which is a 32-bit,
read-only register.
22.3.11.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CINS
CDS
DLS
R CLS
Reserved
Reserved
WP
S
L
L
W
Reset 1 1 1 1 1 1 1 1 1 0 0 0 u u 0 u
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
BWEN
CDIHB
SDOF
CIHB
SDST
Reserved
Reserved
WTA
RTA
DLA
BRE
R
N
B
F
W
Reset 0 0 0 0 0 0 0 0 u 0 0 0 1 0 0 0
22.3.11.4 Fields
Field Function
0-7 DAT[7:0] line signal level
DLSL DAT[7:0] line signal level. This status is used to check the DAT line level to recover from errors, and for
debugging.This is especially useful in detecting the busy signal level from DAT[0]. The reset value is
effected by the external pull-up/pull-down resistors. By default, the read value of this bit field after reset is
8'b11111111
DLSL[0]: Data 0 line signal level
DLSL[1]: Data 1 line signal level
DLSL[2]: Data 2 line signal level
DLSL[3]: Data 3 line signal level
DLSL[4]: Data 4 line signal level
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1039
eSDHC register descriptions
Field Function
DLSL[5]: Data 5 line signal level
DLSL[6]: Data 6 line signal level
DLSL[7]: Data 7 line signal level
8 CMD line signal level. This status is used to check the CMD line level to recover from errors, and for
debugging. The reset value is effected by the external pull-up/pull-down resistor, by default, the read
CLSL
value of this bit after reset is 1, when the command line is pulled up.
9-11 Reserved.
—
12 Write protect state
WPS Write protect state. The write protect switch is supported for memory and combo cards. This bit reflects
the write protect state depending on value of SDHC_WP pin of the card socket. A software reset does not
affect this bit. The reset value is effected by the external write protect switch. If the SDHC_WP pin is not
used, it should be tied low, so that the reset value of this bit is high and write is enabled.
0b - Write protected (SDHC_WP =1)
1b - Write enabled (SDHC_WP =0)
13 Card detect state
CDS Card detect state. This bit reflects the card inserted/removed state depending on value of the
SDHC_CD_B pin for the card socket. Debouncing is not performed on this bit. This bit may be valid, but
is not guaranteed, because of propagation delay. Use of this bit is limited to testing since it must be
debounced by software. A software reset does not effect this bit. A write to the force event register
(FEVT) does not affect this bit. The reset value is effected by the external card detection pin. This bit
shows the value on the SDHC_CD_B pin (that is, when a card is inserted in the socket, it is 0 on the
SDHC_CD_B input, and consequently the CDS reads 1.)
0b - No card present (SDHC_CD_B =1)
1b - Card present SDHC_CD_B =0)
14 Reserved.
—
15 Card inserted. This bit indicates whether a card has been inserted. The eSDHC debounces this signal so
that the host driver will not need to wait for it to stabilize. Changing from a 0 to 1 generates a card
CINS
insertion interrupt in the interrupt status register (IRQSTAT). Changing from a 1 to 0 generates a card
removal interrupt in the interrupt status register (IRQSTAT). A write to the force event register (FEVT)
does not effect this bit.
The software reset for all in the system control register (SYSCTL) does not effect this bit. A software reset
does not effect this bit.
0b - Power on reset or no card
1b - Card inserted
16-19 Reserved.
—
20 Buffer read enable. This status bit is used for non-DMA read transfers. The eSDHC may implement
multiple buffers to transfer data efficiently. This read only flag indicates that valid data exists in the host
BREN
side buffer. If this bit is high, valid data greater than the watermark level exist in the buffer. A change of
this bit from 1 to 0 occurs when any read from the buffer is made. A change of this bit from 0 to1 occurs
when there is enough valid data ready in the buffer and the buffer read ready interrupt has been
generated and enabled.
0b - Read disable
1b - Read enable
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1040 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
Field Function
21 Buffer write enable. This status bit is used for non-DMA write transfers. The eSDHC can implement
multiple buffers to transfer data efficiently. This read only flag indicates if space is available for write data.
BWEN
If this bit is 1, valid data greater than the watermark level can be written to the buffer. A change of this bit
from 1 to 0 occurs when any write to the buffer is made. A change of this bit from 0 to 1 occurs when the
buffer can hold valid data greater than the write watermark level and the buffer write ready interrupt is
generated and enabled.
0b - Write disable
1b - Write enable
22 Read transfer active. This status bit is used for detecting completion of a read transfer.
RTA • This bit is set for either of the following conditions:
• After the end bit of the read command.
• When read operation is restarted by writing a 1 to PROCTL[CREQ].
• This bit is cleared for either of the following conditions:
• When the last data block as specified by block length is transferred to the system.
• In the case of ADMA2, end of read operation is designated by descriptor table.
• When all valid data blocks in the host controller have been transferred to the system and no
current block transfers are being sent as a result of the stop at block gap request being set to
1.
A transfer complete interrupt is generated when this bit changes to 0.
0b - No valid data
1b - Transferring data
23 Write transfer active. This status bit indicates a write transfer is active. If this bit is 0, it means no valid
write data exists in the eSDHC.
WTA
• This bit is set in either of the following cases:
• After the end bit of the write command.
• When write operation is restarted by writing a 1 to PROCTL[CREQ].
• This bit is cleared in either of the following cases:
• After getting the CRC status of the last data block as specified by the transfer count (single
and multiple). In case of ADMA2, transfer count is designated by descriptor table.
• After getting the CRC status of any block where data transmission is about to be stopped by
a stop at block gap request.
During a write transaction, a block gap event interrupt is generated when this bit is changed to 0, as result
of the stop at block gap request being set. This status is useful for the host driver in determining when to
issue commands during write busy state.
0b - No valid data
1b - Transferring data
24 SD clock gated off internally. This status bit indicates that the SD clock is internally gated off, because of
buffer over/under-run or read pause without read wait assertion.
SDOFF
0b - SD clock is active
1b - SD clock is gated off
25-27 Reserved.
—
28 SD clock stable. This status bit indicates that the internal card clock is stable. This bit is for the host driver
to poll clock status when changing the clock frequency. It is recommended to clear SYSCTL[SDCLKEN]
SDSTB
to remove glitch on the card clock when the frequency is changing.
0b - Clock is changing frequency and not stable
1b - Clock is stable
29 Data line active. This status bit indicates whether one of the DAT lines on the SD bus is in use.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1041
eSDHC register descriptions
Field Function
DLA In the case of read transactions:
• This status indicates if a read transfer is executing on the SD bus. Changes in this value from 1 to
0, between data blocks, generates a block gap event interrupt in the interrupt status register
(IRQSTAT).
• This bit will be set in either of the following cases:
• After the end bit of the read command.
• When writing a 1 to PROCTL[CREQ] to restart a read transfer.
• This bit should be cleared in either of the following cases:
• When the end bit of the last data block is sent from the SD bus to the host controller. In case
of ADMA2, the last block is designated by the last transfer of descriptor table.
• When a read transfer is stopped at the block gap initiated by a stop at block gap request.
• The eSDHC will wait at the next block gap by driving read wait at the start of the interrupt cycle. If
the read wait signal is already driven (data buffer cannot receive data), the eSDHC can wait for a
current block gap by continuing to drive the read wait signal. It is necessary to support read wait in
order to use the suspend/resume function. This bit will remain 1 during read wait.
In the case of write transactions:
• This status indicates that a write transfer is executing on the SD bus. Changes in this value from 1
to 0 generate a transfer complete interrupt in the interrupt status register (IRQSTAT).
• This bit will be set in either of the following cases:
• After the end bit of the write command.
• When writing to 1 to PROCTL[CREQ] to continue a write transfer.
• This bit will be cleared in either of the following cases:
• When the SD card releases write busy of the last data block. If SD card does not drive busy
signal for 8 SD Clocks, the host controller should consider the card drive "Not Busy". In case
of ADMA2, the last block is designated by the last transfer of descriptor table.
• When the SD card releases write busy, prior to waiting for write transfer, and as a result of a
stop at block gap request.
In the case of command with busy pending:
• Command with busy. This status indicates whether a command indicates busy (for example, erase
command for memory) is executing on the SD bus. This bit is set after the end bit of the command
with busy and cleared when busy is de-asserted.
Changing this bit from 1 to 0 generate a transfer complete interrupt in the interrupt status register
(IRQSTAT).
0b - DAT line inactive
1b - DAT line active
30 Command inhibit (DAT). This status bit is generated if either the DAT line active or the read transfer
active is set to 1. If this bit is 0, it indicates the eSDHC can issue the next SD/MMC Command.
CDIHB
Commands with busy signal belong to command inhibit (DAT) (for example, R1b, R5b type). Changing
from 1 to 0 generates a transfer complete interrupt in the interrupt status register (IRQSTAT).
NOTE: The SD host driver can save registers for a suspend transaction after this bit has changed from 1
to 0.
0b - Can issue command which uses the DAT line
1b - Cannot issue command which uses the DAT line
31 Command inhibit (CMD). If this status bit is 0, it indicates that the CMD line is not in use and the eSDHC
can issue a SD/MMC Command using the CMD line.
CIHB
This bit is set also immediately after the transfer type register (XFERTYP) is written. This bit is cleared
when the command response is received. Even if the command inhibit (DAT) is set to 1, Commands
using only the CMD line can be issued if this bit is 0. Changing from 1 to 0 generates a command
complete interrupt in the interrupt status register (IRQSTAT). If the eSDHC cannot issue the command
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1042 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
Field Function
because of a command conflict error (Refer to command CRC error) or because of a command not
issued by Auto CMD12 Error, this bit will remain 1 and the command complete is not set. The status of
issuing an Auto CMD12 does not show on this bit.
0b - Can issue command using only CMD line
1b - Cannot issue command
22.3.12 Protocol control register (PROCTL)
22.3.12.1 Offset
Register Offset
PROCTL 28h
22.3.12.2 Function
There are three cases to restart the transfer after stop at the block gap. Which case is
appropriate depends on whether the eSDHC issues a suspend command or the SD card
accepts the suspend command.
1. If the host driver does not issue a suspend command, the continue request should be
used to restart the transfer.
2. If the host driver issues a suspend command and the SD card accepts it, a resume
command should be used to restart the transfer.
3. If the host driver issues a suspend command and the SD card does not accept it, the
continue request should be used to restart the transfer.
Any time a stop at block gap request stops the data transfer, the host driver should wait
for a transfer complete (in the interrupt status register, IRQSTAT), before attempting to
restart the transfer. When restarting the data transfer by continue request, the host driver
should clear the stop at block gap request before or simultaneously.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1043
eSDHC register descriptions
22.3.12.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
WECINS
WECRM
WECINT
Reserved
Reserved
SABGRE
RWCTL
CREQ
IABG
W
Q
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
VOLT_SEL
Reserved
Reserved
Reserved
EMODE
DMAS
CDTL
DTW
CDS
W
S
Reset 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
22.3.12.4 Fields
Field Function
0-4 Reserved.
—
5 Wakeup event enable on SD card removal
WECRM Wakeup event enable on SD card removal. This bit enables a wakeup event, via a card removal, in the
interrupt status register (IRQSTAT). FN_WUS (wake up support) in CIS of SDIO card does not effect this
bit. When this bit is set, the card removal status and the eSDHC interrupt can be asserted without
SDHC_CLK toggling. When the wakeup feature is not enabled, the SDHC_CLK must be active in order to
assert the card removal status and the eSDHC interrupt.
0b - Disable
1b - Enable
6 Wakeup event enable on SD card insertion
WECINS Wakeup event enable on SD card insertion. This bit enables a wakeup event, via a card insertion, in the
interrupt status register (IRQSTAT). FN_WUS (wake up support) in CIS of the SDIO card does not affect
this bit. When this bit is set, the card insertion status and the eSDHC interrupt can be asserted without
SDHC_CLK toggling. When the wakeup feature is not enabled, the SDHC_CLK must be active in order to
assert the card insertion status and the eSDHC interrupt.
0b - Disable
1b - Enable
7 Wakeup event enable on card interrupt
WECINT Wakeup event enable on card interrupt. This bit enables a wakeup event, via a card interrupt, in the
interrupt status register (IRQSTAT). This bit can be set to 1 if FN_WUS (wake up support) in CIS of SDIO
card is set to 1. When this bit is set, the card interrupt status and the eSDHC interrupt can be asserted
without SDHC_CLK toggling. When the wakeup feature is not enabled, the SDHC_CLK must be active in
order to assert the card interrupt status and the eSDHC interrupt.
0b - Disable
1b - Enable
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1044 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
Field Function
8-11 Reserved.
—
12 Interrupt at block gap. This bit is valid only in 4-bit mode of the SDIO card, and selects a sample point in
the interrupt cycle. Setting to 1 enables interrupt detection at the block gap for a multiple block transfer.
IABG
Setting to 0 disables interrupt detection during a multiple block transfer. If the SDIO card cannot signal an
interrupt during a multiple block transfer, this bit should be set to 0 to avoid an inadvertent interrupt. When
the host driver detects an SDIO card insertion, it should set this bit according to the CCCR of the card.
0b - Disable
1b - Enable
13 Read wait control. The read wait function is optional for SDIO cards. If the card supports read wait, set
this bit to enable use of the read wait protocol to stop read data using the DAT[2] line. Otherwise the
RWCTL
eSDHC has to stop the SD Clock to hold read data, which restricts commands generation. When the host
driver detects an SDIO card insertion, it should set this bit according to the CCCR of the card. If the card
does not support read wait, this bit should never be set to 1, otherwise DAT line conflicts may occur. If
this bit is set to 0, stop at block gap during read operation is also supported, but the eSDHC will stop the
SD clock to pause reading operation.
0b - Disable read wait control, and stop SD clock at block gap when SABGREQ bit is set
1b - Enable read wait control, and assert read wait without stopping SD clock at block gap when
SABGREQ bit is set
14 Continue request. This bit is used to restart a transaction, which was stopped using the stop at block gap
request. To cancel stop at the block gap, set stop at block gap request to 0 and set this bit 1 to restart the
CREQ
transfer.
The eSDHC automatically clears this bit in either of the following cases:
• In the case of a read transaction, the DAT line active changes from 0 to 1 as a read transaction
restarts.
• In the case of a write transaction, the write transfer active changes from 0 to 1 as the write
transaction restarts.
Therefore, it is not necessary for host driver to set this bit to 0. If stop at block gap request is set to 1, any
write to this bit is ignored.
0b - No effect
1b - Restart
15 Stop at block gap request
SABGREQ Stop at block gap request. This bit is used to stop executing a transaction at the next block gap for both
DMA and non-DMA transfers. Until the transfer complete is set to 1, indicating a transfer completion, the
host driver should leave this bit set to 1. Clearing both the stop at block gap request and continue request
does not cause the transaction to restart. Read wait is used to stop the read transaction at the block gap.
The eSDHC will honor the stop at block gap request for write transfers, but for read transfers it requires
that the SDIO card support read wait. Therefore, the host driver should not set this bit during read
transfers unless the SDIO card supports read wait and has set the read wait control to 1, otherwise the
eSDHC will stop the SD bus clock to pause the read operation during block gap. In the case of write
transfers in which the host driver writes data to the data port register, the host driver should set this bit
after all block data is written. If this bit is set to 1, the host driver should not write data to the data port
register after a block is sent. Once this bit is set, the host driver should not clear this bit before the
transfer complete bit in (IRQSTAT)is set, otherwise the eSDHCs behavior is undefined.
This bit effects read transfer active, write transfer active, PRSSTAT[DLA] and PRSSTAT[CDIHB].
0b - Transfer
1b - Stop
16-20 Reserved.
—
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1045
eSDHC register descriptions
Field Function
21 Voltage selection
VOLT_SEL Voltage selection. Change the value of output signal SDHC_VS , to control the SD bus supply voltage for
external card. There must be a control circuit out of eSDHC to change the voltage.
0b - Change the SD Bus Supply voltage to high voltage range, around 3.0V
1b - Change the SD bus supply voltage to low voltage range, around 1.8V
22-23 DMA select
DMAS DMA select. This field is valid while DMA (SDMA or ADMA) is enabled and selects the DMA operation.
00b - Single DMA is selected
01b - ADMA1 is selected
10b - 32-bit address ADMA2 is selected
11b - Reserved
24 Card detect signal selection. This bit selects the source for the card detection.
CDSS 0b - SD CD pin is selected (for normal purposes)
1b - Card detection test level is selected (for test purposes)
25 Card detect test level. This is bit is enabled while the card detection signal selection is set to 1 and it
indicates card insertion.
CDTL
0b - Card detect test level is 0, no card inserted
1b - Card detect test level is 1, card inserted
26-27 Endian mode. The eSDHC supports little and big endian mode for transferring between buffer port
register and data buffer.
EMODE
00b - Big endian mode
01b - Reserved
10b - Little endian mode
11b - Reserved
28 Reserved.
—
29-30 Data transfer width. This bit selects the data width of the SD bus for a data transfer. The host driver
should set it to match the data width of the card. Possible Data transfer widths are 1-bit, 4-bits, and 8-bits.
DTW
00b - 1-bit mode
01b - 4-bit mode
10b - 8-bit mode
11b - Reserved
31 Reserved.
—
22.3.13 System Control Register when ESDHCCTL[CRS=0]
(SYSCTL_ESDHCCTL_CRS_0)
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1046 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
22.3.13.1 Offset
Register Offset
SYSCTL_ESDHCCTL_ 2Ch
CRS_0
22.3.13.2 Function
The clock divider mode(16-27 bits in this register) is selected according to Clock
Register Select field in eSDHC Control register. Other bits of the register remain
unaffected by clock register select value.
22.3.13.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
Reserved
Reserved
DTOCV
INITA
RST
RST
RST
W
D
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
SDCLKEN
Reserved
SDCLKF
DVS
W
S
Reset 1 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0
22.3.13.4 Fields
Field Function
0-3 Reserved.
—
4 Initialization active. When this bit is set, 80 SD clocks are sent to the card. After the 80 clocks are sent,
this bit is self cleared. This bit is very useful during the card power-up period when 74 SD-Clocks are
INITA
needed. Writing 1 to this bit when this bit is already 1 has no effect. Writing 0 to this bit at any time has no
effect. When either PRSSTAT[CIHB] or PRSSTAT[CDIHB] are set, writing 1 to this bit is ignored (that is,
when command line or data lines are active, write to this bit is not allowed). On the other hand, when this
bit is set, that is, during intialization active period, it is allowed to issue command, and the command bit
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1047
eSDHC register descriptions
Field Function
stream will appear on the CMD pad after all 80 clock cycles are done. So when this command ends, the
driver can make sure the 80 clock cycles are sent out. This is very useful when the driver needs send 80
cycles to the card and does not want to wait till this bit is self cleared.
5 Software reset for DAT line. Only part of the data circuit is reset. DMA circuit is also reset.
RSTD The following registers and bits are cleared by this bit:
• Data port register
• Buffer is cleared and initialized
• Present state register (PRSSTAT)
• Buffer read enable
• Buffer write enable
• Read transfer active
• Write transfer active
• DAT line active
• Command inhibit (DAT)
• Protocol control register (PROCTL)
• Continue request
• Stop at block gap request
• Interrupt status register (IRQSTAT)
• Buffer read ready
• Buffer write ready
• DMA interrupt
• Block gap event
• Transfer complete
NOTE: This bit will be self cleared by eSDHC when Software Reset for Data is complete, so Software
should poll for it to be cleared after setting it.
0b - No reset
1b - Reset
6 Software reset for CMD line. Only part of the command circuit is reset.
RSTC The following registers and bits are cleared by this bit:
• PRSSTAT[CIHB]
• IRQSTAT[CC]
NOTE: This bit will be self cleared by eSDHC when Software Reset for Command is complete, so
software should poll for it to be cleared after setting it.
0b - No reset
1b - Reset
7 Software reset for all. This reset effects the entire host controller except for the card detection circuit.
Register bits of type R, RW, RW1C are cleared. During its initialization, the host driver should set this bit
RSTA
to 1 to reset the eSDHC. The eSDHC should reset this bit to 0 when the capabilities registers are valid
and the host driver can read them. Additional use of software reset for all does not affect the value of the
capabilities registers. After this bit is set, it is recommended that the host driver reset the external card
and re-initialize it.
NOTE: The Software Reset For All in the System Control register clears Card Insertion and Card
Removal bits in Interrupt Status Register. Software should issue partial reset(Reset for
Command and Reset for Data) instead of Reset for All, if it wants to reset eSDHC without
clearing these Interrupt Status Register bits.
This bit will be self cleared by eSDHC when Software Reset for All is complete, so Software
should poll for it to be cleared after setting it.
0b - No reset
1b - Reset
8-11 Reserved.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1048 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
Field Function
—
12-15 Data timeout counter value
DTOCV Data timeout counter value. This value determines the interval by which DAT line timeouts are detected.
Refer to the data timeout error bit in the Interrupt status enable register (IRQSTATEN) for information on
factors that dictate time-out generation. Time-out clock frequency will be generated by dividing the
SDCLK value by this value.
The host driver can clear IRQSTATEN[DTOESEN] to prevent inadvertent time-out events.
0000b - SDCLK x 2 13
0001b - SDCLK x 2 14
1110b - SDCLK x 2 27
1111b - Reserved
16-23 SDCLK frequency select. This register is used to select the frequency of the SDCLK pin. The frequency is
not programmed directly, rather this register holds the prescaler (this register) and divisor (next register)
SDCLKFS
of the base clock frequency register.
Base clock can be selected by programming ESDHCCTL[PCS]. It selects between platform clock and
peripheral clock / 2 .
Setting 0x00 bypasses the frequency prescaler of the SD clock. Multiple bits must not be set, or the
behavior of this prescaler is undefined. The two default divider values can be calculated by the frequency
of the base clock and the following divisor bits.
The frequency of SDCLK is set by the following formula: Clock Frequency = (Base Clock) / (prescaler x
divisor)
For example, if the base clock frequency is 96 MHz and the target frequency is 25 MHz, then choosing
the prescaler value of 0x01 and divisor value of 0x1 will yield 24 MHz, which is the nearest frequency less
than or equal to the target. Similarly, to approach a clock value of 400 KHz, the prescaler value of 0x08
and divisor value of 0xE yields the exact clock value of 400 KHz.
The reset value of this bit field is 0x80, so if the input base clock is about 96 MHz, the default SD clock
after reset is 375 KHz.
The programmed SD Clock frequency shall never exceed maximum SD clock supported by the card.
NOTE: Both DVS and SDCLKFS fields should not be programmed 0 simultaneously.
Only the following settings are allowed:
00000000b - Base clock
00000001b - Base clock divided by 2
00000010b - Base clock divided by 4
00000100b - Base clock divided by 8
00001000b - Base clock divided by 16
00010000b - Base clock divided by 32
00100000b - Base clock divided by 64
01000000b - Base clock divided by 128
10000000b - Base clock divided by 256
24-27 Divisor. This register is used to provide a more exact divisor to generate the desired SD clock frequency.
DVS Note the divider can even support odd divisor without deterioration of duty cycle. The settings are as
following:
0000b - Divisor by 1
0001b - Divisor by 2 ...
1110b - Divisor by 15
1111b - Divisor by 16
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1049
eSDHC register descriptions
Field Function
28 SD clock enable. the host controller should stop SDCLK when writing this bit to 0. SDCLK frequency can
be changed when this bit is 0. Then, the host controller should maintain the same clock frequency until
SDCLKEN
SDCLK is stopped (stop at SDCLK=0). If PRSSTAT[CINS] is cleared, this bit should be cleared by the
host driver to save power.
29-31 Reserved.
—
22.3.14 System Control Register when ESDHCCTL[CRS=1]
(SYSCTL_ESDHCCTL_CRS_1)
22.3.14.1 Offset
Register Offset
SYSCTL_ESDHCCTL_ 2Ch
CRS_1
22.3.14.2 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
Reserved
Reserved
DTOCV
INITA
RST
RST
RST
W
D
Reset 0 0 0 0 u u u u 0 0 0 0 u u u u
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
SDCLKEN
USDCLKF
Reserved
Reserved
SDCLKF
CG
W
S
S
Reset u u u u u u u u u u u 0 u 0 0 0
22.3.14.3 Fields
Field Function
0-3 Reserved.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1050 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
Field Function
—
4 Initialization active. When this bit is set, 80 SD clocks are sent to the card. After the 80 clocks are sent,
this bit is self cleared. This bit is very useful during the card power-up period when 74 SD-Clocks are
INITA
needed. Writing 1 to this bit when this bit is already 1 has no effect. Writing 0 to this bit at any time has no
effect. When either PRSSTAT[CIHB] or PRSSTAT[CDIHB] are set, writing 1 to this bit is ignored (that is,
when command line or data lines are active, write to this bit is not allowed). On the other hand, when this
bit is set, that is, during intialization active period, it is allowed to issue command, and the command bit
stream will appear on the CMD pad after all 80 clock cycles are done. So when this command ends, the
driver can make sure the 80 clock cycles are sent out. This is very useful when the driver needs send 80
cycles to the card and does not want to wait till this bit is self cleared.
5 Software reset for DAT line. Only part of the data circuit is reset. DMA circuit is also reset.
RSTD The following registers and bits are cleared by this bit:
• Data port register
• Buffer is cleared and initialized
• Present state register (PRSSTAT)
• Buffer read enable
• Buffer write enable
• Read transfer active
• Write transfer active
• DAT line active
• Command inhibit (DAT)
• Protocol control register (PROCTL)
• Continue request
• Stop at block gap request
• Interrupt status register (IRQSTAT)
• Buffer read ready
• Buffer write ready
• DMA interrupt
• Block gap event
• Transfer complete
NOTE: This bit will be self cleared by eSDHC when Software Reset for Data is complete, so Software
should poll for it to be cleared after setting it.
0b - No reset
1b - Reset
6 Software reset for CMD line. Only part of the command circuit is reset.
RSTC The following registers and bits are cleared by this bit:
• PRSSTAT[CIHB]
• IRQSTAT[CC]
NOTE: This bit will be self cleared by eSDHC when Software Reset for Command is complete, so
software should poll for it to be cleared after setting it.
0b - No reset
1b - Reset
7 Software reset for all. This reset effects the entire host controller except for the card detection circuit.
Register bits of type R, RW, RW1C are cleared. During its initialization, the host driver should set this bit
RSTA
to 1 to reset the eSDHC. The eSDHC should reset this bit to 0 when the capabilities registers are valid
and the host driver can read them. Additional use of software reset for all does not affect the value of the
capabilities registers. After this bit is set, it is recommended that the host driver reset the external card
and re-initialize it.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1051
eSDHC register descriptions
Field Function
NOTE: The software reset for all in the system control register clears card insertion and card removal
bits in interrupt status register. Software should issue partial reset (reset for command and reset
for data) instead of reset for all, if it wants to reset eSDHC without clearing these interrupt status
register bits.
This bit will be self cleared by eSDHC when software reset for all is complete, so software
should poll for it to be cleared after setting it.
0b - No reset
1b - Reset
8-11 Reserved.
—
12-15 Data timeout counter value
DTOCV Data timeout counter value. This value determines the interval by which DAT line timeouts are detected.
Refer to the data timeout error bit in the Interrupt status enable register (IRQSTATEN) for information on
factors that dictate time-out generation. Time-out clock frequency will be generated by dividing the
SDCLK value by this value.
The host driver can clear IRQSTATEN[DTOESEN] to prevent inadvertent time-out events.
0000b - SDCLK x 2 13
0001b - SDCLK x 2 14
1110b - SDCLK x 2 27
1111b - Reserved
16-23 SDCLK Frequency Select:
SDCLKFS This register is used to select the frequency of the SDCLK pin. 10-bit divisor value is formed by
concatenating USDCLKFS(2-bit) and SDCLKFS(8-bit), that is, Divisor = {USDCLKFS[0:1],
SDCLKFS[0:7]}
Following Divisor definition is selected depending on Clock Generation Select value:
10-bit Divided Clock Mode
0x3FF Base clock divided by 2048
0x04 Base clock divided by 8
0x03 Base clock divided by 6
0x02 Base clock divided by 4
0x01 Base clock divided by 2
0x00 Reserved
10-bit Programmable Clock Mode
0x3FF Base clock divided by 1024
0x04 Base clock divided by 5
0x03 Base clock divided by 4
0x02 Base clock divided by 3
0x01 Base clock divided by 2
0x00 Reserved
The frequency of SDCLK is set by the following formula: Clock Frequency = (Base Clock) / (divisor)
24-25 Upper bits of SDCLK frequency select. This field is used to expand SDCLKFS to 10 bits. These two bits
occupies most significant portion of 10-bit SDCLKFS.
USDCLKFS
26 Clock Generator Select. This field selects 10-bit SDCLKFS clock mode.
0b - Divided clock mode is selected
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1052 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
Field Function
CGS 1b - Programmable clock mode is selected
27 Reserved.
—
28 SD clock enable. The host controller shall stop SDCLK when writing this bit to 0. SDCLK frequency can
be changed when this bit is 0. Then, the host controller shall maintain the same clock frequency until
SDCLKEN
SDCLK is stopped (Stop at SDCLK=0). If the card inserted in the present state register is cleared, this bit
should be cleared by the host driver to save power.
29-31 Reserved.
—
22.3.15 Interrupt status register (IRQSTAT)
22.3.15.1 Offset
Register Offset
IRQSTAT 30h
22.3.15.2 Function
An interrupt is generated when the normal interrupt signal enable is enabled and at least
one of the status bits is set to 1. For most bits, writing 1 to a bit clears it; writing to 0
keeps the bit unchanged. More than one status can be cleared with a single register write.
For card interrupt, before writing 1 to clear, it is required that the card stops asserting the
interrupt, meaning that when the card driver services the interrupt condition, otherwise
the CINT bit will be asserted again
Table 22-5. eSDHC Status for Command Timeout Error/Command Complete Bit
Combinations
Command Complete Command Timeout Error Meaning of the Status
0 0 X
X 1 Response not received within 64 SDCLK cycles
1 0 Response received
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1053
eSDHC register descriptions
Table 22-6. eSDHC Status for Data Timeout Error/Transfer Complete Bit Combinations
Transfer Complete Data Timeout Error Meaning of the Status
0 0 X
0 1 Timeout occurred during transfer
1 X Data Transfer Complete
Table 22-7. eSDHC Status for Command CRC Error/Command Timeout Error Bit
Combinations
Command CRC Error Command Timeout Error Meaning of the Status
0 0 No error
0 1 Response Timeout Error
1 0 Response CRC Error
1 1 CMD line conflict
22.3.15.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
W1C ADMAE
W1C AC12E
RTOE
DMAE
DTOE
CTOE
DCE
CCE
TNE
DEB
CEB
R
Reserved
Reserved
Reserved
CI
E
E
E
W1C
W1C
W1C
W1C
W1C
W1C
W1C
W1C
W1C
W1C
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
W1C CINS
W1C BWR
CINT
W1C CRM
W1C DINT
CC
R
TC
BG
RT
BR
Reserved
Reserved
E
E
W1C
W1C
W1C
W1C
W1C
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
22.3.15.4 Fields
Field Function
0-1 Reserved.
—
2 Register access timeout error. This bit indicate that register access has timed-out.
0b - No timeout error
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1054 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
Field Function
RTOE 1b - Timeout error
3 DMA error
DMAE DMA error. This bit indicates that DMA (SDMA or ADMA) transfer has failed.
0b - No error
1b - Error
4 Reserved.
—
5 Tuning Error. This bit is set when an unrecoverable error is detected in a tuning circuit except during
tuning procedure (Occurrence of an error during tuning procedure is indicated by Sampling Clock Select).
TNE
By detecting Tuning Error, Host Driver needs to abort a command executing and perform tuning. The
Tuning Error is higher priority than the other error interrupts generated during data transfer. By detecting
Tuning Error, the Host Driver should discard data transferred by a current read/write command and retry
data transfer after the Host Controller retrieved from tuning circuit error. This bit might not be set in some
cases, but SD command or Data error might be set; Driver should consider it as tuning circuit error and
perform tuning procedure.
0b - No error
1b - Error
6 ADMA error. This bit is set when the host controller detects errors during ADMA operation. The state of
the ADMA at an error occurrence is saved in the ADMA error status register.
ADMAE
0b - No error
1b - Error
7 Auto CMD12 error. Occurs when detecting that one of the bits in the Auto CMD12 error status register
(AUTOC12ERR) has changed from 0 to 1. This bit is set to 1, not only when the errors in Auto CMD12
AC12E
occur, but also when the Auto CMD12 is not executed due to the previous command error.
0b - No error
1b - Error
8 Reserved.
—
9 Data end bit error. Occurs either when detecting 0 at the end bit position of read data, which uses the
DAT line, or at the end bit position of the CRC.
DEBE
0b - No error
1b - Error
10 Data CRC error. Occurs when detecting a CRC error when transferring read data, which uses the DAT
line, or when detecting the write CRC status having a value other than 010.
DCE
0b - No error
1b - Error
11 Data timeout error. Occurs when detecting one of following time-out conditions.
DTOE • Busy time-out for R1b, R5b type
• Busy time-out after write CRC status
• Write CRC status time-out
• Read data time-out
0b - No error
1b - Time out
12 Command index error. Occurs if a command index error occurs in the command response.
CIE 0b - No error
1b - Error
13 Command end bit error. Occurs when detecting that the end bit of a command response is 0.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1055
eSDHC register descriptions
Field Function
CEBE 0b - No error
1b - End bit error generated
14 Command CRC error. A command crc error is generated in two cases:
CCE • If a response is returned and the command timeout error is set to 0 (indicating no time-out), this bit
is set when detecting a CRC error in the command response.
• The eSDHC detects a CMD line conflict by monitoring the CMD line when a command is issued. If
the eSDHC drives the CMD line to 1, but detects 0 on the CMD line at the next SDCLK edge, then
the eSDHC should abort the command (stop driving CMD line) and set this bit to 1. The command
timeout error should also be set to 1 to distinguish CMD line conflict.
0b - No error
1b - CRC error generated
15 Command timeout error
CTOE Command timeout error. Occurs only if no response is returned within 64 SDCLK cycles from the end bit
of the command. If the eSDHC detects a CMD line conflict, in which case a command CRC error should
also be set (as shown in ), this bit should be set without waiting for 64 SDCLK cycles. This is because the
command will be aborted by the eSDHC.
0b - No error
1b - Time out
16-18 Reserved.
—
19 Re-tuning event. This status is set if re-tuning request in the eSDHC control register changes from 0 to 1.
eSDHC requests host driver to perform re-tuning for next data transfer. Current data transfer (not large
RTE
block count) can be completed without re-tuning.
0b - Re-tuning is not required
1b - Re-tuning should be performed
20-22 Reserved.
—
23 Card interrupt. Writing this bit to 1 does not clear this bit. It is cleared by resetting the SD card interrupt
factor. In 1-bit mode, the host controller should detect the card interrupt without SD clock to support
CINT
wakeup. In 4-bit mode, the card interrupt signal is sampled during the interrupt cycle, so there are some
sample delays between the interrupt signal from the SD card and the interrupt to the host system. It is
necessary to define how to handle this delay.
When this status has been set and the host driver needs to start this interrupt service,
IRQSTATEN[CINTSEN] should be set to 0 in order to clear the card interrupt statuses latched in the
eSDHC and to stop driving the interrupt signal to the host system. After completion of the card interrupt
service (It should reset interrupt factors in the SD card and the interrupt signal may not be asserted), set
the card interrupt status enable bit to 1 and start sampling the interrupt signal again.
0b - No card interrupt
1b - Generate card interrupt
24 Card removal. This status is set if the PRSSTAT[CINS] changes from 1 to 0.
CRM When the host driver writes this bit to 1 to clear this status, the status of the PRSSTAT[CINS] should be
confirmed. Because the card detect state may possibly be changed when the host driver clear this bit and
interrupt event may not be generated.
NOTE: The Software Reset For All in the System Control register clears this bit. Software should issue
partial reset(Reset for Command and Reset for Data) instead of Reset for All, if it wants to reset
eSDHC without clearing this bit.
eSDHC does not implement de-bouncing circuit on card detect pin, so Software should check
Card Inserted in Present State register to confirm card insertion/removal status.
0b - Card state unstable or inserted
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1056 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
Field Function
1b - Card removed
25 Card insertion. This status is set if PRSSTAT[CINS] changes from 0 to 1.
CINS When the host driver writes this bit to 1 to clear this status, the status of the PRSSTAT[CINS] should be
confirmed. Because the card detect state may possibly be changed when the host driver clear this bit and
interrupt event may not be generated.
NOTE: The Software Reset For All in the System Control register clears this bit. Software should issue
partial reset(Reset for Command and Reset for Data) instead of Reset for All, if it wants to reset
eSDHC without clearing this bit.
eSDHC does not implement de-bouncing circuit on card detect pin, so Software should check
Card Inserted in Present State register to confirm card insertion/removal status.
0b - Card state unstable or removed
1b - Card inserted
26 Buffer read ready
BRR Buffer read ready. This status bit is set if PRSSTAT[BREN] changes from 0 to 1. Refer to the description
of the buffer read enable bit in Present state register (PRSSTAT) for additional information.
0b - Not ready to read buffer
1b - Ready to read buffer
27 Buffer write ready
BWR Buffer write ready. This status bit is set if the PRSSTAT[BWEN] changes from 0 to 1. Refer to the
description of the buffer write enable bit in Present state register (PRSSTAT) for additional information.
0b - Not ready to write buffer
1b - Ready to write buffer
28 DMA interrupt
DINT DMA interrupt. Occurs only when the DMA finishes the data transfer successfully. Whenever errors occur
during data transfer, this bit will not be set. Instead, the DMAE bit will be set. Either single DMA or ADMA
finishes data transferring, this bit will be set.
0b - No DMA Interrupt
1b - DMA Interrupt is generated
29 Block gap event. If PROCTL[SABGREQ] is set, this bit is set when a read or write transaction is stopped
at a block gap. If PROCTL[SABGREQ] is not set to 1, this bit is not set to 1.
BGE
• In the case of a read transaction, this bit is set at the falling edge of the DAT Line active status
(when the transaction is stopped at SD bus timing). The read wait must be supported in order to
use this function.
• In the case of a write transaction, this bit is set at the falling edge of write transfer active status
(after getting CRC status at SD Bus timing).
0b - No block gap event
1b - Transaction stopped at block gap
30 Transfer complete. This bit is set when a read/write transfer and a command with busy is completed.
TC While performing tuning procedure (Execute Tuning is set to 1), Transfer Complete is not set for CMD19
execution.
0b - Transfer not complete
1b - Transfer complete
31 Command complete. This bit is set when the end bit of the command response is received (except Auto
CMD12). Refer to PRSSTAT[CIHB].
CC
0b - Command not complete
1b - Command complete
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1057
eSDHC register descriptions
22.3.16 Interrupt status enable register (IRQSTATEN)
22.3.16.1 Offset
Register Offset
IRQSTATEN 34h
22.3.16.2 Function
Setting the bits to 1 in the IRQSTATEN enables the corresponding interrupt status to be
set by the specified event. If any bit is cleared, the corresponding interrupt status bit is
also cleared (that is, when the bit in this register is cleared, the corresponding bit in
interrupt status register, IRQSTAT, is always 0).
NOTE
• Depending on how PROCTL[IABG] is set, eSDHC may be
programmed to sample the card interrupt signal during the
interrupt period and hold its value in the flip-flop. There
will be some delays on the card interrupt, asserted from the
card, to the time the host system is informed.
• To detect a CMD line conflict, the host driver must set both
IRSTAT[CTOESEN] and IRSTAT[CCESEN] to 1.
22.3.16.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
ADMAESEN
AC12ESEN
DMAESEN
Reserved
Reserved
Reserved
DEBESE
CEBESE
RTOESE
DTOESE
CTOESE
DCESE
CCESE
TNESE
CIESE
W
N
N
N
N
N
N
Reset 0 0 1 1 0 1 1 1 0 1 1 1 1 1 1 1
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
CINTSEN
CRMSEN
DINTSEN
CINSEN
Reserved
Reserved
BWRSE
BRRSE
BGESE
RTESE
CCSE
TCSE
W
N
N
N
N
N
Reset 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 1
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1058 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
22.3.16.4 Fields
Field Function
0-1 Reserved.
—
2 Register access timeout status enable
0b - Masked
RTOESEN
1b - Enabled
3 DMA error status enable.
DMAESEN 0b - Masked
1b - Enabled
4 Reserved.
—
5 Tuning error status enable
0b - Masked
TNESEN
1b - Enabled
6 ADMA error status enable.
ADMAESEN 0b - Masked
1b - Enabled
7 Auto CMD12 error status enable.
AC12ESEN 0b - Masked
1b - Enabled
8 Reserved.
—
9 Data end bit error status enable.
DEBESEN 0b - Masked
1b - Enabled
10 Data CRC error status enable.
DCESEN 0b - Masked
1b - Enabled
11 Data timeout error status enable.
DTOESEN 0b - Masked
1b - Enabled
12 Command index error status enable.
CIESEN 0b - Masked
1b - Enabled
13 Command end bit error status enable.
CEBESEN 0b - Masked
1b - Enabled
14 Command CRC error status enable.
CCESEN 0b - Masked
1b - Enabled
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1059
eSDHC register descriptions
Field Function
15 Command timeout error status enable.
CTOESEN 0b - Masked
1b - Enabled
16-18 Reserved.
—
19 Re-tuning event status enable.
0b - Masked
RTESEN
1b - Enabled
20-22 Reserved.
—
23 Card interrupt status enable. If this bit is set to 0, the eSDHC will clear the interrupt request to the system.
The card interrupt detection is stopped when this bit is cleared and restarted when this bit is set to 1. The
CINTSEN
host driver should clear the card interrupt status enable before servicing the card interrupt and should set
this bit again after all interrupt requests from the card are cleared to prevent inadvertent interrupts.
0b - Masked
1b - Enabled
24 Card removal status enable.
CRMSEN 0b - Masked
1b - Enabled
25 Card insertion status enable.
CINSEN 0b - Masked
1b - Enabled
26 Buffer read ready status enable.
BRRSEN 0b - Masked
1b - Enabled
27 Buffer write ready status enable.
BWRSEN 0b - Masked
1b - Enabled
28 DMA interrupt status enable.
DINTSEN 0b - Masked
1b - Enabled
29 Block gap event status enable.
BGESEN 0b - Masked
1b - Enabled
30 Transfer complete status enable.
TCSEN 0b - Masked
1b - Enabled
31 Command complete status enable.
CCSEN 0b - Masked
1b - Enabled
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1060 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
22.3.17 Interrupt signal enable register (IRQSIGEN)
22.3.17.1 Offset
Register Offset
IRQSIGEN 38h
22.3.17.2 Function
The IRQSIGEN is used to select which interrupt status is indicated to the host system as
the interrupt. These status bits all share the same interrupt line. Setting any of these bits to
1 enables interrupt generation. The corresponding status register bit will generate an
interrupt when the corresponding interrupt signal enable bit is set.
22.3.17.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
ADMAEIEN
AC12EIEN
DMAEIEN
DTOEIEN
CTOEIEN
DCEIEN
CCEIEN
Reserved
Reserved
Reserved
DEBEIE
CEBEIE
RTOEIE
TNEIE
CIEIE
W
N
N
N
N
Reset 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
CINSIEN
BWRIEN
CINTIEN
CRMIEN
DINTIEN
Reserved
Reserved
CCIEN
TCIEN
BRRIE
BGEIE
RTEIE
W
N
Reset 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
22.3.17.4 Fields
Field Function
0-1 Reserved.
—
2 Register timeout error interrupt enable
0b - Masked
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1061
eSDHC register descriptions
Field Function
RTOEIEN 1b - Enable
3 DMA error interrupt enable.
DMAEIEN 0b - Masked
1b - Enabled
4 Reserved.
—
5 Tuning error interrupt enable
0b - Masked
TNEIEN
1b - Enable
6 ADMA Error Interrupt Enable.
ADMAEIEN
7 Auto CMD12 error interrupt enable.
AC12EIEN 0b - Masked
1b - Enabled
8 Reserved.
—
9 Data end bit error interrupt enable.
DEBEIEN 0b - Masked
1b - Enabled
10 Data CRC error interrupt enable.
DCEIEN 0b - Masked
1b - Enabled
11 Data timeout error interrupt enable.
DTOEIEN 0b - Masked
1b - Enabled
12 Command index error interrupt enable.
CIEIEN 0b - Masked
1b - Enabled
13 Command end bit error interrupt enable.
CEBEIEN 0b - Masked
1b - Enabled
14 Command CRC error interrupt enable.
CCEIEN 0b - Masked
1b - Enabled
15 Command timeout error interrupt enable.
CTOEIEN 0b - Masked
1b - Enabled
16-18 Reserved.
—
19 Re-tuning event interrupt enable
0b - Masked
RTEIEN
1b - Enabled
20-22 Reserved.
—
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1062 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
Field Function
23 Card interrupt interrupt enable.
CINTIEN 0b - Masked
1b - Enabled
24 Card removal interrupt enable.
CRMIEN 0b - Masked
1b - Enabled
25 Card insertion interrupt enable.
CINSIEN 0b - Masked
1b - Enabled
26 Buffer read ready interrupt enable.
BRRIEN 0b - Masked
1b - Enabled
27 Buffer write ready interrupt enable.
BWRIEN 0b - Masked
1b - Enabled
28 DMA interrupt enable.
DINTIEN 0b - Masked
1b - Enabled
29 Block gap event interrupt enable.
BGEIEN 0b - Masked
1b - Enabled
30 Transfer complete interrupt enable.
TCIEN 0b - Masked
1b - Enabled
31 Command complete interrupt enable.
CCIEN 0b - Masked
1b - Enabled
22.3.18 Auto CMD Error Status Register / System Control 2
Register (AUTOCERR_SYSCTL2)
22.3.18.1 Offset
Register Offset
AUTOCERR_SYSCTL2 3Ch
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1063
eSDHC register descriptions
22.3.18.2 Function
When the Auto CMD12 error status bit in the AUTOC12ERR is set, the host driver
checks this register to identify the kind of error indicated by the Auto CMD12. This
register is valid only when the auto CMD12 error status bit is set.
Table 22-8. Relationship Between Command CRC Error and Command Timeout Error for
Auto CMD12
Auto CMD12 CRC Error Auto CMD12 Timeout Error Type of Error
0 0 No Error
0 1 Response Timeout Error
1 0 Response CRC Error
1 1 CMD line conflict
Changes in Auto CMD12 error status register (AUTOC12ERR) can be classified in three
scenarios:
1. When the eSDHC is going to issue an Auto CMD12
• Set bit 0 to 1 if the Auto CMD12 cannot be issued due to an error in the previous
command
• Set bit 0 to 0 if the Auto CMD12 is issued
2. At the end bit of an Auto CMD12 response
• Check errors correspond to bits 1-4
• Set bits 1-4 corresponding to detected errors
• Clear bits 1-4 corresponding to detected errors
3. Before reading the Auto CMD12 error status bit 7
• Set bit 7 to 1 if there is a command that cannot be issued
• Clear bit 7 if there is no command to issue
The timing for generating the Auto CMD12 error and writing to the command register are
asynchronous. After that, bit 7 should be sampled when the driver is not writing to the
command register. So it is suggested to read this register only when IRQSTAT[AC12E]
is set. An Auto CMD12 error interrupt is generated when one of the error bits (0-4) is set
to 1. The command not issued by Auto CMD12 Error does not generate an interrupt.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1064 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
22.3.18.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SMPCLKSE
Reserved
Reserved
Reserved
UHSM
AIE
EXT
W
N
L
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
CNIBAC12E
AC12EBE
AC12TOE
AC12CE
AC12NE
AC12IE
Reserved
Reserved
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
22.3.18.4 Fields
Field Function
0 Reserved.
—
1 Asynchronous Interrupt Enable. This bit can be set to 1 if a card supports asynchronous interrupts and
asynchronous interrupt support is set to 1 in capability register. If this bit is set to 1, host driver can stop
AIE
SDCLK during asynchronous inrrupt period to save power. During this period, eSDHC continues to
deliver the card interrupt to the system when it is assrted by card.
0b - Disabled
1b - Enabled
2-7 Reserved.
—
8 Sampling clock select. This bit is set by eSDHC during tuning procedure and valid after the completion of
tuning (when execute tuning is cleared). Setting 1 by eSDHC means that tuning is completed successfully
SMPCLKSEL
and setting 0 means that tuning is failed. Host driver should not write to this bit. Change of this bit is not
allowed while eSDHC is receiving response or a read data block.
0b - Tuning procedure unsuccessful
1b - Tuning procedure completed successfully
9 Execute Tuning. This bit is set to 1 by host driver to start tuning procedure and automatically cleared by
eSDHC when tuning procedure is completed. The result of tuning is indicated to sampling clock select
EXTN
field. Tuning procedure is aborted by writing 0.
0b - Not tuned or tuning not compelted
1b - Execute tuning
10-12 Reserved.
—
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1065
eSDHC register descriptions
Field Function
13-15 UHS mode select
UHSM UHS mode select. This field is used to select one of UHS-1 modes for SD 3.0 card; and select HS200or
DDR mode for MMC card.
Host driver should reset SDCLKEN in system control register before changing this field, and then set
SDCLKEN again.
000b - SDR12 for SD, or max 52 MHz mode for SD 2.0 / MMC 4.2 or older spec
001b - SDR25 for SD
010b - SDR50 for SD
011b - SDR104 for SD, HS200 for MMC
100b - DDR
101b - Rest all the fields are reserved
16-23 Reserved.
—
24 Command not issued by Auto CMD12 error. Setting this bit to 1 means CMD_wo_DAT is not executed
due to an Auto CMD12 error (D04-D01) in this register.
CNIBAC12E
0b - No error
1b - Not Issued
25-26 Reserved.
—
27 Auto CMD index error. Occurs if the command index error occurs in response to a command.
AC12IE 0b - No error
1b - Error, the CMD index in response is not CMD12
28 Auto CMD end bit error. Occurs when detecting that the end bit of command response is 0 which should
be 1.
AC12EBE
0b - No error
1b - End bit error generated
29 Auto CMD CRC error. Occurs when detecting a CRC error in the command response.
AC12CE 0b - No CRC error
1b - CRC error met in Auto CMD12 response
30 Auto CMD timeout error. Occurs if no response is returned within 64 SDCLK cycles from the end bit of
the command. If this bit is set to1, the other error status bits (2-4) have no meaning.
AC12TOE
0b - No error
1b - Time out
31 Auto CMD12 not executed. If memory multiple block data transfer is not started, due to a command error,
this bit is not set because it is not necessary to issue an Auto CMD12. Setting this bit to 1 means the
AC12NE
eSDHC cannot issue the Auto CMD12 to stop a memory multiple block data transfer due to some error. If
this bit is set to 1, other error status bits (1-4) have no meaning.
This bit is set to 0 when Auto CMD Error is generated by Auto CMD23.
0b - Executed
1b - Not executed
22.3.19 Host controller capabilities register (HOSTCAPBLT)
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1066 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
22.3.19.1 Offset
Register Offset
HOSTCAPBLT 40h
22.3.19.2 Function
The HOSTCAPBLT provides the host driver with information specific to the eSDHC
implementation. The value in this register is the power-on-reset value, and does not
change with a software reset. Any write to this register is ignored.
22.3.19.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
ADMAS
DMAS
SBS64
VS18
VS30
VS33
Reserved
Reserved
Reserved
MBL
AIS
R
SR
HS
S
S
B
W
Reset u u 1 1 u 1 u u 1 1 1 1 u 0 1 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
Reserved
W
Reset u u u u u u u u u u u u u u u u
22.3.19.4 Fields
Field Function
0-1 Reserved.
—
2 Asynchronous Interrupt Support. This bit indicates whether the eSDHC supports SDIO asynchronous
interrupt. Refer to SDIO Specification Version 3.0
AIS
0b - Asynchronous interrupt not supported
1b - Asynchronous interrupt supported
3 64-bit system bus support. This bit indicates that system supports 64-bit address descriptor mode and is
connected to 64-bit adress system bus.
SBS64B
0b - 64-bit system bus not supported
1b - 64-bit system bus supported
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1067
eSDHC register descriptions
Field Function
4 Reserved.
—
5 Voltage support 1.8V. This bit should depend on the host system ability.
VS18 0b - 1.8V not supported
1b - 1.8V supported
6 Voltage Support 3.0V. This bit shall depend on the Host System ability.
VS30 0b - 3.0V not supported
1b - 3.0V supported
7 Voltage support 3.3V. This bit should depend on the host system ability.
VS33 0b - 3.3V not supported
1b - 3.3V supported
8 Suspend/resume support. This bit indicates whether the eSDHC supports suspend/resume functionality.
If this bit is 0, the suspend and resume mechanism, as well as the read wait, are not supported, and the
SRS
host driver should not issue either suspend or resume commands.
0b - Not supported
1b - Supported
9 DMA support. This bit indicates whether the eSDHC is capable of using the DMA to transfer data
between system memory and the data buffer directly.
DMAS
0b - DMA not supported
1b - DMA supported
10 High speed support. This bit indicates whether the eSDHC supports high speed mode and the host
system can supply a SD clock frequency from 25-50 MHz.
HSS
0b - High speed not supported
1b - High speed supported
11 ADMA support. This bit indicates whether the eSDHC supports the ADMA feature.
ADMAS 0b - Advanced DMA not supported
1b - Advanced DMA supported
12 Reserved.
—
13-15 Maximum block length. This value indicates the maximum block size that the host driver can read and
write to the buffer in the eSDHC. The buffer should transfer block size without wait cycles.
MBL
000b - 512 bytes
001b - 1024 bytes
010b - 2048 bytes
011-111b - Reserved
16-31 Reserved.
—
22.3.20 Watermark level register (WML)
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1068 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
22.3.20.1 Offset
Register Offset
WML 44h
22.3.20.2 Function
Both write and read watermark levels (FIFO threshold) are configurable in the WML.
They can range from 1- 128 words. Both write and read burst lengths are also
configurable. They can range from 1- 16 beats.
22.3.20.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
WR_BRST_LE
WR_WML
Reserved
Reserved
W
N
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
RD_BRST_LE
RD_WML
Reserved
Reserved
W
N
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
22.3.20.4 Fields
Field Function
0-3 Reserved.
—
4-7 Max write burst length. Burst length desirable for write on system bus when DMA is used. This is the
maximum burst length, actual burst length may be less than this depending on other factors, such as
WR_BRST_LEN
block boundary
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1069
eSDHC register descriptions
Field Function
0000b - 16 transfers in a single burst
0001b - 1 transfer in a single burst
0010b - 2 transfers in a single burst
1111b - 15 transfers in a single burst
8 Reserved.
—
9-15 Write watermark level. The number of words (32-bit) used as the watermark level (FIFO threshold) for SD
write in CPU polling mode.
WR_WML
0000000b - 128 words
0000001b - 1 word
0000010b - 2 words
1111111b - 127 words
16-19 Reserved.
—
20-23Max read burst length. Burst length desirable for read on system bus when DMA is used. This is the
maximum burst length, actual burst length may be less than this depending on other factors, such as
RD_BRST_LEN
block boundary
0000b - 16 transfers in a single burst
0001b - 1 transfers in a single burst
0010b - 2 transfers in a single burst
1111b - 15 transfers in a single burst
24 Reserved.
—
25-31 Read watermark level. The number of words (32-bit) used as the watermark level (FIFO threshold) for SD
read in CPU polling mode.
RD_WML
0000000b - 128 words
0000001b - 1 word
0000010b - 2 words
1111111b - 127 words
22.3.21 Force event register (FEVT)
22.3.21.1 Offset
Register Offset
FEVT 50h
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1070 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
22.3.21.2 Function
The FEVT is not a physically implemented register. Rather, it is an address at which the
interrupt status register (IRQSTAT) can be written if the corresponding bit of the
interrupt status enable register (IRQSTATEN) is set. This register is a write only register
and writing 0 to it has no effect. Writing 1 to this register actually sets the corresponding
bit of interrupt status register (IRQSTAT). A read from this register always results in
zeros.
22.3.21.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R FEVTADMAE
FEVTAC12E
Reserved
Reserved
Reserved
FEVTDMAE
FEVTDTOE
FEVTCTOE
FEVTDEB
FEVTCEB
FEVTDC
FEVTCC
FEVTCI
W
E
E
E
E
E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
FEVTCNIBAC12E
FEVTAC12EBE
FEVTAC12TOE
FEVTAC12CE
FEVTAC12NE
FEVTAC12IE
Reserved
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
22.3.21.4 Fields
Field Function
0-2 Reserved.
—
3 Force event DMA error. Forces the IRQSTAT[DMAE] to be set.
FEVTDMAE
4-5 Reserved.
—
6 Force event ADMA error. Forces the IRQSTAT[ADMAE] to be set.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1071
eSDHC register descriptions
Field Function
FEVTADMAE
7 Force event Auto CMD12 error. Forces IRQSTAT[AC12E] to be set.
FEVTAC12E
8 Reserved.
—
9 Force event data end bit error. Forces IRQSTAT[DEBE] to be set.
FEVTDEBE
10 Force event data CRC error. Forces IRQSTAT[DCE] to be set.
FEVTDCE
11 Force event data time out error. Forces IRQSTAT[DTOE] to be set.
FEVTDTOE
12 Force event command index error. Forces the IRQSTAT[CCE] to be set.
FEVTCIE
13 Force event command end bit error. Forces IRQSTAT[CEBE] to be set.
FEVTCEBE
14 Force event command CRC error. Forces IRQSTAT[CCE] to be set.
FEVTCCE
15 Force event command time out error. Forces IRQSTAT[CTOE] to be set.
FEVTCTOE
16-23 Reserved.
—
24 Force event command not executed by Auto CMD12 error. Forces AUTOC12ERR[CNIBAC12E] to be
set.
FEVTCNIBAC12
E
25-26 Reserved.
—
27 Force event Auto CMD12 index error. Forces AUTOC12ERR[AC12IE] to be set.
FEVTAC12IE
28 Force event Auto CMD12 end bit error. Forces AUTOC12ERR[AC12EBE] to be set.
FEVTAC12EBE
29 Force event Auto CMD12 CRC error. Forces AUTOC12ERR[AC12CE] to be set.
FEVTAC12CE
30 Force event Auto CMD12 time out error. Forces the AUTOC12ERR[AC12TOE] to be set.
FEVTAC12TOE
31 Force event Auto CMD12 not executed. Forces AUTOC12ERR[AC12NE] to be set.
FEVTAC12NE
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1072 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
22.3.22 ADMA error status register (ADMAES)
22.3.22.1 Offset
Register Offset
ADMAES 54h
22.3.22.2 Function
When an ADMA error interrupt occurs, the ADMA error states field in the ADMAES
holds the ADMA state and the ADMA system address register (ADSADDR) holds the
address around the error descriptor.
For recovering from this error, the host driver requires the ADMA state to identify the
error descriptor address as follows:
• ST_STOP: Previous location set in the ADMA system address register (ADSADDR)
is the error descriptor address
• ST_FDS: Current location set in the ADMA system address register (ADSADDR) is
the error descriptor address
• ST_CADR: This state is never set because it only increments the descriptor pointer
and does not generate an ADMA error
• ST_TFR: Previous location set in the ADMA system address register (ADSADDR)
is the error descriptor address
In case of a write operation, the host driver should use the ACMD22 to get the number of
the written block rather than using this information, since unwritten data may exist in the
host controller.
The Host controller generates the ADMA error interrupt when it detects invalid
descriptor data (valid=0) in the ST_FDS state. The host driver can distinguish this error
by reading the valid bit of the error descriptor.
Table 22-9. ADMA Error State Coding
D30-D31 ADMA Error State (When Error Has Contents of ADMA System Address Register
Occurred)
00 IDLE (idle) Current descriptor address on which ADMA error occured
01 FETCH_DESC (fetch descriptor) Current descriptor address on which ADMA error occured
10 DATA_XFER (data transfer) Current descriptor address on which ADMA error occured
11 WAIT_STOP (Wait for ADMA to stop) Current descriptor address on which ADMA error occured
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1073
eSDHC register descriptions
22.3.22.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
ADMADCE
ADMALME
ADMAIBE
ADMAES
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
22.3.22.4 Fields
Field Function
0-26 Reserved.
—
27 ADMA internal bus error. This bit indicates that a system bus error occurred while ADMA transaction was
ADMAIBE underway. It is set when error response is received on the system bus.
0b - No error
1b - Error
28 ADMA descriptor error. This error occurs when invalid descriptor fetched by ADMA.
ADMADCE 0b - No error
1b - Error
29 ADMA length mismatch error. This error occurs in the following two cases:
ADMALME • While XFERTYP[BCEN] is being set, the total data length specified by the descriptor table is
different from that specified by the block count and block length
• Total data length can not be divided by the block length
0b - No error
1b - Error
30-31 ADMA error state (when ADMA error is occurred). This field indicates the state of the ADMA when an
error has occurred during an ADMA data transfer. Refer to the table above for more details.
ADMAES
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1074 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
22.3.23 ADMA system address register (ADSADDR)
22.3.23.1 Offset
Register Offset
ADSADDR 58h
22.3.23.2 Function
The ADSADDR contains the physical system memory address used for ADMA transfers.
22.3.23.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
ADS_ADDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
ADS_ADDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
22.3.23.4 Fields
Field Function
0-31 ADMA system address. This register holds 32-bit address of executing command of the descriptor table.
At the start of ADMA, the host driver should set start address of the descriptor table. The ADMA
ADS_ADDR
increments this register address, which points to next line, when every fetching a descriptor line. When
the ADMA error interrupt is generated, this register should hold valid descriptor address depending on the
ADMA state. The host driver should program descriptor table on 32-bit boundary and set 32-bit boundary
address to this register.
It can be accessed only when no transaction is executing (that is, after a transaction has stopped). The
host driver should initialize this register before starting an ADMA transaction.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1075
eSDHC register descriptions
22.3.24 Host controller version register (HOSTVER)
22.3.24.1 Offset
Register Offset
HOSTVER FCh
22.3.24.2 Function
The HOSTVER contains the vendor host controller version information. All bits are read
only and will read the same as the power-reset value.
22.3.24.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R VVN SVN
W
Reset 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0
22.3.24.4 Fields
Field Function
0-15 Reserved.
—
16-23 Vendor version number. These status bits are reserved for the vendor version number. The host driver
should not use this status.
VVN
Patterns not shown are reserved.
00000000b - eSDHC Version 1.0
00010000b - eSDHC Version 2.0
00010001b - eSDHC Version 2.1
00010010b - eSDHC Version 2.2
00010011b - eSDHC Version 2.3
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1076 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
Field Function
00100000b - eSDHC Version 3.0
00100001b - eSDHC Version 3.1
00100010b - eSDHC Version 3.2
24-31 Specification version number. These status bits indicate the host controller specification version.
SVN Patterns not shown are reserved.
00000000b - SD Host Specification Version 1.0
00000001b - SD Host Specification Version 2.0, supports test event register , and ADMA
00000010b - SD Host Specification Version 3.0
22.3.25 DMA error address register (DMAERRADDR)
22.3.25.1 Offset
Register Offset
DMAERRADDR 104h
22.3.25.2 Function
The DMAERRADDR contains the address of the transaction on which DMA error
occured.
22.3.25.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R DMA_ADDRn
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R DMA_ADDRn
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1077
eSDHC register descriptions
22.3.25.4 Fields
Field Function
0-31 DMA error address. This field contains the system address of the transaction on which DMA error
occured.
DMA_ADDRn
22.3.26 DMA error attribute register (DMAERRATTR)
22.3.26.1 Offset
Register Offset
DMAERRATTR 10Ch
22.3.26.2 Function
The DMAERRATTR contains attributes of the transaction on which DMA error occured.
22.3.26.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R DMA_SIZE DMA_LEN
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
22.3.26.4 Fields
Field Function
0-24 Reserved.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1078 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
Field Function
—
25-27 System bus burst size. This field contains burst size of the transaction on which DMA error occured.
DMA_SIZE
28-31 System bus burst length. This field contains burst length of the transaction on which DMA error occured.
DMA_LEN
22.3.27 Host controller capabilities register 2 (HOSTCAPBLT2)
22.3.27.1 Offset
Register Offset
HOSTCAPBLT2 114h
22.3.27.2 Function
This register provides the host driver with information specific to the eSDHC
implementation. The value in this register is the power-on-reset value, and does not
change with a software reset. Any write to this register is ignored.
22.3.27.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
Reserved
W
Reset u u u u u u u u u u u u u u u u
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
UTSDR50
SDR104
SDR50
DDR50
DTDS
DTCS
TCRT
DTAS
Reserved
Reserved
Reserved
RTM
W
Reset 1 0 1 u 1 1 1 1 u 0 0 0 u 1 1 1
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1079
eSDHC register descriptions
22.3.27.4 Fields
Field Function
0-15 Reserved.
—
16-17 Re-tuning modes. This bit indicates the supported re-tuning modes for UHS.
00b - Mode 1 - Software Timer
RTM
01b - Mode 2 - Software Timer and Re-tuning request
10b - Mode 3 - Software Timer, and Auto Re-tuning during data transfer
11b - Reserved
18 Use tuning for SDR50. This bit indicates whether the host support tuning for SDR50 mode.
0b - Tuning for SDR50 mode not supported
UTSDR50
1b - Tuning for SDR50 mode supported
19 Reserved.
—
20-23 Timer Count for Re-Tuning :
TCRT This field indicates an initial value of Re-Tuning timer for retuning mode 1 to 3.
0000b - Re-Tuning timer disabled
0001b - 1 second
0010b - 2 seconds
0011b - 4 seconds ...
1011b - 1024 seconds
1100-1110b - Reserved
1111b - Get timer information from other source.
24 Reserved.
—
25 Driver type D support. This bit indicates whether the system is capable of using driver type D.
0b - Driver Type D not supported
DTDS
1b - Driver Type D Supported
26 Driver type C support. This bit indicates whether the system is capable of using driver type C.
0b - Driver Type C not supported
DTCS
1b - Driver Type C Supported
27 Driver type A support. This bit indicates whether the system is capable of using driver type A.
0b - Driver Type A not supported
DTAS
1b - Driver Type A Supported
28 Reserved.
—
29 DDR50 support. This bit indicates whether the eSDHC supports the DDR mode.
0b - DDR mode not supported
DDR50
1b - DDR mode supported
30 SDR104 Support. This bit indicates whether the eSDHC supports the SDR104.
0b - SDR104 not supported
SDR104
1b - SDR104 supported
31 SDR50 support. This bit indicates whether the eSDHC supports the SDR50.
0b - SDR50 not supported
SDR50
1b - SDR50 supported
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1080 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
22.3.28 Tuning block control register (TBCTL)
22.3.28.1 Offset
Register Offset
TBCTL 120h
22.3.28.2 Function
This register contains fields for controlling the tuning block.
NOTE
Writing or reading to reserved fields of this register does not
guarantee specific values will be written or read.
22.3.28.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
Reserved
Reserved
Reserved
Reserved
Reserved
Reset u u u u u u u u u u u u u u u u
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
TB_MODE
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
TB_E
W
N
Reset u u u u u u u u u u u u u 0 1 0
22.3.28.4 Fields
Field Function
0 Reserved.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1081
eSDHC register descriptions
Field Function
—
1 Reserved.
—
2 Reserved.
—
3-7 Reserved.
—
8-15 Reserved.
—
16-17 Reserved.
—
18-19 Reserved.
—
20-23 Reserved.
—
24 Reserved.
—
25-26 Reserved.
—
27 Reserved.
—
28 Reserved.
—
29 Tuning block enabled. Tuning block should be enabled for high speed SDR mode more than 50 MHz SD
clock frequency.
TB_EN
This bit is not reset by software reset for all.
0b - Tuning block is disabled
1b - Tuning block is enabled
30-31 Tuning Mode
TB_MODE Tuning Mode. Selects tuning mode when tuning block is enabled. Refer to re-tuning modes in Table
22-10
00b - Mode 1 - Software Timer
01b - Mode 2 - Software Timer, and Re-tuning request
10b - Mode 3 - Software Timer, and Auto Re-tuning during data transfer
11b - SW tuning mode - Software tuning mode where start and end point of data window needs to
be programmed in TBPTR register and use software timer for re-tuning
22.3.29 Tuning block status register (TBSTAT)
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1082 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
22.3.29.1 Offset
Register Offset
TBSTAT 124h
22.3.29.2 Function
This register contains the status of the tuning block.
22.3.29.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
TB_STATUS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
TB_STATUS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
22.3.29.4 Fields
Field Function
0-31 Tuning Status.
TB_STATUS
22.3.30 Tuning block pointer register (TBPTR)
22.3.30.1 Offset
Register Offset
TBPTR 128h
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1083
eSDHC register descriptions
22.3.30.2 Function
This register contains fields for controlling tuning block pointers.
22.3.30.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
TB_WNDW_STRT_PTR
TB_WNDW_END_PTR
Reserved
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
22.3.30.4 Fields
Field Function
0-16 Reserved.
—
17-23 Tuning window start pointer. Selects window start pointer for software tuning mode (when
TBCTL[TB_MODE]=3).
TB_WNDW_ST
RT_PTR
24 Reserved.
—
25-31 Tuning window start pointer. Selects window end pointer for software tuning mode (when
TBCTL[TB_MODE]=3)
TB_WNDW_EN
D_PTR
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1084 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
22.3.31 SD direction control register (SDDIRCTL)
22.3.31.1 Offset
Register Offset
SDDIRCTL 140h
22.3.31.2 Function
This register contains control for CMD and DAT lines direction.
22.3.31.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
Reserved DIR_CTL
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
22.3.31.4 Fields
Field Function
0-28 Reserved.
—
29-31 Direction control
DIR_CTL Specify the turnaround time required for external transceiver after the assertion of direction pins in
number of SD clocks
000b - No turnaround time required
001b - 1 SD clock period for turnaround
010b - 2 SD clock periods for turnaround ...
111b - 7 SD clock periods for turnaround
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1085
eSDHC register descriptions
22.3.32 SD Clock Control Register (SDCLKCTL)
22.3.32.1 Offset
Register Offset
SDCLKCTL 144h
22.3.32.2 Function
This register contains fileds for controlling SD external and loopback clock.
22.3.32.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
LPBK_SD_CLK_DLY_DIR
LPBK_CLK_SEL
LPBK_CLK_DLY
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
CMD_CLK_CTL
Reserved
Reserved
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1086 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
22.3.32.4 Fields
Field Function
0 SD Loopback Clock Select. This field specifies whether SD clock is loopbacked from external pin or from
internal pad.
LPBK_CLK_SE
L 0b - SD card clock is loopbacked from internal pad
1b - SD card clock is loopbacked from external pin
1 SD Loopback Clock Delay Direction. This field specifies whether SD loopback card clock is delayed in
positive or negative direction.
LPBK_SD_CLK
_DLY_DIR 0b - SD card loopback clock is delayed by LPBK_CLK_DLY value
1b - SD card loopback clock is early by LPBK_CLK_DLY value
2-3 Reserved.
—
4-15 SD Loopback Clock Delay. This field specifies the number of periphal clocks (based on
ESDHCCTL[PCS]) by which SD loopback card clock is delayed.
LPBK_CLK_DL
Y 000000000000b - No delay in SD card clock
000000000001b - 1/2 peripheral clocks delay introduced in SD card clock
000000000010b - 2/2 peripheral clocks delay introduced in SD card clock ...
111111111111b - 4095/2 peripheral clocks delay introduced in SD card clock
16 Command Logic Clock Control. This field specifies controls clock to the command logic.
CMD_CLK_CTL 0b - Command logic clock is same as data logic clock
1b - Command logic clock is 25% shifted early from data logic clock
17 Reserved.
—
18-19 Reserved.
—
20-31 Reserved.
—
22.3.33 eSDHC control register (ESDHCCTL)
22.3.33.1 Offset
Register Offset
ESDHCCTL 40Ch
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1087
eSDHC register descriptions
22.3.33.2 Function
This register contains fields for controlling DMA transfers.
22.3.33.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R RTR
Reserved RTOCV PCS FAF CRS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
RD_PRFTCH_BLKCNT
WR_BUF
PAD_DIS
Reserved
Reserved
Reserved
SNOOP
RD_SAF
W
E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
22.3.33.4 Fields
Field Function
0-9 Reserved.
—
10-11 Register timeout count value. This field define the timeout value for register access.
00b - Timeout count value for register access is 2^10 clocks
RTOCV
01b - Timeout count value for register access is 2^11 clocks
10b - Timeout count value for register access is 2^12 clocks
11b - Timeout count value for register access is 2^13 clocks
12 Peripheral clock select. This bit selects the clock used for generating SD clock. This bit is not reset by
software reset for all.
PCS
0b - Platform clock is used
1b - Peripheral/2 clock is used
13 Flush asynchronous FIFO. This bit is used to flush asynchronous FIFO. It can be set by software and will
be auto cleared by hardware.
FAF
0b - No Flush
1b - Flush async FIFO
14 Re-tuning request. This bit indicates re-tuning request status. eSDHC may request host driver to execute
re-tuning sequence, by setting this bit, when the data window is shifted by temperature drift and a tuned
RTR
sampling point does not have a good margin to receive correct data. This bit is cleared when a command
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1088 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
Field Function
is issued with setting execute tuning in the system control 2 register. Changing of this bit from 0 to 1
generates re-tuning event. Refer to interrupt status registers for more detail. This bit isn't set to 1 if tuning
block enable in the tuning control register is set to 0 (using fixed sampling clock). This is read-only field.
0b - No re-tuning request
1b - Re-tuning request is set
15 Clock register select. This bit selects the clock division format of SDCLKFS and DVS fields of system
control register.
CRS
0b - SDCLKFS is defined as 8-bit field, and DVS is active in system control register
1b - SDCLKFS is defined as 10-bit field, CGS is active in system control register
16-18 Reserved.
—
19-23 Read prefetch block count. For DMA read (SD write), this field specifies the maximum number of SD
blocks that the host can prefetch from the system memory. It can have following values:
RD_PRFTCH_B
LKCNT 00000b - No prefetch
00001b - 1 SD block prefetch
00010b - 2 SD block prefetch
11111b - 31 SD block prefetch
24 Pad disable
PAD_DIS Pad disable. Padding disable control for DMA transaction with non-word (4-bytes) aligned block size. For
more details refer to Data buffer and block size.
0b - DMA will pad data at the end each block transfer.
1b - DMA will not pad data at the end of each block transfer.
25 Snoop attribute. Snoop enable for DMA transaction.
SNOOP 0b - DMA transactions are not snooped by the CPU data cache.
1b - DMA transactions are snooped by the CPU data cache.
26-27 Reserved.
—
28 Write bufferable. DMA always initiate write transaction on System bus corresponding to last in every SD
block as non-bufferable. This bit specifies whether all non-last write transactions will be bufferable or not.
WR_BUF
0b - Non-last write transactions are not bufferable.
1b - Non-last write transactions are bufferable.
29 Read safe. This bit should be set only if the target of read dma operation is a well behaved memory which
is not affected by the read operation and will return the same data if read again from the same location.
RD_SAFE
This means that unaligned reading operation can be rounded up to enable more efficient read operations.
0b - It is not safe to read more bytes that were intended.
1b - It is safe to read more bytes that were intended.
30-31 Reserved.
—
22.4 Functional description
The eSDHC block is partitioned in five major sub-blocks as shown in Figure 22-2.
• SD interface and control unit
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1089
Functional description
This block interfaces with the SD bus. It is mainly responsible for controlling the SD
bus operation and transferring data from Data Buffer and SD bus. It also interacts
with System Interface and Control Unit.
• System interface and control unit
This block interfaces with the system interfaces (that is, the system bus in DMA
mode and register bus in CPU polling mode) and transfers the card data from the data
buffer and system.
• Register bank
This block interfaces with register bus and contains all the registers. It controls the
overall operation of eSDHC and also provides status through various registers.
• Clock and reset
This block generates divided clock for SD interface and provides appropriate reset to
all the blocks.
• SD monitor
This block monitors the SD bus and provides status to register banks, such as card
interrupt, write protect and card detect.
22.4.1 System interface and control unit (SysICU)
The SysICU block is further partitioned into three major sub-blocks:
• System control block
This sub-block receives data transfer request from the register bank, controls data
transfer for whole transaction and generates control signals for DMA and buffer
control operation on per block basis.
• Buffer control block
This sub-block handles buffer port register access in CPU polling mode and contains
the buffer FIFO to store transfer data. It controls the data transfer per-block basis in
the CPU polling mode.
• DMA block
This sub-block generates DMA transactions on system bus to transfer the data
between system memory and data buffer.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1090 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
The following sections provide a brief functional description of the major system blocks,
including the data buffer, DMA system interface, register bank as well as IP bus
interface, dual-port memory wrapper, data/command controller, clock and reset manager,
and clock generator.
22.4.1.1 Data buffer
The eSDHC uses one configurable data buffer, so that data can be transferred between
the system/register bus and SD card in an optimized manner to maximize throughput
between the two clock domains. See the figure below for illustration of the buffer
scheme.
The buffer is used as temporary storage for data being transferred between the host
system and the card.
The watermark levels for read and write are both configurable, and can be any number
from 1-128 words for CPU polling mode. The burst lengths for read and write are also
configurable, and can be any number from 1-16 for DMA mode.
Reg Bus
eSDHC Registers
SD Bus
Data Buffer SD Control
& I/F
System Bus
Internal RAM
DMA
Figure 22-3. eSDHC buffer scheme
There are two transfer modes to access the data buffer:
• CPU polling mode
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1091
Functional description
Data is transferred over register bus. For a host read operation, when the number of
words received in the buffer meets or exceeds the RD_WML watermark value, then
by monitoring (polling or interrupt) the BRR bit the host driver can read the buffer
data port register (DATPORT) to fetch the amount of words set in the RD_WML
register from the buffer. For block size integral multiple of watermark level value set
in watermark level register (WML), driver must access buffer data port register
(DATPORT) exactly the same number of times as the watermark level. However, if
the block size is not the times of the watermark level value, the software must access
exactly the remained number of words at the end of each block. For example, for
read operation, if the RD_WML is 4, indicating the watermark level is 16 bytes,
block size is 40 bytes, and the block count is 2, then the access times to Data Buffer
Port Register for the burst sequence in the whole transfer process must be 4, 4, 2(for
first block); 4, 4, 2(for second block). The write operation is similar.
• DMA mode (includes simple and advanced DMA accesses)
Data is transferred over system bus. DMA interrupt is generated after all the data is
transferred to/from the buffer.
22.4.1.1.1 Write operation sequence
There are two ways to write data into the buffer when the user transfers data to the card:
• By processor core polling through IRQSTAT[BWR] (interrupt or polling)
• By using the DMA
When the DMA is not used, (CPU polling mode, that is, the XFERTYP[DMAEN] is not
set when the command is sent), and when the amount of buffer space exceeds the value
set in the WR_WML register, PRSSTAT[BWR] is set. The buffer write ready interrupt is
generated if it is enabled by software.
When DMA is used, the eSDHC will not inform the system before all the required
number of bytes are transferred (if no error was encountered). When an error occurs
during the data transfer, the eSDHC aborts the data transfer and abandons the current
block. If the current data transfer is in multi block mode, the eSDHC does not
automatically send CMD12, even though the XFERTYP[AC12EN] is set. The host driver
needs to send CMD12 in this scenario. It is recommended that a Software Reset for Data
be applied before the transfer is re-started after error recovery.
22.4.1.1.2 Read operation sequence
There are two ways to read data from the buffer when the user transfers data to the card:
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1092 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
• By processor core polling through IRQSTAT[BRR] (interrupt or polling)
• By using the DMA
When DMA is not used (CPU polling mode, that is, the XFERTYP[DMAEN] is not set
when the command is sent), and when the amount of data exceeds the value set in the
RD_WML register, that is available and ready for system fetching data, PRSSTAT[BRR]
is set. The buffer read ready interrupt will be generated if it is enabled by software.
When DMA is used, the eSDHC will not inform the system before all the required
number of bytes are transferred (if no error was encountered). When an error occurs
during the data transfer, the eSDHC will abort the data transfer and abandon the current
block. If the current data transfer is in multi block mode, the eSDHC will not
automatically send CMD12, even though the XFERTYP[AC12EN] is set. The host driver
should send CMD12 in this scenario. It is recommended that a software reset for data be
applied before the transfer is re-started after error recovery.
22.4.1.1.3 Data buffer and block size
In eSDHC, the data buffer can hold up to 128 words (32-bit).
The watermark levels for both write and read can be configured for CPU polling mode.
The watermark level can be from one word to a maximum of 128 words. For both DMA
read and write, the burst length can be configured from one to a maximum of 16. The
host driver may configure watermark level and burst length value according to the system
situation and requirement in the watermark level register (WML).
During a multi-block data transfer, the block length may be set to any value between 1
and 2048 bytes inclusive that satisfies the requirements of the external card. The only
restriction to it can be from the external card, which may not support that large a block or
partial access to block (which is not an integer times of 512 bytes).
For CPU polling mode, when block size not a multiple of four; that is, not word aligned,
eSDHC requires stuff bytes at the end of each block, as defined in the host specification.
For example, if the block size is 5 bytes and there are two blocks to write, there must be
two register bus writes to buffer data port register (DATPORT) for each block; and for
each block, the ending non-word aligned bytes should be stuffed in buffer data port
register (DATPORT) write to make it word aligned. For this example, 3 bytes should be
stuffed. eSDHC will transfer only the required number of bytes to the card and ignore the
stuff bytes as shown in the figure below. Read operation is similar.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1093
Functional description
Card memory
Sequential buffer data port reg access 3
1 2 3 1
4 4
5 X X X 5
eSDHC
1 2 3 4 1
5 X X X 2
4
First block data
Second block data 55
Figure 22-4. Byte stuffing for CPU polling mode
For DMA mode, when block size not a multiple of four; that is, not word aligned,
eSDHC requires stuff bytes depending on the PAD_DIS field programmed in DMA
Control register. The data transfer with byte stuffing enabled (when
DMACTL[PAD_DIS]=0) is shown in Figure 22-5. And, data transfer with byte stuffing
disabled (when DMACTL[PAD_DIS]=1) is shown in Figure 22-6. Transfer with byte
stuffing disabled eliminates the software overhead of byte stuffing. Driver may program
DMA Control register accordingly.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1094 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
Card memory
System memory 3
1 2 3 1
4 4
5 X X X 5
eSDHC
1 2 3 4 1
5 X X X 2
4
First block data
Second block data 55
Figure 22-5. Byte stuffing for DMA mode when DMACTL[PAD_DIS]=0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1095
Functional description
Card Memory
System Memory
1 4
1 2 3 4
5
5 1 2 3 eSDHC_AXI
1
4 5 - -
2
4
First Block Data
Second Block Data 55
Figure 22-6. No byte stuffing for DMA mode when DMACTL[PAD_DIS]=1
22.4.1.1.4 Dividing large data transfer
This SDIO command CMD53 definition, limits the maximum data size of data transfers
according to the following formula:
Max data size = Block size x Block count
The length of a multiple block transfer needs to be in block size units. If the total data
length cannot be divided evenly into a multiple of the block size, then based on the
function and the card design, there are two ways to transfer the data. First option is for
the host driver to split the transaction. The remainder of the block size data is then
transferred by using a single block command at the end. Second option is to add dummy
data in the last block to fill the block size provided the card manages the removal of the
dummy data.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1096 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
Figure below shows an example which explains the dividing of large data transfers. In
this figure, assume a kind of WLAN SDIO card that only supports block size up to 64
bytes. Although the eSDHC supports a block size of up to 2048 bytes, the SDIO can only
accept a block size less than 64 bytes. Thus, the data must be divided (see example
below).
544-bytes WLAN Frame
802.11
IV Frame Body ICV FCS
MAC Header
WLAN Frame is divided equally into 64-byte blocks plus the remainder 32-bytes
Data Data Data Data
64-bytes 64-bytes 64-bytes 32-bytes
SDIO Data SDIO Data SDIO Data SDIO Data
Block 1 Block 2 Block 8 32-bytes
Eight 64-byte blocks are sent in Block Transfer Mode and the remainder
32-bytes are sent in Byte Transfer Mode
SDIO Data SDIO Data SDIO Data SDIO Data
CMD53 CMD53
Block 1 Block 2 Block 8 32-bytes
Figure 22-7. Example for dividing large data transfers
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1097
Functional description
22.4.1.1.5 Byte order (endianness) of buffer data port register
For CPU polling mode, sequential and contiguous access is necessary to ensure the
pointer address value is correct. Random or skipped access is not possible.
The byte order of buffer data port register (DATPORT), by reset is little endian mode.
The data buffer is always little endian. The data is swapped inside the buffer, according
to the endian mode configured by software in PROCTL[EMODE].
In little endian mode, the data is transferred between data buffer and buffer data port
register (DATPORT) without any swapping. In big endian mode, the data between data
buffer and buffer data port register (DATPORT) is byte-swapped as shown in the figure
given below. For an SD write operation, byte order is swapped after data is fetched from
the buffer port register and sent to data buffer. For a host read operation, byte order is
swapped after the data is read from data buffer and sent to buffer port register.
Buffer Port Register 7-0 15-8 23-16 31-24
Data Buffer 31-24 23-16 15-8 7-0
Figure 22-8. Data swap between buffer data port register and data buffer in big endian
mode
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1098 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
22.4.1.2 DMA system interface
The DMA implements a DMA engine and the system master.
The eSDHC supports both SDMA and ADMA (ADMA1 and ADMA2). Figure below
illustrates the DMA system interface block.
System Address
System
eSDHC Registers
Interface
R/W Indication
Master
Logic
System Bus
Data Exchange
Data Buffer
SDMA/
ADMA
Engine
Figure 22-9. DMA system interface block
22.4.1.2.1 DMA burst length
The actual burst length on system bus depends on the shortest of following factors:
• Burst length configured in the burst length field of the watermark level register
(WML)
• Block size boundary
• Data boundary configured in the current descriptor (if the ADMA is active)
22.4.1.2.2 System master interface
The System DMA engine can at times fail during data transfer.
When this error occurs:
• The DMA engine stops the transfer and goes to the error state.
• The internal data buffer stops accepting incoming data.
• The IRQSTAT[DMAE] is set to inform the driver.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1099
Functional description
Once the DMAE interrupt is received, the software sends a CMD12 to abort the current
transfer and read the DMAERRADDR[DMA_ADDR] bits to get the starting address of
the corrupted block. For error recovery, the software issues a data reset and re-starts the
transfer from this address to recover the corrupted block.
22.4.1.3 Single DMA (SDMA)
SDMA is single operation DMA, that is, data is transferred for single operation only
(unlike ADMA which has chained descriptor table) from the starting address
programmed in SDMA system address register (DSADDR) for entire data transfer size
(block count x block size) as programmed in the block attributes register (BLKATTR) if
XFERTYP[BCEN] is set.
22.4.1.3.1 SDMA error
SDMA will stop whenever an error is encountered on the system bus.
DMA error address register latches the transaction address on which the error occured.
22.4.1.4 Advanced DMA (ADMA)
Advanced DMA (ADMA) is a new DMA transfer algorithm, which is defined in the SD
Host Controller Standard.
For single DMA, the data can be transferred for single operation only. The ADMA
defines the programmable descriptor table in the system memory. The host driver can
calculate the system address at the page boundary and program the descriptor table before
executing ADMA. Higher speed DMA transfers are realized because the host MCU
intervention is not needed during long DMA based data transfers.
The host controller has two types of ADMA: ADMA1 and ADMA2. ADMA1 can
support data transfer of 4KB aligned data in system memory. ADMA2 improves the
restriction so that data of any location and any size can be transferred in system memory.
Their formats of descriptor table are different.
ADMA can recognize all kinds of descriptors defined in SD Host Controller Standard
and if 'End' flag is detected in the descriptor, ADMA stops after this descriptor is
processed.
eSDHC supports ADMA1 and ADMA2 with 32-bit addressing.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1100 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
22.4.1.4.1 ADMA concept and descriptor format
ADMA1 includes the following descriptors:
• Valid/invalid descriptor
• Nop descriptor
• Set data length and address descriptor
• Link descriptor
• Interrupt flag and End flag in descriptor
ADMA2 includes the following descriptors:
• Valid/Invalid descriptor
• Nop descriptor
• Rsv descriptor
• Set data length and address descriptor
• Link descriptor
• Interrupt flag and End flag in descriptor
Figure 22-10 explains the ADMA1 descriptor table format.
Figure 22-12 explains the ADMA2 descriptor table format. ADMA2 deals with the lower
32-bit first, and then the higher 32-bit. If the 'Valid' flag of descriptor is 0, it will ignore
the high 32-bit. Address field should be set on word aligned (lower 2-bit is always set to
0). Data length is in byte unit.
ADMA starts read/write operation after it reaches the Tran state, using the data length
and data address analyzed from most recent descriptor(s).
For ADMA1, the valid data length descriptor is the last set type descriptor before Tran
type descriptor. Every Tran type triggers a transfer, and the transfer data length is
extracted from the most recent Set type descriptor. If there is no set type descriptor after
the previous Trans descriptor, the data length is the value for previous transfer, or 4
Kbyte if no set descriptor is ever met.
For ADMA2, Tran type descriptor contains both data length and transfer data address.
Thus, only a Tran type descriptor can start a data transfer.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1101
Functional description
Address/Page Field Address/Page Field Attribute Field
31 12 11 6 5 4 3 2 1 0
Addressor Data Length 000000 Act2 Act1 0 Int End Valid
Act2 Act1 Symbol Comment 31-28 27-12
0 0 NOP No Operation Do not care
0 1 Set Set Data Length 0000 Data Length
1 0 Tran Transfer Data Data Address
1 1 Link Link Descriptor Descriptor Address
Valid Valid=1 indicates this line of descriptor is effective. If Valid=0, generate ADMA error interrupt and stop ADMA.
End End=1 indicates current descriptor is the ending descriptor.
Int Int=1 generates DMA Interrupt when this descriptor is processed.
Figure 22-10. Format of the 32-bit address ADMA1 descriptor table
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1102 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
System Memory
Descriptor Table
ADMA Sys Addr Register points to
the head node of Descriptor Table
Address/Length Attribute
Advanced DMA
Address Tran
ADMA Sys Addr Register
Address Link
Data Length (invisible)
Address/Length Attribute
Data Address (invisible)
Data Length Set
Address Tran, End
DMA Interrupt
Flags
Flags
SDMA Transfer Complete Page Data
SDMA
State
Machine
Block Gap Event
Page Data
Figure 22-11. Concept and access method of ADMA1 descriptor table
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1103
Functional description
Address Field Length
Length Reserved Attribute Field
63 32 31 16 15 6 5 4 3 2 1 0
32-bit Address 16-bit Length 0000000000 Act2 Act1 0 Int End Valid
Act2 Act1 Symbol Comment Operation
0 0 NOP No Operation Do not care
Same as NOP. Read this
0 1 Rsv Reserved line and go to next one
Transfer data with address and length
1 0 Tran Transfer Data set in this descriptor line
1 1 Link Link Descriptor Link to another descriptor
Valid Valid=1 indicates this line of descriptor is effective. If Valid=0, generate ADMA error interrupt and stop ADMA.
End End=1 indicates current descriptor is the ending descriptor.
Int Int=1 generates DMA Interrupt when this descriptor is processed.
Figure 22-12. Format of the 32-bit address ADMA2 descriptor table
ADMA Sys Addr Register points to
the head node of Descriptor Table System Memory
Descriptor Table
Advanced DMA
Address Length Attribute
ADMA Sys Addr Register
Address1 Length1 Tran
Address2 Length2 Link
Data Length (invisible)
Data Address (invisible)
Address Attribute
Address3 Tran, End
DMA Interrupt
Flags
Flags
SDMA Transfer Complete Page Data
State SDMA
Machine
ADMA Error
Page Data
Figure 22-13. Concept and access method of ADMA2 descriptor table
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1104 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
22.4.1.4.2 ADMA interrupt
If the 'interrupt' flag of descriptor is set, ADMA will generate an interrupt,
IRQSTAT[DINT] whenever the data transfer for the particular descriptor line is
completed.
22.4.1.4.3 ADMA error
The ADMA stops whenever any of the following error is encountered:
• Fetching descriptor error
• System response error
• Data length mismatch error
ADMA descriptor error is generated when it fails to detect 'Valid' flag in the descriptor. If
ADMA descriptor error occurs, the interrupt is not generated even if the 'Interrupt' flag of
this descriptor is set.
When the BLKCNTEN bit is set, the data transfer length set in buffer must be equal to
the whole data transfer length set in the descriptor nodes, otherwise data length mismatch
error is generated.
If the BLKCNTEN bit is not set, the whole data transfer length set in descriptor should be
times of block length, otherwise, when all data set in the descriptor nodes are done, the
data length mismatch error will occur.
The DMA error address register (DMAERRADDR) latches the transaction address on
which the error occured. The ADMA system address register (ADSADDR) latches the
current descriptor line address which encountered the error.
22.4.2 SD interface and control unit (SDICU)
This block is partitioned into six major sub-blocks as shown in Figure 22-2.
• Transfer control block: This sub-block receives command request from the register
bank and overall controls other SDICU sub-blocks for SD bus operation on
transaction level.
• SD command block: This sub-block controls the SD CMD line for sending command
out. It receives the command request from Transfer Control block and sends it on SD
CMD line.
• SD response block: This sub-block monitors the SD CMD line for receiving response
and detecting line errors. It sends the command and response status to transfer
control for transaction operation.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1105
Functional description
• SD data out block: This sub-block controls the SD DAT lines for sending out the
block write data from the SD data out FIFO.
• SD data in block: This sub-block monitors the SD DAT line for detecting read and
write data block end and busy period end for transfer control module. It also detects
data line error and card interrupt.
• Tuning block: This sub-block receives Tuning block data from card and tunes IP. It
then forwards the sampled data to Async FIFO for further operation.
22.4.2.1 Command CRC
See the figure below for an illustration of the structure for the command CRC shift
register.
CLR_CRC
ZERO
CRC CRC CRC CRC CRC CRC CRC
CRC_IN BUS BUS BUS BUS BUS BUS BUS
[0] [1] [2] [3] [4] [5] [6]
CRC_OUT
Figure 22-14. Command CRC shift register
The CRC polynomials for the CMD are as follows:
Generator polynomial: G(x) = x7 + x3 + 1
M(x) = (first bit) * xn + (second bit) * xn-1 +...+ (last bit) * x0
CRC[6:0] = Remainder [(M(x) * x7) / G(x)]
22.4.2.2 Data CRC
The CRC polynomials for the DAT are as follows:
Generator polynomial: G(x) = x16 + x12 + x5 +1 M(x)
= (first bit) * xn + (second bit) * xn-1 +...+ (last bit) * x0
CRC[15:0] = Remainder [(M(x) * x16) / G(x)]
22.4.2.3 Tuning block (SDICU)
Tuning block is used for SD UHS SDR50, SDR104 and MMC HS200 modes.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1106 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
Tuning block tunes the IP on tuning command (CMD19 for SD, CMD21 for MMC) data
sent by card and the sampled data is sent to async FIFO for further operation.
This block oversamples data from card and selects particular sampling point after
completion of tuning procedure, refer to Tuning block procedure for tuning block usage.
Various re-tuning modes are supported by eSDHC as described below.
Table 22-10. Re-tuning modes
Re-Tuning Mode Re-Tuning Method Data Length
1 Software timer 4MB (Max.)
2 Software timer, and re-tuning request 4MB (Max.)
3 Software timer, and auto re-tuning Any
during data transfer
There are two re-tuning timings: Re-tuning request controlled by eSDHC and expiration
of a re-tuning timer(software timer) controlled by the host driver. By receiving either
timing, the host driver executes the re-tuning procedure just before a next command
issue.
The maximum data length per read/write command is restricted so that re-tuning
procedures can be inserted during data transfers.
Re-tuning mode 1
eSDHC do not generate re-tuning request. In this case, the host driver should maintain all
re-tuning timings by using a re-tuning timer. To enable inserting the re-tuning procedure
during data transfers, the data length per read/write command shall be limited up to 4
MB.
Re-tuning mode 2
eSDHC indicates the re-tuning timing by re-tuning request during data transfers. Then the
data length per read/write command shall be limited up to 4 MB. During non data
transfer, re-tuning timing is determined by re-tuning timer.
Re-tuning mode 3
eSDHC takes care of the re-tuning during data transfer (auto re-tuning). Re-tuning
request will not be generated and there is no limitation to data length per read/write
command. During non data transfer, re-tuning timing is determined by re-tuning timer.
Re-tuning timer control example for re-tuning mode 1
The software timer starts counting by loading the initial value. When the timer expires,
the host driver marks an expiration flag. On receiving a command request, the host driver
checks the expiration flag. If the expiration flag is set, then the host driver should perform
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1107
Functional description
the re-tuning procedure before issuing a command. If the expiration flag is not set, then
the host driver issues a command without performing the re-tuning procedure. Every time
the re-tuning procedure is performed, the timer loads the new initial value and the
expiration flag is cleared.
Re-tuning timer control example for re-tuning mode 2 and mode 3
The software timer control is almost the same as re-tuning mode 1 except the timer loads
the new initial value after data transfer (when receiving transfer complete). in case of
mode 3, timer count for re-tuning is set either smaller value: tuning effective time after
re-tuning procedure or after data transfer.
If a host system goes into power down mode, the host driver should stop the re-tuning
timer and set the expiration flag to 1 when the host system resumes from power down
mode.
22.4.3 Register bank
This block interfaces with register bus and it contains all the registers. It controls the
overall operation of eSDHC and also provides status through various registers.
Register accesses is actually on the register bank. See the figure below for the block
diagram.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1108 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
Register Bank
Control Signals
to other Modules
Status Signals
Software
from other Modules
Visible
Registers
Write 1 Clear
Function
Array
Register
Bus
Signals
Buffer
Data Port
Control
Figure 22-15. Register bank diagram
Partial access is not allowed on any register; that is, it should be 32-bit access only.
22.4.4 Clock and reset module
Clock and reset module generates divided clock for SD interface and provides
appropriate reset to other modules.
There are four kinds of reset signals within eSDHC:
• Hardware reset
• Software reset for all
• Software reset for the data part
• Software reset for the command part
All these signals are fed into this module and stable signals are generated inside the
module to reset all other modules.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1109
Functional description
If the internal data buffer is in danger, and the SD clock must be gated off to avoid buffer
over/under-run, this module asserts the gate of the output SD clock to shut the clock off.
After the buffer danger has recovered, and when the system access of the buffer catches
up, the clock gate of this module opens and the SD clock becomes active again.
22.4.4.1 Clock generator
The clock generator generates the SDHC_CLK by source clock in two stages.
The figure below illustrates the structure of the divider. The term "Base" represents the
frequency of the source clock.
1st Divisor 2nd Divisor
Base by DIV by SDHC_CLK
1, 2, 3, ..., 16 1, 2, 4, ..., 256
Figure 22-16. Two stages of the clock divider
The first stage outputs an intermediate clock (DIV), which can be Base, Base/2, Base/
3, ..., or Base/16.
The second stage is a prescaler, and outputs the actual clock (SDHC_CLK). This clock is
the driving clock for sub modules SD Command and SD Data Out in SD Interface and
Control Unit (refer to Figure 22-2) to synchronize with the data rate from the internal
data buffer. The frequency of the clock output from this stage, can be DIV, DIV/2, DIV/
4,..., or DIV/256. Thus, the highest frequency of the SDHC_CLK is Base, and the next
highest is Base/2, while the lowest frequency is Base/4096.
The figure below illustrates the sequence for changing the SD clock frequency.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1110 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
Clear SYSCTL[SDCLKEN]
Program SD clock divisors
PRSSTAT[SDSTB]=1 SD clock not stable
SD clock stable
Set SYSCTL[SDCLKEN]
Figure 22-17. SD clock frequency change sequence
Base clock can be selected by programming ESDHCCTL[PCS]. It selects between
platform clock and peripheral clock / 2. Base clock is divided by two of peripheral clocks
when PCS=1.
1. Clear SYSCTL[SDCLKEN]
2. Wait for PRSSTAT[SDSTB] to be set
3. Program appropriate value of ESDHCCTL[PCS]
4. Set SYSCTL[SDCLKEN]
5. Wait for PRSSTAT[SDSTB] to be set
22.4.5 SD monitor
The module detects the CD_B (card detection) as well as the DAT3 signal. The
transceiver reports the card insertion state according to the CD_B state, the signal level
on the DAT3 signal.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1111
Functional description
NOTE
Do not use DAT3 pin as a CD pin.
The module detects the WP (write protect) signal. With the information of the WP state,
the register bank ignores the command, accompanied by a write operation, when the WP
switch is on.
22.4.5.1 SDIO card interrupt
22.4.5.1.1 Interrupts in 1-bit mode
In this case the DAT[1] pin is dedicated to providing the interrupt function.
An interrupt is asserted by pulling the DAT[1] low from the SDIO card, until the
interrupt service is finished to clear the interrupt.
22.4.5.1.2 Interrupt in 4-bit mode
Since the interrupt and DAT[1] share pin 8 in 4-bit mode, an interrupt is sent by the card
and recognized by the host only during a specific time.
This is known as the interrupt period. eSDHC only samples the level on pin 8 during the
interrupt period. At all other times, the host ignores the level on pin 8, and treats it as the
data signal. The definition of the interrupt period is different for operations with single
block and multiple block data transfers.
In the case of normal single data block transmissions, the interrupt period becomes active
two clock cycles after the completion of a data packet. This interrupt period lasts until
after the card receives the end bit of the next command that has a data block transfer
associated with it.
For multiple block data transfers in 4-bit mode, there is only a limited period of time that
the Interrupt Period can be active due to the limited period of data line availability
between the multiple blocks of data. This requires a more strict definition of the Interrupt
Period. For this case, the interrupt period is limited to two clock cycles. This begins two
clocks after the end bit of the previous data block. During this 2-clock cycle interrupt
period, if an interrupt is pending, the DAT[1] line is held low for one clock cycle with the
last clock cycle pulling DAT[1] high. On completion of the interrupt period, the card
releases the DAT[1] line into the high Z state. eSDHC samples DAT[1] during the
interrupt period when the PROCTL[IABG] is set.
Refer to SDIO card specification v2.0 for further information about the SDIO card
interrupt.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1112 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
22.4.5.1.3 Card interrupt handling
When the CINTIEN bit in the interrupt signal enable register is set to 0, the eSDHC
clears the interrupt request to the host system.
The host driver should clear this bit before servicing the SDIO interrupt and should set
this bit again after all interrupt requests from the card are cleared to prevent inadvertent
interrupts.
In 1-bit mode, eSDHC detects the SDIO interrupt with or without the SD clock (to
support wakeup). In 4-bit mode, the interrupt signal is sampled during the interrupt
period, so there are some sample delays between the interrupt signal from the SDIO card
and the interrupt to the host system interrupt controller. When the SDIO status is set, and
the host driver needs to service this interrupt, so the SDIO bit in the interrupt control
register of SDIO card is cleared. This is required to clear the SDIO interrupt status
latched in the eSDHC and to stop driving the interrupt signal to the system interrupt
controller. The host driver must issue a CMD52 to clear the card interrupt. After
completion of the card interrupt service, the SDIO interrupt enable bit is set to 1, and the
eSDHC starts sampling the interrupt signal again.
The figure below illustrates the SDIO card interrupt scheme and sequences of software
and hardware events that take place during a card interrupt handling procedure.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1113
Functional description
IP Bus IRQ to CPU
Start
Enable Card IRQ in Host
eSDHC Registers
SDIO IRQ Status Command/
Response Detect & Steer Card IRQ
Handling
SDIO IRQ Enable
Read IRQ Status Register
Disable Card IRQ in Host
IRQ Detecting & Steering
Interrogate & Service Card IRQ
SD Host
SDIO Card
Yes
Response Error
Clear Clear
?
IRQ0 IRQ1
SDIO Card No
IRQ Routing
Clear Card IRQ in Card
IRQ0 IRQ1
Enable Card IRQ in Host
Function 0 Function 1
End
a) b)
Figure 22-18. Card interrupt scheme and card interrupt detection and handling
procedure
22.4.5.2 Card insertion and removal detection
When the DAT[3] pin is not used for card detection (for example, it is implemented in
GPIO), the CD pin must be connected for card detection. Whether DAT[3] is configured
for card detection or not, the CD pin is always a reference for card detection. Whether the
DAT[3] pin or the CD pin is used to detect card insertion, the eSDHC sends an interrupt
(if enabled) to inform the host system that a card is inserted.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1114 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
22.4.5.3 Power management and wake up events
If no operation is expected to happen between eSDHC and the card through the SD bus,
the user can completely disable the IP in the chip-level clock control module to save
power.
When the user needs to use the eSDHC to communicate with the card, it can enable the
clock and start the operation.
In some circumstances, when the clocks to the eSDHC are disabled, for instance, when
the system is in low power mode, there are some events for which the user needs to
enable the clock and handle the event. These events are called wakeup interrupts. The
eSDHC can generate these interrupt even when there are no clocks enabled. The three
interrupts which can be used as wake up events are:
• Card removal interrupt
• Card insertion interrupt
• Interrupt from SDIO card
The eSDHC offers a power management feature. By clearing the clock enabled bits in the
system control register (SYSCTL), the clocks are gated in the low position to the eSDHC.
For maximum power saving, the user can disable all the clocks to the eSDHC when there
is no operation in progress.
These three wake up events (or wakeup interrupts) can also be used to wake up the
system from low-power modes.
NOTE
To make the interrupt a wakeup event, when all the clocks to
the eSDHC are disabled or when the whole system is in low
power mode, the corresponding wakeup enabled bit needs to be
set. Refer to Protocol control register (PROCTL) for more
information.
22.4.5.3.1 Setting wake up events
For eSDHC to respond to a wakeup event, the software must set the respective wakeup
enable bit before the CPU enters sleep mode.
Before the software disables the host clock, it should ensure that all of the following
conditions are met:
• No read or write transfer is active
• Data and command lines are not active
• No interrupts are pending
• Internal data buffer is empty
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1115
Initialization/application of eSDHC
22.5 Initialization/application of eSDHC
All communication between the system and the cards are controlled by the host.
The host sends commands of two types: Broadcast and Addressed (point-to-point).
Broadcast commands are intended for all cards, such as "GO_IDLE_STATE",
"SEND_OP_COND", "ALL_SEND_CID" and so on. In Broadcast mode, all cards are in
the open-drain mode to avoid bus contention. Refer to Commands for MMC/SD/SDIO
and for the commands of bc and bcr categories.
After the Broadcast command CMD3 is issued, the cards enter standby mode. Addressed
type commands are used from this point. In this mode, the CMD/DAT I/O pads will turn
to push-pull mode, to have the driving capability for maximum frequency operation.
Refer to Commands for MMC/SD/SDIO and , for the commands of ac and adtc
categories.
22.5.1 Command send and response receive basic operation
Assuming the data type WORD is an unsigned 32-bit integer, the below flow is a
guideline for sending a command to the card(s):
send_command(cmd_index, cmd_arg, other requirements)
{
WORD wCmd; // 32-bit integer to make up the data to write into transfer type register
(XFERTYP),
it is recommended to implement in a bit-field manner
wCmd = (<cmd_index> & 0x3f) >> 24; // set the first 8 bits as '00'+<cmd_index>
set CMDTYP, DPSEL, CICEN, CCCEN, RSTTYP, DTDSEL accorind to the command index;
if (DMA is used) wCmd |= 0x1;
if (multi-block transfer) {
set MSBSEL bit;
if (finite block number) {
set BCEN bit;
if (auto12 command is to use) set AC12EN bit;
}
}
write_reg(CMDARG, <cmd_arg>); // configure the command argument
write_reg(XFERTYP, wCmd); // set transfer type register (XFERTYP) as wCmd value to issue the
command
}
wait_for_response(cmd_index)
{
while (CC bit in IRQ Status register is not set); // wait until Command Complete bit is set
read IRQ Status register and check if any error bits about Command are set
if (any error bits are set) report error;
write 1 to clear CC bit and all Command Error bits;
}
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1116 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
For the sake of simplicity, the function wait_for_response is implemented here using
polling. For an effective and formal way, the response is usually checked after the
Command Complete Interrupt is received. By doing this, make sure the corresponding
interrupt status bits are enabled.
For some scenarios, the response time-out is expected. For instance, after all cards
respond to CMD3 and go to the Standby State, no response to the Host when CMD2 is
sent. The host driver should deal with 'fake' errors like this with caution.
22.5.2 Card identification mode
When a card is inserted to the socket or the card was reset by the host, the host needs to
validate the operation voltage range, identify the cards, request the cards to publish the
relative card address (RCA) or set the RCA for the MMC cards. All data communications
in the card identification mode use the command line (CMD) only.
22.5.2.1 Card detect
The figure below illustrates a flow diagram showing the detection of MMC, SDIO, and
SD cards using the eSDHC.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1117
Initialization/application of eSDHC
Enable card detection IRQ
Wait for IRQSTAT[CINS]
Card not present
Check PRSSTAT[CINS]
Card present
Voltage validation
Figure 22-19. Flow diagram for card detection
The card detect sequence is as follows:
1. Set the IRQSTAT[CINSIEN] bit and IRQSIGEN[CINSIEN] bit to enable card
detection interrupt.
2. When an interrupt from the eSDHC is received in IRQSTAT[CINS], check
PRSSTAT[CINS] to confirm if it was caused by card insertion.
22.5.2.2 Reset
The host consists of three types of resets:
• Hardware reset (card and host) which is driven by POR (power on reset).
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1118 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
• Software reset (Host Only) is proceed by the write operation on SYSCTL[RSTD],
SYSCTL[RSTC], or SYSCTL[RSTA] bits to reset the data part, command part, or
all parts of the host controller, respectively.
• Card reset (card only). The command, "Go_Idle_State" (CMD0), is the software reset
command for all types of MMC cards and SD memory cards. This command sets
each card into the idle state regardless of the current card state. For an SD I/O Card,
CMD52 is used to write an I/O reset in the CCCR. The cards are initialized with a
default relative card address (RCA=0x0000) and with a default driver stage register
setting (lowest speed, highest driving current capability).
After the card is reset, the host needs to validate the voltage range of the card. Figure
below illustrates the software flow to reset both the eSDHC and the card.
Write '1' to RSTA Bit to Reset eSDHC
Send 80 Clocks to Card
Send CMD0/ CMD52 to Card to Reset Card
Voltage Validation
Figure 22-20. Flow chart for reset of the eSDHC and SD I/O card
software_reset()
{
set_bit(SYSCTRL, RSTA); // software reset the Host
set DTOCV and SDCLKFS bit fields to get the SDHC_CLK of frequency around 400 KHz
configure IO pad to set the power voltage of external card to around 3.0V
poll bits CIHB and CDIHB bits of PRSSTAT to wait both bits are cleared
set_bit(SYSCTRL, INTIA); // send 80 clock ticks for card to power up
send_command(CMD_GO_IDLE_STATE, <other parameters>); // reset the card with CMD0
or send_command(CMD_IO_RW_DIRECT, <other parameters>);
}
22.5.2.3 Voltage validation
All cards should be able to establish communication with the host using any operation
voltage in the maximum allowed voltage range specified in the card specification.
However, the supported minimum and maximum values for Vdd are defined in the
operation conditions register (OCR) and may not cover the whole range. Cards that store
the CID and CSD data in the preload memory are only able to communicate this
information under data transfer Vdd conditions. This means, if the host and card have
non-common Vdd ranges, the card will not be able to complete the identification cycle,
nor will it be able to send CSD data.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1119
Initialization/application of eSDHC
Therefore, a special command Send_Op_Cont (CMD1 for MMC), SD_Send_Op_Cont
(ACMD41 for SD Memory) and IO_Send_Op_Cont (CMD5 for SD I/O) is used. The
voltage validation procedure is designed to provide a mechanism to identify and reject
cards which do not match the Vdd range(s) desired by the host. This is accomplished by
the host sending the desired Vdd voltage window as the operand of this command. Cards
that cannot perform the data transfer in the specified range must discard themselves from
further bus operations and go into the Inactive State. By omitting the voltage range in the
command, the host can query each card and determine the common voltage range before
sending out-of-range cards into the inactive state. This query should be used if the host is
able to select a common voltage range or if a notification should be sent to the system
when a non-usable card in the stack is detected.
The following steps show how to perform voltage validation when a card is inserted:
voltage_validation(voltage_range_arguement)
{
label the card as UNKNOWN;
send_command(IO_SEND_OP_COND, 0x0, <other parameters are omitted>); // CMD5, check SDIO
operation voltage, command argument is zero
if (RESP_TIMEOUT != wait_for_response(IO_SEND_OP_COND)) { // SDIO command is accepted
if (0 < number of IO functions) {
label the card as SDIO;
IORDY = 0;
while (!(IORDY in IO OCR response)) { // set voltage range for each IO
function
send_command(IO_SEND_OP_COND, <voltage range>, <other
parameter>);
wait_for_response(IO_SEND_OP_COND);
} // end of while ...
} // end of if (0 < ...
if (memory part is present inside SDIO card) Label the card as SDCombo; // this is
an
SD-Combo card
} // end of if (RESP_TIMEOUT ...
if (the card is labelled as SDIO card) return; // card type is identified and voltage range
is
set, so exit the function;
send_command(APP_CMD, 0x0, <other parameters are omitted>); // CMD55, Application specific
CMD
prefix
if (no error calling wait_for_response(APP_CMD, <...>) { // CMD55 is accepted
send_command(SD_APP_OP_COND, <voltage range>, <...>); // ACMD41, to set voltage
range
for memory part or SD card
wait_for_response(SD_APP_OP_COND); // voltage range is set
if (card type is UNKNOWN) label the card as SD;
return; //
} // end of if (no error ...
else if (errors other than time-out occur) { // command/response pair is corrupted
deal with it by program specific manner;
} // of else if (response time-out
else { // CMD55 is refuse, it must be MMC card
if (card is already labelled as SDCombo) { // change label
re-label the card as SDIO;
ignore the error or report it;
return; // card is identified as SDIO card
} // of if (card is ...
send_command(SEND_OP_COND, <voltage range>, <...>);
if (RESP_TIMEOUT == wait_for_response(SEND_OP_COND)) { // CMD1 is not accepted,
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1120 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
either
label the card as UNKNOWN;
return;
} // of if (RESP_TIMEOUT ...
else label the card as MMC;
} // of else
}
22.5.2.4 Card registry
Card registry for the MMC and SD/SDIO/SD combo cards are different.
For the SD card, the identification process starts at a clock rate lower than 400 KHz and
the power voltage higher than 2.7 V (as defined by the card specification). At this time,
the CMD line output drives are push-pull drivers instead of open-drain. After the bus is
activated, the host will request the card to send their valid operation conditions. The
response to ACMD41 is the operation condition register of the card. The same command
should be send to all of the new cards in the system. Incompatible cards are put into the
inactive state. The host then issues the command, All_Send_CID (CMD2), to each card
to get its unique card identification (CID) number. Cards that are currently unidentified
(in the ready state), send their CID number as the response. After the CID is sent by the
card, the card goes into the identification state.
The host then issues Send_Relative_Addr (CMD3), requesting the card to publish a new
relative card address (RCA) that is shorter than the CID. This RCA will be used to
address the card for future data transfer operations. Once the RCA is received, the card
changes its state to the standby state. At this point, if the host wants the card to have an
alternative RCA number, it may ask the card to publish a new number by sending another
Send_Relative_Addr command to the card. The last published RCA is the actual RCA of
the card.
The host repeats the identification process with CMD2 and CMD3 for each card in the
system until the last CMD2 gets no response from any of the cards in system.
For MMC operation, the host starts the card identification process in open-drain mode
with the identification clock rate lower than 400 KHz and the power voltage higher than
2.7 V. The open drain driver stages on the CMD line allow parallel card operation during
card identification. After the bus is activated the host will request the cards to send their
valid operation conditions (CMD1). The response to CMD1 is the "wired OR" operation
on the condition restrictions of all cards in the system. Incompatible cards are sent into
the Inactive State. The host then issues the broadcast command All_Send_CID (CMD2),
asking all cards for their unique card identification (CID) number. All unidentified cards
(the cards in Ready State) simultaneously start sending their CID numbers serially, while
bit-wise monitoring their outgoing bit stream. Those cards, whose outgoing CID bits do
not match the corresponding bits on the command line in any one of the bit periods, stop
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1121
Initialization/application of eSDHC
sending their CID immediately and must wait for the next identification cycle. Since the
CID is unique for each card, only one card can be successfully send its full CID to the
host. This card then goes into the Identification State. Thereafter, the host issues
Set_Relative_Addr (CMD3) to assign to the card a relative card address (RCA). Once the
RCA is received the card state changes to the Stand-by State, and the card does not react
in further identification cycles, and its output driver switches from open-drain to push-
pull. The host repeats the process, mainly CMD2 and CMD3, until the host receives a
time-out condition to recognize the completion of the identification process.
card_registry()
{
do { // decide RCA for each card until response time-out
if(card is labelled as SDCombo or SDIO) { // for SDIO card like device
send_command(SET_RELATIVE_ADDR, 0x00, <...>); // ask SDIO card to
publish its
RCA
retrieve RCA from response;
} // end if (card is labelled as SDCombo ...
else if (card is labelled as SD) { // for SD card
send_command(ALL_SEND_CID, <...>);
if (RESP_TIMEOUT == wait_for_response(ALL_SEND_CID)) break;
send_command(SET_RELATIVE_ADDR, <...>);
retrieve RCA from response;
} // else if (card is labelled as SD ...
else if (card is labelled as MMC) {
send_command(ALL_SEND_CID, <...>);
rca = 0x1; // arbitrarily set RCA, 1 here for example
send_command(SET_RELATIVE_ADDR, 0x1 << 16, <...>); // send RCA at upper
16
bits
} // end of else if (card is labelled as MMC ...
} while (response is not time-out);
}
22.5.3 Card access
This section describes access to the card.
22.5.3.1 Block write
22.5.3.1.1 Normal write
During a block write (CMD24 - 27), one or more blocks of data are transferred from the
host to the card with a CRC appended to the end of each block by the host.
If the CRC fails, the card should indicate the failure on the DAT line. The transferred
data will be discarded and not written, and all further transmitted blocks (in multiple
block write mode) will be ignored.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1122 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
If the host uses partial blocks whose accumulated length is not block aligned and block
misalignment is not allowed (CSD parameter WRITE_BLK_MISALIGN is not set), the
card detects the block misalignment error and aborts the programming before the
beginning of the first misaligned block. The card sets the ADDRESS_ERROR error bit in
the status register, and while ignoring all further data transfer, waits in the Receive-data-
State for a stop command. The write operation is also aborted if the host tries to write
over a write protected area.
For MMC and SD cards, programming of the CID and CSD registers do not require a
previous block length setting. The transferred data is also CRC protected. If a part of the
CSD or CID register is stored in ROM, then this unchangeable part must match the
corresponding part of the receive buffer. If this match fails, then the card will report an
error and not change any register contents.
For all types of cards, some may require long and unpredictable periods of time to write a
block of data. After receiving a block of data and completing the CRC check, the card
will begin writing and hold the DAT line low if its write buffer is full and unable to
accept new data from a new WRITE_BLOCK command. The host may poll the status of
the card with a SEND_STATUS command (CMD13) or other means for SDIO cards at
any time, and the card will respond with its status. The responded status indicates
whether the card can accept new data or whether the write process is still in progress. The
host may deselect the card by issuing a CMD7 (to select a different card) to place the
card into the Standby State and release the DAT line without interrupting the write
operation. When re-selecting the card, it will reactivate the busy indication by pulling
DAT to low if the programming is still in progress and the write buffer is unavailable.
The software flow to write to a card using DMA mode is as follows:
1. Check the card status, wait until the card is ready for data.
2. Set the card block length/size:
a. For SD/MMC cards , use SET_BLOCKLEN (CMD16)
b. For SDIO cards or the I/O portion of SDCombo cards, use IO_RW_DIRECT
(CMD52) to set the I/O block size bit field in the CCCR register (for function 0)
or FBR register (for functions 1-7)
3. Set the eSDHC block length register to be the same as the block length set for the
card in Step 2.
4. Set the eSDHC number block register (NOB), nob is 5 (for instance).
5. Disable the buffer write ready interrupt, configure the DMA settings and enable the
eSDHC DMA when sending the command with data transfer. The AC12EN bit
should also be set.
6. Wait for the Transfer Complete interrupt.
7. Check the status bit to see if a write CRC error occurred, or some other error that
occurred during the auto12 command sending and response receiving.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1123
Initialization/application of eSDHC
The software flow to write to a card using CPU Polling mode is as follows:
1. Check the card status, wait until the card is ready for data.
2. Set the card block length/size:
a. For SD/MMC cards , use SET_BLOCKLEN (CMD16)
b. For SDIO cards or the I/O portion of SDCombo cards, use IO_RW_DIRECT
(CMD52) to set the I/O Block Size bit field in the CCCR register (for function 0)
or FBR register (for functions 1-7)
3. Set the eSDHC block length register to be the same as the block length set for the
card in Step 2.
4. Set the eSDHC number block register (NOB), nob is 5 (for instance).
5. Issue the command with data transfer. The AC12EN bit should also be set.
6. Wait for IRQSTAT[BWR] interrupt to be set.
7. Write to Buffer port register for no. of times programmed in WML[WR_WML]
considering restriction mentioned in Software polling procedure.
8. Clear IRQSTAT[BWR].
9. Repeat 6-8 steps for rest of the data transfer.
10. Wait for the Transfer Complete interrupt.
11. Check the status bit to see if a write CRC error occurred, or some other error that
occurred during the auto12 command sending and response receiving.
22.5.3.1.2 Write with pause
The write operation can be paused during the transfer.
Instead of stopping the SDHC_CLK at any time to pause all the operations, which is also
inaccessible to the host driver, the driver can set the PROCTL[SABGREQ] to pause the
transfer between the data blocks. As there is no time-out condition in a write operation
during the data blocks, a write to all types of cards can be paused in this way, and if the
DAT0 line is not required to de-assert to release the busy state, no suspend command is
needed.
Like in the flow described in Normal write, the write with pause is shown with the same
kind of write operation:
1. Check the card status, wait until card is ready for data.
2. Set the card block length/size:
a. For SD/MMC cards , use SET_BLOCKLEN (CMD16)
b. For SDIO cards or the I/O portion of SDCombo cards, use
IO_RW_DIRECT(CMD52) to set the I/O block size bit field in the CCCR
register (for function 0) or FBR register (for functions 1-7)
3. Set the eSDHC block length register to be the same as the block length set for the
card in Step 2.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1124 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
4. Set the eSDHC number block register (NOB), nob is 5 (for instance).
5. Disable the buffer write ready interrupt, configure the DMA settings and enable the
eSDHC DMA when sending the command with data transfer. The AC12EN bit
should also be set.
6. Set the SABGREQ bit.
7. Wait for the Transfer Complete interrupt.
8. Clear the SABGREQ bit.
9. Check the status bit to see if a write CRC error occurred.
10. Set the CREQ bit to continue the write operation.
11. Wait for the Transfer Complete interrupt.
12. Check the status bit to see if a write CRC error occurred, or some another error, that
occurred during the auto12 command sending and response receiving.
The number of blocks left during the data transfer is accessible by reading the contents of
BLKATTR[BLKCNT]. As the data transfer and the setting of the SABGREQ bit are
concurrent, and the delay of register read and the register setting, the actual number of
blocks left may not be exactly the value read earlier. The driver should read the value of
BLKCNT after the transfer is paused and the transfer complete interrupt is received.
It is also possible the last block has begun when the stop at block gap request is sent to
the buffer. In this case, the next block gap is actually the end of the transfer. These types
of requests are ignored and the driver should treat this as a non-pause transfer and deal
with it as a common write operation.
When the write operation is paused, the data transfer inside the host system is not
stopped, and the transfer is active until the data buffer is full. Because of this (if not
needed), it is recommended to avoid using the suspend command for the SDIO card. This
is because, when such a command is sent, the eSDHC thinks that the system will switch
to another function on the SDIO card, and flush the data buffer. The eSDHC takes the
resume command as a normal command with data transfer, and it is left for the driver to
set all the relevant registers before the transfer is resumed. If there is only one block to
send when the transfer is resumed, XFERTYP[MSBSEL] and XFERTYP[BCEN] are set
as well as XFERTYP[AC12EN]. However, the eSDHC will automatically send a
CMD12 to mark the end of the multi-block transfer.
22.5.3.2 Block read
22.5.3.2.1 Normal read
For block reads, the basic unit of data transfer is a block whose maximum size is stored in
areas defined by the corresponding card specification.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1125
Initialization/application of eSDHC
A CRC is appended to the end of each block, ensuring data transfer integrity. The
CMD17, CMD18, CMD53, CMD60, CMD61, and so on, can initiate a block read. After
completing the transfer, the card returns to the transfer state. For multi-blocks read, data
blocks will be continuously transferred until a stop command is issued.
The software flow to read from a card using DMA mode is as follows:
1. Check the card status, wait until card is ready for data.
2. Set the card block length/size:
a. For SD/MMC cards , use SET_BLOCKLEN (CMD16)
b. For SDIO cards or the I/O portion of SDCombo cards, use
IO_RW_DIRECT(CMD52) to set the I/O block size bit field in the CCCR
register (for function 0) or FBR register (for functions 1-7)
3. Set the eSDHC block length register to be the same as the block length set for the
card in Step 2.
4. Set the eSDHC number block register (NOB), nob is 5 (for instance).
5. Disable the buffer read ready interrupt, configure the DMA settings and enable the
eSDHC DMA when sending the command with data transfer. The AC12EN bit
should also be set.
6. Wait for the Transfer Complete interrupt.
7. Check the status bit to see if a read CRC error occurred, or some other error,
occurred during the auto12 command sending and response receiving.
The software flow to read from a card using CPU polling mode is as follows:
1. Check the card status, wait until card is ready for data.
2. Set the card block length/size:
a. For SD/MMC cards , use SET_BLOCKLEN (CMD16)
b. For SDIO cards or the I/O portion of SDCombo cards, use
IO_RW_DIRECT(CMD52) to set the I/O block size bit field in the CCCR
register (for function 0) or FBR register (for functions 1-7)
3. Set the eSDHC block length register to be the same as the block length set for the
card in Step 2.
4. Set the eSDHC number block register (NOB), nob is 5 (for instance).
5. Issue the command with data transfer. The AC12EN bit should also be set.
6. Wait for IRQSTAT[BRR] interrupt to be set.
7. Read from Buffer port register for number of times programmed in
WML[RD_WML] considering restriction mentioned in Software polling procedure.
8. Clear IRQSTAT[BRR].
9. Repeat 6-8 steps for rest of the data transfer.
10. Wait for the Transfer Complete interrupt.
11. Check the status bit to see if a read CRC error occurred, or some other error,
occurred during the auto12 command sending and response receiving.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1126 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
22.5.3.2.2 Read with pause
The read operation is not generally able to pause. Only the SDIO card (and SDCombo
card working under I/O mode) supporting the read wait feature can pause during the read
operation.
If the SDIO card support read wait (SRW bit in CCCR register is 1), the driver can set the
PROCTL[SABGREQ] to pause the transfer between the data blocks. Before setting the
SABGREQ bit, make sure the PROCTL[RWCTL] is set, otherwise the eSDHC will not
assert the read wait signal during the block gap and data corruption occurs. It is
recommended to set the RWCTL bit once the read wait capability of the SDIO card is
recognized.
Like in the flow described in Normal read, the read with pause is shown with the same
kind of read operation:
1. Check the SRW bit in the CCR register on the SDIO card to confirm the card
supports read wait.
2. Set the RWCTL bit.
3. Check the card status and wait until the card is ready for data.
4. Set the card block length/size:
a. For SD/MMC cards , use SET_BLOCKLEN (CMD16)
b. For SDIO cards or the I/O portion of SDCombo cards, use
IO_RW_DIRECT(CMD52) to set the I/O block size bit field in the CCCR
register (for function 0) or FBR register (for functions 1-7)
5. Set the eSDHC block length register to be the same as the block length set for the
card in Step 4.
6. Set the eSDHC number block register (NOB), nob is 5 (for instance).
7. Disable the buffer read ready interrupt, configure the DMA setting and enable the
eSDHC DMA when sending the command with data transfer. The AC12EN bit
should also be set.
8. Set the SABGREQ bit.
9. Wait for the transfer complete interrupt.
10. Clear the SABGREQ bit.
11. Check the status bit to see if read CRC error occurred.
12. Set the CREQ bit to continue the read operation.
13. Wait for the transfer complete interrupt.
14. Check the status bit to see if a read CRC error occurred, or some other error,
occurred during the auto12 command sending and response receiving.
Like the write operation, it is possible to meet the ending block of the transfer when
paused. In this case, the eSDHC will ignore the stop at block gap request and treat it as a
command read operation.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1127
Initialization/application of eSDHC
Unlike the write operation, there is no remaining data inside the buffer when the transfer
is paused. All data received before the pause will be transferred to the Host System. Even
if the Suspend Command is sent or not, the internal data buffer is not flushed.
If the Suspend Command is sent and the transfer is later resumed by means of a Resume
Command, the eSDHC takes the command as a normal one accompanied with data
transfer. It is left for the driver to set all the relevant registers before the transfer is
resumed. If there is only one block to send when the transfer is resumed,
XFERTYP[MSBSEL] and XFERTYP[BCEN] are set, as well as XFERTYP[AC12EN].
However, the eSDHC will automatically send the CMD12 to mark the end of multi-block
transfer.
22.5.3.3 Suspend resume
The eSDHC supports the suspend resume operations of SDIO cards, although slightly
different than the suggested implementation of suspend in the SDIO card specification.
22.5.3.3.1 Suspend
After setting the SABGREQ bit, the host driver may send a Suspend command to switch
to another function of the SDIO card. The eSDHC does not monitor the content of the
response, so it doesn't know if the Suspend command succeeded or not.
Accordingly, it doesn't de-assert Read Wait for read pause. To solve this problem, the
driver should not mark the Suspend command as a "Suspend", (that is, setting the
CMDTYP bits to 01). Instead, the driver should send this command as if it were a normal
command, and only when the command succeeds, and the BS bit is set in the response,
can the driver send another command marked as "Suspend" to inform the eSDHC that the
current transfer is suspended. As shown in the following sequence for Suspend operation:
1. Set the SABREQ bit to pause the current data transfer at block gap.
2. After the BGE bit is set, save the context registers in the system memory for later
use, including the SDMA system address register (DSADDR) for DMA operation,
and the block attributes register (BLKATTR).
3. Send the Suspend command to suspend the active function. The CMDTYP bit field
must be 2'b00.
4. Check the BS bit of the CCCR in the response. If it is 1, repeat this step until the BS
bit is cleared or abandon the suspend operation according to the driver strategy.
5. Send another normal I/O command to the suspended function. The CMDTYP of this
command must be 2'b01, so the eSDHC can detect this special setting and be
informed that the paused operation has successfully suspended. If the paused transfer
is a read operation, the eSDHC stops driving DAT2 and goes to the idle state.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1128 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
6. Begin operation for another function on the SDIO card.
22.5.3.3.2 Resume
To resume the data transfer, a resume command should be issued:
1. To resume the suspended function, restore the context register with the saved value
in step #2 of the suspend operation above.
2. Send the resume command. In the transfer type register (XFERTYP), all bit fields are
set to the value as if this were another ordinary data transfer, instead of a transfer
resume (except the CMDTYP is set to 2'b10).
3. If the resume command has responded, the data transfer will be resumed.
22.5.3.4 ADMA usage
To use the ADMA in a data transfer, the host driver must prepare the correct descriptor
chain prior to sending the read/write command.
To accomplish this:
1. Create a descriptor to set the data length that the current descriptor group is about to
transfer. The data length should be even numbers of the block size.
2. Create another descriptor to transfer the data from the address setting in this
descriptor. The data address must be at a page boundary (4 Kbyte address aligned).
3. If necessary, create a Link descriptor containing the address of the next descriptor.
The descriptor group is created in steps 1-3.
4. Repeat steps 1-3 until all descriptors are created.
5. In the last descriptor, set the end flag to 1 and make sure the total length of all
descriptors match the product of the block size and block number configured in the
block attributes register (BLKATTR).
6. Set the ADMA system address register (ADSADDR) to the address of the first
descriptor and set PROCTL[DMAS] to 01 to select the ADMA.
7. Issue a write or read command with XFERTYP[DMAEN] set.
Steps 1-5 are independent of step 6, so step 6 can finish before steps 1-5. Regarding the
descriptor configuration, it is recommended not to use the link descriptor as it requires
extra system memory access.
22.5.3.5 Tuning block procedure
Tuning block is used for SD UHS SDR50, SDR104 and MMC HS200 modes.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1129
Initialization/application of eSDHC
Host driver should execute tuning procedure before initiating data transfer with these
speed modes.
The steps for using tuning block are:
1. Clear SYSCTL[SDCLKEN]
2. Wait for PRSSTAT[SDSTB] to be set
3. Set ESDHCCTL[FAF]
4. Wait for ESDHCCTL[FAF] to be cleared
5. Set appropriate AUTOCERR[UHSM]
6. Set TBCTL[TB_EN] and program appropriate TBCTL[TB_MODE]
7. Set SYSCTL[SDCLKEN]
8. Wait for PRSSTAT[SDSTB] to be set
9. Execute tuning procedure
While tuning procedure is being performed, eSDHC doesn’t generate any other command
or data interrupt except buffer read ready in IRQSTAT register.
When tuning error is received, host driver should abort the current data transfer and
execute the tuning procedure.
ESDHCCTL[PCS] (peripheral clock select), and TBCTL[TB_EN] (tuning block enable)
should always be set whenever using tuning block. PCS should be set before TB_EN.
NOTE
• Similar steps needs to be performed to disable tuning block,
except programming different values in 5 and 6. Also 9
need not to be performed.
• For tuning mode operation, the SD clock divisor value must
be within 3 to 16.
22.5.3.5.1 Tuning procedure for hardware tuning modes
The steps for tuning procedure, when TBCTL[TB_MODE] is programmed to either
Mode 1, Mode 2 or Mode 3, are:
1. Set SYSCTL2[EXTN], execute tuning.
2. Issue SEND_TUNING_BLK Command (CMD19 for SD, CMD21 for MMC).
3. Wait for IRQSTAT[BRR], buffer read ready, to be set.
4. Clear IRQSTAT[BRR].
5. Check SYSCTL2[EXTN] to be cleared.
6. Repeat steps 2-5, if EXTN is not cleared.
7. Check SYSCTL2[SMPCLKSEL], sampling clock select. It's set value indicates
tuning procedure success, and clears indicate failure. In case of tuning failure, fixed
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1130 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
sampling scheme could be used by clearing TBCTL[TB_EN], tuning block enable
bit.
22.5.3.5.2 Tuning procedure for software tuning mode
The steps for tuning procedure, when TBCTL[TB_MODE] is set to SW tuning mode,
are:
1. Program the start and end pointer for the data window in the TPR register.
2. Set SYSCTL2[EXTN] and SYSCTL2[SMPCLKSEL], execute tuning.
3. Issue SEND_TUNING_BLK Command (CMD19 for SD, CMD21 for MMC).
4. Wait for IRQSTAT[BRR], buffer read ready, to be set.
5. Clear IRQSTAT[BRR].
6. Check SYSCTL2[EXTN] to be cleared.
7. Check SYSCTL2[SMPCLKSEL], sampling clock select. It's set value indicates
tuning procedure success, and clears indicate failure. In case of tuning failure, fixed
sampling scheme could be used by clearing TBCTL[TB_EN], tuning block enable
bit.
22.5.3.6 DDR
The steps for using DDR mode are:
1. Clear SYSCTL[SDCLKEN]
2. Wait for PRSSTAT[SDSTB] to be set
3. Program AUTOCERR[UHSM] to 4
4. If required, change the clock division ratio in SYSCTL register
5. Set SDCLKCTL[CMD_CLK_CTL] and SDCLKCTL[LPBK_CLK_SEL] for DDR
mode
6. Set SYSCTL[SDCLKEN]
7. Wait for PRSSTAT[SDSTB] to be set
8. Again clear SYSCTL[SDCLKEN]
9. Wait for PRSSTAT[SDSTB] to be set
10. Set ESDHCCTL[FAF]
11. Wait for ESDHCCTL[FAF] to be cleared
12. Set SYSCTL[SDCLKEN]
13. Wait for PRSSTAT[SDSTB] to be set
NOTE
1. SD clock divisor should be even for DDR mode.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1131
Initialization/application of eSDHC
2. Similar steps needs to be performed to disable, except
programming different value in 3
22.5.3.7 Transfer error
22.5.3.7.1 CRC transfer error
It is possible at the end of a block transfer, that a write CRC status error or read CRC
error occurs.
For this type of error the latest block received should be discarded.
This is because the integrity of the data block is not guaranteed. It is recommended to
discard the following data blocks and re-transfer the block from the corrupted one. For a
multi-block transfer, the host driver should issue a CMD12 to abort the current process
and start the transfer by a new data command. In this scenario, even when the AC12EN
and BCEND bits are set, the eSDHC does not automatically send a CMD12 because the
last block is not transferred. On the other hand, if it is within the last block that the CRC
error occurs, an Auto CMD12 will be sent by the eSDHC. In this case, the driver should
re-send or re-obtain the last block with a single block transfer.
22.5.3.7.2 DMA transfer error
During the data transfer with internal single DMA, if the DMA engine encounters some
error on the System bus, the DMA operation is aborted and DMA error interrupt is sent to
the host system.
When acknowledged by such an interrupt, the driver should calculate the start address of
data block in which the error occurs. The start address can be calculated by:
Read the DMA error address register (DMAERRADDR). Taking the block size and the
start address intially preogrammed in SDMA Adress register, it is straight forward to
obtain the start address of the corrupted block.
When a DMA error occurs, it is recommended to abort the current transfer by means of a
CMD12 (for multi block transfer), apply a reset for data, and re-start the transfer from the
corrupted block to recover from the error.
22.5.3.7.3 ADMA transfer error
There are three kinds of possible ADMA errors; The System transfer, invalid descriptor,
and data-length mismatch errors.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1132 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
Whenever these errors occur, the DMA transfer stops and the corresponding error status
bit is set. For acknowledging the status, the host driver should recover the error as shown
below and re-transfer from the place of interruption.
1. System transfer error: Such errors may occur during data transfer or descriptor fetch.
For either scenario, it is recommended to retrieve the transfer context, reset for the
data part and re-transfer the block that was corrupted, or the next block if no block is
corrupted.
2. Invalid descriptor error: For such errors, it is recommended to retrieve the transfer
context, reset for the data part and re-create the descriptor chain from the invalid
descriptor and issue a new transfer. As the data to transfer now may be less than the
previous setting, the data length configured in the new descriptor chain should match
the new value.
3. Data-length mismatch error: It is similar to recover from this error. The host driver
polls relating registers to retrieve the transfer context, apply a reset for the data part,
configure a new descriptor chain, and make another transfer if there is data left. Like
the previous scenario of the invalid descriptor error, the data length must match the
new transfer.
22.5.3.7.4 Auto CMD12 error
After the last block of the multi block transfer is sent or received, and the AC12EN bit is
set when the data transfer is initiated by the data command, the eSDHC automatically
sends a CMD12 to the card to stop the transfer.
When errors with this command occur, it is recommended to the driver to deal with the
situations in the following manner:
1. Auto CMD12 response time-out. It is not certain whether the command is accepted
by the card or not. The driver should clear the Auto CMD12 error status bits and re-
send the CMD12 until it is accepted by the card.
2. Auto CMD12 response CRC error. Since card responds to the CMD12, the card will
abort the transfer. The driver may ignore the error and clear the error status bit.
3. Auto CMD12 conflict error or not sent. The command is not sent, so the driver
should send a CMD12 manually.
22.5.3.8 Card interrupt
The external cards can inform the host controller by means of some special signals. For
the SDIO card, it can be the low level on the DAT[1] line during some special period.
The eSDHC only monitors the DAT[1] line and supports the SDIO interrupt.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1133
Initialization/application of eSDHC
When the SDIO interrupt is captured by the eSDHC, and the Host System is informed by
the eSDHC asserting the eSDHC interrupt line, the interrupt service from the host driver
is called.
As the interrupt factor is controlled by the external card, the interrupt from the SDIO card
must be served before the CINT bit is cleared by written 1. Refer to Card interrupt
handling for the card interrupt handling flow.
22.5.4 Switch function
MMC cards transferring data at bus widths other than 1-bit is a new feature added to the
MMC spec.
The high speed timing mode for all card devices, was also recently defined in various
card specifications. To enable these new features, a "switch" command should be issued
by the host driver.
For SDIO cards, the high speed mode is enabled by writing the EHS bit in the CCCR
register after the SHS bit is confirmed. For SD cards, the high speed mode is queried and
enabled by a CMD6 (with the mnemonic symbol as SWITCH_FUNC). For MMC cards,
the high speed mode is queried by a CMD8 and enabled by a CMD6 (with the mnemonic
symbol as SWITCH).
The 4-bit and 8-bit bus width of the MMC is also enabled by the SWITCH command, but
with a different argument.
These new functions can also be disabled by a software reset. For SDIO cards, it can be
done by setting the RES bit in the CCCR register. For other cards, it can be accomplished
by issuing a CMD0. This method of restoring to the normal mode is not recommended
because a complete identification process is needed before the card is ready for data
transfer.
For the sake of simplicity, the following flowcharts do not show current capability check,
which is recommended in the function switch process.
22.5.4.1 Query, enable and disable SDIO high speed mode
enable_sdio_high_speed_mode(void)
{
send CMD52 to query bit SHS at address 0x13;
if (SHS bit is '0') report the SDIO card does not support high speed mode and return;
send CMD52 to set bit EHS at address 0x13 and read after write to confirm EHS bit is set;
change clock divisor value or configure the system clock feeding into eSDHC to generate the
card_clk of around 50MHz;
(data transactions like normal peers)
}
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1134 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
disable_sdio_high_speed_mode(void)
{
send CMD52 to clear bit EHS at address 0x13 and read after write to confirm EHS bit is
cleared;
change clock divisor value or configure the system clock feeding into eSDHC to generate the
card_clk of the desired value below 25MHz;
(data transactions like normal peers)
}
22.5.4.2 Query, enable and disable SD high speed mode
enable_sd_high_speed_mode(void)
{
set BLKCNT field to 1 (block), set BLKSIZE field to 64 (bytes);
send CMD6, with argument 0xFFFFF1 and read 64 bytes of data accompanying the R1 response;
wait data transfer done bit is set;
check if the bit 401 of received 512 bit is set;
if (bit 401 is '0') report the SD card does not support high speed mode and return;
send CMD6, with argument 0x80FFFFF1 and read 64 bytes of data accompanying the R1 response;
check if the bit field 379~376 is 0xF;
if (the bit field is 0xF) report the function switch failed and return;
change clock divisor value or configure the system clock feeding into eSDHC to generate the
card_clk of around 50MHz;
(data transactions like normal peers)
}
disable_sd_high_speed_mode(void)
{
set BLKCNT field to 1 (block), set BLKSIZE field to 64 (bytes);
send CMD6, with argument 0x80FFFFF0 and read 64 bytes of data accompanying the R1 response;
check if the bit field 379~376 is 0xF;
if (the bit field is 0xF) report the function switch failed and return;
change clock divisor value or configure the system clock feeding into eSDHC to generate the
card_clk of the desired value below 25MHz;
(data transactions like normal peers)
}
22.5.4.3 Query, enable and disable MMC high speed mode
enable_mmc_high_speed_mode(void)
{
send CMD9 to get CSD value of MMC;
check if the value of SPEC_VER field is 4 or above;
if (SPEC_VER value is less than 4) report the MMC does not support high speed mode and
return;
set BLKCNT field to 1 (block), set BLKSIZE field to 512 (bytes);
send CMD8 to get EXT_CSD value of MMC;
extract the value of CARD_TYPE field to check the 'high speed mode' in this MMC is 26MHz or
52MHz;
send CMD6 with argument 0x1B90100;
send CMD13 to wait card ready (busy line released);
send CMD8 to get EXT_CSD value of MMC;
check if HS_TIMING byte (byte number 185) is 1;
if (HS_TIMING is not 1) report MMC switching to high speed mode failed and return;
change clock divisor value or configure the system clock feeding into eSDHC to generate the
card_clk of around 26MHz or 52MHz according to the CARD_TYPE;
(data transactions like normal peers)
}
disable_mmc_high_speed_mode(void)
{
send CMD6 with argument 0x2B90100;
set BLKCNT field to 1 (block), set BLKSIZE field to 512 (bytes);
send CMD8 to get EXT_CSD value of MMC;
check if HS_TIMING byte (byte number 185) is 0;
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1135
Initialization/application of eSDHC
if (HS_TIMING is not 0) report the function switch failed and return;
change clock divisor value or configure the system clock feeding into eSDHC to generate the
card_clk of the desired value below 20MHz;
(data transactions like normal peers)
}
22.5.4.4 Set MMC bus width
change_mmc_bus_width(void)
{
send CMD9 to get CSD value of MMC;
check if the value of SPEC_VER field is 4 or above;
if (SPEC_VER value is less than 4) report the MMC does not support multiple bit width and
return;
send CMD6 with argument 0x3B70x00; (8-bit, x=2; 4-bit, x=1; 1-bit, x=0)
send CMD13 to wait card ready (busy line released);
(data transactions like normal peers)
}
22.5.5 ADMA operation
22.5.5.1 ADMA1 operation
Set_adma1_descriptor
{
if (to start data transfer) {
// Make sure the address is 4KB align.
Set 'Set' type descriptor;
{
Set Act bits to 01;
Set [31:12] bits data length (byte unit);
}
Set 'Tran' type descriptor;
{
Set Act bits to 10;
Set [31:12] bits address (4KB align);
}
}
else if (to fetch descriptor at non-continuous address) {
Set Act bits to 11;
Set [31:12] bits the next descriptor address (4KB align);
}
else { // other types of descriptor
Set Act bits accordingly
}
if (this descriptor is the last one) {
Set End bit to 1;
}
if (to generate interrupt for this descriptor) {
Set Int bit to 1;
}
Set Valid bit to 1;
}
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1136 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
22.5.5.2 ADMA2 operation
Set_adma2_descriptor
{
if (to start data transfer) {
// Make sure the address is 32-bit boundary (lower 2-bit are always '00').
Set higher 32-bit of descriptor for this data transfer initial address;
Set [31:16] bits data length (byte unit);
Set Act bits to '10';
}
else if (to fetch descriptor at non-continuous address) {
Set Act bits to '11';
// Make sure the address is 32-bit boundary (lower 2-bit are always set to '00').
Set higher 32-bit of descriptor for the next descriptor address;
}
else { // other types of descriptor
Set Act bits accordingly
}
if (this descriptor is the last one) {
Set 'End' bit '1';
}
if (to generate interrupt for this descriptor) {
Set 'Int' bit '1';
}
Set the 'Valid' bit to '1';
}
22.6 Interfacing Card
eSDHC and card IO voltage might be different. External on board voltage translator can
be used to interface the card in that case.
Following diagram illustrates direct interfacing of eSDHC with card when voltage level
is same at both ends. SD_CLK_SYNC_OUT and SD_CLK_SYNC_IN should be routed
as close as possible to card, with minimum skew with respect to SD_CLK.
SD_CLK
SD_CLK_SYNC_OUT
SD_CLK_SYNC_IN
Card
eSDHC SD_CMD/DATA
Figure 22-21. Direct Interfacing of eSDHC with Card
Below figure illustrates interfacing card with eSDHC through voltage translator when the
voltages are different. CMD/DATA DIR and SD_VS pins might be required when
interfacing with voltage translator that support DDR, and SDR more than 50 MHz
modes. eSDHC SD_VS, or GPIO could be used to control SEL pin of the translator.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1137
Commands for MMC/SD/SDIO and
SD_CLK SD_CLK
SD_CLK_SYNC_IN CLK-f
SD_CMD/DATA SD CMD/DATA
SD_CMD_DIR,
SD_DAT0_DIR, Voltage
Card
eSDHC SD_DAT123_DIR Translator
SD_VS or
GPIO
SEL
Figure 22-22. Card Interfacing with eSDHC through Voltage Translator
NOTE
CD, WP and DAT4-7 are not shown in above figures for
simplicity.
22.7 Commands for MMC/SD/SDIO and
See the table below for the list of commands for the MMC/SD/SDIO cards .
Refer the corresponding specifications for more details about the command information.
There are four kinds of commands defined to control the MultiMediaCard:
• Broadcast commands (bc), no response
• Broadcast commands with response (bcr), response from all cards simultaneously
• Addressed (point-to-point) commands (ac), no data transfer on the DAT
• Addressed (point-to-point) data transfer commands (adtc)
The access bits for the EXT_CSD access modes are shown in Table 22-12.
Table 22-11. Commands for MMC/SD/SDIO cards
CMD Type Argument Resp Abbreviation Description
INDEX
CMD0 bc [31:0] stuff bits - GO_IDLE_STATE Resets all MMC and SD memory cards
to idle state.
CMD1 bcr [31:0] OCR without R3 SEND_OP_COND Asks all MMC and SD Memory cards in
busy idle state to send their operation
conditions register contents in the
response on the CMD line.
CMD2 bcr [31:0] stuff bits R2 ALL_SEND_CID Asks all cards to send their CID
numbers on the CMD line.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1138 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
Table 22-11. Commands for MMC/SD/SDIO cards (continued)
CMD Type Argument Resp Abbreviation Description
INDEX
CMD31 ac [31:16] RCA R1 SET/ Assigns relative address to the card.
SEND_RELATIVE_ADD
[15:0] stuff bits R6 (SDIO)
R
CMD4 bc [31:16] DSR - SET_DSR Programs the DSR of all cards.
[15:0] stuff bits
CMD5 bc [31:0] OCR without R4 IO_SEND_OP_COND Asks all SDIO cards in idle state to send
busy their operation conditions register
contents in the response on the CMD
line.
CMD62 adtc [31] Mode R1 SWITCH_FUNC Checks switch ability (mode 0) and
switch card function (mode 1). Refer
0: Check function
"SD Physical Specification V1.1" for
1: Switch function more details.
[30:8] Reserved for
function groups 6 - 3
(All 0 or 0xFFFF)
[7:4] Function group1
for command system
[3:0] Function group2
for access mode
CMD63 ac [31:26] Set to 0 R1b SWITCH Switches the mode of operation of the
selected card or modifies the EXT_CSD
[25:24] Access
registers. Refer "The MultiMediaCard
[23:16] Index System Specification Version 4.0 Final
draft 2" for more details.
[15:8] Value
[7:3] Set to 0
[2:0] Cmd Set
CMD7 ac [31:16] RCA R1b SELECT/ Toggles a card between the stand-by
DESELECT_CARD and transfer states or between the
[15:0] stuff bits
programming and disconnect states. In
both cases, the card is selected by its
own relative address and gets
deselected by any other address.
Address 0 deselects all.
CMD84 bcr [31:12] reserved bits R7 SEND_IF_COND Sends SD memory card interface
condition, which includes host supply
[11:8] supply voltage
voltage information and asks the card
(VHS)
whether card supports voltage.
[7:0] check pattern Reserved bits shall be set to 0.
CMD85 adtc [31:0] stuff bits R1 SEND_EXT_CSD The card sends its EXT_CSD register as
a block of data, with a block size of 512
bytes.
CMD9 ac [31:16] RCA R2 SEND_CSD Addressed card sends its card-specific
data (CSD) on the CMD line.
[15:0] stuff bits
CMD10 ac [31:16] RCA R2 SEND_CID Addressed card sends its card-
identification (CID) on the CMD line.
[15:0] stuff bits
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1139
Commands for MMC/SD/SDIO and
Table 22-11. Commands for MMC/SD/SDIO cards (continued)
CMD Type Argument Resp Abbreviation Description
INDEX
CMD11 ac [31:0] stuff bits R1 VOLTAGE_SWITCH Switch to 1.8V bus signalling level.
Applicable for UHS SD card.
CMD12 ac [31:0] stuff bits R1b STOP_TRANSMISSION Forces the card to stop transmission.
CMD13 ac [31:16] RCA R1 SEND_STATUS Addressed card sends its status register.
[15:0] stuff bits
CMD14 Reserved
CMD15 ac [31:16] RCA - GO_INACTIVE_STATE Sets the card to inactive state in order to
protect the card stack against
[15:0] stuff bits
communication breakdowns.
CMD16 ac [31:0] block length R1 SET_BLOCKLEN Sets the block length (in bytes) for all
following block commands (read and
write). Default block length is specified in
the CSD.
CMD17 adtc [31:0] data address R1 READ_SINGLE_BLOC Reads a block of the size selected by
K the SET_BLOCKLEN command.
CMD18 adtc [31:0] data address R1 READ_MULTIPLE_BLO Continuously transfers data blocks from
CK card to host until interrupted by a stop
command.
CMD19 adtc [31:0] stuff bits R1 SEND_TUNING_BLOC 64 bytes tuning pattern is sent for
K SDR50 and SDR104. Applicable for
UHS SD card.
CMD20 Reserved
CMD21 adtc [31:0] stuff bits R1 SEND_TUNING_BLOC 128 clocks of tuning pattern (64 byte in
K 4-bit mode or 128 byte in 8-bit mode) is
sent for HS200 optimal sampling point
detection. Applicable for MMC card.
CMD22 Reserved
CMD23 ac [31:16] set to 0 R1 SET_BLOCKCOUNT Defines the number of blocks which are
going to be transferred in the
[15:0] block count
immediately succeeding multiple block
read or write command. If the argument
is all 0s, the subsequent read/write
operations are openended.
CMD24 adtc [31:0] data address R1 WRITE_BLOCK Writes a block of the size selected by
the SET_BLOCKLEN command.
CMD25 adtc [31:0] data address R1 WRITE_MULTIPLE_BL Continuously writes blocks of data until a
OCK STOP_TRANSMISSION follows.
CMD26 adtc [31:0] stuff bits R1 PROGRAM_CID Programming of the card identification
register. This command should be
issued only once per card. The card
contains hardware to prevent this
operation after the first programming.
Normally this command is reserved for
the manufacturer.
CMD27 adtc [31:0] stuff bits R1 PROGRAM_CSD Programming of the programmable bits
of the CSD.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1140 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
Table 22-11. Commands for MMC/SD/SDIO cards (continued)
CMD Type Argument Resp Abbreviation Description
INDEX
CMD28 ac [31:0] data address R1b SET_WRITE_PROT If the card has write protection features,
this command sets the write protection
bit of the addressed group. The
properties of write protection are coded
in the card specific data
(WP_GRP_SIZE).
CMD29 ac [31:0] data address R1b CLR_WRITE_PROT If the card provides write protection
features, this command clears the write
protection bit of the addressed group.
CMD30 adtc [31:0] write protect R1 SEND_WRITE_PROT If the card provides write protection
data address features, this command asks the card to
send the status of the write protection
bits.
CMD31 Reserved
CMD32 ac [31:0] data address R1 ERASE_WR_BLK_STA Sets the address of the first write block
RT to be erased in SD card.
CMD32 ac [31:0] data address R1 TAG_SECTOR_START Sets the address of the first sector of the
erase group in MMC card.
CMD33 ac [31:0] data address R1 ERASE_WR_BLK_END Sets the address of the last write block
of the continuous range to be erased in
SD card.
CMD33 ac [31:0] data address R1 TAG_SECTOR_END Sets the address of the last sector in a
continuous range within the selection of
a single sector to be selected for erase
in MMC card.
CMD34 ac [31:0] data address R1 UNTAG_SECTOR Removes one previously selected sector
from the erase selection in MMC card.
CMD35 ac [31:0] data address R1 TAG_ERASE_GROUP_ Sets the address of the first erase group
START within a range to be selected for erase in
MMC card.
CMD36 ac [31:0] data address R1 TAG_ERASE_GROUP_ Sets the address of the last erase group
END within a continuous range to be selected
for erase in MMC card.
CMD37 ac [31:0] data address R1 UNTAG_ERASE_GRO Removes one previously selected erase
UP group from the erase selection in MMC
card.
CMD38 ac [31:0] stuff bits R1b ERASE Erase all previously selected sectors.
CMD39 ac [31:0] RCA R4 FAST_IO Used to write and read 8-bit (register)
data fields. The command addresses a
[15] register write flag
card, and a register, and provides the
[14:8] register data for writing if the write flag is set.
address The R4 response contains data read
from the address register. This
[7:0] register data
command accesses application
dependent registers which are not
defined in the MMC standard.
CMD40 bcr [31:0] stuff bits R5 GO_IRQ_STATE Sets the system into interrupt mode in
MMC card.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1141
Commands for MMC/SD/SDIO and
Table 22-11. Commands for MMC/SD/SDIO cards (continued)
CMD Type Argument Resp Abbreviation Description
INDEX
CMD41 Reserved
CDM42 adtc [31:0] stuff bits R1b LOCK_UNLOCK Used to set/reset the password or lock/
unlock the card. The size of the data
block is set by the SET_BLOCK_LEN
command.
CMD43-51 Reserved
CMD52 ac As per SDIO spec R5 IO_RW_DIRECT Access a single register within the total
CMD52 format 128k of register space in any I/O
function.
CMD53 ac As per SDIO spec R5 IO_RW_EXTENDED Accesses a multiple I/O register with a
CMD53 format single command. Allows the reading or
writing of a large number of I/O
registers.
CMD54 Reserved
CMD55 ac [31:16] RCA R1 APP_CMD Indicates to the card that the next
command is an application specific
[15:0] stuff bits
command rather that a standard
command.
CMD56 adtc [31:1] stuff bits R1b GEN_CMD Used either to transfer a data block to
the card or to get a data block from the
[0]: RD/WR
card for general purpose / application
specific commands. The size of the data
block is set by the SET_BLOCK_LEN
command.
CMD57-63 Reserved
ACMD6 ac [31:2] stuff bits [1:0] R1 SET_BUS_WIDTH Defines the data bus width ('00'=1bit or
bus width '10'=4bit bus) to be used for data
transfer. The allowed data bus widths
are given in SCR register.
ACMD136 adtc [31:0] stuff bits R1 SD_STATUS Send the SD Memory Card status.
ACMD186 adtc [31:0] stuff bits R1 SECURE_READ_MULT Protected Area Access Command:
I_BLOCK
Reads continuously transfer data blocks
from protected area of SD memory card.
Refer Security Specification Version
2.00 for more details.
ACMD226 adtc [31:0] stuff bits R1 SEND_NUM_WR_SEC Send the number of the written sectors
TORS (without errors). Responds with 32-bit
plus the CRC data block.
ACMD236 ac [31:0] stuff bits R1 SET_WR_BLK_ERASE In SD cards, set the number of write
_COUNT blocks to be pre-erased before writing
(to be used for faster multiple block write
command)
Default value is 1 (one write block).
ACMD256 adtc [31:0] stuff bits R1 SECURE_WRITE_MUL Protected Area Access Command:
TI_BLOCK
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1142 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
Table 22-11. Commands for MMC/SD/SDIO cards (continued)
CMD Type Argument Resp Abbreviation Description
INDEX
Writes continuously transfer data blocks
to protected area of SD memory card.
Refer Security Specification Version
2.00 for more details.
ACMD266 adtc [31:0] stuff bits R1 SECURE_WRITE_MKB System Area Access Command:
Overwrite the existing media key block
(MKB) on the system area of SD
Memory Card with new MKB. This
command is used in dynamic update
MKB scheme. Refer Security
Specification Version 2.00 for more
details.
ACMD386 ac [31:0] stuff bits R1b SECURE_ERASE Protected Area Access Command:
Erase a specified region of the Protected
Area of SD Memory Card. Refer
Security Specification Version 2.00 for
more details.
ACMD416 bcr [31:0] OCR R3 SD_APP_OP_COND Asks the accessed card to send its
operating condition register (OCR)
contents in the response on the CMD
line.
ACMD426 ac [31:1] stuff bits R1 SET_CLR_CARD_DET Connect [1]/Disconnect [0] the 50KΩ
ECT pull-up resistor on CD/DAT3 of SD card.
[0] set_cd
ACMD436 adtc [31:24]Unit_Count: R1 GET_MKB Reads Media Key Block from the
System Area of SD Memory Card.
[23:16] MKB_ID:
-Unit_Count specifies the Number of
[15:0]Unit_Offset:
units to read. (Here, a unit=512 byte
(fixed).)
- MKB_ID specifies the application
unique number.
- Unit_Offset specifies the start
address(offset) to read.
Refer Security Specification Version
2.00 for more details.
ACMD446 adtc [31:0] stuff bits R1 GET_MID Reads Media ID from the system area of
SD memory card. Refer Security
Specification Version 2.00 for more
details.
ACMD456 adtc [31:0] stuff bits R1 SET_CER_RN1 AKE Command:
Writes random number RN1 as
challenge1 in AKE process. Refer
Security Specification Version 2.00 for
more details.
ACMD466 adtc [31:0] stuff bits R1 GET_CER_RN2 AKE Command:
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1143
Software restrictions
Table 22-11. Commands for MMC/SD/SDIO cards (continued)
CMD Type Argument Resp Abbreviation Description
INDEX
Reads random number RN2 as
challenge2 in AKE process. Refer
security specification version 2.00 for
more details.
ACMD476 adtc [31:0] stuff bits R1 SET_CER_RES2 AKE Command:
Writes RES2 as response2 to RN2 in
AKE process
Refer Security Specification Version
2.00 for more details.
ACMD486 adtc [31:0] stuff bits R1 GET_CER_RES1 AKE Command:
Reads RES1 as response1 to RN1 in
AKE process.
Refer Security Specification Version
2.00 for more details.
ACMD496 ac [31:0] stuff bits R1b CHANGE_SECURE_A Protected Area Access Command:
REA
Change size of the protected area. Refer
Security Specification Version 2.00 for
more details.
ACMD516 adtc [31:0] stuff bits R1 SEND_SCR Reads the SD configuration register
(SCR).
1. CMD3 differs for MMC and SD cards. For MMC cards, it is referred to as SET_RELATIVE_ADDR, with a response type of
R1. For SD cards, it is referred to as SEND_RELATIVE_ADDR, with a response type of R6 (with RCA inside).
2. CMD6 differs completely between high speed MMC cards and high speed SD cards. Command SWITCH_FUNC is for
high speed SD cards.
3. Command SWITCH is for high speed MMC cards. The Index field can contain any value from 0-255, but only values 0-191
are valid. If the Index value is in the 192-255 range the card does not perform any modification and the SWITCH_ERROR
status bit in the EXT_CSD register is set. The Access Bits are shown in Table 2.
4. CMD8 for SD stands for SEND_IF_COND.
5. CMD8 for MMC stands for SEND_EXT_CSD.
6. ACMDs should be preceded with the APP_CMD command. (Commands listed are used for SD only, other SD commands
not listed are not supported on this module).
Table 22-12. EXT_CSD access modes
Bits Access name Operation
00 Command set The command set is changed according to the Cmd set field of the argument.
01 Set Bits The bits in the pointed byte are set, according to the 1 bit in the Value field.
10 Clear bits The bits in the pointed byte are cleared, according to the 1 bit in the Value field.
11 Write Byte The Value field is written into the pointed byte.
22.8 Software restrictions
This section covers software restrictions.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1144 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
22.8.1 Software polling procedure
For polling read or write, once the software begins a buffer read or write, it must access
the buffer data port register (DATPORT) exactly the number of times as watermark level
value set in the watermark level register (WML).
However, if the block size is not same as of the value in watermark level register (read
and write respectively), the software must access exactly the remaining number of words
at the end of each block. For example, for read operations, if the RD_WML is 4,
indicating the watermark level is 16 bytes, block size is 40 bytes, and the block count is
2, then the access times to data buffer port register for the burst sequence in the whole
transfer process must be 4, 4, 2 (for first block); 4, 4, 2 (for second block).
22.8.2 Suspend operation
In order to suspend the data transfer, the software must inform eSDHC that the suspend
command is successfully accepted.
To achieve this, after the suspend command is accepted by the SDIO card, software must
send another normal command marked as suspend command (CMDTYP bits set as "01")
to inform eSDHC that the transfer is suspended.
If software needs to resume the suspended transfer, it should read the value in BLKCNT
register to save the remained number of blocks before sending the normal command
marked as suspend, otherwise on sending such "suspend" command, eSDHC will regard
the current transfer a aborted and change the BLKCNT register to its original value,
instead of keeping the remaining number of blocks.
22.8.3 Data port access
Data port does not support parallel access.
For example, during an external DMA access, it is not allowed to write any data to the
data port by CPU; or during a CPU read operation, it is also prohibited to write any data
to the data port, by either CPU or external DMA. Otherwise, the data would be corrupted
inside the eSDHC buffer.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1145
Software restrictions
22.8.4 Multi-block read
For pre-defined multi-block read operation, that is, the number of blocks to read has been
defined by previous CMD23 for MMC, or pre-defined number of blocks in CMD53 for
SDIO/SDCombo, or SD security read commands, or whatever multi-block read without
abort command at card side; soft reset for data(SYSCTL[RSTD]) is required after the
transfer is complete to drive the internal state machine to idle mode.
22.8.5 ADMA address
For ADMA1/ADMA2 operation, the ADMA system address register (ADSADDR) and
address defined in the address field of the descriptor table should be 4-byte aligned.
22.8.6 Allowed operations after stop at block gap
Only one of these operations is allowed after stop at block gap event:
• Continue data transfer by setting SYSCTL[CREQ]
• Issue suspend command
• Abort data transfer by issued abort command
No other command can be issued until one of the operations listed above is performed.
22.8.7 SDIO card interrupt during soft reset
The host driver should disable SDIO card interrupts in IRQSTAT[CINT] before issuing
soft reset for data or all (generally used for error recovery) in the system control register
(SYSCTL), and enable it after error recovery sequence has been completed.
22.8.8 Soft reset for data not allowed when SD clock is disabled
Soft reset for data and CMD (SYSCTL[RSTD]/SYSCTL[RSTC]) should not be issued
when SD clock is disabled; that is, when SYSCTL[SDCLKEN] is cleared.
Instead, the host driver may issue soft reset for all (SYSCTL[RSTA]).
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1146 NXP Semiconductors
Chapter 22 Enhanced Secured Digital Host Controller
22.8.9 Data transfer with Auto CMD12 Enable
When Auto CMD12 is enabled for data transfer, it generates IRQSTAT[TC] for data
transfer completion but does not generate TC for Auto CMD12(command with busy).
Host Driver needs make sure that card has reached to “trans“ state before issuing any new
data command. CMD13(SEND_STATUS) could be sent to check the card status.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1147
Software restrictions
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1148 NXP Semiconductors
Chapter 23
FlexTimer Module (FTM)
23.1 The FlexTimer module as implemented on the chip
This section provides details about how the FlexTimer module is implemented on the
chip.
23.1.1 LS1043A FlexTimer module integration
The following table describes the FlexTimer module integration into this chip:
Table 23-1. FlexTimer module integration
Module Module Base address
FlexTimer Module 1 29D_0000
FlexTimer Module 2 29E_0000
FlexTimer Module 3 29F_0000
FlexTimer Module 4 2A0_0000
FlexTimer Module 5 2A1_0000
FlexTimer Module 6 2A2_0000
FlexTimer Module 7 2A3_0000
FlexTimer Module 8 2A4_0000
The remainder of this chapter refers to a single FlexTimer module. Notes are included to
indicate variations for multiple instantiations.
23.1.2 LS1043A FlexTimer signals
The following table lists the SoC signal names and their corresponding FlexTimer
module signal names used in this chapter:
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1149
The FlexTimer module as implemented on the chip
Table 23-2. FlexTimer signals
LS1043A signal name FlexTimer module signal
FTMn_EXTCLK EXTCLK
FTMn_CHn CHn
FTMn_FAULT FAULTj
FTMn_QD_PHA PHA
FTMn_QD_PHB PHB
23.1.3 LS1043A FlexTimer module special consideration
The FlexTimer module implements the following parameter settings in the chip:
Table 23-3. LS1043A FlexTimer parameter settings
FlexTimer parameters LS1043A parameter value
FTM1 FTM2 FTM3 FTM4 FTM5 FTM6 FTM7 FTM8
Number of channels 8 8 8 8 2 2 2 2
available at device I/O
level
Quadrature decoding Yes Yes Yes Yes No No No No
support
EXT_CLK support Yes Yes Yes Yes Yes Yes Yes No
Fixed frequency clock 32 KHz 32 KHz 32 KHz 32 KHz 32 KHz 32 KHz 32 KHz 32 KHz
support RTC RTC RTC RTC RTC RTC RTC RTC
System clock support Platform Platform Platform Platform Platform Platform Platform Platform
clock/1 clock/1 clock/1 clock/1 clock/1 clock/1 clock/1 clock/1
Stop mode support Yes. Refers to the LPM20 low power mode of the chip.
The table below shows the FlexTimer chaining for 32-bit counter. See FTM chain
configuration (SCFG_FTM_CHAIN_CONFIG) for more details.
Table 23-4. FlexTimer chaining for 32-bit counter
FlexTimer-A FlexTimer-B Control bit Control bit default value
FTM1 FTM5 SCFG_FTM_RESET[FTMCHN1] 0 = Chaining disabled
FTM2 FTM6 SCFG_FTM_RESET[FTMCHN2] 0 = Chaining disabled
FTM3 FTM7 SCFG_FTM_RESET[FTMCHN3] 0 = Chaining disabled
FTM4 FTM8 SCFG_FTM_RESET[FTMCHN4] 0 = Chaining disabled
It is possible to chain two FlexTimer modules to get a bigger 32-bit counter. This is
achieved by:
• Connecting CH7 output of FlexTimer-B to PHA input of FlexTimer-A.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1150 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
• Tieing PHB input of FlexTimer-A to one.
• Programming FlexTimer-A to be in quad-mode.
FlexTimer-A has [31:16] of the 32-bit counter while FlexTimer-B has [15:0] of the 32-bit
counter. The above table also shows how the chaining is implemented for FlexTimer-A
and FlexTimer-B.
23.2 Introduction
The FlexTimer module (FTM) is a two-to-eight channel timer that supports input capture,
output compare, and the generation of PWM signals to control electric motor and power
management applications. The FTM time reference is a 16-bit counter that can be used as
an unsigned or signed counter.
NOTE
The number of channels supported can vary for each instance of
the FTM module on a chip. See the chip-specific FTM
information to see how many channels are supported for each
module instance. For example, if a module instance supports
only six channels, references to channel numbers 6 and 7 do not
apply for that instance.
23.2.1 FlexTimer philosophy
The FlexTimer is built upon a simple timer, the Timer PWM Module – TPM, used for
many years on our HCS08 family of 8-bit microcontrollers. The FlexTimer extends the
functionality to meet the demands of motor control, digital lighting solutions, and power
conversion, while providing low cost and backwards compatibility with the TPM module.
Several key enhancements are made:
• Signed up counter
• Deadtime insertion hardware
• Fault control inputs
• Enhanced triggering functionality
• Initialization and polarity control
All of the features common with the TPM have fully backwards compatible register
assignments. The FlexTimer can also use code on the same core platform without change
to perform the same functions.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1151
Introduction
Motor control and power conversion features have been added through a dedicated set of
registers and defaults turn off all new features. The new features, such as hardware
deadtime insertion, polarity, fault control, and output forcing and masking, greatly reduce
loading on the execution software and are usually each controlled by a group of registers.
FlexTimer input triggers can be from comparators, ADC, or other submodules to initiate
timer functions automatically. These triggers can be linked in a variety of ways during
integration of the sub modules so please note the options available for used FlexTimer
configuration.
More than one FlexTimers may be synchronized to provide a larger timer with their
counters incrementing in unison, assuming the initialization, the input clocks, the initial
and final counting values are the same in each FlexTimer.
All main user access registers are buffered to ease the load on the executing software. A
number of trigger options exist to determine which registers are updated with this user
defined data.
23.2.2 Features
The FTM features include:
• FTM source clock is selectable.
• The source clock can be the system clock, the fixed frequency clock, or an
external clock
• Fixed frequency clock is an additional clock input to allow the selection of an on
chip clock source other than the system clock
• Selecting external clock connects FTM clock to a chip level input pin therefore
allowing to synchronize the FTM counter with an off chip clock source
• Prescaler divide-by 1, 2, 4, 8, 16, 32, 64, or 128
• 16-bit counter
• It can be a free-running counter or a counter with initial and final value
• The counting can be up or up-down
• Each channel can be configured for input capture, output compare, or edge-aligned
PWM mode
• In Input Capture mode:
• The capture can occur on rising edges, falling edges or both edges
• An input filter can be selected for some channels
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1152 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
• In Output Compare mode the output signal can be set, cleared, or toggled on match
• All channels can be configured for center-aligned PWM mode
• Each pair of channels can be combined to generate a PWM signal with independent
control of both edges of PWM signal
• The FTM channels can operate as pairs with equal outputs, pairs with
complementary outputs, or independent channels with independent outputs
• The deadtime insertion is available for each complementary pair
• Generation of match triggers
• Initialization trigger
• Software control of PWM outputs
• Up to 4 fault inputs for global fault control
• The polarity of each channel is configurable
• The generation of an interrupt per channel
• The generation of an interrupt when the counter overflows
• The generation of an interrupt when the fault condition is detected
• Synchronized loading of write buffered FTM registers
• Write protection for critical registers
• Backwards compatible with TPM
• Testing of input captures for a stuck at zero and one conditions
• Dual edge capture for pulse and period width measurement
• Quadrature decoder with input filters, relative position counting, and interrupt on
position count or capture of position count on external event
23.2.3 Modes of operation
When the chip is in an active mode, the FTM temporarily suspends all counting until the
chip returns to normal user operating mode. During Stop mode, all FTM input clocks are
stopped, so the FTM is effectively disabled until clocks resume. During Wait mode, the
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1153
Introduction
FTM continues to operate normally. If the FTM does not need to produce a real time
reference or provide the interrupt sources needed to wake the chip from Wait mode, the
power can then be saved by disabling FTM functions before entering Wait mode.
23.2.4 Block diagram
The FTM uses one input/output (I/O) pin per channel, CHn (FTM channel (n)) where n is
the channel number (0–7).
The following figure shows the FTM structure. The central component of the FTM is the
16-bit counter with programmable initial and final values and its counting can be up or
up-down.
NOTE
The number of channels supported can vary for each instance of
the FTM module on a chip. See the chip-specific FTM
information to see how many channels are supported for each
module instance. For example, if a module instance supports
only six channels, references to channel numbers 6 and 7 do not
apply for that instance.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1154 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
CLKS
FTMEN
QUADEN
no clock selected
(FTM counter disable) PS
system clock
fixed frequency clock
external clock prescaler
synchronizer
(1, 2, 4, 8, 16, 32, 64 or 128)
phase A Quadrature
phase B decoder
QUADEN
CPWMS
CAPTEST INITTRIGEN initialization
CNTIN trigger
FAULTM[1:0]
FTM counter TOIE timer overflow
MOD TOF interrupt
FFVAL[3:0]
FAULTIE TOFDIR
FAULTIN
FAULTnEN*
FAULTF
FFLTRnEN* QUADIR
FAULTFn*
fault control fault interrupt
fault input n* *where n = 3, 2, 1, 0
fault condition
DECAPEN pair channels 0 - channels 0 and 1
COMBINE0
CPWMS
MS0B:MS0A
ELS0B:ELS0A CH0IE channel 0 CH0TRIG channel 0
dual edge capture interrupt match trigger
CH0F
mode logic
channel 0
input input capture output modes logic
mode logic C0V channel 0
(generation of channels 0 and 1 outputs signals in output
compare, EPWM, CPWM and combine modes according to output signal
initialization, complementary mode, inverting, software output channel 1
input capture C1V control, deadtime insertion, output mask, fault control output signal
channel 1 mode logic and polarity control)
input
DECAPEN
COMBINE0 CH1F channel 1
interrupt channel 1
CPWMS CH1IE CH1TRIG match trigger
MS1B:MS1A
ELS1B:ELS1A
DECAPEN pair channels 3 - channels 6 and 7
COMBINE3
CPWMS
MS6B:MS6A
ELS6B:ELS6A CH6IE channel 6 CH6TRIG channel 6
dual edge capture CH6F
interrupt match trigger
mode logic
channel 6
input input capture output modes logic
mode logic C6V channel 6
(generation of channels 6 and 7 outputs signals in output
compare, EPWM, CPWM and combine modes according to output signal
initialization, complementary mode, inverting, software output channel 7
input capture C7V control, deadtime insertion, output mask, fault control output signal
channel 7 mode logic and polarity control)
input
DECAPEN
COMBINE3 CH7F channel 7 channel 7
CPWMS CH7IE
interrupt CH7TRIG match trigger
MS7B:MS7A
ELS7B:ELS7A
Figure 23-1. FTM block diagram
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1155
FTM signal descriptions
23.3 FTM signal descriptions
Table 23-5 shows the user-accessible signals for the FTM.
Table 23-5. FTM signal descriptions
Signal Description I/O Function
EXTCLK External clock. FTM external I The external clock input signal is used as the FTM counter
clock can be selected to drive clock if selected by CLKS[1:0] bits in the SC register. This
the FTM counter. clock signal must not exceed 1/4 of system clock frequency.
The FTM counter prescaler selection and settings are also
used when an external clock is selected.
CHn FTM channel (n), where n can I/O Each FTM channel can be configured to operate either as
be 7-0 input or output. The direction associated with each channel,
input or output, is selected according to the mode assigned
for that channel.
FAULTj Fault input (j), where j can be I The fault input signals are used to control the CHn channel
3-0 output state. If a fault is detected, the FAULTj signal is
asserted and the channel output is put in a safe state. The
behavior of the fault logic is defined by the FAULTM[1:0]
control bits in the MODE register and FAULTEN bit in the
COMBINEm register. Note that each FAULTj input may affect
all channels selectively since FAULTM[1:0] and FAULTEN
control bits are defined for each pair of channels. Because
there are several FAULTj inputs, maximum of 4 for the FTM
module, each one of these inputs is activated by the
FAULTjEN bit in the FLTCTRL register.
PHA Quadrature decoder phase A I The quadrature decoder phase A input is used as the
input. Input pin associated Quadrature Decoder mode is selected. The phase A input
with quadrature decoder signal is one of the signals that control the FTM counter
phase A. increment or decrement in the Quadrature Decoder mode.
PHB Quadrature decoder phase B I The quadrature decoder phase B input is used as the
input. Input pin associated Quadrature Decoder mode is selected. The phase B input
with quadrature decoder signal is one of the signals that control the FTM counter
phase B. increment or decrement in the Quadrature Decoder mode.
23.4 Memory map and register definition
23.4.1 Memory map
This section presents a high-level summary of the FTM registers and how they are
mapped.
The registers and bits of an unavailable function in the FTM remain in the memory map
and in the reset value, but they have no active function.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1156 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
Note
Do not write in the region from the CNTIN register through the
PWMLOAD register when FTMEN = 0.
NOTE
The number of channels supported can vary for each instance of
the FTM module on a chip. See the chip-specific FTM
information to see how many channels are supported for each
module instance. For example, if a module instance supports
only six channels, references to channel numbers 6 and 7 do not
apply for that instance.
23.4.2 Register descriptions
Accesses to reserved addresses result in transfer errors. Registers for absent channels are
considered reserved.
FTM memory map
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
29D_0000 Status And Control (FTM1_SC) 32 R/W 0000_0000h 23.4.3/1169
29D_0004 Counter (FTM1_CNT) 32 R/W 0000_0000h 23.4.4/1170
29D_0008 Modulo (FTM1_MOD) 32 R/W 0000_0000h 23.4.5/1171
29D_000C Channel (n) Status And Control (FTM1_C0SC) 32 R/W 0000_0000h 23.4.6/1172
29D_0010 Channel (n) Value (FTM1_C0V) 32 R/W 0000_0000h 23.4.7/1174
29D_0014 Channel (n) Status And Control (FTM1_C1SC) 32 R/W 0000_0000h 23.4.6/1172
29D_0018 Channel (n) Value (FTM1_C1V) 32 R/W 0000_0000h 23.4.7/1174
29D_001C Channel (n) Status And Control (FTM1_C2SC) 32 R/W 0000_0000h 23.4.6/1172
29D_0020 Channel (n) Value (FTM1_C2V) 32 R/W 0000_0000h 23.4.7/1174
29D_0024 Channel (n) Status And Control (FTM1_C3SC) 32 R/W 0000_0000h 23.4.6/1172
29D_0028 Channel (n) Value (FTM1_C3V) 32 R/W 0000_0000h 23.4.7/1174
29D_002C Channel (n) Status And Control (FTM1_C4SC) 32 R/W 0000_0000h 23.4.6/1172
29D_0030 Channel (n) Value (FTM1_C4V) 32 R/W 0000_0000h 23.4.7/1174
29D_0034 Channel (n) Status And Control (FTM1_C5SC) 32 R/W 0000_0000h 23.4.6/1172
29D_0038 Channel (n) Value (FTM1_C5V) 32 R/W 0000_0000h 23.4.7/1174
29D_003C Channel (n) Status And Control (FTM1_C6SC) 32 R/W 0000_0000h 23.4.6/1172
29D_0040 Channel (n) Value (FTM1_C6V) 32 R/W 0000_0000h 23.4.7/1174
29D_0044 Channel (n) Status And Control (FTM1_C7SC) 32 R/W 0000_0000h 23.4.6/1172
29D_0048 Channel (n) Value (FTM1_C7V) 32 R/W 0000_0000h 23.4.7/1174
29D_004C Counter Initial Value (FTM1_CNTIN) 32 R/W 0000_0000h 23.4.8/1175
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1157
Memory map and register definition
FTM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
29D_0050 Capture And Compare Status (FTM1_STATUS) 32 R/W 0000_0000h 23.4.9/1175
23.4.10/
29D_0054 Features Mode Selection (FTM1_MODE) 32 R/W 0000_0004h
1177
23.4.11/
29D_0058 Synchronization (FTM1_SYNC) 32 R/W 0000_0000h
1179
23.4.12/
29D_005C Initial State For Channels Output (FTM1_OUTINIT) 32 R/W 0000_0000h
1182
23.4.13/
29D_0060 Output Mask (FTM1_OUTMASK) 32 R/W 0000_0000h
1183
23.4.14/
29D_0064 Function For Linked Channels (FTM1_COMBINE) 32 R/W 0000_0000h
1185
23.4.15/
29D_0068 Deadtime Insertion Control (FTM1_DEADTIME) 32 R/W 0000_0000h
1190
23.4.16/
29D_006C FTM External Trigger (FTM1_EXTTRIG) 32 R/W 0000_0000h
1191
23.4.17/
29D_0070 Channels Polarity (FTM1_POL) 32 R/W 0000_0000h
1193
23.4.18/
29D_0074 Fault Mode Status (FTM1_FMS) 32 R/W 0000_0000h
1195
23.4.19/
29D_0078 Input Capture Filter Control (FTM1_FILTER) 32 R/W 0000_0000h
1197
23.4.20/
29D_007C Fault Control (FTM1_FLTCTRL) 32 R/W 0000_0000h
1198
23.4.21/
29D_0080 Quadrature Decoder Control And Status (FTM1_QDCTRL) 32 R/W 0000_0000h
1200
23.4.22/
29D_0084 Configuration (FTM1_CONF) 32 R/W 0000_0000h
1202
23.4.23/
29D_0088 FTM Fault Input Polarity (FTM1_FLTPOL) 32 R/W 0000_0000h
1203
23.4.24/
29D_008C Synchronization Configuration (FTM1_SYNCONF) 32 R/W 0000_0000h
1205
23.4.25/
29D_0090 FTM Inverting Control (FTM1_INVCTRL) 32 R/W 0000_0000h
1207
23.4.26/
29D_0094 FTM Software Output Control (FTM1_SWOCTRL) 32 R/W 0000_0000h
1208
23.4.27/
29D_0098 FTM PWM Load (FTM1_PWMLOAD) 32 R/W 0000_0000h
1210
29E_0000 Status And Control (FTM2_SC) 32 R/W 0000_0000h 23.4.3/1169
29E_0004 Counter (FTM2_CNT) 32 R/W 0000_0000h 23.4.4/1170
29E_0008 Modulo (FTM2_MOD) 32 R/W 0000_0000h 23.4.5/1171
29E_000C Channel (n) Status And Control (FTM2_C0SC) 32 R/W 0000_0000h 23.4.6/1172
29E_0010 Channel (n) Value (FTM2_C0V) 32 R/W 0000_0000h 23.4.7/1174
29E_0014 Channel (n) Status And Control (FTM2_C1SC) 32 R/W 0000_0000h 23.4.6/1172
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1158 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
FTM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
29E_0018 Channel (n) Value (FTM2_C1V) 32 R/W 0000_0000h 23.4.7/1174
29E_001C Channel (n) Status And Control (FTM2_C2SC) 32 R/W 0000_0000h 23.4.6/1172
29E_0020 Channel (n) Value (FTM2_C2V) 32 R/W 0000_0000h 23.4.7/1174
29E_0024 Channel (n) Status And Control (FTM2_C3SC) 32 R/W 0000_0000h 23.4.6/1172
29E_0028 Channel (n) Value (FTM2_C3V) 32 R/W 0000_0000h 23.4.7/1174
29E_002C Channel (n) Status And Control (FTM2_C4SC) 32 R/W 0000_0000h 23.4.6/1172
29E_0030 Channel (n) Value (FTM2_C4V) 32 R/W 0000_0000h 23.4.7/1174
29E_0034 Channel (n) Status And Control (FTM2_C5SC) 32 R/W 0000_0000h 23.4.6/1172
29E_0038 Channel (n) Value (FTM2_C5V) 32 R/W 0000_0000h 23.4.7/1174
29E_003C Channel (n) Status And Control (FTM2_C6SC) 32 R/W 0000_0000h 23.4.6/1172
29E_0040 Channel (n) Value (FTM2_C6V) 32 R/W 0000_0000h 23.4.7/1174
29E_0044 Channel (n) Status And Control (FTM2_C7SC) 32 R/W 0000_0000h 23.4.6/1172
29E_0048 Channel (n) Value (FTM2_C7V) 32 R/W 0000_0000h 23.4.7/1174
29E_004C Counter Initial Value (FTM2_CNTIN) 32 R/W 0000_0000h 23.4.8/1175
29E_0050 Capture And Compare Status (FTM2_STATUS) 32 R/W 0000_0000h 23.4.9/1175
23.4.10/
29E_0054 Features Mode Selection (FTM2_MODE) 32 R/W 0000_0004h
1177
23.4.11/
29E_0058 Synchronization (FTM2_SYNC) 32 R/W 0000_0000h
1179
23.4.12/
29E_005C Initial State For Channels Output (FTM2_OUTINIT) 32 R/W 0000_0000h
1182
23.4.13/
29E_0060 Output Mask (FTM2_OUTMASK) 32 R/W 0000_0000h
1183
23.4.14/
29E_0064 Function For Linked Channels (FTM2_COMBINE) 32 R/W 0000_0000h
1185
23.4.15/
29E_0068 Deadtime Insertion Control (FTM2_DEADTIME) 32 R/W 0000_0000h
1190
23.4.16/
29E_006C FTM External Trigger (FTM2_EXTTRIG) 32 R/W 0000_0000h
1191
23.4.17/
29E_0070 Channels Polarity (FTM2_POL) 32 R/W 0000_0000h
1193
23.4.18/
29E_0074 Fault Mode Status (FTM2_FMS) 32 R/W 0000_0000h
1195
23.4.19/
29E_0078 Input Capture Filter Control (FTM2_FILTER) 32 R/W 0000_0000h
1197
23.4.20/
29E_007C Fault Control (FTM2_FLTCTRL) 32 R/W 0000_0000h
1198
23.4.21/
29E_0080 Quadrature Decoder Control And Status (FTM2_QDCTRL) 32 R/W 0000_0000h
1200
23.4.22/
29E_0084 Configuration (FTM2_CONF) 32 R/W 0000_0000h
1202
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1159
Memory map and register definition
FTM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
23.4.23/
29E_0088 FTM Fault Input Polarity (FTM2_FLTPOL) 32 R/W 0000_0000h
1203
23.4.24/
29E_008C Synchronization Configuration (FTM2_SYNCONF) 32 R/W 0000_0000h
1205
23.4.25/
29E_0090 FTM Inverting Control (FTM2_INVCTRL) 32 R/W 0000_0000h
1207
23.4.26/
29E_0094 FTM Software Output Control (FTM2_SWOCTRL) 32 R/W 0000_0000h
1208
23.4.27/
29E_0098 FTM PWM Load (FTM2_PWMLOAD) 32 R/W 0000_0000h
1210
29F_0000 Status And Control (FTM3_SC) 32 R/W 0000_0000h 23.4.3/1169
29F_0004 Counter (FTM3_CNT) 32 R/W 0000_0000h 23.4.4/1170
29F_0008 Modulo (FTM3_MOD) 32 R/W 0000_0000h 23.4.5/1171
29F_000C Channel (n) Status And Control (FTM3_C0SC) 32 R/W 0000_0000h 23.4.6/1172
29F_0010 Channel (n) Value (FTM3_C0V) 32 R/W 0000_0000h 23.4.7/1174
29F_0014 Channel (n) Status And Control (FTM3_C1SC) 32 R/W 0000_0000h 23.4.6/1172
29F_0018 Channel (n) Value (FTM3_C1V) 32 R/W 0000_0000h 23.4.7/1174
29F_001C Channel (n) Status And Control (FTM3_C2SC) 32 R/W 0000_0000h 23.4.6/1172
29F_0020 Channel (n) Value (FTM3_C2V) 32 R/W 0000_0000h 23.4.7/1174
29F_0024 Channel (n) Status And Control (FTM3_C3SC) 32 R/W 0000_0000h 23.4.6/1172
29F_0028 Channel (n) Value (FTM3_C3V) 32 R/W 0000_0000h 23.4.7/1174
29F_002C Channel (n) Status And Control (FTM3_C4SC) 32 R/W 0000_0000h 23.4.6/1172
29F_0030 Channel (n) Value (FTM3_C4V) 32 R/W 0000_0000h 23.4.7/1174
29F_0034 Channel (n) Status And Control (FTM3_C5SC) 32 R/W 0000_0000h 23.4.6/1172
29F_0038 Channel (n) Value (FTM3_C5V) 32 R/W 0000_0000h 23.4.7/1174
29F_003C Channel (n) Status And Control (FTM3_C6SC) 32 R/W 0000_0000h 23.4.6/1172
29F_0040 Channel (n) Value (FTM3_C6V) 32 R/W 0000_0000h 23.4.7/1174
29F_0044 Channel (n) Status And Control (FTM3_C7SC) 32 R/W 0000_0000h 23.4.6/1172
29F_0048 Channel (n) Value (FTM3_C7V) 32 R/W 0000_0000h 23.4.7/1174
29F_004C Counter Initial Value (FTM3_CNTIN) 32 R/W 0000_0000h 23.4.8/1175
29F_0050 Capture And Compare Status (FTM3_STATUS) 32 R/W 0000_0000h 23.4.9/1175
23.4.10/
29F_0054 Features Mode Selection (FTM3_MODE) 32 R/W 0000_0004h
1177
23.4.11/
29F_0058 Synchronization (FTM3_SYNC) 32 R/W 0000_0000h
1179
23.4.12/
29F_005C Initial State For Channels Output (FTM3_OUTINIT) 32 R/W 0000_0000h
1182
23.4.13/
29F_0060 Output Mask (FTM3_OUTMASK) 32 R/W 0000_0000h
1183
23.4.14/
29F_0064 Function For Linked Channels (FTM3_COMBINE) 32 R/W 0000_0000h
1185
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1160 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
FTM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
23.4.15/
29F_0068 Deadtime Insertion Control (FTM3_DEADTIME) 32 R/W 0000_0000h
1190
23.4.16/
29F_006C FTM External Trigger (FTM3_EXTTRIG) 32 R/W 0000_0000h
1191
23.4.17/
29F_0070 Channels Polarity (FTM3_POL) 32 R/W 0000_0000h
1193
23.4.18/
29F_0074 Fault Mode Status (FTM3_FMS) 32 R/W 0000_0000h
1195
23.4.19/
29F_0078 Input Capture Filter Control (FTM3_FILTER) 32 R/W 0000_0000h
1197
23.4.20/
29F_007C Fault Control (FTM3_FLTCTRL) 32 R/W 0000_0000h
1198
23.4.21/
29F_0080 Quadrature Decoder Control And Status (FTM3_QDCTRL) 32 R/W 0000_0000h
1200
23.4.22/
29F_0084 Configuration (FTM3_CONF) 32 R/W 0000_0000h
1202
23.4.23/
29F_0088 FTM Fault Input Polarity (FTM3_FLTPOL) 32 R/W 0000_0000h
1203
23.4.24/
29F_008C Synchronization Configuration (FTM3_SYNCONF) 32 R/W 0000_0000h
1205
23.4.25/
29F_0090 FTM Inverting Control (FTM3_INVCTRL) 32 R/W 0000_0000h
1207
23.4.26/
29F_0094 FTM Software Output Control (FTM3_SWOCTRL) 32 R/W 0000_0000h
1208
23.4.27/
29F_0098 FTM PWM Load (FTM3_PWMLOAD) 32 R/W 0000_0000h
1210
2A0_0000 Status And Control (FTM4_SC) 32 R/W 0000_0000h 23.4.3/1169
2A0_0004 Counter (FTM4_CNT) 32 R/W 0000_0000h 23.4.4/1170
2A0_0008 Modulo (FTM4_MOD) 32 R/W 0000_0000h 23.4.5/1171
2A0_000C Channel (n) Status And Control (FTM4_C0SC) 32 R/W 0000_0000h 23.4.6/1172
2A0_0010 Channel (n) Value (FTM4_C0V) 32 R/W 0000_0000h 23.4.7/1174
2A0_0014 Channel (n) Status And Control (FTM4_C1SC) 32 R/W 0000_0000h 23.4.6/1172
2A0_0018 Channel (n) Value (FTM4_C1V) 32 R/W 0000_0000h 23.4.7/1174
2A0_001C Channel (n) Status And Control (FTM4_C2SC) 32 R/W 0000_0000h 23.4.6/1172
2A0_0020 Channel (n) Value (FTM4_C2V) 32 R/W 0000_0000h 23.4.7/1174
2A0_0024 Channel (n) Status And Control (FTM4_C3SC) 32 R/W 0000_0000h 23.4.6/1172
2A0_0028 Channel (n) Value (FTM4_C3V) 32 R/W 0000_0000h 23.4.7/1174
2A0_002C Channel (n) Status And Control (FTM4_C4SC) 32 R/W 0000_0000h 23.4.6/1172
2A0_0030 Channel (n) Value (FTM4_C4V) 32 R/W 0000_0000h 23.4.7/1174
2A0_0034 Channel (n) Status And Control (FTM4_C5SC) 32 R/W 0000_0000h 23.4.6/1172
2A0_0038 Channel (n) Value (FTM4_C5V) 32 R/W 0000_0000h 23.4.7/1174
2A0_003C Channel (n) Status And Control (FTM4_C6SC) 32 R/W 0000_0000h 23.4.6/1172
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1161
Memory map and register definition
FTM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
2A0_0040 Channel (n) Value (FTM4_C6V) 32 R/W 0000_0000h 23.4.7/1174
2A0_0044 Channel (n) Status And Control (FTM4_C7SC) 32 R/W 0000_0000h 23.4.6/1172
2A0_0048 Channel (n) Value (FTM4_C7V) 32 R/W 0000_0000h 23.4.7/1174
2A0_004C Counter Initial Value (FTM4_CNTIN) 32 R/W 0000_0000h 23.4.8/1175
2A0_0050 Capture And Compare Status (FTM4_STATUS) 32 R/W 0000_0000h 23.4.9/1175
23.4.10/
2A0_0054 Features Mode Selection (FTM4_MODE) 32 R/W 0000_0004h
1177
23.4.11/
2A0_0058 Synchronization (FTM4_SYNC) 32 R/W 0000_0000h
1179
23.4.12/
2A0_005C Initial State For Channels Output (FTM4_OUTINIT) 32 R/W 0000_0000h
1182
23.4.13/
2A0_0060 Output Mask (FTM4_OUTMASK) 32 R/W 0000_0000h
1183
23.4.14/
2A0_0064 Function For Linked Channels (FTM4_COMBINE) 32 R/W 0000_0000h
1185
23.4.15/
2A0_0068 Deadtime Insertion Control (FTM4_DEADTIME) 32 R/W 0000_0000h
1190
23.4.16/
2A0_006C FTM External Trigger (FTM4_EXTTRIG) 32 R/W 0000_0000h
1191
23.4.17/
2A0_0070 Channels Polarity (FTM4_POL) 32 R/W 0000_0000h
1193
23.4.18/
2A0_0074 Fault Mode Status (FTM4_FMS) 32 R/W 0000_0000h
1195
23.4.19/
2A0_0078 Input Capture Filter Control (FTM4_FILTER) 32 R/W 0000_0000h
1197
23.4.20/
2A0_007C Fault Control (FTM4_FLTCTRL) 32 R/W 0000_0000h
1198
23.4.21/
2A0_0080 Quadrature Decoder Control And Status (FTM4_QDCTRL) 32 R/W 0000_0000h
1200
23.4.22/
2A0_0084 Configuration (FTM4_CONF) 32 R/W 0000_0000h
1202
23.4.23/
2A0_0088 FTM Fault Input Polarity (FTM4_FLTPOL) 32 R/W 0000_0000h
1203
23.4.24/
2A0_008C Synchronization Configuration (FTM4_SYNCONF) 32 R/W 0000_0000h
1205
23.4.25/
2A0_0090 FTM Inverting Control (FTM4_INVCTRL) 32 R/W 0000_0000h
1207
23.4.26/
2A0_0094 FTM Software Output Control (FTM4_SWOCTRL) 32 R/W 0000_0000h
1208
23.4.27/
2A0_0098 FTM PWM Load (FTM4_PWMLOAD) 32 R/W 0000_0000h
1210
2A1_0000 Status And Control (FTM5_SC) 32 R/W 0000_0000h 23.4.3/1169
2A1_0004 Counter (FTM5_CNT) 32 R/W 0000_0000h 23.4.4/1170
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1162 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
FTM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
2A1_0008 Modulo (FTM5_MOD) 32 R/W 0000_0000h 23.4.5/1171
2A1_000C Channel (n) Status And Control (FTM5_C0SC) 32 R/W 0000_0000h 23.4.6/1172
2A1_0010 Channel (n) Value (FTM5_C0V) 32 R/W 0000_0000h 23.4.7/1174
2A1_0014 Channel (n) Status And Control (FTM5_C1SC) 32 R/W 0000_0000h 23.4.6/1172
2A1_0018 Channel (n) Value (FTM5_C1V) 32 R/W 0000_0000h 23.4.7/1174
2A1_001C Channel (n) Status And Control (FTM5_C2SC) 32 R/W 0000_0000h 23.4.6/1172
2A1_0020 Channel (n) Value (FTM5_C2V) 32 R/W 0000_0000h 23.4.7/1174
2A1_0024 Channel (n) Status And Control (FTM5_C3SC) 32 R/W 0000_0000h 23.4.6/1172
2A1_0028 Channel (n) Value (FTM5_C3V) 32 R/W 0000_0000h 23.4.7/1174
2A1_002C Channel (n) Status And Control (FTM5_C4SC) 32 R/W 0000_0000h 23.4.6/1172
2A1_0030 Channel (n) Value (FTM5_C4V) 32 R/W 0000_0000h 23.4.7/1174
2A1_0034 Channel (n) Status And Control (FTM5_C5SC) 32 R/W 0000_0000h 23.4.6/1172
2A1_0038 Channel (n) Value (FTM5_C5V) 32 R/W 0000_0000h 23.4.7/1174
2A1_003C Channel (n) Status And Control (FTM5_C6SC) 32 R/W 0000_0000h 23.4.6/1172
2A1_0040 Channel (n) Value (FTM5_C6V) 32 R/W 0000_0000h 23.4.7/1174
2A1_0044 Channel (n) Status And Control (FTM5_C7SC) 32 R/W 0000_0000h 23.4.6/1172
2A1_0048 Channel (n) Value (FTM5_C7V) 32 R/W 0000_0000h 23.4.7/1174
2A1_004C Counter Initial Value (FTM5_CNTIN) 32 R/W 0000_0000h 23.4.8/1175
2A1_0050 Capture And Compare Status (FTM5_STATUS) 32 R/W 0000_0000h 23.4.9/1175
23.4.10/
2A1_0054 Features Mode Selection (FTM5_MODE) 32 R/W 0000_0004h
1177
23.4.11/
2A1_0058 Synchronization (FTM5_SYNC) 32 R/W 0000_0000h
1179
23.4.12/
2A1_005C Initial State For Channels Output (FTM5_OUTINIT) 32 R/W 0000_0000h
1182
23.4.13/
2A1_0060 Output Mask (FTM5_OUTMASK) 32 R/W 0000_0000h
1183
23.4.14/
2A1_0064 Function For Linked Channels (FTM5_COMBINE) 32 R/W 0000_0000h
1185
23.4.15/
2A1_0068 Deadtime Insertion Control (FTM5_DEADTIME) 32 R/W 0000_0000h
1190
23.4.16/
2A1_006C FTM External Trigger (FTM5_EXTTRIG) 32 R/W 0000_0000h
1191
23.4.17/
2A1_0070 Channels Polarity (FTM5_POL) 32 R/W 0000_0000h
1193
23.4.18/
2A1_0074 Fault Mode Status (FTM5_FMS) 32 R/W 0000_0000h
1195
23.4.19/
2A1_0078 Input Capture Filter Control (FTM5_FILTER) 32 R/W 0000_0000h
1197
23.4.20/
2A1_007C Fault Control (FTM5_FLTCTRL) 32 R/W 0000_0000h
1198
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1163
Memory map and register definition
FTM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
23.4.21/
2A1_0080 Quadrature Decoder Control And Status (FTM5_QDCTRL) 32 R/W 0000_0000h
1200
23.4.22/
2A1_0084 Configuration (FTM5_CONF) 32 R/W 0000_0000h
1202
23.4.23/
2A1_0088 FTM Fault Input Polarity (FTM5_FLTPOL) 32 R/W 0000_0000h
1203
23.4.24/
2A1_008C Synchronization Configuration (FTM5_SYNCONF) 32 R/W 0000_0000h
1205
23.4.25/
2A1_0090 FTM Inverting Control (FTM5_INVCTRL) 32 R/W 0000_0000h
1207
23.4.26/
2A1_0094 FTM Software Output Control (FTM5_SWOCTRL) 32 R/W 0000_0000h
1208
23.4.27/
2A1_0098 FTM PWM Load (FTM5_PWMLOAD) 32 R/W 0000_0000h
1210
2A2_0000 Status And Control (FTM6_SC) 32 R/W 0000_0000h 23.4.3/1169
2A2_0004 Counter (FTM6_CNT) 32 R/W 0000_0000h 23.4.4/1170
2A2_0008 Modulo (FTM6_MOD) 32 R/W 0000_0000h 23.4.5/1171
2A2_000C Channel (n) Status And Control (FTM6_C0SC) 32 R/W 0000_0000h 23.4.6/1172
2A2_0010 Channel (n) Value (FTM6_C0V) 32 R/W 0000_0000h 23.4.7/1174
2A2_0014 Channel (n) Status And Control (FTM6_C1SC) 32 R/W 0000_0000h 23.4.6/1172
2A2_0018 Channel (n) Value (FTM6_C1V) 32 R/W 0000_0000h 23.4.7/1174
2A2_001C Channel (n) Status And Control (FTM6_C2SC) 32 R/W 0000_0000h 23.4.6/1172
2A2_0020 Channel (n) Value (FTM6_C2V) 32 R/W 0000_0000h 23.4.7/1174
2A2_0024 Channel (n) Status And Control (FTM6_C3SC) 32 R/W 0000_0000h 23.4.6/1172
2A2_0028 Channel (n) Value (FTM6_C3V) 32 R/W 0000_0000h 23.4.7/1174
2A2_002C Channel (n) Status And Control (FTM6_C4SC) 32 R/W 0000_0000h 23.4.6/1172
2A2_0030 Channel (n) Value (FTM6_C4V) 32 R/W 0000_0000h 23.4.7/1174
2A2_0034 Channel (n) Status And Control (FTM6_C5SC) 32 R/W 0000_0000h 23.4.6/1172
2A2_0038 Channel (n) Value (FTM6_C5V) 32 R/W 0000_0000h 23.4.7/1174
2A2_003C Channel (n) Status And Control (FTM6_C6SC) 32 R/W 0000_0000h 23.4.6/1172
2A2_0040 Channel (n) Value (FTM6_C6V) 32 R/W 0000_0000h 23.4.7/1174
2A2_0044 Channel (n) Status And Control (FTM6_C7SC) 32 R/W 0000_0000h 23.4.6/1172
2A2_0048 Channel (n) Value (FTM6_C7V) 32 R/W 0000_0000h 23.4.7/1174
2A2_004C Counter Initial Value (FTM6_CNTIN) 32 R/W 0000_0000h 23.4.8/1175
2A2_0050 Capture And Compare Status (FTM6_STATUS) 32 R/W 0000_0000h 23.4.9/1175
23.4.10/
2A2_0054 Features Mode Selection (FTM6_MODE) 32 R/W 0000_0004h
1177
23.4.11/
2A2_0058 Synchronization (FTM6_SYNC) 32 R/W 0000_0000h
1179
23.4.12/
2A2_005C Initial State For Channels Output (FTM6_OUTINIT) 32 R/W 0000_0000h
1182
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1164 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
FTM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
23.4.13/
2A2_0060 Output Mask (FTM6_OUTMASK) 32 R/W 0000_0000h
1183
23.4.14/
2A2_0064 Function For Linked Channels (FTM6_COMBINE) 32 R/W 0000_0000h
1185
23.4.15/
2A2_0068 Deadtime Insertion Control (FTM6_DEADTIME) 32 R/W 0000_0000h
1190
23.4.16/
2A2_006C FTM External Trigger (FTM6_EXTTRIG) 32 R/W 0000_0000h
1191
23.4.17/
2A2_0070 Channels Polarity (FTM6_POL) 32 R/W 0000_0000h
1193
23.4.18/
2A2_0074 Fault Mode Status (FTM6_FMS) 32 R/W 0000_0000h
1195
23.4.19/
2A2_0078 Input Capture Filter Control (FTM6_FILTER) 32 R/W 0000_0000h
1197
23.4.20/
2A2_007C Fault Control (FTM6_FLTCTRL) 32 R/W 0000_0000h
1198
23.4.21/
2A2_0080 Quadrature Decoder Control And Status (FTM6_QDCTRL) 32 R/W 0000_0000h
1200
23.4.22/
2A2_0084 Configuration (FTM6_CONF) 32 R/W 0000_0000h
1202
23.4.23/
2A2_0088 FTM Fault Input Polarity (FTM6_FLTPOL) 32 R/W 0000_0000h
1203
23.4.24/
2A2_008C Synchronization Configuration (FTM6_SYNCONF) 32 R/W 0000_0000h
1205
23.4.25/
2A2_0090 FTM Inverting Control (FTM6_INVCTRL) 32 R/W 0000_0000h
1207
23.4.26/
2A2_0094 FTM Software Output Control (FTM6_SWOCTRL) 32 R/W 0000_0000h
1208
23.4.27/
2A2_0098 FTM PWM Load (FTM6_PWMLOAD) 32 R/W 0000_0000h
1210
2A3_0000 Status And Control (FTM7_SC) 32 R/W 0000_0000h 23.4.3/1169
2A3_0004 Counter (FTM7_CNT) 32 R/W 0000_0000h 23.4.4/1170
2A3_0008 Modulo (FTM7_MOD) 32 R/W 0000_0000h 23.4.5/1171
2A3_000C Channel (n) Status And Control (FTM7_C0SC) 32 R/W 0000_0000h 23.4.6/1172
2A3_0010 Channel (n) Value (FTM7_C0V) 32 R/W 0000_0000h 23.4.7/1174
2A3_0014 Channel (n) Status And Control (FTM7_C1SC) 32 R/W 0000_0000h 23.4.6/1172
2A3_0018 Channel (n) Value (FTM7_C1V) 32 R/W 0000_0000h 23.4.7/1174
2A3_001C Channel (n) Status And Control (FTM7_C2SC) 32 R/W 0000_0000h 23.4.6/1172
2A3_0020 Channel (n) Value (FTM7_C2V) 32 R/W 0000_0000h 23.4.7/1174
2A3_0024 Channel (n) Status And Control (FTM7_C3SC) 32 R/W 0000_0000h 23.4.6/1172
2A3_0028 Channel (n) Value (FTM7_C3V) 32 R/W 0000_0000h 23.4.7/1174
2A3_002C Channel (n) Status And Control (FTM7_C4SC) 32 R/W 0000_0000h 23.4.6/1172
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1165
Memory map and register definition
FTM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
2A3_0030 Channel (n) Value (FTM7_C4V) 32 R/W 0000_0000h 23.4.7/1174
2A3_0034 Channel (n) Status And Control (FTM7_C5SC) 32 R/W 0000_0000h 23.4.6/1172
2A3_0038 Channel (n) Value (FTM7_C5V) 32 R/W 0000_0000h 23.4.7/1174
2A3_003C Channel (n) Status And Control (FTM7_C6SC) 32 R/W 0000_0000h 23.4.6/1172
2A3_0040 Channel (n) Value (FTM7_C6V) 32 R/W 0000_0000h 23.4.7/1174
2A3_0044 Channel (n) Status And Control (FTM7_C7SC) 32 R/W 0000_0000h 23.4.6/1172
2A3_0048 Channel (n) Value (FTM7_C7V) 32 R/W 0000_0000h 23.4.7/1174
2A3_004C Counter Initial Value (FTM7_CNTIN) 32 R/W 0000_0000h 23.4.8/1175
2A3_0050 Capture And Compare Status (FTM7_STATUS) 32 R/W 0000_0000h 23.4.9/1175
23.4.10/
2A3_0054 Features Mode Selection (FTM7_MODE) 32 R/W 0000_0004h
1177
23.4.11/
2A3_0058 Synchronization (FTM7_SYNC) 32 R/W 0000_0000h
1179
23.4.12/
2A3_005C Initial State For Channels Output (FTM7_OUTINIT) 32 R/W 0000_0000h
1182
23.4.13/
2A3_0060 Output Mask (FTM7_OUTMASK) 32 R/W 0000_0000h
1183
23.4.14/
2A3_0064 Function For Linked Channels (FTM7_COMBINE) 32 R/W 0000_0000h
1185
23.4.15/
2A3_0068 Deadtime Insertion Control (FTM7_DEADTIME) 32 R/W 0000_0000h
1190
23.4.16/
2A3_006C FTM External Trigger (FTM7_EXTTRIG) 32 R/W 0000_0000h
1191
23.4.17/
2A3_0070 Channels Polarity (FTM7_POL) 32 R/W 0000_0000h
1193
23.4.18/
2A3_0074 Fault Mode Status (FTM7_FMS) 32 R/W 0000_0000h
1195
23.4.19/
2A3_0078 Input Capture Filter Control (FTM7_FILTER) 32 R/W 0000_0000h
1197
23.4.20/
2A3_007C Fault Control (FTM7_FLTCTRL) 32 R/W 0000_0000h
1198
23.4.21/
2A3_0080 Quadrature Decoder Control And Status (FTM7_QDCTRL) 32 R/W 0000_0000h
1200
23.4.22/
2A3_0084 Configuration (FTM7_CONF) 32 R/W 0000_0000h
1202
23.4.23/
2A3_0088 FTM Fault Input Polarity (FTM7_FLTPOL) 32 R/W 0000_0000h
1203
23.4.24/
2A3_008C Synchronization Configuration (FTM7_SYNCONF) 32 R/W 0000_0000h
1205
23.4.25/
2A3_0090 FTM Inverting Control (FTM7_INVCTRL) 32 R/W 0000_0000h
1207
23.4.26/
2A3_0094 FTM Software Output Control (FTM7_SWOCTRL) 32 R/W 0000_0000h
1208
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1166 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
FTM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
23.4.27/
2A3_0098 FTM PWM Load (FTM7_PWMLOAD) 32 R/W 0000_0000h
1210
2A4_0000 Status And Control (FTM8_SC) 32 R/W 0000_0000h 23.4.3/1169
2A4_0004 Counter (FTM8_CNT) 32 R/W 0000_0000h 23.4.4/1170
2A4_0008 Modulo (FTM8_MOD) 32 R/W 0000_0000h 23.4.5/1171
2A4_000C Channel (n) Status And Control (FTM8_C0SC) 32 R/W 0000_0000h 23.4.6/1172
2A4_0010 Channel (n) Value (FTM8_C0V) 32 R/W 0000_0000h 23.4.7/1174
2A4_0014 Channel (n) Status And Control (FTM8_C1SC) 32 R/W 0000_0000h 23.4.6/1172
2A4_0018 Channel (n) Value (FTM8_C1V) 32 R/W 0000_0000h 23.4.7/1174
2A4_001C Channel (n) Status And Control (FTM8_C2SC) 32 R/W 0000_0000h 23.4.6/1172
2A4_0020 Channel (n) Value (FTM8_C2V) 32 R/W 0000_0000h 23.4.7/1174
2A4_0024 Channel (n) Status And Control (FTM8_C3SC) 32 R/W 0000_0000h 23.4.6/1172
2A4_0028 Channel (n) Value (FTM8_C3V) 32 R/W 0000_0000h 23.4.7/1174
2A4_002C Channel (n) Status And Control (FTM8_C4SC) 32 R/W 0000_0000h 23.4.6/1172
2A4_0030 Channel (n) Value (FTM8_C4V) 32 R/W 0000_0000h 23.4.7/1174
2A4_0034 Channel (n) Status And Control (FTM8_C5SC) 32 R/W 0000_0000h 23.4.6/1172
2A4_0038 Channel (n) Value (FTM8_C5V) 32 R/W 0000_0000h 23.4.7/1174
2A4_003C Channel (n) Status And Control (FTM8_C6SC) 32 R/W 0000_0000h 23.4.6/1172
2A4_0040 Channel (n) Value (FTM8_C6V) 32 R/W 0000_0000h 23.4.7/1174
2A4_0044 Channel (n) Status And Control (FTM8_C7SC) 32 R/W 0000_0000h 23.4.6/1172
2A4_0048 Channel (n) Value (FTM8_C7V) 32 R/W 0000_0000h 23.4.7/1174
2A4_004C Counter Initial Value (FTM8_CNTIN) 32 R/W 0000_0000h 23.4.8/1175
2A4_0050 Capture And Compare Status (FTM8_STATUS) 32 R/W 0000_0000h 23.4.9/1175
23.4.10/
2A4_0054 Features Mode Selection (FTM8_MODE) 32 R/W 0000_0004h
1177
23.4.11/
2A4_0058 Synchronization (FTM8_SYNC) 32 R/W 0000_0000h
1179
23.4.12/
2A4_005C Initial State For Channels Output (FTM8_OUTINIT) 32 R/W 0000_0000h
1182
23.4.13/
2A4_0060 Output Mask (FTM8_OUTMASK) 32 R/W 0000_0000h
1183
23.4.14/
2A4_0064 Function For Linked Channels (FTM8_COMBINE) 32 R/W 0000_0000h
1185
23.4.15/
2A4_0068 Deadtime Insertion Control (FTM8_DEADTIME) 32 R/W 0000_0000h
1190
23.4.16/
2A4_006C FTM External Trigger (FTM8_EXTTRIG) 32 R/W 0000_0000h
1191
23.4.17/
2A4_0070 Channels Polarity (FTM8_POL) 32 R/W 0000_0000h
1193
23.4.18/
2A4_0074 Fault Mode Status (FTM8_FMS) 32 R/W 0000_0000h
1195
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1167
Memory map and register definition
FTM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
23.4.19/
2A4_0078 Input Capture Filter Control (FTM8_FILTER) 32 R/W 0000_0000h
1197
23.4.20/
2A4_007C Fault Control (FTM8_FLTCTRL) 32 R/W 0000_0000h
1198
23.4.21/
2A4_0080 Quadrature Decoder Control And Status (FTM8_QDCTRL) 32 R/W 0000_0000h
1200
23.4.22/
2A4_0084 Configuration (FTM8_CONF) 32 R/W 0000_0000h
1202
23.4.23/
2A4_0088 FTM Fault Input Polarity (FTM8_FLTPOL) 32 R/W 0000_0000h
1203
23.4.24/
2A4_008C Synchronization Configuration (FTM8_SYNCONF) 32 R/W 0000_0000h
1205
23.4.25/
2A4_0090 FTM Inverting Control (FTM8_INVCTRL) 32 R/W 0000_0000h
1207
23.4.26/
2A4_0094 FTM Software Output Control (FTM8_SWOCTRL) 32 R/W 0000_0000h
1208
23.4.27/
2A4_0098 FTM PWM Load (FTM8_PWMLOAD) 32 R/W 0000_0000h
1210
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1168 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
23.4.3 Status And Control (FTMx_SC)
SC contains the overflow status flag and control bits used to configure the interrupt
enable, FTM configuration, clock source, and prescaler factor. These controls relate to all
channels within this module.
Address: Base address + 0h offset
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
TOF
R 0 CPWMS
TOIE CLKS PS
W 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FTMx_SC field descriptions
Field Description
0–23 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
24 Timer Overflow Flag
TOF
Set by hardware when the FTM counter passes the value in the MOD register. The TOF bit is cleared by
reading the SC register while TOF is set and then writing a 0 to TOF bit. Writing a 1 to TOF has no effect.
If another FTM overflow occurs between the read and write operations, the write operation has no effect;
therefore, TOF remains set indicating an overflow has occurred. In this case, a TOF interrupt request is
not lost due to the clearing sequence for a previous TOF.
0 FTM counter has not overflowed.
1 FTM counter has overflowed.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1169
Memory map and register definition
FTMx_SC field descriptions (continued)
Field Description
25 Timer Overflow Interrupt Enable
TOIE
Enables FTM overflow interrupts.
0 Disable TOF interrupts. Use software polling.
1 Enable TOF interrupts. An interrupt is generated when TOF equals one.
26 Center-Aligned PWM Select
CPWMS
Selects CPWM mode. This mode configures the FTM to operate in Up-Down Counting mode.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 FTM counter operates in Up Counting mode.
1 FTM counter operates in Up-Down Counting mode.
27–28 Clock Source Selection
CLKS
Selects FTM counter clock sources.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
00 No clock selected. This in effect disables the FTM counter.
01 System clock
10 Fixed frequency clock
11 External clock
29–31 Prescale Factor Selection
PS
Selects one of 8 division factors for the clock source selected by CLKS. The new prescaler factor affects
the clock source on the next system clock cycle after the new value is updated into the register bits.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
000 Divide by 1
001 Divide by 2
010 Divide by 4
011 Divide by 8
100 Divide by 16
101 Divide by 32
110 Divide by 64
111 Divide by 128
23.4.4 Counter (FTMx_CNT)
The CNT register contains the FTM counter value.
Reset clears the CNT register. Writing any value to COUNT updates the counter with its
initial value, CNTIN.
When is active, the FTM counter is frozen. This is the value that you may read.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1170 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
Address: Base address + 4h offset
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 COUNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FTMx_CNT field descriptions
Field Description
0–15 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
16–31 Counter Value
COUNT
23.4.5 Modulo (FTMx_MOD)
The Modulo register contains the modulo value for the FTM counter. After the FTM
counter reaches the modulo value, the overflow flag (TOF) becomes set at the next clock,
and the next value of FTM counter depends on the selected counting method; see
Counter.
Writing to the MOD register latches the value into a buffer. The MOD register is updated
with the value of its write buffer according to Registers updated from write buffers.
If FTMEN = 0, this write coherency mechanism may be manually reset by writing to the
SC register whether is active or not.
Initialize the FTM counter, by writing to CNT, before writing to the MOD register to
avoid confusion about when the first counter overflow will occur.
Address: Base address + 8h offset
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
Reserved MOD
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FTMx_MOD field descriptions
Field Description
0–15 This field is reserved.
Reserved
16–31 Modulo Value
MOD
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1171
Memory map and register definition
23.4.6 Channel (n) Status And Control (FTMx_CnSC)
CnSC contains the channel-interrupt-status flag and control bits used to configure the
interrupt enable, channel configuration, and pin function.
Table 23-6. Mode, edge, and level selection
DECAPEN COMBINE CPWMS MSnB:MSnA ELSnB:ELSnA Mode Configuration
X X X XX 00 Pin not used for FTM—revert the
channel pin to general purpose I/O
or other peripheral control
0 0 0 00 01 Input Capture Capture on
Rising Edge
Only
10 Capture on
Falling Edge
Only
11 Capture on
Rising or Falling
Edge
01 01 Output Compare Toggle Output
on match
10 Clear Output on
match
11 Set Output on
match
1X 10 Edge-Aligned High-true pulses
PWM (clear Output on
match)
X1 Low-true pulses
(set Output on
match)
1 XX 10 Center-Aligned High-true pulses
PWM (clear Output on
match-up)
X1 Low-true pulses
(set Output on
match-up)
1 0 XX 10 Combine PWM High-true pulses
(set on channel
(n) match, and
clear on channel
(n+1) match)
X1 Low-true pulses
(clear on
channel (n)
match, and set
on channel (n
+1) match)
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1172 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
Table 23-6. Mode, edge, and level selection (continued)
DECAPEN COMBINE CPWMS MSnB:MSnA ELSnB:ELSnA Mode Configuration
1 0 0 X0 See the Dual Edge One-Shot
following table Capture Capture mode
(Table 23-7).
X1 Continuous
Capture mode
Table 23-7. Dual Edge Capture mode — edge polarity selection
ELSnB ELSnA Channel Port Enable Detected Edges
0 0 Disabled No edge
0 1 Enabled Rising edge
1 0 Enabled Falling edge
1 1 Enabled Rising and falling edges
Address: Base address + Ch offset + (8d × i), where i=0d to 7d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 CHF 0
CHIE MSB MSA ELSB ELSA DMA
W 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FTMx_CnSC field descriptions
Field Description
0–23 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
24 Channel Flag
CHF
Set by hardware when an event occurs on the channel. CHF is cleared by reading the CSC register while
CHnF is set and then writing a 0 to the CHF bit. Writing a 1 to CHF has no effect.
If another event occurs between the read and write operations, the write operation has no effect; therefore,
CHF remains set indicating an event has occurred. In this case a CHF interrupt request is not lost due to
the clearing sequence for a previous CHF.
0 No channel event has occurred.
1 A channel event has occurred.
25 Channel Interrupt Enable
CHIE
Enables channel interrupts.
0 Disable channel interrupts. Use software polling.
1 Enable channel interrupts.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1173
Memory map and register definition
FTMx_CnSC field descriptions (continued)
Field Description
26 Channel Mode Select
MSB
Used for further selections in the channel logic. Its functionality is dependent on the channel mode. See
Table 23-6 .
This field is write protected. It can be written only when MODE[WPDIS] = 1.
27 Channel Mode Select
MSA
Used for further selections in the channel logic. Its functionality is dependent on the channel mode. See
Table 23-6 .
This field is write protected. It can be written only when MODE[WPDIS] = 1.
28 Edge or Level Select
ELSB
The functionality of ELSB and ELSA depends on the channel mode. See Table 23-6 .
This field is write protected. It can be written only when MODE[WPDIS] = 1.
29 Edge or Level Select
ELSA
The functionality of ELSB and ELSA depends on the channel mode. See Table 23-6 .
This field is write protected. It can be written only when MODE[WPDIS] = 1.
30 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
31 DMA Enable
DMA
Enables DMA transfers for the channel.
0 Disable DMA transfers.
1 Enable DMA transfers.
23.4.7 Channel (n) Value (FTMx_CnV)
These registers contain the captured FTM counter value for the input modes or the match
value for the output modes.
In Input Capture, Capture Test, and Dual Edge Capture modes, any write to a CnV
register is ignored.
In output modes, writing to a CnV register latches the value into a buffer. A CnV register
is updated with the value of its write buffer according to Registers updated from write
buffers.
If FTMEN = 0, this write coherency mechanism may be manually reset by writing to the
CnSC register whether mode is active or not.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1174 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
Address: Base address + 10h offset + (8d × i), where i=0d to 7d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 VAL
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FTMx_CnV field descriptions
Field Description
0–15 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
16–31 Channel Value
VAL
Captured FTM counter value of the input modes or the match value for the output modes
23.4.8 Counter Initial Value (FTMx_CNTIN)
The Counter Initial Value register contains the initial value for the FTM counter.
Writing to the CNTIN register latches the value into a buffer. The CNTIN register is
updated with the value of its write buffer according to Registers updated from write
buffers.
When the FTM clock is initially selected, by writing a non-zero value to the CLKS bits,
the FTM counter starts with the value 0x0000. To avoid this behavior, before the first
write to select the FTM clock, write the new value to the the CNTIN register and then
initialize the FTM counter by writing any value to the CNT register.
Address: Base address + 4Ch offset
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
Reserved INIT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FTMx_CNTIN field descriptions
Field Description
0–15 This field is reserved.
Reserved
16–31 Initial Value Of The FTM Counter
INIT
23.4.9 Capture And Compare Status (FTMx_STATUS)
The STATUS register contains a copy of the status flag CHnF bit in CnSC for each FTM
channel for software convenience.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1175
Memory map and register definition
Each CHnF bit in STATUS is a mirror of CHnF bit in CnSC. All CHnF bits can be
checked using only one read of STATUS. All CHnF bits can be cleared by reading
STATUS followed by writing 0x00 to STATUS.
Hardware sets the individual channel flags when an event occurs on the channel. CHnF is
cleared by reading STATUS while CHnF is set and then writing a 0 to the CHnF bit.
Writing a 1 to CHnF has no effect.
If another event occurs between the read and write operations, the write operation has no
effect; therefore, CHnF remains set indicating an event has occurred. In this case, a CHnF
interrupt request is not lost due to the clearing sequence for a previous CHnF.
Address: Base address + 50h offset
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
CH7F
CH6F
CH5F
CH4F
CH3F
CH2F
CH1F
CH0F
R 0
W 0 0 0 0 0 0 0 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FTMx_STATUS field descriptions
Field Description
0–23 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
24 Channel 7 Flag
CH7F
See the register description.
0 No channel event has occurred.
1 A channel event has occurred.
25 Channel 6 Flag
CH6F
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1176 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
FTMx_STATUS field descriptions (continued)
Field Description
See the register description.
0 No channel event has occurred.
1 A channel event has occurred.
26 Channel 5 Flag
CH5F
See the register description.
0 No channel event has occurred.
1 A channel event has occurred.
27 Channel 4 Flag
CH4F
See the register description.
0 No channel event has occurred.
1 A channel event has occurred.
28 Channel 3 Flag
CH3F
See the register description.
0 No channel event has occurred.
1 A channel event has occurred.
29 Channel 2 Flag
CH2F
See the register description.
0 No channel event has occurred.
1 A channel event has occurred.
30 Channel 1 Flag
CH1F
See the register description.
0 No channel event has occurred.
1 A channel event has occurred.
31 Channel 0 Flag
CH0F
See the register description.
0 No channel event has occurred.
1 A channel event has occurred.
23.4.10 Features Mode Selection (FTMx_MODE)
This register contains the global enable bit for FTM-specific features and the control bits
used to configure:
• Fault control mode and interrupt
• Capture Test mode
• PWM synchronization
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1177
Memory map and register definition
• Write protection
• Channel output initialization
These controls relate to all channels within this module.
Address: Base address + 54h offset
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
PWMSYNC
0
CAPTEST
R
FAULTIE
FTMEN
WPDIS
FAULTM INIT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
FTMx_MODE field descriptions
Field Description
0–23 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
24 Fault Interrupt Enable
FAULTIE
Enables the generation of an interrupt when a fault is detected by FTM and the FTM fault control is
enabled.
0 Fault control interrupt is disabled.
1 Fault control interrupt is enabled.
25–26 Fault Control Mode
FAULTM
Defines the FTM fault control mode.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
00 Fault control is disabled for all channels.
01 Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is
the manual fault clearing.
10 Fault control is enabled for all channels, and the selected mode is the manual fault clearing.
11 Fault control is enabled for all channels, and the selected mode is the automatic fault clearing.
27 Capture Test Mode Enable
CAPTEST
Enables the capture test mode.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 Capture test mode is disabled.
1 Capture test mode is enabled.
28 PWM Synchronization Mode
PWMSYNC
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1178 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
FTMx_MODE field descriptions (continued)
Field Description
Selects which triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization. See
PWM synchronization. The PWMSYNC bit configures the synchronization when SYNCMODE is 0.
0 No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM
counter synchronization.
1 Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only
be used by OUTMASK and FTM counter synchronization.
29 Write Protection Disable
WPDIS
When write protection is enabled (WPDIS = 0), write protected bits cannot be written. When write
protection is disabled (WPDIS = 1), write protected bits can be written. The WPDIS bit is the negation of
the WPEN bit. WPDIS is cleared when 1 is written to WPEN. WPDIS is set when WPEN bit is read as a 1
and then 1 is written to WPDIS. Writing 0 to WPDIS has no effect.
0 Write protection is enabled.
1 Write protection is disabled.
30 Initialize The Channels Output
INIT
When a 1 is written to INIT bit the channels output is initialized according to the state of their
corresponding bit in the OUTINIT register. Writing a 0 to INIT bit has no effect.
The INIT bit is always read as 0.
31 FTM Enable
FTMEN
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 TPM compatibility. Free running counter and synchronization compatible with TPM.
1 Free running counter and synchronization are different from TPM behavior.
23.4.11 Synchronization (FTMx_SYNC)
This register configures the PWM synchronization.
A synchronization event can perform the synchronized update of MOD, CV, and
OUTMASK registers with the value of their write buffer and the FTM counter
initialization.
NOTE
The software trigger, SWSYNC bit, and hardware triggers
TRIG0, TRIG1, and TRIG2 bits have a potential conflict if
used together when SYNCMODE = 0. Use only hardware or
software triggers but not both at the same time, otherwise
unpredictable behavior is likely to happen.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1179
Memory map and register definition
The selection of the loading point, CNTMAX and CNTMIN
bits, is intended to provide the update of MOD, CNTIN, and
CnV registers across all enabled channels simultaneously. The
use of the loading point selection together with SYNCMODE =
0 and hardware trigger selection, TRIG0, TRIG1, or TRIG2
bits, is likely to result in unpredictable behavior.
The synchronization event selection also depends on the
PWMSYNC (MODE register) and SYNCMODE (SYNCONF
register) bits. See PWM synchronization.
Address: Base address + 58h offset
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SYNCHOM
R 0
SWSYNC
CNTMAX
CNTMIN
REINIT
TRIG2
TRIG1
TRIG0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FTMx_SYNC field descriptions
Field Description
0–23 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
24 PWM Synchronization Software Trigger
SWSYNC
Selects the software trigger as the PWM synchronization trigger. The software trigger happens when a 1 is
written to SWSYNC bit.
0 Software trigger is not selected.
1 Software trigger is selected.
25 PWM Synchronization Hardware Trigger 2
TRIG2
Enables hardware trigger 2 to the PWM synchronization. Hardware trigger 2 happens when a rising edge
is detected at the trigger 2 input signal.
0 Trigger is disabled.
1 Trigger is enabled.
26 PWM Synchronization Hardware Trigger 1
TRIG1
Enables hardware trigger 1 to the PWM synchronization. Hardware trigger 1 happens when a rising edge
is detected at the trigger 1 input signal.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1180 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
FTMx_SYNC field descriptions (continued)
Field Description
0 Trigger is disabled.
1 Trigger is enabled.
27 PWM Synchronization Hardware Trigger 0
TRIG0
Enables hardware trigger 0 to the PWM synchronization. Hardware trigger 0 occurs when a rising edge is
detected at the trigger 0 input signal.
0 Trigger is disabled.
1 Trigger is enabled.
28 Output Mask Synchronization
SYNCHOM
Selects when the OUTMASK register is updated with the value of its buffer.
0 OUTMASK register is updated with the value of its buffer in all rising edges of the system clock.
1 OUTMASK register is updated with the value of its buffer only by the PWM synchronization.
29 FTM Counter Reinitialization By Synchronization (FTM counter synchronization)
REINIT
Determines if the FTM counter is reinitialized when the selected trigger for the synchronization is detected.
The REINIT bit configures the synchronization when SYNCMODE is zero.
0 FTM counter continues to count normally.
1 FTM counter is updated with its initial value when the selected trigger is detected.
30 Maximum Loading Point Enable
CNTMAX
Selects the maximum loading point to PWM synchronization. See Boundary cycle and loading points. If
CNTMAX is 1, the selected loading point is when the FTM counter reaches its maximum value (MOD
register).
0 The maximum loading point is disabled.
1 The maximum loading point is enabled.
31 Minimum Loading Point Enable
CNTMIN
Selects the minimum loading point to PWM synchronization. See Boundary cycle and loading points. If
CNTMIN is one, the selected loading point is when the FTM counter reaches its minimum value (CNTIN
register).
0 The minimum loading point is disabled.
1 The minimum loading point is enabled.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1181
Memory map and register definition
23.4.12 Initial State For Channels Output (FTMx_OUTINIT)
Address: Base address + 5Ch offset
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0
CH7OI
CH6OI
CH5OI
CH4OI
CH3OI
CH2OI
CH1OI
CH0OI
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FTMx_OUTINIT field descriptions
Field Description
0–23 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
24 Channel 7 Output Initialization Value
CH7OI
Selects the value that is forced into the channel output when the initialization occurs.
0 The initialization value is 0.
1 The initialization value is 1.
25 Channel 6 Output Initialization Value
CH6OI
Selects the value that is forced into the channel output when the initialization occurs.
0 The initialization value is 0.
1 The initialization value is 1.
26 Channel 5 Output Initialization Value
CH5OI
Selects the value that is forced into the channel output when the initialization occurs.
0 The initialization value is 0.
1 The initialization value is 1.
27 Channel 4 Output Initialization Value
CH4OI
Selects the value that is forced into the channel output when the initialization occurs.
0 The initialization value is 0.
1 The initialization value is 1.
28 Channel 3 Output Initialization Value
CH3OI
Selects the value that is forced into the channel output when the initialization occurs.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1182 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
FTMx_OUTINIT field descriptions (continued)
Field Description
0 The initialization value is 0.
1 The initialization value is 1.
29 Channel 2 Output Initialization Value
CH2OI
Selects the value that is forced into the channel output when the initialization occurs.
0 The initialization value is 0.
1 The initialization value is 1.
30 Channel 1 Output Initialization Value
CH1OI
Selects the value that is forced into the channel output when the initialization occurs.
0 The initialization value is 0.
1 The initialization value is 1.
31 Channel 0 Output Initialization Value
CH0OI
Selects the value that is forced into the channel output when the initialization occurs.
0 The initialization value is 0.
1 The initialization value is 1.
23.4.13 Output Mask (FTMx_OUTMASK)
This register provides a mask for each FTM channel. The mask of a channel determines if
its output responds, that is, it is masked or not, when a match occurs. This feature is used
for BLDC control where the PWM signal is presented to an electric motor at specific
times to provide electronic commutation.
Any write to the OUTMASK register, stores the value in its write buffer. The register is
updated with the value of its write buffer according to PWM synchronization.
Address: Base address + 60h offset
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0
CH7OM
CH6OM
CH5OM
CH4OM
CH3OM
CH2OM
CH1OM
CH0OM
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1183
Memory map and register definition
FTMx_OUTMASK field descriptions
Field Description
0–23 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
24 Channel 7 Output Mask
CH7OM
Defines if the channel output is masked or unmasked.
0 Channel output is not masked. It continues to operate normally.
1 Channel output is masked. It is forced to its inactive state.
25 Channel 6 Output Mask
CH6OM
Defines if the channel output is masked or unmasked.
0 Channel output is not masked. It continues to operate normally.
1 Channel output is masked. It is forced to its inactive state.
26 Channel 5 Output Mask
CH5OM
Defines if the channel output is masked or unmasked.
0 Channel output is not masked. It continues to operate normally.
1 Channel output is masked. It is forced to its inactive state.
27 Channel 4 Output Mask
CH4OM
Defines if the channel output is masked or unmasked.
0 Channel output is not masked. It continues to operate normally.
1 Channel output is masked. It is forced to its inactive state.
28 Channel 3 Output Mask
CH3OM
Defines if the channel output is masked or unmasked.
0 Channel output is not masked. It continues to operate normally.
1 Channel output is masked. It is forced to its inactive state.
29 Channel 2 Output Mask
CH2OM
Defines if the channel output is masked or unmasked.
0 Channel output is not masked. It continues to operate normally.
1 Channel output is masked. It is forced to its inactive state.
30 Channel 1 Output Mask
CH1OM
Defines if the channel output is masked or unmasked.
0 Channel output is not masked. It continues to operate normally.
1 Channel output is masked. It is forced to its inactive state.
31 Channel 0 Output Mask
CH0OM
Defines if the channel output is masked or unmasked.
0 Channel output is not masked. It continues to operate normally.
1 Channel output is masked. It is forced to its inactive state.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1184 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
23.4.14 Function For Linked Channels (FTMx_COMBINE)
This register contains the control bits used to configure the fault control, synchronization,
deadtime insertion, Dual Edge Capture mode, Complementary, and Combine mode for
each pair of channels (n) and (n+1), where n equals 0, 2, 4, and 6.
Address: Base address + 64h offset
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DECAPEN3
DECAPEN2
0 0
COMBINE3
COMBINE2
FAULTEN3
FAULTEN2
R
SYNCEN3
SYNCEN2
DECAP3
DECAP2
COMP3
COMP2
DTEN3
DTEN2
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
DECAPEN1
DECAPEN0
0 0
COMBINE1
COMBINE0
FAULTEN1
FAULTEN0
R
SYNCEN1
SYNCEN0
DECAP1
DECAP0
COMP1
COMP0
DTEN1
DTEN0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FTMx_COMBINE field descriptions
Field Description
0 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
1 Fault Control Enable For n = 6
FAULTEN3
Enables the fault control in channels (n) and (n+1).
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 The fault control in this pair of channels is disabled.
1 The fault control in this pair of channels is enabled.
2 Synchronization Enable For n = 6
SYNCEN3
Enables PWM synchronization of registers C(n)V and C(n+1)V.
0 The PWM synchronization in this pair of channels is disabled.
1 The PWM synchronization in this pair of channels is enabled.
3 Deadtime Enable For n = 6
DTEN3
Enables the deadtime insertion in the channels (n) and (n+1).
This field is write protected. It can be written only when MODE[WPDIS] = 1.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1185
Memory map and register definition
FTMx_COMBINE field descriptions (continued)
Field Description
0 The deadtime insertion in this pair of channels is disabled.
1 The deadtime insertion in this pair of channels is enabled.
4 Dual Edge Capture Mode Captures For n = 6
DECAP3
Enables the capture of the FTM counter value according to the channel (n) input event and the
configuration of the dual edge capture bits.
This field applies only when DECAPEN = 1.
DECAP bit is cleared automatically by hardware if dual edge capture – one-shot mode is selected and
when the capture of channel (n+1) event is made.
0 The dual edge captures are inactive.
1 The dual edge captures are active.
5 Dual Edge Capture Mode Enable For n = 6
DECAPEN3
Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit reconfigures the function of
MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in Dual Edge Capture mode according to Table
23-6.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 The Dual Edge Capture mode in this pair of channels is disabled.
1 The Dual Edge Capture mode in this pair of channels is enabled.
6 Complement Of Channel (n) for n = 6
COMP3
Enables Complementary mode for the combined channels. In Complementary mode the channel (n+1)
output is the inverse of the channel (n) output.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 The channel (n+1) output is the same as the channel (n) output.
1 The channel (n+1) output is the complement of the channel (n) output.
7 Combine Channels For n = 6
COMBINE3
Enables the combine feature for channels (n) and (n+1).
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 Channels (n) and (n+1) are independent.
1 Channels (n) and (n+1) are combined.
8 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
9 Fault Control Enable For n = 4
FAULTEN2
Enables the fault control in channels (n) and (n+1).
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 The fault control in this pair of channels is disabled.
1 The fault control in this pair of channels is enabled.
10 Synchronization Enable For n = 4
SYNCEN2
Enables PWM synchronization of registers C(n)V and C(n+1)V.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1186 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
FTMx_COMBINE field descriptions (continued)
Field Description
0 The PWM synchronization in this pair of channels is disabled.
1 The PWM synchronization in this pair of channels is enabled.
11 Deadtime Enable For n = 4
DTEN2
Enables the deadtime insertion in the channels (n) and (n+1).
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 The deadtime insertion in this pair of channels is disabled.
1 The deadtime insertion in this pair of channels is enabled.
12 Dual Edge Capture Mode Captures For n = 4
DECAP2
Enables the capture of the FTM counter value according to the channel (n) input event and the
configuration of the dual edge capture bits.
This field applies only when DECAPEN = 1.
DECAP bit is cleared automatically by hardware if dual edge capture – one-shot mode is selected and
when the capture of channel (n+1) event is made.
0 The dual edge captures are inactive.
1 The dual edge captures are active.
13 Dual Edge Capture Mode Enable For n = 4
DECAPEN2
Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit reconfigures the function of
MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in Dual Edge Capture mode according to Table
23-6.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 The Dual Edge Capture mode in this pair of channels is disabled.
1 The Dual Edge Capture mode in this pair of channels is enabled.
14 Complement Of Channel (n) For n = 4
COMP2
Enables Complementary mode for the combined channels. In Complementary mode the channel (n+1)
output is the inverse of the channel (n) output.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 The channel (n+1) output is the same as the channel (n) output.
1 The channel (n+1) output is the complement of the channel (n) output.
15 Combine Channels For n = 4
COMBINE2
Enables the combine feature for channels (n) and (n+1).
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 Channels (n) and (n+1) are independent.
1 Channels (n) and (n+1) are combined.
16 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
17 Fault Control Enable For n = 2
FAULTEN1
Enables the fault control in channels (n) and (n+1).
This field is write protected. It can be written only when MODE[WPDIS] = 1.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1187
Memory map and register definition
FTMx_COMBINE field descriptions (continued)
Field Description
0 The fault control in this pair of channels is disabled.
1 The fault control in this pair of channels is enabled.
18 Synchronization Enable For n = 2
SYNCEN1
Enables PWM synchronization of registers C(n)V and C(n+1)V.
0 The PWM synchronization in this pair of channels is disabled.
1 The PWM synchronization in this pair of channels is enabled.
19 Deadtime Enable For n = 2
DTEN1
Enables the deadtime insertion in the channels (n) and (n+1).
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 The deadtime insertion in this pair of channels is disabled.
1 The deadtime insertion in this pair of channels is enabled.
20 Dual Edge Capture Mode Captures For n = 2
DECAP1
Enables the capture of the FTM counter value according to the channel (n) input event and the
configuration of the dual edge capture bits.
This field applies only when DECAPEN = 1.
DECAP bit is cleared automatically by hardware if Dual Edge Capture – One-Shot mode is selected and
when the capture of channel (n+1) event is made.
0 The dual edge captures are inactive.
1 The dual edge captures are active.
21 Dual Edge Capture Mode Enable For n = 2
DECAPEN1
Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit reconfigures the function of
MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in Dual Edge Capture mode according to Table
23-6.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 The Dual Edge Capture mode in this pair of channels is disabled.
1 The Dual Edge Capture mode in this pair of channels is enabled.
22 Complement Of Channel (n) For n = 2
COMP1
Enables Complementary mode for the combined channels. In Complementary mode the channel (n+1)
output is the inverse of the channel (n) output.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 The channel (n+1) output is the same as the channel (n) output.
1 The channel (n+1) output is the complement of the channel (n) output.
23 Combine Channels For n = 2
COMBINE1
Enables the combine feature for channels (n) and (n+1).
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 Channels (n) and (n+1) are independent.
1 Channels (n) and (n+1) are combined.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1188 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
FTMx_COMBINE field descriptions (continued)
Field Description
24 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
25 Fault Control Enable For n = 0
FAULTEN0
Enables the fault control in channels (n) and (n+1).
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 The fault control in this pair of channels is disabled.
1 The fault control in this pair of channels is enabled.
26 Synchronization Enable For n = 0
SYNCEN0
Enables PWM synchronization of registers C(n)V and C(n+1)V.
0 The PWM synchronization in this pair of channels is disabled.
1 The PWM synchronization in this pair of channels is enabled.
27 Deadtime Enable For n = 0
DTEN0
Enables the deadtime insertion in the channels (n) and (n+1).
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 The deadtime insertion in this pair of channels is disabled.
1 The deadtime insertion in this pair of channels is enabled.
28 Dual Edge Capture Mode Captures For n = 0
DECAP0
Enables the capture of the FTM counter value according to the channel (n) input event and the
configuration of the dual edge capture bits.
This field applies only when DECAPEN = 1.
DECAP bit is cleared automatically by hardware if dual edge capture – one-shot mode is selected and
when the capture of channel (n+1) event is made.
0 The dual edge captures are inactive.
1 The dual edge captures are active.
29 Dual Edge Capture Mode Enable For n = 0
DECAPEN0
Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit reconfigures the function of
MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in Dual Edge Capture mode according to Table
23-6.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 The Dual Edge Capture mode in this pair of channels is disabled.
1 The Dual Edge Capture mode in this pair of channels is enabled.
30 Complement Of Channel (n) For n = 0
COMP0
Enables Complementary mode for the combined channels. In Complementary mode the channel (n+1)
output is the inverse of the channel (n) output.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 The channel (n+1) output is the same as the channel (n) output.
1 The channel (n+1) output is the complement of the channel (n) output.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1189
Memory map and register definition
FTMx_COMBINE field descriptions (continued)
Field Description
31 Combine Channels For n = 0
COMBINE0
Enables the combine feature for channels (n) and (n+1).
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 Channels (n) and (n+1) are independent.
1 Channels (n) and (n+1) are combined.
23.4.15 Deadtime Insertion Control (FTMx_DEADTIME)
This register selects the deadtime prescaler factor and deadtime value. All FTM channels
use this clock prescaler and this deadtime value for the deadtime insertion.
Address: Base address + 68h offset
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 DTPS DTVAL
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FTMx_DEADTIME field descriptions
Field Description
0–23 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
24–25 Deadtime Prescaler Value
DTPS
Selects the division factor of the system clock. This prescaled clock is used by the deadtime counter.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0x Divide the system clock by 1.
10 Divide the system clock by 4.
11 Divide the system clock by 16.
26–31 Deadtime Value
DTVAL
Selects the deadtime insertion value for the deadtime counter. The deadtime counter is clocked by a
scaled version of the system clock. See the description of DTPS.
Deadtime insert value = (DTPS × DTVAL).
DTVAL selects the number of deadtime counts inserted as follows:
When DTVAL is 0, no counts are inserted.
When DTVAL is 1, 1 count is inserted.
When DTVAL is 2, 2 counts are inserted.
This pattern continues up to a possible 63 counts.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1190 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
23.4.16 FTM External Trigger (FTMx_EXTTRIG)
This register:
• Indicates when a channel trigger was generated
• Enables the generation of a trigger when the FTM counter is equal to its initial value
• Selects which channels are used in the generation of the channel triggers
Several channels can be selected to generate multiple triggers in one PWM period. See
Channel trigger output and Initialization trigger.
Channels 6 and 7 are not used to generate channel triggers.
Address: Base address + 6Ch offset
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
TRIGF
R
INITTRIGEN
CH1TRIG
CH0TRIG
CH5TRIG
CH4TRIG
CH3TRIG
Reserved CH2TRIG
W 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1191
Memory map and register definition
FTMx_EXTTRIG field descriptions
Field Description
0–23 This field is reserved.
Reserved
24 Channel Trigger Flag
TRIGF
Set by hardware when a channel trigger is generated. Clear TRIGF by reading EXTTRIG while TRIGF is
set and then writing a 0 to TRIGF. Writing a 1 to TRIGF has no effect.
If another channel trigger is generated before the clearing sequence is completed, the sequence is reset
so TRIGF remains set after the clear sequence is completed for the earlier TRIGF.
0 No channel trigger was generated.
1 A channel trigger was generated.
25 Initialization Trigger Enable
INITTRIGEN
Enables the generation of the trigger when the FTM counter is equal to the CNTIN register.
0 The generation of initialization trigger is disabled.
1 The generation of initialization trigger is enabled.
26 Channel 1 Trigger Enable
CH1TRIG
Enables the generation of the channel trigger when the FTM counter is equal to the CnV register.
0 The generation of the channel trigger is disabled.
1 The generation of the channel trigger is enabled.
27 Channel 0 Trigger Enable
CH0TRIG
Enables the generation of the channel trigger when the FTM counter is equal to the CnV register.
0 The generation of the channel trigger is disabled.
1 The generation of the channel trigger is enabled.
28 Channel 5 Trigger Enable
CH5TRIG
Enables the generation of the channel trigger when the FTM counter is equal to the CnV register.
0 The generation of the channel trigger is disabled.
1 The generation of the channel trigger is enabled.
29 Channel 4 Trigger Enable
CH4TRIG
Enables the generation of the channel trigger when the FTM counter is equal to the CnV register.
0 The generation of the channel trigger is disabled.
1 The generation of the channel trigger is enabled.
30 Channel 3 Trigger Enable
CH3TRIG
Enables the generation of the channel trigger when the FTM counter is equal to the CnV register.
0 The generation of the channel trigger is disabled.
1 The generation of the channel trigger is enabled.
31 Channel 2 Trigger Enable
CH2TRIG
Enables the generation of the channel trigger when the FTM counter is equal to the CnV register.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1192 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
FTMx_EXTTRIG field descriptions (continued)
Field Description
0 The generation of the channel trigger is disabled.
1 The generation of the channel trigger is enabled.
23.4.17 Channels Polarity (FTMx_POL)
This register defines the output polarity of the FTM channels.
NOTE
The safe value that is driven in a channel output when the fault
control is enabled and a fault condition is detected is the
inactive state of the channel. That is, the safe value of a channel
is the value of its POL bit.
Address: Base address + 70h offset
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
W
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
Reserved POL7 POL6 POL5 POL4 POL3 POL2 POL1 POL0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FTMx_POL field descriptions
Field Description
0–23 This field is reserved.
Reserved
24 Channel 7 Polarity
POL7
Defines the polarity of the channel output.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 The channel polarity is active high.
1 The channel polarity is active low.
25 Channel 6 Polarity
POL6
Defines the polarity of the channel output.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 The channel polarity is active high.
1 The channel polarity is active low.
26 Channel 5 Polarity
POL5
Defines the polarity of the channel output.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1193
Memory map and register definition
FTMx_POL field descriptions (continued)
Field Description
0 The channel polarity is active high.
1 The channel polarity is active low.
27 Channel 4 Polarity
POL4
Defines the polarity of the channel output.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 The channel polarity is active high.
1 The channel polarity is active low.
28 Channel 3 Polarity
POL3
Defines the polarity of the channel output.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 The channel polarity is active high.
1 The channel polarity is active low.
29 Channel 2 Polarity
POL2
Defines the polarity of the channel output.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 The channel polarity is active high.
1 The channel polarity is active low.
30 Channel 1 Polarity
POL1
Defines the polarity of the channel output.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 The channel polarity is active high.
1 The channel polarity is active low.
31 Channel 0 Polarity
POL0
Defines the polarity of the channel output.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 The channel polarity is active high.
1 The channel polarity is active low.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1194 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
23.4.18 Fault Mode Status (FTMx_FMS)
This register contains the fault detection flags, write protection enable bit, and the logic
OR of the enabled fault inputs.
Address: Base address + 74h offset
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
FAULTF3
FAULTF2
FAULTF1
FAULTF0
FAULTIN
FAULTF
R 0 0
WPEN
W 0 0 0 0 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FTMx_FMS field descriptions
Field Description
0–23 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
24 Fault Detection Flag
FAULTF
Represents the logic OR of the individual FAULTFj bits where j = 3, 2, 1, 0. Clear FAULTF by reading the
FMS register while FAULTF is set and then writing a 0 to FAULTF while there is no existing fault condition
at the enabled fault inputs. Writing a 1 to FAULTF has no effect.
If another fault condition is detected in an enabled fault input before the clearing sequence is completed,
the sequence is reset so FAULTF remains set after the clearing sequence is completed for the earlier fault
condition. FAULTF is also cleared when FAULTFj bits are cleared individually.
0 No fault condition was detected.
1 A fault condition was detected.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1195
Memory map and register definition
FTMx_FMS field descriptions (continued)
Field Description
25 Write Protection Enable
WPEN
The WPEN bit is the negation of the WPDIS bit. WPEN is set when 1 is written to it. WPEN is cleared
when WPEN bit is read as a 1 and then 1 is written to WPDIS. Writing 0 to WPEN has no effect.
0 Write protection is disabled. Write protected bits can be written.
1 Write protection is enabled. Write protected bits cannot be written.
26 Fault Inputs
FAULTIN
Represents the logic OR of the enabled fault inputs after their filter (if their filter is enabled) when fault
control is enabled.
0 The logic OR of the enabled fault inputs is 0.
1 The logic OR of the enabled fault inputs is 1.
27 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
28 Fault Detection Flag 3
FAULTF3
Set by hardware when fault control is enabled, the corresponding fault input is enabled and a fault
condition is detected at the fault input.
Clear FAULTF3 by reading the FMS register while FAULTF3 is set and then writing a 0 to FAULTF3 while
there is no existing fault condition at the corresponding fault input. Writing a 1 to FAULTF3 has no effect.
FAULTF3 bit is also cleared when FAULTF bit is cleared.
If another fault condition is detected at the corresponding fault input before the clearing sequence is
completed, the sequence is reset so FAULTF3 remains set after the clearing sequence is completed for
the earlier fault condition.
0 No fault condition was detected at the fault input.
1 A fault condition was detected at the fault input.
29 Fault Detection Flag 2
FAULTF2
Set by hardware when fault control is enabled, the corresponding fault input is enabled and a fault
condition is detected at the fault input.
Clear FAULTF2 by reading the FMS register while FAULTF2 is set and then writing a 0 to FAULTF2 while
there is no existing fault condition at the corresponding fault input. Writing a 1 to FAULTF2 has no effect.
FAULTF2 bit is also cleared when FAULTF bit is cleared.
If another fault condition is detected at the corresponding fault input before the clearing sequence is
completed, the sequence is reset so FAULTF2 remains set after the clearing sequence is completed for
the earlier fault condition.
0 No fault condition was detected at the fault input.
1 A fault condition was detected at the fault input.
30 Fault Detection Flag 1
FAULTF1
Set by hardware when fault control is enabled, the corresponding fault input is enabled and a fault
condition is detected at the fault input.
Clear FAULTF1 by reading the FMS register while FAULTF1 is set and then writing a 0 to FAULTF1 while
there is no existing fault condition at the corresponding fault input. Writing a 1 to FAULTF1 has no effect.
FAULTF1 bit is also cleared when FAULTF bit is cleared.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1196 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
FTMx_FMS field descriptions (continued)
Field Description
If another fault condition is detected at the corresponding fault input before the clearing sequence is
completed, the sequence is reset so FAULTF1 remains set after the clearing sequence is completed for
the earlier fault condition.
0 No fault condition was detected at the fault input.
1 A fault condition was detected at the fault input.
31 Fault Detection Flag 0
FAULTF0
Set by hardware when fault control is enabled, the corresponding fault input is enabled and a fault
condition is detected at the fault input.
Clear FAULTF0 by reading the FMS register while FAULTF0 is set and then writing a 0 to FAULTF0 while
there is no existing fault condition at the corresponding fault input. Writing a 1 to FAULTF0 has no effect.
FAULTF0 bit is also cleared when FAULTF bit is cleared.
If another fault condition is detected at the corresponding fault input before the clearing sequence is
completed, the sequence is reset so FAULTF0 remains set after the clearing sequence is completed for
the earlier fault condition.
0 No fault condition was detected at the fault input.
1 A fault condition was detected at the fault input.
23.4.19 Input Capture Filter Control (FTMx_FILTER)
This register selects the filter value for the inputs of channels.
Channels 4, 5, 6 and 7 do not have an input filter.
NOTE
Writing to the FILTER register has immediate effect and must
be done only when the channels 0, 1, 2, and 3 are not in input
modes. Failure to do this could result in a missing valid signal.
Address: Base address + 78h offset
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
Reserved CH3FVAL CH2FVAL CH1FVAL CH0FVAL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FTMx_FILTER field descriptions
Field Description
0–15 This field is reserved.
Reserved
16–19 Channel 3 Input Filter
CH3FVAL
Selects the filter value for the channel input.
The filter is disabled when the value is zero.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1197
Memory map and register definition
FTMx_FILTER field descriptions (continued)
Field Description
20–23 Channel 2 Input Filter
CH2FVAL
Selects the filter value for the channel input.
The filter is disabled when the value is zero.
24–27 Channel 1 Input Filter
CH1FVAL
Selects the filter value for the channel input.
The filter is disabled when the value is zero.
28–31 Channel 0 Input Filter
CH0FVAL
Selects the filter value for the channel input.
The filter is disabled when the value is zero.
23.4.20 Fault Control (FTMx_FLTCTRL)
This register selects the filter value for the fault inputs, enables the fault inputs and the
fault inputs filter.
Address: Base address + 7Ch offset
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
FAULT3EN
FAULT2EN
FAULT1EN
FAULT0EN
FFLTR3EN
FFLTR2EN
FFLTR1EN
FFLTR0EN
R 0
FFVAL
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FTMx_FLTCTRL field descriptions
Field Description
0–19 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
20–23 Fault Input Filter
FFVAL
Selects the filter value for the fault inputs.
The fault filter is disabled when the value is zero.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1198 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
FTMx_FLTCTRL field descriptions (continued)
Field Description
NOTE: Writing to this field has immediate effect and must be done only when the fault control or all fault
inputs are disabled. Failure to do this could result in a missing fault detection.
24 Fault Input 3 Filter Enable
FFLTR3EN
Enables the filter for the fault input.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 Fault input filter is disabled.
1 Fault input filter is enabled.
25 Fault Input 2 Filter Enable
FFLTR2EN
Enables the filter for the fault input.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 Fault input filter is disabled.
1 Fault input filter is enabled.
26 Fault Input 1 Filter Enable
FFLTR1EN
Enables the filter for the fault input.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 Fault input filter is disabled.
1 Fault input filter is enabled.
27 Fault Input 0 Filter Enable
FFLTR0EN
Enables the filter for the fault input.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 Fault input filter is disabled.
1 Fault input filter is enabled.
28 Fault Input 3 Enable
FAULT3EN
Enables the fault input.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 Fault input is disabled.
1 Fault input is enabled.
29 Fault Input 2 Enable
FAULT2EN
Enables the fault input.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 Fault input is disabled.
1 Fault input is enabled.
30 Fault Input 1 Enable
FAULT1EN
Enables the fault input.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1199
Memory map and register definition
FTMx_FLTCTRL field descriptions (continued)
Field Description
0 Fault input is disabled.
1 Fault input is enabled.
31 Fault Input 0 Enable
FAULT0EN
Enables the fault input.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 Fault input is disabled.
1 Fault input is enabled.
23.4.21 Quadrature Decoder Control And Status (FTMx_QDCTRL)
This register has the control and status bits for the Quadrature Decoder mode.
Address: Base address + 80h offset
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
QUADIR
TOFDIR
R 0
PHAFLTREN
PHBFLTREN
QUADMODE
QUADEN
PHAPOL
PHBPOL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1200 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
FTMx_QDCTRL field descriptions
Field Description
0–23 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
24 Phase A Input Filter Enable
PHAFLTREN
Enables the filter for the quadrature decoder phase A input. The filter value for the phase A input is
defined by the CH0FVAL field of FILTER. The phase A filter is also disabled when CH0FVAL is zero.
0 Phase A input filter is disabled.
1 Phase A input filter is enabled.
25 Phase B Input Filter Enable
PHBFLTREN
Enables the filter for the quadrature decoder phase B input. The filter value for the phase B input is
defined by the CH1FVAL field of FILTER. The phase B filter is also disabled when CH1FVAL is zero.
0 Phase B input filter is disabled.
1 Phase B input filter is enabled.
26 Phase A Input Polarity
PHAPOL
Selects the polarity for the quadrature decoder phase A input.
0 Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of
this signal.
1 Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this
signal.
27 Phase B Input Polarity
PHBPOL
Selects the polarity for the quadrature decoder phase B input.
0 Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of
this signal.
1 Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this
signal.
28 Quadrature Decoder Mode
QUADMODE
Selects the encoding mode used in the Quadrature Decoder mode.
0 Phase A and phase B encoding mode.
1 Count and direction encoding mode.
29 FTM Counter Direction In Quadrature Decoder Mode
QUADIR
Indicates the counting direction.
0 Counting direction is decreasing (FTM counter decrement).
1 Counting direction is increasing (FTM counter increment).
30 Timer Overflow Direction In Quadrature Decoder Mode
TOFDIR
Indicates if the TOF bit was set on the top or the bottom of counting.
0 TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter
changes from its minimum value (CNTIN register) to its maximum value (MOD register).
1 TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter
changes from its maximum value (MOD register) to its minimum value (CNTIN register).
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1201
Memory map and register definition
FTMx_QDCTRL field descriptions (continued)
Field Description
31 Quadrature Decoder Mode Enable
QUADEN
Enables the Quadrature Decoder mode. In this mode, the phase A and B input signals control the FTM
counter direction. The Quadrature Decoder mode has precedence over the other modes. See Table 23-6.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 Quadrature Decoder mode is disabled.
1 Quadrature Decoder mode is enabled.
23.4.22 Configuration (FTMx_CONF)
This register selects the number of times that the FTM counter overflow should occur
before the TOF bit to be set, the FTM behavior in modes, the use of an external global
time base, and the global time base signal generation.
Address: Base address + 84h offset
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
GTBEOUT
R 0 0 0 0
GTBEEN
NUMTOF
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FTMx_CONF field descriptions
Field Description
0–20 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
21 Global Time Base Output
GTBEOUT
Enables the global time base signal generation to other FTMs.
0 A global time base signal generation is disabled.
1
A global time base signal generation is enabled.
22 Global Time Base Enable
GTBEEN
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1202 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
FTMx_CONF field descriptions (continued)
Field Description
Configures the FTM to use an external global time base signal that is generated by another FTM.
0 Use of an external global time base is disabled.
1
Use of an external global time base is enabled.
23 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
24–25 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
26 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
27–31 TOF Frequency
NUMTOF
Selects the ratio between the number of counter overflows to the number of times the TOF bit is set.
NUMTOF = 0: The TOF bit is set for each counter overflow.
NUMTOF = 1: The TOF bit is set for the first counter overflow but not for the next overflow.
NUMTOF = 2: The TOF bit is set for the first counter overflow but not for the next 2 overflows.
NUMTOF = 3: The TOF bit is set for the first counter overflow but not for the next 3 overflows.
This pattern continues up to a maximum of 31.
23.4.23 FTM Fault Input Polarity (FTMx_FLTPOL)
This register defines the fault inputs polarity.
Address: Base address + 88h offset
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0
FLT3POL
FLT2POL
FLT1POL
FLT0POL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FTMx_FLTPOL field descriptions
Field Description
0–27 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1203
Memory map and register definition
FTMx_FLTPOL field descriptions (continued)
Field Description
28 Fault Input 3 Polarity
FLT3POL
Defines the polarity of the fault input.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 The fault input polarity is active high. A 1 at the fault input indicates a fault.
1 The fault input polarity is active low. A 0 at the fault input indicates a fault.
29 Fault Input 2 Polarity
FLT2POL
Defines the polarity of the fault input.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 The fault input polarity is active high. A 1 at the fault input indicates a fault.
1 The fault input polarity is active low. A 0 at the fault input indicates a fault.
30 Fault Input 1 Polarity
FLT1POL
Defines the polarity of the fault input.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 The fault input polarity is active high. A 1 at the fault input indicates a fault.
1 The fault input polarity is active low. A 0 at the fault input indicates a fault.
31 Fault Input 0 Polarity
FLT0POL
Defines the polarity of the fault input.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 The fault input polarity is active high. A 1 at the fault input indicates a fault.
1 The fault input polarity is active low. A 0 at the fault input indicates a fault.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1204 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
23.4.24 Synchronization Configuration (FTMx_SYNCONF)
This register selects the PWM synchronization configuration, SWOCTRL, INVCTRL
and CNTIN registers synchronization, if FTM clears the TRIGj bit, where j = 0, 1, 2,
when the hardware trigger j is detected.
Address: Base address + 8Ch offset
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
HWRSTCNT
HWWRBUF
R 0
HWINVC
HWSOC
HWOM
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
HWTRIGMOD
SYNCMODE
0 SWRSTCNT 0 0 0
SWWRBUF
R
SWINVC
SWSOC
CNTINC
SWOM
SWOC
INVC
E
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FTMx_SYNCONF field descriptions
Field Description
0–10 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
11 Software output control synchronization is activated by a hardware trigger.
HWSOC
0 A hardware trigger does not activate the SWOCTRL register synchronization.
1 A hardware trigger activates the SWOCTRL register synchronization.
12 Inverting control synchronization is activated by a hardware trigger.
HWINVC
0 A hardware trigger does not activate the INVCTRL register synchronization.
1 A hardware trigger activates the INVCTRL register synchronization.
13 Output mask synchronization is activated by a hardware trigger.
HWOM
0 A hardware trigger does not activate the OUTMASK register synchronization.
1 A hardware trigger activates the OUTMASK register synchronization.
14 MOD, CNTIN, and CV registers synchronization is activated by a hardware trigger.
HWWRBUF
0 A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization.
1 A hardware trigger activates MOD, CNTIN, and CV registers synchronization.
15 FTM counter synchronization is activated by a hardware trigger.
HWRSTCNT
0 A hardware trigger does not activate the FTM counter synchronization.
1 A hardware trigger activates the FTM counter synchronization.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1205
Memory map and register definition
FTMx_SYNCONF field descriptions (continued)
Field Description
16–18 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
19 Software output control synchronization is activated by the software trigger.
SWSOC
0 The software trigger does not activate the SWOCTRL register synchronization.
1 The software trigger activates the SWOCTRL register synchronization.
20 Inverting control synchronization is activated by the software trigger.
SWINVC
0 The software trigger does not activate the INVCTRL register synchronization.
1 The software trigger activates the INVCTRL register synchronization.
21 Output mask synchronization is activated by the software trigger.
SWOM
0 The software trigger does not activate the OUTMASK register synchronization.
1 The software trigger activates the OUTMASK register synchronization.
22 MOD, CNTIN, and CV registers synchronization is activated by the software trigger.
SWWRBUF
0 The software trigger does not activate MOD, CNTIN, and CV registers synchronization.
1 The software trigger activates MOD, CNTIN, and CV registers synchronization.
23 FTM counter synchronization is activated by the software trigger.
SWRSTCNT
0 The software trigger does not activate the FTM counter synchronization.
1 The software trigger activates the FTM counter synchronization.
24 Synchronization Mode
SYNCMODE
Selects the PWM Synchronization mode.
0 Legacy PWM synchronization is selected.
1 Enhanced PWM synchronization is selected.
25 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
26 SWOCTRL Register Synchronization
SWOC
0 SWOCTRL register is updated with its buffer value at all rising edges of system clock.
1 SWOCTRL register is updated with its buffer value by the PWM synchronization.
27 INVCTRL Register Synchronization
INVC
0 INVCTRL register is updated with its buffer value at all rising edges of system clock.
1 INVCTRL register is updated with its buffer value by the PWM synchronization.
28 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
29 CNTIN Register Synchronization
CNTINC
0 CNTIN register is updated with its buffer value at all rising edges of system clock.
1 CNTIN register is updated with its buffer value by the PWM synchronization.
30 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
31 Hardware Trigger Mode
HWTRIGMODE
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1206 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
FTMx_SYNCONF field descriptions (continued)
Field Description
0 FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.
1 FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.
23.4.25 FTM Inverting Control (FTMx_INVCTRL)
This register controls when the channel (n) output becomes the channel (n+1) output, and
channel (n+1) output becomes the channel (n) output. Each INVmEN bit enables the
inverting operation for the corresponding pair channels m.
This register has a write buffer. The INVmEN bit is updated by the INVCTRL register
synchronization.
Address: Base address + 90h offset
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0
INV3EN
INV2EN
INV1EN
INV0EN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FTMx_INVCTRL field descriptions
Field Description
0–27 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
28 Pair Channels 3 Inverting Enable
INV3EN
0 Inverting is disabled.
1 Inverting is enabled.
29 Pair Channels 2 Inverting Enable
INV2EN
0 Inverting is disabled.
1 Inverting is enabled.
30 Pair Channels 1 Inverting Enable
INV1EN
0 Inverting is disabled.
1 Inverting is enabled.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1207
Memory map and register definition
FTMx_INVCTRL field descriptions (continued)
Field Description
31 Pair Channels 0 Inverting Enable
INV0EN
0 Inverting is disabled.
1 Inverting is enabled.
23.4.26 FTM Software Output Control (FTMx_SWOCTRL)
This register enables software control of channel (n) output and defines the value forced
to the channel (n) output:
• The CHnOC bits enable the control of the corresponding channel (n) output by
software.
• The CHnOCV bits select the value that is forced at the corresponding channel (n)
output.
This register has a write buffer. The fields are updated by the SWOCTRL register
synchronization.
Address: Base address + 94h offset
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
CH7OCV
CH6OCV
CH5OCV
CH4OCV
CH3OCV
CH2OCV
CH1OCV
CH0OCV
CH7OC
CH6OC
CH5OC
CH4OC
CH3OC
CH2OC
CH1OC
CH0OC
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FTMx_SWOCTRL field descriptions
Field Description
0–15 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
16 Channel 7 Software Output Control Value
CH7OCV
0 The software output control forces 0 to the channel output.
1 The software output control forces 1 to the channel output.
17 Channel 6 Software Output Control Value
CH6OCV
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1208 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
FTMx_SWOCTRL field descriptions (continued)
Field Description
0 The software output control forces 0 to the channel output.
1 The software output control forces 1 to the channel output.
18 Channel 5 Software Output Control Value
CH5OCV
0 The software output control forces 0 to the channel output.
1 The software output control forces 1 to the channel output.
19 Channel 4 Software Output Control Value
CH4OCV
0 The software output control forces 0 to the channel output.
1 The software output control forces 1 to the channel output.
20 Channel 3 Software Output Control Value
CH3OCV
0 The software output control forces 0 to the channel output.
1 The software output control forces 1 to the channel output.
21 Channel 2 Software Output Control Value
CH2OCV
0 The software output control forces 0 to the channel output.
1 The software output control forces 1 to the channel output.
22 Channel 1 Software Output Control Value
CH1OCV
0 The software output control forces 0 to the channel output.
1 The software output control forces 1 to the channel output.
23 Channel 0 Software Output Control Value
CH0OCV
0 The software output control forces 0 to the channel output.
1 The software output control forces 1 to the channel output.
24 Channel 7 Software Output Control Enable
CH7OC
0 The channel output is not affected by software output control.
1 The channel output is affected by software output control.
25 Channel 6 Software Output Control Enable
CH6OC
0 The channel output is not affected by software output control.
1 The channel output is affected by software output control.
26 Channel 5 Software Output Control Enable
CH5OC
0 The channel output is not affected by software output control.
1 The channel output is affected by software output control.
27 Channel 4 Software Output Control Enable
CH4OC
0 The channel output is not affected by software output control.
1 The channel output is affected by software output control.
28 Channel 3 Software Output Control Enable
CH3OC
0 The channel output is not affected by software output control.
1 The channel output is affected by software output control.
29 Channel 2 Software Output Control Enable
CH2OC
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1209
Memory map and register definition
FTMx_SWOCTRL field descriptions (continued)
Field Description
0 The channel output is not affected by software output control.
1 The channel output is affected by software output control.
30 Channel 1 Software Output Control Enable
CH1OC
0 The channel output is not affected by software output control.
1 The channel output is affected by software output control.
31 Channel 0 Software Output Control Enable
CH0OC
0 The channel output is not affected by software output control.
1 The channel output is affected by software output control.
23.4.27 FTM PWM Load (FTMx_PWMLOAD)
Enables the loading of the MOD, CNTIN, C(n)V, and C(n+1)V registers with the values
of their write buffers when the FTM counter changes from the MOD register value to its
next value or when a channel (j) match occurs. A match occurs for the channel (j) when
FTM counter = C(j)V.
Address: Base address + 98h offset
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0
CH7SEL
CH6SEL
CH5SEL
CH4SEL
CH3SEL
CH2SEL
CH1SEL
CH0SEL
LDOK
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FTMx_PWMLOAD field descriptions
Field Description
0–21 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
22 Load Enable
LDOK
Enables the loading of the MOD, CNTIN, and CV registers with the values of their write buffers.
0 Loading updated values is disabled.
1 Loading updated values is enabled.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1210 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
FTMx_PWMLOAD field descriptions (continued)
Field Description
23 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
24 Channel 7 Select
CH7SEL
0 Do not include the channel in the matching process.
1 Include the channel in the matching process.
25 Channel 6 Select
CH6SEL
0 Do not include the channel in the matching process.
1 Include the channel in the matching process.
26 Channel 5 Select
CH5SEL
0 Do not include the channel in the matching process.
1 Include the channel in the matching process.
27 Channel 4 Select
CH4SEL
0 Do not include the channel in the matching process.
1 Include the channel in the matching process.
28 Channel 3 Select
CH3SEL
0 Do not include the channel in the matching process.
1 Include the channel in the matching process.
29 Channel 2 Select
CH2SEL
0 Do not include the channel in the matching process.
1 Include the channel in the matching process.
30 Channel 1 Select
CH1SEL
0 Do not include the channel in the matching process.
1 Include the channel in the matching process.
31 Channel 0 Select
CH0SEL
0 Do not include the channel in the matching process.
1 Include the channel in the matching process.
23.5 Functional description
The notation used in this document to represent the counters and the generation of the
signals is shown in the following figure.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1211
Functional description
FTM counting is up.
Channel (n) is in high-true EPWM mode.
PS[2:0] = 001
CNTIN = 0x0000
MOD = 0x0004
CnV = 0x0002
prescaler counter 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
FTM counter 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2
channel (n) output
counter channel (n) counter channel (n) counter channel (n)
overflow match overflow match overflow match
Figure 23-2. Notation used
23.5.1 Clock source
The FTM has only one clock domain: the system clock.
23.5.1.1 Counter clock source
The CLKS[1:0] bits in the SC register selects clock sources for the FTM counter or
disables the FTM counter. After any chip reset, CLKS[1:0] = 0:0 so no clock source is
selected.
The CLKS[1:0] bits may be read or written at any time. Disabling the FTM counter by
writing 0:0 to the CLKS[1:0] bits does not affect the FTM counter value or other
registers.
The fixed frequency clock is an alternative clock source for the FTM counter that allows
the selection of a clock other than the system clock or an external clock. This clock input
is defined by chip integration; see the chip-specific FTM information for further details.
Due to FTM hardware implementation limitations, the frequency of the fixed frequency
clock must not exceed 1/2 of the system clock frequency.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1212 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
The external clock passes through a synchronizer clocked by the system clock to assure
that counter transitions are properly aligned to system clock transitions.Therefore, to
meet Nyquist criteria considering also jitter, the frequency of the external clock source
must not exceed 1/4 of the system clock frequency.
23.5.2 Prescaler
The selected counter clock source passes through a prescaler that is a 7-bit counter. The
value of the prescaler is selected by the PS[2:0] bits. The following figure shows an
example of the prescaler counter and FTM counter.
FTM counting is up.
PS[2:0] = 001
CNTIN = 0x0000
MOD = 0x0003
selected input clock
prescaler counter 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
FTM counter 0 1 2 3 0 1 2 3 0 1
Figure 23-3. Example of the prescaler counter
23.5.3 Counter
The FTM has a 16-bit counter that is used by the channels either for input or output
modes. The FTM counter clock is the selected clock divided by the prescaler.
The FTM counter has these modes of operation:
• Up counting
• Up-down counting
• Quadrature Decoder mode
23.5.3.1 Up counting
Up counting is selected when:
• QUADEN = 0, and
• CPWMS = 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1213
Functional description
CNTIN defines the starting value of the count and MOD defines the final value of the
count, see the following figure. The value of CNTIN is loaded into the FTM counter, and
the counter increments until the value of MOD is reached, at which point the counter is
reloaded with the value of CNTIN.
The FTM period when using up counting is (MOD – CNTIN + 0x0001) × period of the
FTM counter clock.
The TOF bit is set when the FTM counter changes from MOD to CNTIN.
FTM counting is up.
CNTIN = 0xFFFC (in two's complement is equal to -4)
MOD = 0x0004
FTM counter (in decimal values) 4 -4 -3 -2 -1 0 1 2 3 4 -4 -3 -2 -1 0 1 2 3 4 -4 -3
TOF bit
set TOF bit set TOF bit set TOF bit
period of FTM counter clock
period of counting = (MOD - CNTIN + 0x0001) x period of FTM counter clock
Figure 23-4. Example of FTM up and signed counting
Table 23-8. FTM counting based on CNTIN value
When Then
CNTIN = 0x0000 The FTM counting is equivalent to TPM up counting, that is,
up and unsigned counting. See the following figure.
CNTIN[15] = 1 The initial value of the FTM counter is a negative number in
two's complement, so the FTM counting is up and signed.
CNTIN[15] = 0 and CNTIN ≠ 0x0000 The initial value of the FTM counter is a positive number, so
the FTM counting is up and unsigned.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1214 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
FTM counting is up
CNTIN = 0x0000
MOD = 0x0004
FTM counter 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2
TOF bit
set TOF bit set TOF bit set TOF bit
period of FTM counter clock
period of counting = (MOD - CNTIN + 0x0001) x period of FTM counter clock
= (MOD + 0x0001) x period of FTM counter clock
Figure 23-5. Example of FTM up counting with CNTIN = 0x0000
Note
• FTM operation is only valid when the value of the CNTIN
register is less than the value of the MOD register, either in
the unsigned counting or signed counting. It is the
responsibility of the software to ensure that the values in
the CNTIN and MOD registers meet this requirement. Any
values of CNTIN and MOD that do not satisfy this criteria
can result in unpredictable behavior.
• MOD = CNTIN is a redundant condition. In this case, the
FTM counter is always equal to MOD and the TOF bit is
set in each rising edge of the FTM counter clock.
• When MOD = 0x0000, CNTIN = 0x0000, for example
after reset, and FTMEN = 1, the FTM counter remains
stopped at 0x0000 until a non-zero value is written into the
MOD or CNTIN registers.
• Setting CNTIN to be greater than the value of MOD is not
recommended as this unusual setting may make the FTM
operation difficult to comprehend. However, there is no
restriction on this configuration, and an example is shown
in the following figure.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1215
Functional description
FTM counting is up
MOD = 0x0005
CNTIN = 0x0015
load of CNTIN load of CNTIN
FTM counter 0x0005 0x0015 0x0016 ... 0xFFFE 0xFFFF 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0015 0x0016 ...
...
TOF bit
set TOF bit set TOF bit
Figure 23-6. Example of up counting when the value of CNTIN is greater than the value
of MOD
23.5.3.2 Up-down counting
Up-down counting is selected when:
• QUADEN = 0, and
• CPWMS = 1
CNTIN defines the starting value of the count and MOD defines the final value of the
count. The value of CNTIN is loaded into the FTM counter, and the counter increments
until the value of MOD is reached, at which point the counter is decremented until it
returns to the value of CNTIN and the up-down counting restarts.
The FTM period when using up-down counting is 2 × (MOD – CNTIN) × period of the
FTM counter clock.
The TOF bit is set when the FTM counter changes from MOD to (MOD – 1).
If (CNTIN = 0x0000), the FTM counting is equivalent to TPM up-down counting, that is,
up-down and unsigned counting. See the following figure.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1216 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
FTM counting is up-down
CNTIN = 0x0000
MOD = 0x0004
FTM counter 0 1 2 3 4 3 2 1 0 1 2 3 4 3 2 1 0 1 2 3 4
TOF bit
set TOF bit set TOF bit
period of FTM counter clock
period of counting = 2 x (MOD - CNTIN) x period of FTM counter clock
= 2 x MOD x period of FTM counter clock
Figure 23-7. Example of up-down counting when CNTIN = 0x0000
Note
When CNTIN is different from zero in the up-down counting, a
valid CPWM signal is generated:
• if CnV > CNTIN, or
• if CnV = 0 or if CnV[15] = 1. In this case, 0% CPWM is
generated.
23.5.3.3 Free running counter
If (FTMEN = 0) and (MOD = 0x0000 or MOD = 0xFFFF), the FTM counter is a free
running counter. In this case, the FTM counter runs free from 0x0000 through 0xFFFF
and the TOF bit is set when the FTM counter changes from 0xFFFF to 0x0000. See the
following figure.
FTMEN = 0
MOD = 0x0000
FTM counter ... 0x0003 0x0004 ... 0xFFFE 0xFFFF 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 ...
TOF bit
set TOF bit
Figure 23-8. Example when the FTM counter is free running
The FTM counter is also a free running counter when:
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1217
Functional description
• FTMEN = 1
• QUADEN = 0
• CPWMS = 0
• CNTIN = 0x0000, and
• MOD = 0xFFFF
23.5.3.4 Counter reset
Any one of the following cases resets the FTM counter to the value in the CNTIN register
and the channels output to its initial value, except for channels in Output Compare mode.
• Any write to CNT.
• FTM counter synchronization.
23.5.3.5 When the TOF bit is set
The NUMTOF[4:0] bits define the number of times that the FTM counter overflow
should occur before the TOF bit to be set. If NUMTOF[4:0] = 0x00, then the TOF bit is
set at each FTM counter overflow.
Initialize the FTM counter, by writing to CNT, after writing to the NUMTOF[4:0] bits to
avoid confusion about when the first counter overflow will occur.
FTM counter
NUMTOF[4:0] 0x02
TOF counter 0x01 0x02 0x00 0x01 0x02 0x00 0x01 0x02
set TOF bit
Figure 23-9. Periodic TOF when NUMTOF = 0x02
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1218 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
FTM counter
NUMTOF[4:0] 0x00
TOF counter 0x00
set TOF bit
Figure 23-10. Periodic TOF when NUMTOF = 0x00
23.5.4 Input Capture mode
The Input Capture mode is selected when:
• DECAPEN = 0
• COMBINE = 0
• CPWMS = 0
• MSnB:MSnA = 0:0, and
• ELSnB:ELSnA ≠ 0:0
When a selected edge occurs on the channel input, the current value of the FTM counter
is captured into the CnV register, at the same time the CHnF bit is set and the channel
interrupt is generated if enabled by CHnIE = 1. See the following figure.
When a channel is configured for input capture, the FTMxCHn pin is an edge-sensitive
input. ELSnB:ELSnA control bits determine which edge, falling or rising, triggers input-
capture event. Note that the maximum frequency for the channel input signal to be
detected correctly is system clock divided by 4, which is required to meet Nyquist criteria
for signal sampling.
Writes to the CnV register is ignored in Input Capture mode.
While in , the input capture function works as configured. When a selected edge event
occurs, the FTM counter value, which is frozen because of , is captured into the CnV
register and the CHnF bit is set.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1219
Functional description
was rising
edge selected?
is filter
enabled? channel (n) interrupt
0 0 CHnIE
CHnF
synchronizer rising edge 1
0
channel (n) input DQ DQ edge
detector CnV
Filter* 1
system clock CLK CLK 1
falling edge
0 0
was falling
edge selected?
* Filtering function is only available in the inputs of channel 0, 1, 2, and 3 FTM counter
Figure 23-11. Input Capture mode
If the channel input does not have a filter enabled, then the input signal is always delayed
3 rising edges of the system clock, that is, two rising edges to the synchronizer plus one
more rising edge to the edge detector. In other words, the CHnF bit is set on the third
rising edge of the system clock after a valid edge occurs on the channel input.
23.5.4.1 Filter for Input Capture mode
The filter function is only available on channels 0, 1, 2, and 3.
First, the input signal is synchronized by the system clock. Following synchronization,
the input signal enters the filter block. See the following figure.
CHnFVAL[3:0]
Logic to control
channel (n) input after the filter counter
the synchronizer filter output
S Q
filter counter Logic to define
C
the filter output
divided by 4
CLK
system clock
Figure 23-12. Channel input filter
When there is a state change in the input signal, the counter is reset and starts counting
up. As long as the new state is stable on the input, the counter continues to increment.
When the counter is equal to CHnFVAL[3:0], the state change of the input signal is
validated. It is then transmitted as a pulse edge to the edge detector.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1220 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
If the opposite edge appears on the input signal before it can be validated, the counter is
reset. At the next input transition, the counter starts counting again. Any pulse that is
shorter than the minimum value selected by CHnFVAL[3:0] (× 4 system clocks) is
regarded as a glitch and is not passed on to the edge detector. A timing diagram of the
input filter is shown in the following figure.
The filter function is disabled when CHnFVAL[3:0] bits are zero. In this case, the input
signal is delayed 3 rising edges of the system clock. If (CHnFVAL[3:0] ≠ 0000), then the
input signal is delayed by the minimum pulse width (CHnFVAL[3:0] × 4 system clocks)
plus a further 4 rising edges of the system clock: two rising edges to the synchronizer,
one rising edge to the filter output, plus one more to the edge detector. In other words,
CHnF is set (4 + 4 × CHnFVAL[3:0]) system clock periods after a valid edge occurs on
the channel input.
The clock for the counter in the channel input filter is the system clock divided by 4.
system clock divided by 4
channel (n) input
after the synchronizer
counte r
CHnFVAL[3:0] = 0100
(binary value)
Time
filter output *
* Note: Filter output is delayed one system clock of filter counter logic output.
Figure 23-13. Channel input filter example
The figure below shows an example of input capture with filter enabled and the delay
added by each part of the input capture logic. Note that the input signal is delayed only by
the synchronizer and edge dector logic if the filter is disabled.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1221
Functional description
filter edge
output detector
synchronizer delay filter counter delay delay delay
system clock
channel (n) input
FTM counter 1 2 3 4 5 6 7 8 9 10 11 12 13
CHnFVAL[3:0] 2
filter counter 1 2 1
filter output
C(n)V 0 12
CHnF
Figure 23-14. Input capture example
23.5.5 Output Compare mode
The Output Compare mode is selected when:
• DECAPEN = 0
• COMBINE = 0
• CPWMS = 0, and
• MSnB:MSnA = 0:1
In Output Compare mode, the FTM can generate timed pulses with programmable
position, polarity, duration, and frequency. When the counter matches the value in the
CnV register of an output compare channel, the channel (n) output can be set, cleared, or
toggled.
When a channel is initially configured to Toggle mode, the previous value of the channel
output is held until the first output compare event occurs.
The CHnF bit is set and the channel (n) interrupt is generated if CHnIE = 1 at the channel
(n) match (FTM counter = CnV).
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1222 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
MOD = 0x0005
CnV = 0x0003
counter channel (n) counter channel (n) counter
overflow match overflow match overflow
CNT ... 0 1 2 3 4 5 0 1 2 3 4 5 0 1 ...
channel (n) output previous value
CHnF bit previous value
TOF bit
Figure 23-15. Example of the Output Compare mode when the match toggles the
channel output
MOD = 0x0005
CnV = 0x0003
counter channel (n) counter channel (n) counter
overflow match overflow match overflow
CNT ... 0 1 2 3 4 5 0 1 2 3 4 5 0 1 ...
channel (n) output previous value
CHnF bit previous value
TOF bit
Figure 23-16. Example of the Output Compare mode when the match clears the channel
output
MOD = 0x0005
CnV = 0x0003
counter channel (n) counter channel (n) counter
overflow match overflow match overflow
CNT ... 0 1 2 3 4 5 0 1 2 3 4 5 0 1 ...
channel (n) output previous value
CHnF bit previous value
TOF bit
Figure 23-17. Example of the Output Compare mode when the match sets the channel
output
If (ELSnB:ELSnA = 0:0) when the counter reaches the value in the CnV register, the
CHnF bit is set and the channel (n) interrupt is generated if CHnIE = 1, however the
channel (n) output is not modified and controlled by FTM.
23.5.6 Edge-Aligned PWM (EPWM) mode
The Edge-Aligned mode is selected when:
• QUADEN = 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1223
Functional description
• DECAPEN = 0
• COMBINE = 0
• CPWMS = 0, and
• MSnB = 1
The EPWM period is determined by (MOD − CNTIN + 0x0001) and the pulse width
(duty cycle) is determined by (CnV − CNTIN).
The CHnF bit is set and the channel (n) interrupt is generated if CHnIE = 1 at the channel
(n) match (FTM counter = CnV), that is, at the end of the pulse width.
This type of PWM signal is called edge-aligned because the leading edges of all PWM
signals are aligned with the beginning of the period, which is the same for all channels
within an FTM.
counter overflow counter overflow counter overflow
period
pulse
width
channel (n) output
channel (n) match channel (n) match channel (n) match
Figure 23-18. EPWM period and pulse width with ELSnB:ELSnA = 1:0
If (ELSnB:ELSnA = 0:0) when the counter reaches the value in the CnV register, the
CHnF bit is set and the channel (n) interrupt is generated if CHnIE = 1, however the
channel (n) output is not controlled by FTM.
If (ELSnB:ELSnA = 1:0), then the channel (n) output is forced high at the counter
overflow when the CNTIN register value is loaded into the FTM counter, and it is forced
low at the channel (n) match (FTM counter = CnV). See the following figure.
MOD = 0x0008
CnV = 0x0005
counter channel (n) counter
overflow match overflow
CNT ... 0 1 2 3 4 5 6 7 8 0 1 2 ...
channel (n) output
CHnF bit previous value
TOF bit
Figure 23-19. EPWM signal with ELSnB:ELSnA = 1:0
If (ELSnB:ELSnA = X:1), then the channel (n) output is forced low at the counter
overflow when the CNTIN register value is loaded into the FTM counter, and it is forced
high at the channel (n) match (FTM counter = CnV). See the following figure.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1224 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
MOD = 0x0008
CnV = 0x0005 counter channel (n) counter
overflow match overflow
CNT ... 0 1 2 3 4 5 6 7 8 0 1 2 ...
channel (n) output
CHnF bit previous value
TOF bit
Figure 23-20. EPWM signal with ELSnB:ELSnA = X:1
If (CnV = 0x0000), then the channel (n) output is a 0% duty cycle EPWM signal and
CHnF bit is not set even when there is the channel (n) match.
If (CnV > MOD), then the channel (n) output is a 100% duty cycle EPWM signal and
CHnF bit is not set.Therefore, MOD must be less than 0xFFFF in order to get a 100%
duty cycle EPWM signal.
Note
When CNTIN is different from zero the following EPWM
signals can be generated:
• 0% EPWM signal if CnV = CNTIN,
• EPWM signal between 0% and 100% if CNTIN < CnV <=
MOD,
• 100% EPWM signal when CNTIN > CnV or CnV > MOD.
23.5.7 Center-Aligned PWM (CPWM) mode
The Center-Aligned mode is selected when:
• QUADEN = 0
• DECAPEN = 0
• COMBINE = 0, and
• CPWMS = 1
The CPWM pulse width (duty cycle) is determined by 2 × (CnV − CNTIN) and the
period is determined by 2 × (MOD − CNTIN). See the following figure. MOD must be
kept in the range of 0x0001 to 0x7FFF because values outside this range can produce
ambiguous results.
In the CPWM mode, the FTM counter counts up until it reaches MOD and then counts
down until it reaches CNTIN.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1225
Functional description
The CHnF bit is set and channel (n) interrupt is generated (if CHnIE = 1) at the channel
(n) match (FTM counter = CnV) when the FTM counting is down (at the begin of the
pulse width) and when the FTM counting is up (at the end of the pulse width).
This type of PWM signal is called center-aligned because the pulse width centers for all
channels are aligned with the value of CNTIN.
The other channel modes are not compatible with the up-down counter (CPWMS = 1).
Therefore, all FTM channels must be used in CPWM mode when (CPWMS = 1).
FTM counter = CNTIN
counter overflow channel (n) match channel (n) match counter overflow
FTM counter = (FTM counting (FTM counting FTM counter =
MOD is down) is up) MOD
channel (n) output
pulse width
2 x (CnV - CNTIN)
period
2 x (MOD - CNTIN)
Figure 23-21. CPWM period and pulse width with ELSnB:ELSnA = 1:0
If (ELSnB:ELSnA = 0:0) when the FTM counter reaches the value in the CnV register,
the CHnF bit is set and the channel (n) interrupt is generated (if CHnIE = 1), however the
channel (n) output is not controlled by FTM.
If (ELSnB:ELSnA = 1:0), then the channel (n) output is forced high at the channel (n)
match (FTM counter = CnV) when counting down, and it is forced low at the channel (n)
match when counting up. See the following figure.
MOD = 0x0008 counter counter
CnV = 0x0005 overflow overflow
channel (n) match in channel (n) match in channel (n) match in
down counting up counting down counting
CNT ... 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 ...
channel (n) output
CHnF bit previous value
TOF bit
Figure 23-22. CPWM signal with ELSnB:ELSnA = 1:0
If (ELSnB:ELSnA = X:1), then the channel (n) output is forced low at the channel (n)
match (FTM counter = CnV) when counting down, and it is forced high at the channel (n)
match when counting up. See the following figure.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1226 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
MOD = 0x0008 counter counter
overflow overflow
CnV = 0x0005
channel (n) match in channel (n) match in channel (n) match in
down counting up counting down counting
CNT ... 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 ...
channel (n) output
CHnF bit previous value
TOF bit
Figure 23-23. CPWM signal with ELSnB:ELSnA = X:1
If (CnV = 0x0000) or CnV is a negative value, that is (CnV[15] = 1), then the channel (n)
output is a 0% duty cycle CPWM signal and CHnF bit is not set even when there is the
channel (n) match.
If CnV is a positive value, that is (CnV[15] = 0), (CnV ≥ MOD), and (MOD ≠ 0x0000),
then the channel (n) output is a 100% duty cycle CPWM signal and CHnF bit is not set
even when there is the channel (n) match. This implies that the usable range of periods
set by MOD is 0x0001 through 0x7FFE, 0x7FFF if you do not need to generate a 100%
duty cycle CPWM signal. This is not a significant limitation because the resulting period
is much longer than required for normal applications.
The CPWM mode must not be used when the FTM counter is a free running counter.
23.5.8 Combine mode
The Combine mode is selected when:
• QUADEN = 0
• DECAPEN = 0
• COMBINE = 1, and
• CPWMS = 0
In Combine mode, an even channel (n) and adjacent odd channel (n+1) are combined to
generate a PWM signal in the channel (n) output.
In the Combine mode, the PWM period is determined by (MOD − CNTIN + 0x0001) and
the PWM pulse width (duty cycle) is determined by (|C(n+1)V − C(n)V|).
The CHnF bit is set and the channel (n) interrupt is generated (if CHnIE = 1) at the
channel (n) match (FTM counter = C(n)V). The CH(n+1)F bit is set and the channel (n
+1) interrupt is generated, if CH(n+1)IE = 1, at the channel (n+1) match (FTM counter =
C(n+1)V).
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1227
Functional description
If (ELSnB:ELSnA = 1:0), then the channel (n) output is forced low at the beginning of
the period (FTM counter = CNTIN) and at the channel (n+1) match (FTM counter = C(n
+1)V). It is forced high at the channel (n) match (FTM counter = C(n)V). See the
following figure.
If (ELSnB:ELSnA = X:1), then the channel (n) output is forced high at the beginning of
the period (FTM counter = CNTIN) and at the channel (n+1) match (FTM counter = C(n
+1)V). It is forced low at the channel (n) match (FTM counter = C(n)V). See the
following figure.
In Combine mode, the ELS(n+1)B and ELS(n+1)A bits are not used in the generation of
the channels (n) and (n+1) output. However, if (ELSnB:ELSnA = 0:0) then the channel
(n) output is not controlled by FTM, and if (ELS(n+1)B:ELS(n+1)A = 0:0) then the
channel (n+1) output is not controlled by FTM.
channel (n+1) match
FTM counter
channel (n) match
channel (n) output
with ELSnB:ELSnA = 1:0
channel (n) output
with ELSnB:ELSnA = X:1
Figure 23-24. Combine mode
The following figures illustrate the PWM signals generation using Combine mode.
FTM counter
MOD
C(n+1)V
C(n)V
CNTIN
channel (n) output
with ELSnB:ELSnA = 1:0
channel (n) output
with ELSnB:ELSnA = X:1
Figure 23-25. Channel (n) output if (CNTIN < C(n)V < MOD) and (CNTIN < C(n+1)V < MOD)
and (C(n)V < C(n+1)V)
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1228 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
FTM counter
MOD = C(n+1)V
C(n)V
CNTIN
channel (n) output
with ELSnB:ELSnA = 1:0
channel (n) output
with ELSnB:ELSnA = X:1
Figure 23-26. Channel (n) output if (CNTIN < C(n)V < MOD) and (C(n+1)V = MOD)
FTM counter
MOD
C(n+1)V
C(n)V = CNTIN
channel (n) output
with ELSnB:ELSnA = 1:0
channel (n) output
with ELSnB:ELSnA = X:1
Figure 23-27. Channel (n) output if (C(n)V = CNTIN) and (CNTIN < C(n+1)V < MOD)
FTM counter
MOD = C(n+1)V
C(n)V
CNTIN
not fully 100% duty cycle
channel (n) output
with ELSnB:ELSnA = 1:0
channel (n) output not fully 0% duty cycle
with ELSnB:ELSnA = X:1
Figure 23-28. Channel (n) output if (CNTIN < C(n)V < MOD) and (C(n)V is Almost Equal to
CNTIN) and (C(n+1)V = MOD)
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1229
Functional description
FTM counter
MOD
C(n+1)V
C(n)V = CNTIN
not fully 100% duty cycle
channel (n) output
with ELSnB:ELSnA = 1:0
channel (n) output not fully 0% duty cycle
with ELSnB:ELSnA = X:1
Figure 23-29. Channel (n) output if (C(n)V = CNTIN) and (CNTIN < C(n+1)V < MOD) and
(C(n+1)V is Almost Equal to MOD)
FTM counter
C(n+1)V
MOD
CNTIN
C(n)V
channel (n) output 0% duty cycle
with ELSnB:ELSnA = 1:0
channel (n) output
with ELSnB:ELSnA = X:1 100% duty cycle
Figure 23-30. Channel (n) output if C(n)V and C(n+1)V are not between CNTIN and MOD
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1230 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
FTM counter
MOD
C(n+1)V = C(n)V
CNTIN
channel (n) output 0% duty cycle
with ELSnB:ELSnA = 1:0
channel (n) output 100% duty cycle
with ELSnB:ELSnA = X:1
Figure 23-31. Channel (n) output if (CNTIN < C(n)V < MOD) and (CNTIN < C(n+1)V < MOD)
and (C(n)V = C(n+1)V)
FTM counter
MOD
C(n)V =
C(n+1)V = CNTIN
channel (n) output 0% duty cycle
with ELSnB:ELSnA = 1:0
channel (n) output
100% duty cycle
with ELSnB:ELSnA = X:1
Figure 23-32. Channel (n) output if (C(n)V = C(n+1)V = CNTIN)
MOD = FTM counter
C(n+1)V =
C(n)V
CNTIN
channel (n) output
0% duty cycle
with ELSnB:ELSnA = 1:0
channel (n) output
100% duty cycle
with ELSnB:ELSnA = X:1
Figure 23-33. Channel (n) output if (C(n)V = C(n+1)V = MOD)
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1231
Functional description
FTM counter
MOD
C(n)V
C(n+1)V
CNTIN
channel (n) match
is ignored
channel (n) output 0% duty cycle
with ELSnB:ELSnA = 1:0
channel (n) output 100% duty cycle
with ELSnB:ELSnA = X:1
Figure 23-34. Channel (n) output if (CNTIN < C(n)V < MOD) and (CNTIN < C(n+1)V < MOD)
and (C(n)V > C(n+1)V)
FTM counter
MOD
C(n+1)V
CNTIN
C(n)V
channel (n) output 0% duty cycle
with ELSnB:ELSnA = 1:0
channel (n) output 100% duty cycle
with ELSnB:ELSnA = X:1
Figure 23-35. Channel (n) output if (C(n)V < CNTIN) and (CNTIN < C(n+1)V < MOD)
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1232 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
FTM counter
MOD
C(n)V
CNTIN
C(n+1)V
channel (n) output
with ELSnB:ELSnA = 1:0
channel (n) output
with ELSnB:ELSnA = X:1
Figure 23-36. Channel (n) output if (C(n+1)V < CNTIN) and (CNTIN < C(n)V < MOD)
FTM counter
C(n)V
MOD
C(n+1)V
CNTIN
channel (n) output 0% duty cycle
with ELSnB:ELSnA = 1:0
channel (n) output 100% duty cycle
with ELSnB:ELSnA = X:1
Figure 23-37. Channel (n) output if (C(n)V > MOD) and (CNTIN < C(n+1)V < MOD)
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1233
Functional description
FTM counter
C(n+1)V
MOD
C(n)V
CNTIN
channel (n) output
with ELSnB:ELSnA = 1:0
channel (n) output
with ELSnB:ELSnA = X:1
Figure 23-38. Channel (n) output if (C(n+1)V > MOD) and (CNTIN < C(n)V < MOD)
FTM counter
C(n+1)V
MOD = C(n)V
CNTIN
channel (n) output
not fully 0% duty cycle
with ELSnB:ELSnA = 1:0
channel (n) output
not fully 100% duty cycle
with ELSnB:ELSnA = X:1
Figure 23-39. Channel (n) output if (C(n+1)V > MOD) and (CNTIN < C(n)V = MOD)
23.5.8.1 Asymmetrical PWM
In Combine mode, the control of the PWM signal first edge, when the channel (n) match
occurs, that is, FTM counter = C(n)V, is independent of the control of the PWM signal
second edge, when the channel (n+1) match occurs, that is, FTM counter = C(n+1)V. So,
Combine mode allows the generation of asymmetrical PWM signals.
23.5.9 Complementary mode
The Complementary mode is selected when:
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1234 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
• QUADEN = 0
• DECAPEN = 0
• COMP = 1
In Complementary mode, the channel (n+1) output is the inverse of the channel (n)
output.
So, the channel (n+1) output is the same as the channel (n) output when:
• QUADEN = 0
• DECAPEN = 0
• COMP = 0
channel (n+1) match
FTM counter
channel (n) match
channel (n) output
with ELSnB:ELSnA = 1:0
channel (n+1) output
with COMP = 0
channel (n+1) output
with COMP = 1
Figure 23-40. Channel (n+1) output in Complementary mode with (ELSnB:ELSnA = 1:0)
channel (n+1) match
FTM counter
channel (n) match
channel (n) output
with ELSnB:ELSnA = X:1
channel (n+1) output
with COMP = 0
channel (n+1) output
with COMP = 1
Figure 23-41. Channel (n+1) output in Complementary mode with (ELSnB:ELSnA = X:1)
NOTE
The complementary mode is not available in Output Compare
mode.
23.5.10 Registers updated from write buffers
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1235
Functional description
23.5.10.1 CNTIN register update
The following table describes when CNTIN register is updated:
Table 23-9. CNTIN register update
When Then CNTIN register is updated
CLKS[1:0] = 0:0 When CNTIN register is written, independent of FTMEN bit.
• FTMEN = 0, or At the next system clock after CNTIN was written.
• CNTINC = 0
• FTMEN = 1, By the CNTIN register synchronization.
• SYNCMODE = 1, and
• CNTINC = 1
23.5.10.2 MOD register update
The following table describes when MOD register is updated:
Table 23-10. MOD register update
When Then MOD register is updated
CLKS[1:0] = 0:0 When MOD register is written, independent of FTMEN bit.
• CLKS[1:0] ≠ 0:0, and According to the CPWMS bit, that is:
• FTMEN = 0
• If the selected mode is not CPWM then MOD register is updated after MOD
register was written and the FTM counter changes from MOD to CNTIN. If
the FTM counter is at free-running counter mode then this update occurs
when the FTM counter changes from 0xFFFF to 0x0000.
• If the selected mode is CPWM then MOD register is updated after MOD
register was written and the FTM counter changes from MOD to (MOD –
0x0001).
• CLKS[1:0] ≠ 0:0, and By the MOD register synchronization.
• FTMEN = 1
23.5.10.3 CnV register update
The following table describes when CnV register is updated:
Table 23-11. CnV register update
When Then CnV register is updated
CLKS[1:0] = 0:0 When CnV register is written, independent of FTMEN bit.
• CLKS[1:0] ≠ 0:0, and According to the selected mode, that is:
• FTMEN = 0
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1236 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
Table 23-11. CnV register update (continued)
When Then CnV register is updated
• If the selected mode is Output Compare, then CnV register is updated on the
next FTM counter change, end of the prescaler counting, after CnV register
was written.
• If the selected mode is EPWM, then CnV register is updated after CnV
register was written and the FTM counter changes from MOD to CNTIN. If
the FTM counter is at free-running counter mode then this update occurs
when the FTM counter changes from 0xFFFF to 0x0000.
• If the selected mode is CPWM, then CnV register is updated after CnV
register was written and the FTM counter changes from MOD to (MOD –
0x0001).
• CLKS[1:0] ≠ 0:0, and According to the selected mode, that is:
• FTMEN = 1
• If the selected mode is output compare then CnV register is updated
according to the SYNCEN bit. If (SYNCEN = 0) then CnV register is updated
after CnV register was written at the next change of the FTM counter, the
end of the prescaler counting. If (SYNCEN = 1) then CnV register is updated
by the C(n)V and C(n+1)V register synchronization.
• If the selected mode is not output compare and (SYNCEN = 1) then CnV
register is updated by the C(n)V and C(n+1)V register synchronization.
23.5.11 PWM synchronization
The PWM synchronization provides an opportunity to update the MOD, CNTIN, CnV,
OUTMASK, INVCTRL and SWOCTRL registers with their buffered value and force the
FTM counter to the CNTIN register value.
Note
The legacy PWM synchronization (SYNCMODE = 0) is a
subset of the enhanced PWM synchronization (SYNCMODE =
1). Thus, only the enhanced PWM synchronization must be
used.
23.5.11.1 Hardware trigger
Three hardware trigger signal inputs of the FTM module are enabled when TRIGn = 1,
where n = 0, 1 or 2 corresponding to each one of the input signals, respectively. The
hardware trigger input n is synchronized by the system clock. The PWM synchronization
with hardware trigger is initiated when a rising edge is detected at the enabled hardware
trigger inputs.
If (HWTRIGMODE = 0) then the TRIGn bit is cleared when 0 is written to it or when the
trigger n event is detected.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1237
Functional description
In this case, if two or more hardware triggers are enabled (for example, TRIG0 and
TRIG1 = 1) and only trigger 1 event occurs, then only TRIG1 bit is cleared. If a trigger n
event occurs together with a write setting TRIGn bit, then the synchronization is initiated,
but TRIGn bit remains set due to the write operation.
system clock
write 1 to TRIG0 bit
TRIG0 bit
trigger_0 input
synchronized trigger_0
by system clock
trigger 0 event
Note
All hardware trigger inputs have the same behavior.
Figure 23-42. Hardware trigger event with HWTRIGMODE = 0
If HWTRIGMODE = 1, then the TRIGn bit is only cleared when 0 is written to it.
NOTE
The HWTRIGMODE bit must be 1 only with enhanced PWM
synchronization (SYNCMODE = 1).
23.5.11.2 Software trigger
A software trigger event occurs when 1 is written to the SYNC[SWSYNC] bit. The
SWSYNC bit is cleared when 0 is written to it or when the PWM synchronization,
initiated by the software event, is completed.
If another software trigger event occurs (by writing another 1 to the SWSYNC bit) at the
same time the PWM synchronization initiated by the previous software trigger event is
ending, a new PWM synchronization is started and the SWSYNC bit remains equal to 1.
If SYNCMODE = 0 then the SWSYNC bit is also cleared by FTM according to
PWMSYNC and REINIT bits. In this case if (PWMSYNC = 1) or (PWMSYNC = 0 and
REINIT = 0) then SWSYNC bit is cleared at the next selected loading point after that the
software trigger event occurred; see Boundary cycle and loading points and the following
figure. If (PWMSYNC = 0) and (REINIT = 1) then SWSYNC bit is cleared when the
software trigger event occurs.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1238 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
If SYNCMODE = 1 then the SWSYNC bit is also cleared by FTM according to the
SWRSTCNT bit. If SWRSTCNT = 0 then SWSYNC bit is cleared at the next selected
loading point after that the software trigger event occurred; see the following figure. If
SWRSTCNT = 1 then SWSYNC bit is cleared when the software trigger event occurs.
system clock
write 1 to SWSYNC bit
SWSYNC bit
software trigger event
PWM synchronization
selected loading point
Figure 23-43. Software trigger event
23.5.11.3 Boundary cycle and loading points
The boundary cycle definition is important for the loading points for the registers MOD,
CNTIN, and C(n)V.
In Up counting mode, the boundary cycle is defined as when the counter wraps to its
initial value (CNTIN). If in Up-down counting mode, then the boundary cycle is defined
as when the counter turns from down to up counting and when from up to down counting.
The following figure shows the boundary cycles and the loading points for the registers.
In the Up Counting mode, the loading points are enabled if one of CNTMIN or CTMAX
bits are 1. In the Up-Down Counting mode, the loading points are selected by CNTMIN
and CNTMAX bits, as indicated in the figure. These loading points are safe places for
register updates thus allowing a smooth transitions in PWM waveform generation.
For both counting modes, if neither CNTMIN nor CNTMAX are 1, then the boundary
cycles are not used as loading points for registers updates. See the register
synchronization descriptions in the following sections for details.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1239
Functional description
loading points if CNTMAX = 1 or CNTMIN = 1
CNT = MOD -> CNTIN
up counting mode
loading points if CNTMAX = 1
CNT = (MOD - 0x0001) -> MOD
up-down counting mode
CNT = (CNTIN + 0x0001) -> CNTIN
loading points if CNTMIN = 1
Figure 23-44. Boundary cycles and loading points
23.5.11.4 MOD register synchronization
The MOD register synchronization updates the MOD register with its buffer value. This
synchronization is enabled if (FTMEN = 1).
The MOD register synchronization can be done by either the enhanced PWM
synchronization (SYNCMODE = 1) or the legacy PWM synchronization (SYNCMODE
= 0). However, it is expected that the MOD register be synchronized only by the
enhanced PWM synchronization.
In the case of enhanced PWM synchronization, the MOD register synchronization
depends on SWWRBUF, SWRSTCNT, HWWRBUF, and HWRSTCNT bits according to
this flowchart:
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1240 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
begin
legacy =0
PWM synchronization SYNCMODE
bit ?
=1
enhanced PWM synchronization
MOD register is MOD register is
updated by software trigger updated by hardware trigger
SWWRBUF =0 HWWRBUF = 0
bit ? bit ?
=1 =1
end end
software hardware
trigger trigger
0= TRIGn
=0
SWSYNC
bit ? bit ?
=1
=1
FTM counter is reset by
software trigger
=0
=1 wait hardware trigger n
SWRSTCNT
bit ?
wait the next selected HWTRIGMODE
=1
loading point bit ?
=0
update MOD with update MOD with
its buffer value its buffer value clear TRIGn bit
clear SWSYNC bit clear SWSYNC bit FTM counter is reset by
hardware trigger
0= =1
HWRSTCNT
end end bit ?
wait the next selected
loading point
update MOD with update MOD with
its buffer value its buffer value
end end
Figure 23-45. MOD register synchronization flowchart
In the case of legacy PWM synchronization, the MOD register synchronization depends
on PWMSYNC and REINIT bits according to the following description.
If (SYNCMODE = 0), (PWMSYNC = 0), and (REINIT = 0), then this synchronization is
made on the next selected loading point after an enabled trigger event takes place. If the
trigger event was a software trigger, then the SWSYNC bit is cleared on the next selected
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1241
Functional description
loading point. If the trigger event was a hardware trigger, then the trigger enable bit
(TRIGn) is cleared according to Hardware trigger. Examples with software and hardware
triggers follow.
system clock
write 1 to SWSYNC bit
SWSYNC bit
software trigger event
selected loading point
MOD register is updated
Figure 23-46. MOD synchronization with (SYNCMODE = 0), (PWMSYNC = 0), (REINIT =
0), and software trigger was used
system clock
write 1 to TRIG0 bit
TRIG0 bit
trigger 0 event
selected loading point
MOD register is updated
Figure 23-47. MOD synchronization with (SYNCMODE = 0), (HWTRIGMODE = 0),
(PWMSYNC = 0), (REINIT = 0), and a hardware trigger was used
If (SYNCMODE = 0), (PWMSYNC = 0), and (REINIT = 1), then this synchronization is
made on the next enabled trigger event. If the trigger event was a software trigger, then
the SWSYNC bit is cleared according to the following example. If the trigger event was a
hardware trigger, then the TRIGn bit is cleared according to Hardware trigger. Examples
with software and hardware triggers follow.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1242 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
system clock
write 1 to SWSYNC bit
SWSYNC bit
software trigger event
MOD register is updated
Figure 23-48. MOD synchronization with (SYNCMODE = 0), (PWMSYNC = 0), (REINIT =
1), and software trigger was used
system clock
write 1 to TRIG0 bit
TRIG0 bit
trigger 0 event
MOD register is updated
Figure 23-49. MOD synchronization with (SYNCMODE = 0), (HWTRIGMODE = 0),
(PWMSYNC = 0), (REINIT = 1), and a hardware trigger was used
If (SYNCMODE = 0) and (PWMSYNC = 1), then this synchronization is made on the
next selected loading point after the software trigger event takes place. The SWSYNC bit
is cleared on the next selected loading point:
system clock
write 1 to SWSYNC bit
SWSYNC bit
software trigger event
selected loading point
MOD register is updated
Figure 23-50. MOD synchronization with (SYNCMODE = 0) and (PWMSYNC = 1)
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1243
Functional description
23.5.11.5 CNTIN register synchronization
The CNTIN register synchronization updates the CNTIN register with its buffer value.
This synchronization is enabled if (FTMEN = 1), (SYNCMODE = 1), and (CNTINC =
1). The CNTIN register synchronization can be done only by the enhanced PWM
synchronization (SYNCMODE = 1). The synchronization mechanism is the same as the
MOD register synchronization done by the enhanced PWM synchronization; see MOD
register synchronization.
23.5.11.6 C(n)V and C(n+1)V register synchronization
The C(n)V and C(n+1)V registers synchronization updates the C(n)V and C(n+1)V
registers with their buffer values.
This synchronization is enabled if (FTMEN = 1) and (SYNCEN = 1). The
synchronization mechanism is the same as the MOD register synchronization. However,
it is expected that the C(n)V and C(n+1)V registers be synchronized only by the
enhanced PWM synchronization (SYNCMODE = 1).
23.5.11.7 OUTMASK register synchronization
The OUTMASK register synchronization updates the OUTMASK register with its buffer
value.
The OUTMASK register can be updated at each rising edge of system clock
(SYNCHOM = 0), by the enhanced PWM synchronization (SYNCHOM = 1 and
SYNCMODE = 1) or by the legacy PWM synchronization (SYNCHOM = 1 and
SYNCMODE = 0). However, it is expected that the OUTMASK register be synchronized
only by the enhanced PWM synchronization.
In the case of enhanced PWM synchronization, the OUTMASK register synchronization
depends on SWOM and HWOM bits. See the following flowchart:
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1244 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
begin
update OUTMASK register at
each rising edge of system clock update OUTMASK register by
0= =1 PWM synchronization
SYNCHOM
bit ?
1= =0
SYNCMODE
no = rising edge
of system bit ?
clock ?
legacy
= yes PWM synchronization
update OUTMASK
with its buffer value
end
enhanced PWM synchronization
OUTMASK is updated OUTMASK is updated
by software trigger by hardware trigger
1= SWOM =0 0= HWOM =1
bit ? bit ?
software end end hardware
0=
SWSYNC trigger TRIGn =0
trigger
bit ? bit ?
=1
=1
wait hardware trigger n
update OUTMASK
with its buffer value
update OUTMASK
end with its buffer value
=1
HWTRIGMODE
bit ?
=0
clear TRIGn bit
end
Figure 23-51. OUTMASK register synchronization flowchart
In the case of legacy PWM synchronization, the OUTMASK register synchronization
depends on PWMSYNC bit according to the following description.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1245
Functional description
If (SYNCMODE = 0), (SYNCHOM = 1), and (PWMSYNC = 0), then this
synchronization is done on the next enabled trigger event. If the trigger event was a
software trigger, then the SWSYNC bit is cleared on the next selected loading point. If
the trigger event was a hardware trigger, then the TRIGn bit is cleared according to
Hardware trigger. Examples with software and hardware triggers follow.
system clock
write 1 to SWSYNC bit
SWSYNC bit
software trigger event
selected loading point
OUTMASK register is updated SWSYNC bit is cleared
Figure 23-52. OUTMASK synchronization with (SYNCMODE = 0), (SYNCHOM = 1),
(PWMSYNC = 0) and software trigger was used
system clock
write 1 to TRIG0 bit
TRIG0 bit
trigger 0 event
OUTMASK register is updated and
TRIG0 bit is cleared
Figure 23-53. OUTMASK synchronization with (SYNCMODE = 0), (HWTRIGMODE = 0),
(SYNCHOM = 1), (PWMSYNC = 0), and a hardware trigger was used
If (SYNCMODE = 0), (SYNCHOM = 1), and (PWMSYNC = 1), then this
synchronization is made on the next enabled hardware trigger. The TRIGn bit is cleared
according to Hardware trigger. An example with a hardware trigger follows.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1246 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
system clock
write 1 to TRIG0 bit
TRIG0 bit
trigger 0 event
OUTMASK register is updated and
TRIG0 bit is cleared
Figure 23-54. OUTMASK synchronization with (SYNCMODE = 0), (HWTRIGMODE = 0),
(SYNCHOM = 1), (PWMSYNC = 1), and a hardware trigger was used
23.5.11.8 INVCTRL register synchronization
The INVCTRL register synchronization updates the INVCTRL register with its buffer
value.
The INVCTRL register can be updated at each rising edge of system clock (INVC = 0) or
by the enhanced PWM synchronization (INVC = 1 and SYNCMODE = 1) according to
the following flowchart.
In the case of enhanced PWM synchronization, the INVCTRL register synchronization
depends on SWINVC and HWINVC bits.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1247
Functional description
begin
update INVCTRL register at
each rising edge of system clock update INVCTRL register by
PWM synchronization
0= INVC =1
bit ?
1= =0
SYNCMODE
bit ?
no = rising edge
of system end
clock ?
= yes
update INVCTRL
with its buffer value
end
enhanced PWM synchronization
INVCTRL is updated INVCTRL is updated
by software trigger by hardware trigger
1= SWINVC =0 0= HWINVC =1
bit ? bit ?
software end end hardware
0=
SWSYNC trigger TRIGn =0
trigger
bit ? bit ?
=1
=1
update INVCTRL
wait hardware trigger n
with its buffer value
update INVCTRL
end with its buffer value
=1
HWTRIGMODE
bit ?
=0
clear TRIGn bit
end
Figure 23-55. INVCTRL register synchronization flowchart
23.5.11.9 SWOCTRL register synchronization
The SWOCTRL register synchronization updates the SWOCTRL register with its buffer
value.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1248 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
The SWOCTRL register can be updated at each rising edge of system clock (SWOC = 0)
or by the enhanced PWM synchronization (SWOC = 1 and SYNCMODE = 1) according
to the following flowchart.
In the case of enhanced PWM synchronization, the SWOCTRL register synchronization
depends on SWSOC and HWSOC bits.
begin
update SWOCTRL register at
each rising edge of system clock update SWOCTRL register by
0= =1 PWM synchronization
SWOC
bit ?
1= =0
SYNCMODE
bit ?
no = rising edge
of system end
clock ?
= yes
update SWOCTRL
with its buffer value
end
enhanced PWM synchronization
SWOCTRL is updated SWOCTRL is updated
by software trigger by hardware trigger
1= SWSOC =0 0= HWSOC =1
bit ? bit ?
software end end hardware
0=
SWSYNC trigger TRIGn =0
trigger
bit ? bit ?
=1
=1
update SWOCTRL
wait hardware trigger n
with its buffer value
update SWOCTRL
end with its buffer value
=1
HWTRIGMODE
bit ?
=0
clear TRIGn bit
end
Figure 23-56. SWOCTRL register synchronization flowchart
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1249
Functional description
23.5.11.10 FTM counter synchronization
The FTM counter synchronization is a mechanism that allows the FTM to restart the
PWM generation at a certain point in the PWM period. The channels outputs are forced
to their initial value, except for channels in Output Compare mode, and the FTM counter
is forced to its initial counting value defined by CNTIN register.
The following figure shows the FTM counter synchronization. Note that after the
synchronization event occurs, the channel (n) is set to its initial value and the channel (n
+1) is not set to its initial value due to a specific timing of this figure in which the
deadtime insertion prevents this channel output from transitioning to 1. If no deadtime
insertion is selected, then the channel (n+1) transitions to logical value 1 immediately
after the synchronization event occurs.
channel (n+1) match
FTM counter
channel (n) match
channel (n) output
(after deadtime
insertion)
channel (n+1) output
(after deadtime
insertion)
synchronization event
Figure 23-57. FTM counter synchronization
The FTM counter synchronization can be done by either the enhanced PWM
synchronization (SYNCMODE = 1) or the legacy PWM synchronization (SYNCMODE
= 0). However, the FTM counter must be synchronized only by the enhanced PWM
synchronization.
In the case of enhanced PWM synchronization, the FTM counter synchronization
depends on SWRSTCNT and HWRSTCNT bits according to the following flowchart.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1250 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
begin
legacy =0
PWM synchronization SYNCMODE
bit ?
=1
enhanced PWM synchronization
FTM counter is reset by FTM counter is reset by
software trigger hardware trigger
=0
1= =0 =1
SWRSTCNT HWRSTCNT
bit ? bit ?
end end hardware
TRIGn =0
=0 software
SWSYNC trigger
bit ?
trigger
bit ?
=1
=1
update FTM counter with wait hardware trigger n
CNTIN register value
update FTM counter with
update the channels outputs CNTIN register value
with their initial value
update the channels outputs
clear SWSYNC bit with their initial value
end
=1
HWTRIGMODE
bit ?
=0
clear TRIGn bit
end
Figure 23-58. FTM counter synchronization flowchart
In the case of legacy PWM synchronization, the FTM counter synchronization depends
on REINIT and PWMSYNC bits according to the following description.
If (SYNCMODE = 0), (REINIT = 1), and (PWMSYNC = 0) then this synchronization is
made on the next enabled trigger event. If the trigger event was a software trigger then
the SWSYNC bit is cleared according to the following example. If the trigger event was a
hardware trigger then the TRIGn bit is cleared according to Hardware trigger. Examples
with software and hardware triggers follow.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1251
Functional description
system clock
write 1 to SWSYNC bit
SWSYNC bit
software trigger event
FTM counter is updated with the CNTIN register value
and channel outputs are forced to their initial value
Figure 23-59. FTM counter synchronization with (SYNCMODE = 0), (REINIT = 1),
(PWMSYNC = 0), and software trigger was used
system clock
write 1 to TRIG0 bit
TRIG0 bit
trigger 0 event
FTM counter is updated with the CNTIN register value
and channel outputs are forced to their initial value
Figure 23-60. FTM counter synchronization with (SYNCMODE = 0), (HWTRIGMODE = 0),
(REINIT = 1), (PWMSYNC = 0), and a hardware trigger was used
If (SYNCMODE = 0), (REINIT = 1), and (PWMSYNC = 1) then this synchronization is
made on the next enabled hardware trigger. The TRIGn bit is cleared according to
Hardware trigger.
system clock
write 1 to TRIG0 bit
TRIG0 bit
trigger 0 event
FTM counter is updated with the CNTIN register value
and channel outputs are forced to their initial value
Figure 23-61. FTM counter synchronization with (SYNCMODE = 0), (HWTRIGMODE = 0),
(REINIT = 1), (PWMSYNC = 1), and a hardware trigger was used
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1252 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
23.5.12 Inverting
The invert functionality swaps the signals between channel (n) and channel (n+1)
outputs. The inverting operation is selected when:
• QUADEN = 0
• DECAPEN = 0
• COMP = 1, and
• INVm = 1 (where m represents a channel pair)
The INVm bit in INVCTRL register is updated with its buffer value according to
INVCTRL register synchronization
In High-True (ELSnB:ELSnA = 1:0) Combine mode, the channel (n) output is forced low
at the beginning of the period (FTM counter = CNTIN), forced high at the channel (n)
match and forced low at the channel (n+1) match. If the inverting is selected, the channel
(n) output behavior is changed to force high at the beginning of the PWM period, force
low at the channel (n) match and force high at the channel (n+1) match. See the following
figure.
channel (n+1) match
FTM counter
channel (n) match
channel (n) output
before the inverting
channel (n+1) output
before the inverting
write 1 to INV(m) bit
INV(m) bit buffer
INVCTRL register
synchronization
INV(m) bit
channel (n) output
after the inverting
channel (n+1) output
after the inverting
NOTE
INV(m) bit selects the inverting to the pair channels (n) and (n+1).
Figure 23-62. Channels (n) and (n+1) outputs after the inverting in High-True
(ELSnB:ELSnA = 1:0) Combine mode
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1253
Functional description
Note that the ELSnB:ELSnA bits value should be considered because they define the
active state of the channels outputs. In Low-True (ELSnB:ELSnA = X:1) Combine mode,
the channel (n) output is forced high at the beginning of the period, forced low at the
channel (n) match and forced high at the channel (n+1) match. When inverting is
selected, the channels (n) and (n+1) present waveforms as shown in the following figure.
channel (n+1) match
FTM counter
channel (n) match
channel (n) output
before the inverting
channel (n+1) output
before the inverting
write 1 to INV(m) bit
INV(m) bit buffer
INVCTRL register
synchronization
INV(m) bit
channel (n) output
after the inverting
channel (n+1) output
after the inverting
NOTE
INV(m) bit selects the inverting to the pair channels (n) and (n+1).
Figure 23-63. Channels (n) and (n+1) outputs after the inverting in Low-True
(ELSnB:ELSnA = X:1) Combine mode
Note
The inverting feature is not available in Output Compare mode.
23.5.13 Software output control
The software output control forces the channel output according to software defined
values at a specific time in the PWM generation.
The software output control is selected when:
• QUADEN = 0
• DECAPEN = 0, and
• CHnOC = 1
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1254 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
The CHnOC bit enables the software output control for a specific channel output and the
CHnOCV selects the value that is forced to this channel output.
Both CHnOC and CHnOCV bits in SWOCTRL register are buffered and updated with
their buffer value according to SWOCTRL register synchronization.
The following figure shows the channels (n) and (n+1) outputs signals when the software
output control is used. In this case the channels (n) and (n+1) are set to Combine and
Complementary mode.
channel (n+1) match
FTM counter
channel (n) match
channel (n) output
after the software
output control
channel (n+1) output
after the software
output control
CH(n)OC buffer
CH(n+1)OC buffer
write to SWOCTRL register write to SWOCTRL register
CH(n)OC bit
CH(n+1)OC bit
SWOCTRL register synchronization SWOCTRL register synchronization
NOTE
CH(n)OCV = 1 and CH(n+1)OCV = 0.
Figure 23-64. Example of software output control in Combine and Complementary mode
Software output control forces the following values on channels (n) and (n+1) when the
COMP bit is zero.
Table 23-12. Software ouput control behavior when (COMP = 0)
CH(n)OC CH(n+1)OC CH(n)OCV CH(n+1)OCV Channel (n) Output Channel (n+1) Output
0 0 X X is not modified by SWOC is not modified by SWOC
1 1 0 0 is forced to zero is forced to zero
1 1 0 1 is forced to zero is forced to one
1 1 1 0 is forced to one is forced to zero
1 1 1 1 is forced to one is forced to one
Software output control forces the following values on channels (n) and (n+1) when the
COMP bit is one.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1255
Functional description
Table 23-13. Software ouput control behavior when (COMP = 1)
CH(n)OC CH(n+1)OC CH(n)OCV CH(n+1)OCV Channel (n) Output Channel (n+1) Output
0 0 X X is not modified by SWOC is not modified by SWOC
1 1 0 0 is forced to zero is forced to zero
1 1 0 1 is forced to zero is forced to one
1 1 1 0 is forced to one is forced to zero
1 1 1 1 is forced to one is forced to zero
Note
• The CH(n)OC and CH(n+1)OC bits should be equal.
• The COMP bit must not be modified when software output
control is enabled, that is, CH(n)OC = 1 and/or CH(n
+1)OC = 1.
• Software output control has the same behavior with
disabled or enabled FTM counter (see the CLKS field
description in the Status and Control register).
23.5.14 Deadtime insertion
The deadtime insertion is enabled when (DTEN = 1) and (DTVAL[5:0] is non- zero).
DEADTIME register defines the deadtime delay that can be used for all FTM channels.
The DTPS[1:0] bits define the prescaler for the system clock and the DTVAL[5:0] bits
define the deadtime modulo, that is, the number of the deadtime prescaler clocks.
The deadtime delay insertion ensures that no two complementary signals (channels (n)
and (n+1)) drive the active state at the same time.
If POL(n) = 0, POL(n+1) = 0, and the deadtime is enabled, then when the channel (n)
match (FTM counter = C(n)V) occurs, the channel (n) output remains at the low value
until the end of the deadtime delay when the channel (n) output is set. Similarly, when the
channel (n+1) match (FTM counter = C(n+1)V) occurs, the channel (n+1) output remains
at the low value until the end of the deadtime delay when the channel (n+1) output is set.
See the following figures.
If POL(n) = 1, POL(n+1) = 1, and the deadtime is enabled, then when the channel (n)
match (FTM counter = C(n)V) occurs, the channel (n) output remains at the high value
until the end of the deadtime delay when the channel (n) output is cleared. Similarly,
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1256 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
when the channel (n+1) match (FTM counter = C(n+1)V) occurs, the channel (n+1)
output remains at the high value until the end of the deadtime delay when the channel (n
+1) output is cleared.
channel (n+1) match
FTM counter
channel (n) match
channel (n) output
(before deadtime
insertion)
channel (n+1) output
(before deadtime
insertion)
channel (n) output
(after deadtime
insertion)
channel (n+1) output
(after deadtime
insertion)
Figure 23-65. Deadtime insertion with ELSnB:ELSnA = 1:0, POL(n) = 0, and POL(n+1) = 0
channel (n+1) match
FTM counter
channel (n) match
channel (n) output
(before deadtime
insertion)
channel (n+1) output
(before deadtime
insertion)
channel (n) output
(after deadtime
insertion)
channel (n+1) output
(after deadtime
insertion)
Figure 23-66. Deadtime insertion with ELSnB:ELSnA = X:1, POL(n) = 0, and POL(n+1) = 0
NOTE
• The deadtime feature must be used only in Complementary
mode.
• The deadtime feature is not available in Output Compare
mode.
23.5.14.1 Deadtime insertion corner cases
If (PS[2:0] is cleared), (DTPS[1:0] = 0:0 or DTPS[1:0] = 0:1):
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1257
Functional description
• and the deadtime delay is greater than or equal to the channel (n) duty cycle ((C(n
+1)V – C(n)V) × system clock), then the channel (n) output is always the inactive
value (POL(n) bit value).
• and the deadtime delay is greater than or equal to the channel (n+1) duty cycle
((MOD – CNTIN + 1 – (C(n+1)V – C(n)V) ) × system clock), then the channel (n+1)
output is always the inactive value (POL(n+1) bit value).
Although, in most cases the deadtime delay is not comparable to channels (n) and (n+1)
duty cycle, the following figures show examples where the deadtime delay is comparable
to the duty cycle.
channel (n+1) match
FTM counter
channel (n) match
channel (n) output
(before deadtime
insertion)
channel (n+1) output
(before deadtime
insertion)
channel (n) output
(after deadtime
insertion)
channel (n+1) output
(after deadtime
insertion)
Figure 23-67. Example of the deadtime insertion (ELSnB:ELSnA = 1:0, POL(n) = 0, and
POL(n+1) = 0) when the deadtime delay is comparable to channel (n+1) duty cycle
channel (n+1) match
FTM counter
channel (n) match
channel (n) output
(before deadtime
insertion)
channel (n+1) output
(before deadtime
insertion)
channel (n) output
(after deadtime
insertion)
channel (n+1) output
(after deadtime
insertion)
Figure 23-68. Example of the deadtime insertion (ELSnB:ELSnA = 1:0, POL(n) = 0, and
POL(n+1) = 0) when the deadtime delay is comparable to channels (n) and (n+1) duty
cycle
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1258 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
23.5.15 Output mask
The output mask can be used to force channels output to their inactive state through
software. For example: to control a BLDC motor.
Any write to the OUTMASK register updates its write buffer. The OUTMASK register is
updated with its buffer value by PWM synchronization; see OUTMASK register
synchronization.
If CHnOM = 1, then the channel (n) output is forced to its inactive state (POLn bit value).
If CHnOM = 0, then the channel (n) output is unaffected by the output mask. See the
following figure.
the beginning of new PWM cycles
FTM counter
channel (n) output
(before output mask)
CHnOM bit
channel (n) output
(after output mask)
channel (n) output is disabled
configured PWM signal starts
to be available in the channel (n) output
Figure 23-69. Output mask with POLn = 0
The following table shows the output mask result before the polarity control.
Table 23-14. Output mask result for channel (n) before the polarity control
CHnOM Output Mask Input Output Mask Result
0 inactive state inactive state
active state active state
1 inactive state inactive state
active state
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1259
Functional description
23.5.16 Fault control
The fault control is enabled if (FAULTM[1:0] ≠ 0:0).
FTM can have up to four fault inputs. FAULTnEN bit (where n = 0, 1, 2, 3) enables the
fault input n and FFLTRnEN bit enables the fault input n filter. FFVAL[3:0] bits select
the value of the enabled filter in each enabled fault input.
First, each fault input signal is synchronized by the system clock; see the synchronizer
block in the following figure. Following synchronization, the fault input n signal enters
the filter block. When there is a state change in the fault input n signal, the 5-bit counter
is reset and starts counting up. As long as the new state is stable on the fault input n, the
counter continues to increment. If the 5-bit counter overflows, that is, the counter exceeds
the value of the FFVAL[3:0] bits, the new fault input n value is validated. It is then
transmitted as a pulse edge to the edge detector.
If the opposite edge appears on the fault input n signal before validation (counter
overflow), the counter is reset. At the next input transition, the counter starts counting
again. Any pulse that is shorter than the minimum value selected by FFVAL[3:0] bits (×
system clock) is regarded as a glitch and is not passed on to the edge detector.
The fault input n filter is disabled when the FFVAL[3:0] bits are zero or when
FAULTnEN = 0. In this case, the fault input n signal is delayed 2 rising edges of the
system clock and the FAULTFn bit is set on 3th rising edge of the system clock after a
rising edge occurs on the fault input n.
If FFVAL[3:0] ≠ 0000 and FAULTnEN = 1, then the fault input n signal is delayed (3 +
FFVAL[3:0]) rising edges of the system clock, that is, the FAULTFn bit is set (4 +
FFVAL[3:0]) rising edges of the system clock after a rising edge occurs on the fault input
n.
(FFVAL[3:0] 0000)
and (FFLTRnEN*)
FLTnPOL
synchronizer fault input n* value
0
fault input n* D Q D Q fault input
polarity rising edge
control FAULTFn*
Fault filter detector
(5-bit counter) 1
system clock CLK CLK
* where n = 3, 2, 1, 0
Figure 23-70. Fault input n control block diagram
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1260 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
If the fault control and fault input n are enabled and a rising edge at the fault input n
signal is detected, a fault condition has occurred and the FAULTFn bit is set. The
FAULTF bit is the logic OR of FAULTFn[3:0] bits. See the following figure.
fault input 0 value
fault input 1 value
FAULTIN
fault input 2 value
fault input 3 value
FAULTIE fault interrupt
FAULTF0
FAULTF1
FAULTF
FAULTF2
FAULTF3
Figure 23-71. FAULTF and FAULTIN bits and fault interrupt
If the fault control is enabled (FAULTM[1:0] ≠ 0:0), a fault condition has occurred and
(FAULTEN = 1), then outputs are forced to their safe values:
• Channel (n) output takes the value of POL(n)
• Channel (n+1) takes the value of POL(n+1)
The fault interrupt is generated when (FAULTF = 1) and (FAULTIE = 1). This interrupt
request remains set until:
• Software clears the FAULTF bit by reading FAULTF bit as 1 and writing 0 to it
• Software clears the FAULTIE bit
• A reset occurs
23.5.16.1 Automatic fault clearing
If the automatic fault clearing is selected (FAULTM[1:0] = 1:1), then the channels output
disabled by fault control is again enabled when the fault input signal (FAULTIN) returns
to zero and a new PWM cycle begins. See the following figure.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1261
Functional description
the beginning of new PWM cycles
FTM counter
channel (n) output
(before fault control)
FAULTIN bit
channel (n) output
FAULTF bit
FAULTF bit is cleared
NOTE
The channel (n) output is after the fault control with automatic fault clearing and POLn = 0.
Figure 23-72. Fault control with automatic fault clearing
23.5.16.2 Manual fault clearing
If the manual fault clearing is selected (FAULTM[1:0] = 0:1 or 1:0), then the channels
output disabled by fault control is again enabled when the FAULTF bit is cleared and a
new PWM cycle begins. See the following figure.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1262 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
the beginning of new PWM cycles
FTM counter
channel (n) output
(before fault control)
FAULTIN bit
channel (n) output
FAULTF bit
FAULTF bit is cleared
NOTE
The channel (n) output is after the fault control with manual fault clearing and POLn = 0.
Figure 23-73. Fault control with manual fault clearing
23.5.16.3 Fault inputs polarity control
The FLTjPOL bit selects the fault input j polarity, where j = 0, 1, 2, 3:
• If FLTjPOL = 0, the fault j input polarity is high, so the logical one at the fault input j
indicates a fault.
• If FLTjPOL = 1, the fault j input polarity is low, so the logical zero at the fault input j
indicates a fault.
23.5.17 Polarity control
The POLn bit selects the channel (n) output polarity:
• If POLn = 0, the channel (n) output polarity is high, so the logical one is the active
state and the logical zero is the inactive state.
• If POLn = 1, the channel (n) output polarity is low, so the logical zero is the active
state and the logical one is the inactive state.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1263
Functional description
23.5.18 Initialization
The initialization forces the CHnOI bit value to the channel (n) output when a one is
written to the INIT bit.
The initialization depends on COMP and DTEN bits. The following table shows the
values that channels (n) and (n+1) are forced by initialization when the COMP and
DTEN bits are zero.
Table 23-15. Initialization behavior when (COMP = 0 and DTEN = 0)
CH(n)OI CH(n+1)OI Channel (n) Output Channel (n+1) Output
0 0 is forced to zero is forced to zero
0 1 is forced to zero is forced to one
1 0 is forced to one is forced to zero
1 1 is forced to one is forced to one
The following table shows the values that channels (n) and (n+1) are forced by
initialization when (COMP = 1) or (DTEN = 1).
Table 23-16. Initialization behavior when (COMP = 1 or DTEN = 1)
CH(n)OI CH(n+1)OI Channel (n) Output Channel (n+1) Output
0 X is forced to zero is forced to one
1 X is forced to one is forced to zero
Note
The initialization feature must be used only with disabled FTM
counter. See the description of the CLKS field in the Status and
Control register.
23.5.19 Features priority
The following figure shows the priority of the features used at the generation of channels
(n) and (n+1) outputs signals.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1264 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
pair channels (m) - channels (n) and (n+1)
FTM counter
QUADEN
DECAPEN
COMBINE(m)
CPWMS
C(n)V
MS(n)B CH(n)OC
MS(n)A CH(n)OCV POL(n)
ELS(n)B CH(n+1)OC POL(n+1)
CH(n)OI CH(n)OM
ELS(n)A CH(n+1)OI COMP(m) INV(m)EN CH(n+1)OCV DTEN(m) CH(n+1)OM FAULTEN(m)
generation of channel
channel (n) (n)
output
output signal signal
software deadtime polarity
complementary output fault
initialization inverting output insertion control
mode mask control
control
generation of channel
(n+1)
channel (n+1)
output
output signal signal
C(n+1)V
MS(n+1)B
MS(n+1)A
ELS(n+1)B
ELS(n+1)A
NOTE
The channels (n) and (n+1) are in output compare, EPWM, CPWM or combine modes.
Figure 23-74. Priority of the features used at the generation of channels (n) and (n+1)
outputs signals
Note
The Initialization feature must not be used with Inverting and
Software output control features.
23.5.20 Channel trigger output
If CH(j)TRIG bit of the FTM External Trigger (FTM_EXTTRIG) register is set, where j
= 0, 1, 2, 3, 4, or 5, then the FTM generates a trigger when the channel (j) match occurs
(FTM counter = C(j)V).
The channel trigger output provides a trigger signal which has one FTM clock period
width and is used for on-chip modules.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1265
Functional description
The FTM is able to generate multiple triggers in one PWM period. Because each trigger
is generated for a specific channel, several channels are required to implement this
functionality. This behavior is described in the following figure.
the beginning of new PWM cycles
MOD
FTM counter = C5V
FTM counter = C4V
FTM counter = C3V
FTM counter = C2V
FTM counter = C1V
FTM counter = C0V
CNTIN
(a)
(b)
(c)
(d)
System clock
CnV 0x14
FTM counter 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17
Channel Trigger Output
NOTE
(a) CH0TRIG = 0, CH1TRIG = 0, CH2TRIG = 0, CH3TRIG = 0, CH4TRIG = 0, CH5TRIG = 0
(b) CH0TRIG = 1, CH1TRIG = 0, CH2TRIG = 0, CH3TRIG = 0, CH4TRIG = 0, CH5TRIG = 0
(c) CH0TRIG = 0, CH1TRIG = 0, CH2TRIG = 0, CH3TRIG = 1, CH4TRIG = 1, CH5TRIG = 1
(d) CH0TRIG = 1, CH1TRIG = 1, CH2TRIG = 1, CH3TRIG = 1, CH4TRIG = 1, CH5TRIG = 1
Figure 23-75. Channel match trigger
23.5.21 Initialization trigger
If INITTRIGEN = 1, then the FTM generates a trigger when the FTM counter is updated
with the CNTIN register value in the following cases.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1266 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
• The FTM counter is automatically updated with the CNTIN register value by the
selected counting mode.
• When there is a write to CNT register.
• When there is the FTM counter synchronization.
• If (CNT = CNTIN), (CLKS[1:0] = 0:0), and a value different from zero is written to
CLKS[1:0] bits.
The following figures show these cases.
CNTIN = 0x0000
MOD = 0x000F
CPWMS = 0
system clock
FTM counter 0x0C 0x0D 0x0E 0x0F 0x00 0x01 0x02 0x03 0x04 0x05
initialization trigger
Figure 23-76. Initialization trigger is generated when the FTM counting achieves the
CNTIN register value
CNTIN = 0x0000
MOD = 0x000F
CPWMS = 0
system clock
FTM counter 0x04 0x05 0x06 0x00 0x01 0x02 0x03 0x04 0x05 0x06
write to CNT
initialization trigger
Figure 23-77. Initialization trigger is generated when there is a write to CNT register
NOTE
The behavior depicted in the Figure 23-77 is not available on
CPWM.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1267
Functional description
CNTIN = 0x0000
MOD = 0x000F
CPWMS = 0
system clock
FTM counter 0x04 0x05 0x06 0x07 0x00 0x01 0x02 0x03 0x04 0x05
FTM counter
synchronization
initialization trigger
Figure 23-78. Initialization trigger is generated when there is the FTM counter
synchronization
NOTE
The behavior depicted in the Figure 23-78 is not available on
CPWM.
CNTIN = 0x0000
MOD = 0x000F
CPWMS = 0
system clock
FTM counter 0x00 0x01 0x02 0x03 0x04 0x05
CLKS[1:0] bits 00 01
initialization trigger
Figure 23-79. Initialization trigger is generated if (CNT = CNTIN), (CLKS[1:0] = 0:0), and a
value different from zero is written to CLKS[1:0] bits
NOTE
The behavior depicted in the Figure 23-79 is not available on
CPWM.
The initialization trigger output provides a trigger signal that is used for on-chip modules.
23.5.22 Capture Test mode
The Capture Test mode allows to test the CnV registers, the FTM counter and the
interconnection logic between the FTM counter and CnV registers.
In this test mode, all channels must be configured for Input Capture mode and FTM
counter must be configured to the Up counting.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1268 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
When the Capture Test mode is enabled (CAPTEST = 1), the FTM counter is frozen and
any write to CNT register updates directly the FTM counter; see the following figure.
After it was written, all CnV registers are updated with the written value to CNT register
and CHnF bits are set. Therefore, the FTM counter is updated with its next value
according to its configuration. Its next value depends on CNTIN, MOD, and the written
value to FTM counter.
The next reads of CnV registers return the written value to the FTM counter and the next
reads of CNT register return FTM counter next value.
FTM counter clock
set CAPTEST
clear CAPTEST
write to MODE
CAPTEST bit
FTM counter 0x1053 0x1054 0x1055 0x1056 0x78AC 0x78AD 0x78AE 0x78AF 0x78B0
write 0x78AC
write to CNT
CHnF bit
0x0300 0x78AC
CnV
NOTE
- FTM counter configuration: (FTMEN = 1), (QUADEN = 0), (CAPTEST = 1), (CPWMS = 0), (CNTIN = 0x0000), and
(MOD = 0xFFFF)
- FTM channel n configuration: input capture mode - (DECAPEN = 0), (COMBINE = 0), and (MSnB:MSnA = 0:0)
Figure 23-80. Capture Test mode
23.5.23 DMA
The channel generates a DMA transfer request according to DMA and CHnIE bits. See
the following table.
Table 23-17. Channel DMA transfer request
DMA CHnIE Channel DMA Transfer Request Channel Interrupt
0 0 The channel DMA transfer request is not The channel interrupt is not generated.
generated.
0 1 The channel DMA transfer request is not The channel interrupt is generated if (CHnF = 1).
generated.
1 0 The channel DMA transfer request is not The channel interrupt is not generated.
generated.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1269
Functional description
Table 23-17. Channel DMA transfer request (continued)
DMA CHnIE Channel DMA Transfer Request Channel Interrupt
1 1 The channel DMA transfer request is generated if The channel interrupt is not generated.
(CHnF = 1).
If DMA = 1, the CHnF bit is cleared either by channel DMA transfer done or reading
CnSC while CHnF is set and then writing a zero to CHnF bit according to CHnIE bit. See
the following table.
Table 23-18. Clear CHnF bit when DMA = 1
CHnIE How CHnF Bit Can Be Cleared
0 CHnF bit is cleared either when the channel DMA transfer is done or by reading CnSC while CHnF is set and
then writing a 0 to CHnF bit.
1 CHnF bit is cleared when the channel DMA transfer is done.
23.5.24 Dual Edge Capture mode
The Dual Edge Capture mode is selected if DECAPEN = 1. This mode allows to measure
a pulse width or period of the signal on the input of channel (n) of a channel pair. The
channel (n) filter can be active in this mode when n is 0 or 2.
FTMEN
DECAPEN
is filter DECAP
enabled? channel (n)
MS(n)A CH(n)IE interrupt
ELS(n)B:ELS(n)A
CH(n)F
synchronizer ELS(n+1)B:ELS(n+1)A
0 C(n)V[15:0]
channel (n) input D Q D Q Dual edge capture
mode logic
channel (n+1)
Filter* 1 CH(n+1)IE interrupt
system clock CLK CLK
CH(n+1)F
C(n+1)V[15:0]
FTM counter
* Filtering function for dual edge capture mode is only available in the channels 0 and 2
Figure 23-81. Dual Edge Capture mode block diagram
The MS(n)A bit defines if the Dual Edge Capture mode is one-shot or continuous.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1270 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
The ELS(n)B:ELS(n)A bits select the edge that is captured by channel (n), and ELS(n
+1)B:ELS(n+1)A bits select the edge that is captured by channel (n+1). If both
ELS(n)B:ELS(n)A and ELS(n+1)B:ELS(n+1)A bits select the same edge, then it is the
period measurement. If these bits select different edges, then it is a pulse width
measurement.
In the Dual Edge Capture mode, only channel (n) input is used and channel (n+1) input is
ignored.
If the selected edge by channel (n) bits is detected at channel (n) input, then CH(n)F bit is
set and the channel (n) interrupt is generated (if CH(n)IE = 1). If the selected edge by
channel (n+1) bits is detected at channel (n) input and (CH(n)F = 1), then CH(n+1)F bit is
set and the channel (n+1) interrupt is generated (if CH(n+1)IE = 1).
The C(n)V register stores the value of FTM counter when the selected edge by channel
(n) is detected at channel (n) input. The C(n+1)V register stores the value of FTM
counter when the selected edge by channel (n+1) is detected at channel (n) input.
In this mode, a coherency mechanism ensures coherent data when the C(n)V and C(n
+1)V registers are read. The only requirement is that C(n)V must be read before C(n
+1)V.
Note
• The CH(n)F, CH(n)IE, MS(n)A, ELS(n)B, and ELS(n)A
bits are channel (n) bits.
• The CH(n+1)F, CH(n+1)IE, MS(n+1)A, ELS(n+1)B, and
ELS(n+1)A bits are channel (n+1) bits.
• The Dual Edge Capture mode must be used with
ELS(n)B:ELS(n)A = 0:1 or 1:0, ELS(n+1)B:ELS(n+1)A =
0:1 or 1:0 and the FTM counter in Free running counter.
23.5.24.1 One-Shot Capture mode
The One-Shot Capture mode is selected when (DECAPEN = 1), and (MS(n)A = 0). In
this capture mode, only one pair of edges at the channel (n) input is captured. The
ELS(n)B:ELS(n)A bits select the first edge to be captured, and ELS(n+1)B:ELS(n+1)A
bits select the second edge to be captured.
The edge captures are enabled while DECAP bit is set. For each new measurement in
One-Shot Capture mode, first the CH(n)F and CH(n+1) bits must be cleared, and then the
DECAP bit must be set.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1271
Functional description
In this mode, the DECAP bit is automatically cleared by FTM when the edge selected by
channel (n+1) is captured. Therefore, while DECAP bit is set, the one-shot capture is in
process. When this bit is cleared, both edges were captured and the captured values are
ready for reading in the C(n)V and C(n+1)V registers.
Similarly, when the CH(n+1)F bit is set, both edges were captured and the captured
values are ready for reading in the C(n)V and C(n+1)V registers.
23.5.24.2 Continuous Capture mode
The Continuous Capture mode is selected when (DECAPEN = 1), and (MS(n)A = 1). In
this capture mode, the edges at the channel (n) input are captured continuously. The
ELS(n)B:ELS(n)A bits select the initial edge to be captured, and ELS(n+1)B:ELS(n+1)A
bits select the final edge to be captured.
The edge captures are enabled while DECAP bit is set. For the initial use, first the
CH(n)F and CH(n+1)F bits must be cleared, and then DECAP bit must be set to start the
continuous measurements.
When the CH(n+1)F bit is set, both edges were captured and the captured values are
ready for reading in the C(n)V and C(n+1)V registers. The latest captured values are
always available in these registers even after the DECAP bit is cleared.
In this mode, it is possible to clear only the CH(n+1)F bit. Therefore, when the CH(n+1)F
bit is set again, the latest captured values are available in C(n)V and C(n+1)V registers.
For a new sequence of the measurements in the Dual Edge Capture – Continuous mode,
clear the CH(n)F and CH(n+1)F bits to start new measurements.
23.5.24.3 Pulse width measurement
If the channel (n) is configured to capture rising edges (ELS(n)B:ELS(n)A = 0:1) and the
channel (n+1) to capture falling edges (ELS(n+1)B:ELS(n+1)A = 1:0), then the positive
polarity pulse width is measured. If the channel (n) is configured to capture falling edges
(ELS(n)B:ELS(n)A = 1:0) and the channel (n+1) to capture rising edges (ELS(n
+1)B:ELS(n+1)A = 0:1), then the negative polarity pulse width is measured.
The pulse width measurement can be made in One-Shot Capture mode or Continuous
Capture mode.
The following figure shows an example of the Dual Edge Capture – One-Shot mode used
to measure the positive polarity pulse width. The DECAPEN bit selects the Dual Edge
Capture mode, so it remains set. The DECAP bit is set to enable the measurement of next
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1272 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
positive polarity pulse width. The CH(n)F bit is set when the first edge of this pulse is
detected, that is, the edge selected by ELS(n)B:ELS(n)A bits. The CH(n+1)F bit is set
and DECAP bit is cleared when the second edge of this pulse is detected, that is, the edge
selected by ELS(n+1)B:ELS(n+1)A bits. Both DECAP and CH(n+1)F bits indicate when
two edges of the pulse were captured and the C(n)V and C(n+1)V registers are ready for
reading.
4 8 12 16 20 24
3 28
7 11 15 19
FTM counter 23 27
2 6 10 14 18 22 26
1 5 9 13 17 21 25
channel (n) input
(after the filter
channel input)
DECAPEN bit
set DECAPEN
DECAP bit
set DECAP
C(n)V 1 3 5 7 9 15 19
CH(n)F bit
clear CH(n)F
C(n+1)V 2 4 6 8 10 16 20 22 24
CH(n+1)F bit
clear CH(n+1)F
problem 1 problem 2
Note
- The commands set DECAPEN, set DECAP, clear CH(n)F, and clear CH(n+1)F are made by the user.
- Problem 1: channel (n) input = 1, set DECAP, not clear CH(n)F, and clear CH(n+1)F.
- Problem 2: channel (n) input = 1, set DECAP, not clear CH(n)F, and not clear CH(n+1)F.
Figure 23-82. Dual Edge Capture – One-Shot mode for positive polarity pulse width
measurement
The following figure shows an example of the Dual Edge Capture – Continuous mode
used to measure the positive polarity pulse width. The DECAPEN bit selects the Dual
Edge Capture mode, so it remains set. While the DECAP bit is set the configured
measurements are made. The CH(n)F bit is set when the first edge of the positive polarity
pulse is detected, that is, the edge selected by ELS(n)B:ELS(n)A bits. The CH(n+1)F bit
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1273
Functional description
is set when the second edge of this pulse is detected, that is, the edge selected by ELS(n
+1)B:ELS(n+1)A bits. The CH(n+1)F bit indicates when two edges of the pulse were
captured and the C(n)V and C(n+1)V registers are ready for reading.
4 8 12 16 20 24 28
3 7 11 15 19
FTM counter 23 27
2 6 10 14 18 22 26
1 5 9 13 17 21 25
channel (n) input
(after the filter
channel input)
DECAPEN bit
set DECAPEN
DECAP bit
set DECAP
C(n)V 1 3 5 7 9 11 15 19 21 23
CH(n)F bit
clear CH(n)F
C(n+1)V 2 4 6 8 10 12 16 20 22 24
CH(n+1)F bit
clear CH(n+1)F
Note
- The commands set DECAPEN, set DECAP, clear CH(n)F, and clear CH(n+1)F are made by the user.
Figure 23-83. Dual Edge Capture – Continuous mode for positive polarity pulse width
measurement
23.5.24.4 Period measurement
If the channels (n) and (n+1) are configured to capture consecutive edges of the same
polarity, then the period of the channel (n) input signal is measured. If both channels (n)
and (n+1) are configured to capture rising edges (ELS(n)B:ELS(n)A = 0:1 and ELS(n
+1)B:ELS(n+1)A = 0:1), then the period between two consecutive rising edges is
measured. If both channels (n) and (n+1) are configured to capture falling edges
(ELS(n)B:ELS(n)A = 1:0 and ELS(n+1)B:ELS(n+1)A = 1:0), then the period between
two consecutive falling edges is measured.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1274 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
The period measurement can be made in One-Shot Capture mode or Continuous Capture
mode.
The following figure shows an example of the Dual Edge Capture – One-Shot mode used
to measure the period between two consecutive rising edges. The DECAPEN bit selects
the Dual Edge Capture mode, so it remains set. The DECAP bit is set to enable the
measurement of next period. The CH(n)F bit is set when the first rising edge is detected,
that is, the edge selected by ELS(n)B:ELS(n)A bits. The CH(n+1)F bit is set and DECAP
bit is cleared when the second rising edge is detected, that is, the edge selected by ELS(n
+1)B:ELS(n+1)A bits. Both DECAP and CH(n+1)F bits indicate when two selected
edges were captured and the C(n)V and C(n+1)V registers are ready for reading.
4 8 12 16 20 24
3 28
7 11 15 19 23
FTM counter 2 6 27
10 14 18
1 22 26
5 9 13 17 21 25
channel (n) input
(after the filter
channel input)
DECAPEN bit
set DECAPEN
DECAP bit
set DECAP
C(n)V 1 3 5 6 7 14 17 18 20 27
CH(n)F bit
clear CH(n)F
C(n+1)V 2 4 6 7 9 15 18 20 23 26
CH(n+1)F bit
clear CH(n+1)F
problem 1 problem 2 problem 3
Note
- The commands set DECAPEN, set DECAP, clear CH(n)F, and clear CH(n+1)F are made by the user.
- Problem 1: channel (n) input = 0, set DECAP, not clear CH(n)F, and not clear CH(n+1)F.
- Problem 2: channel (n) input = 1, set DECAP, not clear CH(n)F, and clear CH(n+1)F.
- Problem 3: channel (n) input = 1, set DECAP, not clear CH(n)F, and not clear CH(n+1)F.
Figure 23-84. Dual Edge Capture – One-Shot mode to measure of the period between
two consecutive rising edges
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1275
Functional description
The following figure shows an example of the Dual Edge Capture – Continuous mode
used to measure the period between two consecutive rising edges. The DECAPEN bit
selects the Dual Edge Capture mode, so it remains set. While the DECAP bit is set the
configured measurements are made. The CH(n)F bit is set when the first rising edge is
detected, that is, the edge selected by ELS(n)B:ELS(n)A bits. The CH(n+1)F bit is set
when the second rising edge is detected, that is, the edge selected by ELS(n+1)B:ELS(n
+1)A bits. The CH(n+1)F bit indicates when two edges of the period were captured and
the C(n)V and C(n+1)V registers are ready for reading.
4 8 12 16 20 24 28
3 7 11 15 19 23
FTM counter 2 6 10 14
27
18 22 26
1 5 9 13 17 21 25
channel (n) input
(after the filter
channel input)
DECAPEN bit
set DECAPEN
DECAP bit
set DECAP
C(n)V 1 3 5 6 7 8 9 10 11 12 14 15 16 18 19 20 21 22 23 24 26
CH(n)F bit
clear CH(n)F
C(n+1)V 2 4 6 7 8 9 10 11 12 13 15 16 17 19 20 21 22 23 24 25 27
CH(n+1)F bit
clear CH(n+1)F
Note
- The commands set DECAPEN, set DECAP, clear CH(n)F, and clear CH(n+1)F are made by the user.
Figure 23-85. Dual Edge Capture – Continuous mode to measure of the period between
two consecutive rising edges
23.5.24.5 Read coherency mechanism
The Dual Edge Capture mode implements a read coherency mechanism between the
FTM counter value captured in C(n)V and C(n+1)V registers. The read coherency
mechanism is illustrated in the following figure. In this example, the channels (n) and (n
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1276 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
+1) are in Dual Edge Capture – Continuous mode for positive polarity pulse width
measurement. Thus, the channel (n) is configured to capture the FTM counter value when
there is a rising edge at channel (n) input signal, and channel (n+1) to capture the FTM
counter value when there is a falling edge at channel (n) input signal.
When a rising edge occurs in the channel (n) input signal, the FTM counter value is
captured into channel (n) capture buffer. The channel (n) capture buffer value is
transferred to C(n)V register when a falling edge occurs in the channel (n) input signal.
C(n)V register has the FTM counter value when the previous rising edge occurred, and
the channel (n) capture buffer has the FTM counter value when the last rising edge
occurred.
When a falling edge occurs in the channel (n) input signal, the FTM counter value is
captured into channel (n+1) capture buffer. The channel (n+1) capture buffer value is
transferred to C(n+1)V register when the C(n)V register is read.
In the following figure, the read of C(n)V returns the FTM counter value when the event
1 occurred and the read of C(n+1)V returns the FTM counter value when the event 2
occurred.
event 1 event 2 event 3 event 4 event 5 event 6 event 7 event 8 event 9
FTM counter 1 2 3 4 5 6 7 8 9
channel (n) input
(after the filter
channel input)
channel (n) 1 3 5 7 9
capture buffer
C(n)V 1 3 5 7
channel (n+1) 2 4 6 8
capture buffer
C(n+1)V 2
read C(n)V read C(n+1)V
Figure 23-86. Dual Edge Capture mode read coherency mechanism
C(n)V register must be read prior to C(n+1)V register in dual edge capture one-shot and
continuous modes for the read coherency mechanism works properly.
23.5.25 Quadrature Decoder mode
The Quadrature Decoder mode is selected if (QUADEN = 1). The Quadrature Decoder
mode uses the input signals phase A and B to control the FTM counter increment and
decrement. The following figure shows the quadrature decoder block diagram.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1277
Functional description
PHAFLTREN
CH0FVAL[3:0]
synchronizer CNTIN
0
MOD
phase A input D Q D Q filtered phase A signal
PHAPOL PHBPOL
Filter 1
system clock CLK CLK FTM counter
enable
FTM counter up/down
direction
PHBFLTREN
CH1FVAL[3:0]
synchronizer TOFDIR QUADIR
0
phase B input D Q D Q
filtered phase B signal
Filter 1
CLK CLK
Figure 23-87. Quadrature Decoder block diagram
Each one of input signals phase A and B has a filter that is equivalent to the filter used in
the channels input; Filter for Input Capture mode. The phase A input filter is enabled by
PHAFLTREN bit and this filter’s value is defined by CH0FVAL[3:0] bits
(CH(n)FVAL[3:0] bits in FILTER0 register). The phase B input filter is enabled by
PHBFLTREN bit and this filter’s value is defined by CH1FVAL[3:0] bits (CH(n
+1)FVAL[3:0] bits in FILTER0 register).
Except for CH0FVAL[3:0] and CH1FVAL[3:0] bits, no channel logic is used in
Quadrature Decoder mode.
Note
Notice that the FTM counter is clocked by the phase A and B
input signals when quadrature decoder mode is selected.
Therefore it is expected that the Quadrature Decoder be used
only with the FTM channels in input capture or output compare
modes.
Note
An edge at phase A must not occur together an edge at phase B
and vice-versa.
The PHAPOL bit selects the polarity of the phase A input, and the PHBPOL bit selects
the polarity of the phase B input.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1278 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
The QUADMODE selects the encoding mode used in the Quadrature Decoder mode. If
QUADMODE = 1, then the count and direction encoding mode is enabled; see the
following figure. In this mode, the phase B input value indicates the counting direction,
and the phase A input defines the counting rate. The FTM counter is updated when there
is a rising edge at phase A input signal.
phase B (counting direction)
phase A (counting rate)
FTM counter
increment/decrement +1 +1 +1 +1 +1 +1 +1 +1 -1 -1 -1 -1 -1
FTM counter
MOD
CNTIN
0x0000
Time
Figure 23-88. Quadrature Decoder – Count and Direction Encoding mode
If QUADMODE = 0, then the Phase A and Phase B Encoding mode is enabled; see the
following figure. In this mode, the relationship between phase A and B signals indicates
the counting direction, and phase A and B signals define the counting rate. The FTM
counter is updated when there is an edge either at the phase A or phase B signals.
If PHAPOL = 0 and PHBPOL = 0, then the FTM counter increment happens when:
• there is a rising edge at phase A signal and phase B signal is at logic zero;
• there is a rising edge at phase B signal and phase A signal is at logic one;
• there is a falling edge at phase B signal and phase A signal is at logic zero;
• there is a falling edge at phase A signal and phase B signal is at logic one;
and the FTM counter decrement happens when:
• there is a falling edge at phase A signal and phase B signal is at logic zero;
• there is a falling edge at phase B signal and phase A signal is at logic one;
• there is a rising edge at phase B signal and phase A signal is at logic zero;
• there is a rising edge at phase A signal and phase B signal is at logic one.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1279
Functional description
phase A
phase B
FTM counter
increment/decrement +1 +1 +1 +1 +1 +1 +1 +1 -1 -1 -1 -1 -1 -1 -1 +1 +1 +1 +1 +1 +1 +1 +1 -1 -1 -1 -1 -1 -1 -1 +1 +1 +1 +1 +1 +1 +1
FTM counter
MOD
CNTIN
0x0000
Time
Figure 23-89. Quadrature Decoder – Phase A and Phase B Encoding mode
The following figure shows the FTM counter overflow in up counting. In this case, when
the FTM counter changes from MOD to CNTIN, TOF and TOFDIR bits are set. TOF bit
indicates the FTM counter overflow occurred. TOFDIR indicates the counting was up
when the FTM counter overflow occurred.
phase A
phase B
FTM counter +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1
increment/decrement
FTM counter
MOD
CNTIN
0x0000
Time
set TOF set TOF
set TOFDIR set TOFDIR
Figure 23-90. FTM Counter overflow in up counting for Quadrature Decoder mode
The following figure shows the FTM counter overflow in down counting. In this case,
when the FTM counter changes from CNTIN to MOD, TOF bit is set and TOFDIR bit is
cleared. TOF bit indicates the FTM counter overflow occurred. TOFDIR indicates the
counting was down when the FTM counter overflow occurred.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1280 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
phase A
phase B
FTM counter
-1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
increment/decrement
FTM counter
MOD
CNTIN
0x0000
Time
set TOF set TOF
clear TOFDIR clear TOFDIR
Figure 23-91. FTM counter overflow in down counting for Quadrature Decoder mode
23.5.25.1 Quadrature Decoder boundary conditions
The following figures show the FTM counter responding to motor jittering typical in
motor position control applications.
phase A
phase B
FTM counter
MOD
CNTIN
0x0000
Time
Figure 23-92. Motor position jittering in a mid count value
The following figure shows motor jittering produced by the phase B and A pulses
respectively:
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1281
Functional description
phase A
phase B
FTM counter
MOD
CNTIN
0x0000
Time
Figure 23-93. Motor position jittering near maximum and minimum count value
The first highlighted transition causes a jitter on the FTM counter value near the
maximum count value (MOD). The second indicated transition occurs on phase A and
causes the FTM counter transition between the maximum and minimum count values
which are defined by MOD and CNTIN registers.
The appropriate settings of the phase A and phase B input filters are important to avoid
glitches that may cause oscillation on the FTM counter value. The preceding figures
show examples of oscillations that can be caused by poor input filter setup. Thus, it is
important to guarantee a minimum pulse width to avoid these oscillations.
23.5.26 Intermediate load
The PWMLOAD register allows to update the MOD, CNTIN, and C(n)V registers with
the content of the register buffer at a defined load point. In this case, it is not required to
use the PWM synchronization.
There are multiple possible loading points for intermediate load:
Table 23-19. When possible loading points are enabled
Loading point Enabled
When the FTM counter wraps from MOD value to CNTIN Always
value
At the channel (j) match (FTM counter = C(j)V) When CHjSEL = 1
The following figure shows some examples of enabled loading points.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1282 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
FTM counter = MOD
FTM counter = C7V
FTM counter = C6V
FTM counter = C5V
FTM counter = C4V
FTM counter = C3V
FTM counter = C2V
FTM counter = C1V
FTM counter = C0V
(a)
(b)
(c)
(d)
(e)
(f)
NOTE
(a) LDOK = 0, CH0SEL = 0, CH1SEL = 0, CH2SEL = 0, CH3SEL = 0, CH4SEL = 0, CH5SEL = 0, CH6SEL = 0, CH7SEL = 0
(b) LDOK = 1, CH0SEL = 0, CH1SEL = 0, CH2SEL = 0, CH3SEL = 0, CH4SEL = 0, CH5SEL = 0, CH6SEL = 0, CH7SEL = 0
(c) LDOK = 0, CH0SEL = 0, CH1SEL = 0, CH2SEL = 0, CH3SEL = 1, CH4SEL = 0, CH5SEL = 0, CH6SEL = 0, CH7SEL = 0
(d) LDOK = 1, CH0SEL = 0, CH1SEL = 0, CH2SEL = 0, CH3SEL = 0, CH4SEL = 0, CH5SEL = 0, CH6SEL = 1, CH7SEL = 0
(e) LDOK = 1, CH0SEL = 1, CH1SEL = 0, CH2SEL = 1, CH3SEL = 0, CH4SEL = 1, CH5SEL = 0, CH6SEL = 1, CH7SEL = 0
(f) LDOK = 1, CH0SEL = 1, CH1SEL = 1, CH2SEL = 1, CH3SEL = 1, CH4SEL = 1, CH5SEL = 1, CH6SEL = 1, CH7SEL = 1
Figure 23-94. Loading points for intermediate load
After enabling the loading points, the LDOK bit must be set for the load to occur. In this
case, the load occurs at the next enabled loading point according to the following
conditions:
Table 23-20. Conditions for loads occurring at the next enabled loading point
When a new value was written Then
To the MOD register The MOD register is updated with its write buffer value.
To the CNTIN register and CNTINC = 1 The CNTIN register is updated with its write buffer value.
To the C(n)V register and SYNCENm = 1 – where m indicates The C(n)V register is updated with its write buffer value.
the pair channels (n) and (n+1)
To the C(n+1)V register and SYNCENm = 1 – where m The C(n+1)V register is updated with its write buffer value.
indicates the pair channels (n) and (n+1)
NOTE
• If ELSjB and ELSjA bits are different from zero, then the
channel (j) output signal is generated according to the
configured output mode. If ELSjB and ELSjA bits are zero,
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1283
Functional description
then the generated signal is not available on channel (j)
output.
• If CHjIE = 1, then the channel (j) interrupt is generated
when the channel (j) match occurs.
• At the intermediate load neither the channels outputs nor
the FTM counter are changed. Software must set the
intermediate load at a safe point in time.
23.5.27 Global time base (GTB)
The global time base (GTB) is a FTM function that allows the synchronization of
multiple FTM modules on a chip. The following figure shows an example of the GTB
feature used to synchronize two FTM modules. In this case, the FTM A and B channels
can behave as if just one FTM module was used, that is, a global time base.
FTM module A FTM module B
GTBEEN bit FTM counter
FTM counter enable
enable logic
gtb_in
gtb_in
example glue logic
gtb_out
GTBEOUT bit gtb_out
Figure 23-95. Global time base (GTB) block diagram
The GTB functionality is implemented by the GTBEEN and GTBEOUT bits in the
CONF register, the input signal gtb_in, and the output signal gtb_out. The GTBEEN bit
enables gtb_in to control the FTM counter enable signal:
• If GTBEEN = 0, each one of FTM modules works independently according to their
configured mode.
• If GTBEEN = 1, the FTM counter update is enabled only when gtb_in is 1.
In the configuration described in the preceding figure, FTM modules A and B have their
FTM counters enabled if at least one of the gtb_out signals from one of the FTM modules
is 1. There are several possible configurations for the interconnection of the gtb_in and
gtb_out signals, represented by the example glue logic shown in the figure. Note that
these configurations are chip-dependent and implemented outside of the FTM modules.
See the chip-specific FTM information for the chip's specific implementation.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1284 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
NOTE
• In order to use the GTB signals to synchronize the FTM
counter of different FTM modules, the configuration of
each FTM module should guarantee that its FTM counter
starts counting as soon as the gtb_in signal is 1.
• The GTB feature does not provide continuous
synchronization of FTM counters, meaning that the FTM
counters may lose synchronization during FTM operation.
The GTB feature only allows the FTM counters to start
their operation synchronously.
23.5.27.1 Enabling the global time base (GTB)
To enable the GTB feature, follow these steps for each participating FTM module:
1. Stop the FTM counter: Write 00b to SC[CLKS].
2. Program the FTM to the intended configuration. The FTM counter mode needs to be
consistent across all participating modules.
3. Write 1 to CONF[GTBEEN] and write 0 to CONF[GTBEOUT] at the same time.
4. Select the intended FTM counter clock source in SC[CLKS]. The clock source needs
to be consistent across all participating modules.
5. Reset the FTM counter: Write any value to the CNT register.
To initiate the GTB feature in the configuration described in the preceding figure, write 1
to CONF[GTBEOUT] in the FTM module used as the time base.
23.6 Reset overview
The FTM is reset whenever any chip reset occurs.
When the FTM exits from reset:
• the FTM counter and the prescaler counter are zero and are stopped (CLKS[1:0] =
00b);
• the timer overflow interrupt is zero, see Timer Overflow Interrupt;
• the channels interrupts are zero, see Channel (n) Interrupt;
• the fault interrupt is zero, see Fault Interrupt;
• the channels are in input capture mode, see Input Capture mode;
• the channels outputs are zero;
• the channels pins are not controlled by FTM (ELS(n)B:ELS(n)A = 0:0) (See the table
in the description of CnSC register).
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1285
Reset overview
The following figure shows the FTM behavior after the reset. At the reset (item 1), the
FTM counter is disabled (see the description of the CLKS field in the Status and Control
register), its value is updated to zero and the pins are not controlled by FTM (See the
table in the description of CnSC register).
After the reset, the FTM should be configurated (item 2). It is necessary to define the
FTM counter mode, the FTM counting limits (MOD and CNTIN registers value), the
channels mode and CnV registers value according to the channels mode.
Thus, it is recommended to write any value to CNT register (item 3). This write updates
the FTM counter with the CNTIN register value and the channels output with its initial
value (except for channels in output compare mode) (Counter reset).
The next step is to select the FTM counter clock by the CLKS[1:0] bits (item 4). It is
important to highlight that the pins are only controlled by FTM when CLKS[1:0] bits are
different from zero (See the table in the description of CnSC register).
(3) write any value
(1) FTM reset to CNT register (4) write 1 to SC[CLKS]
FTM counter XXXX 0x0000 0x0010 0x0011 0x0012 0x0013 0x0014 0x0015 0x0016 0x0017 0x0018 . . .
CLKS[1:0] XX 00 01
channel (n) output
(2) FTM configuration channel (n) pin is controlled by FTM
NOTES:
– CNTIN = 0x0010
– Channel (n) is in low-true combine mode with CNTIN < C(n)V < C(n+1)V < MOD
– C(n)V = 0x0015
Figure 23-96. FTM behavior after reset when the channel (n) is in Combine mode
The following figure shows an example when the channel (n) is in Output Compare mode
and the channel (n) output is toggled when there is a match. In the Output Compare
mode, the channel output is not updated to its initial value when there is a write to CNT
register (item 3). In this case, use the software output control (Software output control) or
the initialization (Initialization) to update the channel output to the selected value (item
4).
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1286 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
(4) use of software output control or initialization
to update the channel output to the zero
(3) write any value
(1) FTM reset to CNT register (5) write 1 to SC[CLKS]
FTM counter XXXX 0x0000 0x0010 0x0011 0x0012 0x0013 0x0014 0x0015 0x0016 0x0017 . . .
CLKS[1:0] XX 00 01
channel (n) output
(2) FTM configuration channel (n) pin is controlled by FTM
NOTES:
– CNTIN = 0x0010
– Channel (n) is in output compare and the channel (n) output is toggled when there is a match
– C(n)V = 0x0014
Figure 23-97. FTM behavior after reset when the channel (n) is in Output Compare mode
23.7 FTM Interrupts
23.7.1 Timer Overflow Interrupt
The timer overflow interrupt is generated when (TOIE = 1) and (TOF = 1).
23.7.2 Channel (n) Interrupt
The channel (n) interrupt is generated when (CHnIE = 1) and (CHnF = 1).
23.7.3 Fault Interrupt
The fault interrupt is generated when (FAULTIE = 1) and (FAULTF = 1).
23.8 Initialization Procedure
The following initialization procedure is recommended to configure the FlexTimer
operation. This procedure can also be used to do a new configuration of the FlexTimer
operation.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1287
Initialization Procedure
• Define the POL bits.
• Mask the channels outputs using SYNCHOM = 0. Two clocks after the write to
OUTMASK, the channels output are in the safe value.
• (Re)Configuration FTM counter and channels to generation of periodic signals -
Disable the clock. If the selected mode is Quadrature Decoder, then disable this
mode. Examples of the (re)configuration:
• Write to MOD.
• Write to CNTIN.
• Select OC, EPWM, CPWM, Combine, Complement modes for all channels that
will be used
• Select the high-true and low-true channels modes.
• Write to CnV for all channels that will be used .
• (Re)Configure deadtime and fault control.
• Do not use the SWOC without SW synchronization (see item 6).
• Do not use the Inverting without SW synchronization (see item 6).
• Do not use the Initialization.
• Do not change the polarity control.
• Do not configure the HW synchronization
• Write any value to CNT. The FTM Counter is reset and the channels output are
updated according to new configuration.
• Enable the clock. Write to CLKS[1:0] bits a value different from zero. If in the
Quadrature Decoder mode, enable this mode.
• Configure the SW synchronization for SWOC (if it is necessary), Inverting (if it is
necessary) and Output Mask (always)
• Select synchronization for Output Mask Write to SYNC (SWSYNC = 0, TRIG2
= 0, TRIG1 = 0, TRIG0 = 0, SYNCHOM = 1, REINIT = 0, CNTMAX = 0,
CNTMIN = 0)
• Write to SYNCONF.
• HW Synchronization can not be enabled (HWSOC = 0, HWINVC = 0,
HWOM = 0, HWWRBUF = 0, HWRSTCNT = 0, HWTRIGMODE = 0).
• SW Synchronization for SWOC (if it is necessary): SWSOC = [0/1] and
SWOC = [0/1].
• SW Synchronization for Inverting (if it is necessary): SWINVC = [0/1] and
INVC = [0/1].
• SW Synchronization for SWOM (always): SWOM = 1. No enable the SW
Synchronization for write buffers (because the writes to registers with write
buffer are done using CLKS[1:0] = 2’b00): SWWRBUF = 0 and CNTINC =
0.
• SW Synchronization for counter reset (always): SWRSTCNT = 1.
• Enhanced synchronization (always): SYNCMODE = 1
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1288 NXP Semiconductors
Chapter 23 FlexTimer Module (FTM)
• If the SWOC is used (SWSOC = 1 and SWOC = 1), then write to SWOCTRL
register.
• If the Inverting is used (SWINVC = 1 and INVC = 1), then write to INVCTRL
register.
• Write to OUTMASK to enable the masked channels.
• Generate the Software Trigger Write to SYNC (SWSYNC = 1, TRIG2 = 0, TRIG1 =
0, TRIG0 = 0, SYNCHOM = 1, REINIT = 0, CNTMAX = 0, CNTMIN = 0)
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1289
Initialization Procedure
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1290 NXP Semiconductors
Chapter 24
General Purpose I/O (GPIO)
24.1 The GPIO module as implemented on the chip
This section provides details about how the GPIO module is integrated into this chip.
Table 24-1. GPIO module as implemented on chip
Module name Module base Supported1 ports Number
address of ports
GPIO1 0x230_0000 13:31 (GPIO1[13] is output only signal) 19
GPIO2 0x231_0000 0:15, 25:27 19
GPIO3 0x232_0000 0:27 28
GPIO4 0x233_0000 0:3,10:13, 29:30 10
1. GPIO signals are typically multiplexed with other signals. “Supported” in this context means that any signal multiplexing
configuration has selected GPIO functionality. See the Signals chapter for signal multiplexing details.
24.2 GPIO overview
This chapter describes the general-purpose I/O (GPIO) module, including signal
descriptions, register settings and interrupt capabilities.
This figure shows the block diagram for the GPIO module.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1291
GPIO features summary
GPIO[n]
GPDAT
Register
To/From Register
Peripheral Bus Interface
GPDIR/
GPODR
GPIER/ Registers
GPIMR/
gpio_int
GPICR
Registers
Figure 24-1. GPIO module block diagram
In general, the GPIO module supports up to 32 general-purpose I/O ports. Each port can
be configured as an input or as an output. However, some implementations may restrict
specific ports to input-only, output-only, or reserved (unimplemented). See "The GPIO
module as implemented on the chip" section for more information. If a port is configured
as an input, it can optionally generate an interrupt upon detection of a change. If a port is
configured as an output, it can be individually configured as an open-drain or a fully
active output.
24.3 GPIO features summary
The GPIO unit includes the following features:
• Supports 32 general-purpose input/output ports
• All signals are high-impedance during reset
• Open-drain capability on all ports
• All ports can optionally generate an interrupt upon changing their state
• Ports may be multiplexed with other functional signals
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1292 NXP Semiconductors
Chapter 24 General Purpose I/O (GPIO)
24.4 GPIO signal descriptions
This table provides detailed descriptions of the external GPIO signals. Note that
depending on the signal multiplexing, some signals may not be available.
Table 24-2. GPIO external signals-detailed signal descriptions
Signal I/O Description
GPIOn[0:31] I/O General Purpose I/O. Each signal can be individually set to act as input or output, according to
application needs.
Some implementations may restrict specific ports to input-only, output-only, or reserved
(unimplemented). See "The GPIO module as implemented on the chip" section for more information.
State Asserted/Negated-Defined per application.
Meaning
Timing Assertion/Negation-Inputs can be asserted completely asynchronously.
Outputs are asynchronous to any externally visible clock.
24.5 GPIO register descriptions
The programmable register map for the GPIO module occupies 28 bytes of memory-
mapped space. The full register address is comprised of the base address (specified in
CCSR address space) plus the module base address, plus the specific register's offset
within the module. The table below shows the memory map for the GPIO module.
All GPIO registers are 32 bits wide located on 32-bit address boundaries. Note that
reading undefined portions of the memory map returns all zeros and writing has no effect.
24.5.1 GPIO Memory map
GPIO1 base address: 230_0000h
GPIO2 base address: 231_0000h
GPIO3 base address: 232_0000h
GPIO4 base address: 233_0000h
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1293
GPIO register descriptions
Offset Register Width Access Reset value
(In bits)
0h GPIO direction register (GPDIR) 32 RW 0000_0000h
4h GPIO open drain register (GPODR) 32 RW 0000_0000h
8h GPIO data register (GPDAT) 32 RW 0000_0000h
Ch GPIO interrupt event register (GPIER) 32 W1C See
description.
10h GPIO interrupt mask register (GPIMR) 32 RW 0000_0000h
14h GPIO interrupt control register (GPICR) 32 RW 0000_0000h
24.5.2 GPIO direction register (GPDIR)
24.5.2.1 Offset
Register Offset
GPDIR 0h
24.5.2.2 Function
The GPIO direction register (GPDIR) defines the direction of the individual ports.
24.5.2.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
DRn
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
DRn
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1294 NXP Semiconductors
Chapter 24 General Purpose I/O (GPIO)
24.5.2.4 Fields
Field Function
0-31 Direction. Indicates whether a pin is used as an input or an output.
DRn 00000000000000000000000000000000b - The corresponding pin is an input.
00000000000000000000000000000001b - The corresponding pin is an output.
24.5.3 GPIO open drain register (GPODR)
24.5.3.1 Offset
Register Offset
GPODR 4h
24.5.3.2 Function
The GPIO open drain register (GPODR) defines the way individual ports drive their
output.
24.5.3.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
ODn
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
ODn
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1295
GPIO register descriptions
24.5.3.4 Fields
Field Function
0-31 Open drain configuration. Indicates whether a signal is actively driven as an output or is an open-drain
driver. This register has no effect on signals programmed as inputs in GPDIR.
ODn
00000000000000000000000000000000b - The corresponding signal is actively driven as an
output.
00000000000000000000000000000001b - The corresponding signal is an open-drain driver. As an
output, the signal is driven active-low, otherwise it is not driven (high impedance).
24.5.4 GPIO data register (GPDAT)
24.5.4.1 Offset
Register Offset
GPDAT 8h
24.5.4.2 Function
The GPIO data register (GPDAT) carries the data in/out for the individual ports.
24.5.4.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
Dn
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
Dn
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1296 NXP Semiconductors
Chapter 24 General Purpose I/O (GPIO)
24.5.4.4 Fields
Field Function
0-31 Data. Writes to this register latches the data which is presented on the external pins provided the
corresponding GPDIR bit is configured as an output. When GPDIR is in output mode, GPDAT read
Dn
operation returns data at pin. When GPDIR is in input mode, GPDAT read operation returns state of the
port.
24.5.5 GPIO interrupt event register (GPIER)
24.5.5.1 Offset
Register Offset
GPIER Ch
24.5.5.2 Function
The GPIO interrupt event register (GPIER) carries information of the events that caused
an interrupt. Each bit in GPIER, corresponds to an interrupt source. GPIER bits are
cleared by writing ones. However, writing zero has no effect.
NOTE
Some implementations may ignore the interrupt mask as
configured in GPIMR. In these implementations, a GPIER bit
can be set even though the associated interrupt is masked. See
The "GPIO module as implemented on the chip" section for
more information.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1297
GPIO register descriptions
24.5.5.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R EVn
W W1C
Reset u u u u u u u u u u u u u u u u
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R EVn
W W1C
Reset u u u u u u u u u u u u u u u u
24.5.5.4 Fields
Field Function
0-31 Interrupt events. Indicates whether an interrupt event occurred on the corresponding GPIO signal.
EVn 00000000000000000000000000000000b - No interrupt event occurred on the corresponding GPIO
signal.
00000000000000000000000000000001b - An interrupt event occurred on the corresponding GPIO
signal.
24.5.6 GPIO interrupt mask register (GPIMR)
24.5.6.1 Offset
Register Offset
GPIMR 10h
24.5.6.2 Function
The GPIO interrupt mask register (GPIMR) defines the interrupt masking for the
individual ports. When a masked interrupt request occurs, the corresponding GPIER bit is
set, regardless of the GPIMR state. When one or more non-masked interrupt events
occur, the GPIO module issues an interrupt to the interrupt controller.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1298 NXP Semiconductors
Chapter 24 General Purpose I/O (GPIO)
24.5.6.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
IMn
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
IMn
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
24.5.6.4 Fields
Field Function
0-31 Interrupt mask. Indicates whether an interrupt event is masked or not masked for the corresponding
GPIO signal.
IMn
00000000000000000000000000000000b - The input interrupt signal is masked (disabled).
00000000000000000000000000000001b - The input interrupt signal is not masked (enabled).
24.5.7 GPIO interrupt control register (GPICR)
24.5.7.1 Offset
Register Offset
GPICR 14h
24.5.7.2 Function
The GPIO interrupt control register (GPICR) determines whether the corresponding port
line asserts an interrupt request upon either a high-to-low change or any change on the
state of the signal.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1299
GPIO register descriptions
24.5.7.3 Diagram
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
EDn
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
EDn
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
24.5.7.4 Fields
Field Function
0-31 Edge detection mode. The corresponding port line asserts an interrupt request according to the following:
EDn 00000000000000000000000000000000b - Any change on the state of the port generates an
interrupt request.
00000000000000000000000000000001b - High-to-low change on the port generates an interrupt
request.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1300 NXP Semiconductors
Chapter 25
Integrated Flash Controller (IFC)
25.1 IFC overview
The integrated flash controller (IFC) is used to interface with external asynchronous/
synchronous NAND flash, asynchronous NOR flash, SRAM, generic ASIC memory and
EPROM.
It has seven chip-selects, to which a maximum of seven flash devices can be attached,
although only one of these can be accessed at any given time.
The IFC handles pin multiplexing to the internal system bus based on the selected
controller (NAND, NOR, GPCM, or generic ASIC). To save pins at the chip level,
multiplexing of address pins can be done on the data bus using an address valid signal
(AVD). The BCH error-correction algorithm is used to correct the error bits while
reading from a NAND device.
This figure shows the block diagram of IFC.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1301
IFC overview
Programming interface to
system bus IFC clock
Clock control
module
GPCM
Programming Generic
registers ASIC FSM
Normal GPCM
FSM
NOR FCM
Data External
interface Data machine interface
to system Flash interface
bus arbiter
NAND FCM
NAND
async FCM
SRAM control unit
NAND Data
BCH encoder
Path
Error-fixing
BCH decoder
64-bit SRAM (1r1w) logic
Bus
Key Single signal line
Slave bus signal
Figure 25-1. IFC block diagram
25.1.1 IFC features summary
The IFC supports both general and controller-specific features.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1302 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
The general features of the IFC include the following:
• Flash controller with seven chip-selects
• Supports error and debug registers
• Functional muxing of pins between NAND, NOR, and GPCM
• Supports memory banks of sizes up to 256 MB (for NOR and GPCM)
• Write-protection capability (for NAND and NOR)
• Provision of software reset
• External transceiver enable/disable control on a per-bank basis
25.1.1.1 NAND flash features
The IFC features a NAND flash controller.
• x8/x16 NAND flash interface
• Support for ONFI-2.2 asynchronous interface (8-/16-bit)/NVDDR interface and
mandatory commands
• BCH code for 4-bit and 8-bit error correction per sector of 512 bytes (using GF-213
Galois field) and 24 and 40-bit ECC per sector of 1 KB (using GF- 214 Galois field):
• For a 512-byte page and 16-byte spare region, 4-bit error correction is supported
• For a 2 KB page and 64-byte spare region, 4-bit error correction is supported
• For a 4 KB page width:
• For 128-byte spare region, 4-bit error correction is supported
• For 210-, 218-, and 224-byte spare regions, 4- or 8-bit error correction is
supported
• Spare size of minimum 176 bytes (8 for BBI + 4x42 for ECC bytes), 4-, 8-,
or 24-bit BCH
• Spare size of minimum 288 bytes (8 for BBI + 4x70 for ECC bytes), 4-, 8-,
24-, or 40-bit BCH
• For an 8 KB page width:
• At least 136(8 + 128) bytes of spare region is required for bad block
information and ECC bytes, 4-bit BCH
• 8 KB page, at least 264(8 + 256) bytes of spare region required for bad block
information and ECC bytes, 4-bit or 8-bit BCH
• Spare size of minimum 344 bytes (8 for BBI + 8x42 for ECC bytes), 4-, 8-,
or 24-bit BCH
• Spare size of minimum 568 bytes (8 for BBI + 8x70 for ECC bytes), 4-, 8-,
24-, or 40-bit BCH
• For all ECC modes (4/8/24/40), parity bytes are stored at offset 08h in a spare
region
• ECC generation/checking is optional
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1303
IFC overview
• Flexible timing control to allow interfacing with proprietary NAND devices
• Supports SLC and MLC flash devices with configurable page sizes of up to 8 KB
• Supports advance NAND commands such as cache, copy-back, and multi-plane
programming
• Supports four RDY_B/BSY_B signals
• Programmable command and data transfer sequences of up to 15 steps
• Configurable block-size
• Interrupt for error handling and flash command completion event
• Internal SRAM of 9 KB
• Memory-mapped
• Can be configured as boot RAM
• Acts as data buffer for normal operation
• Boot chip-select (CS0) available after system reset, with a boot block size of 8 KB
for execute-in-place boot loading from NAND flash
• Supports flash devices of a magnitude of terabytes
• By using 32 bit row address, 4 Giga pages of NAND flash can be accessed
25.1.1.2 NOR flash features
The IFC features a NOR flash controller.
• Compatible with asynchronous NOR flash (synchronous burst-read not supported)
• Provides memory-mapped interfacing to NOR
• Supports an address data multiplexed (ADM) NOR device
• Flexible timing control allows interfacing with proprietary NOR devices (WE_B
controlled writes only)
• Boot chip-select (CS0) is available at system reset
• Data bus width of 16-bits
• Burst size in NOR is governed by system bus size and length
25.1.1.3 GPCM and GASIC features
The IFC’s general-purpose, chip-select Controller (GPCM) supports operation in either
normal or generic ASIC modes.
Normal GPCM features include the following:
• Support for x8-/16-bit devices
• Compatible with general-purpose addressable device, such as SRAM and ROM
• External clock is generated with programmable division ratio (2, 3, 4, ... up to 16)
• Output enable signal (OE_B)
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1304 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
• Write enable signal(s) (WE_B)
• Even/odd parity data bus support
• External access termination signal (IFCTA_B)
• Programmable burst support
Generic ASIC features include the following:
• Support for x8-/16-bit devices
• Address and data are shared on I/O bus
• The following address and data sequences are supported on the I/O bus:
• 16-bit I/O: AADD
• 8-bit I/O: AAAADDDD
• Configurable even/odd parity on address/data bus
• Parity-error detection
25.1.2 IFC modes of operation
The IFC contains one NAND controller, one NOR flash controller, and one GPCM/
generic-ASIC controller.
It can be programmed such that all seven memory banks can work with NAND, NOR,
and GPCM/generic-ASIC interfaces as required. However, only one memory bank can be
active at any given time.
25.2 External signal descriptions
This section provides both general and detailed information on the chip's external signals.
This table provides an overview of the chip's external signals, and the following table
then provides a much more detailed description of the signals.
Table 25-1. Signal properties
Chip signal IFC signal name Alternate Mode Description / Number of I/O
name Functions Function signals
IFC_AD[0:15] AD[0:15] AD[0:15] NAND FCM I/O Bus for 16 I/O
Asynchronous
NAND
AD[0:7] NVDDR I/O Bus for
NVDDR sync
NAND
AD[0:15] NOR FCM Bidirectional
Data Bus for
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1305
External signal descriptions
Table 25-1. Signal properties (continued)
Chip signal IFC signal name Alternate Mode Description / Number of I/O
name Functions Function signals
NOR. During
AVD assertion,
this bus will
carry address
bits. Address
LSB or MSB will
be governed by
CSOR[ADM_SH
FT_MODE]
AD[0:15] GPCM Bidirectional
data bus for
GPCM. For
external address
latching, this bus
is used to carry
address MSBs.
AD[0:15] GASIC Bidirectional
shared address/
data bus for
GASIC.
IFC_A[16:27] ADDR[16:27] - - Dedicated 12 O
address bus
used by NOR
and GPCM
mode
IFC_PAR[0:1] PAR[0:1] PAR[0:1] GPCM Parity data 2 I/O
PAR[0:1] GASIC Parity address
and data
IFC_NDDDR_CLK IFC_NDDDR_CLK IFC_NDDDR_CLK NV-DDR External IFC 1 O
DDR Clock
(NVDDR mode)
NDWE_B Async NAND NAND Write 1 O
Enable
IFC_CS[0:6]_B CE/CS[0:6]_B - - Chip Selects 7 O
NDWE_B Async NAND Write
Enable
IFC_BCTL BCTL - - Data buffer 1 O
control
IFC_TE TE - - External 1 I/O
Transceiver
Enable/Disable
Control
IFC_NDDQS NDDQS - NVDDR Data Qualify 1 I/O
Strobe to/from
NAND memory
(in NVDDR )
IFC_AVD ALE/AVD NDALE NAND FCM NAND Address 1 O
Latch Enable
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1306 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
Table 25-1. Signal properties (continued)
Chip signal IFC signal name Alternate Mode Description / Number of I/O
name Functions Function signals
NRAVD NOR FCM NOR External
Address Latch
Enable/AVD
GPALE GPCM GPCM External
Address Latch
Enable
IFC_CLE CLE NDCLE NAND FCM NAND 1 O
Command Latch
Enable
GPWE1_B GPCM GPCM Write
Byte Select 1
IFC_OE_B OE_B NROE_B NOR FCM NOR Output 1 O
Enable
GPOE_B GPCM GPCM Output
Enable
RW_L_B GASIC GASIC Read/
Write Indication
NDRE_B Async/NVDDR NAND Read
Enable
IFC_WP[0:3]_B WP[0:3]_B NDWP[0:3]_B NAND FCM Per chip select 4 O
based NAND
Write Protect
IFC_RB[0:3]_B RB[0:3]_B NAND FCM NAND Ready/ 4 I
Busy Input
NRRB[0:3]_B NOR FCM NOR
Ready
Busy
Input
IFCTA[0:3]_B GPCM GPCM
External
Termina
tion
RDY_L[0:3]_B GASIC GASIC
Ready
Indicatio
n
IFC_PERR_B PERR_L_B PERR_L_B GASIC Parity error from 1 I
Generic ASIC
IFC_CLK[0:1] CLK[0:1] - - External IFC 2 O
clock
This table describes the external signals in detail.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1307
External signal descriptions
Table 25-2. Detailed signal description
Signal I/O Description
AD[0:n] I/O Multiplexed address/data bus.
State Asserted/Negated - During the assertion of AVD, AD[0:n] are driven with the address
meaning for the access to follow. External logic should propagate the address on AD[0:n]while
AVD is asserted and latch the address upon negation of AVD. After it is negated,
AD[0:n] are either driven by write data or are switched to an input to sample read data
driven by an external device. Following the last data transfer of a write access, AD[0:n]
are released to a high-impedance state.
For exact functionality, behavior, and timings, refer to detailed waveform and timing
diagrams within the specific interface.
ADDR[n:m] O Non-multiplexed address bus.
State Asserted/Negated - It is a non-multiplexed address bus which carries address MSBs or
meaning LSBs depending on CSOR[ADM_SHFT_MODE].
ALE O External Address Latch Enable (NAND)
External Address Valid Signal (NOR)
External Address Latch Enable(GPCM)
Control signal for an external address latch, which allows address and data to be multiplexed on the
device pins
State Asserted - Latch enable is asserted with the address at the beginning of each memory
meaning controller transaction. The number of cycles for which it is asserted is governed by the
FTIM0_CSn[EADC] field.
Negated - The exact timing of the negation of AVD is controlled by the
FTIM0_CSn[EAHC] field. Note that no other control signals are asserted during the
assertion of AVD.
CS[0:n]_B O Chip-Select; mutually exclusive chip-selects are available.
State Asserted/Negated - Used to enable each specific memory device connected to the IFC.
meaning CS_B[0] corresponds to the chip-select for memory bank 0, which has the memory
type and attributes defined by CSPR0 and FTIM0_CS0.
WE[0]_B O NOR write enable, GPCM write byte select 0, GASIC start of frame.
State Asserted/Negated - Used to control the data write cycles on NOR flash.
meaning
For GPCM it validates its corresponding byte number on the data bus.
For GASIC it indicates start of a transaction frame.
NDDQS I/O Bi-directional Data Qualify Strobe for NAND in NV-DDR mode
State Bi-directional signal used to capture write data in the NAND flash and read data in IFC.
Meaning Data is captured/driven on both of its edges (rising and falling).
For program operations, the DQS is centred with respect to program data when driven
by IFC.
For read operations, the DQS is edge-aligned with respect to read data when driven by
NAND memory.
CLE O NAND Command latch enable, GPCM write byte select 1 which is WE[1]_B.
State Asserted/Negated - It enables the command cycle on NAND flash.
meaning
For GPCM it validates 1st byte(AD [8:15]) on data bus.
OE_B O NAND read enable, NOR output enable, GPCM output enable, GASIC Read/Write Enable and is
valid only when SOF_L_B is asserted.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1308 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
Table 25-2. Detailed signal description (continued)
Signal I/O Description
State Asserted/Negated - It enables data read cycles on NOR and GPCM devices.
meaning
For GASIC, it indicates whether the transaction is read or write. High value on this
indicates read operation while low value indicates write.
WP[0:n]_B O Per chip select based non-muxed NAND Write Protect Output.
State Asserted/Negated - It protects NAND flash from accidental erasure or program when
meaning asserted low. For GPCM it validates the corresponding byte number on data bus.
RB[0:n]_B I NAND ready busy for all the chip-selects, NOR Read Busy, GPCM External Termination of Access,
GASIC Ready Indication. Valid after the completion of address phase till it asserts.
State Asserted/Negated - It indicates the ready busy status of the flash operation. It is used
meaning to stall the controller operation when the flash is indicating busy.
For GPCM this input is used for termination of current access.
For GASIC it indicates that the current GASIC transaction is accepted by device and
the host can start the next transaction.
BCTL O Data buffer control. Buffer control is disabled by FTIM0_CS0[BCTLD] field.
State Asserted/Negated - The BCTL pin normally functions as a write (High)/read (Low)
meaning direction control for the external data buffer used in the AD lines (bidirectional bus).
Default value of BCTL is high (write direction).
TE I/O External transceiver enable/disable. This pin acts as an input during reset and should be weakly
pulled up/down so as to disable the external transceiver during that time. After reset, the IFC drives
TE with the value configured in CSPRn[TE] as per the selected chip select. When none of the CS
pins are selected, TE is driven High-Z from the IFC (the external transceiver will be disabled by the
appropriate external pull device).
State Asserted/Negated - The TE pin functions as an enable/disable for an external
meaning transceiver connected to the AD lines. In asserted state, it enables the external
transceiver and when negated, disables the transceiver.
PAR[0:n] I/O GPCM data bus parity, GASIC address bus parity.
State Asserted/Negated - For GPCM during Write a parity bit is generated for each data byte
meaning sent over the bus. Unused byte lanes have undefined parity.
For GASIC a parity bit is sent for each address and data byte sent over the AD bus.
IFC_NDDDR_CL O IFC NAND DDR External Clock for NV-DDR mode
K/NDWE_B
NAND Write Enable for ASync
State NV-DDR mode: External divided clock derived from IP clock for the NAND Flash.
Meaning
ASync Used to control write cycles for NAND Flash
PERR_L_B I GASIC parity error indication. PERR_B is sampled a configurable number of IFC_CLK cycles after
the assertion of SOF_L_B.
State Asserted/Negated - Parity error is indicated by GASIC for wrong parity sent for address
meaning and data bytes.
CLK[0:n] O IFC external clock.
State This is an external clock derived from the IFC module input clock. Division ratio is
meaning programmable (using CCR register).
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1309
External signal descriptions
25.2.1 Internal connectivity of WP/RB signal
The IFC supports one write protect and one ready/busy signal per chip select. The
available write protect and ready/busy signals are mapped to the seven chip selects that
the IFC supports.
The chip supports one dedicated write protect signal (IFC_WP0_B), three multiplexed
write protect pins (IFC_WP[1:3]_B), one dedicated ready/busy signals (IFC_RB0_B) and
three multiplexed ready/busy signals IFC_RB[1:3]_B .
NOTE
The internal connectivity of WP/RB signal depends on the IFC
mode selected by RCW[IFC_MODE].
25.2.1.1 Internal connectivity of WP signal
For the 25/28-bit address mode, the write protect signal (WP0_B) is sourced by the
logical OR of all the seven write protect signals from the IFC block which corresponds to
chip selects 0-6.
WP0
WP1
WP2
WP3
WP4 WP0
WP5
WP6
Figure 25-2. Internal connectivity of WP signal for 25/28-bit address mode
For the 22-bit address mode, the first three write protect signals WP_B[0:2] are directly
sourced by the three write protect signals from the IFC block which correspond to chip
selects 0-2, respectively. The fourth write protect signal (WP_B[3]) is sourced by the
logical OR of the remaining four write protect signals from the IFC block which
correspond to chip selects 3-6. This allows for some flexibility in controlling write
protection to individual or groups of NAND flash devices.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1310 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
WP0 WP0
WP1 WP1
WP2 WP2
WP3
WP4
WP3
WP5
WP6
Figure 25-3. Internal connectivity of WP signal for 22-bit address mode
25.2.1.2 Internal connectivity of RB signal
For the 28-bit address mode:RB1_B is directly routed to the ready/busy inputs of the IFC
block which correspond to chip select 1.
The first ready/busy signal RB0_B is routed to the ready/busy inputs of the IFC block
which correspond to chip selects 0 and 2-6. In these modes of operation, this overall
solution allows for one bank of flash to be fully optimized from a performance
perspective, while leaving one additional ready/busy for one or more ASICs or lower
performance tier of flash devices.
RB1 RB1
RB0
RB2
RB3
RB4 RB0
RB5
RB6
Figure 25-4. Internal connectivity of RB signal for 28-bit address mode
For the 22-/25-bit address mode:RB[0:2]_B is directly routed to the ready/busy inputs of
the IFC block which correspond to chip selects 0-2. The fourth ready/busy signal RB3_B
is routed to the ready/busy inputs of the IFC block which correspond to chip selects 3-6 .
Note that If IFC_CS_B[5] is used, then IFC_RB_B[3] cannot be used and vice-versa.
This configuration allows for four banks of flash to be fully optimized from a
performance perspective, while leaving one additional ready/busy for one or more ASICs
or lower performance tier of flash devices.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1311
IFC memory map/register definition
RB0 RB0
RB1 RB1
RB2 RB2
RB3
RB4
RB5 RB3
RB6
Figure 25-5. Internal connectivity of RB signal for 22/25-bit address mode
25.3 IFC memory map/register definition
The IFC is allocated 8 KB of memory-mapped space. The memory map is divided into
two parts (4 KB each):
• Common registers shared by NAND, NOR, and GPCM FCM
• Specific registers defined for the NAND FCM, NOR FCM (IFC global), and GPCM
FCM (IFC run time) exclusively
IFC memory map
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
153_0000 IFC Revision Control register (IFC_REV) 32 R See section 25.3.1/1322
153_000C Extended Chip Select Property registers (IFC_CSPR0_EXT) 32 R/W 0000_0000h 25.3.2/1323
153_0010 Chip-select Property register n (IFC_CSPR0) 32 R/W 0000_0000h 25.3.3/1323
153_0018 Extended Chip Select Property registers (IFC_CSPR1_EXT) 32 R/W 0000_0000h 25.3.2/1323
153_001C Chip-select Property register n (IFC_CSPR1) 32 R/W 0000_0000h 25.3.3/1323
153_0024 Extended Chip Select Property registers (IFC_CSPR2_EXT) 32 R/W 0000_0000h 25.3.2/1323
153_0028 Chip-select Property register n (IFC_CSPR2) 32 R/W 0000_0000h 25.3.3/1323
153_0030 Extended Chip Select Property registers (IFC_CSPR3_EXT) 32 R/W 0000_0000h 25.3.2/1323
153_0034 Chip-select Property register n (IFC_CSPR3) 32 R/W 0000_0000h 25.3.3/1323
153_003C Extended Chip Select Property registers (IFC_CSPR4_EXT) 32 R/W 0000_0000h 25.3.2/1323
153_0040 Chip-select Property register n (IFC_CSPR4) 32 R/W 0000_0000h 25.3.3/1323
153_0048 Extended Chip Select Property registers (IFC_CSPR5_EXT) 32 R/W 0000_0000h 25.3.2/1323
153_004C Chip-select Property register n (IFC_CSPR5) 32 R/W 0000_0000h 25.3.3/1323
153_0054 Extended Chip Select Property registers (IFC_CSPR6_EXT) 32 R/W 0000_0000h 25.3.2/1323
153_0058 Chip-select Property register n (IFC_CSPR6) 32 R/W 0000_0000h 25.3.3/1323
153_00A0 Address Mask register (IFC_AMAS0K) 32 R/W 0000_0000h 25.3.4/1325
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1312 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
IFC memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
153_00AC Address Mask register (IFC_AMAS1K) 32 R/W 0000_0000h 25.3.4/1325
153_00B8 Address Mask register (IFC_AMAS2K) 32 R/W 0000_0000h 25.3.4/1325
153_00C4 Address Mask register (IFC_AMAS3K) 32 R/W 0000_0000h 25.3.4/1325
153_00D0 Address Mask register (IFC_AMAS4K) 32 R/W 0000_0000h 25.3.4/1325
153_00DC Address Mask register (IFC_AMAS5K) 32 R/W 0000_0000h 25.3.4/1325
153_00E8 Address Mask register (IFC_AMAS6K) 32 R/W 0000_0000h 25.3.4/1325
Chip-Select Option register - NAND Flash Mode
153_0130 32 R/W See section 25.3.5/1327
(IFC_CSOR0_NAND)
Chip-Select Option register - NOR Flash Mode
153_0130 32 R/W See section 25.3.6/1330
(IFC_CSOR0_NOR)
153_0130 Chip-Select Option register - GPCM (IFC_CSOR0_GPCM) 32 R/W See section 25.3.7/1332
Extended Chip-Select Option register - NAND Flash Mode
153_0134 32 R/W 0010_0000h 25.3.8/1336
(IFC_CSOR0_EXT)
Chip-Select Option register - NAND Flash Mode
153_013C 32 R/W See section 25.3.5/1327
(IFC_CSOR1_NAND)
Chip-Select Option register - NOR Flash Mode
153_013C 32 R/W See section 25.3.6/1330
(IFC_CSOR1_NOR)
153_013C Chip-Select Option register - GPCM (IFC_CSOR1_GPCM) 32 R/W See section 25.3.7/1332
Extended Chip-Select Option register - NAND Flash Mode
153_0140 32 R/W 0010_0000h 25.3.8/1336
(IFC_CSOR1_EXT)
Chip-Select Option register - NAND Flash Mode
153_0148 32 R/W See section 25.3.5/1327
(IFC_CSOR2_NAND)
Chip-Select Option register - NOR Flash Mode
153_0148 32 R/W See section 25.3.6/1330
(IFC_CSOR2_NOR)
153_0148 Chip-Select Option register - GPCM (IFC_CSOR2_GPCM) 32 R/W See section 25.3.7/1332
Extended Chip-Select Option register - NAND Flash Mode
153_014C 32 R/W 0010_0000h 25.3.8/1336
(IFC_CSOR2_EXT)
Chip-Select Option register - NAND Flash Mode
153_0154 32 R/W See section 25.3.5/1327
(IFC_CSOR3_NAND)
Chip-Select Option register - NOR Flash Mode
153_0154 32 R/W See section 25.3.6/1330
(IFC_CSOR3_NOR)
153_0154 Chip-Select Option register - GPCM (IFC_CSOR3_GPCM) 32 R/W See section 25.3.7/1332
Extended Chip-Select Option register - NAND Flash Mode
153_0158 32 R/W 0010_0000h 25.3.8/1336
(IFC_CSOR3_EXT)
Chip-Select Option register - NAND Flash Mode
153_0160 32 R/W See section 25.3.5/1327
(IFC_CSOR4_NAND)
Chip-Select Option register - NOR Flash Mode
153_0160 32 R/W See section 25.3.6/1330
(IFC_CSOR4_NOR)
153_0160 Chip-Select Option register - GPCM (IFC_CSOR4_GPCM) 32 R/W See section 25.3.7/1332
Extended Chip-Select Option register - NAND Flash Mode
153_0164 32 R/W 0010_0000h 25.3.8/1336
(IFC_CSOR4_EXT)
Chip-Select Option register - NAND Flash Mode
153_016C 32 R/W See section 25.3.5/1327
(IFC_CSOR5_NAND)
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1313
IFC memory map/register definition
IFC memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Chip-Select Option register - NOR Flash Mode
153_016C 32 R/W See section 25.3.6/1330
(IFC_CSOR5_NOR)
153_016C Chip-Select Option register - GPCM (IFC_CSOR5_GPCM) 32 R/W See section 25.3.7/1332
Extended Chip-Select Option register - NAND Flash Mode
153_0170 32 R/W 0010_0000h 25.3.8/1336
(IFC_CSOR5_EXT)
Chip-Select Option register - NAND Flash Mode
153_0178 32 R/W See section 25.3.5/1327
(IFC_CSOR6_NAND)
Chip-Select Option register - NOR Flash Mode
153_0178 32 R/W See section 25.3.6/1330
(IFC_CSOR6_NOR)
153_0178 Chip-Select Option register - GPCM (IFC_CSOR6_GPCM) 32 R/W See section 25.3.7/1332
Extended Chip-Select Option register - NAND Flash Mode
153_017C 32 R/W 0010_0000h 25.3.8/1336
(IFC_CSOR6_EXT)
Flash Timing register 0 for Chip Select n - NAND flash
153_01C0 32 R/W 0000_0000h 25.3.9/1338
asyncNVDDR mode (IFC_FTIM0_CS0_NAND)
Flash Timing register 0 for Chip Select n - NAND flash
25.3.10/
153_01C0 Asynchronous Mode 32 R/W 0000_0000h
1340
(IFC_FTIM0_CS_NAND_ASYNC_MODE)
Flash Timing register 0 for CSn - NOR Flash Mode 25.3.11/
153_01C0 32 R/W 0000_0000h
(IFC_FTIM0_CS0_NOR) 1341
Flash Timing register 0 for CSn - Normal GPCM Mode 25.3.12/
153_01C0 32 R/W 0000_0000h
(IFC_FTIM0_CS0_GPCM) 1343
Flash Timing register 1 for Chip-Select n - NAND Flash 25.3.13/
153_01C4 32 R/W 0000_0000h
NVDDR Mode (IFC_FTIM1_CS0_NAND) 1344
Flash Timing register 1 for Chip Select n - Asynchronous 25.3.14/
153_01C4 32 R/W 0000_0000h
Mode (IFC_FTIM1_CS0_NAND_ASYNC_MODE) 1345
Flash Timing register 1 for CSn - NOR Flash Mode 25.3.15/
153_01C4 32 R/W 0000_0000h
(IFC_FTIM1_CS0_NOR) 1346
Flash Timing register 1 for CSn - Normal GPCM Mode 25.3.16/
153_01C4 32 R/W 0000_0000h
(IFC_FTIM1_CS0_GPCM) 1347
Flash Timing register 2 for Chip Select n - NAND Flash 25.3.17/
153_01C8 32 R/W 0000_0000h
NVDDR Mode (IFC_FTIM2_CS0_NAND) 1348
Flash Timing register 2 for Chip Select n - NAND Flash
25.3.18/
153_01C8 Asynchronous Mode 32 R/W 0000_0000h
1348
(IFC_FTIM2_CS0_NAND_ASYNC_MODE)
Flash Timing register 2 for CSn - NOR Flash Mode 25.3.19/
153_01C8 32 R/W 0000_0000h
(IFC_FTIM2_CS0_NOR) 1349
Flash Timing register 2 for CSn - Normal GPCM Mode 25.3.20/
153_01C8 32 R/W 0000_0000h
(IFC_FTIM2_CS0_GPCM) 1351
Flash Timing register 3 for Chip Select n - NAND Flash 25.3.21/
153_01CC 32 R/W 0000_0000h
Mode (IFC_FTIM3_CS0_NAND) 1352
Flash Timing register 3 for Chip Select n - NAND Flash
25.3.22/
153_01CC Asynchronous Mode 32 R/W 0000_0000h
1352
(IFC_IFC_FTIM03_CS_NAND_ASYNC_MODE)
Flash Timing register 3 for CSn - NOR Flash Mode 25.3.23/
153_01CC 32 R/W 0000_0000h
(IFC_FTIM3_CS_NOR) 1353
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1314 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
IFC memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Flash Timing register 3 for CSn - Normal GPCM Mode 25.3.24/
153_01CC 32 R/W 0000_0000h
(IFC_FTIM3_CS0_GPCM) 1353
Flash Timing register 0 for Chip Select n - NAND flash
153_01F0 32 R/W 0000_0000h 25.3.9/1338
asyncNVDDR mode (IFC_FTIM0_CS1_NAND)
Flash Timing register 0 for CSn - NOR Flash Mode 25.3.11/
153_01F0 32 R/W 0000_0000h
(IFC_FTIM0_CS1_NOR) 1341
Flash Timing register 0 for CSn - Normal GPCM Mode 25.3.12/
153_01F0 32 R/W 0000_0000h
(IFC_FTIM0_CS1_GPCM) 1343
Flash Timing register 1 for Chip-Select n - NAND Flash 25.3.13/
153_01F4 32 R/W 0000_0000h
NVDDR Mode (IFC_FTIM1_CS1_NAND) 1344
Flash Timing register 1 for Chip Select n - Asynchronous 25.3.14/
153_01F4 32 R/W 0000_0000h
Mode (IFC_FTIM1_CS1_NAND_ASYNC_MODE) 1345
Flash Timing register 1 for CSn - NOR Flash Mode 25.3.15/
153_01F4 32 R/W 0000_0000h
(IFC_FTIM1_CS1_NOR) 1346
Flash Timing register 1 for CSn - Normal GPCM Mode 25.3.16/
153_01F4 32 R/W 0000_0000h
(IFC_FTIM1_CS1_GPCM) 1347
Flash Timing register 2 for Chip Select n - NAND Flash 25.3.17/
153_01F8 32 R/W 0000_0000h
NVDDR Mode (IFC_FTIM2_CS1_NAND) 1348
Flash Timing register 2 for Chip Select n - NAND Flash
25.3.18/
153_01F8 Asynchronous Mode 32 R/W 0000_0000h
1348
(IFC_FTIM2_CS1_NAND_ASYNC_MODE)
Flash Timing register 2 for CSn - NOR Flash Mode 25.3.19/
153_01F8 32 R/W 0000_0000h
(IFC_FTIM2_CS1_NOR) 1349
Flash Timing register 2 for CSn - Normal GPCM Mode 25.3.20/
153_01F8 32 R/W 0000_0000h
(IFC_FTIM2_CS1_GPCM) 1351
Flash Timing register 3 for Chip Select n - NAND Flash 25.3.21/
153_01FC 32 R/W 0000_0000h
Mode (IFC_FTIM3_CS1_NAND) 1352
Flash Timing register 3 for Chip Select n - NAND Flash
25.3.22/
153_01FC Asynchronous Mode 32 R/W 0000_0000h
1352
(IFC_IFC_FTIM13_CS_NAND_ASYNC_MODE)
Flash Timing register 3 for CSn - Normal GPCM Mode 25.3.24/
153_01FC 32 R/W 0000_0000h
(IFC_FTIM3_CS1_GPCM) 1353
Flash Timing register 0 for Chip Select n - NAND flash
153_0220 32 R/W 0000_0000h 25.3.9/1338
asyncNVDDR mode (IFC_FTIM0_CS2_NAND)
Flash Timing register 0 for CSn - NOR Flash Mode 25.3.11/
153_0220 32 R/W 0000_0000h
(IFC_FTIM0_CS2_NOR) 1341
Flash Timing register 0 for CSn - Normal GPCM Mode 25.3.12/
153_0220 32 R/W 0000_0000h
(IFC_FTIM0_CS2_GPCM) 1343
Flash Timing register 1 for Chip-Select n - NAND Flash 25.3.13/
153_0224 32 R/W 0000_0000h
NVDDR Mode (IFC_FTIM1_CS2_NAND) 1344
Flash Timing register 1 for Chip Select n - Asynchronous 25.3.14/
153_0224 32 R/W 0000_0000h
Mode (IFC_FTIM1_CS2_NAND_ASYNC_MODE) 1345
Flash Timing register 1 for CSn - NOR Flash Mode 25.3.15/
153_0224 32 R/W 0000_0000h
(IFC_FTIM1_CS2_NOR) 1346
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1315
IFC memory map/register definition
IFC memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Flash Timing register 1 for CSn - Normal GPCM Mode 25.3.16/
153_0224 32 R/W 0000_0000h
(IFC_FTIM1_CS2_GPCM) 1347
Flash Timing register 2 for Chip Select n - NAND Flash 25.3.17/
153_0228 32 R/W 0000_0000h
NVDDR Mode (IFC_FTIM2_CS2_NAND) 1348
Flash Timing register 2 for Chip Select n - NAND Flash
25.3.18/
153_0228 Asynchronous Mode 32 R/W 0000_0000h
1348
(IFC_FTIM2_CS2_NAND_ASYNC_MODE)
Flash Timing register 2 for CSn - NOR Flash Mode 25.3.19/
153_0228 32 R/W 0000_0000h
(IFC_FTIM2_CS2_NOR) 1349
Flash Timing register 2 for CSn - Normal GPCM Mode 25.3.20/
153_0228 32 R/W 0000_0000h
(IFC_FTIM2_CS2_GPCM) 1351
Flash Timing register 3 for Chip Select n - NAND Flash 25.3.21/
153_022C 32 R/W 0000_0000h
Mode (IFC_FTIM3_CS2_NAND) 1352
Flash Timing register 3 for Chip Select n - NAND Flash
25.3.22/
153_022C Asynchronous Mode 32 R/W 0000_0000h
1352
(IFC_IFC_FTIM23_CS_NAND_ASYNC_MODE)
Flash Timing register 3 for CSn - Normal GPCM Mode 25.3.24/
153_022C 32 R/W 0000_0000h
(IFC_FTIM3_CS2_GPCM) 1353
Flash Timing register 0 for Chip Select n - NAND flash
153_0250 32 R/W 0000_0000h 25.3.9/1338
asyncNVDDR mode (IFC_FTIM0_CS3_NAND)
Flash Timing register 0 for CSn - NOR Flash Mode 25.3.11/
153_0250 32 R/W 0000_0000h
(IFC_FTIM0_CS3_NOR) 1341
Flash Timing register 0 for CSn - Normal GPCM Mode 25.3.12/
153_0250 32 R/W 0000_0000h
(IFC_FTIM0_CS3_GPCM) 1343
Flash Timing register 1 for Chip-Select n - NAND Flash 25.3.13/
153_0254 32 R/W 0000_0000h
NVDDR Mode (IFC_FTIM1_CS3_NAND) 1344
Flash Timing register 1 for Chip Select n - Asynchronous 25.3.14/
153_0254 32 R/W 0000_0000h
Mode (IFC_FTIM1_CS3_NAND_ASYNC_MODE) 1345
Flash Timing register 1 for CSn - NOR Flash Mode 25.3.15/
153_0254 32 R/W 0000_0000h
(IFC_FTIM1_CS3_NOR) 1346
Flash Timing register 1 for CSn - Normal GPCM Mode 25.3.16/
153_0254 32 R/W 0000_0000h
(IFC_FTIM1_CS3_GPCM) 1347
Flash Timing register 2 for Chip Select n - NAND Flash 25.3.17/
153_0258 32 R/W 0000_0000h
NVDDR Mode (IFC_FTIM2_CS3_NAND) 1348
Flash Timing register 2 for Chip Select n - NAND Flash
25.3.18/
153_0258 Asynchronous Mode 32 R/W 0000_0000h
1348
(IFC_FTIM2_CS3_NAND_ASYNC_MODE)
Flash Timing register 2 for CSn - NOR Flash Mode 25.3.19/
153_0258 32 R/W 0000_0000h
(IFC_FTIM2_CS3_NOR) 1349
Flash Timing register 2 for CSn - Normal GPCM Mode 25.3.20/
153_0258 32 R/W 0000_0000h
(IFC_FTIM2_CS3_GPCM) 1351
Flash Timing register 3 for Chip Select n - NAND Flash 25.3.21/
153_025C 32 R/W 0000_0000h
Mode (IFC_FTIM3_CS3_NAND) 1352
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1316 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
IFC memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Flash Timing register 3 for Chip Select n - NAND Flash
25.3.22/
153_025C Asynchronous Mode 32 R/W 0000_0000h
1352
(IFC_IFC_FTIM33_CS_NAND_ASYNC_MODE)
Flash Timing register 3 for CSn - Normal GPCM Mode 25.3.24/
153_025C 32 R/W 0000_0000h
(IFC_FTIM3_CS3_GPCM) 1353
Flash Timing register 0 for Chip Select n - NAND flash
153_0280 32 R/W 0000_0000h 25.3.9/1338
asyncNVDDR mode (IFC_FTIM0_CS4_NAND)
Flash Timing register 0 for CSn - NOR Flash Mode 25.3.11/
153_0280 32 R/W 0000_0000h
(IFC_FTIM0_CS4_NOR) 1341
Flash Timing register 0 for CSn - Normal GPCM Mode 25.3.12/
153_0280 32 R/W 0000_0000h
(IFC_FTIM0_CS4_GPCM) 1343
Flash Timing register 1 for Chip-Select n - NAND Flash 25.3.13/
153_0284 32 R/W 0000_0000h
NVDDR Mode (IFC_FTIM1_CS4_NAND) 1344
Flash Timing register 1 for Chip Select n - Asynchronous 25.3.14/
153_0284 32 R/W 0000_0000h
Mode (IFC_FTIM1_CS4_NAND_ASYNC_MODE) 1345
Flash Timing register 1 for CSn - NOR Flash Mode 25.3.15/
153_0284 32 R/W 0000_0000h
(IFC_FTIM1_CS4_NOR) 1346
Flash Timing register 1 for CSn - Normal GPCM Mode 25.3.16/
153_0284 32 R/W 0000_0000h
(IFC_FTIM1_CS4_GPCM) 1347
Flash Timing register 2 for Chip Select n - NAND Flash 25.3.17/
153_0288 32 R/W 0000_0000h
NVDDR Mode (IFC_FTIM2_CS4_NAND) 1348
Flash Timing register 2 for Chip Select n - NAND Flash
25.3.18/
153_0288 Asynchronous Mode 32 R/W 0000_0000h
1348
(IFC_FTIM2_CS4_NAND_ASYNC_MODE)
Flash Timing register 2 for CSn - NOR Flash Mode 25.3.19/
153_0288 32 R/W 0000_0000h
(IFC_FTIM2_CS4_NOR) 1349
Flash Timing register 2 for CSn - Normal GPCM Mode 25.3.20/
153_0288 32 R/W 0000_0000h
(IFC_FTIM2_CS4_GPCM) 1351
Flash Timing register 3 for Chip Select n - NAND Flash 25.3.21/
153_028C 32 R/W 0000_0000h
Mode (IFC_FTIM3_CS4_NAND) 1352
Flash Timing register 3 for Chip Select n - NAND Flash
25.3.22/
153_028C Asynchronous Mode 32 R/W 0000_0000h
1352
(IFC_IFC_FTIM43_CS_NAND_ASYNC_MODE)
Flash Timing register 3 for CSn - Normal GPCM Mode 25.3.24/
153_028C 32 R/W 0000_0000h
(IFC_FTIM3_CS4_GPCM) 1353
Flash Timing register 0 for Chip Select n - NAND flash
153_02B0 32 R/W 0000_0000h 25.3.9/1338
asyncNVDDR mode (IFC_FTIM0_CS5_NAND)
Flash Timing register 0 for CSn - NOR Flash Mode 25.3.11/
153_02B0 32 R/W 0000_0000h
(IFC_FTIM0_CS5_NOR) 1341
Flash Timing register 0 for CSn - Normal GPCM Mode 25.3.12/
153_02B0 32 R/W 0000_0000h
(IFC_FTIM0_CS5_GPCM) 1343
Flash Timing register 1 for Chip-Select n - NAND Flash 25.3.13/
153_02B4 32 R/W 0000_0000h
NVDDR Mode (IFC_FTIM1_CS5_NAND) 1344
Flash Timing register 1 for Chip Select n - Asynchronous 25.3.14/
153_02B4 32 R/W 0000_0000h
Mode (IFC_FTIM1_CS5_NAND_ASYNC_MODE) 1345
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1317
IFC memory map/register definition
IFC memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Flash Timing register 1 for CSn - NOR Flash Mode 25.3.15/
153_02B4 32 R/W 0000_0000h
(IFC_FTIM1_CS5_NOR) 1346
Flash Timing register 1 for CSn - Normal GPCM Mode 25.3.16/
153_02B4 32 R/W 0000_0000h
(IFC_FTIM1_CS5_GPCM) 1347
Flash Timing register 2 for Chip Select n - NAND Flash 25.3.17/
153_02B8 32 R/W 0000_0000h
NVDDR Mode (IFC_FTIM2_CS5_NAND) 1348
Flash Timing register 2 for Chip Select n - NAND Flash
25.3.18/
153_02B8 Asynchronous Mode 32 R/W 0000_0000h
1348
(IFC_FTIM2_CS5_NAND_ASYNC_MODE)
Flash Timing register 2 for CSn - NOR Flash Mode 25.3.19/
153_02B8 32 R/W 0000_0000h
(IFC_FTIM2_CS5_NOR) 1349
Flash Timing register 2 for CSn - Normal GPCM Mode 25.3.20/
153_02B8 32 R/W 0000_0000h
(IFC_FTIM2_CS5_GPCM) 1351
Flash Timing register 3 for Chip Select n - NAND Flash 25.3.21/
153_02BC 32 R/W 0000_0000h
Mode (IFC_FTIM3_CS5_NAND) 1352
Flash Timing register 3 for Chip Select n - NAND Flash
25.3.22/
153_02BC Asynchronous Mode 32 R/W 0000_0000h
1352
(IFC_IFC_FTIM53_CS_NAND_ASYNC_MODE)
Flash Timing register 3 for CSn - Normal GPCM Mode 25.3.24/
153_02BC 32 R/W 0000_0000h
(IFC_FTIM3_CS5_GPCM) 1353
Flash Timing register 0 for Chip Select n - NAND flash
153_02E0 32 R/W 0000_0000h 25.3.9/1338
asyncNVDDR mode (IFC_FTIM0_CS6_NAND)
Flash Timing register 0 for CSn - NOR Flash Mode 25.3.11/
153_02E0 32 R/W 0000_0000h
(IFC_FTIM0_CS6_NOR) 1341
Flash Timing register 0 for CSn - Normal GPCM Mode 25.3.12/
153_02E0 32 R/W 0000_0000h
(IFC_FTIM0_CS6_GPCM) 1343
Flash Timing register 1 for Chip-Select n - NAND Flash 25.3.13/
153_02E4 32 R/W 0000_0000h
NVDDR Mode (IFC_FTIM1_CS6_NAND) 1344
Flash Timing register 1 for Chip Select n - Asynchronous 25.3.14/
153_02E4 32 R/W 0000_0000h
Mode (IFC_FTIM1_CS6_NAND_ASYNC_MODE) 1345
Flash Timing register 1 for CSn - NOR Flash Mode 25.3.15/
153_02E4 32 R/W 0000_0000h
(IFC_FTIM1_CS6_NOR) 1346
Flash Timing register 1 for CSn - Normal GPCM Mode 25.3.16/
153_02E4 32 R/W 0000_0000h
(IFC_FTIM1_CS6_GPCM) 1347
Flash Timing register 2 for Chip Select n - NAND Flash 25.3.17/
153_02E8 32 R/W 0000_0000h
NVDDR Mode (IFC_FTIM2_CS6_NAND) 1348
Flash Timing register 2 for Chip Select n - NAND Flash
25.3.18/
153_02E8 Asynchronous Mode 32 R/W 0000_0000h
1348
(IFC_FTIM2_CS6_NAND_ASYNC_MODE)
Flash Timing register 2 for CSn - NOR Flash Mode 25.3.19/
153_02E8 32 R/W 0000_0000h
(IFC_FTIM2_CS6_NOR) 1349
Flash Timing register 2 for CSn - Normal GPCM Mode 25.3.20/
153_02E8 32 R/W 0000_0000h
(IFC_FTIM2_CS6_GPCM) 1351
Flash Timing register 3 for Chip Select n - NAND Flash 25.3.21/
153_02EC 32 R/W 0000_0000h
Mode (IFC_FTIM3_CS6_NAND) 1352
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1318 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
IFC memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Flash Timing register 3 for Chip Select n - NAND Flash
25.3.22/
153_02EC Asynchronous Mode 32 R/W 0000_0000h
1352
(IFC_IFC_FTIM63_CS_NAND_ASYNC_MODE)
Flash Timing register 3 for CSn - Normal GPCM Mode 25.3.24/
153_02EC 32 R/W 0000_0000h
(IFC_FTIM3_CS6_GPCM) 1353
25.3.25/
153_0400 Ready Busy Status for each Chip Select (IFC_RB_STAT) 32 R See section
1354
25.3.26/
153_040C General Control register (IFC_GCR) 32 R/W 0000_0000h
1356
Common Event and Error Status register 25.3.27/
153_0418 32 w1c 0000_0000h
(IFC_CM_EVTER_STAT) 1357
Common Event and Error Enable register 25.3.28/
153_0424 32 R/W 8000_0000h
(IFC_CM_EVTER_EN) 1358
Common Event and Error Interrupt Enable register 25.3.29/
153_0430 32 R/W 0000_0000h
(IFC_CM_EVTER_INTR_EN) 1359
Common Transfer Error Attributes register 0 25.3.30/
153_043C 32 R 0000_0000h
(IFC_CM_ERATTR0) 1359
Common Transfer Error Attributes register 1 25.3.31/
153_0440 32 R 0000_0000h
(IFC_CM_ERATTR1) 1361
25.3.32/
153_044C Clock Control register (IFC_CCR) 32 R/W 0300_8000h
1361
25.3.33/
153_0450 Clock Status register (IFC_CSR) 32 R See section
1363
25.3.34/
153_0454 DDR Clock Control register (IFC_DDR_CCR) 32 R/W 0080_0000h
1364
25.3.35/
153_1000 NAND Configuration register (IFC_NCFGR) 32 R/W 0000_0000h
1366
25.3.36/
153_1014 NAND Flash Command register 0 (IFC_NAND_FCR0) 32 R/W 0000_0000h
1368
25.3.37/
153_1018 NAND Flash Command register 1 (IFC_NAND_FCR1) 32 R/W 0000_0000h
1369
25.3.38/
153_103C Flash Row Address register n (IFC_ROW0) 32 R/W 0000_0000h
1369
25.3.39/
153_1044 Flash COL Address register n (IFC_COL0) 32 R/W 0000_0000h
1370
Flash COL Address register for 2 KB Large-Page Device 25.3.40/
153_1044 32 R/W 0000_0000h
(IFC_COL0_2KB) 1371
Flash COL Address register for 4 KB Large-Page Device 25.3.41/
153_1044 32 R/W 0000_0000h
(IFC_COL0_4KB) 1372
Flash COL Address register for 8 KB Large-Page Device 25.3.42/
153_1044 32 R/W 0000_0000h
(IFC_COL0_8KB) 1373
25.3.38/
153_104C Flash Row Address register n (IFC_ROW1) 32 R/W 0000_0000h
1369
25.3.39/
153_1054 Flash COL Address register n (IFC_COL1) 32 R/W 0000_0000h
1370
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1319
IFC memory map/register definition
IFC memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Flash COL Address register for 2 KB Large-Page Device 25.3.40/
153_1054 32 R/W 0000_0000h
(IFC_COL1_2KB) 1371
Flash COL Address register for 4 KB Large-Page Device 25.3.41/
153_1054 32 R/W 0000_0000h
(IFC_COL1_4KB) 1372
Flash COL Address register for 8 KB Large-Page Device 25.3.42/
153_1054 32 R/W 0000_0000h
(IFC_COL1_8KB) 1373
25.3.38/
153_105C Flash Row Address register n (IFC_ROW2) 32 R/W 0000_0000h
1369
25.3.39/
153_1064 Flash COL Address register n (IFC_COL2) 32 R/W 0000_0000h
1370
Flash COL Address register for 2 KB Large-Page Device 25.3.40/
153_1064 32 R/W 0000_0000h
(IFC_COL2_2KB) 1371
Flash COL Address register for 4 KB Large-Page Device 25.3.41/
153_1064 32 R/W 0000_0000h
(IFC_COL2_4KB) 1372
Flash COL Address register for 8 KB Large-Page Device 25.3.42/
153_1064 32 R/W 0000_0000h
(IFC_COL2_8KB) 1373
25.3.38/
153_106C Flash Row Address register n (IFC_ROW3) 32 R/W 0000_0000h
1369
25.3.39/
153_1074 Flash COL Address register n (IFC_COL3) 32 R/W 0000_0000h
1370
Flash COL Address register for 2 KB Large-Page Device 25.3.40/
153_1074 32 R/W 0000_0000h
(IFC_COL3_2KB) 1371
Flash COL Address register for 4 KB Large-Page Device 25.3.41/
153_1074 32 R/W 0000_0000h
(IFC_COL3_4KB) 1372
Flash COL Address register for 8 KB Large-Page Device 25.3.42/
153_1074 32 R/W 0000_0000h
(IFC_COL3_8KB) 1373
25.3.43/
153_1108 Flash Byte Count register for NAND Flash (IFC_NAND_BC) 32 R/W 0000_0000h
1374
25.3.44/
153_1110 NAND Flash Instruction register 0 (IFC_NAND_FIR0) 32 R/W 0000_0000h
1375
25.3.45/
153_1114 NAND Flash Instruction register 1 (IFC_NAND_FIR1) 32 R/W 0000_0000h
1377
25.3.46/
153_1118 NAND Flash Instruction register 2 (IFC_NAND_FIR2) 32 R/W 0000_0000h
1378
25.3.47/
153_115C NAND Chip-Select register (IFC_NAND_CSEL) 32 R/W 0000_0000h
1379
25.3.48/
153_1164 NAND Operation Sequence Start (IFC_NANDSEQ_STRT) 32 R/W 0000_0000h
1379
NAND Event and Error Status register 25.3.49/
153_116C 32 w1c 0000_0000h
(IFC_NAND_EVTER_STAT) 1381
NAND Page Read Completion Event Status register 25.3.50/
153_1174 32 w1c 0000_0000h
(IFC_PGRDCMPL_EVT_STAT) 1383
NAND Event and Error Enable register 25.3.51/
153_1180 32 R/W AE00_0000h
(IFC_NAND_EVTER_EN) 1385
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1320 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
IFC memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
NAND Event and Error Interrupt Enable register 25.3.52/
153_118C 32 R/W 0000_0000h
(IFC_NAND_EVTER_INTR_EN) 1387
NAND Transfer Error Attributes register 0 25.3.53/
153_1198 32 R 0000_0000h
(IFC_NAND_ERATTR0) 1388
NAND Transfer Error Attributes register 1 25.3.54/
153_119C 32 R 0000_0000h
(IFC_NAND_ERATTR1) 1389
25.3.55/
153_11E0 NAND Flash Status register (IFC_NAND_FSR) 32 R 0000_0000h
1390
ECC Status and Result of Flash Operation register 0 25.3.56/
153_11E8 32 R 0000_0000h
(IFC_ECCSTAT0) 1390
ECC Status and Result of Flash Operation register 1 25.3.57/
153_11EC 32 R 0000_0000h
(IFC_ECCSTAT1) 1392
ECC Status and Result of Flash Operation register 2 25.3.58/
153_11F0 32 R 0000_0000h
(IFC_ECCSTAT2) 1393
ECC Status and Result of Flash Operation register 3 25.3.59/
153_11F4 32 R 0000_0000h
(IFC_ECCSTAT3) 1394
25.3.60/
153_1278 NAND Control register (IFC_NANDCR) 32 R/W 1E00_0000h
1395
NAND Autoboot Trigger register 25.3.61/
153_1284 32 W 0000_0000h
(IFC_NAND_AUTOBOOT_TRGR) 1395
25.3.62/
153_128C NAND Flash Memory Data register (IFC_NAND_MDR) 32 R 0000_0000h
1397
Nand DLL Low Config 0 Register 25.3.63/
153_1300 32 R/W 8007_0000h
(IFC_NAND_DLL_LOW_CFG0) 1398
Nand DLL Low Config 1 Register 25.3.64/
153_1304 32 R/W 8000_0000h
(IFC_NAND_DLL_LOW_CFG1) 1399
NAND DLL Low Status Register 25.3.65/
153_130C 32 R 0000_0000h
(IFC_NAND_DLL_LOW_STAT) 1401
NOR Event and Error Status register 25.3.66/
153_1400 32 w1c 0000_0000h
(IFC_NOR_EVTER_STAT) 1402
NOR Event and Error Enable register 25.3.67/
153_140C 32 R/W 8500_0000h
(IFC_NOR_EVTER_EN) 1404
NOR Event and Error Interrupt enable register 25.3.68/
153_1418 32 R/W 0000_0000h
(IFC_NOR_EVTER_INTR_EN) 1406
NOR Transfer Error Attributes register 0 25.3.69/
153_1424 32 R 0000_0000h
(IFC_NOR_ERATTR0) 1407
NOR Transfer Error Attribute register 1 25.3.70/
153_1428 32 R 0000_0000h
(IFC_NOR_ERATTR1) 1408
NOR Transfer Error Attribute register 2 25.3.71/
153_142C 32 R 0000_0000h
(IFC_NOR_ERATTR2) 1409
25.3.72/
153_1440 NOR Control register (IFC_NORCR) 32 R/W 000F_0000h
1409
GPCM Event and Error Status register 25.3.73/
153_1800 32 w1c 0000_0000h
(IFC_GPCM_EVTER_STAT) 1411
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1321
IFC memory map/register definition
IFC memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
GPCM Event and Error Enable register 25.3.74/
153_180C 32 R/W 0540_0000h
(IFC_GPCM_EVTER_EN) 1413
GPCM Event and Error Interrupt enable register 25.3.75/
153_1818 32 R/W 0000_0000h
(IFC_GPCM_EVTER_INTR_EN) 1414
GPCM Transfer Error Attributes register 0 25.3.76/
153_1824 32 R 0000_0000h
(IFC_GPCM_ERATTR0) 1416
GPCM Transfer Error Attributes register 1 25.3.77/
153_1828 32 R 0000_0000h
(IFC_GPCM_ERATTR1) 1417
GPCM Transfer Error Attributes register 2 25.3.78/
153_182C 32 R 0000_0000h
(IFC_GPCM_ERATTR2) 1418
25.3.79/
153_1830 GPCM Status register (IFC_GPCM_STAT) 32 R 0000_0000h
1420
25.3.1 IFC Revision Control register (IFC_REV)
This register represents the revision number of the IFC.
Address: 153_0000h base + 0h offset = 153_0000h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R REV_MAJ REV_MIN
Reserved Reserved Reserved
W
Reset 0 0 0 0 0 0 n n 0 0 0 0 n n n n 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_REV field descriptions
Field Description
0–3 This field is reserved.
-
4–7 Major Revision. It represents the major revision of IFC
REV_MAJ
8–11 This field is reserved.
-
12–15 Minor Revision. It represents the minor revision of IFC.
REV_MIN
16–31 This field is reserved.
-
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1322 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
25.3.2 Extended Chip Select Property registers (IFC_CSPRn_EXT)
The extended chip select property register (CSPRn_EXT) contains the extended base
address, that is, the most significant bits (msb) of the base address.
Address: 153_0000h base + Ch offset + (12d × i), where i=0d to 6d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
Reserved BA_EXT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_CSPRn_EXT field descriptions
Field Description
0–23 This field is reserved.
-
24–31 Extended Base Address: This field contains the msbs of the base address. Complete base address can be
BA_EXT represented by concatenating CSPRn_EXT[BA_EXT] and CSPRn[BA] fields. Each chip selects's base
register value is compared to the address on the address bus to determine if the master is accessing a
memory bank controlled by the IFC. Address decoding is performed by using the address mask bit in
AMASKn[AM] field more details of decoding is given in AMASK register description.
25.3.3 Chip-select Property register n (IFC_CSPRn)
The chip-select property register (CSPRn) contains the base address and memory
attributes for each bank.
NOTE
CSPR0: Only chip-select 0 is used for booting. PS, MSEL[1],
and TE is obtained from the configuration word when
boot_load/rcw_load occurs. V will be set for CSPR0 when
boot_load/rcw_load occurs with valid port size.
Address: 153_0000h base + 10h offset + (12d × i), where i=0d to 6d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
BA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1323
IFC memory map/register definition
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Reserved
Reserved
Reserved PS WP TE MSEL V
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_CSPRn field descriptions
Field Description
0–15 Base Address: Each base register value is compared to the address on the address bus to determine if
BA the master is accessing a memory bank controlled by the IFC. Used with the address mask bit.
16–22 This field is reserved.
-
23–24 Port Size-Specifies the port size of this memory region. For CSPR0, PS is configured through reset
PS configuration word as loaded during power on reset. For all other banks the value is reset to 00 (port size
not defined).
00 Reserved
01 8 bit
10 16 bit
11 Reserved
25 Write Protect:
WP
NOTE: 1. This bit is valid only for NAND and NOR; for GPCM this bit should not be set.
NOTE: 2. If CS0 is used for booting from NAND or NOR, CSPR0[WP] will be set (write protected).
Software must clear this bit after completing the boot operation to permit write operations on CS0
0 Read and write accesses are allowed.
1 Only read accesses are allowed. The memory controller does not assert chip-select on write cycles to
this memory bank for NOR flash. (Refer Write protect for more details)
26 This field is reserved.
-
27 External Transceiver Enable. It specifies the value that will be driven on TE pin when a particular CSn is
TE selected.
0 Logic 0 will be driven on TE pin
1 Logic 1 will be driven on TE pin
28 This field is reserved.
-
29–30 Machine Select
MSEL
00 NOR flash
01 NAND flash
10 GPCM
11 Reserved
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1324 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
IFC_CSPRn field descriptions (continued)
Field Description
31 Valid: Indicates that the contents of CSPRn are valid.
V
1 Bank is valid
0 Bank is invalid
25.3.4 Address Mask register (IFC_AMASnK)
The address mask (AMASKn) registers contains the 16-bit address mask field for all four
memory banks. The selected 16-bit address mask field masks corresponding CSPRn[BA]
fields. The 16 lsbs of the 32-bit internal address do not participate in bank address
matching in selecting a bank for access. Masking address bits independently allows
external devices of different size address ranges to be used. Address mask bits can be set
or cleared in any order in the field, allowing a resource to reside in more than one area of
the address map.
The IFC only has 32 address pins at the external memory interface side. Since the system
side address bus width is 40 bits, only the lower 32 bits will be given out. The upper 8
bits are used only for address decoding to identify the bank (chip select) on which access
will be performed. There is no masking of the upper 8 bits of the system side address so it
will be compared with CSPRn_EXT[BA_EXT] field as it is. Therefore, if the user
programs the same value in the CSPRn_EXT[BA_EXT] field, the entire address range of
the IFC will be 4 GB. If different values are programmed in the CSPRn_EXT[BA_EXT]
field, the address range of the IFC will then be (number of chip selects) x 4 GB, that is,
32 GB.
The following logic is used for address decoding:
24-bit base address is formed as, BASE_ADDRn[0:23] = {CSPRn_EXT[BA_EXT],
CSPRn[BA]}, n=0-6 (chip select)
Select CSn (chip select n) if,
{BASE_ADDRn[0:7], (BASE_ADDRn[8:23] & AMn[0:15])} ==
{SYSTEM_ADDR[39:32], (SYSTEM_ADDR[31:16] & AMn[0:15])}, where
• SYSTEM_ADDR is a 40-bit incoming address from the system side
• Index 39-32 represents 8 address msbs
• SYSTEM_ADDR[31:16] represent the next lower 16 address bits and the remaining
16 lsbs are not used in the bank selection
• In the logic mentioned above, the 8 msbs are not masked and are used as is for
comparison.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1325
IFC memory map/register definition
NOTE
Chip select 0 (CS0) is used for boot purposes; if the boot source
is NOR, then it must be executed in place. During booting, the
IFC registers (including BA_EXT, BA, and AMASK registers)
are modified. If there is race condition between the update of
BA_EXT, BA, and AMASK registers, a chip select error may
occur. To avoid this error and to map every transaction in CS0
during boot, the upper 8 bits of the system address and the base
address, will be masked before comparison. Masking of these
fields is turned off only after the first write transaction modifies
the AMASK0 register.
After reset, until a first write transaction occurs to update AMASK0 register, all the
transactions coming from the system side will always be mapped to CS0. After receiving
the first write transaction to update AMASK0, the chip select decoding logic will work as
per the above mentioned equation.
The table below shows memory bank size from 64 KB to 4 GB.
Table 25-3. Memory Bank Sizes in Relation to Address Mask
AM Memory Bank Size
0000_0000_0000_0000 4 GBytes
1000_0000_0000_0000 2 Gbytes
1100_0000_0000_0000 1 Gbytes
1110_0000_0000_0000 512 MB
1111_0000_0000_0000 256 MB
1111_1000_0000_0000 128 MB
1111_1100_0000_0000 64 MB
1111_1110_0000_0000 32 MB
1111_1111_0000_0000 16 MB
1111_1111_1000_0000 8 MB
1111_1111_1100_0000 4 MB
1111_1111_1110_0000 2 MB
1111_1111_1111_0000 1 MB
1111_1111_1111_1000 512 KB
1111_1111_1111_1100 256 KB
1111_1111_1111_1110 128 KB
1111_1111_1111_1111 64 KB
Address: 153_0000h base + A0h offset + (12d × i), where i=0d to 6d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
AM Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1326 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
IFC_AMASnK field descriptions
Field Description
0–15 16-bit Address mask corresponding to memory bank
AM
16–31 This field is reserved.
-
25.3.5 Chip-Select Option register - NAND Flash Mode
(IFC_CSORn_NAND)
The following figure shows the CSORn fields when CSPRn[MSEL] selects the NAND
flash mode.
NOTE
• CSOR0 is the only chip-select used for booting.
• ECC_DEC_EN, ECC_MODE[0:1], and PGS are obtained
from the configuration word when boot_load/rcw_load
occurs.
• For boot time RAL value, see NAND asynchronous mode
boot mechanism (the default is set to max assuming that the
device will ignore extra address cycles).
Address: 153_0000h base + 130h offset + (12d × i), where i=0d to 6d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
ECC_ENC_EN
ECC_DEC_EN
Reserved
Reserved
Reserved
ECC_MODE RAL Reserved PGS Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
Reserved
Reserved
BCTLD
NAND_
SPRZ Reserved PB TRHZ
MODE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1327
IFC memory map/register definition
IFC_CSORn_NAND field descriptions
Field Description
0 ECC Encoder Enable/Disable bit:
ECC_ENC_EN
NOTE: The encoder should be enabled only when performing full page operations. In case of partial
page operations, the encoder should be disabled.
0 ECC encoding disabled
1 ECC Encoding enabled
1 This field is reserved.
-
2–3 ECC Mode of operation
ECC_MODE
00 4 bit correction per 512 byte data sector
01 8 bit correction per 512 byte data sector
10 24 bit correction per 1 KB sector
11 40 bit correction per 1 KB sector
4 This field is reserved.
-
5 ECC Decoding Enable/Disable bit
ECC_DEC_EN
NOTE: The decoder should be enabled only when performing full page operations. In case of partial
page operations, the decoder should be disabled
0 ECC decoding disabled
1 ECC decoding enabled
6 This field is reserved.
-
7–8 Row Address Length: Number of address bytes issued during page address operation
RAL
NOTE: Bytes for column address are determined by page size
00 1 byte
01 2 bytes
10 3 bytes
11 4 bytes
9–10 This field is reserved.
-
11–12 Page Size
PGS
00 512 Bytes
01 2 KB
10 4 KB
11 8 KB
13–15 This field is reserved.
-
16–18 Spare size
SPRZ
NOTE: Depending on the ECC mode and page size, a fixed value of the spare region is selected during
boot. For more information, see Booting methods.
Others Reserved
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1328 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
IFC_CSORn_NAND field descriptions (continued)
Field Description
000 16 Bytes
001 64 Bytes
010 128 Bytes
011 210 Bytes
100 218 Bytes
101 224 Bytes
110 Spare size information will be used from corresponding CSORn_EXT register.
19–20 This field is reserved.
-
21–23 Pages per Block
PB
Others Reserved
000 32 Pages
001 64 Pages
010 128 Pages
011 256 Pages
100 512 Pages
24 This field is reserved.
-
25–26 NAND mode of operation
NAND_MODE
Others Reserved
00 Asynchronous mode
01 NVDDR
10 Reserved
11 Reserved
27–29 Time for read enable high to output high impedance (Z). Number of clocks required for memory to go in
TRHZ high-Z after read enable deassertion.
This field is used during last read data access. If the IFC is accessing the NAND flash for a read operation,
then after the last byte is read the NAND FSM must wait for TRHZ clock cycles so that there is no
contention on the external buffer.
Other settings are Reserved.
000 Wait for 20 IP Clocks
001 Wait for 40 IP Clocks
010 Wait for 60 IP Clocks
011 Wait for 80 IP Clocks
100 Wait for 100 IP Clocks
30 This field is reserved.
-
31 Buffer control disable. This bit signifies presence or absence of external buffer. If buffer is absent then this
BCTLD bit should be set to 1.
0 BCTL is actively driven by IFC based on direction of access.
1 BCTL is set to its default value (high) irrespective of direction of access.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1329
IFC memory map/register definition
25.3.6 Chip-Select Option register - NOR Flash Mode
(IFC_CSORn_NOR)
The following figure shows the CSORn fields when CSPRn[MSEL] selects the NOR
flash mode.
NOTE
• CSOR0 is the only chip-select used for booting.
• ADM_SHFT_MODE/ADM_SHFT is obtained from the
configuration word when boot_load/rcw_load occurs.
Address: 153_0000h base + 130h offset + (12d × i), where i=0d to 6d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
AVD_TGL_PGM_EN
ADM_SHFT_MODE
R
PGRD_EN
Reserved Reserved Reserved ADM_SHFT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
NOR_MODE
Reserved
BCTLD
ADM_SHFT Reserved TRHZ
Reset n n n 0 0 0 0 0 0 0 0 0 1 1 0 0
IFC_CSORn_NOR field descriptions
Field Description
0 Address shift mode
ADM_SHFT_
MODE NOTE: Details of shifting is given in Mode 0 pin muxing (CSORn[ADM_SHFT_MODE] = 0) .
0 Address msbs will be assigned to AD bus and ADDR bus carries the lsb
1 AD bus will carry lsbs and ADDR bus carries the msb
1–2 This field is reserved.
-
3 Page read enable from NOR device
PGRD_EN
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1330 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
IFC_CSORn_NOR field descriptions (continued)
Field Description
NOTE: Software should issue transaction based on device page size and it is valid only for parallel NOR
devices and should not be set for ADM NOR devices.
0 A multi-beat read transaction received from system bus will be split into per-beat accesses (based on
NOR port size).
1 A multi-beat read transaction received from system bus will be performed as a single-page read
operation (burst type) on NOR flash.
4–6 This field is reserved.
-
7 AVD toggle enable during burst program
AVD_TGL_
PGM_EN 0 Assert AVD only for the first address phase (performed on the flash interface) of a burst write
operation received from the system interface
1 Assert AVD during every subsequent address phase (performed on the flash interface) including the
first phase of a burst write operation received from the system interface
8–13 This field is reserved.
-
14–18 Address data multiplexing shift. It controls the way internal 32 bit address is placed on the external bus,
ADM_SHFT during NOR/GPCM address phase. Address shifting will be done by 1 bit.
Patterns not shown are reserved.
During reset, in case the RCW source is from NOR then,
if cfg_rcw_src[6:7]=00 (00 22b addressability) then ADM_SHFT = 10
if cfg_rcw_src[6:7]=01 (00 25b addressability) then ADM_SHFT = 7
if cfg_rcw_src[6:7]=10 (00 28b addressability) then ADM_SHFT = 4
00000 No shift
00001 shift ifc_addr by 1
00010 shift ifc_addr by 2
00011 shift ifc_addr by 3
00100 shift ifc_addr by 4
00101 shift ifc_addr by 5
00110 shift ifc_addr by 6
00111 shift ifc_addr by 7
01000 shift ifc_addr by 8
01001 shift ifc_addr by 9
01010 shift ifc_addr by 10
01011 shift ifc_addr by 11
01100 shift ifc_addr by 12
01101 shift ifc_addr by 13
01110 shift ifc_addr by 14
01111 shift ifc_addr by 15
10000 shift ifc_addr by 16
10001 shift ifc_addr by 17
10010 shift ifc_addr by 18
10011 shift ifc_addr by 19
10100 shift ifc_addr by 20
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1331
IFC memory map/register definition
IFC_CSORn_NOR field descriptions (continued)
Field Description
19–24 This field is reserved.
-
25–26 Type of the NOR device hooked at CSn.
NOR_MODE
00 Simple asynchronous NOR (ALE is asserted before CE_B)
01 Internal latch based AVD NOR device (ALE is asserted after CE_B)
Others Reserved
27–29 Time for read enable high to output high impedance (Z). Number of clocks required for memory to go in
TRHZ high Z after read enable deassertion.
If IFC is accessing NOR flash for read operation, then after last byte read NOR FSM must wait for these
many clock cycles so that there is no contention on external buffer.
Others Reserved
000 Wait for 20 IP Clocks
001 Wait for 40 IP Clocks
010 Wait for 60 IP Clocks
011 Wait for 80 IP Clocks
100 Wait for 100 IP Clocks
30 This field is reserved.
-
31 Buffer control disable. This bit signifies presence or absence of external buffer. If buffer is absent then this
BCTLD bit should be set to 1.
0 BCTL is actively driven by IFC based on direction of access.
1 BCTL is set to its default value (high) irrespective of direction of access.
25.3.7 Chip-Select Option register - GPCM (IFC_CSORn_GPCM)
The CSCORn can work in following two modes:
• Normal GPCM
• Generic ASIC
The following figure shows the CSORn fields when CSPRn[MSEL] selects the GPCM
mode.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1332 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
Address: 153_0000h base + 130h offset + (12d × i), where i=0d to 6d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
ABRT_RSP_EN
GPMODE
Reserved
PAR_EN
WGETA
RGETA
PAR GPTO Reserved ADM_SHFT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
Reserved
Reserved
BCTLD
ADM_SHFT BURST_LEN GAPERRD Reserved TRHZ
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0
IFC_CSORn_GPCM field descriptions
Field Description
0 GPCM Mode of operation:
GPMODE
0 Normal GPCM operation
1 Generic ASIC mode operation
1 Parity mode.
PAR
0 Odd Parity
1 Even Parity
2 Parity checking enable/disable:
PAR_EN
0 Parity checking disabled over the received data
1 Parity checking enabled over the received data
3 This field is reserved.
-
4–7 GPCM Timeout Count: For normal GPCM, the timeout occur only when read data/write data transaction is
GPTO external transaction acknowledgement based and IFCTA signal has not come.
In Generic ASIC mode timeout occurs when RDY_L has not come for the number of IP clks cycles defined
by this register field.
0000 256 cycles of IFC module input clocks
0001 512 cycles of IFC module input clocks
0010 1024 cycles of IFC module input clocks
0011 2048 cycles of IFC module input clocks
0100 4096 cycles of IFC module input clocks
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1333
IFC memory map/register definition
IFC_CSORn_GPCM field descriptions (continued)
Field Description
0101 8192 cycles of IFC module input clocks
0110 16,384 cycles of IFC module input clocks
0111 32,768 cycles of IFC module input clocks
1000 65,536 cycles of IFC module input clocks
1001 131,072 cycles of IFC module input clocks
1010 262,144 cycles of IFC module input clocks
1011 524,288 cycles of IFC module input clocks
1100 1,048,576 cycles of IFC module input clocks
1101 2,097,152 cycles of IFC module input clocks
1110 4,194,304 cycles of IFC module input clocks
1111 8,388,608 cycles of IFC module input clocks
8–10 This field is reserved.
-
11 Abort Error Response Enable. An error response will be sent for read transaction if the transaction is
ABRT_RSP_EN aborted by IFCTA_B when REGTA is programmed in abort mode.
This bit is valid only for normal GPCM mode.
0 No error response will be sent.
1 Error response will be sent for abort.
12 GPCM external access termination mode for read access.
RGETA
NOTE: This bit is valid only for normal GPCM Mode.
0 Abort mode. IFCTA_B signal acts as abort signal.
GPCM read access is terminated internally by the controller at the expiry of TRAD counter unless
aborted externally (If IFCTA_B asserts before the expiry of TRAD counter access will be terminated).
Error will be reported in GPCM_EVTER_STAT[ABER] register.
1 Acknowledgement mode. IFCTA_B acts as acknowledgement/data qualifier signal.
GPCM read access is acknowledged by external pin IFCTA_B and only it can complete the read
access. If it is not asserted within CSOR[GPTO] time, GPCM_EVTER_STAT[TOER] will be set.
13 GPCM external access termination mode for write access:
WGETA
NOTE: This bit is valid only for normal GPCM Mode.
0 Abort mode. GPCM write access is terminated if IFCTA_B asserts before expiry of TWP counter in
case of single beat transaction. If IFCTA_B is asserted during burst write the current transaction is
aborted and only after deassertion of IFCTA_B it will be resumed. Details are given in Normal GPCM
program operation, Figure 25-46. Note that in abort mode no error is reported for write transaction.
1 Acknowledgement mode: GPCM write access is acknowledged/qualified by external pin IFCTA_B
assertion. If it is not asserted within CSOR[GPTO] time, GPCM_EVTER_STAT[TOER] will be set
14–18 Address data multiplexing shift:
ADM_SHFT
Left shift the flash address by this value and assign it to address data multiplexed bus (AD[0:15]) ifc_data.
By this method, the address msbs will be assigned to address data muxed bus that can be latched by
asserting the AVD/ALE signal.
NOTE: This shifting is only valid in normal GPCM mode.
Others Reserved
00000 No shift
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1334 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
IFC_CSORn_GPCM field descriptions (continued)
Field Description
00001 Left shift addr[0:31] by 1 and assign it to AD[0:15]
00010 Left shift ifc_addr by 2
00011 Left shift ifc_addr by 3
00100 Left shift ifc_addr by 4
00101 Left shift ifc_addr by 5
00110 Left shift ifc_addr by 6
00111 Left shift ifc_addr by 7
01000 Left shift ifc_addr by 8
01001 Left shift ifc_addr by 9
01010 Left shift ifc_addr by 10
01011 Left shift ifc_addr by 11
01100 Left shift ifc_addr by 12
01101 Left shift ifc_addr by 13
01110 Left shift ifc_addr by 14
01111 Left shift ifc_addr by 15
10000 Left shift ifc_addr by 16
10001 Left shift ifc_addr by 17
10010 Left shift ifc_addr by 18
10011 Left shift ifc_addr by 19
10100 Left shift ifc_addr by 20
19 This field is reserved.
-
20–22 GPCM burst length. It defines the maximum number of beats that will be sent/received in one burst cycle.
BURST_LEN This is programmed in terms of port-size transfer. For example, if the port size is 2 bytes and burst_length
is 2, then the total of 8 bytes will be transferred in one burst cycle (that is, 4 beats of data transfers and
each data transfer of 2 bytes).
This is valid only in normal GPCM mode.
000 Non-burst mode
001 2
010 4
011 8
100 16
101 32
110 64
111 128
23–24 Generic ASIC parity error indication delay. Represents the delay (in terms of number of IFC_CLK)
GAPERRD between the indication of parity error for address and write data with respect to start of frame (SOF_L).
00 1 IFC_CLK delayed
01 2 IFC_CLK delayed
10 3 IFC_CLK delayed
11 4 IFC_CLK delayed
25–26 This field is reserved.
-
27–29 Time for read enable high to output high impedance (Z)- Number of clocks required for memory to go in
TRHZ high Z after read enable deassertion.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1335
IFC memory map/register definition
IFC_CSORn_GPCM field descriptions (continued)
Field Description
If IFC is accessing for read operation, then after last byte read wait for these many clock cycles so that
there is no contention on external bus.
Others Reserved
000 Wait for 20 IFC module input clocks
001 Wait for 40 IFC module input clocks
010 Wait for 60 IFC module input clocks
011 Wait for 80 IFC module input clocks
100 Wait for 100 IFC module input clocks
30 This field is reserved.
-
31 Buffer control disable. This bit signifies presence or absence of external buffer. If buffer is absent then this
BCTLD bit should be set to 1.
0 BCTL is actively driven by IFC based on direction of access.
1 BCTL is set to its default value (high) irrespective of direction of access.
25.3.8 Extended Chip-Select Option register - NAND Flash Mode
(IFC_CSORn_EXT)
The figure below shows the CSORn_EXT fields when CSPRn[MSEL] selects the NAND
flash mode.
NOTE
CSORn_EXT register is reserved if CSPRn[MSEL] is in NOR/
GPCM mode.
Address: 153_0000h base + 134h offset + (12d × i), where i=0d to 6d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
AUTO_TIM_PARAMS_
R
Reserved
SEL
Reserved MODE_FREQ
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1336 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Reserved SPARE_BYTES_CSn
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_CSORn_EXT field descriptions
Field Description
0–10 This field is reserved.
-
11 Used to select the automatically calculated timing parameters instead of the user programmed timing
AUTO_TIM_ parameters.
PARAMS_SEL
NOTE: Automatic parameter calculation option is not applicable for Async Mode. User has to compute
and program FTIM registers for Async Mode.
0 User programmed timing parameters (FTIM0-FTIM3) selected
1 Automatically calculated timing parameters selected
12 This field is reserved.
-
13–15 Indicates the timing mode with which the source synchronous device is programmed. This field is qualified
MODE_FREQ with NAND_MODE (CSOR[25:26]) and defined as follows:NAND_MODE = 01 (NVDDR mode)
000 20 MHz
001 33 MHz
010 50 MHz
011 66 MHz
100 83 MHz
101 100 MHz
110 Reserved
111 Reserved
16–20 This field is reserved.
-
21–31 No. of bytes in spare region. This filed is applicable only when corresponding CSORn[SPRZ] is 3'h110.
SPARE_BYTES_
Others Reserved.
CSn
0x000 0 Spare region bytes
0x001 1 Spare region byte
...
0x400 1024 spare region bytes
0x7FE 2046 spare region bytes
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1337
IFC memory map/register definition
25.3.9 Flash Timing register 0 for Chip Select n - NAND flash
asyncNVDDR mode (IFC_FTIM0_CSn_NAND)
The flash timing registers define the flash interface timings. These register fields are
defined differently depending on the machine type (NOR/NAND/GPCM) selected for
that bank by CSPRn[MSEL] field. Timing registers are provided separately for each
chip-select. Timing parameter are in terms of IFC module input clock cycles. More
details about the register field is given in section Programming model for flash interface
timing .
NOTE
• Timing values of FTIM0, FTIM1, FTIM2, and FTIM3
registers for chip-select 0 in NAND/NOR flash mode will
be loaded at boot_load/rcw_load by the parameters passed.
• If CSOR_EXTn[AUTO_TIM_PARAMS_SEL] is set, then
the values returned on reading the FTIM0, FTIM1, FTIM2,
FTIM3 registers will be the ones calcuated automatically
by IFC (based on CSOR_EXTn[MODE_FREQ] and the
Clock divsion ratio) and not the ones programmed in the
FTIM registers. This is valid only when
CSORn[NAND_MODE] = 2’b01, 2’b10, 2’b11.
• The TRP value loaded during RCW/boot load is taken as
(TRAD +2) input clocks.
• For normal GPCM mode (write transaction) all the three
timing parameters (that is, TEAHC, TACSE, and TCS)
should not be programmed zero together.
• For normal GPCM mode (read transaction) all the three
timing parameters (that is, TEAHC, TACSE, and TACO)
should not be programmed zero together.
During NAND and NOR boot, default values of FTIMnCS0 must be as shown in below
table.
Table 25-4. Default values of FTIMnCS0 during boot
FTIMnCS0 Value during NAND boot Value during NOR boot
FTIM0_CS0 181C_080C 400B_0206
FTIM1_CS0 3850_141A 1b00_3005
FTIM2_CS0 0300_8028 0208_1C0A
FTIM3_CS0 2800_0000 00000000
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1338 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
The following figure shows the FTIM0_CSn fields when CSPRn[MSEL] selects the
NAND flash mode and CSORn[NAND MODE] selects NAND flash async mode.
Address: 153_0000h base + 1C0h offset + (48d × i), where i=0d to 6d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
W
Reserved TCS Reserved TCAD
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_FTIM0_CSn_NAND field descriptions
Field Description
0–1 This field is reserved.
-
2–7 Chip Enable (CE) setup time.
TCS
000000 Reserved
000001 1 IFC module input clock
000010 2 IFC module input clocks
...
111111 63 IFC module input clocks
8–9 This field is reserved.
-
10–15 Command, Address, Data delay (Command-command, command-address, address-address, address-
TCAD command, command/address- start of data)
000000 Reserved
000001 1 IFC module input clock
000010 2 IFC module input clocks
...
111111 63 IFC module input clocks
16–31 This field is reserved.
-
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1339
IFC memory map/register definition
25.3.10 Flash Timing register 0 for Chip Select n - NAND flash
Asynchronous Mode (IFC_FTIM0_CS_NAND_ASYNC_MODE)
The following register shows the FTIM0_CSn fields when CSPRn[MSEL] selects the
NAND Flash Mode and CSORn[NAND_MODE] selects NAND Flash Asynchronous
Mode.
Address: 153_0000h base + 1C0h offset = 153_01C0h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
Reserved
Reserved
TCCST TWP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Reserved TWCHT Reserved TWH
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_FTIM0_CS_NAND_ASYNC_MODE field descriptions
Field Description
0 This field is reserved.
-
1–6 This parameter is defined in the following two ways:
TCCST
Command latch enable (CLE) assertion time with respect to CS assertion time.
CLE/ALE assertion time after previous CLE/ALE phase (post TWH time).
000000 Reserved
000001 1 IFC module input clock
000010 2 IFC module input clocks
...
111111 63 IFC module input clocks
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1340 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
IFC_FTIM0_CS_NAND_ASYNC_MODE field descriptions (continued)
Field Description
7 This field is reserved.
-
8–15 Write enable (WE) pulse width
TWP
00000000 Reserved
00000001 1 IFC module input clock
00000010 2 IFC module input clocks
...
11111111 255 IFC module input clocks
16–17 This field is reserved.
-
18–23 WE to command hold time
TWCHT
000000 Reserved
000001 1 IFC module input clock
000010 2 IFC module input clocks
...
111111 63 IFC module input clocks
24–25 This field is reserved.
-
26–31 WE high hold time
TWH
000000 Reserved
000001 1 IFC module input clock
000010 2 IFC module input clocks
...
111111 63 IFC module input clocks
25.3.11 Flash Timing register 0 for CSn - NOR Flash Mode
(IFC_FTIM0_CSn_NOR)
The following figure shows the FTIM0_CSn fields when CSPRn[MSEL] selects the
NOR flash mode.
Address: 153_0000h base + 1C0h offset + (48d × i), where i=0d to 6d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
W
TACSE Reserved TEADC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
Reserved TAVDS Reserved TEAHC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1341
IFC memory map/register definition
IFC_FTIM0_CSn_NOR field descriptions
Field Description
0–3 Address phase (after external latch enable deassertion) end to chip enable assertion time
TACSE
0000 Reserved
0001 1 IFC module input clock
0010 2 IFC module input clocks
...
1111 15 IFC module input clocks
4–9 This field is reserved.
-
10–15 External latch address delay cycles: External address valid (AVD) assertion time (pulse width of external
TEADC latch enable signal).
000000 Reserved
000001 1 IFC module input clock
000010 2 IFC module input clocks
...
111111 63 IFC module input clocks
16–17 This field is reserved.
-
18–23 Delay between CS assertion to AVD/ALE assertionin AVD devices (address latch internal to the device)
TAVDS
000000 Reserved
000001 1 IFC module input clock
000010 2 IFC module input clocks
...
111111 63 IFC module input clocks
24–25 This field is reserved.
-
26–31 Latch address hold cycles.
TEAHC
000000 Reserved
000001 1 IFC module input clock
000010 2 IFC module input clocks
...
111111 63 IFC module input clocks
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1342 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
25.3.12 Flash Timing register 0 for CSn - Normal GPCM Mode
(IFC_FTIM0_CSn_GPCM)
The following figure shows the FTIM0_CSn fields when CSPRn[MSEL] selects the
GPCM mode.
Address: 153_0000h base + 1C0h offset + (48d × i), where i=0d to 6d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
TACSE Reserved TEADC Reserved TEAHC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_FTIM0_CSn_GPCM field descriptions
Field Description
0–3 Address phase (After address hold cycle) end to chip enable assertion time
TACSE
0000 Reserved
0001 1 IFC module input clock
0010 2 IFC module input clocks
...
1111 15 IFC module input clocks
4–9 This field is reserved.
-
10–15 External latch address delay cycles. External address latch enable (ALE) assertion time (pulse width of
TEADC external latch enable signal)
000000 Reserved
000001 1 IFC module input clock
000010 2 IFC module input clocks
...
111111 63 IFC module input clocks
16–25 This field is reserved.
-
26–31 External latch address hold cycles: Address hold cycle relative to external latch enable signal
TEAHC
000000 Reserved
000001 1 IFC module input clock
000010 2 IFC module input clocks
...
111111 63 IFC module input clocks
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1343
IFC memory map/register definition
25.3.13 Flash Timing register 1 for Chip-Select n - NAND Flash
NVDDR Mode (IFC_FTIM1_CSn_NAND)
The following figure shows the FTIM1_CSn fields when CSPRn[MSEL] selects the
NAND flash mode.
Address: 153_0000h base + 1C4h offset + (48d × i), where i=0d to 6d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
W
TADLE TWB
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
Reserved TRR TWRCK
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_FTIM1_CSn_NAND field descriptions
Field Description
0–7 Effective address to data loading time
TADLE
00000000 Reserved
00000001 1 IFC module input clock
00000010 2 IFC module input clocks
...
11111111 255 IFC module input clocks
8–15 Clock Rising Edge to SR[6] (R/B) low
TWB
16–17 This field is reserved.
-
18–23 Ready busy high to read enable (RE) low time
TRR
000000 Reserved
000001 1 IFC module input clock
000010 2 IFC module input clocks
...
111111 63 IFC module input clocks
24–31 W/R low to data output cycle
TWRCK
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1344 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
25.3.14 Flash Timing register 1 for Chip Select n - Asynchronous
Mode (IFC_FTIM1_CSn_NAND_ASYNC_MODE)
The following figure shows the FTIM1_CSn fields when CSPRn[MSEL] selects the
NAND flash asynchronus mode.
Address: 153_0000h base + 1C4h offset + (48d × i), where i=0d to 6d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
W
TADLE TWBE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
Reserved TRR TRP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_FTIM1_CSn_NAND_ASYNC_MODE field descriptions
Field Description
0–7 Effective address to data loading time
TADLE
00000000 Reserved
00000001 1 IFC module input clock
00000010 2 IFC module input clocks
...
11111111 255 IFC module input clocks
8–15 WE high (after TWH time) to ready busy (RB_B) low time
TWBE
00000000 Reserved
00000001 1 IFC module input clock
00000010 2 IFC module input clocks
...
11101111 239 IFC module input clocks
11110000-11111111 Reserved
16–17 This field is reserved.
-
18–23 Ready busy high to read enable (RE) low time
TRR
000000 Reserved
000001 1 IFC module input clock
000010 2 IFC module input clocks
...
111111 63 IFC module input clocks
24–31 RE pulse width
TRP
00000000 Reserved
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1345
IFC memory map/register definition
IFC_FTIM1_CSn_NAND_ASYNC_MODE field descriptions (continued)
Field Description
00000001 1 IFC module input clock
00000010 2 IFC module input clocks
...
11111111 255 IFC module input clocks
25.3.15 Flash Timing register 1 for CSn - NOR Flash Mode
(IFC_FTIM1_CSn_NOR)
The following figure shows the FTIM1_CSn fields when CSPRn[MSEL] selects the
NOR flash mode.
Address: 153_0000h base + 1C4h offset + (48d × i), where i=0d to 6d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
TACO Reserved TRAD_NOR TSEQRAD_NOR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_FTIM1_CSn_NOR field descriptions
Field Description
0–7 This field represents CS_B assertion to output enable (OE) assertion setup time for conventional NOR
TACO and address hold time to OE_B assertion in case of ADM NOR
00000000 Reserved
00000001 1 IFC module input clock
00000010 2 IFC module input clocks
...
11111111 255 IFC module input clocks
8–15 This field is reserved.
-
16–23 NOR flash read access delay: It represents the read enable to data access time plus total round trip board
TRAD_NOR delay from the external NOR flash memory during read operation. Its value can be calculated as Read
data access time considering data gets sampled in the mid of data eye + 2* Board Delay + 2 .
00000000 Reserved
00000001 1 IFC module input clock
00000010 2 IFC module input clocks
...
11111111 255 IFC module input clocks
24–31 NOR flash sequential read access delay. It represents the address to data access time plus total round
TSEQRAD_NOR trip delay from the external NOR flash memory during sequential read operation. Its value can be
calculated as [NOR Page Address Delay (max) for sequential read + 2*Board Delay + Device Setup
Time].
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1346 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
IFC_FTIM1_CSn_NOR field descriptions (continued)
Field Description
00000000 Reserved
00000001 1 IFC module input clock
00000010 2 IFC module input clocks
..........
11111111 255 IFC module input clocks
25.3.16 Flash Timing register 1 for CSn - Normal GPCM Mode
(IFC_FTIM1_CSn_GPCM)
The following figure shows the FTIM1_CSn fields when CSPRn[MSEL] and
CSOPn[GPMODE] selects the normal GPCM mode.
Address: 153_0000h base + 1C4h offset + (48d × i), where i=0d to 6d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
TACO Reserved TRAD Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_FTIM1_CSn_GPCM field descriptions
Field Description
0–7 CS assertion to output enable (OE) assertion setup time
TACO
00000000 Reserved
00000001 1 IFC module input clock
00000010 2 IFC module input clocks
...
11111111 255 IFC module input clock
8–17 This field is reserved.
-
18–23 GPCM read access delay: It represents the output enable assertion time.
TRAD
See Normal GPCM read operation .
000000 Reserved
000001 1 IFC module input clock
000010 2 IFC module input clocks
...
111111 63 IFC module input clocks
24–31 This field is reserved.
-
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1347
IFC memory map/register definition
25.3.17 Flash Timing register 2 for Chip Select n - NAND Flash
NVDDR Mode (IFC_FTIM2_CSn_NAND)
The following figure shows the FTIM2_CSn fields when CSPRn[MSEL] selects the
NAND flash mode.
Address: 153_0000h base + 1C8h offset + (48d × i), where i=0d to 6d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
TCKWR TWHR TRHW Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_FTIM2_CSn_NAND field descriptions
Field Description
0–7 Data output end to W/R high.
TCKWR
8–15 Command, Address or Data input cycle to Data output clycle.
TWHR
16–23 Data Output cycle to Command, Address or Data Input cycle
TRHW
24–31 This field is reserved.
-
25.3.18 Flash Timing register 2 for Chip Select n - NAND Flash
Asynchronous Mode
(IFC_FTIM2_CSn_NAND_ASYNC_MODE)
The following figure shows the FTIM2_CSn fields when CSPRn[MSEL] selects the
NAND flash asynchronous mode.
Address: 153_0000h base + 1C8h offset + (48d × i), where i=0d to 6d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
Reserved TRAD Reserved TREH Reserved TWHRE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_FTIM2_CSn_NAND_ASYNC_MODE field descriptions
Field Description
0–2 This field is reserved.
-
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1348 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
IFC_FTIM2_CSn_NAND_ASYNC_MODE field descriptions (continued)
Field Description
3–10 Flash read access delay: It represents the data sampling time of read data. It should be programmed such
TRAD that sampling is done at the center of the received data eye. For calculation of data eye width and
appropriate data sampling time refer to NAND asynchronous mode calculating read data window width .
00000000 Reserved
00000001 1 IFC module input clock
00000010 2 IFC module input clocks
...
11111111 255 IFC module input clocks
11–14 This field is reserved.
-
15–20 RE_B High Time
TREH
000000 Reserved
000001 1 IFC module input clock
000010 2 IFC module input clocks
...
111111 63 IFC module input clocks
21–23 This field is reserved.
-
24–31 WE_B High to RE_B Low Effective
TWHRE
00000000 Reserved
00000001 1 IFC module input clock
00000010 2 IFC module input clocks
...
11111111 255 IFC module input clocks
25.3.19 Flash Timing register 2 for CSn - NOR Flash Mode
(IFC_FTIM2_CSn_NOR)
The following figure shows the FTIM2_CSn fields when CSPRn[MSEL] selects the
NOR flash mode.
Address: 153_0000h base + 1C8h offset + (48d × i), where i=0d to 6d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
W
Reserved TCS Reserved TCH Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
TWPH Reserved TWP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1349
IFC memory map/register definition
IFC_FTIM2_CSn_NOR field descriptions
Field Description
0–3 This field is reserved.
-
4–7 Chip-select assertion to WE assertion setup time
TCS
0000 Reserved
0001 1 IFC module input clock
0010 2 IFC module input clocks
...
1111 15 IFC module input clocks
8–9 This field is reserved.
-
10–13 Chip-select hold time with respect to WE deassertion
TCH
0000 Reserved
0001 1 IFC module input clock
0010 2 IFC module input clocks
...
1111 15 IFC module input clocks
14–15 This field is reserved.
-
16–21 Write enable pulse high time
TWPH
000000 Reserved
000001 1 IFC module input clock
000010 2 IFC module input clocks
...
111111 63 IFC module input clocks
22–23 This field is reserved.
-
24–31 Write enable pulse width
TWP
00000000 Reserved
00000001 1 IFC module input clock
00000010 2 IFC module input clocks
...
11111111 255 IFC module input clocks
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1350 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
25.3.20 Flash Timing register 2 for CSn - Normal GPCM Mode
(IFC_FTIM2_CSn_GPCM)
The following figure shows the FTIM2_CSn fields when CSPRn[MSEL] selects the
normal GPCM mode.
Address: 153_0000h base + 1C8h offset + (48d × i), where i=0d to 6d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
W
Reserved TCS Reserved TCH Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
Reserved TWP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_FTIM2_CSn_GPCM field descriptions
Field Description
0–3 This field is reserved.
-
4–7 Chip-select assertion to WE assertion setup time
TCS
0000 Reserved
0001 1 IFC module input clock
0010 2 IFC module input clocks
...
1111 15 IFC module input clocks
8–9 This field is reserved.
-
10–13 Chip-select hold time with respect to WE deassertion
TCH
0000 Reserved
0001 1 IFC module input clock
0010 2 IFC module input clocks
...
1111 15 IFC module input clocks
14–23 This field is reserved.
-
24–31 Write enable pulse width
TWP
00000000 Reserved
00000001 1 IFC module input clock
00000010 2 IFC module input clocks
...
11111111 255 IFC module input clock
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1351
IFC memory map/register definition
25.3.21 Flash Timing register 3 for Chip Select n - NAND Flash Mode
(IFC_FTIM3_CSn_NAND)
The following figure shows the FTIM3_CSn fields when CSPRn[MSEL] selects the
NAND flash NVDDRmode.
Address: 153_0000h base + 1CCh offset + (48d × i), where i=0d to 6d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
TWW Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_FTIM3_CSn_NAND field descriptions
Field Description
0–7 Write Protect WP_B transition time. It represents the idle cycles inserted by the IFC controller whenever
TWW corresponding WP_B pin toggles.
Refer Write protect for more details.
00000000 Reserved
00000001 1 IFC module input clock
00000010 2 IFC module input clocks
...
11111111 255 IFC module input clocks
8–31 This field is reserved.
-
25.3.22 Flash Timing register 3 for Chip Select n - NAND Flash
Asynchronous Mode
(IFC_IFC_FTIMn3_CS_NAND_ASYNC_MODE)
The following figure shows the FTIM3_CSn fields when CSPRn[MSEL] selects the
NAND flash asynchronous mode.
Address: 153_0000h base + 1CCh offset + (48d × i), where i=0d to 6d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
TWW Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1352 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
IFC_IFC_FTIMn3_CS_NAND_ASYNC_MODE field descriptions
Field Description
0–7 Write Protect WP_B transition time. It represents the idle cycles inserted by the IFC controller whenever
TWW corresponding WP_B pin toggles.
Refer Write protect for more details.
00000000 Reserved
00000001 1 IFC module input clock
00000010 2 IFC module input clocks
...
11111111 255 IFC module input clocks
8–31 This field is reserved.
-
25.3.23 Flash Timing register 3 for CSn - NOR Flash Mode
(IFC_FTIM3_CS_NOR)
The following figure shows the FTIM3_CSn fields when CSPRn[MSEL] selects the
NOR flash mode.
NOTE
Offset for IFC_FTIM3_CSn_NOR are 0x0_01CC, 0x0_01FC,
0x0_022C, 0x0_025C, 0x0_028C, 0x0_02BC, and 0x0_02EC
Address: 153_0000h base + 1CCh offset = 153_01CCh
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_FTIM3_CS_NOR field descriptions
Field Description
0–31 This field is reserved.
-
25.3.24 Flash Timing register 3 for CSn - Normal GPCM Mode
(IFC_FTIM3_CSn_GPCM)
The following figure shows the FTIM3_CSn fields when CSPRn[MSEL] selects the
GPCM flash mode.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1353
IFC memory map/register definition
Address: 153_0000h base + 1CCh offset + (48d × i), where i=0d to 6d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
TAAD Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_FTIM3_CSn_GPCM field descriptions
Field Description
0–5 GPCM address access delay. This timing parameter is required for read cycles when GPCM is working in
TAAD burst mode, that is, burst length is programmed to a non-zero value. The first data beat of a burst is
sampled after TRAD time of OE assertion; subsequent beat data are sampled after TAAD time of the
previous sample pulse. The same timing is used for sending the new address of the beat. The second
address is sent after TRAD time of OE assertion and subsequent address beats are sent after TAAD time
of the last beat. This is programmed in terms of IFC module input clock but should always be a mupltiple
of IFC_CLK.
This is valid only for normal GPCM mode.
000000 Reserved
000001 1 IFC module input clock
000010 2 IFC module input clocks
...
111111 63 IFC module input clocks
6–31 This field is reserved.
-
25.3.25 Ready Busy Status for each Chip Select (IFC_RB_STAT)
Address: 153_0000h base + 400h offset = 153_0400h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R RB0 RB1 RB2 RB3 RB4 RB5 RB6
Reserved
W
Reset n n n n 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_RB_STAT field descriptions
Field Description
0 Ready Busy input from CS0. This register field represents the status of RB_B signal of CS0 sampled by
RB0 IFC at every clock.
0 Device connected at CS0 is driving RB_B signal as Busy
1 Device connected at CS0 is driving RB_B signal as Ready.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1354 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
IFC_RB_STAT field descriptions (continued)
Field Description
1 Ready Busy input from CS1
RB1
This register field represents the status of RB_B signal of CS1 sampled by IFC at every clock.
0 Device connected at CS1 is driving RB_B signal as Busy
1 Device connected at CS1 is driving RB_B signal as Ready.
2 Ready Busy input from CS2
RB2
This register field represents the status of RB_B signal of CS2 sampled by IFC at every clock.
0 Device connected at CS2 is driving RB_B signal as Busy
1 Device connected at CS2 is driving RB_B signal as Ready.
3 Ready Busy input from CS3
RB3
This register field represents the status of RB_B signal of CS3 sampled by IFC at every clock.
0 Device connected at CS3 is driving RB_B signal as Busy
1 Device connected at CS3 is driving RB_B signal as Ready.
4 Ready Busy input from CS4
RB4
This register field represents the status of RB_B signal of CS4 sampled by IFC at every clock.
0 Device connected at CS4 is driving RB_B signal as Busy
1 Device connected at CS4 is driving RB_B signal as Ready.
5 Ready Busy input from CS5
RB5
This register field represents the status of RB_B signal of CS5 sampled by IFC at every clock.
0 Device connected at CS5 is driving RB_B signal as Busy
1 Device connected at CS5 is driving RB_B signal as Ready.
6 Ready Busy input from CS6
RB6
This register field represents the status of RB_B signal of CS6 sampled by IFC at every clock.
0 Device connected at CS6 is driving RB_B signal as Busy
1 Device connected at CS6 is driving RB_B signal as Ready.
7–31 This field is reserved.
-
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1355
IFC memory map/register definition
25.3.26 General Control register (IFC_GCR)
The reset value of this field is passed through parameter.
Address: 153_0000h base + 40Ch offset = 153_040Ch
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SOFT_RST_
R
ALL
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
TBCTL_TRN_TIME Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_GCR field descriptions
Field Description
0 Software Reset All: It is used to reset the whole IFC hardware (NAND, NOR, and GPCM).
SOFT_RST_ALL
With this reset only the event/error status registers of IFC will be cleared. Programming registers will retain
their value.
The software reset mechanism is implemented such that IFC will send the pending transactions on system
bus with good response. In case of pending read transaction, garbage data will be supplied back. Once
the whole IFC is in IDLE state, the software can clear this bit. IFC hardware stops software from clearing
this bit till all the processing has been done and IFC hardware is in idle state.
If this bit is set, hardware will clear it once reset operation is completed. Software should poll this bit to get
cleared before initiating any new transaction.
0 No Software reset
1 Assert Software reset
1–15 This field is reserved.
-
16–20 It represents the turnaround time of external buffer in terms of number of IFC module input clock cycles.
TBCTL_TRN_ BCTL should be kept high for these many clock cycles before issuing a write transaction after a read on
TIME flash interface. See Data buffer control (BCTL) for more details.
21–31 This field is reserved.
-
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1356 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
25.3.27 Common Event and Error Status register
(IFC_CM_EVTER_STAT)
Common event and error status register (CM_EVTER_STAT) indicates the cause of an
error or event that cannot be classified in NAND, NOR, and GPCM.
Address: 153_0000h base + 418h offset = 153_0418h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R CSER
Reserved
W w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_CM_EVTER_STAT field descriptions
Field Description
0 Chip-Select Error
CSER
0 No chip-select error
1 A transaction was sent to IFC which is not mapped to any memory bank
1–31 This field is reserved.
-
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1357
IFC memory map/register definition
25.3.28 Common Event and Error Enable register
(IFC_CM_EVTER_EN)
This register is used to enable/disable the logging of event and error indication in the
CM_EVTER_STAT register.
Address: 153_0000h base + 424h offset = 153_0424h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
CSEREN
Reserved
W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_CM_EVTER_EN field descriptions
Field Description
0 Chip-Select Error Checking Enable
CSEREN
0 Chip-Select Error Checking Disabled
1 Chip-Select Error Checking Enabled
1–31 This field is reserved.
-
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1358 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
25.3.29 Common Event and Error Interrupt Enable register
(IFC_CM_EVTER_INTR_EN)
Common event and error interrupt enable register (CM_EVTER_INTR_EN) is used to
enable/disable the generation of interrupt signals corresponding to common error and
event reporting. Software must clear pending events and errors in CM_EVTER_STAT
register before enabling the interrupts.
Address: 153_0000h base + 430h offset = 153_0430h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CSERIREN
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_CM_EVTER_INTR_EN field descriptions
Field Description
0 Chip-Select Error Interrupt Enable
CSERIREN
0 Chip-Select Error Interrupt Disabled
1 Chip-Select Error Interrupt Enabled
1–31 This field is reserved.
-
25.3.30 Common Transfer Error Attributes register 0
(IFC_CM_ERATTR0)
These registers store the attribute corresponding to the first transaction on which common
error occured.
Common transfer error attribute register 0 (CM_ERATTR0) is used to register the
transaction attributes corresponding to the first common error occured.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1359
IFC memory map/register definition
Address: 153_0000h base + 43Ch offset = 153_043Ch
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
ERTYP
R ERAID
Reserved Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R ERSRCID
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_CM_ERATTR0 field descriptions
Field Description
0 Transaction type of the error
ERTYP
0 Write Transaction
1 Read Transaction
1–3 This field is reserved.
-
4–11 ID of the error transaction
ERAID
12–15 This field is reserved.
-
16–23 Source ID of the error transaction, always zero.
ERSRCID
24–31 This field is reserved.
-
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1360 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
25.3.31 Common Transfer Error Attributes register 1
(IFC_CM_ERATTR1)
Common transfer error attribute register1 (CM_ERATTR1) is used to register the
transaction address corresponding to the first error.
Address: 153_0000h base + 440h offset = 153_0440h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R ERADDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_CM_ERATTR1 field descriptions
Field Description
0–31 32 bits of transaction address corresponding to error transaction
ERADDR
25.3.32 Clock Control register (IFC_CCR)
Address: 153_0000h base + 44Ch offset = 153_044Ch
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Reserved CLKDIV Reserved CLK_DLY
W
Reset 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
INV_CLK_EN
Reserved
W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_CCR field descriptions
Field Description
0–3 This field is reserved.
-
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1361
IFC memory map/register definition
IFC_CCR field descriptions (continued)
Field Description
4–7 Clock division ratio: This field is used to generate the IFC clock from the IFC module input clock. The IFC
CLKDIV clock is sent out after inverting it according to the INV_CLK_EN setting.
0000 Reserved
0001 Divide by 2
0010 Divide by 3
0011 Divide by 4
0100 Reserved
0101
0110 Reserved
0111 Divide by 8
1000 Reserved
1001 Reserved
1010 Reserved
1011 Reserved
1100 Reserved
1101 Reserved
1110 Reserved
1111 Reserved
8–11 This field is reserved.
-
12–15 IFC Clock Delay
CLK_DLY
This field specifies the number of IFC module input clocks by which external clock is delayed.
0000 No delay
0001 1 IFC module input clocks delay introduced
0010 2 IFC module input clocks delay introduced
...
1111 15 IFC module input clocks delay introduced
16 IFC Clock Inversion
INV_CLK_EN
This field specifies whether IFC clock is inverted before sending out.
0 IFC clock is not inverted
1 IFC clock is inverted
17–31 This field is reserved.
-
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1362 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
25.3.33 Clock Status register (IFC_CSR)
Address: 153_0000h base + 450h offset = 153_0450h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CLK_STAT
Reserved
Reset n 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_CSR field descriptions
Field Description
0 Clock Status. This bit is cleared by hardware in case any of the field of CCR is changed. It is again set
CLK_STAT when external clock is stable. New GPCM operation can be initiated only after clock is stable for new
CLK_DIV ratio.
0 Clock is unstable
1 Clock is stable
1–31 This field is reserved.
-
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1363
IFC memory map/register definition
25.3.34 DDR Clock Control register (IFC_DDR_CCR)
This register is used for programming the clock divider when NV-DDR interface is at
frequencies up to 100 MHz.
Address: 153_0000h base + 454h offset = 153_0454h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
GLOBAL_DDR_CLK_EN
PGM_DDR_CLK_STOP
R
Reserved
TDQSS
Reserved DDR_LOW_CLKDIV Reserved Reserved
Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_DDR_CCR field descriptions
Field Description
0–1 This field is reserved.
- Reserved
2 Switches off the IFC DDR clock. Used when device is not programmed as Source Synchronous.
GLOBAL_DDR_
CLK_EN 0 Clock disabled.
1 Clock enabled.
3 DDR Clock Stop in case of Program Operation (except SET FEATURES).This field is valid only when
PGM_DDR_ CSOR[NAND_MODE] = 2'b01
CLK_STOP
0 Clock Enabled
1 Clock Stopped
4 This field is reserved.
- Reserved
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1364 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
IFC_DDR_CCR field descriptions (continued)
Field Description
5–8 Clock division ratio: This field is used to generate the divided clock from ip_clk.
DDR_LOW_
0000- Divide by 2
CLKDIV
0001- Divide by 4
0010- Divide by 6
0011- Divide by 8
0100- Divide by 10
0101- Divide by 12
0110- Divide by 14
0111- Divide by 16
1000- Divide by 18
1001- Divide by 20
1010- Divide by 22
1011- Divide by 24
1100- Divide by 26
1101- Divide by 28
1110- Divide by 30
1111- Divide by 32
Note- After reset, divided by 4 clock is sent out
9–10 This field is reserved.
- Reserved
11 Data input to first DQS transition delay. This field is valid only when CSOR[NAND_MODE] = 2'b01
TDQSS
0 0.75 IFC_DDR_CLOCK period
1 1.25 IFC_DDR_CLOCK period
12–31 This field is reserved.
-
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1365
IFC memory map/register definition
25.3.35 NAND Configuration register (IFC_NCFGR)
A separate 1 KB memory-mapped region is assigned to NAND-specific registers.
Address: 153_0000h base + 1000h offset = 153_1000h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R SINGLE_DATA_MODE
SRAM_INIT_EN
Reserved
Reserved
BOOT
ADDR_
Reserved Reserved
MODE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
NUM_LOOP Reserved NUM_WAIT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_NCFGR field descriptions
Field Description
0 NAND flash auto-boot load mode:
BOOT
During system boot from NAND flash, this bit remains set to alter the use of the FCM buffer RAM.
Software should clear BOOT once FCM is to be restored for normal operation. Setting BOOT without
auto-boot in progress only alters the mapping of the buffer RAM.
0 NAND FCM is operating in normal functional mode, with a 16-KB FCM buffer RAM. In this case
normal SRAM buffer mapping applies.
1 Flash is accessed in boot mode. SRAM buffer mapping gets changed and whole 8 KB NAND flash
main area in the buffer looks as contiguous linear addressable memory region. This bit is set by
hardware when por_cfg_rcw_load or por_cfg_boot_load occurs with NAND as bootable device.
1 This field is reserved.
-
2 SRAM Initialization Enable
SRAM_INIT_EN
This bit is provided to trigger the auto initialization of complete SRAM with FF data. Software must set this
bit before initiating first program operation on NAND post reset. IFC clears this bit after finishing this
operation.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1366 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
IFC_NCFGR field descriptions (continued)
Field Description
After setting this bit to 1, software must poll this bit. Reading back value 0 confirms that IFC hardware has
filled the SRAM and cleared this bit.
0 No auto SRAM Initialization.
1 Triggers the IFC sram initialization logic which fills all sram buffer locations with ‘hFF data
3 This field is reserved.
-
4 This bit is valid only when CSORn[NAND_MODE] is configured as NV-DDR Mode.
SINGLE_DATA_
In case of source synchronous operation the NAND flash repeats a byte of data on both the rising and
MODE
falling edge of the DQS for certain commands, namely GET FEATURES, READ ID. For the SET
FEATURES command, IFC has to repeat each byte of data for the rising and falling edge of DQS.
When this bit is set:
For read operations (GET FEATURES, READ ID), IFC will ignore the repeated bytes of data sent by the
NAND Flash on the falling edge of the DQS for read operations.
For write operations (SET FEATURES), IFC will replicate each byte of data to be written on both rising
and falling edge of DQS.
0 Single data mode disabled
1 Single data mode enabled
5–7 This field is reserved.
-
8–9 Addressing Mode: Applicable for the current active CS. Applicable only with opcodes CA0 and RA0.
ADDR_MODE
Others Reserved
00 ROW0/COL0, ROW0+1/COL0, ROW0+2/COL0 and so on, in each iteration defined by NUM_LOOP
field (Incremental by Page Size)
01 ROW0/COL0 addresses in first iteration, ROW1/COL1 address in second iteration, ROW2/COL2
address in third iteration, ROW3/COL3 address in fourth iteration
10–15 This field is reserved.
-
16–19 Number of loop iterations of FIR sequences for multipage operations
NUM_LOOP
FIR sequence will execute lopping by NUM_LOOP's time.
NOTE: 1 NUM_LOOP value should be programmed carefully as it is restricted by SRAM buffer size. We
support 16-page operation for small page, 4-page operation for large page of size 2 KB and 2-
page operations for 4 KB page size. Hence NUM_LOOP value of 0000-1111 is only valid for
small page; for 2 KB page size NUM_LOOP 0000-0011 are valid values; and for 4-KB page size
NUM_LOOP value 0000 and 0001 are valid.
NOTE: 2 For ADDR_MODE = 01, NUM_LOOP should not exceed 4.
NOTE: 3 Ensure that separate SRAM buffers should be allocated during consecutive runs of
NUM_LOOP else the data from the previous iteration will be overwritten and produce incorrect
results.
0000 1 time execution of FIR sequence
0001 2 time execution of FIR sequence
0010 3 time execution of FIR sequence
0011 4 time execution of FIR sequence
0100 5 time execution of FIR sequence
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1367
IFC memory map/register definition
IFC_NCFGR field descriptions (continued)
Field Description
0101 6 time execution of FIR sequence
0110 7 time execution of FIR sequence
0111 8 time execution of FIR sequence
1000 9 time execution of FIR sequence
1001 10 time execution of FIR sequence
1010 11 time execution of FIR sequence
1011 12 time execution of FIR sequence
1100 13 time execution of FIR sequence
1101 14 time execution of FIR sequence
1110 15 time execution of FIR sequence
1111 16 time execution of FIR sequence
20–23 This field is reserved.
-
24–31 Number of wait cycles
NUM_WAIT
It represents the count value for which FCM will wait when used with opcode NWAIT in FIR. The value
specified in this register represents the number of IFC module input clock cycles. Minimum value to be
programmed is 2.
25.3.36 NAND Flash Command register 0 (IFC_NAND_FCR0)
The NAND flash command registers hold up to 8 NAND flash EEPROM command bytes
that may be referenced by opcodes in NAND_FIR during FCM operation. The values of
the commands should follow the manufacturer's datasheet for the relevant NAND flash.
Address: 153_0000h base + 1014h offset = 153_1014h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
CMD0 CMD1 CMD2 CMD3
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_NAND_FCR0 field descriptions
Field Description
0–7 General purpose FCM flash command byte 0. Opcodes in FIR that issue command index 0 write CMD0 to
CMD0 the NAND flash command/data bus.
8–15 General purpose FCM flash command byte 1. Opcodes in FIR that issue command index 1 write CMD1 to
CMD1 the NAND flash command/data bus.
16–23 General purpose FCM flash command byte 2. Opcodes in FIR that issue command index 2 write CMD2 to
CMD2 the NAND flash command/data bus.
24–31 General purpose FCM flash command byte 3. Opcodes in FIR that issue command index 3 write CMD3 to
CMD3 the NAND flash command/data bus
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1368 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
25.3.37 NAND Flash Command register 1 (IFC_NAND_FCR1)
Address: 153_0000h base + 1018h offset = 153_1018h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
CMD4 CMD5 CMD6 CMD7
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_NAND_FCR1 field descriptions
Field Description
0–7 General purpose FCM flash command byte 4. Opcodes in FIR that issue command index 4 write CMD4 to
CMD4 the NAND flash command/data bus.
8–15 General purpose FCM flash command byte 5. Opcodes in FIR that issue command index 5write CMD5 to
CMD5 the NAND flash command/data bus.
16–23 General purpose FCM flash command byte 6. Opcodes in FIR that issue command index 6 write CMD6 to
CMD6 the NAND flash command/data bus.
24–31 General purpose FCM flash command byte 7. Opcodes in FIR that issue command index 7 write CMD7 to
CMD7 the NAND flash command/data bus
25.3.38 Flash Row Address register n (IFC_ROWn)
ROWn registers are used for addressing the NAND flash memory. These registers are
used as per the field NCFGR1[ADDR_MODE]. ROWn register holds the row address to
be issued on NAND flash interface using address phase. CSORn[RAL] field determines
the number of bits to be issued to the flash from ROW register during row address phase.
Address: 153_0000h base + 103Ch offset + (16d × i), where i=0d to 3d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
RA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_ROWn field descriptions
Field Description
0–31 Row Address
RA
This register holds the row address to be issued on flash during row address phase
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1369
IFC memory map/register definition
25.3.39 Flash COL Address register n (IFC_COLn)
COLn registers are used for addressing the NAND FLASH memory. These registers are
used as per the field NCFGR1[ADDR_MODE]. The following holds the column address
to be issued to flash during address phase. CSORn[PGS] field determines the number of
bits to be issued to flash from COL register during column address phase.
For small-page size, that is, 512 Bytes, the four lsbs of ROWn register is used to select
the IFC buffer for data transfer to/from IFC buffer to/from flash. It indexes the page in
NAND flash EEPROM at the current block, and locates the corresponding transfer buffer
in the FCM buffer RAM.
The four lsbs of RA index, 1 of the 16, 1-KB buffers in the FCM buffer RAM as follows:
• 0000-The page is transferred to/from FCM buffer 0, address offsets 0x0000-0x03FF
• 0001-The page is transferred to/from FCM buffer 1, address offsets 0x0400-0x07FF
• 0010-The page is transferred to/from FCM buffer 2, address offsets 0x0800-0x0BFF
• 0011-The page is transferred to/from FCM buffer 3, address offsets 0x0C00-0x0FFF
• 0100-The page is transferred to/from FCM buffer 4, address offsets 0x1000-0x13FF
• 0101-The page is transferred to/from FCM buffer 5, address offsets 0x1400-0x17FF
• 0110-The page is transferred to/from FCM buffer 6, address offsets 0x1800-0x1BFF
• 0111-The page is transferred to/from FCM buffer 7, address offsets 0x1C00-0x1FFF
• 1000-The page is transferred to/from FCM buffer 8, address offsets 0x2000-0x23FF
• 1001-The page is transferred to/from FCM buffer 9, address offsets 0x2400-0x27FF
• 1010-The page is transferred to/from FCM buffer 10, address offsets
0x2800-0x2BFF
• 1011-The page is transferred to/from FCM buffer 11, address offsets
0x2C00-0x2FFF
• 1100-The page is transferred to/from FCM buffer 12, address offsets 0x3000-0x33FF
• 1101-The page is transferred to/from FCM buffer 13, address offsets 0x3400-0x37FF
• 1110-The page is transferred to/from FCM buffer 14, address offsets
0x3800-0x3BFF
• 1111-The page is transferred to/from FCM buffer 15, address offsets
0x3C00-0x3FFF
Address: 153_0000h base + 1044h offset + (16d × i), where i=0d to 3d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
W
MS Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
Reserved CA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1370 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
IFC_COLn field descriptions
Field Description
0 Main/spare region locator.:
MS
NOTE: In the case that NAND_BC[BC] = 0, MS is treated as 0.
0 Data is transferred to/from the main region of the SRAM buffer; that is, the first 512 bytes of the buffer
are used.
1 Data is transferred to/from the spare region of the SRAM buffer; that is, the second 512 bytes of the
buffer are used, but only an initial 16 bytes of spare region are defined.
1–18 This field is reserved.
-
19–31 Column Address
CA
This register holds the column address to be issued on flash during column address phase.
CA indexes the first byte to transfer to/from the main or spare region of the NAND flash EEPROM and
corresponding transfer buffer. In the case that NAND_BC[BC] = 0, CA is treated as 0.
For MS = 0, CA can range 0x0000-0x1FF; for MS = 1, CA can range 0x000-0x00F.
For a 16-bit port size, the least significant bit of the Column Address is assumed to be zero; hence, the
Column Address remains a byte index at all times.
25.3.40 Flash COL Address register for 2 KB Large-Page Device
(IFC_COLn_2KB)
For large-page size of 2 KB, two lsbs of ROWn register are used to select the IFC buffer
for data transfer to/from IFC buffer to/from flash. It indexes the page in NAND flash
EEPROM at the current block, and locates the corresponding transfer buffer in the FCM
buffer RAM.
The two lsbs of RA index one of the four 4-KB buffers in the FCM buffer RAM as
follows:
• 00-The page is transferred to/from FCM buffer 0, address offsets 0x0000-0x0FFF
• 01-The page is transferred to/from FCM buffer 1, address offsets 0x1000-0x1FFF
• 10-The page is transferred to/from FCM buffer 2, address offsets 0x2000-0x2FFF
• 11-The page is transferred to/from FCM buffer 3, address offsets 0x3000-0x3FFF
Address: 153_0000h base + 1044h offset + (16d × i), where i=0d to 3d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
W
MS Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
Reserved CA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1371
IFC memory map/register definition
IFC_COLn_2KB field descriptions
Field Description
0 Main/spare region locator. In the case that NAND_BC[BC] = 0, MS is treated as 0.
MS
0 Data is transferred to/from the main region of the SRAM buffer; that is, the first 2048 bytes of the
buffer are used.
1 Data is transferred to/from the spare region of the SRAM buffer; that is, the second 2048 bytes of the
buffer are used, but only an initial 64 bytes of spare region are defined.
1–18 This field is reserved.
-
19–31 Column Address
CA
This register holds the column address to be issued on flash during column address phase.
CA indexes the first byte to transfer to/from the main or spare region of the NAND flash EEPROM and
corresponding transfer buffer. In the case that NAND_BC[BC] = 0, CA is treated as 0.
For MS = 0, CA can range 0x000-0x7FF; for MS = 1, CA can range 0x000-0x03F.
For a 16-bit port size, the least significant bit of the Column Address is assumed to be zero; hence, the
Column Address remains a byte index at all times.
25.3.41 Flash COL Address register for 4 KB Large-Page Device
(IFC_COLn_4KB)
For large-page size of 4 KB, lsb of ROWn register is used to select the IFC buffer for
data transfer to/from IFC buffer to/from flash. It indexes the page in NAND flash
EEPROM at the current block, and locates the corresponding transfer buffer in the FCM
buffer RAM.
The lsb of RA indexes one of the two 8 KB buffers in the FCM buffer RAM as follows:
• 0-The page is transferred to/from FCM buffer 0, address offsets 0x0000-0x1FFF
• 1-The page is transferred to/from FCM buffer 1, address offsets 0x2000-0x3FFF
Address: 153_0000h base + 1044h offset + (16d × i), where i=0d to 3d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
W
MS Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
Reserved CA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_COLn_4KB field descriptions
Field Description
0 Main/spare region locator. In the case that NAND_BC[BC] = 0, MS is treated as 0.
MS
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1372 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
IFC_COLn_4KB field descriptions (continued)
Field Description
0 Data is transferred to/from the main region of the SRAM buffer; that is, the first 4096 bytes of the
buffer are used.
1 Data is transferred to/from the spare region of the SRAM buffer; that is, the second 4096 bytes of the
buffer are used, but only an initial 64 bytes of spare region are defined.
1–18 This field is reserved.
-
19–31 Column Address
CA
This register holds the column address to be issued on flash during column address phase.
CA indexes the first byte to transfer to/from the main or spare region of the NAND flash EEPROM and
corresponding transfer buffer. In the case that NAND_BC[BC] = 0, COL is treated as 0. For MS = 0, CA
can range 0x000-0xFFF; for MS = 1, CA can range 0x000- CSORn[SPRZ].
For a 16-bit port size, the least significant bit of the Column Address is assumed to be zero; hence, the
Column Address remains a byte index at all times.
25.3.42 Flash COL Address register for 8 KB Large-Page Device
(IFC_COLn_8KB)
For large-page size of 8 KB, lsb of ROWn register is used to select the IFC buffer for
data transfer to/from IFC buffer to/from flash. It indexes the page in NAND flash
EEPROM at the current block, and locates the corresponding transfer buffer in the FCM
buffer RAM.
The lsb of RA indexes one of the two 8 KB buffers in the FCM buffer RAM as follows:
• 0-The page is transferred to/from FCM buffer 0, address offsets 0x0000-0x1FFF
• 1-The page is transferred to/from FCM buffer 1, address offsets 0x2000-0x3FFF
• Only single 8 KB page can be accessed using SRAM buffer.
Address: 153_0000h base + 1044h offset + (16d × i), where i=0d to 3d
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
W
MS Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
Reserved CA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_COLn_8KB field descriptions
Field Description
0 Main/spare region locator. In the case that NAND_BC[BC] = 0, MS is treated as 0.
MS
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1373
IFC memory map/register definition
IFC_COLn_8KB field descriptions (continued)
Field Description
0 Data is transferred to/from the main region of the SRAM buffer; that is, the first 4096 bytes of the
buffer are used.
1 Data is transferred to/from the spare region of the SRAM buffer; that is, the second 8192 bytes of the
buffer are used, but only an initial CSOR[SPRZ] bytes of spare region are defined. Maximum
addressable bytes in sprae region buffer are 1024 bytes with this page size.
1–18 This field is reserved.
-
19–31 Column Address
CA
This register holds the column address to be issued on Flash during column address phase. CA indexes
the first byte to transfer to/from the main or spare region of the NAND flash E2PROM and corresponding
transfer buffer. In the case that NAND_BC[BC] = 0, COL is treated as 0. For MS = 0, CA can range
0x000-0x1FFF; for MS = 1, CA can range 0x000- CSOR[SPRZ]. For a 16 bit port size or a NVDDR device
the least significant bit of the column address is assumed to be zero, hence, the column address remains
a byte index at all times.
25.3.43 Flash Byte Count register for NAND Flash (IFC_NAND_BC)
This register defines the NAND flash data block transfer size.
Address: 153_0000h base + 1108h offset = 153_1108h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
Reserved BC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_NAND_BC field descriptions
Field Description
0–17 This field is reserved.
-
18–31 Byte count determines how many bytes are transferred by the flash controller during data read (RBCD) or
BC data write (WBCD) opcodes. In case of partial page operations, the value programmed in this field must
be aligned to the port size of the device. Thus, if the bank port size is 16 bits, the lsb bit of BC (that is, bit
31) is ignored.
The first byte accessed in the NAND flash is located by the COLn register, and successive bytes are
transferred until BC bytes have been counted
If BC = 0, an entire flash page and its spare region will be transferred by FCM, in which case COLn[MS]
and COLn[CA] are treated as zero regardless of their values.
NOTE: BC = 0 is the only setting that permits flash controller to generate and check ECC.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1374 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
25.3.44 NAND Flash Instruction register 0 (IFC_NAND_FIR0)
The following flash instruction registers hold the instructions. When any operation on a
selected bank is triggered and the FIR is programmed by the user, flash controller
executes 6-bit opcode at a time until all the opcodes have been fetched from all the FIR
registers. There are three such registers provided for the application. A total of 15
instructions can be programmed for FLASH operations.
NAND flash instruction register0 holds first five opcodes.
Table 25-5. Instruction Opcodes
Opcode encoding (6 Opcode name Description
bits)
0x00 NOOP No-operation and end of operation sequence
0x01 CA0 Issue current column address (CA) as set in COL0
0x02 CA1 Issue current column address as set in COL1
0x03 CA2 Issue current column address as set in COL2
0x04 CA3 Issue current column address as set in COL3
0x05 RA0 Issue current row address as set in ROW0
0x06 RA1 Issue current row address as set in ROW1
0x07 RA2 Issue current row address as set in ROW2
0x08 RA3 Issue current row address as set in ROW3
0x09 CMD0 Issue command from NAND_FCR0[CMD0]
0x0A CMD1 Issue command from NAND_FCR0[CMD1]
0x0B CMD2 Issue command from NAND_FCR0[CMD2]
0x0C CMD3 Issue command from NAND_FCR0[CMD3]
0x0D CMD4 Issue command from NAND_FCR1[CMD4]
0x0E CMD5 Issue command from NAND_FCR1[CMD5]
0x0F CMD6 Issue command from NAND_FCR1[CMD6]
0x10 CMD7 Issue command from NAND_FCR1[CMD7]
0x11 CW0 Wait for TWBE time, poll R/B to return high or time-out (depends upon
IFC_NANDCR[FTOCNT]), then issue command from
NAND_FCR0[CMD0]
0x12 CW1 Wait for TWBE time, poll R/B to return high or time-out (depends upon
IFC_NANDCR[FTOCNT]), then issue command from
NAND_FCR0[CMD1]
0x13 CW2 Wait for TWBE time, poll R/B to return high or time-out (depends upon
IFC_NANDCR[FTOCNT]), then issue command from
NAND_FCR0[CMD2]
0x14 CW3 Wait for TWBE time, poll R/B to return high or time-out (depends upon
IFC_NANDCR[FTOCNT]), then issue command from
NAND_FCR0[CMD3]
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1375
IFC memory map/register definition
Table 25-5. Instruction Opcodes (continued)
Opcode encoding (6 Opcode name Description
bits)
0x15 CW4 Wait for TWBE time, poll R/B to return high or time-out (depends upon
IFC_NANDCR[FTOCNT]), then issue command from
NAND_FCR1[CMD4]
0x16 CW5 Wait for TWBE time, poll R/B to return high or time-out (depends upon
IFC_NANDCR[FTOCNT]), then issue command from
NAND_FCR1[CMD5]
0x17 CW6 Wait for TWBE time, poll R/B to return high or time-out (depends upon
IFC_NANDCR[FTOCNT]), then issue command from
NAND_FCR1[CMD6]
0x18 CW7 Wait for TWBE time, poll R/B to return high or time-out (depends upon
IFC_NANDCR[FTOCNT]), then issue command from
NAND_FCR1[CMD7]
0x19 WBCD Write BC bytes of data from current FCM buffer to flash device
0x1A RBCD Wait for R/B_B to return high or time-out (depends upon
IFC_NANDCR[FTOCNT]), then Read BC bytes of data from flash device
into current FCM RAM buffer
0x1B BTRD Same as RBCD except in this case deassertion of read enable will happen
once the read data has been sampled (same as boot read)
0x1C RDSTAT Wait for TWHR (for NVDDR)/TWHRE (Async) time, then Read one
byte/two bytes (8b/16b port) of data from flash device into RS0 and RS1
field of FSR.
0x1D NWAIT Wait for NCFGR[NUM_WAIT] Clock cycles
0x1E WFR Wait for TWBE time, poll Ready
0x1F SBRD Wait for R/B to return high or time-out (depends upon
IFC_NANDCR[FTOCNT]), then Read 8/16 bits of data from NAND flash
memory into the NAND_MDR register. COLn register will determine the
location from where the data will be fetched in a given page.
Deassertion of read enable will happen once the read data has been
sampled.
With this opcode NAND_BC register field value will be ignored. Although
the value is ignored, it is mandatory that the NAND_BC register hold a
non-zero value else the Column Address would be treated as 0 (refer
Flash COL Address register n (IFC_COLn) )
0x20 UA Issue current row address as set in ROW3
The SRAM Buffer used for data transfers is always Buffer 0
0x21 RB Wait for TWHR (for NVDDR)/TWHRE (Async) time, then Read BC bytes of
data from flash device into current FCM RAM buffer. Deassertion of read
enable will happen once the read data has been sampled
Others - Reserved
Address: 153_0000h base + 1110h offset = 153_1110h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
W
OP0 OP1 OP2
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1376 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
OP2 OP3 OP4 Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_NAND_FIR0 field descriptions
Field Description
0–5 Opcode0
OP0
6–11 Opcode1
OP1
12–17 Opcode2
OP2
18–23 Opcode3
OP3
24–29 Opcode4
OP4
30–31 This field is reserved.
-
25.3.45 NAND Flash Instruction register 1 (IFC_NAND_FIR1)
NAND flash instruction register1 holds other five opcodes.
Address: 153_0000h base + 1114h offset = 153_1114h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
W
OP5 OP6 OP7
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
OP7 OP8 OP9 Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_NAND_FIR1 field descriptions
Field Description
0–5 Opcode5
OP5
6–11 Opcode6
OP6
12–17 Opcode7
OP7
18–23 Opcode8
OP8
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1377
IFC memory map/register definition
IFC_NAND_FIR1 field descriptions (continued)
Field Description
24–29 Opcode9
OP9
30–31 This field is reserved.
-
25.3.46 NAND Flash Instruction register 2 (IFC_NAND_FIR2)
NAND flash instruction register2 holds last five opcodes.
Address: 153_0000h base + 1118h offset = 153_1118h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
W
OP10 OP11 OP12
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
OP12 OP13 OP14 Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_NAND_FIR2 field descriptions
Field Description
0–5 Opcode10
OP10
6–11 Opcode11
OP11
12–17 Opcode12
OP12
18–23 Opcode13
OP13
24–29 Opcode14
OP14
30–31 This field is reserved.
-
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1378 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
25.3.47 NAND Chip-Select register (IFC_NAND_CSEL)
This register tells the NAND FCM about the selected chip-select on which a program or
read operation has to be performed. As NAND flash is accessed through an SRAM buffer
(memory-mapped), software tells the NAND FCM which chip-select is desired using this
register.
Address: 153_0000h base + 115Ch offset = 153_115Ch
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
Reserved CSEL Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_NAND_CSEL field descriptions
Field Description
0–2 This field is reserved.
-
3–5 Chip-Select for NAND flash operation
CSEL
000 Chip-select0
001 Chip-select1
010 Chip-select2
011 Chip-select3
...
110 Chip select6
111 Reserved
6–31 This field is reserved.
-
25.3.48 NAND Operation Sequence Start (IFC_NANDSEQ_STRT)
This register is used to trigger the operation on NAND flash.
The following figure shows the NANDSEQ_STRT register. Only one operation can be
triggered at a time. Software has to trigger the operation and the chip will clear this after
completing the operation.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1379
IFC memory map/register definition
Address: 153_0000h base + 1164h offset = 153_1164h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
AUTO_PGM
NAND_FIR_
R
AUTO_ERS
AUTO_CPB
STRT
Reserv
Reserved Reserved Reserved
ed
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
AUTO_STAT_RD
R
AUTO_RD
Reserv
Reserved Reserved
ed
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_NANDSEQ_STRT field descriptions
Field Description
0 NAND flash operation start
NAND_FIR_
Writing 1 to this register bit triggers normal operation sequence programmed in NAND FIR registers on
STRT
NAND flash.
1–7 This field is reserved.
-
8 Automatic erase
AUTO_ERS
Writing 1 to this register bit triggers automatic erase operation
NOTE: The FIR sequence executed is {CW0, RA0, CMD1, and NOOP}
9–10 This field is reserved.
-
11 Automatic program
AUTO_PGM
Writing 1 to this register bit triggers automatic program operation
NOTE: The FIR sequence executed is {CW0, CA0, RA0, WBCD, CMD1, and NOOP}. This sequence will
not support small page program, hence user cannot use auto program for small page device.
12–13 This field is reserved.
-
14 Automatic copyback
AUTO_CPB
Writing 1 to this register bit triggers automatic copy back operation
NOTE: The FIR sequence executed is {CW0, CA0, RA0, CMD1, CW2, CA1, RA1, CMD3, CW4,
RDSTAT, and NOOP}
15–16 This field is reserved.
-
17 Automatic read operation
AUTO_RD
Writing 1 to this register bit triggers automatic read operation
NOTE: The FIR sequence executed is:
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1380 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
IFC_NANDSEQ_STRT field descriptions (continued)
Field Description
For small-page device: {CW0, CA0, RA0, RBCD, NOOP}
For large-page device: {CW0, CA0, RA0, CMD1, RBCD, NOOP}
18–19 This field is reserved.
-
20 Automatic status read
AUTO_STAT_RD
Writing 1 to this register bit triggers automatic read status
NOTE: The FIR sequence executed is {CW0, RDSTAT, NOOP}
21–31 This field is reserved.
-
25.3.49 NAND Event and Error Status register
(IFC_NAND_EVTER_STAT)
NAND event and error status register (NAND_EVTER_STAT) indicates the cause of an
error or event corresponding to NAND flash.
The following figure shows the register fields. It is write-1-to-clear register.
Address: 153_0000h base + 116Ch offset = 153_116Ch
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
ECCER
FTOER
WPER
OPC
Reserved Reserved
W w1c w1c w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1381
IFC memory map/register definition
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
BBI_SRCH_SEL
BOOT_DN
RCW_DN
R
Reserved Reserved
W w1c w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_NAND_EVTER_STAT field descriptions
Field Description
0 NAND flash operation complete event. OPC indicates that all instructions in FIR has been executed.
OPC
NOTE: 1. The software should not poll this bit during auto boot. Instead RCW_DN/ BOOT_DN should be
used. However, software must clear this bit post auto boot.
NOTE: 2. This bit is set even if a flash timeout, ECC or write protect error occurs. For example, if a flash
timeout error is detected for a read operation intiated on the NAND flash memory device, IFC will
dump BC bytes worth of garbage data from the NAND flash interface into the internal SRAM and
set this bit. Similarly, in case of NAND write protect error, IFC asserts chip select and sends the
program data to NAND device, it is device which ignores the data as write protect signal is
asserted. User must wait for operation completion (poll for OPC bit getting set) even in case of
timeout before initiating next operation.
As the transaction goes into NAND, OPC will be set at the end of FIR execution. OPC bit indicates that all
the instructions in the FIRs have been executed. Also, it implies that OPC should be polled first and then
FSR for completion.
0 NAND flash operation is not complete
1 NAND flash operation completed
1–3 This field is reserved.
-
4 Flash timeout error
FTOER
0 No flash interface timeout
1 Flash interface timeout occured
5 Write protect error
WPER
NOTE: Error is asserted when the write operation starts executing on the flash interface.
0 No write protect error
1 A write is attempted to the memory bank which is write protected
6 ECC error
ECCER
NOTE: With the clearing of this error status bit, the ECCSTAT0/1/2/3 register contents will also be
cleared.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1382 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
IFC_NAND_EVTER_STAT field descriptions (continued)
Field Description
0 No uncorrectable ECC Error occured on page read operation
1 Uncorrectable ECC error occured in page read operation
7–15 This field is reserved.
-
16 This bit is set when one flash page has been read from the flash device and written into the SRAM buffer
RCW_DN during RCW load. It is write-1-to-clear bit and can be cleared by software after RCW loading. This event
does not have any corresponding event enable and interrupt enable bit.
17 This event is set when 8 KB flash data has been read from the flash device and written into the SRAM
BOOT_DN buffer during BOOT load. It is write-1-to-clear bit and can be cleared by software after BOOT loading. This
events will not have any corresponding event enable and interrupt enable bit.
18–19 This field is reserved.
-
20 Bad Block Indicator search select: This status register bit represents the location of bad block indication in
BBI_SRCH_SEL each block of NAND flash device connected at chip-select0. This field will be updated with input port value
por_cfg_bbi_srch_sel when por_cfg_boot_load /por_cfg_rcw_load pulse occurs.
0 Read bad block indicator (BBI) corresponding to page0 and page1 of each block of the NAND flash
device connected at chipselect 0, to identify the first good block during auto-boot
1 Read bad block indicator (BBI) corresponding to page0 and the last page of each block of the NAND
flash device connected at chipselect 0, to identify the first good block during auto-boot
21–31 This field is reserved.
-
25.3.50 NAND Page Read Completion Event Status register
(IFC_PGRDCMPL_EVT_STAT)
NAND flash page read completion event register indicates the status of the pages read
from NAND flash and stored in SRAM buffer. 16 bits of this register represent 16 sectors
each of 512 bytes (used in ECC decoding). There can be 1, 4, 8, and 16 sectors in each
page of size 512 bytes, 2 KB, 4 KB, and 8 KB . Event interrupt will be generated if one
complete page has been written in SRAM buffer (when ecc_dec_en = 0) or when one
complete page has been fixed in the SRAM after decoding (ecc_dec_en = 1). Software
can read the corresponding page whose data has been completely written in SRAM (ECC
fixed) and clear the corresponding bits in this register.
24/40-bit ECC is computed on 1 KB sector and applicable for 4 KB and 8 KB page sizes.
However the definition of this register remains same except the fact that 512 is the byte
size and not the sector size.
NOTE
The register gets cleared when software clears the OPC bit in
NAND_EVTER_STAT register. Even if per page event
interrupt is used for reading the data from SRAM,
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1383
IFC memory map/register definition
NAND_EVTER_STAT[OPC] is the true indication of NAND
operation completion.
The following figure shows the register fields. It is write-1-to-clear register.
Address: 153_0000h base + 1174h offset = 153_1174h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R SEC_DONE
Reserved
W w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_PGRDCMPL_EVT_STAT field descriptions
Field Description
0–15 For small page: Each of the 16 bits of this field represent one small page read data completion status
SEC_DONE
Bit 0 set-Page 0 done, that is, flash read data is completely written and fixed in SRAM buffer
Bit 1 set-Page 1 done
Bit 2 set-Page 2 done
Bit 3 set-Page 3 done
...
Bit15 Set-Page 15 done
For 2KB Page: SRAM buffer can accommodate 4 page (2KB) each containing four 512 byte sectors
SEC_DONE[0:3] = 4'b1111: Page 0 done
SEC_DONE[4:7] = 4'b1111: Page 1 done
SEC_DONE[8:11] = 4'b1111: Page 2 done
SEC_DONE[12:15] = 4'b1111: Page 3 done
For 4KB Page: SRAM buffer can accommodate 2 page (4KB) each containing eight 512 byte sectors
SEC_DONE[0:7] = 8'b1111_1111: Page 0 done
SEC_DONE[8:15] = 8'b1111_1111: Page 1 done
For 8KB Page: Only one page can be buffered in SRAM.
SEC_DONE[0:15] = 16'b 1111_1111_1111_1111: Single page of 8KB done.
NOTE: Event interrupt will be generated when one complete page read is done. Software has to read the
corresponding page from SRAM buffer and clear the bits from this register. For example if page
size is 2 KB and page 0 is being written in SRAM buffer, then SEC_DONE[0:15] will be
16'HF000, now software has to write the data 16'HF000 in this register to clear it.
16–31 This field is reserved.
-
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1384 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
25.3.51 NAND Event and Error Enable register
(IFC_NAND_EVTER_EN)
Event and Error Enable Register (NAND_EVTER_EN) is used to enable/disable the
logging of event and error indication in the NAND_EVTER_STAT and
PGRDCMPL_EVT_STAT registers.
Address: 153_0000h base + 1180h offset = 153_1180h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
PGRDCMPLEN
ECCEREN
FTOEREN
WPEREN
Reserved
Reserved
OPCEN
Reserved
Reset 1 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_NAND_EVTER_EN field descriptions
Field Description
0 NAND flash operation complete event enable
OPCEN
0 NAND flash operation complete event is disabled
1 NAND flash operation completed event is enabled
1 This field is reserved.
-
2 NAND flash page read completion event enable
PGRDCMPLEN
0 Per page read event disable
1 Event will be generated on per page flash read operation completion. Status about the page whose
data is available in sram buffer is given by PGRDCMPL_EVT_STAT register.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1385
IFC memory map/register definition
IFC_NAND_EVTER_EN field descriptions (continued)
Field Description
3 This field is reserved.
-
4 Flash time out error enable (for R/B timeoutand DQS timeout)
FTOEREN
0 Flash timeout error is disabled
1 Flash timeout error is enabled
5 Write protect error checking enable.
WPEREN
0 No write protect error checking
1 Write protect error checking is enabled
6 ECC error logging enable.
ECCEREN
0 ECCER event is not logged in NAND_EVTER_STAT register
1 ECCER event is logged in NAND_EVTER_STAT register
7–31 This field is reserved.
-
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1386 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
25.3.52 NAND Event and Error Interrupt Enable register
(IFC_NAND_EVTER_INTR_EN)
Event and Error Interrupt Enable Register (NAND_EVTER_INTR_EN) is used to
enable/disable the generation of interrupt signals corresponding to error and event
reporting. Software must clear pending events and errors in NAND_EVTER_STAT and
PGRDCMPL_EVT_STAT register before enabling the interrupts.
Address: 153_0000h base + 118Ch offset = 153_118Ch
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PGRDCMPLIREN
R ECCERIREN
FTOERIREN
WPERIREN
OPCIREN
Reserved
Reserved
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_NAND_EVTER_INTR_EN field descriptions
Field Description
0 NAND flash operation complete event interrupt enable
OPCIREN
0 NAND flash operation Complete Event Interrupt is disabled
1 NAND flash operation completed Event Interrupt is Enabled
1 This field is reserved.
-
2 Page read completion event interrupt enable
PGRDCMPLIREN
0 NAND flash page read event interrupt is disabled (per page basis)
1 NAND flash page read event interrupt is enabled
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1387
IFC memory map/register definition
IFC_NAND_EVTER_INTR_EN field descriptions (continued)
Field Description
3 This field is reserved.
-
4 Flash timeout error interrupt enable (for R/B timeoutand DQS timeout)
FTOERIREN
0 Flash timeout error interrupt is disabled
1 Flash timeout error interrupt is enabled
5 Write protect error interrupt enable
WPERIREN
0 Write protect error interrupt disable
1 Write protect error interrupt is enabled
6 ECC error interrupt enable
ECCERIREN
0 ECC Error Interrupt is disabled
1 ECC Error Interrupt is enabled
7–31 This field is reserved.
-
25.3.53 NAND Transfer Error Attributes register 0
(IFC_NAND_ERATTR0)
Transfer error attribute register 0 (NAND_ERATTR0) is used to register the transaction
attributes corresponding to the first error.
These registers store the attribute corresponding to the first transaction on which an error
occured.
Address: 153_0000h base + 1198h offset = 153_1198h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
ERTTYPE
R ERCS
Reserved Reserved Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1388 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_NAND_ERATTR0 field descriptions
Field Description
0–2 This field is reserved.
-
3–5 Chip-Select Corresponding to NAND Error
ERCS
000 Bank0
001 Bank1
010 Bank2
...
111 Reserved
6–11 This field is reserved.
-
12 Transaction type of NAND error
ERTTYPE
0 Write
1 Read
13–31 This field is reserved.
-
25.3.54 NAND Transfer Error Attributes register 1
(IFC_NAND_ERATTR1)
Transfer error attribute register (NAND_ERATTR1) is used to register the transaction
address corresponding to the first error.
Address: 153_0000h base + 119Ch offset = 153_119Ch
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R ER_ROWAD
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1389
IFC memory map/register definition
IFC_NAND_ERATTR1 field descriptions
Field Description
0–31 Row address corresponding to error transaction
ER_ROWAD
25.3.55 NAND Flash Status register (IFC_NAND_FSR)
Flash status register (NAND_FSR) contains read status data from NAND flash.
Address: 153_0000h base + 11E0h offset = 153_11E0h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R RS0 RS1
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_NAND_FSR field descriptions
Field Description
0–7 First byte of data read from read status operation
RS0
8–15 Second byte of data read from read status operation
RS1
16–31 This field is reserved.
-
25.3.56 ECC Status and Result of Flash Operation register 0
(IFC_ECCSTAT0)
ECC status registers are used to store the number of ECC errors occured on read
operation. It has different meanings for 4/8 and 24/40 bit ECC Modes as the sector size is
different for 4/8 and 24/40 bit modes.
ECC is computed on sector basis, and in the SRAM buffer there can be 16 such sectors of
512 byte each for 4 and 8 bit ECC (Galois field GF-2 13 ) and 8 sectors of 1 KB each for
24 and 40 bit ECC (Galois Field 2 14). Hence, each field of these registers represents
number of errors in each sector. Depending on the page index mapped in the SRAM
buffer, the corresponding field in the ECCSTAT0 will be updated.
As SRAM buffer can have 8 sectors of 1KB each, only the first eight register fields in
ECCSTAT0/1 registers are defined with width 6 to represent 24 and 40 bit ECC along
with 4 and 8 bit ECC.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1390 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
NOTE
1. These registers will be updated whenever decoder is enable
(ECC_DEC_EN =1’b1) irrespective of ECC Error Event
Indication is enabled or not (ECCEREN).
2. With the clearing of NAND_EVTER_STAT[ECCER]
register bit the contents of ECCSTAT0/1/2/3 registers will
also be cleared. These registers will also be cleared with
soft_reset.
3. For every NAND sequence start, all the ECCSTAT
registers will be cleared. It is implemented in order to flush
the previously logged information.
Address: 153_0000h base + 11E8h offset = 153_11E8h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R NUMER0 NUMER1
Reserved Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R NUMER2 NUMER3
Reserved Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_ECCSTAT0 field descriptions
Field Description
0–1 This field is reserved.
-
2–7 Number of ECC errors on sector #0 of SRAM buffer
NUMER0
For 4/8 bit ECC Mode (512 byte sector):
000000 No Error
000001 1 Bit Error
000010 2 Bit Error
000011 3 bit Error
000100 4 Bit Error
000101 5 Bit Error
000110 6 Bit Error
000111 7 BIt Error
001000 8 Bit Error
001111 - Uncorrectable Errors
Others Reserve
For 24/40 bit ECC Mode (1KB sector):
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1391
IFC memory map/register definition
IFC_ECCSTAT0 field descriptions (continued)
Field Description
000000 No Error
000001 - 101000 1 Bit Error to 40 bit Error in this sector
111111 Uncorrectable Errors
Others Reserve
8–9 This field is reserved.
-
10–15 Number of ECC errors on sector #1 of SRAM buffer
NUMER1
16–17 This field is reserved.
-
18–23 Number of ECC errors on sector #2 of SRAM buffer
NUMER2
24–25 This field is reserved.
-
26–31 Number of ECC errors on sector #3 of SRAM buffer
NUMER3
25.3.57 ECC Status and Result of Flash Operation register 1
(IFC_ECCSTAT1)
ECC Status Register (ECCSTAT1) is used to store the number of ECC errors occured on
Sector 4-7 during page read operation.
Address: 153_0000h base + 11ECh offset = 153_11ECh
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R NUMER4 NUMER5
Reserved Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R NUMER6 NUMER7
Reserved Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_ECCSTAT1 field descriptions
Field Description
0–1 This field is reserved.
-
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1392 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
IFC_ECCSTAT1 field descriptions (continued)
Field Description
2–7 Number of ECC errors on sector #4 of SRAM buffer
NUMER4
8–9 This field is reserved.
-
10–15 Number of ECC errors on sector #5 of SRAM buffer
NUMER5
16–17 This field is reserved.
-
18–23 Number of ECC errors on sector #6 of SRAM buffer
NUMER6
24–25 This field is reserved.
-
26–31 Number of ECC errors on sector #7 of SRAM buffer
NUMER7
25.3.58 ECC Status and Result of Flash Operation register 2
(IFC_ECCSTAT2)
ECC Status Register (ECCSTAT1) is used to store the number of ECC errors occured on
Sector 8-11 during page read operation.
Address: 153_0000h base + 11F0h offset = 153_11F0h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R NUMER8 NUMER9 NUMER10 NUMER11
Reserved Reserved Reserved Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_ECCSTAT2 field descriptions
Field Description
0–3 This field is reserved.
-
4–7 Number of ECC errors on sector #8 of SRAM buffer
NUMER8
8–11 This field is reserved.
-
12–15 Number of ECC errors on sector #9 of SRAM buffer
NUMER9
16–19 This field is reserved.
-
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1393
IFC memory map/register definition
IFC_ECCSTAT2 field descriptions (continued)
Field Description
20–23 Number of ECC errors on sector #10 of SRAM buffer
NUMER10
24–27 This field is reserved.
-
28–31 Number of ECC errors on sector #11 of SRAM buffer
NUMER11
25.3.59 ECC Status and Result of Flash Operation register 3
(IFC_ECCSTAT3)
ECC Status Register (ECCSTAT3) is used to store the number of ECC errors occured on
Sector 12-15 during page read operation.
Address: 153_0000h base + 11F4h offset = 153_11F4h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R NUMER12 NUMER13 NUMER14 NUMER15
Reserved Reserved Reserved Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_ECCSTAT3 field descriptions
Field Description
0–3 This field is reserved.
-
4–7 Number of ECC errors on sector #12 of SRAM buffer
NUMER12
8–11 This field is reserved.
-
12–15 Number of ECC errors on sector #13 of SRAM buffer
NUMER13
16–19 This field is reserved.
-
20–23 Number of ECC errors on sector #14 of SRAM buffer
NUMER14
24–27 This field is reserved.
-
28–31 Number of ECC errors on sector #15 of SRAM buffer
NUMER15
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1394 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
25.3.60 NAND Control register (IFC_NANDCR)
Address: 153_0000h base + 1278h offset = 153_1278h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
Reserved FTOCNT Reserved
Reset 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_NANDCR field descriptions
Field Description
0–2 This field is reserved.
-
3–6 Flash timeout count
FTOCNT
0000 256 cycles of IFC module input clock
0001 512 cycles of IFC module input clock
0010 1024 cycles of IFC module input clock
0011 2048 cycles of IFC module input clock
0100 4096 cycles of IFC module input clock
0101 8192 cycles of IFC module input clock
0110 16,384 cycles of IFC module input clock
0111 32,768 cycles of IFC module input clock
1000 65,536 cycles of IFC module input clock
1001 131,072 cycles of IFC module input clock
1010 262,144 cycles of IFC module input clock
1011 524,288 cycles of IFC module input clock
1100 1,048,576 cycles of IFC module input clock
1101 2,097,152 cycles of IFC module input clock
1110 4,194,304 cycles of IFC module input clock
1111 8,388,608 cycles of IFC module input clock
7–31 This field is reserved.
-
25.3.61 NAND Autoboot Trigger register
(IFC_NAND_AUTOBOOT_TRGR)
This register is used to trigger the booting on the NAND flash. This register is provided if
por_cfg_rcw_load and por_cfg_boot_load signals are not coming through the pins for the
booting. The user can use this register to achieve the same boot functionality as described
in NAND asynchronous mode boot mechanism .
It is a self-clearing register; hence, the user just has to write 1 in appropriate field to
trigger the auto-boot operation and hardware will clear it.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1395
IFC memory map/register definition
Address: 153_0000h base + 1284h offset = 153_1284h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0
Reserved
Reserved
BOOT_LD
RCW_LD
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_NAND_AUTOBOOT_TRGR field descriptions
Field Description
0 RCW Load
RCW_LD
NOTE: The values on the various por_cfg pins should be driven valid when this bit is set.
0 No RCW loading
1 Trigger RCW load from NAND flash (same functionality that can be achieved by sending pulse on
por_cfg_rcw_load)
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1396 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
IFC_NAND_AUTOBOOT_TRGR field descriptions (continued)
Field Description
1 This field is reserved.
-
2 BOOT Load
BOOT_LD
NOTE: The values on the various por_cfg pins should be driven valid when this bit is set.
0 No BOOT loading
1 Trigger autoboot loading from NAND flash (same functionality that can be achieved by sending pulse
on por_cfg_boot_load)
3–31 This field is reserved.
-
25.3.62 NAND Flash Memory Data register (IFC_NAND_MDR)
This register is used to store one beat of data read from NAND flash memory when
opcode, "SBRD" is used in the FIR register. This register is provided for reading 1 or 2
bytes of data from 8- or 16-bit NAND flash. The location from where the data gets
fetched can be controlled by column register (COLn ). When NAND FIR is programmed
with opcode "SBRD", IFC always reads 1/2 bytes of data irrespective of the value of BC
(no. of bytes) programmed in NAND_BC register.
Also note that the read data fetched from NAND flash is only stored in this register and
SRAM buffer does not get updated as this opcode is intended for register access only.
Address: 153_0000h base + 128Ch offset = 153_128Ch
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R RDATA0 RDATA1
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_NAND_MDR field descriptions
Field Description
0–7 1st read data byte when opcode SBRD is used for read
RDATA0
8–15 Second read data byte when opcode SBRD is used for read (only valid for 16 bit NAND flash)
RDATA1
16–31 This field is reserved.
-
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1397
IFC memory map/register definition
25.3.63 Nand DLL Low Config 0 Register
(IFC_NAND_DLL_LOW_CFG0)
This registers is used to configure the DLL used to facilitate the shifiting on the incoming
DQS to the centre of the data eye during read operations. This register is used to
configure the DLL for interface frequency upto 133 MHz (based on
CSOR_EXT[MODE_FREQ])
Address: 153_0000h base + 1300h offset = 153_1300h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DLL_ENABLE
DLL_RESET
Reserved
W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_NAND_DLL_LOW_CFG0 field descriptions
Field Description
0 This bit Enables the DLL.
DLL_ENABLE
0 DLL disabled.
1 DLL enabled.
1 This bit resets the DLL. When this bit is set, TAP 0 for both the master and the slave delay lines gets
DLL_RESET selected.
0 DLL is not reset.
1 DLL is reset.
2–31 This field is reserved.
-
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1398 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
25.3.64 Nand DLL Low Config 1 Register
(IFC_NAND_DLL_LOW_CFG1)
This registers is used to configure the DLL used to facilitate shifiting of the incoming
DQS to the centre of the data eye during read operations.This register is used to configure
the DLL for interface frequency upto 133 Mhz (based on CSOR_EXT[MODE_FREQ])
Address: 153_0000h base + 1304h offset = 153_1304h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DLL_PD_PULSE_
STRETCH_SEL
Reserved DLL_REF_UPDATE_INT
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Reserved DLL_SLV_UPDATE_INT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_NAND_DLL_LOW_CFG1 field descriptions
Field Description
0 Used to select between a 2 delay cell or 4 delays cells for reliable detection of pulse width by the pulse
DLL_PD_ width detection logic.
PULSE_
STRETCH_SEL 0 4 delay cell selected.
1 2 delay cell selected.
1–11 This field is reserved.
- Reserved
12–15 This field is used to override the default update interval of the reference delay line. The default value of the
DLL_REF_ update interval is 2 REF_CLK cycles. When this field is programmed, the value of the update interval is 2
UPDATE_INT + DLL_REF_UPDATE_INT
0000 - Update interval value is 2 + 0 REF clock cycles.
0001 - Update interval value is 2 + 1 REF clock cycles.
0010 - Update interval value is 2 + 2 REF clock cycles.
0011 - Update interval value is 2 + 3 REF clock cycles.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1399
IFC memory map/register definition
IFC_NAND_DLL_LOW_CFG1 field descriptions (continued)
Field Description
...
1111 - Update interval value is 2 + 15 REF clock cycles.
16–23 This field is reserved.
- Reserved
24–31 This field is used to override the default update interval of the slave delay line. The default value of the
DLL_SLV_ update interval is 256 REF_CLK cycles. This field is valid only if a non zero value is programmed.
UPDATE_INT
00000000- Update interval value is 256 REF clock cycles.
00000001- Update interval value is 1 REF clock cycles.
00000010- Update interval value is 2 REF clock cycles.
00000011- Update interval value is 3 REF clock cycles.
...
11111111- Update interval value is 255 REF clock cycles.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1400 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
25.3.65 NAND DLL Low Status Register
(IFC_NAND_DLL_LOW_STAT)
This register is used to store the status of the DLL for interface frequency upto 133 MHz
Address: 153_0000h base + 130Ch offset = 153_130Ch
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DLL_STS_REF_LOCK
DLL_STS_SLV_LOCK
R DLL_STS_REF_SEL
Reserved Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R DLL_STS_REF_SEL DLL_STS_SLV_SEL
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1401
IFC memory map/register definition
IFC_NAND_DLL_LOW_STAT field descriptions
Field Description
0 DLL Reference Delay line lock status
DLL_STS_REF_
LOCK
1–3 This field is reserved.
- Reserved
4 DLL Slave Delay Chain lock status
DLL_STS_SLV_
LOCK
5–11 This field is reserved.
- Reserved
12–19 Status of selected tap for reference delay line
DLL_STS_REF_
SEL
20–23 This field is reserved.
- Reserved
24–31 Status of selected tap for slave delay line
DLL_STS_SLV_
SEL
25.3.66 NOR Event and Error Status register
(IFC_NOR_EVTER_STAT)
As with NAND FCM, 1 KB memory-mapped region is allocated for the NOR-specific
registers. This section describes these registers.
NOR event and error status register (NOR_EVTER_STAT) indicates the cause of an
error or event corresponding to NOR flash.
The following figure shows the register fields. It is write-1-to-clear register.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1402 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
Address: 153_0000h base + 1400h offset = 153_1400h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
OPC_NOR
STOER
WPER
R
Reserved
Reserved Reserved
W w1c w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_NOR_EVTER_STAT field descriptions
Field Description
0 NOR Command Sequence Operation Complete Event Indication
OPC_NOR
NOTE: Not valid in case of read operations which do not require a command sequence to be performed
0 NOR Command Sequence Operation not completed
1 Indicates the completion of a Command Sequence performed on the NOR flash device. A command
sequence is said to have completed once all the phases (as indicated in the NORCR[NUM_PHASE])
have been sent to the NOR flash device.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1403
IFC memory map/register definition
IFC_NOR_EVTER_STAT field descriptions (continued)
Field Description
1–4 This field is reserved.
-
5 Write Protect Error
WPER
0 No write protect error
1 A write is attempted to the memory bank which is write protected
6 This field is reserved.
-
7 Command sequence timeout error
STOER
0 No command sequence timeout from system side
1 Command sequence timeout from system side
8–31 This field is reserved.
-
25.3.67 NOR Event and Error Enable register (IFC_NOR_EVTER_EN)
Event and Error Enable Register (NOR_EVTER_EN) is used to enable/disable the
logging of event and error indication in the NOR_EVTER_STAT register.
Address: 153_0000h base + 140Ch offset = 153_140Ch
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
OPCEN_NOR
STOEREN
WPEREN
Reserved
Reserved Reserved
Reset 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1404 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
IFC_NOR_EVTER_EN field descriptions
Field Description
0 NOR Command Sequence operation complete event enable
OPCEN_NOR
0 OPC_NOR Event is not enabled
1 OPC_NOR Event is enabled
1–4 This field is reserved.
-
5 Write Protect Error Checking Enable
WPEREN
0 No write protect error checking
1 Write protect error checking is enabled
6 This field is reserved.
-
7 Command Sequence Timeout Error Enable
STOEREN
0 No command sequence timeout checking
1 Command sequence timeout error checking enable
8–31 This field is reserved.
-
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1405
IFC memory map/register definition
25.3.68 NOR Event and Error Interrupt enable register
(IFC_NOR_EVTER_INTR_EN)
Event and Error Interrupt Enable Register (NOR_EVTER_INTR_EN) is used to enable/
disable the generation of interrupt signals corresponding to error and event reporting.
Software must clear pending events and errors in NOR_EVTER_STAT register before
enabling the interrupts.
Address: 153_0000h base + 1418h offset = 153_1418h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
OPCIREN_NOR
STOERIREN
WPERIREN
Reserved
Reserved Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_NOR_EVTER_INTR_EN field descriptions
Field Description
0 NOR command sequence operation complete event Interrupt enable
OPCIREN_NOR
0 Event Interrupt is not enabled
1 Event Interrupt is enabled
1–4 This field is reserved.
-
5 Write protect error interrupt enable
WPERIREN
0 Write protect error interrupt disable
1 Write protect error interrupt is enabled
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1406 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
IFC_NOR_EVTER_INTR_EN field descriptions (continued)
Field Description
6 This field is reserved.
-
7 NOR command sequence timeout error interrupt enable
STOERIREN
0 Command Sequence Timeout error interrupt disable
1 Command Sequence Timeout error interrupt is enabled
8–31 This field is reserved.
-
25.3.69 NOR Transfer Error Attributes register 0
(IFC_NOR_ERATTR0)
These registers store the attribute corresponding to the first transaction on which error
occured.
Transfer error attribute register 0 (NOR_ERATTR0) is used to register the transaction
attributes corresponding to the first error.
Address: 153_0000h base + 1424h offset = 153_1424h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R ERSRCID ERAID
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
ERTYPE
R ERAID ERCS
Reserved Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1407
IFC memory map/register definition
IFC_NOR_ERATTR0 field descriptions
Field Description
0–7 SRCID corresponding to error transaction
ERSRCID
8–11 This field is reserved.
-
12–19 ID of the error transaction. This field is valid only for write protect error.
ERAID
20–22 This field is reserved.
-
23–25 Chip-select corresponding to NOR error
ERCS
000 Bank0
001 Bank1
010 Bank2
...
111 Reserved
26–30 This field is reserved.
-
31 Type of the transaction
ERTYPE
0 Write
1 Read
25.3.70 NOR Transfer Error Attribute register 1 (IFC_NOR_ERATTR1)
Transfer error attribute register (NOR_ERATTR1) is used to register the transaction
address corresponding to the first error.
Address: 153_0000h base + 1428h offset = 153_1428h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R ERADDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_NOR_ERATTR1 field descriptions
Field Description
0–31 In the case of a write protect error, this field refelcts the address corresponding to which a write cycle was
ERADDR received from the system side.
In the case of a sequence timeout error, this field reflects the last address received from the system side
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1408 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
25.3.71 NOR Transfer Error Attribute register 2 (IFC_NOR_ERATTR2)
Transfer error attribute register (NOR_ERATTR2) is used to register the transaction
SRCID corresponding to the first error.
Address: 153_0000h base + 142Ch offset = 153_142Ch
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
ER_NUM_ ER_NUM_
R
Reserved PHASE_EXP Reserved PHASE_PER Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_NOR_ERATTR2 field descriptions
Field Description
0–11 This field is reserved.
-
12–15 Number of phase expected in command sequence which timed-out by system side.
ER_NUM_
PHASE_EXP NOTE: This attribute is valid only for sequence timeout error.
0000 1 Phase
0001 2 Phase
...
1111 16 Phases
16–19 This field is reserved.
-
20–23 Actual no. of command sequence phases performed on NOR flash before timeout occured
ER_NUM_
PHASE_PER NOTE: This attribute is valid only for sequence timeout error
0000 0 Phase
0001 1 Phase
...
1111 15 Phases
24–31 This field is reserved.
-
25.3.72 NOR Control register (IFC_NORCR)
Address: 153_0000h base + 1440h offset = 153_1440h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
Reserved NUM_PHASE Reserved STOCNT Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1409
IFC memory map/register definition
IFC_NORCR field descriptions
Field Description
0–3 This field is reserved.
-
4–7 No. of Address/Data phase on device for which chip-select has to be asserted:
NUM_PHASE
This field is used for the NOR devices for which CS has to be asserted for multiple address data cycles. It
can be used for command based NOR, where CS remains asserted during unlock cycles and actual
address/data phase.
For example, if the total number of phases (that is, command and address/data) to be sent corresponding
to a particular operation (such as program, block erase, and chip erase) is 5, then this field should be
programmed to 0100. This would indicate to the NOR FCM that the CE needs to be asserted for five
consecutive commands sent from the system side (there by for a complete operation)
0000 1 phase
0001 2 phase
0010 3 phase
0011 4 phase
0100 5 phase
0101 6 phase
0110 7 phase
0111 8 phase
1000 9 phase
1001 10 phase
1010 11 phase
1011 12 phase
1100 13 phase
1101 14 phase
1110 15 phase
1111 16 phase
8–11 This field is reserved.
-
12–15 Sequence Timeout Count
STOCNT
NOTE: This counter is used for timeout on sequential transactions on command based NOR.
0000 256 cycles of IFC module input clock
0001 512 cycles of IFC module input clock
0010 1024 cycles of IFC module input clock
0011 2048 cycles of IFC module input clock
0100 4096 cycles of IFC module input clock
0101 8192 cycles of IFC module input clock
0110 16,384 cycles of IFC module input clock
0111 32,768 cycles of IFC module input clock
1000 65,536 cycles of IFC module input clock
1001 131,072 cycles of IFC module input clock
1010 262,144 cycles of IFC module input clock
1011 524,288 cycles of IFC module input clock
1100 1,048,576 cycles of IFC module input clock
1101 2,097,152 cycles of IFC module input clock
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1410 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
IFC_NORCR field descriptions (continued)
Field Description
1110 4,194,304 cycles of IFC module input clock
1111 8,388,608 cycles of IFC module input clock
16–31 This field is reserved.
-
25.3.73 GPCM Event and Error Status register
(IFC_GPCM_EVTER_STAT)
A separate 1 KB memory-mapped region is allocated for the GPCM specific registers.
GPCM Event and Error Status Register (GPCM_EVTER_STAT) indicates the cause of
an error or event corresponding to GPCM flash devices.
Address: 153_0000h base + 1800h offset = 153_1800h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
TOER
ABER
R PER
Reserved
Reserved
Reserved Reserved
W w1c w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1411
IFC memory map/register definition
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_GPCM_EVTER_STAT field descriptions
Field Description
0–4 This field is reserved.
-
5 Timeout Error
TOER
NOTE: Timeout for Normal GPCM mode will only be observed if IFCTA_B is configured as
acknowledgement signal for transaction access completion, that is, by setting 1 in
CSORn[WGETA] and CSORn[RGETA]. Timeout error will occur if IFC is waiting for the
acknowledgement signal IFCTA_B to come and timeout counter value specified in CSOR[GPTO]
counter has expired
0 No Timeout Error
1 Timeout observed for read/write transaction.
6 This field is reserved.
-
7 Parity Error
PER
0 No Parity Error
1 Parity Error for read/write transaction.
8 This field is reserved.
-
9 Abort Error. Abort for Normal GPCM mode will only be observed if access is terminated by IFCTA_B when
ABER CSORn[RGETA] is programmed to 0. It is valid for read transaction and no error is reported for write
transaction.
0 No abort error
1 Abort happened for the current read transaction
10–31 This field is reserved.
-
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1412 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
25.3.74 GPCM Event and Error Enable register
(IFC_GPCM_EVTER_EN)
Event and Error Enable Register (GPCM_EVTER_EN) is used to enable/disable the
logging of event and error indication in the GPCM_EVTER_STAT register.
Address: 153_0000h base + 180Ch offset = 153_180Ch
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Reserved
Reserved
TOEREN
ABEREN
PEREN
Reserved Reserved
Reset 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_GPCM_EVTER_EN field descriptions
Field Description
0–4 This field is reserved.
-
5 Timeout error checking enable
TOEREN
0 No Timeout Error checking
1 Timeout Error checking is enabled
6 This field is reserved.
-
7 Parity error checking enable.
PEREN
0 No Parity Error Checking
1 Parity Error checking Enabled
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1413
IFC memory map/register definition
IFC_GPCM_EVTER_EN field descriptions (continued)
Field Description
8 This field is reserved.
-
9 Abort Error Checking Enable
ABEREN
0 No Abort Error checking
1 Abort Error checking is enabled
10–31 This field is reserved.
-
25.3.75 GPCM Event and Error Interrupt enable register
(IFC_GPCM_EVTER_INTR_EN)
Event and Error Interrupt Enable Register (GPCM_EVTER_INTR_EN) is used to
enable/disable the generation of interrupt signals corresponding to error and event
reporting. Software must clear pending events and errors in GPCM_EVTER_STAT
register before enabling the interrupts.
Address: 153_0000h base + 1818h offset = 153_1818h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
TOERIREN
ABERIREN
PERIREN
Reserved
Reserved
Reserved Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1414 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
IFC_GPCM_EVTER_INTR_EN field descriptions
Field Description
0–4 This field is reserved.
-
5 Tmeout Error Interrupt Enable
TOERIREN
0 Timeout Error interrupt disable
1 Timeout Error interrupt is enabled
6 This field is reserved.
-
7 Parity Error Interrupt Enable
PERIREN
0 Parity Error interrupt disable
1 Parity Error interrupt is enabled
8 This field is reserved.
-
9 Abort Error Interrupt Enable
ABERIREN
0 Abort Error interrupt disable
1 Abort Error interrupt is enabled
10–31 This field is reserved.
-
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1415
IFC memory map/register definition
25.3.76 GPCM Transfer Error Attributes register 0
(IFC_GPCM_ERATTR0)
Transfer error attribute register 0 (GPCM_ERATTR0) is used to register the transaction
attributes corresponding to error occured.
Address: 153_0000h base + 1824h offset = 153_1824h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R ERSRCID ERAID
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
ERTYPE
R ERAID ERCS
Reserved Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_GPCM_ERATTR0 field descriptions
Field Description
0–7 SRCID corresponding to error transaction
ERSRCID
8–11 This field is reserved.
-
12–19 ID of the error transaction
ERAID
20–22 This field is reserved.
-
23–25 ERCS
ERCS
000 Bank0
001 Bank1
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1416 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
IFC_GPCM_ERATTR0 field descriptions (continued)
Field Description
010 Bank2
.
.
.
111 Reserved
26–30 This field is reserved.
-
31 Type of the transaction
ERTYPE
0 Write
1 Read
25.3.77 GPCM Transfer Error Attributes register 1
(IFC_GPCM_ERATTR1)
Transfer error attribute register (GPCM_ERATTR1) is used to register the transaction
address corresponding to error occured.
Address: 153_0000h base + 1828h offset = 153_1828h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R ERADDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_GPCM_ERATTR1 field descriptions
Field Description
0–31 Address corresponding to error transaction
ERADDR
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1417
IFC memory map/register definition
25.3.78 GPCM Transfer Error Attributes register 2
(IFC_GPCM_ERATTR2)
Transfer error attribute register (GPCM_ERATTR2) is used to register the transaction
attributes corresponding to error occured.
Address: 153_0000h base + 182Ch offset = 153_182Ch
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
PERR_AD
R PERR_BEAT PERR_BYTE
Reserved Reserved Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_GPCM_ERATTR2 field descriptions
Field Description
0–19 This field is reserved.
-
20–21 This gives information on which beat of address/data parity error is observed. This has value from 0 to 3.
PERR_BEAT
For example, if port size is 16 bit and parity error is observed on second beat, then value 1 is reported in
the status register. This field is valid for Generic ASIC mode.
22–23 This field is reserved.
-
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1418 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
IFC_GPCM_ERATTR2 field descriptions (continued)
Field Description
24–27 Parity Error on byte. For GPCM there are four parity error status bit, one per byte. A bit is set for the byte
PERR_BYTE that has parity error (bit 24 represents byte 0, the most significant byte lane). This field is valid for Normal
GPCM mode.
28–30 This field is reserved.
-
31 Parity Error reported in address or data phase. Address phase is only valid for Generic ASIC mode of
PERR_AD GPCM.
0 Address phase
1 Data Phase
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1419
IFC memory map/register definition
25.3.79 GPCM Status register (IFC_GPCM_STAT)
This register is used to reflect the busy status of the GPCM controller.
Address: 153_0000h base + 1830h offset = 153_1830h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
GPCM_BSY
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFC_GPCM_STAT field descriptions
Field Description
0 GPCM_BSY
GPCM_BSY
0 No transaction being done by GPCM controller.
1 GPCM controller is busy with transactions.
1–31 This field is reserved.
-
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1420 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
25.4 IFC functional description
The IFC is used to interface with external NAND flash, asynchronous NOR flash,
SRAM, EPROM, and generic ASIC devices.
To achieve this functionality, the logic is partitioned in independent flash control
machines (FCMs) in the IFC to control the timings of NAND flash, NOR flash, and
GPCM separately. Seven independent chip-selects are provided, but they all share the
same pins; hence, only one memory can be accessed at a time based on the machine-
select bits of the chip-select property register for that bank (CSPRn[MSEL]). If a bank
match occurs, the corresponding machine (NAND, NOR, or GPCM) takes ownership of
the external signals that control the access and maintains control until the transaction
ends.
This figure is a functional block diagram of the flash memory interface and its signal
muxing.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1421
IFC functional description
PERR_L PERR_L
PAR[0:1] PAR[1:0]
CE[3]_B CS_L
RDY_L
ASIC
AD
SOF_L
RW_L
CLK
IFC_CLK CLK
PAR[0:1]
RDY_BSY2_B/
IFCTA/RDY_L TA
CE[2]_B CE_B
External GPCM
Latch
ADDR
WE[0:1]_B
OE_B
DATA
IFC
WP_B
ADDR ADDR
CE[0]_B CE_B
WE0/SOF_L WE_B NOR
FLASH
OE_B/RE_B/RW_L OE_B
AD_8/16 DATA
RDY_BSY0_B RDY/BSY_B
RDY_BSY1_B RDY/BSY_B
WP1_B I/O
WP0_B RE_B
WP2_B
WE_B
WP3_B
WP_B
NAND
CE[1] CE_B FLASH
WE1/CLE CLE
AVD_ALE ALE
BCTL
CE[4]_B
RDY_BSY3_B
CE[5]_B
CE[6]_B
CE[7]_B
RDY_BSY4_B
Figure 25-6. Flash memory interface and muxing (with NVDDR NAND)
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1422 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
The IFC supports the following types of flash control machines (FCMs):
• NOR FCM provides interfacing with NOR flash memories that have a 8-/16-bit-wide
data bus. NOR FCM-controlled banks are used primarily for booting (direct memory-
mapped) and code storage.
• The NAND FCM interfaces to NAND flash EEPROMs with 8- and 16-bit data
buses. If NAND is chosen as the booting device, after reset, the NAND FCM can
load boot code into SRAM buffer for execution. Following boot, the NAND FCM
provides a flexible instruction sequencer that allows a user-defined command,
address, and data transfer sequence of up to 15 steps to be executed against a
memory-mapped buffer RAM. An advance ECC algorithm (BCH codes) is
implemented to correct up to 4-/8-bit errors per sector of 512 bytes and 24/40 bit
erros per 1KB sector.
• GPCM provides an interface to simple, synchronous, memory-mapped devices.
Each memory bank can be assigned to any of these types of machines through the
machine-select bits of the chip-select property register for that chip-select
(CSPRn[MSEL]).
25.4.1 General architecture
The basic architecture of the IFC allows bank selection through address decoding and
address/data pin muxing.
25.4.1.1 Bank selection through address decoding
Banks can be selected via address decoding.
The defined base addresses are written to CSPRn[BA] and CSPRn_EXT[BA_EXT],
while the corresponding address masks are written to AMASKn[AM]. Each time a local
system access is requested, the internal transaction address is compared with each bank.
Address decoding logic is explained in Address Mask register (IFC_AMASnK). If a
match is found on a memory controller bank, the attributes defined in the CSPRn and
CSORn for that bank are used to control the memory access. If a match is found in more
than one bank, the lowest-numbered bank handles the memory access (that is, bank 0 has
priority over bank 1).
25.4.1.2 Address/Data pin muxing for external address latch
There are various pin-muxing schemes available at the IFC interface.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1423
IFC functional description
The IFC provides muxing of the address and data bits on the same bus (AD), where the
muxing is controlled by the AVD/ALE signal. There are two modes supported to supply,
either address msbs (most significant bits) or lsbs (least significant bits) on AD bus.
Chip-select register field CSORn[ADM_SHFT_MODE] determines the mode of address-
data pin muxing for the chip. The pin-muxing modes are described in Mode 0 pin muxing
(CSORn[ADM_SHFT_MODE] = 0) and Mode 1 pin muxing
(CSORn[ADM_SHFT_MODE] = 1).
25.4.1.2.1 Mode 0 pin muxing (CSORn[ADM_SHFT_MODE] = 0)
In this mode of muxing, the IFC supplies the most significant bit (msb) of the address bits
on the AD bus. Register field CSORn[ADM_SHFT] controls the amount of address shift
to align the msb of address with AD[0]. This shift can be utilized to align the msb of
system address with the AD[0] signal during address phase (when AVD/ALE is
asserted).
An application of this mode is an external latched-based system where the AVD/ALE
signal is connected to the latch enable such that external latch latches the address msb
coming through the AD bus during AVD/ALE assertion. This mode is used to connect
conventional NOR devices (having dedicated address and data pins) as well as GPCM-
based interfaces.
In this mode, system address is left shifted by CSORn[ADM_SHFT] shift value and
assigned to AD[0:31]. The address msb will be assigned to data bus msb (AD[0]). The
shifted address can be latched by external latch at the falling edge of AVD/ALE.
The system address directly gets assigned to the IFC address bus (ADDR [0:31])
irrespective of the ADM_SHFT value. The least significant bit (lsb) can be retrieved from
the ADDR bus. ADDR[31] will carry the lsb of the system address.
To interface with a x16 NOR device, the address lsb must be left unconnected on the
board.
For a chip that has a 16-bit AD bus and an 11-bit ADDR bus, which needs to be
interfaced with a memory of 8-bit port width and 128 MB memory size (requiring a 27-
bit address), the following figure shows how system address bits are placed during IFC
address phase (AVD/ALE assertion) with a CSORn[ADM_SHFT] value of 5.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1424 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
Bit position Content
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
System Address A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31
Left shift system address by ADM_SHFT = 5
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Intermittent Shifted X X X X X
A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31
System Address
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
AD Bus at IP A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 X X X X X
Address bus at IP level gets directly assigned by system
address irrespective of ADM_SHFT
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Address Bus at IP A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Exposed AD Bus
A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20
at SoC (Pins)
16 17 18 19 20 21 22 23 24 25 26
Exposed ADDR
A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31
Bus at SoC (Pins)
Figure 25-7. System address assignment with CSORn[ADM_SHFT]= 5 for ADM MODE 0
These figures show a x8 and x16 memory connection for the configuration given above,
where the shift value is 5.
NOTE
These figures are intended to be examples only and may show
ADDR pins that are not supported.
AVD Address msbs
AD0
A26
Latch x8 NOR
(128 MB)
SoC AD15
A11
A16
A10
A26
A0
Address lsbs
Figure 25-8. Connection of x8 NOR for ADM MODE 0
For a x16 memory connection, since the memory expects a 26-bit word address, the
address lsb is left unconnected at the board to supply the word address.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1425
IFC functional description
AVD Address msbs
AD0
A25
Latch x16 NOR
(128 MB)
SoC AD15
A10
A16
A9
A25
A0
NC
A26
Address lsbs
Figure 25-9. Connection of x16 NOR for ADM MODE 0
25.4.1.2.2 Mode 1 pin muxing (CSORn[ADM_SHFT_MODE] = 1)
In this mode of muxing, the IFC supplies the address least significant bit (lsb) on the AD
bus. CSORn[ADM_SHFT] controls the address shift to align the system address lsb with
AD[0]. In this mode, the ADDR bus carries the address most significant bit (msb). This
mode is used to interface address data multiplexed (ADM) NOR devices (internal latch-
based).
Connection in this mode should be treated as a special case since the board connectivity
is in decrementing (reverse) bit order, as shown in following examples.
This is done to simplify the board connection for the ADM NOR as these devices expect
the lsb to get latched at their internal latch with the assertion of AVD. In this mode, the
system address remains the same and the IFC internally rearranges (based on the port
size) the data bus in order to maintain the same data image for both the conventional
NOR (external latched-based) as well as the ADM NOR (internal latch-based). This data
rearrangement is performed internally within the IFC during both the read and write
phases because the board connection for ADM NOR is opposite of the conventional
(non-ADM) NOR devices. This mode is valid only for NOR mode of operation and not
for GPCM.
Unlike in CSORn[ADM_SHFT_MODE] = 0, there is no need to leave the ADDR lsb
unconnected on the board to supply word address to memory for x16- and x32-bit
memories. The reason is that the lsb are now carried by the AD bus, which cannot be left
unconnected since they carry the data during the data phase. Therefore, the logic is
implemented in such a way that the IFC does a necessary address shift internally to
supply word addresses to memory.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1426 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
Example 1: The chip has exposed a 32-bit AD bus and x8 ADM NOR of 128 MB is
connected through it.
In this example, ADM_SHFT does not have any role as the chip has not exposed the
ADDR bus and all address bits are available through the AD bus.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
System address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Shifted system
address based on 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
port size CSPR[PS]
(word address)
Swap address bits and assign to AD bus
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
AD bus at IP 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Exposed AD bus
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
at SoC (ball)
Figure 25-10. Example 1 - System address assignment to the AD bus for ADM MODE 1
AD31
NC
AD27
NC
AD26
A26
x8
SoC ADM
AD8 A8
AD7
AD7
AD0
AD0
AVD_B
Figure 25-11. Example 1 - Connection of x8 ADM NOR for ADM MODE 1
NOTE
The board connections are in decrementing (reverse) bit order
for the ADM NOR only.
Example 2: The chip has exposed a 32-bit AD bus and x16 ADM NOR of 128 MB is
connected through it.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1427
IFC functional description
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
System address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Shifted system
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
address based on
port size
(word address)
Swap address bits and assign to AD bus
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
AD bus at IP 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Exposed AD bus
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x
at SoC (Ball)
Figure 25-12. Example 2 - System address assignment to the AD bus for ADM MODE 1
AD31
NC
AD26
NC
AD25
A25
x16
SoC AD16 A16 ADM
AD15
AD15
AD0
AD0
AVD_B
Figure 25-13. Example 2 - Connection of x16 ADM NOR for ADM MODE 1
Based on the port size, the address is generated such that the proper word address goes to
the memory, unlike conventional NOR (ADM MODE 0). The lsb cannot be left
unconnected as they are carried by AD[0] and is also used in the data phase.
Example 3: The chip has exposed a 16-bit AD bus, 11-bit ADDR bus, and x8 ADM
NOR of 128 MB is connected through it.
In this example, ADM_SHFT=5 is required to align the system address msb with the
right-most ADDR index as shown in the figure below.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1428 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
System address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Word address
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
based on
port size CSPR[PS]
Swap address bits and assign to AD bus
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
AD bus at IP 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Right shift the swapped address by ADM_SHFT programmed to align
msb to index 31 (in same line as in left shift mode)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
ADDR bus at IP x x x x x 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Exposed AD bus
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
at SoC (ball)
16 17 18 19 20 21 22 23 24 25 26
Exposed ADDR bus at SoC (ball) 15 14 13 12 11 10 9 8 7 6 5
Figure 25-14. Example 3 - System address assignment to the AD and ADDR bus for ADM
MODE 1
A26
A26
A16 A16
AD15
A15
x8
ADM
SoC AD8 A8
NOR
AD7
AD7
AD0
AD0
AVD_B
Figure 25-15. Example 3 - Connection of x8 ADM NOR for ADM MODE 1
Example 4: The chip has exposed a 16-bit AD bus, 11-bit ADDR bus, and x16 ADM
NOR of 128 MB is connected through it.
In this example, ADM_SHFT=5 is required to align the system address msb with the
right-most ADDR index as shown below.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1429
IFC functional description
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
System address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Shifted system
address based on x 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
port size CSPR[PS]
Swap address bits and assign to the AD bus
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
AD bus at IP 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x
Right shift the swapped address by ADM_SHFT programmed to align
msb to index 31 (in same line as in left shift mode)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
ADDR bus at IP x x x x x 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Exposed AD bus
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15
at SoC (ball)
16 17 18 19 20 21 22 23 24 25 26
Exposed ADDR bus at SoC (ball) 14 13 12 11 10 9 8 7 6 5 4
Figure 25-16. Example 4 - System address assignment to AD and ADDR bus for ADM
MODE 1
A26
NC
A25
A25
x16
ADM
SoC A16 A16 NOR
AD15
AD15
AD0
AD0
AVD_B
Figure 25-17. Example 4 - Connection of x16 ADM NOR for ADM MODE 1
NOTE
Timing of AVD and AVD_B is same. Both are generated by
the same logic except they are opposite in polarity. If the chip is
only exposing AVD and not exposing AVD_B, then it can be
generated by using an on-board inverter and can be used for
interfacing with ADM NOR.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1430 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
25.4.2 Programming model for flash interface timing
The IFC follows a counter-based approach to generate the required timings on the flash
side.
Programming registers (FTIMn) are provided that correspond to the various flash timing
parameters. The values to be programmed in these registers are in terms of the number of
IFC input clock-cycles derived by the following formula:
Timing counter value = [{Flash Timing Parameter(ns) x IFC module input clock
frequency (MHz)} + 1000 - 1] / 1000
In this approach, counters running at the IFC module input clock generate the appropriate
values for the flash interface signals depending on the value programmed in the Timing
Registers (FTIM0-FTIM3). These timing registers must be programmed per the values
specified in the flash device datasheet mapped to the waveforms shown in NAND
asynchronous mode timings, Unmuxed (parallel) asynchronous NOR read timings, and
Simple asynchronous NOR write timings.
25.4.3 Booting methods
Booting can be performed from NAND or NOR flash on the IFC.
• NOR is directly memory-mapped, so booting from NOR can be done as simple read
operations without any special arrangements. Default timing parameters are loaded
with the assertion of rcw_load/boot_load, details of this requirement is explained in
NOR boot.
• NAND is not directly memory-mapped, so the boot code is loaded first into an
SRAM buffer from where the code can be executed. See NAND flash control
machine for more information about booting from NAND.
The flash timing registers (Flash Timing register 0 for Chip Select n - NAND flash
asyncNVDDR mode (IFC_FTIM0_CSn_NAND) through Flash Timing register 3 for
Chip Select n - NAND Flash Mode (IFC_FTIM3_CSn_NAND)) that control chip-select
0 have default values corresponding to the slowest-mode devices to guarantee boot.
Reset initialization is performed by the reset controller and the default configuration is
determined by cfg_rcw_src and/or RCW settings.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1431
IFC functional description
25.4.4 Software reset handling
Software reset requires that software read and clear specific registers.
Software follows these steps as part of software reset handling:
1. Read all the event and error status registers.
2. Clear the NANDSEQ_STRT register.
3. Clear the NAND_AUTOBOOT_TRGR register.
4. Apply soft reset.
After the soft reset has been applied, the hardware automatically clears all the event and
error status registers. None of the other registers are reset. Therefore, the initial
configuration done by the software is preserved.
25.4.4.1 System bus handling
Any pending transactions on the system bus are terminated with a valid response.
During software reset assertion, providing a good response that corresponds to the
pending transaction on the IFC helps prevent a corresponding interrupt. The core expects
an error interrupt whenever there is an error response from the system bus. Therefore, in
the case of a software reset and an error response is provided, the core goes into a hang
state because there is no corresponding interrupt. If there are pending read transactions,
the garbage data is supplied back; if there is a pending write transaction, the data is not
written in the memory.
The hardware does not allow the software to clear the soft reset bit until all pending
transactions on the system bus have been gracefully terminated (with a good response).
When there are no more transactions pending on the system bus, the hardware allows the
software to clear the soft reset bit.
25.4.4.2 Flash interface handling
All the state machines (NAND, NOR, GPCM, and GASIC) are reset to the idle state.
All related FIFOs and registers are flushed, so the flash interface would be in the idle
state.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1432 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
25.4.5 Data buffer control (BCTL)
The IFC provides a data buffer control signal (BCTL) that can be disabled (remain high)
by setting CSORn[BCTLD]. BCTL should be used to signify the write direction when
high.
NOTE
BCTL is a static value; it cannot be programmed on the fly.
If the access is a write, BCTL remains high for the whole duration. However, if the
access is a read, BCTL is negated (low) so that the memory device is able to drive the
bus. Note that the default (reset and bus idle) value of BCTL is also high.
While accessing slow memories, the data driven by the flash is available on the bus after
deassertion of read enable. To avoid bus contention, BCTL remains low (read mode) for
the time defined by the CSORn[TRHZ] field.
Apart from CSORn[TRHZ], another signal timing that requires attention during the
external buffer control is buffer turn-around. The external buffer takes time to reverse the
direction of the shared I/O bus. This situation is more relevant when a read is followed by
a write. To handle this, GCR[TBCTL_TRN_TIME] is defined, which represents the time
for which BCTL remains high before starting another flash access. The timings are
shown in the following figures.
ip_clk
CE_B
CLE
AVD/ALE
I.O [0:15] CMD ADDR DATA DATA DATA CMD
WE_B
RB_B
RE_B
SAMPL
BCTL
TBCTL_TRN_TIME
TRHZ
Figure 25-18. BCTL signal in NAND read followed by any other operation
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1433
IFC functional description
ip_clk
AVD
CS_B
ADDR ADDR0 ADDR1
OE_B
Data ADDR0 DO ADDR1
Sample
BCTL
TRHZ TBCTL_TRN_TIME
Figure 25-19. BCTL signal in NOR read followed by any other operation
25.4.6 External transceiver enable (TE)
This signal is used to enable/disable the external transceiver depending on whether a
slow/fast memory is connected to the bank servicing the current request.
If various fast/slow memories are connected to different banks of the IFC, the AD bus
may become loaded due to sharing. Such a scenario results in poor rise/fall times and
therefore limits the speed of operation of fast memories given their strict timing
requirements. To address this issue, fast memories should be segregated from the slower
memories using an external transceiver that is connected to the AD bus. In these
scenarios, the IFC provides the configurable transceiver enable (TE) pin.
25.4.6.1 Transceiver enable during boot
The IFC can be used for booting after reset.
The IFC can obtain the TE value, which is used during booting, in the following ways:
• By sampling the TE pin.
In this scenario, the TE pin acts as an input during reset. During this time, the
external transceiver should not drive anything onto the AD bus (that is, keep it
tristated). This is accomplished by connecting a weak pull up/down resistor on the
TE pin so that the external transceiver is disabled. With rcw_load/boot_load, the IFC
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1434 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
samples the TE pin in order to know the polarity of external transceiver's enable pin.
With rcw_load/boot_load, the value stored in CSPR0[TE] as the default value will be
opposite of the polarity of external transceiver's enable pin. Therefore, the polarity of
external transceiver's enable pin is configurable with the help of pull up/down
resistors.
Table 25-6. Programming of
CSPRn[TE]
Transceiver Enable (TE) Input Value of CSPRn[TE]
Slow Memory Fast Memory
Active low 0 1
Active high 1 0
• By the chip booting from fast/slow device
If boot source is a fast device and connected directly to chip (without transceiver),
then the chip should drive the IFC_TE signal such that IFC disables external
transceiver.
For booting from slower devices where transceiver is present in the connectivity,
then the chip should drive the IFC_TE signal such that IFC enables external
transceivers.
25.4.6.2 Transceiver enable post-boot
After booting, and during normal read/write transactions, the TE pin acts as an output
pin.
The configuration of this pin is done on a per-bank basis using CSPRn[TE] bits:
• If a transaction hits bank n, the logic specified by CSPRn[TE] appears on the TE pin
when CSn gets selected by a flash interface arbitration.
• If no CSn is selected, the default (board tied) value appears on the TE pin. (By
default, the transceiver is disabled.)
This table shows how CSPRn[TE] should be programmed depending on polarity of the
transceiver's enable pin and type of memory connected to that particular bank.
Table 25-7. Programming of CSPRn[TE]
External transceiver input Value of CSPRn[TE]
Slow memory Fast memory
Active low 0 1
Active high 1 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1435
NAND flash control machine
25.4.6.3 Transceiver enable example
In this scenario, three chip-selects are used.
The connections are as follows:
• CS0: Slow device
• CS1: Fast device
• CS2: Slow device
Because the transceiver used in this scenario has an active-low enable (TOE), the
programming of the CSPRn[TE] should be:
• 0 when a slow device is connected to the corresponding bank (to enable the
transceiver).
• 1 when a fast device is connected to the corresponding bank (to disable the
transceiver).
Therefore, configuration would be as follows:
• CSPR0[TE] = 0
• CSPR1[TE] = 1
• CSPR2[TE] = 0
25.5 NAND flash control machine
The NAND flash control machine (FCM) provides an interface to parallel-bus NAND
flash devices.
There are separate machines for asynchronous, NVDDR mode.
25.5.1 NAND flash synchronous mode
Only 8-bit port size NAND flash EEPROMs are supported for source Synchronous mode
in ONFI 2.2. The commands, address bytes, and data are transferred on AD[0:7].
For both writes and reads, the DQS is used to qualify data. IFC signals CLE and
AVD/ALE determine whether the writes are of command type (only CLE asserted),
address (only AVD/ALE asserted), or write data (both AVD/ALE and CLE asserted with
read/write being high). Reads are indicated by asserting both AVD/ALE and CLE, with
read/write being low.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1436 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
25.5.2 NAND flash asynchronous mode
For connections between an 8-bit port size NAND flash EEPROM and the IFC in FCM
mode, commands, address bytes, and data are all transferred on AD[0:7] with WE_B
asserted for transfers written to the chip, or RE_B asserted for transfers read from the
chip. IFC signals CLE and AVD/ALE to determine whether writes are of the type
command (only CLE asserted), address (only AVD/ALE asserted), or write data (neither
CLE nor AVD/ALE asserted).
For connection to a 16-bit NAND flash EEPROM to IFC in FCM mode, the high byte of
data appear on AD[0:7], whereas the commands, address bytes, and the low byte of 16-
bit data is placed on AD[8:15] during read and write data transfers.
25.5.3 NV-DDR Mode
Only 8-bit port size NAND flash EEPROM is supported for NV-DDR.
The commands, address bytes and data are transferred on AD[0:7]. For both writes and
reads, the DQS is used to qualify data. IFC signals CLE and ALE determine whether the
writes are of command type (only CLE asserted), address (only ALE asserted), or write
data (both ALE and CLE asserted with W/R_B being high). Reads are indicated by
asserting both ALE and CLE, with W/R_B being low.
25.5.4 Write protect
NAND/NOR flash devices come with an input pin, write-protect (WP_B), used to protect
the flash data from any write.
Register bit CSPRn[WP] per chip-select indicates whether or not write accesses are
allowed on the particular chip-select.
If a NOR device is connected and a write transaction arrives to a write-protected chip-
select, then do not assert chip-select on the NOR flash device and consume the
transaction internally. Hence, the protection is controlled by software and the IFC
hardware. A write protect error is also generated.
When NAND operation is triggered and IFC detects transition of IFC_CSPRn[WP] from
its previous value then it inserts idle cycles on the interface for TWW time where CS_B
and WP_B are asserted as shown in figure below.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1437
NAND flash control machine
As a NAND device is not directly memory-mapped like a NOR device and is accessed
through the instruction register (FIR), hence there is no prior information of the type of
operation to be performed on the NAND. Thus, assert chip-select even if the device is
write-protected and expect the device to ignore the write data sent.
ip_clk
CS_B
CLE
WE_B
TWW
WP_B
Figure 25-20. Write-protect timing in NAND asynchronous mode
For synchronous mode, when cleared to zero, the WP_B signal disables the flash array
program and erase operations. This signal should only be transitioned while there are no
commands executing on the device. After modifying the value of WP, the host should not
issue a new command to the device for at least tWW delay time. The transition of the
WP_B signal is asynchronous and unrelated to any CLK transition in the source
synchronous data interface. The following figure shows the write protect timing
requirement for source synchronous mode. The figure above shows the timing details.
ip_clk
IFC_DDR_CLK
CE#
tWW
WP#
CLE
CMD0
DQ[7:0]
Figure 25-21. Write protect timing in NAND (synchronous mode)
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1438 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
25.5.5 SRAM buffer
Read and write accesses to IFC banks controlled by NAND FCM do not access attached
NAND flash EEPROMs directly. Rather, these accesses read and write the buffer RAM
(a single, shared 16-KB space internal to the IFC and mapped by the base address of
every NAND FCM bank).
Even though each NAND FCM-controlled bank has a different base address to
differentiate it, all accesses to such banks access the same buffer space. External IFC
signals, such as AVD/ALE and CSn, do not assert upon accesses to the buffer RAM.
• To perform a page-read operation from a NAND flash device, software initializes the
FCM command, mode, and address registers, and triggers the read operation on a
particular bank by setting the bit in NANDSEQ_STRT register. FCM executes the
sequence of op-codes held in FIR, reading data from the flash device into the shared
buffer RAM. While this read is taking place, software should not access buffer RAM.
After loading the complete page on buffer RAM ECC decoding can be performed if
it is enabled. Once all the errors have been fixed and if operation completion
interrupt is enabled, an interrupt is generated. When FCM has completed its last
command, buffer RAM can be read.
• To perform a page-write operation, the software writes data into the SRAM buffer.
Then, the software initializes the FCM command, mode, and address registers and
triggers the write operation on a particular BANK by setting the bit in
NANDSEQ_STRT register. FCM will execute the sequence of op-codes held in FIR,
writing the data from shared buffer RAM to the flash device. While this write is
taking place, the software is free to write data in other buffers of the FCM buffer
RAM.
By programming NCFGR[NUM_LOOP] field, the NAND FCM can be used for multi-
page read and write operation. A maximum of 16 pages (for 512-byte page), 4 pages (2-
KB page), and 2-page (4-KB page) can be used for multi-page operation. Operation
completion interrupt will be sent only after completing last page operation.
25.5.5.1 Guidelines for SRAM buffer for NAND access
Guidelines for SRAM buffer for NAND access are as follows:
• The IFC supports only one operation at a time on the NAND flash; that is, the user
can either read data from the SRAM buffer for a NAND flash read or write data in
the SRAM buffer for a NAND flash-write.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1439
NAND flash control machine
• NAND program: The user must fill the complete program data in the IFC's SRAM
buffer before setting the trigger on the IFC to start the data transfer from the SRAM
buffer to the NAND flash. When the trigger is set to transfer the data to a NAND
device, the SRAM buffer must not be accessed for either read or write. Accessing the
SRAM buffer during this time may result in undesirable outcome. The user must wait
for the current program operation to complete before accessing the SRAM buffer for
the next operation.
• NAND read: When the trigger is set in the IFC, the read data coming from the
NAND device is stored in an SRAM buffer. In this operation, the SRAM buffer
should not be accessed until the event-completion flag is set.
25.5.5.2 Buffer layout and page mapping for 512-byte page NAND
flash
The FCM buffer space is divided into 1-KB buffers for 512-byte-page devices
(CSORn[PGS] = 00), mapped as shown in the figure below.
The EEPROM's page numbered P is associated with buffer number (P mod 16), where P
= ROWn. Because the bank size set by AMASKn[AM] is greater than 16 KB, an
identical image of the FCM buffer RAM appears replicated every 16 KB throughout the
bank address space.
In the case where NAND_BC[BC] = 0, FCM transfers an entire page, comprising the
512-byte main region followed by the 16-byte spare region; the 496-byte reserved region
is not accessed and remains undefined for software. However, for commands given a
specific byte-count in NAND_BC[BC], COLn[MS] locates the starting address in either
the main region (MS = 0) or the spare region (MS = 1).
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1440 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
Logical Map (16K Byte) of IFC Buffer SRAM for Flash
Page of 512 Bytes
Bank Base Address 1K Byte Page Buffer
Buffer 0 / Page0
0x0400
Buffer1 / Page1
0x0800 512 Byte
Buffer2 / Page2 Main
Main Page
0x0000
Buffer3 / Page3
0x1000
Buffer4 / Page4 Space 16 Byte Spare
0x1400
Buffer5 / Page5 Reserved
0x1800 Reserved
(496 Bytes)
Buffer6 / Page6
0x1000
Buffer7 / Page7
0x2000
Buffer8 / Page8
0x2400
Buffer9 / Page9
0x2800
Buffer 10 / Page10
0x2000
Buffer 11 / Page11
0x3000
Buffer 12 / Page12
0x3400
Buffer 13 / Page13
0x3800
Buffer 14 / Page14
0x3000
Buffer 15 / Page15
0x4000
Replicated FCM
Buffer RAM
Images in Bank
End of Bank
Figure 25-22. SRAM buffer layout for 512-byte page device
25.5.5.3 Buffer layout and page mapping for 2-KB page NAND flash
The FCM buffer space is divided into four 4 KB buffers for 2-KB page devices
(CSORn[PGS] = 01).
Each page in a 2 KB-page NAND flash comprises 2112 bytes, where 2048 bytes appear
as main-region data and 64 bytes as spare-region data. The EEPROM's page numbered P
is associated with buffer number (P mod 4), where P = ROWn. Because the bank size set
by AMASKn[AM] is greater than 16 KB, an identical image of the FCM buffer RAM
appears replicated every 16 KB throughout the bank address space.
If NAND_BC[BC] = 0, the FCM transfers an entire page comprising the 2048-byte main
region followed by the 64-byte spare region; the 1984-byte reserved region is not
accessed, and remains undefined for software. However, for commands given a specific
byte count in NAND_BC[BC], COLn[MS] locates the starting address in either the main
region (MS = 0) or the spare region (MS = 1). When different IFC banks control both
page devices, a 4 KB-page buffer must be assigned to either the first four or last four 512-
byte page buffers.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1441
NAND flash control machine
Bank Base Address
4K Byte Page Buffer
Buffer 0 / Page0
0X1000
Main 2K Byte
Main Page
Buffer 1 / Page1
0X2000
Spare 64 Byte Spare
Buffer 2 / Page2
Reserve Reserved
0X3000 (1984 Bytes)
Buffer 3 / Page2
0X4000
Replicated FCM
Buffer RAM
Images in Bank
End of Bank
Figure 25-23. SRAM buffer layout for 2-KB page device
25.5.5.4 Buffer layout and page mapping for 4 KB page NAND flash
The FCM buffer space is divided into two 8 KB buffers for 4 KB-page devices
(CSORn[PGS] = 10).
Each page in a NAND flash comprises 4224 bytes, where 4096 bytes appear as main
region data and 128 bytes as spare region data. The EEPROM's page numbered P is
associated with buffer number (P mod 2), where P = ROWn. Because the bank size set by
AMASKn[AM] is greater than 16 KB, an identical image of the FCM buffer RAM
appears replicated every 16 KB throughout the bank address space.
If NAND_BC[BC] = 0, FCM transfers an entire page comprising the 4096-byte main
region followed by the CSORn[SPRZ]-byte spare region.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1442 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
Bank Base Address
8K Byte Page Buffer
Buffer 0 / Page0
4 KByte Main Page
Main
0x2000
Spare Region
Spare
(SPRZ Bytes)
Buffer 1 / Page1 Reserved Reserved
(4096-SPRZ Bytes)
0x4000
Replicated FCM
Buffer RAM
Images in Bank
End of Bank
Figure 25-24. SRAM buffer layout for 4 KB-page device
25.5.5.5 Buffer layout and page mapping for 8 KB page NAND flash
The FCM buffer space is divided into single 8 KB buffers for 8 KB large-page devices
(CSORn[PGS] = 11).
Each page in a large-page NAND flash comprises 8192 + spare region bytes, where 8192
bytes appear as main region data, and spare region bytes appear as spare region data.
Because the bank size set by AMASKn[AM] will be greater than 16 KB, an identical
image of the FCM buffer RAM appears replicated every 16 KB throughout the bank
address space.
If NAND_BC[BC] = 0, the FCM transfers an entire page comprising the 8192-byte main
region followed by the CSORn[SPRZ]-byte spare region.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1443
NAND flash control machine
Bank Base Address
16K Byte Page Buffer
8K Byte Main Page
Main
Buffer #0
/ Page0
Spare Region
Spare (SPRZ Bytes)
Reserve Reserve
(8192-SPRZ Bytes)
0x4000
Replicated
FCM
Buffer RAM
Images
in Bank
End of Bank
Figure 25-25. SRAM buffer layout for 8 KB-page device
25.5.5.6 SRAM buffer initialization requirement
Set NCFGR[SRAM_INIT_EN] bit to initialize the SRAM before initiating the first
program operation. See NAND Configuration register (IFC_NCFGR) for details.
25.5.6 Use of ECC algorithms
BCH encoder and decoder algorithms are implemented to detect and correct up to 4/8 bits
in each 512-byte sector and 24/40 bits in each 1 KB sector.
A Galois Field 213 is used for the encoding and decoding of 4- and 8-bit ECC and a
Galois field 214 is used for 24-/40-bit ECC.
25.5.6.1 Generating Galois field elements
The Galois field elements can be generated by shifting the LFSR.
The following primitive polynomials are used for the computation of respective field
elements.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1444 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
Galois Field 213 field elements
As shown in this figure, the field elements can be generated by shifting the LFSR. Each
state of LFSR represents the field element.
P(x) = 11011000000001 in binary form and 1+x+x3+x4+x13in polynomial form.
X^13 X^4 X^3 X^1 X^0
13 12 11 10 9 8 7 6 5 4 3 2 1
Galois Field 214 field elements
Primitive polynomial P(x) = 110000000001101; that is, 1 + x + x11 + x12 + x14
X^14 X^12 X^11 X^1 X^0
14 13 12 11 10 9 8 7 6 5 4 3 2 1
25.5.6.2 BCH encoding
This section describes BCH encoding scheme.
This figure represents the encoder implementation.
Switch-1
gN gN-1 gN-2 gN-3 g5 g4 g3 g2 g1 g0
Data Out
B N- N- 5 4 3 2 1
N 1 2
ENCODER_LFSR[N-1:0]
Switch-2
A Data In
• 4-bit ECC: g(x) = 11010101011000011101010111000010000011000100101000101
• 8-bit ECC:
g(x)=1100010011011111001000111010001110000010111000011100100000110000
1101111000000111001010001001111110101
• 24-bit ECC:
g(x)=1010000011110100000110100100000100010001000001011000111111011001
11110011111101000010001100000011110001001000100010010001000101001010
11011110101000001111001011011101111101101110110001100011111011011110
10011000000111001000000111000010110101111011011001111101110011111011
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1445
NAND flash control machine
10110011011100010111000110100000000011011000000000110010000110100111
1
• 40-bit ECC:
g(x)=1110000011101110011001100111110110100101110011101000011000000000
00011100111110001001111000000000101000110111010100011101101101011101
01000111100101111111000011010110101001000001100110001110100011110101
00110100000110011011011101111010101101000111111000010011100100001111
01001011001011111010011101110110110110000101011011100010010011100010
11111110110100111011010000000101011101010001011001110110101010110100
00001000011001100001100101001011111111000110111011001000111011000111
11111100111000000111110110100010110000011111010110011010010100110011
01111
In each of the generator polynomial binary forms mentioned above, the msb represents
the lowest polynomial power (g0) and the lsb represents highest polynomial power (gN).
The following LFSR can be used for BCH encoding.
In encoding, operation data corresponding to a sector is given to the LFSR. During this
time, the following events occur:
• Switch 1 is closed and switch 2 is in the down position (A) to allow the transfer of
data to the output.
• After the transfer of a sector's data, switch 1 is opened and switch 2 is moved to the
up position (B).
• Now N parity bits can be read out from the LFSR. ENCODER_LFSR[N-1]
represents the first parity bit out and ENCODER_LFSR[0] the last parity bit.
• The value of N is 52, 104, 336 and 560 for 4-, 8-, 24- and 40-bit ECC.
When the IFC accesses the NAND flash device for a read operation, it performs a BCH
detection algorithm and indicates how many bit errors were detected and corrected. The
number of errors per sector gets registered in the ECCSTAT0/1/2/3 registers. For 24- and
40-bit ECC, only ECCSTAT0/1 are valid as only 8 sectors of 1 KB is possible for SRAM
buffer.
ECC is kept in spare region of page at offset 08h. BCH ECC bytes are first written to the
SRAM buffer and then to the NAND flash device. During program, the user can read the
ECC bytes by reading the appropriate locations in the SRAM buffer.
During encoding, ECC is always calculated for 512-byte data for 4-/8-bit ECC and 1 KB
data for 24-/40-bit ECC. CSORn[ECC_MODE] can be used to select 4-/8-/24-/40-bit
correction mode, and CSORn[ECC_ENC_EN] and CSORn[ECC_DEC_EN] can be used
to enable/disable the ECC logic.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1446 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
If the encoder is enabled to calculate the ECC, then the data to the encoder is fed in the
following manner:
• 16 bits are fed to the encoder every other clock cycle
• The encoder processes the bits in the following manner:
• Bit #15 (d0), bit #14 (d1), bit #13 (d2), .... , bit #0 (d15), that is, bit #15 is the
first bit to enter the encoder
• Parity bit #0 (p0) is the first parity bit which comes out of the encoder
This table explains the manner in which the data and parity bits are stored in the 16-bit
NAND flash memory for 4-bit encoding/decoding.
NOTE
• Even when storing data in an 8-bit NAND flash memory,
the manner in which the data is fed to the encoder remains
unchanged.
• The data to the decoder also needs to be fed in the same
manner.
Table 25-8. 16-bit NAND flash memory organization with 4-bit/sector ECC
bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit
#15 #14 #13 #12 #11 #10
#9 #8 #7 #6 #5 #4 #3 #2 #1 #0
Data d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15
Word 0
Data d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 d28 d29 d30 d31
Word 1
...
Data d408 d408 d408 d408 d408 d408 d408 d408 d408 d408 d409 d409 d409 d409 d409 d409
Word 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5
255
Spare s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 s14 s15
Word 0
Spare s16 s17 s18 s19 s20 s21 s22 s23 s24 s25 s26 s27 s28 s29 s30 s31
Word 1
.
Spare s48 s49 s50 s51 s52 s53 s54 s55 s56 s57 s58 s59 s60 s61 s62 s63
Word 3
Spare p0 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15
Word 4
Spare p16 p17 p18 p19 p20 p21 p22 p23 p24 p25 p26 p27 p28 p29 p30 p31
Word 5
.
Spare p48 p49 p50 p51 0 0 0 0 0 0 0 0 0 0 0 0
Word 7
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1447
NAND flash control machine
Table 25-9. 16-bit NAND flash memory organization with 8-bit/sector ECC
bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit
#15 #14 #13 #12 #11 #10
#9 #8 #7 #6 #5 #4 #3 #2 #1 #0
Data d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15
Word 0
Data d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 d28 d29 d30 d31
Word 1
...
Data d408 d408 d408 d408 d408 d408 d408 d408 d408 d408 d409 d409 d409 d409 d409 d409
Word 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5
255
Spare s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 s14 s15
Word 0
Spare s16 s17 s18 s19 s20 s21 s22 s23 s24 s25 s26 s27 s28 s29 s30 s31
Word 1
.
Spare s48 s49 s50 s51 s52 s53 s54 s55 s56 s57 s58 s59 s60 s61 s62 s63
Word 3
Spare p0 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15
Word 4
Spare p16 p17 p18 p19 p20 p21 p22 p23 p24 p25 p26 p27 p28 p29 p30 p31
Word 5
...
Spare p96 p97 p98 p99 p100 p101 p102 p103 0 0 0 0 0 0 0 0
Word
10
Spare 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Word
11
Table 25-10. 16-bit, large page (2K) NAND flash memory organization with 4-bit/sector
ECC
bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit
#15 #14 #13 #12 #11 #10
#9 #8 #7 #6 #5 #4 #3 #2 #1 #0
Data d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15
Word 0
Data d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 d28 d29 d30 d31
Word 1
...
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1448 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
Table 25-10. 16-bit, large page (2K) NAND flash memory organization with 4-bit/sector
ECC (continued)
Data d163 d163 d163 d163 d163 d163 d163 d163 d163 d163 d163 d163 d163 d163 d163 d163
Word 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83
1023
Spare s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 s14 s15
Word 0
Spare s16 s17 s18 s19 s20 s21 s22 s23 s24 s25 s26 s27 s28 s29 s30 s31
Word 1
.
Spare s48 s49 s50 s51 s52 s53 s54 s55 s56 s57 s58 s59 s60 s61 s62 s63
Word 3
Spare p0_0 p0_1 p0_2 p0_3 p0_4 p0_5 p0_6 p0_7 p0_8 p0_9 p0_1 p0_1 p0_1 p0_1 p0_1 p0_1
0 1 2 3 4 5
Word 4
Spare p0_1 p0_1 p0_1 p0_1 p0_2 p0_2 p0_2 p0_2 p0_2 p0_2 p0_2 p0_2 p0_2 p0_2 p0_3 p0_3
6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
Word 5
.
Spare p0_4 p0_4 p0_5 p0_5 0 0 0 0 0 0 0 0 0 0 0 0
8 9 0 1
Word 7
Spare p1_0 p1_1 p1_2 p1_3 p1_4 p1_5 p1_6 p1_7 p1_8 p1_9 p1_1 p1_1 p1_1 p1_1 p1_1 p1_1
0 1 2 3 4 5
Word 8
Spare p1_1 p1_1 p1_1 p1_1 p1_2 p1_2 p1_2 p1_2 p1_2 p1_2 p1_2 p1_2 p1_2 p1_2 p1_3 p1_3
6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
Word 9
.
Spare p1_4 p1_4 p1_5 p1_5 0 0 0 0 0 0 0 0 0 0 0 0
8 9 0 1
Word
11
Spare p2_0 p2_1 p2_2 p2_3 p2_4 p2_5 p2_6 p2_7 p2_8 p2_9 p2_1 p2_1 p2_1 p2_1 p2_1 p2_1
0 1 2 3 4 5
Word
12
Spare p2_1 p2_1 p2_1 p2_1 p2_2 p2_2 p2_2 p2_2 p2_2 p2_2 p2_2 p2_2 p2_2 p2_2 p2_3 p2_3
6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
Word
13
.
Spare p2_4 p2_4 p2_5 p2_5 0 0 0 0 0 0 0 0 0 0 0 0
8 9 0 1
Word
15
Spare p3_0 p3_1 p3_2 p3_3 p3_4 p3_5 p3_6 p3_7 p3_8 p3_9 p3_1 p3_1 p3_1 p3_1 p3_1 p3_1
0 1 2 3 4 5
Word
16
Spare p3_1 p3_1 p3_1 p3_1 p3_2 p3_2 p3_2 p3_2 p3_2 p3_2 p3_2 p3_2 p3_2 p3_2 p3_3 p3_3
6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
Word
17
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1449
NAND flash control machine
Table 25-10. 16-bit, large page (2K) NAND flash memory organization with 4-bit/sector
ECC (continued)
.
Spare p3_4 p3_4 p3_5 p3_5 0 0 0 0 0 0 0 0 0 0 0 0
8 9 0 1
Word
19
Spare
Word
20
...
Spare
Word
31
Note that pn_m, such that
• n = sector number (0, 1, 2, 3), where:
• Sector 0: d0 to d4095
• Sector 1: d4096 to d8191
• Sector 2: d8192 to d12287
• Sector 3: d12288 to d16383
• m = parity bit number, where:
• 4-bit ECC: 0 to 51 (12 bits padded to 0 to align the number of parity bytes to the
8 bytes boundary)
• 8-bit ECC: 0 to 104 (24 bits padded to 0 to align the number of parity bytes to
the 8 bytes boundary)
During decoding, the full page is loaded into buffer RAM from flash and then decoding
begins. This is required because the BCH decoder can work when a sector's data and
corresponding ECC bytes are supplied to the decoder.
For 4-bit correction, 8 parity bytes, 8-bit correction 16 parity bytes, 24-bit correction 42
parity bytes, and 40-bit correction 70 parity bytes per sector are required. These parity
bytes are stored in the spare region of the page at offset 08h. For small pages, only 4-bit
mode is allowed. For a 2 KB page, four sectors of 512 bytes each can be present in the
main region; hence a total of 4x8= 32 parity bytes are store at offset 08h. For a 4 KB
page size, eight sectors of 512 bytes each can be present; hence 8x8 =64 parity bytes are
required for 4-bit mode and 128 bytes for 8-bit mode.
In 24- and 40-bit mode, the parity information is stored adjacent to each other in the spare
region; that is, the ECC bytes will be placed one after another. With 24-/40-bit ECC
mode, there is no need to pad 0 bits in order to align it to the 8-byte boundary, unlike the
padding that is performed with the 4-/8-bit ECC mode.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1450 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
Main
Main Page
Region
0x08
ECC bytes for
all sectors Spare
Region
Figure 25-26. ECC arrangement on a page
For example, there is a memory of 4 KB page size and a 24-bit ECC is needed to protect
it. A 4 KB page size memory will have four sectors of 1 KB each. The encoder will
generate 42 bytes of parity information for each sector. Therefore, there will be a total of
42x4 = 168 ECC bytes. All 168 bytes are placed in the spare region of the NAND flash at
offset 08h: { Sector-1 {P0, P1,...P335}, Sector-2 {P0,P1,...P335}, Sector-3 {P0,
P1,...P335}, Sector-4 {P0,P1,...P335} } from offset 08h where P0 is the first parity bit
coming out from encoder and P335 the last bit. The data and parity feeding and
arrangement for all the modes remains same and as shown in Table 25-10.
This figure represents the logical flow of encoding and decoding operation during
program and read. During program, ECC bytes are also written back in SRAM. During
read, first, all data bytes corresponding to a page are written in SRAM buffer, and then
the decoding starts on sector basis. At any time, only one operation can be performed on
the NAND; that is, it can only be either read or programmed.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1451
NAND flash control machine
ECC Bytes BCH
ENCODER
Program Data Bytes
MAIN
DATA
NAND
IFC SRAM FLASH
Buffer Read Data Bytes DEVICE
Fixed Data
Read Data
Bytes of a SPARE
sector ECC DATA
bytes
BCH
DECODER
Figure 25-27. BCH encoding/decoding during flash program/read
NOTE
The BCH encoder and decoder should be enabled only when
performing full-page operations. If there are partial page
operations, the encoder and decoder should be disabled.
NOTE
The IFC computes the ECC only for the main region data (as
the ECC is not computed for the spare region). The decoder
detects and corrects 4/8 bits of error on the main region data
and the corresponding ECC bytes stored.
25.5.7 Programming the NAND FCM
The NAND FCM performs operations on the NAND flash interface based on the values
programmed in the common and NAND register spaces.
The user is expected to program the following registers with the appropriate values
before triggering the NAND FCM operation:
• Chip-select option registers
• Flash timing registers
• General control register
• NAND configuration register
• NAND flash command registers
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1452 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
• Flash row and column address registers
• NAND flash byte count register
• NAND flash instruction registers
• NAND chip-select register
• NAND event and error interrupt enable register (in case an interrupt needs to be
generated)
• NAND control register
When all the above registers have been programmed, the NAND FCM can then be
triggered through the NAND operation sequence start register.
{FIR0, FIR1,FIR2}
NOOP
OP0 OP1 OP2 OP3 OP14
Register Space AD[0:15]
CLE
ALE/AVD
NAND Flash
Control WE_B
Machine
RE_B
R/B_B
WP_B
Figure 25-28. FCM instruction sequence mechanism
NOTE
User must use the WFR opcode at the end of NAND FIR
programming to probe the RDY_B/BSY_B signal before end of
operation. Status poll is also recommended after every write or
erase command.
25.5.7.1 FCM command instructions
There are different types of command instructions.
• Commands that issue immediately (CMD0-CMD7)
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1453
NAND flash control machine
• Asynchronous mode: These commands write a single command byte by
asserting CLE and WE_B while driving an 8-bit command on the AD[0:7]/
AD[8:15] (8-/16-bit port) bus. The opcode CMDn sources its command byte
from the field FCR[CMDn]. Therefore, up to eight different commands can be
issued in any instruction sequence.
• NV-DDR Mode: These commands write a single command byte by asserting
CLE with respect to IFC_DDR_CLK while driving an 8-bit command on the
AD[0:7] bus. The opcode CMDn sources its command byte from the field
FCR[CMDn]. Therefore, up to 8 different commands can be issued in any
instruction sequence.
• Commands that wait for RB_B to be sampled high before issuing (CW0-CW7)
• Asynchronous mode: These commands first poll the RB_B signal to be sampled
high before writing a single command write on the AD[0:7]/AD[8:15] (8-/16-bit
port) bus sourced from FCR[CMDn] for opcode CWn. It is necessary to use
CWn opcodes whenever the memory is expected to be in the busy state (such as
following a page read, block erase or program operation) and therefore, initially
unresponsive to commands.
• NV-DDR Mode: These commands first poll the R/B signal to be sampled high
before writing a single command write on the AD[0:7] (8 bit port) bus sourced
from FCR[CMDn] for opcode CWn. It is necessary to use CWn opcodes
whenever the memory is expected to be in the busy state (such as following a
page read, block erase or program operation) and therefore, initially
unresponsive to commands.
Consult the manufacturer's datasheet to determine the values to be programmed into the
FCR register and whether a given command in the sequence is expected to initiate device
busy behavior.
25.5.7.2 FCM address instructions
Address instructions are used to issue addresses to the NAND flash device.
• Asynchronous mode: A complete address is formed by a sequence of 1 or more
bytes, each written onto AD[0:7]/AD[8:15] (8-bit/16-bit port) with AVD/ALE and
WE_B asserted together.
• NV-DDR Mode: A complete address is formed via a sequence of one or more bytes,
each written onto AD[0:7] (8-bit port) with AVD/ALE asserted with respect to
IFC_DDR_CLK.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1454 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
25.5.7.3 FCM data read instructions
Read data instructions assert RE_B repeatedly to transfer one or more bytes of read data
from the NAND flash device.
The different types of data read instructions provided are as follows:
• Read BC bytes of data from the NAND flash device into the internal SRAM
• Asynchronous mode: This instruction reads NAND_BC[BC] into the current
FCM SRAM buffer addressed. The data driven by the NAND flash device is
sampled on the basis of the TRAD timing parameter and the RE_B is asserted
for a time period equivalent to the TRP timing parameter. If NAND_BC[BC] =
0, an entire page (including the main and the spare regions) is transferred in a
burst.
• NVDDR mode: This instruction reads NAND_BC[BC] into the current FCM
SRAM Buffer addressed. The data driven by the NAND flash device is sampled
on the basis of the quarter cycle shifted DQS . If NAND_BC[BC] = 0, an entire
page (including the main and the spare regions) is transferred in a burst.
• Read BC bytes of data from the NAND flash device into the internal SRAM during
boot
• Asynchronous mode: This instruction reads NAND_BC[BC] into the current
FCM SRAM buffer addressed. The data driven by the NAND flash device is
sampled on the basis of the TRAD timing parameter and the RE_B is deasserted
once the read data has been sampled by the NAND FCM. If NAND_BC[BC] =
0, an entire page (including the main and the spare regions) is transferred in a
burst. This instruction can also be used for non-boot applications wherein the
RE_B signal needs to be asserted until the read data has been sampled.
• NV-DDR Mode: Not valid
• Read the NAND flash device status
• Asynchronous mode: This instruction performs a status read operation on the
NAND flash device. The status returned by the device is stored in the
NAND_FSR register.
• NVDDR mode: This instruction performs a status read operation on the NAND
flash device. The status returned by the device is stored in the NAND_FSR
register. Two bytes (duplicate) of data will be stored in the NAND_FSR register.
• Read data into the MDR register
• Asynchronous mode: This instruction reads 8/16 bits of data from a given page
in the NAND flash device (based upon the column address programmed) into the
MDR register.
• NVDDR mode: This instruction reads 16 bits of data from a given page in the
NAND flash device (based upon the column address programmed) into the MDR
register.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1455
NAND flash control machine
25.5.7.4 FCM data write instructions
Write data instructions assert WE repeatedly to transfer program data to the NAND flash
device.
• Asynchronous mode: Write data instructions assert WE repeatedly to transfer 1 or
more bytes of program data to the NAND flash device. If NAND_BC[BC] = 0, an
entire page (including the main and the spare regions) is transferred in a burst.
• NV-DDR Mode: Write data instructions assert CLE and ALE together to transfer 2
or more bytes of program data to the NAND Flash Device. The data is driven along
with centre aligned DQS for the NAND to sample the data. If NAND_BC[BC] = 0,
an entire page (including the main and the spare regions) is transferred in a burst.
25.5.8 Looping FIR sequences
The loop feature provides the flexibility to loop certain FIR sequences (such as program,
read, and erase) a finite number of times based on the value programmed in
NCFGR[NUM_LOOP].
The row and column addresses sent to the NAND flash device during a loop operation
depend on NCFGR[ADDR_MODE]. For a more detailed description of the addresses
performed on the NAND flash device for every subsequent execution of the FIR
sequence during a loop operation, see NAND Configuration register (IFC_NCFGR).
NOTE
For this feature to correctly execute, it is important to note that
the opcodes programmed in the FIR sequence corresponding to
the column and row addresses should always be CA0 and RA0.
Therefore, it is recommended that only one type of operation
(such program/read/erase) be performed through a loop
sequence.
25.5.9 NAND DLL
The DLL is a dynamically-adaptive clock delay module. It provides the ability to
programmably select a quantized delay (in fractions of the clock period) regardless of on-
chip variations such as process, voltage, and temperature (PVT).
This module is functional when NVDDR device is connected to IFC.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1456 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
• The DLL is used to calculate the half pulse width of an internally generated reference
clock (clk_ref) and has the same period as IFC_ND_DDR_CLK. This calculated half
pulse width is used to calculate a delay for the incoming raw DQS (clk_in), which is
then used to capture the read data
The DLL is comprised of three major components:
• One instance of the delay chain - used for reference calibration (half-phase detect)
• One instance of the delay - used as the slave delay line (performs the programmed
delay)
• Phase detector module - forms the control loop with the reference delay line and
provides the decoding and controls for the slave delay line
The following figure shows the block diagram of the DLL used in the IFC.
ifc_dl
dl_dly_chai (ref) clk_ref
dl_pdetec
controls
status
clk_out dl_dly_chai (slav) clk_in
Figure 25-29. DLL block diagram
The DLL control loop consists of a counter, reference delay line, and phase detector
which operate on the ref_clock reference clock input. The reference clock (clk_ref) is fed
into the reference delay line. After reset, a single delay tap is selected. A phase detector is
used to detect the condition where a half shift has a occurred. In addition to this, signals
are generated to either increment or decrement the counter which controls the delay line
(if the half-phase detect condition is not met). Any changes in the delay of the individual
elements of the delay chain (due to PVT) will automatically cause the phase detector
logic to determine if a change in the counter value is required. Once the half-phase shift
is detected, an internal lock signal is generated.
Refer to DLL configuration guideline (valid when IFC is in NVDDR Mode) for
guidelines on DLL usage.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1457
NAND flash control machine
25.5.10 NAND asynchronous mode timings
This section describes the basic NAND flash timing waveforms and the programmable
timing parameters.
Figure 25-30 explains the NAND program cycle; Figure 25-31 and Figure 25-32 explain
the basic read cycle waveforms and corresponding timing parameters for NON-EDO and
EDO mode flash. Non-EDO mode corresponds to ONFi2.0 async mode 0/1/2/3 while
EDO mode corresponds to ONFi mode 4/5.
25.5.10.1 NAND asynchronous mode program data timing
This figure shows the NAND flash program.
ip_clk
CE_B
TCCST
CLE
TCCST
ALE
TCCST
AD COMMAND ADDRESS DATA
TWP TWCHT TWP TWCHT TADLE TWP TWCHT
WE_B
TWH TWH TWH
Figure 25-30. NAND flash program
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1458 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
25.5.10.2 NAND asynchronous mode read data timing
This figure shows the NAND flash read.
ip_clk
CE_B
TCCST
CLE
ALE
IAD] COMMAND ADDRESS DATA0 DATA1
WE_B
TWP TWH TCCST TWP TWH TWBE
R/B_B
TRR TRP TREH
RE_B
tRC
SAMPL
TRAD
Figure 25-31. NAND flash read
25.5.10.3 NAND asynchronous mode calculating read data window
width
Calculating the read data window width can be done in several ways.
• Non-EDO mode NAND
• The window size for the received data is calculated as tRP - tREA + tRHOH.
• EDO mode NAND
• The window size for the received data (except the last data beat) is calculated as
tREH - (tREA - tRP) + tRLOH.
• The window size for last data beat received is calculated as tRHOH - (tREA - tRP).
Based on these calculations, the minimum size of the data window width is 9 ns (for
EDO ONFi mode 5). To support this data window width, a minimum of 333 MHz for the
IFC module input clock is required. By increasing the value of timing parameter tRP, that
is, the RE pulse width, the data window size can be increased.
NOTE
The read cycle time should satisfy this condition: ((tRP + tREH)≥
tRCmin). If the sum of the tRPmin and the tREHmin values specified
by the datasheet is less than the tRCmin (from the datasheet), it is
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1459
NAND flash control machine
then recommended that the tRPmin value be increased to meet
the tRCmin timing requirement. This is recommended because
increasing the tRPmin value causes the data window size to
increase.
Read data sampling time (TRAD) represents the read data sampling time on the NAND.
The value should be programmed where the sampling at the IFC should be done at the
center of the received data eye. Its value can be calculated as [TREAmax (from NAND
datasheet) + 2 x board delay + 1/2 received data window size]. If in EDO mode, the user
should choose the TRAD value corresponding to the smaller data window calculated
using the two formulae explained above for EDO.
NOTE
For EDO mode, the value of TRAD should always be less than
tRP + tREH. If the board delay value used in the TRAD
calculation results in this condition to not be met, the user may
not be able to run the interface at the EDO mode frequency. In
this situation, the read timing should be relaxed by increasing
tRP value to access the NAND device at a slower speed.
25.5.10.4 NAND asynchronous mode read data sampling approach
The IFC follows the approach in which the timing parameters are programmable.
The IFC logic runs at the IFC module input clock and can generate these timings on the
flash interface through the programmed value in the timing registers. Based on the timing
values as given in the ONFi 2.0 spec for each mode, received data window width is
calculated (as explained in the previous section).
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1460 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
25.5.10.5 NAND asynchronous mode read status timing
This figure shows NAND read status timing.
ip_clk
TCCST
CE_B
CLE
ALE/AVD
I/O [0:15] COMMAND STAT
TWP TWH TWHRE
WE_B
TRP
RE_B
TREH
TRAD
SAMPL
Figure 25-32. NAND status read
25.5.11 NV-DDR mode timings
25.5.11.1 NAND synchronous mode program operation
In a program operation, the data is expected by the flash memory on both the rising and
falling edges of the DQS. The DQS should be center-aligned with respect to the data.
The following figure shows the program operation and the relevant timing parameters for
a IFC module input clock:external DDR clock (IFC_DDR_CLK) ratio of 1:2.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1461
NAND flash control machine
IFC module
input clock
IFC_DDR_CLK
tCS
CE
CLE tCAD tCAD
tCH
ALE/AVD tCAD tCAD tADL
COL ROW
DQ[7:0] CMD0 ADD ADD
D0
-E
D0
-O
D1
-E
D1
-O
tWPRE
tWPST
DQS
tDQSS
Figure 25-33. NAND synchronous mode program operation
25.5.11.2 NAND synchronous mode program with clock stopped
The user can program the IFC to save power during the data input cycles by setting the
DDR clock stop bit in the IFC DDR clock control register.
This will result in the IFC_DDR_CLK signal being held high (that is, stopping the CLK).
However, the IFC_DDR_CLK will be stopped only during program phase. The following
figure shows the timing relationship of a program operation with the clock stopped. The
values of the AVD/ALE, CLE, and W/R_n signals are latched on the rising edge of
IFC_DDR_CLK and thus, while the clock is held high, these signals are don‘t care.
The following figure shows the program operation with the clocked stopped and the
relevant timing parameters for an IFC module input clock:external DDR clock
(IFC_DDR_CLK) ratio of 1:2.
IFC module
input clock
IFC_DDR_CLK
tCS
CE
tCAD
CLE
tCAD tCAD tADL
ALE/AVD
W/R#
COL ROW
DQ[7:0] CMD0 ADD ADD
D0
-E
D0
-O
D1
-E
D1
-O
D2
-E
D2
-O
D3
-E
D3
-O
tWPRE
tWPST
DQS
tDQSS
Figure 25-34. NAND synchronous mode program operation with clock stopped
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1462 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
25.5.11.3 NAND synchronous page read operation
For page read operation, the flash memory sends the read data aligned with the rising and
falling edge of the DQS. In this case, the DQS is edge-aligned with the data.
The following figure shows the read page operation and the relevant timing parameters
for an IFC module input clock:external DDR clock (IFC_DDR_CLK) ratio of 1:2.
IFC module
input clock
clk_sync
IFC_CLK
CE tCS tCH
tCAD tWRCK
CLE
tCAD tCAD tCAD tCAD tWRCK
ALE/AVD
W/R# tCKWR
tDQSCK
DQS
DQ[7:0] COL ROW D0 D0 D1 D1
CMD0 ADD ADD CMD0 -E -O -E -O
Figure 25-35. NAND synchronous mode page read operation
25.6 NOR flash control machine
The NOR FCM allows an interface to asynchronous, simple, and internal latch-based
NOR flash devices.
25.6.1 NOR boot
For NOR boot, CS0 is the boot chip-select.
Before fetching the first instruction from the NOR flash, the IFC flash timing registers
are loaded with default timing parameters.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1463
NOR flash control machine
25.6.2 Unmuxed (parallel) asynchronous NOR read timings
The figures show the read cycle and burst read cycle timing diagrams.
ip_clk
TEADC
ALE
TEAHC TACSE
CS_B
ADDR ADDR
TACO
OE_B
Data ADDR D0
TRAD
Sample
Figure 25-36. Read cycle timing
ip_clk
ALE
CS_B
ADDR ADDR0 ADDR1 ADDR2 ADDR3
OE_B
TACO
Data ADDR0 D0 D1 D2 D3
TSEQRAD TSEQRAD
TRAD
Sample
Figure 25-37. Burst read cycle timing
25.6.3 Simple asynchronous NOR write timings
The figures show the write cycle and burst write cycle timing diagrams.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1464 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
ip_clk
TEADC
TEAHC
ALE
TACSE
CS_B
ADDR ADDR
TCS TCH
TWP
WE_B
DATA ADDR DO
Figure 25-38. Write cycle timing
ip_clk
ALE
CS_B
TCS TCH
ADDR ADDR0 ADDR1 ADR2 ADDR3
TCH
WE_B TWP
TWPH
AD D0 D1 D2 D3
Figure 25-39. Burst write cycle timing
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1465
NOR flash control machine
25.6.4 Muxed (ADM) asynchronous NOR read timings
This figure shows the read cycle timing diagram.
ip_clk
CS_B
TAVDS TEADC TEAHC
AVD_B
Addr ADDR
TACO
OE
AD ADDR DO
Sample
Figure 25-40. Read cycle timing
25.6.5 Muxed (ADM) asynchronous NOR write timings
This figure shows the write cycle timing diagram.
IP_CLK
CS_B
TAVDS, TEADC, TEAHC
AVD_B
Addr ADDRO ADDR1
TCS
WE_B
AD ADDRO DATAO ADDR1 DATA1
Figure 25-41. Write cycle timing
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1466 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
25.7 General purpose chip-select machine (GPCM)
The GPCM controller has two modes of operation: normal GPCM and generic ASIC.
Only one mode is operational at a time per chip select. The mode is selected by the value
programmed in GPMODE field of CSORn_GPCM register.
25.7.1 Normal GPCM mode of operation
The figure below explains the interface of the IFC to a device connected through the
normal GPCM FCM.
CS_B
IFC_CLK
OE_B
WE_B
GPCM
SRAM/
FCM
EPROM
(IFC) ADDR
AD
Parity
IFCTA_B
Figure 25-42. Normal GPCM interface
25.7.1.1 Normal GPCM program operation
In normal GPCM, the write transaction depends on the register field CSORn[WGETA].
The following options, through an internal counter or through an external device giving
an access termination signal, are explained below.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1467
General purpose chip-select machine (GPCM)
25.7.1.1.1 Normal GPCM internal counter-based program operation
Transactions are based on control-signal timings that are programmed in the flash timing
registers for GPCM mode (IFC_FTIMx_CSn_GPCM) when CSORn[WGETA]=0.
Assertion of AVD/ALE is aligned to the rising edge of ifc_launch_clk (an internal clock),
after that all the timing parameters are in terms of the IFC module input clock (ip_clk).
IFC_CLK is external clock which goes to the device and it is generated by inverting
ifc_launch_clk.
ip_clk
ifc_launch_clk
IFC_CLK
TEADC
ALE
TACSE
TCH
CS_B
ADDR Addr0
TCS TWP
WE_B F WE0 F
TEAHC
AD Addr0 Data0
Parity 0 par0
Figure 25-43. Normal GPCM program operation - non-burst mode
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1468 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
ip_clk
IFC_CLK
ALE/AVD
CS_B
ADDR ADDR0 ADDR1
WE_B F 0 F 0 F
Data ADDR0 DATA0 ADDR1 DATA1
Parity 0 Parity0 0 Parity1
OE_B
BCTL
Figure 25-44. Normal GPCM back-to-back program operation
In burst mode, the next data and next address are sent after one TWP period (the amount
of time between address/data cycles). If IFCTA_B is deasserted and the burst is
controlled by the timing parameter programmed in FTIM registers, the burst will
continue until either the burst length is reached or complete data is transferred. If the
number of bytes of data to be transferred is less than programmed burst length multiplied
by port size, then the burst will be terminated before the programmed maximum number
of burst transfers.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1469
General purpose chip-select machine (GPCM)
ip_clk
ifc_launch_clk
IFC_CLK
TEADC
ALE/AVD
TACSE
CS_B
TWP TWP TWP
ADDR Addr0 Addr1 Addr2 Addr3
TCS TWP
WE_B
F WE0 WE1 WE2 WE3 F
TEAHC
DATA Addr0 Data0 Data1 Data2 Data3
Parity 0 par0 par1 par2 par3
burst_length = 2
WGETA =0
no external termination
Figure 25-45. Normal GPCM program operation - burst mode
For a normal timing-based transaction, CSORn[RGETA]=0. If the access is aborted by
IFCTA_B and there is remaining data to be transferred, the current burst is terminated
and a new burst transaction is launched. Ongoing burst terminates at the next rising edge
of ifc_launch_clk after the assertion of IFCTA_B. The next burst's starting address is the
last burst address + the number of bytes that needed to be transferred in the last burst.
Addressn+1 = Addressn + (number of bytes for current burst)
The next burst starts only after deassertion of IFCTA_B. This is registered as an abort
error in the status register and all transaction attributes are locked.
Since IFCTA_B is synchronized through asynchronous FIFO, bus termination occurs
only after a synchronization delay of IFCTA_B. IFCTA_B should be asserted for at least
one IFC_CLK cycle if it is synchronous (that is, meeting setup and hold time); otherwise,
asynchronous IFCTA_B should be asserted for a minimum of two IFC_CLK cycles.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1470 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
ip_clk
ifc_launch_clk
IFC_CLK
clk_sync
IFCTA_B
ALE/AVD
ADDRESS ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7
DATA_IO ADDR0 DATA0 DATA1 DATA2 DATA3 ADDR4 DATA4 DATA5 DATA6 DATA7
CS_B
WE_B F WE0 WE1 WE2 WE3 F WE4 WE5 WE6 WE7 F
IFC_TA_SYNC_B
burst_length = 2
wgeta = 0
External termination by TA.
current burst terminates
Figure 25-46. Normal GPCM program operation - transaction aborted
25.7.1.1.2 Normal GPCM external termination-based program operation
When WGETA is set, the next address and data are sent only after sampling the rising
edge of IFCTA_B or after timeout (as defined in register CSORn[GPTO]).
IFCTA_B is synchronized to the IFC module input clock through asynchronous FIFO
and only after the rising edge of IFCTA_B, the new beat is sent over the interface. The
next data and address beat is sent in sync with the positive edge of ifc_launch_clk. The
last beat of the last burst completes at the next rising edge of ifc_launch_clk after
assertion of IFCTA_B, without waiting for deassertion of IFCTA_B and CS_B is
deasserted.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1471
General purpose chip-select machine (GPCM)
If transaction size is greater than GPCM port size, the transaction will be split into
multiple port size accesses. For non-burst mode, the last split is terminated at the rising
edge of ifc_launch_clk after assertion of IFCTA_B or after timeout. For other splits, IFC
waits for IFC_TA deassertion and not available for further transactions until IFC_TA is
deasserted.
As IFCTA_B is synchronized through asynchronous FIFO, bus termination occurs only
after the synchronization delay of the IFCTA_B signal. IFCTA_B should be asserted for
at least one IFC_CLK cycle if it is synchronous (that is, meeting setup and hold time);
otherwise, if it is asynchronous, IFCTA_B should be asserted for a minimum of two
IFC_CLK cycles.
ip_clk
ifc_launch_clk
IFC_CLK
clk_sync
IFCTA_B
ALE_B
Address ADDR0 ADDR1
DATA_IO ADDR0 DATA0 DATA1
CS_B
WE_B F WE0 WE1
IFC_TA_SYNC_B
burst_length = 1
wgeta = 1
Note: Addr1 is last transaction cycle of complete data transfer, hence
terminates before deassertion of ifc_ta
Figure 25-47. Normal GPCM program operation - acknowledgment mode
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1472 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
25.7.1.2 Normal GPCM read operation
In normal GPCM, the read operation depends on the register field CSORn[RGETA]. The
following options, through an internal counter or through an external device giving an
access termination signal, are explained below.
25.7.1.2.1 Normal GPCM internal counter-based read operation
In this approach, read data from memory is sampled based on the programming of
FTIM1_CSn_GPCM[TRAD] and FTIM3_CSn_GPCM[TAAD].
In non-burst mode, TRAD defines the pulse width of OE_B. The read data is sampled on
rising edge of IFC_CLK just before the de-assertion of OE_B
By default, (CCR[INV_CLK_EN]=1 and CCR[CLK_DLY]=0) inverted clock of
ifc_launch_clk goes out (IFC_CLK) to the external device. Because the address is
launched at the rising edge of ifc_launch_clk, the setup time on an external device for the
address phase is half the cycle period of IFC_CLK. The read data launched by the device
will be sampled by the IFC at the next rising edge of IFC_CLK. The programming of
TRAD_GPCM and TAAD_GPCM should be as follows:
• For non-burst mode TRAD value should be programmed as {(2 + n)*
(CCR[CLK_DIV] + 1)}, where n defines the memory access time in terms of
IFC_CLK. Memory takes n ifc_clk to output data after output enable is asserted or
after new address is sampled. n can take values 0,1,2,3...
• For burst mode TRAD/TAAD programmed will be {(2 + n)* (CCR[CLK_DIV] +
1)}, where n defines the memory access time in terms of IFC_CLK. Memory takes n
IFC_CLK to output data after output enable is asserted or after new address is
sampled. n can take values 0,1,2,3...
The following figures explain the above-mentioned read data sampling schemes:
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1473
General purpose chip-select machine (GPCM)
ip_clk
ifc_launch_clk
IFC_CLK
ALE/AVD
CS
ADDR Addr
TACO
TRAD
OE_B
AD ADDR0 DATA
Parity PARITY
TRAD= {(2 + 1)x(CCR[CLK_DIV] + 1)}
n=1, CLK_DIV=1
TRAD = 6 ip_clks
Figure 25-48. Normal GPCM read operation - non-burst mode
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1474 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
ip_clk
IFC_CLK
ALE/AVD
CS_B
ADDR ADDR0 ADDR1
OE_B
Data ADDR0 DATA0 ADDR1 DATA1
TRHZ
TEAHC TBCTL
BCTL
WE_B
TRHZ: Extended hold time for slow memories to disable their bus drivers
TBCTL: Bus turn-around time
Figure 25-49. Normal GPCM back-to-back read operation
When RGETA is programmed to 0 and access is aborted by ifc_ta, then the current burst
is terminated and new burst transaction is launched. The ongoing burst is terminated at
the next rising edge of ifc_launch_clk after assertion of ifc_ta. The next burst starting
address will be the last burst address + number of bytes that needed to be received in the
last burst.
Addressn+1 = Addressn + (number bytes for current burst)
The next burst starts only after deassertion of ifc_ta.
An abort error is registered in the status registers and all the trasaction attributes are
locked. Since ifc_ta is synchronized through asynchronous FIFO, bus termination occurs
only after synchronization delay of ifc_ta signal. ifc_ta should be asserted for minimum
two IFC_CLK cycles.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1475
General purpose chip-select machine (GPCM)
ip_clk
ifc_launch_clk
IFC_CLK
TEADC
ALE/AVD
TACSE
CS_B
TAAD TAAD
ADDR Addr0 Addr1 Addr2 Addr3
TACO
OE_B TRAD
DATA_IO Addr0 0 Data0 Data1 Data2 Data3
OE_SYNC
DATA_SYNC Data 0 Data 1 Data 2 Data 3
TRAD TAAD TAAD TAAD
SAMP_PULSE
busrt_length = 2
rgeta = 0
no external termination
Figure 25-50. Normal GPCM read operation - burst mode
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1476 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
Figure 25-51. Normal GPCM read operation - transaction aborted
25.7.1.2.2 Normal GPCM external termination-based read operation
When RGETA is set to 1, each beat of the transaction waits for an external termination
by IFCTA_B or timeout.
For address transfer, the next address is sent only after IFCTA_B is deasserted or after
timeout. IFCTA_B is synchronized to ip_clk through the asynchronous FIFO and only
after the rising edge new address beat is sent over the interface. The new address beat is
sent in sync with ifc_launch_clk. The last transaction cycle does not wait for deassertion
of IFCTA_B; it ends at the next rising edge of ifc_launch_clk after assertion of IFCTA_B
or after timeout.
For read data sampling, the read data is sampled on the falling edge of IFCTA_B.
IFCTA_B and data both are synchronized through the asynchronous FIFO.
For non-burst mode, access is terminated after IFCTA_B is asserted or timeout.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1477
General purpose chip-select machine (GPCM)
In case of a timeout, an error is registered in the GPCM status register and all transaction
attributes are locked. As IFCTA_B is synchronized through the asynchronous FIFO, bus
termination occurs only after a synchronization delay of the IFCTA_B signal. IFCTA_B
should be asserted for at least one IFC_CLK cycle if it is synchronous (that is, meeting
setup and hold time); otherwise, if asynchronous, IFCTA_B should be asserted for a
minimum of two IFC_CLK cycles.
ip_clk
ifc_launch_clk
IFC_CLK
IFCTA_B
ALE
Address ADDR0 ADDR1 ADDR3 ADDR4
AD ADDR0 DATA0 DATA1 DATA3 DATA4
CS_B
IFC_TA_SYNC_B
OE_B
Note: Addr4 is last transaction cycle of the complete data transfer, hence temrinates before deassertion of ifc_ta burst_length = 4 beats
RGETA = 1
Figure 25-52. Normal GPCM read operation - acknowledgment mode
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1478 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
Figure 25-53. Normal GPCM back-to-back Read Operation
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1479
General purpose chip-select machine (GPCM)
25.7.2 Generic ASIC mode of operation
This figure explains the interface of the IFC to a device connected through generic ASIC
mode of GPCM (CSORn[GPMODE]=1).
CS_B
ifc_clk
RW_L
Sof_L
GASIC
GENERIC
FCM
Data ASIC
(IFC)
Parity
PERR_L
RDY_L
Figure 25-54. Generic ASIC interface
25.7.2.1 General ASIC program operation
Before initiating any general ASIC (GASIC) operation, the chip-select (CS_B) is asserted
to select the appropriate device.
The assertion of start of frame (SOF_B) along with the low value on RW_B indicates the
start of address phase for write transfer. In the case of a 16-bit device, the upper 16 bits of
address is driven on the AD[0:15] first, followed by the lower 16 bits on the next clock.
After the address phase, the write data sequences are driven on AD lines based on the
port size. Along with the address and write data phases, per-byte parity is driven on the
parity lines. On the completion of write data phase, the host controller waits for the ready
status (RDY_B) and the parity error sampling (based on CSORn[GAPERRD] time)
before deasserting the chip-select to complete the transfer. In the case where the device is
not asserting RDY_B before timeout (as defined in CSORn[GPTO]) occurs, the host
terminates the transfer by deasserting the CS_B.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1480 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
IFC_CLK
BCTL
CS_B
SOF_B
RW_B
AD[0:15] A[0:15] A[16:31] D[0:15] D[16:31]
PAR[0:1] A[0:15] PAR A[16:31] PAR D[0:15] PAR D[0:15] PAR
RDY_B
PERR_B A[0:15] PERR A[16:31] PERR D[0:15] PERR D[16:31]PERR
Figure 25-55. GASIC program operation with 16-bit device and zero-wait state
For program operation, wait state represents delay (in terms of IFC_CLK) between first
write data beat versus RDY_B assertion time.
For read, wait state represents delay (in terms of IFC_CLK) between last address beat
sent by controller and RDY_L assertion time. If RDY_L is asserted in next cycles of
address sampled by GASIC device then it is termed as zero wait state.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1481
General purpose chip-select machine (GPCM)
25.7.2.2 Generic ASIC read data sampling
After selecting the general ASIC (GASIC) device, the host asserts start of frame (SOF_B)
and drive high value on RW_B to indicate the start of address phase for read transfer.
The host drives the AD lines and the corresponding PAR parity lines in this phase to send
the 16 -bit of address to the device. After completing the address phase, the host stops
driving the AD lines and waits for the assertion of ready status (RDY_B) from the device.
The assertion of RDY_B indicates the start of read data phase. In the case the device has
not asserted RDY_B before timeout occurs, the host terminates the transfer by
deasserting the CS_B.
IFC_CLK
BCTL
CS_B
SOF_B
RW_B
AD[0:15] A[0:15] A[16:31] D[0:15] D[16:31]
PAR[0:1] A[0:15] PAR A[16:31] PAR D[0:15] PAR D[16:31] PAR
RDY_B
PERR_B A[0:15] PERR A[16:31] PERR
Figure 25-56. GASIC read operation with 16-bit device and 2-wait state
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1482 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
25.8 Clock generation module
The clock generation module generates a divided clock derived from the IFC module
input clock depending on the programmed value in the CCR register.
Whenever there is a change in any clock division ratio, the clock is gated for few IFC
module input clocks. The clock status is reported as unstable in the CSR register.
ip_clk
clk_div 4 5
div_cntr 4 3 2 1 0 4 3 2 1 0 4 3 2 1 0 5 4 3 2 1 0 5 4 3 2 1 0 5 4 3 2 1 0 5 4 3 2 1 0 5 4 3 2
ungated_ifc_clk
clk_stat
IFC_CLK
Figure 25-57. External clock generation
25.9 Initialization/Application information
The IFC can be used with separate address and data buses or with a multiplexed address/
data bus.
This section provides guidelines for interfacing peripherals in the IFC's various modes.
25.9.1 Switching Interfaces in ONFi NAND
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1483
Initialization/Application information
25.9.1.1 Activating the NVDDR Interface
After coming out of reset and performing device initialization, by default the
asynchronous interface of the NAND device is activated. To switch to the NV-DDR
interface, the following steps should be performed:
• Wait for OPC, if any previous operation is being executed on the NAND device.
• Program a FIR sequence (CMD0 - UA - WBCD - WFR - NOOP) that will issue the
SET FEATURE command, followed by Wait For Ready, followed by NOOP.
• Issue the SET FEATURES (EFh) command. (CMD0)
• Write address 01h, which selects the timing mode. (UA)
• Write P1 with 1Xh for NVDDR devices, where "X" is the timing mode used in the
synchronous interface (WBCD)
• Write P2-P4 as 00h-00h-00h. (WBCD)
• tWB time after the last data of the SET FEATURE command has been written the
device goes into busy state (R/B_B is pulled low). After tITC time elapses, the
device enters ready state (R/B_B transitions to high) and the NAND will now be in
desired mode. The user is required to poll for the OPC status bit before issuing any
new operation on the NAND device.
• Program the CSORn[NAND_MODE] field to "0x01" for NV-DDR mode .
• If the user wants to use auto timing parameters, write the desired timing frequency
value with which the NAND device is configured, to the
CSOR_EXTn[MODE_FREQ] field. This will configure the FTIM registers,
corresponding to the chip select whose MODE_FREQ field has been written to, for
the source synchronous device. The values programmed in the FTIM registers will be
calculated based on the timing mode value programmed in
CSOR_EXTn[MODE_FREQ], the clock divider value in the DDR-CCR register and
the maximum permissible operating frequency (as per the ONFI ) for the
programmed timing mode. Also the CSOR_EXTn[AUTO_TIM_PARAMS_SEL]
should be set.
• If the user wants to use the FTIM registers to program timing parameters, the
AUTO_TIM_PARAMS_SEL bit should not be set.
• Before starting read operation using NVDDRmode, user must wait for DLL to get
lock as specified in DLL configuration guideline (valid when IFC is in NVDDR
Mode).
25.9.1.2 Switching to the asynchronous interface
To activate the asynchronous NAND interface, once the NVDDR interface is active,
program the NAND_CSORn[NAND_MODE] to set the asynchronous mode.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1484 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
The user should ensure that there is no activity on the NAND interface while
programming this register field. Then perform the following steps:
• Wait for OPC, if any previous operation is being executed on the NAND device.
• Program the CSORn[NAND_MODE] field to 00hh.
• Program FIR sequence (CMD0 -WFR - NOOP) that will issue the reset command
(FFh) to the NAND device using an asynchronous command cycle. tWB time after the
command is issued, the RB_B signal goes low indication the device is in busy state.
After tRST time, the device will be in ready state. The user should poll for the OPC
status bit before issuing any new operations on the NAND device.
Once the above FIR sequence is complete, the NAND device will be in asynchronous
mode and will be set to timing mode 0.
25.9.1.3 Switching timing modes when configured in NVDDR mode
To switch timing modes on the device (with NVDDR interface active) the following
steps should be performed:
• Wait for OPC, if any previous operation is being executed on the NAND device.
• Program a FIR sequence (CMD0 - UA - WBCD - WFR - NOOP) that will issue the
SET FEATURE command, followed by Wait For Ready, followed by NOOP.
• Issue the SET FEATURES (EFh) command. (CMD0)
• Write address 01h, which selects the timing mode. (UA)
• Write P1 with 1Xh for NVDDR devices, where "X" is the timing mode used in
the synchronous interface (WBCD)
• Write P2-P4 as 00h-00h-00h. (WBCD)
• tWB time after the last data of the SET FEATURE command has been written the
device goes into busy state (R/B_B is pulled low). After tITC time elapses, the
device enters ready state (R/B_B transitions to high) and the NAND will now be in
desired mode. The user is required to poll for the OPC status bit before issuing any
new operation on the NAND device.
• If the user wants to use auto timing parameters, write the desired timing frequency
value with which the NAND device is configured, to the
CSOR_EXTn[MODE_FREQ] field. This will configure the FTIM registers,
corresponding to the chip select whose MODE_FREQ field has been written to, for
the source synchronous device. The values used for interface signal timing
generation will be calculated based on the timing mode value programmed in
CSOR_EXTn[MODE_FREQ], the clock divider value in the DDR-CCR register and
the maximum permissible operating frequency (as per the ONFI spec) for the
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1485
Initialization/Application information
programmed timing mode. Also the CSOR_EXTn[AUTO_TIM_PARAMS_SEL]
should be set
• If the user wants to use the FTIM registers to program timing parameters, the
AUTO_TIM_PARAMS_SEL bit should not be set.
25.9.2 ONFI mode timing parameters
For source-synchronous devices, there is an option to program the IFC with timing
parameters as per the ONFI 2.2 timing parameters for all timing modes.
CSOR_EXTn[ONFI_MODE] is used to indicate the timing mode with which the chip is
programmed and the CSOR_EXTn[ONFI_TIM_PARAMS] is set to enable this feature.
Based on the value of CSOR_EXTn[ONFI_MODE], the value of
DDR_CCR[DDR_CLK_DIV], and the maximum-permissible operating frequency for a
particular timing mode (as per ONFI 2.2), the timing values are programmed in the
number of IPG clock cycles.
The values of the timing parameters (rounded to the next higher integer) can be
calculated as follows:
• ONFI_TIMING_PARAMETER + (MODE_PERIOD/(2 x DDR_CLK_DIV + 2) - 1)
• MODE_PERIOD/(2 x DDR_CLK_DIV + 2)
where
• ONFI_TIMING_PARAMETER is an ONFI timing parameter (such as tcad, tcs, and
so on)
• MODE_PERIOD is the minimum clock period (ns) for a particular ONFI mode.
• DDR_CLK_DIV is the clock division ratio programmed in the
DDR_CCR[DDR_CLK_DIV] register.
25.9.3 DLL configuration guideline (valid when IFC is in NVDDR
Mode)
The DLL (NAND_DLL_LOW is) configured using the Configuration 0 and
Configuration 1 registers. The following sequence should be followed before the DLL
can be used to delay the incoming data strobe:
• The NAND_DLL_LOW is enabled when the DDR clock is enabled (by setting DDR
CCR LOW [2]) and CSOR[NAND_MODE] = NVDDR mode.
• The NAND_DLL_LOW is used for interface frequencies up to 133 MHz.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1486 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
• The reset value of the dll_slv_dly_target field in DLL Configuration 0 register for
NAND_DLL_LOW is 0x7. This will ensure a delay of REF_CLK/4 on the incoming
DQS.
• The user must change the NAND_DLL_CFG1[DLL_PD_PULSE_STRETCH_SEL]
bit from its default value 1’b1 to 1’b0 for reliable pulse detection and DLL lock.
• The user has to poll for the value of ‘1’ on the DLL_STS_SLV_LOCK bit of
NAND_DLL_LOW_STAT (if enabled) register before issuing any access to the
NAND Flash. Neglecting this would result in incorrect read data capture by IFC.
• If the CSOR_EXT[MODE_FREQ] bit is changed, then the delay chain needs to be
reset to make it lock again.
25.9.4 IFC flash connections
25.9.4.1 NAND flash connections
The NAND FCM provides a glueless interface to 8- or 16-bit parallel-bus NAND flash
EEPROM devices.
This figure shows a simple connection between an 8-bit port size NAND flash EEPROM
and the IFC. In NAND FCM mode, commands, address bytes, and data are all transferred
on AD[0:7].
CSn_B CE_B
CLE CLE
ALE/AVD ALE
WE_B WE_B
RE_B RE_B
Refer the chip data 8-bit
IFC
sheet for IFC I/O voltage NAND flash
RB_B RDY/BSY_B
WP_B WP_B
ADDR N.C.
AD[0:7] IO[7:0]
AD[8:15] N.C.
Figure 25-58. IFC to 8-bit asynchronous NAND device interface
This figure shows connection of a 16-bit NAND flash to IFC. Commands and address
bytes appear on AD[8:15].
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1487
Initialization/Application information
CSn_B CE_B
CLE CLE
ALE/AVD ALE
WE_B WE_B
RE_B RE_B
16-bit
Refer the chip data
NAND Flash
IFC sheet for IFC I/O voltage
RB_B RDY/BSY_B
WP_B WP_B
Addr N.C.
AD[0:7] IO[15:8]
AD[8:15] IO[7:0]
Figure 25-59. IFC to 16-bit asynchronous NAND flash device interface
This figure shows a simple connection between an 8-bit port size NAND flash EEPROM
(in source synchronous mode) and the IFC. In NAND FCM mode, commands, address
bytes, and data are all transferred on AD[0:7].
CSn_B CE_B
CLE CLE
ALE ALE
RE_B W/R_B
WE_B CLK
8-bit source sync
IFC Refer the chip data NAND flash
sheet for IFC I/O voltage
RB_B RDY/BSY_B
WP_B WP_B
AD[0:7] IO [7:0]
AD[8:15] N.C.
DQS DQS
ADDR N.C.
Figure 25-60. IFC to 8-bit NVDDR NAND flash device interface
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1488 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
25.9.4.1.1 Switching to the synchronous interface
After coming out of reset and performing device initialization, by default the
asynchronous interface of the NAND device is activated.
To switch to the synchronous interface:
• Wait for OPC, if any previous operation is being executed on the NAND device.
• Program a FIR sequence (CMD0 -UA-WBCD-WFR - NOOP) that issues the SET
FEATURE command, followed by wait-for-ready, followed by NOOP.
• Issue the SET FEATURES (EFh) command. (CMD0)
• Write address 01h, which selects the timing mode. (UA)
• Write P1 with 1nh, where "n" is the timing mode used in the synchronous
interface (WBCD).
• Write P2-P4 as 00h-00h-00h. (WBCD)
• tWB time after the last data of the SET FEATURE command has been written the
device goes into busy state (RB_B is pulled low). After tITC time elapses, the device
enters ready state (RB_B transitions to high) and the NAND is now in source-
synchronous mode. It is required to poll for the OPC status bit before issuing any
new operation on the NAND device.
• Program the CSORn[NAND_MODE] field to 01h.
• To use ONFI timing parameters, write the desired timing mode value (0-5) with
which the NAND device is configured, to the CSOR_EXTn[ONFI_MODE] field.
This configures the FTIM registers, corresponding to the chip-select whose
ONFI_MODE field has been written to, for the source-synchronous device. The
values programmed in the FTIM registers are calculated based on the timing-mode
value programmed in CSOR_EXTn[ONFI_MODE], the clock divider value in the
DDR-CCR register, and the maximum permissible operating frequency (as per the
ONFI 2.2 spec) for the programmed timing mode. Also the
CSOR_EXTn[ONFI_TIM_PARAMS] should be set.
• To use the FTIM registers to program timing parameters, do not set the
ONFI_TIM_PARAMS bit.
25.9.4.1.2 Switching to the asynchronous interface
To activate the asynchronous NAND interface, once the NVDDR interface is active,
program the NAND_CSORn[NAND_MODE] to set the asynchronous mode.
The user should ensure that there is no activity on the NAND interface while
programming this register field. Then perform the following steps:
• Wait for OPC, if any previous operation is being executed on the NAND device.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1489
Initialization/Application information
• Program the CSORn[NAND_MODE] field to 00hh.
• Program FIR sequence (CMD0 -WFR - NOOP) that will issue the reset command
(FFh) to the NAND device using an asynchronous command cycle. tWB time after the
command is issued, the RB_B signal goes low indication the device is in busy state.
After tRST time, the device will be in ready state. The user should poll for the OPC
status bit before issuing any new operations on the NAND device.
Once the above FIR sequence is complete, the NAND device will be in asynchronous
mode and will be set to timing mode 0.
25.9.4.2 NOR flash connections
For 16-bit devices, ADDR[26] is used and ADDR[27] is irrelevant; however, for 8-bit
devices, ADDR[26:27] are necessary. If the bus width is 2 bytes wide, then ADDR[27] is
a don't care and would not be connected.
This figure shows the IFC-to-NOR device interface.
IFC 16-bit NOR device
AD[0:15] D[15:0]
D
AD[0:15]
Q A[26:11]
ALE/AVD LE
Latch
ADDR[16:26] A[10:0]
ADDR[27] NC
Muxed Address/Data
Unmuxed Address
Figure 25-61. IFC to 16-bit NOR device interface
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1490 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
IFC 8 Bit NOR Device
AD[0:15] D[7:0]
D
AD[0:15]
Q A[27:12]
ALE/AVD LE
Latch
Addr[16:27] A[11:0]
Muxed Address/Data
Unmuxed Address
Figure 25-62. IFC to 8-bit NOR device interface
25.9.5 Bus turnaround
Because the IFC uses multiplexed address and data, special consideration is given to
avoid bus contention at bus turnaround.
The following cases must be examined:
• Address phase after previous read
• Read-data phase after address phase
• Read-modify-write cycle for parity-protected memory banks
The bus does not change direction for the following cases, so no special attention is
required:
• Continued burst after the first beat
• Write-data phase after address phase
• Address phase after previous write
25.9.5.1 Address phase after previous read
During a read cycle, the memory/peripheral drives the bus and the bus transceiver drives
AD.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1491
Initialization/Application information
After the data has been sampled, the output drivers of the external device must be
disabled, which can take some time.
After the previous cycle ends, BCTL goes high and changes the direction of the bus
transceiver. The IFC then inserts a bus turnaround time (that is, TBCTL) to avoid
contention. The external device has now already placed its data signals in high impedance
and no bus contention occurs.
25.9.5.2 Read-data phase after address phase
During the address phase, AD actively drives the address and BCTL is high, driving the
bus transceivers in the same direction as during a write.
After the end of the address phase, BCTL goes low and changes the direction of the bus
transceiver.
25.9.5.3 Read-modify-write cycle for parity protected memory banks
Principally, a read-modify-write cycle is a read cycle immediately followed by a write
cycle. Because the write cycle has a new address phase in any case, this essentially is the
same as an address phase after a previous read.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1492 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
25.9.6 Interfacing to different port sizes
The IFC supports 8- 16-bit data port sizes.
However, the IFC requires that the portion of the data bus used for a transfer to or from a
particular port size be fixed. A 16-bit port must reside on AD[0:15], and an 8-bit port on
AD[0:7]. This figure shows the device connections on the data bus.
Interface Output Register
0 31 63
OP0 OP1 OP2 OP3 OP4 OP5 OP6 OP7
AD[0:7] AD[8:15]
16-Bit Port Size
OP0 OP1
OP2 OP3
OP4 OP5
OP6 OP7
8-Bit Port Size
OP0
OP7
Figure 25-63. Interface to different port-size devices
25.9.7 Command sequence examples for NAND flash EEPROM
To program the IFC and FCM for executing NAND flash command sequences, obtain
command codes and pause states from the relevant NAND flash device datasheet and
program into FCM configuration registers.
This section describes some common sequences for multi-gigabit NAND flash
EEPROMs; however, details should be verified against manufacturer's specific
programming data.
Throughout these examples, it is assumed that one or more banks of the IFC have been
configured under FCM control with base address, port size, ECC mode, and timing
parameters configured in accordance with the device's data sheet .
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1493
Initialization/Application information
25.9.7.1 NAND flash soft reset command sequence example
An example of configuring FCM to execute a soft reset command to a 2 KB-page NAND
flash is shown in this table.
This sequence does not require the use of the shared FCM buffer RAM. At the conclusion
of the sequence, IFC issues a command complete interrupt if interrupts are enabled.
Table 25-11. FCM register settings for soft reset
Register Initial contents Description
NAND_FCR0 FF00_0000h CMD0 = FFh = reset command; other commands unused
ROW0 - Unused
COL0 - Unused
NAND_BC - Unused
NAND_FSR - Unused
NAND_FIR0, 2400_0000h, OP0 = CMD0 = command 0;
NAND_FIR1,
0000_0000h, OP1-OP14 = NOOP
NAND_FIR2
0000_0000h
25.9.7.2 NAND flash read status command sequence example
An example of configuring FCM to execute a status read command to 2 KB-page NAND
flash is shown in this table.
This sequence does not require the use of the shared FCM buffer RAM, but reads the
NAND flash status into NAND_FSR.
At the conclusion of the sequence, the IFC issues a command complete interrupt if
interrupts are enabled.
Table 25-12. FCM register settings for status read
Register Initial contents Description
NAND_FCR0 7000_0000h CMD0 = 70h = read status command; other commands unused
ROW0 - Unused
COL0 - Unused
NAND_BC - Unused
NAND_FSR - Status returned in RS0
NAND_FIR0, 25C0_0000h, OP0 = CMD0 = command 0;
NAND_FIR1, 0000_0000h, OP1 = RDSTAT = read status to NAND_FSR;
NAND_FIR2 0000_0000h OP2-OP14 = NOOP
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1494 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
25.9.7.3 NAND flash read identification command sequence example
An example of configuring FCM to execute a status ID command to 2 KB-page NAND
flash is shown in this table.
This sequence uses the shared FCM buffer RAM to receive the bytes of ID during the
sequence.
At the conclusion of the sequence, IFC issues a command complete interrupt if interrupts
are enabled.
Table 25-13. FCM register settings for ID read
Register Initial contents Description
NAND_FCR0 9000_0000h CMD0 = 90h Read ID command; other commands unused
ROW3 Row address Locates the block and the page within that block to be accessed
(0000_0020h)
COL0 0000_0000h Locates the byte to be accessed within a given page
MS = 0
NAND_BC 0000_0004h BC = 4 to read the ONFI Signature (for ONFI devices)
NAND_FSR - Unused
NAND_FIR0, 2608_4000h, OP0 = CMD0 = command 0;
NAND_FIR1, 0000_0000h, OP1 = UA = Send row address programmed in row address register 3. Use
SRAM buffer 0 to store the read ID bytes;
NAND_FIR2 0000_0000h
OP2 = RB = Read BC bytes of data into the SRAM buffer 0;
OP3-OP14 = NOOP
The above sequence uses opcode UA to send the address stored in row address register 3.
This is done so that the data transfer, that is, the read data is stored in buffer 0 of the
internal SRAM. Thus, the UA could also be used for operations, such as read page
parameter, get feature, set feature, read unique ID always using buffer 0 of the internal
SRAM.
25.9.7.4 NAND flash page read command sequence example
An example of configuring FCM to execute a random page read command to 2-Kbytes
page NAND flash is shown in the table below.
This sequence reads an entire page (main and spare region) into the shared FCM buffer
RAM, checking ECC (if enabled) as it proceeds.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1495
Initialization/Application information
At the conclusion of the sequence, IFC will issue a command complete interrupt if
interrupts are enabled. Once the sequence has completed, the shared buffer (buffer 1 for
page index 5) and transfer error registers are valid.
Table 25-14. FCM register settings for page read
Register Initial contents Description
NAND_FCR0 0030_0000h CMD0 = 00h = random read address entry;
CMD1 = 30h = read page
ROW0 row address (for Locates the block and the page within that block to be accessed
example, 0000_0005h
locates page5 in block0)
COL0 0000_0000h Locates the byte to be accessed within a given page MS = 0
NAND_BC 0000_0000h BC = 0 to read entire 2112-byte page
NAND_FSR - unused
NAND_FIR0, 2411_4A68h, OP0 = CMD0 = command 0; OP1 = CA0 = column address; OP2 = RA0 =
NAND_FIR1,NAN 0000_0000h, page address; OP3 = CMD1 = command 1; OP4 = RBCD = read BC bytes of
D_FIR2 0000_0000h data into FCM buffer; OP5 - OP14 = NOOP
25.9.7.5 NAND flash program command sequence example
An example of configuring FCM to execute a program command to 2 KB-page NAND
flash is shown in this table.
This sequence writes an entire page (main and spare region) from the shared FCM buffer
RAM, generating ECC (if enabled) as it proceeds.
The shared buffer (buffer 1 for page index 5) must be initialized by software prior to
starting the sequence. At the conclusion of the sequence, the IFC issues a command
complete interrupt if interrupts are enabled. The status of the programming operation is
returned in NAND_FSR.
Note that operations specified by OP5 and OP6 (status read) should never be skipped
while programming a NAND flash device, because it may happen that a new command is
issued to the NAND flash device even when the device has not yet finished processing
the previous request. This may result in unpredictable behavior.
Table 25-15. FCM register settings for page program
Register Initial contents Description
NAND_FCR0 8070_1000h CMD0 = 80h = page address and data entry;
CMD1 = 70h = read status
CMD2 = 10h = program page;
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1496 NXP Semiconductors
Chapter 25 Integrated Flash Controller (IFC)
Table 25-15. FCM register settings for page program (continued)
Register Initial contents Description
ROW0 Row address (for example, Locates the block and the page within that block to be accessed
0000_0005h locates page5
in block0)
COL0 0000_0000h Locates the byte to be accessed within a given page
MS = 0
NAND_BC 0000_0000h BC = 0 to read entire 2112-byte page
NAND_FSR - Returns with AS0 holding program status
NAND_FIR0, 2411_592Ch, 49C0_0000h, OP0 = CMD0 = command 0; OP1 = CA0 = column address; OP2 = RA0 =
NAND_FIR1, 0000_0000h page address; OP3 = WBCD = write BC bytes of data from buffer; OP4 =
NAND_FIR2 CMD2 = command 2; OP5 = CW1 = wait on flash ready and issue command
1; OP6 = RDSTAT = read erase status into NAND_FSR; OP7-OP14 =
NOOP
25.9.7.6 Read status command during busy period of program/erase
operation
During program and erase operation, the device permits the user to read status during its
busy period.
To achieve this, use the sequence of commands in this table.
Table 25-16. FCM register settings for read status during program busy period
Register Initial contents Description
NAND_FCR0 8070_1000h CMD0 = 80h = page address and data entry;
CMD1 = 0x70 = read status
CMD2 = 10h = program page;
ROW0 row address Locates the block and the page within that block to be accessed
(for example, 0000_0005h
locates page5 in block0)
COL0 0000_0000h Locates the byte to be accessed within a given page
MS = 0
NAND_BC 0000_0000h BC = 0 to read entire 2112-byte page
NAND_FSR - Returns with AS0 holding program status
NAND_FIR0, 2411_592Ch, 49C00_000h, OP0 = CMD0 = command 0;
NAND_FIR1, 00000_000h
OP1 = CA0 = column address;
NAND_FIR2
OP2 = RA0 = page address;
OP3 = WBCD = write BC bytes of data from buffer;
OP4 = CMD2 = command 2;
OP5 = NWAIT = program NCFGR[NUM_WAIT] for tWB time.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1497
Initialization/Application information
Table 25-16. FCM register settings for read status during program busy period
Register Initial contents Description
OP6 = CMD1 = command 1;
OP7 = RDSTAT = read erase status into NAND_FSR;
OP8–OP14 = NOOP
In this sequence, use opcode (NWAIT, CMD1) instead of CW1 to issue a read status
during the device-busy phase. This is different from the sequence NAND flash program
command sequence example, where a read status is issued after the device becomes
ready.
25.9.7.7 Valid opcode transitions in the IFC
This table describes the valid opcode transitions.
Ensure that the FIR sequence is programmed using only valid opcode transitions.
Table 25-17. Supported opcode transitions (in FIR)
Current Next opcode supported
opcode
n=0-7, m=0-3
CMDn CAm/ RAm CMDn UA RBCD/ CWn WFR NWAIT NOOP
BTRD/
SBRD/
RDSTAT/
RB_B
CAm CAm/ RAm CMDn UA RDSTAT/ RB CWn WFR NWAIT NOOP
RAm RAm CMDn UA WBCD RDSTAT/R CWn WFR NWAIT NO
B OP
UAm RAm CMDn UA WBCD RDSTAT/R CWn WFR NWAIT NO
B OP
WBCD CMDn CWn WFR NWAIT NOOP
CWn CAm/ RAm CMDn UA RBCD/ CWn WFR NWAIT NOOP
BTRD/
SBRD/
RDSTAT/
RB_B
WFR CMDn RBCD/ NWAIT NOOP - - - -
SBRD
NWAIT CMDn CAm/ RAm UA WBCD RDSTAT/R CWn WFR NOOP
B
RBCD/ RDSTAT CMDn CWn CAm/ RAm NWAIT NOOP - -
BTRD/ SBRD/
RDSTAT/ RB
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1498 NXP Semiconductors
Chapter 26
Inter-Integrated Circuit (I2C)
26.1 The I2C module as implemented on the chip
This section provides details about how the I2C module is implemented on the chip.
26.1.1 LS1043A I2C module integration
The following table describes the I2C module integration into the chip:
Table 26-1. I2C module integration
Module Module Base address
I2C1 218_0000
I2C2 219_0000
I2C3 21A_0000
I2C4 21B_0000
Additionally, both modules have been integrated with identical parameters and
connections.
The remainder of this chapter refers to a single I2C module. Notes are included to
indicate variations for multiple instantiations.
26.1.2 LS1043A I2C module special consideration
The I2C module implements the following parameter settings in the chip:
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1499
Overview
Table 26-2. LS1043A I2C parameter settings
I2C parameters LS1043A parameter value
Stop mode support Yes. Refers to LPM20 low power mode of
the chip.
The table below provides the clock sources to each I2C module:
Table 26-3. LS1043A I2C clocking
Module LS1043A clocking source
I2C1 platform clock
I2C2 platform clock
I2C3 platform clock
I2C4 platform clock
26.2 Overview
This chapter describes the Inter-Integrated Circuit (I2C) bus module implemented on this
chip and presents the following topics:
• Introduction to I2C
• External signal descriptions
• Memory map and register definition
• Functional description
• Initialization/application information
26.3 Introduction to I2C
This section presents the following topics:
• Definition: I2C module
• Advantages of the I2C bus
• Module block diagram
• Features
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1500 NXP Semiconductors
Chapter 26 Inter-Integrated Circuit (I2C)
• Modes of operation
• Definition: I2C conditions
26.3.1 Definition: I2C module
The I2C module is a functional unit that provides a two-wire— serial data (SDA) and
serial clock (SCL) — bidirectional serial bus that provides a simple and efficient method
of data exchange between this chip and other devices, such as microcontrollers,
EEPROMs, real-time clock devices, analog-to-digital converters, and LCDs.
26.3.2 Advantages of the I2C bus
The synchronous, multiple-master two-wire I2C bus:
• Minimizes interconnections between devices
• Allows the connection of additional devices to the bus for expansion and system
development
• Includes collision detection and arbitration that prevent data corruption if two or
more masters attempt to control the bus simultaneously
• Does not require an external address decoder
26.3.3 Module block diagram
The following figure shows a block diagram of the I2C module.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1501
Introduction to I2C
Address DMA request IRQ Data bus
ADDR_DECODE DATA_MUX
CTRL_REG FREQ_REG ADDR_REG STATUS_REG DATA_REG
In/Out
Input
Data
Sync
Shift
Start
Register
Stop
Arbitration
Control
Clock Address
Control Compare
SCL SDA
Figure 26-1. I2C block diagram
26.3.4 Features
The I2C module has the following key features:
• Compatible with I2C bus standard1
• Operating speeds
• Up to 100 kbps in Standard Mode
• Up to 400 kbps in Fast Mode
1. Compliant with I2C 2.0 standard with the exception that HS (high speed) mode is not supported
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1502 NXP Semiconductors
Chapter 26 Inter-Integrated Circuit (I2C)
• Operation at higher baud rates (up to a maximum of module clock/20) with
reduced bus loading
• Actual baud rate dependent on the SCL rise time (which depends on external
pull-up resistor values and bus loading)
• Multi-master operation
• Software programmable for one of 256 different serial clock frequencies
• Software selectable acknowledge bit
• Interrupt driven byte-by-byte data transfer
• Arbitration lost interrupt with automatic mode switching from master to slave
• Calling address identification interrupt
• Start and stop signal generation/detection
• Repeated start signal generation
• Acknowledge bit generation/detection
• Bus busy detection
• Basic DMA interface
• Maximum communication length and the number of devices that can be connected
are limited by a maximum bus capacitance of 400 pF
26.3.5 Modes of operation
The I2C module supports the chip modes described in the following table.
Table 26-4. Chip modes supported by the I2C module
Chip mode Description Important notes
RUN Basic mode of operation —
DOZE A low-power mode that allows the system to turn The I2C module can enter this mode when there
off the clock depending on the state of an internal are no active transfers (active data between valid
bit START and STOP conditions) on the bus.
STOP The lowest-power mode that allows the chip to The I2C module can enter this mode when there
turn off all the clocks to the I2C module are no active transfers (active data between valid
START and STOP conditions) on the bus. See
STOP mode.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1503
Introduction to I2C
In addition to chip modes, the I2C module has several module-specific modes. These are
described in the following table.
Table 26-5. Module-specific modes supported by the I2C module
Module mode Description Important notes
Master mode The I2C module is the driver of the SDA line. • Do not use the I2C module's slave address
as a calling address.
• The I2C module cannot be a master and a
slave simultaneously.
Slave mode The I2C module is not the driver of the SDA line. • Enable the I2C module before a START
condition from a non-I2C master is
detected.
• By default the I2C module performs as a
slave receiver.
26.3.6 Definition: I2C conditions
The following table shows the I2C-specific conditions defined for the I2C module.
Table 26-6. I2C Conditions
Condition Description
START A condition that denotes the beginning of a new data transfer and awakens all slaves. Each data
transfer contains several bytes of data. It is defined as a high-to-low transition of SDA while SCL is
high, as shown in the following figure.
STOP A condition generated by the master to terminate a transfer and free the bus. It is defined as a low-
to-high transition of SDA while SCL is high, as shown in the following figure.
Repeated START A START condition that is generated without a STOP condition to terminate the previous transfer.
SDA
SCL
START condition STOP condition
Figure 26-2. START and STOP conditions
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1504 NXP Semiconductors
Chapter 26 Inter-Integrated Circuit (I2C)
26.4 External signal descriptions
This section presents the following topics:
• Signal overview
• Detailed external signal descriptions
26.4.1 Signal overview
The I2C module uses the Serial Data (SDA) and Serial Clock (SCL) signals as a
communication interconnect with other devices. The signal patterns driven on the SDA
signal represent address, data, or read/write information at different stages of the
protocol.
All devices connected to the SDA and SCL signals must have open-drain or open-
collector outputs. The logical AND function is performed on both signals with external
pull-up resistors. For the electrical characteristics of these signals, see the data sheet for
this chip.
26.4.2 Detailed external signal descriptions
The SDA and SCL signals are described in the following table.
Table 26-7. External signal descriptions
Signal Description
SCL Bidirectional serial clock line of the module, compatible with the I2C bus specification
SDA Bidirectional serial data line of the module, compatible with the I2C bus specification
26.5 Memory map and register definition
This section provides a detailed description of all memory-mapped registers in the I2C
module. It presents the following topics:
• Register accessibility
• Register figure conventions
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1505
Memory map and register definition
• I2C Bus Address Register (I2C_IBAD)
• I2C Bus Frequency Divider Register (I2C_IBFD)
• I2C Bus Control Register (I2C_IBCR)
• I2C Bus Status Register (I2C_IBSR)
• I2C Bus Data I/O Register (I2C_IBDR)
• I2C Bus Interrupt Config Register (I2C_IBIC)
26.5.1 Register accessibility
Address location 0x0007 is a reserved location, but access to this location will not
generate any bus error.
All the I2C registers are one byte wide. Reads and writes to these registers must be byte-
wide operations.
26.5.2 Register figure conventions
The register figures show the field structure using the conventions in the following figure.
R 0 1 R FIELD1 FIELD2 R
FIELD
W W W
Reserved bits Read-only fields Read/write fields
R 0 0 0 R FIELD
W FIELD1 FIELD2 W w1c
Write-only fields Write 1 to clear" field
(field will always read 0)
Figure 26-3. Register figure convention
The memory map for the I2C module is given below. The total address for each register is
the sum of the base address for the I2C module and the address offset for each register.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1506 NXP Semiconductors
Chapter 26 Inter-Integrated Circuit (I2C)
I2C memory map
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
218_0000 I2C Bus Address Register (I2C1_IBAD) 8 R/W 00h 26.5.3/1507
218_0001 I2C Bus Frequency Divider Register (I2C1_IBFD) 8 R/W 00h 26.5.4/1508
218_0002 I2C Bus Control Register (I2C1_IBCR) 8 R/W 80h 26.5.5/1508
218_0003 I2C Bus Status Register (I2C1_IBSR) 8 R/W 80h 26.5.6/1510
218_0004 I2C Bus Data I/O Register (I2C1_IBDR) 8 R/W 00h 26.5.7/1511
218_0005 I2C Bus Interrupt Config Register (I2C1_IBIC) 8 R/W 00h 26.5.8/1512
219_0000 I2C Bus Address Register (I2C2_IBAD) 8 R/W 00h 26.5.3/1507
219_0001 I2C Bus Frequency Divider Register (I2C2_IBFD) 8 R/W 00h 26.5.4/1508
219_0002 I2C Bus Control Register (I2C2_IBCR) 8 R/W 80h 26.5.5/1508
219_0003 I2C Bus Status Register (I2C2_IBSR) 8 R/W 80h 26.5.6/1510
219_0004 I2C Bus Data I/O Register (I2C2_IBDR) 8 R/W 00h 26.5.7/1511
219_0005 I2C Bus Interrupt Config Register (I2C2_IBIC) 8 R/W 00h 26.5.8/1512
21A_0000 I2C Bus Address Register (I2C3_IBAD) 8 R/W 00h 26.5.3/1507
21A_0001 I2C Bus Frequency Divider Register (I2C3_IBFD) 8 R/W 00h 26.5.4/1508
21A_0002 I2C Bus Control Register (I2C3_IBCR) 8 R/W 80h 26.5.5/1508
21A_0003 I2C Bus Status Register (I2C3_IBSR) 8 R/W 80h 26.5.6/1510
21A_0004 I2C Bus Data I/O Register (I2C3_IBDR) 8 R/W 00h 26.5.7/1511
21A_0005 I2C Bus Interrupt Config Register (I2C3_IBIC) 8 R/W 00h 26.5.8/1512
21B_0000 I2C Bus Address Register (I2C4_IBAD) 8 R/W 00h 26.5.3/1507
21B_0001 I2C Bus Frequency Divider Register (I2C4_IBFD) 8 R/W 00h 26.5.4/1508
21B_0002 I2C Bus Control Register (I2C4_IBCR) 8 R/W 80h 26.5.5/1508
21B_0003 I2C Bus Status Register (I2C4_IBSR) 8 R/W 80h 26.5.6/1510
21B_0004 I2C Bus Data I/O Register (I2C4_IBDR) 8 R/W 00h 26.5.7/1511
21B_0005 I2C Bus Interrupt Config Register (I2C4_IBIC) 8 R/W 00h 26.5.8/1512
26.5.3 I2C Bus Address Register (I2Cx_IBAD)
This register contains the address the I2C Bus will respond to when addressed as a slave.
This is not the address sent on the bus during the address transfer.
Address: Base address + 0h offset
Bit 7 6 5 4 3 2 1 0
Read 0
ADR
Write
Reset 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1507
Memory map and register definition
I2Cx_IBAD field descriptions
Field Description
7–1 Slave Address. Specific slave address to be used by the I2C Bus module.
ADR
NOTE: The default mode of I2C Bus is slave mode for an address match on the bus.
0 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
26.5.4 I2C Bus Frequency Divider Register (I2Cx_IBFD)
Address: Base address + 1h offset
Bit 7 6 5 4 3 2 1 0
Read IBC
Write
Reset 0 0 0 0 0 0 0 0
I2Cx_IBFD field descriptions
Field Description
IBC I-Bus Clock Rate. This field is used to prescale the bus clock for bit rate selection. See Clock rate and
IBFD settings.
26.5.5 I2C Bus Control Register (I2Cx_IBCR)
Address: Base address + 2h offset
Bit 7 6 5 4 3 2 1 0
Read 0
MDIS IBIE MSSL TXRX NOACK DMAEN IBDOZE
Write RSTA
Reset 1 0 0 0 0 0 0 0
I2Cx_IBCR field descriptions
Field Description
7 Module disable. This bit controls the software reset of the entire I2C Bus module.
MDIS
NOTE: If the I2C Bus module is enabled in the middle of a byte transfer, the interface behaves as follows:
slave mode ignores the current transfer on the bus and starts operating whenever a subsequent
start condition is detected. Master mode will not be aware that the bus is busy, hence if a start
cycle is initiated then the current bus cycle may become corrupt. This would ultimately result in
either the current bus master or the I2C Bus module losing arbitration, after which, bus operation
would return to normal.
0 The I2C Bus module is enabled. This bit must be cleared before any other IBCR bits have any effect
1 The module is reset and disabled. This is the power-on reset situation. When high, the interface is
held in reset, but registers can still be accessed. Status register bits (IBSR) are not valid when module
is disabled.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1508 NXP Semiconductors
Chapter 26 Inter-Integrated Circuit (I2C)
I2Cx_IBCR field descriptions (continued)
Field Description
6 I-Bus Interrupt Enable.
IBIE
0 Interrupts from the I2C Bus module are disabled. This does not clear any currently pending interrupt
condition.
1 Interrupts from the I2C Bus module are enabled. An I2C Bus interrupt occurs provided the IBIF bit in
the status register is also set.
5 Master/Slave mode select. When this bit is changed from 0 to 1, a START signal is generated on the bus
MSSL and the master mode is selected. When this bit is changed from 1 to 0, a STOP signal is generated and
the operation mode changes from master to slave. A STOP signal should be generated only if the IBIF flag
is set. This field is cleared without generating a STOP signal when the master loses arbitration.
0 Slave Mode
1 Master Mode
4 Transmit/Receive mode select. This bit selects the direction of master and slave transfers. When
TXRX addressed as a slave this bit should be set by software according to the SRW bit in the status register. In
master mode this bit should be set according to the type of transfer required. Therefore, for address
cycles, this bit will always be high.
0 Receive
1 Transmit
3 Data Acknowledge disable. This bit specifies the value driven onto SDA during data acknowledge cycles
NOACK for both master and slave receivers. The I2C module will always acknowledge address matches, provided
it is enabled, regardless of the value of NOACK.
NOTE: Values written to this bit are only used when the I2C Bus is a receiver, not a transmitter.
0 An acknowledge signal will be sent out to the bus at the 9th clock bit after receiving one byte of data
1 No acknowledge signal response is sent (i.e., acknowledge bit = 1)
2 Repeat Start. Writing a one to this bit will generate a repeated START condition on the bus, provided it is
RSTA the current bus master. This bit will always be read as a low. Attempting a repeated start at the wrong
time, if the bus is owned by another master, will result in loss of arbitration.
0 No effect
1 Generate repeat start cycle
1 DMA Enable. When this bit is set, the DMA Tx and Rx lines will be asserted when the I2C module requires
DMAEN data to be read or written to the data register. No Transfer Done interrupts will be generated when this bit
is set, however an interrupt will be generated if the loss of arbitration or addressed as slave conditions
occur. The DMA mode is only valid when the I2C module is configured as a Master and the DMA transfer
still requires CPU intervention at the start and the end of each frame of data. See the DMA Application
Information section for more details.
0 Disable the DMA TX/RX request signals
1 Enable the DMA TX/RX request signals
0 I-Bus Interface Stop in DOZE mode.
IBDOZE
If the IBDOZE mode is SET, the I 2 C module will enter DOZE mode when the DOZE signal is asserted, if
there are no current transactions on the bus. The I 2 C module would then signal to the system that the
clock can be shut down.
If the IBDOZE bit is cleared when the DOZE signal is asserted, the I 2 C Bus module clock remains alive,
and any current transactions continue as normal.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1509
Memory map and register definition
I2Cx_IBCR field descriptions (continued)
Field Description
0 I 2 C Bus module clock operates normally
1 Halt I 2 C Bus module clock generation (if DOZE mode signal asserted)
26.5.6 I2C Bus Status Register (I2Cx_IBSR)
Address: Base address + 3h offset
Bit 7 6 5 4 3 2 1 0
Read TCF IAAS IBB IBAL 0 SRW IBIF RXAK
Write w1c w1c
Reset 1 0 0 0 0 0 0 0
I2Cx_IBSR field descriptions
Field Description
7 Transfer complete.
TCF
While one byte of data is being transferred, this bit is cleared. It is set by the falling edge of the 9th clock of
a byte transfer.
NOTE: This bit is only valid during or immediately following a transfer to the I2C module or from the I2C
module.
0 Transfer in progress
1 Transfer complete
6 Addressed as a slave.
IAAS
When its own specific address (I-Bus Address Register) is matched with the calling address, this bit is set.
The CPU is interrupted provided the IBIE is set. Then the CPU needs to check the SRW bit and set the
TXRX field accordingly. Writing to the I-Bus Control Register clears this bit.
0 Not addressed
1 Addressed as a slave
5 Bus busy.
IBB
This bit indicates the status of the bus. When a START signal is detected, IBB is set. If a STOP signal is
detected, IBB is cleared and the bus enters idle state.
NOTE: Software must ensure that the I2C bus is idle by checking the IBSR[IBB] field (bus busy) before
switching to master mode and attempting a START cycle.
0 Bus is Idle
1 Bus is busy
4 Arbitration Lost.
IBAL
The arbitration lost bit (IBAL) is set by hardware when the arbitration procedure is lost. Arbitration is lost in
the following circumstances:
• SDA is sampled low when the master drives a high during an address or data transmit cycle.
• SDA is sampled low when the master drives a high during the acknowledge bit of a data receive
cycle.
• A start cycle is attempted when the bus is busy.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1510 NXP Semiconductors
Chapter 26 Inter-Integrated Circuit (I2C)
I2Cx_IBSR field descriptions (continued)
Field Description
• A repeated start cycle is requested in slave mode.
• A stop condition is detected when the master did not request it.
This bit must be cleared by software, by writing a one to it. A write of zero has no effect.
3 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
2 Slave Read/Write. When the IAAS bit is set, this bit indicates the value of the R/W command bit of the
SRW calling address sent from the master. This bit is only valid when the I-Bus is in slave mode, a complete
address transfer has occurred with an address match and no other transfers have been initiated. By
reading this field, the CPU can detect slave transmit/receive mode according to the command of the
master.
0 Slave receive, master writing to slave
1 Slave transmit, master reading from slave
1 I-Bus Interrupt Flag. The IBIF bit is set when one of the following conditions occurs:
IBIF • Arbitration lost (IBAL bit set)
• Byte transfer complete (TCF bit set and DMAEN bit not set)
• Addressed as slave (IAAS bit set)
• NoAck from Slave (MS & Tx bits set)
• I2C Bus going idle (IBB high-low transition and enabled by BIIE)
A processor interrupt request will be caused if the IBIE bit is set. This bit must be cleared by software, by
writing a one to it. A write of zero has no effect on this bit. In DMA mode (DMAEN set) a byte transfer
complete condition will not trigger the setting of IBIF. All other conditions still apply.
0 Received Acknowledge. This is the value of SDA during the acknowledge bit of a bus cycle. If the received
RXAK acknowledge bit (RXAK) is low, it indicates an acknowledge signal has been received after the completion
of 8 bits data transmission on the bus. If RXAK is high, it means no acknowledge signal is detected at the
9th clock. This bit is valid only after transfer is complete.
0 Acknowledge received
1 No acknowledge received
26.5.7 I2C Bus Data I/O Register (I2Cx_IBDR)
In master transmit mode, when data is written to the IBDR, a data transfer is initiated.
The most significant bit is sent first. In master receive mode, reading this register initiates
next byte data receiving. In slave mode, the same functions are available after an address
match has occurred.
NOTE
The IBCR[TXRX] field must correctly reflect the desired
direction of transfer in master and slave modes for the
transmission to begin. For instance, if the I2C is configured for
master transmit but a master receive is desired, then reading the
IBDR will not initiate the receive.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1511
Memory map and register definition
Reading the IBDR will return the most recent byte received while the I2C is configured in
either master receive or slave receive modes. The IBDR does not reflect every byte that is
transmitted on the I2C bus, nor can software verify that a byte has been written to the
IBDR correctly by reading it back.
In master transmit mode, the first byte of data written to IBDR following assertion of
MSSL is used for the address transfer and should comprise the calling address (in
position DATA[7:1]) concatenated with the required R/ W bit (in position D0).
NOTE
When the I2C
is configured in master mode and receiving data
from a slave that is transmitting data bytes on an irregular basis,
the master cannot know whether the data received in the IBDR
is the old latched data or the new data received from the slave.
To avoid this, 2 consecutive intermittent data bytes from slave
should be different.
Address: Base address + 4h offset
Bit 7 6 5 4 3 2 1 0
Read DATA
Write
Reset 0 0 0 0 0 0 0 0
I2Cx_IBDR field descriptions
Field Description
DATA Data transmitted or received
26.5.8 I2C Bus Interrupt Config Register (I2Cx_IBIC)
To program BIIE = 1, you must ensure that IBCR[MDIS] = 0.
Address: Base address + 5h offset
Bit 7 6 5 4 3 2 1 0
Read 0
BIIE BYTERXIE
Write
Reset 0 0 0 0 0 0 0 0
I2Cx_IBIC field descriptions
Field Description
7 Bus Idle Interrupt Enable bit. This config bit can be used to enable the generation of an interrupt once the
BIIE I2C bus becomes idle. Once this bit is set, an IBB high-low transition will set the IBIF bit. This feature can
be used to signal to the CPU the completion of a STOP on the I2C bus.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1512 NXP Semiconductors
Chapter 26 Inter-Integrated Circuit (I2C)
I2Cx_IBIC field descriptions (continued)
Field Description
0 Bus Idle Interrupts disabled
1 Bus Idle Interrupts enabled
6 Byte receive interrupt enable
BYTERXIE
This field is used to generate an interrupt every time the I2C master/slave receives a new byte. This
feature can be useful when an I2C master is receiving data from a slave that is transmitting on an irregular
basis.
BYTERXIE is updated only when the I2C is enabled (IBCR[MDIS]=0).
Reserved This field is reserved.
This read-only field is reserved and always has the value 0.
26.6 Functional description
This section presents the following topics:
• Notes about module operation
• Transactions
• Arbitration procedure
• Clock behavior
• Interrupts
• DMA interface
26.6.1 Notes about module operation
• The I2C module always performs as a slave receiver by default, unless explicitly
programmed to be a master or slave transmitter.
• When the I2C module is acting as a master, it must not try to call its own slave
address.
26.6.2 Transactions
This section presents the following topics:
• Protocol overview
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1513
Functional description
• Transaction protocol definitions
• High-level protocol steps
• START condition
• Slave address transmission
• Data transmission
• STOP condition
• Repeated START condition
26.6.2.1 Protocol overview
The following figure shows the behavior of SCL and SDA during a typical I2C
transaction.
MSB LSB MSB LSB
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
SDA AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W XXX D7 D6 D5 D4 D3 D2 D1 D0
START Calling address Read/ Ack Data byte No STOP
Write ack
MSB LSB MSB LSB
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
SDA AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W Data AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
START Calling address Read/ Ack Repeated New calling address Read/ No STOP
Write START Write ack
Figure 26-4. I2C transaction protocol
26.6.2.2 Transaction protocol definitions
This section defines several important terms presented in Figure 26-4.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1514 NXP Semiconductors
Chapter 26 Inter-Integrated Circuit (I2C)
Table 26-8. I2C definitions
Term Definition
START A START condition, as defined in Section 1.2.6, Definition: I2C conditions"
STOP A STOP condition, as defined in Section 1.2.6, Definition: I2C conditions"
Calling (slave) address A seven-bit address used to identify a slave on the I2C bus. The requirements for
specifying this address are presented in Section 1.5.2.3, I2C calling address
requirements."
Read/write (R/W) A bit that specifies the direction of the data transfer to the slave as follows:
• 0=The data is being transferred from the master to the slave ("write")
• 1=The data is being transferred from the slave to the master ("read")
Ack A bit that specifies the acknowledgement of a calling address, indicated by pulling SDA
low.
26.6.2.3 I2C calling address requirements
The calling addresses of the devices used on an I2C network are subject to the following
requirements:
• Each slave must have a unique calling address.
• A master must not transmit a calling address that is the same as its own slave
address.
26.6.2.4 High-level protocol steps
The I2C protocol conceptually supports two types of transfers, which are illustrated in
Figure 26-4. The significant steps in these transfers are presented in the following table.
Details of each of these steps are presented in subsequent sections.
Table 26-9. I2C high-level protocol steps
Standard Transfer Repeated START Transfer
1. START condition 1. START condition
2. Slave target or general call address transmission 2. Slave target or general call address transmission
3. Acknowledgment from slave 3. Acknowledgment from slave
4. Data transfer 4. Data transfer
5. STOP condition 5. Repeated START condition
6. (repeat Steps 1–4) 6. (repeat Steps 2–4 as needed)
7. STOP condition.
8. (repeat Steps 1–7)
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1515
Functional description
26.6.2.5 START condition
When the bus is free, that is, no master device is engaging the bus (both SCL and SDA
lines are at logical high), a master may initiate communication by sending a START
condition (see Definition: I2C conditions). This signal denotes the beginning of a new
data transfer (each data transfer may contain several bytes of data) and brings all slaves
out of their idle states.
See Clock rate and IBFD settings and I2C Bus Frequency Divider Register (I2C_IBFD)
for the associated timing requirements.
26.6.2.6 Slave address transmission
The master transmits the slave address on the next clock cycle after the START condition
(see START condition). The process of slave address transmission is presented in the
following table.
Table 26-10. Slave address transmission process
Step Action
1 The master transmits the seven-bit slave address.
2 The master transmits the R/W bit.
3 Each slave examines the transmitted address and compares it to its own. If the addresses match, the
slave device returns the acknowledge bit on the ninth SCL clock cycle.
4 The master waits for the acknowledge bit and determines the next step as follows:
• The acknowledge bit is set: The master must initiate a data transfer followed by either a STOP
condition or a repeated START condition.
• The acknowledge bit is cleared: The master must wait for SCL to return to logic zero.
26.6.2.7 Data transmission
A data transfer session has the following characteristics:
• Can transmit one or more bytes of data
• Awakens all slaves
• Proceeds on a byte-by-byte basis in the direction specified by the R/W bit sent by the
calling master
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1516 NXP Semiconductors
Chapter 26 Inter-Integrated Circuit (I2C)
The transmitted data is subject to the following requirements:
• Each data byte must consist of 8 bits.
• Data bits can be changed only while SCL is low and must be held stable while SCL
is high.
• One data bit is transmitted during one SCL clock pulse.
• The most significant bit (msb) must be transmitted first.
• Each data byte must be followed by an acknowledge bit on the ninth SCL clock
pulse.
If the slave receiver does not acknowledge the master, the SDA line must be left high by
the slave. The master can then generate a stop condition to abort the data transfer or a
START condition (repeated START) to begin a new calling.
If the master receiver does not acknowledge the slave transmitter after a byte of
transmission, the slave interprets that the end-of-data has been reached. Then the slave
releases the SDA line for the master to generate a STOP or a START condition.
26.6.2.8 STOP condition
The master can terminate the communication by generating a STOP condition (see
Definition: I2C conditions). It can do so even if the slave has generated an acknowledge,
at which point the slave must release the bus.
A master is not required to send a STOP condition at the end of every transfer. For more
information, see Repeated START condition.
See Clock rate and IBFD settings and I2C Bus Frequency Divider Register (I2C_IBFD)
for the associated timing requirements.
26.6.2.9 Repeated START condition
The I2C protocol also supports a repeated START condition, which can be generated
without a preceding STOP condition. A master device can use this condition to
communicate with another slave or with the same slave in a different mode without
releasing the bus. This condition is illustrated in the second timing diagram of Figure
26-4.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1517
Functional description
26.6.3 Arbitration procedure
The I2C bus is a true multi-master bus that allows more than one master to be connected
to it. If two or more masters try to control the bus at the same time, a clock
synchronization procedure determines the bus clock, for which the low period is equal to
the longest clock low period and the high is equal to the shortest one among the masters.
The relative priority of the contending masters is determined by a data arbitration
procedure. A bus master loses arbitration if it transmits logic "1" while another master
transmits logic "0". The losing masters immediately switch over to slave mode and stop
driving the SDA output. In this case, the transition from master to slave mode does not
generate a STOP condition. Meanwhile, a status bit is set by hardware to indicate loss of
arbitration.
26.6.4 Clock behavior
This section presents the following topics:
• Clock synchronization
• Clock stretching
• Handshaking
• Clock rate and IBFD settings
26.6.4.1 Clock synchronization
Due to the wired-AND logic on the SCL line, a high-to-low transition on the SCL line
affects all devices connected on the bus. The devices begin counting their low period
when the master drives the SCL line low. After a device has driven SCL low, it holds the
SCL line low until the clock high state is reached.
However, the change of low-to-high in a device clock may not change the state of the
SCL line if another device is still within its low period. Therefore, the synchronized clock
signal, SCL, is held low by the device with the longest low period. Devices with shorter
low periods enter a high wait state during this time (see the following figure). When all
devices concerned have counted off their low period, the synchronized SCL line is
released and pulled high. Then there is no difference between the devices' clocks and the
state of the SCL line, and all the devices begin counting their high periods. The first
device to complete its high period pulls the SCL line low again.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1518 NXP Semiconductors
Chapter 26 Inter-Integrated Circuit (I2C)
WAIT Start Counting High Period
SCL1
SCL2
SCL
Internal Counter Reset
Figure 26-5. I2C bus clock synchronization
26.6.4.2 Clock stretching
The clock synchronization mechanism can be used by slaves to slow down the bit rate of
a transfer. After the master has driven SCL low, the slave can drive SCL low for the
required period and then release it. If the slave SCL low period is greater than the master
SCL low period then the resulting SCL bus signal low period is stretched.
26.6.4.3 Handshaking
The clock synchronization mechanism can be used as a handshake in data transfer. Slave
devices may hold the SCL low after completion of one byte transfer (9 bits). In such
cases, it halts the bus clock and forces the master clock into wait state until the slave
releases the SCL line.
26.6.4.4 Clock rate and IBFD settings
26.6.4.4.1 Timing definitions
Table 26-11. Timing definitions relevant to clock rate and IBFD settings
Term Definition
SCL Divider The factor used to prescale the CPU clock for bit rate selection (see Figure 26-6 and
Table 26-12)
SCL period (CPU clock period) × (SCL Divider)
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1519
Functional description
Table 26-11. Timing definitions relevant to clock rate and IBFD settings (continued)
Term Definition
SCL Hold The required number of CPU clocks to generate a START or STOP condition (see
Figure 26-6 and Table 26-12)
SDA Hold See Figure 26-7 and Table 26-12
SDA
SCL Hold(start) SCL Hold(stop)
SCL
START condition STOP condition
Figure 26-6. SCL Divider and SDA Hold
SCL Divider
SCL
SDA Hold
SDA
Figure 26-7. SDA Hold time
26.6.4.4.2 Divider and hold values
Table 26-12. I2C divider and hold values
IBC SCL Divider (clocks) SDA Hold (clocks) SCL Hold (start) SCL Hold (stop)
(hex)
MUL=1 00 20 7 6 11
01 22 7 7 12
02 24 8 8 13
03 26 8 9 14
04 28 9 10 15
05 30 9 11 16
06 34 10 13 18
07 40 10 16 21
08 28 7 10 15
09 32 7 12 17
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1520 NXP Semiconductors
Chapter 26 Inter-Integrated Circuit (I2C)
Table 26-12. I2C divider and hold values (continued)
IBC SCL Divider (clocks) SDA Hold (clocks) SCL Hold (start) SCL Hold (stop)
(hex)
0A 36 9 14 19
0B 40 9 16 21
0C 44 11 18 23
0D 48 11 20 25
0E 56 13 24 29
0F 68 13 30 35
10 48 9 18 25
11 56 9 22 29
12 64 13 26 33
13 72 13 30 37
14 80 17 34 41
15 88 17 38 45
16 104 21 46 53
17 128 21 58 65
18 80 9 38 41
19 96 9 46 49
1A 112 17 54 57
1B 128 17 62 65
1C 144 25 70 73
1D 160 25 78 81
1E 192 33 94 97
1F 240 33 118 121
20 160 17 78 81
21 192 17 94 97
22 224 33 110 113
23 256 33 126 129
MUL=1 24 288 49 142 145
25 320 49 158 161
26 384 65 190 193
27 480 65 238 241
28 320 33 158 161
29 384 33 190 193
2A 448 65 222 225
2B 512 65 254 257
2C 576 97 286 289
2D 640 97 318 321
2E 768 129 382 385
2F 960 129 478 481
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1521
Functional description
Table 26-12. I2C divider and hold values (continued)
IBC SCL Divider (clocks) SDA Hold (clocks) SCL Hold (start) SCL Hold (stop)
(hex)
30 640 65 318 321
31 768 65 382 385
32 896 129 446 449
33 1024 129 510 513
34 1152 193 574 577
35 1280 193 638 641
36 1536 257 766 769
37 1920 257 958 961
38 1280 129 638 641
39 1536 129 766 769
3A 1792 257 894 897
3B 2048 257 1022 1025
3C 2304 385 1150 1153
3D 2560 385 1278 1281
3E 3072 513 1534 1537
3F 3840 513 1918 1921
MUL=2 40 40 14 12 22
41 44 14 14 24
42 48 16 16 26
43 52 16 18 28
44 56 18 20 30
45 60 18 22 32
46 68 20 26 36
47 80 20 32 42
48 56 14 20 30
49 64 14 24 34
MUL=2 4A 72 18 28 38
4B 80 18 32 42
4C 88 22 36 46
4D 96 22 40 50
4E 112 26 48 58
4F 136 26 60 70
50 96 18 36 50
51 112 18 44 58
52 128 26 52 66
53 144 26 60 74
54 160 34 68 82
55 176 34 76 90
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1522 NXP Semiconductors
Chapter 26 Inter-Integrated Circuit (I2C)
Table 26-12. I2C divider and hold values (continued)
IBC SCL Divider (clocks) SDA Hold (clocks) SCL Hold (start) SCL Hold (stop)
(hex)
56 208 42 92 106
57 256 42 116 130
58 160 18 76 82
59 192 18 92 98
5A 224 34 108 114
5B 256 34 124 130
5C 288 50 140 146
5D 320 50 156 162
5E 384 66 188 194
5F 480 66 236 242
60 320 34 156 162
61 384 34 188 194
62 448 66 220 226
63 512 66 252 258
64 576 98 284 290
65 640 98 316 322
66 768 130 380 386
67 960 130 476 482
68 640 66 316 322
69 768 66 380 386
6A 896 130 444 450
6B 1024 130 508 514
MUL=2 6C 1152 194 572 578
6D 1280 194 636 642
6E 1536 258 764 770
6F 1920 258 956 962
70 1280 130 636 642
71 1536 130 764 770
72 1792 258 892 898
73 2048 258 1020 1026
74 2304 386 1148 1154
75 2560 386 1276 1282
76 3072 514 1532 1538
77 3840 514 1916 1922
78 2560 258 1276 1282
79 3072 258 1532 1538
7A 3584 514 1788 1794
7B 4096 514 2044 2050
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1523
Functional description
Table 26-12. I2C divider and hold values (continued)
IBC SCL Divider (clocks) SDA Hold (clocks) SCL Hold (start) SCL Hold (stop)
(hex)
7C 4608 770 2300 2306
7D 5120 770 2556 2562
7E 6144 1026 3068 3074
7F 7680 1026 3836 3842
MUL=4 80 80 28 24 44
81 88 28 28 48
82 96 32 32 52
83 104 32 36 56
84 112 36 40 60
85 120 36 44 64
86 136 40 52 72
87 160 40 64 84
88 112 28 40 60
89 128 28 48 68
8A 144 36 56 76
8B 160 36 64 84
8C 176 44 72 92
8D 192 44 80 100
8E 224 52 96 116
8F 272 52 120 140
90 192 36 72 100
91 224 36 88 116
92 256 52 104 132
MUL=4 93 288 52 120 148
94 320 68 136 164
95 352 68 152 180
96 416 84 184 212
97 512 84 232 260
98 320 36 152 164
99 384 36 184 196
9A 448 68 216 228
9B 512 68 248 260
9C 576 100 280 292
9D 640 100 312 324
9E 768 132 376 388
9F 960 132 472 484
A0 640 68 312 324
A1 768 68 376 388
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1524 NXP Semiconductors
Chapter 26 Inter-Integrated Circuit (I2C)
Table 26-12. I2C divider and hold values (continued)
IBC SCL Divider (clocks) SDA Hold (clocks) SCL Hold (start) SCL Hold (stop)
(hex)
A2 896 132 440 452
A3 1024 132 504 516
A4 1152 196 568 580
A5 1280 196 632 644
A6 1536 260 760 772
A7 1920 260 952 964
A8 1280 132 632 644
A9 1536 132 760 772
AA 1792 260 888 900
AB 2048 260 1016 1028
AC 2304 388 1144 1156
AD 2560 388 1272 1284
AE 3072 516 1528 1540
AF 3840 516 1912 1924
30 2560 260 1272 1284
B1 3072 260 1528 1540
B2 3584 516 1784 1796
B3 4096 516 2040 2052
B4 4608 772 2296 2308
B5 5120 772 2552 2564
B6 6144 1028 3064 3076
B7 7680 1028 3832 3844
B8 5120 516 2552 2564
MUL=4 B9 6144 516 3064 3076
BA 7168 1028 3576 3588
BB 8192 1028 4088 4100
BC 9216 1540 4600 4612
BD 10240 1540 5112 5124
BE 12288 2052 6136 6148
BF 15360 2052 7672 7684
26.6.5 Interrupts
This section presents the following topics:
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1525
Functional description
• Interrupt vector
• Interrupt description
26.6.5.1 Interrupt vector
The I2C module uses only one interrupt vector.
Table 26-13. Interrupt summary
Interrupt Offset Vector Priority Source Description
I2C Interrupt — — — IBAL, TCF, IAAS, When any of IBAL, TCF or IAAS bits is set, an
IBB bits in IBSR interrupt may be caused based on Arbitration
register lost, Transfer Complete or Address Detect
conditions. If enabled by BIIE, the de-assertion of
IBB can also cause an interrupt, indicating that
the bus is idle.
26.6.5.2 Interrupt description
There are five types of internal interrupts in the I2C. The interrupt service routine can
determine the interrupt type by reading the Status register.
I2C Interrupt can be generated on the following events:
• Arbitration Lost condition (IBAL bit set)
• Byte Transfer condition (TCF bit set and DMAEN bit not set)
• Address Detect condition (IAAS bit set)
• No Acknowledge from slave received when expected
• Bus Going Idle (IBB bit not set)
The I2C interrupt is enabled by the IBCR[IBIE] bit. It must be cleared by writing '1' to
the IBIF bit in the interrupt service routine. The Bus Going Idle interrupt needs to be
additionally enabled by the IBIC[BIIE] bit.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1526 NXP Semiconductors
Chapter 26 Inter-Integrated Circuit (I2C)
26.6.6 STOP mode
This mode allows the software to put the I2C module in power-down state. Once the
STOP request is asserted, the I2C module comes to a graceful halt after completing all the
ongoing transactions.
As soon as the I2C module enters STOP mode:
• The I2C clock is disabled.
• No transaction can take place.
• All registers are inaccessible.
The I2C module enters this mode only after successfully completing the current ongoing
transaction, hence the low-power request is acknowledged once the STOP condition
occurs. The user must ensure that the bus is free when STOP is requested. To request
STOP for ongoing transmission the user must wait until the transmission is complete,
followed by clearing of the IBCR[TXRX] field. See the figure below for more details.
Figure 26-8. I2C stop mode behavior when master is receiving and slave is transmitting
26.6.7 DMA interface
A simple DMA interface is implemented so that the I2C can request data transfers with
minimal support from the CPU (see DMA application information). DMA mode is
enabled by setting bit 1 in the Control Register (IBCR).
The DMA interface is operational when the I2C module is configured for Master mode.
At least three bytes of data per frame must be transferred from/to the slave when using
DMA mode, although in practice it will only be worthwhile using the DMA mode when
there is a large number of data bytes to transfer per frame.
Two internal signals, TX request and RX request, are used to signal the DMA controller
when the I2C module requires data to be written or read from the data register.
Further details of the DMA interface can be found in the Initialization/application
information, of this document.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1527
Initialization/application information
26.7 Initialization/application information
This section presents the following topics:
• Recommended interrupt service flow
• General programming guidelines (for both master and slave mode)
• Programming guidelines specific to master mode
• Programming guidelines specific to slave mode
• DMA application information
26.7.1 Recommended interrupt service flow
The following figure shows a flowchart for the recommended I2C interrupt service
routine. Deviation from the flowchart may result in unpredictable I2C bus behavior.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1528 NXP Semiconductors
Chapter 26 Inter-Integrated Circuit (I2C)
Clear
IBIF
Y Master N
Mode
?
TX RX Y Arbitration
Tx/Rx
Lost
?
?
N
Last Byte
Clear IBAL
Transmitted Y
?
N
Last
N Y
RXAK=0 Byte To Be Read IAAS=1 IAAS=1
N Y
? ? ? ?
Y N Y N
Address Transfer Data Transfer
End Of Y
2nd Last (Read)
Y Addr Cycle Y SRW=1 TX/RX RX
Byte To Be Read
(Master Rx) ? ?
?
?
N N N (Write) TX
Y ACK From
Write Next Generate Set TX
Set NOACK = 1 Receiver
Byte To IBDR Stop Signal Mode ?
N
Tx Next Read Data
Write Data
Byte From IBDR
To IBDR
And Store
Switch To Set RX Switch To
Rx Mode Mode Rx Mode
Dummy Read Generate Read Data Dummy Read Dummy Read
From IBDR Stop Signal From IBDR From IBDR From IBDR
And Store
RTI
Figure 26-9. Recommended I2C interrupt service routine flowchart
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1529
Initialization/application information
26.7.2 General programming guidelines (for both master and
slave mode)
This section provides programming guidelines recommended for the I2C module in both
master and slave mode. It presents the following topics:
• Initializing the I2C module
• Software response after a transfer
26.7.2.1 Initializing the I2C module
The following table describes how to initialize the I2C module.
Table 26-14. I2C initialization procedure
Step Action
1 Use I2C Bus Frequency Divider Register (I2C_IBFD) to select the required division ratio to obtain SCL frequency
from the system clock.
2 Use I2C Bus Address Register (I2C_IBAD) to define the slave address.
3 Clear the MDIS field in I2C Bus Control Register (I2C_IBCR) to enable the I2C interface system.
4 Use I2C Bus Control Register (I2C_IBCR) to select Master/Slave mode, Transmit/Receive mode, and whether
interrupts are enabled or disabled.
5 (Optional) Use I2C Bus Interrupt Config Register (I2C_IBIC) to further refine the interrupt behavior.
26.7.2.2 Software response after a transfer
Transmission or reception of a byte will set the data transferring bit (TCF) to 1, which
indicates one byte communication is finished. The I2C Bus interrupt bit (IBIF) is set also;
an interrupt will be generated if the interrupt function is enabled during initialization by
setting the IBIE bit. The IBIF (interrupt flag) can be cleared by writing one (in the
interrupt service routine, if interrupts are used).
The TCF bit will be cleared to indicate data transfer in progress whenever data register is
written to in transmit mode, or during reading out from data register in receive mode. The
TCF bit should not be used as a data transfer complete flag as the flag timing is
dependent on a number of factors including the I2C bus frequency. This bit may not
conclusively provide an indication of a transfer complete situation. It is recommended
that transfer complete situations are detected using the IBIF flag.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1530 NXP Semiconductors
Chapter 26 Inter-Integrated Circuit (I2C)
Software may service the I2C I/O in the main program by monitoring the IBIF bit if the
interrupt function is disabled. Polling should monitor the IBIF bit rather than the TCF bit
since their operation is different when arbitration is lost.
When a "Transfer Complete" interrupt occurs at the end of the address cycle, the master
will always be in transmit mode, i.e. the address is transmitted. If master receive mode is
required, indicated by R/W bit sent with slave calling address, then the Tx/Rx bit at
Master side should be toggled at this stage. If Master does not receive an ACK from
Slave, then transmission must be re-initiated or terminated.
In slave mode, IAAS bit will get set in IBSR if Slave address (IBAD) matches the Master
calling address. This is an indication that Master-Slave data communication can now
start. During address cycles (IBSR[IAAS]=1), the SRW bit in the status register is read to
determine the direction of the subsequent transfer and the Tx/Rx bit is programmed
accordingly. For slave mode data cycles (IBSR[IAAS]=0), the SRW bit is not valid. The
Tx/Rx bit in the control register should be read to determine the direction of the current
transfer.
26.7.3 Programming guidelines specific to master mode
This section presents the following topics:
• Generating START
• Transmit/receive sequence
• Generating STOP
• Generating repeated START
• Loss of arbitration
26.7.3.1 Generating START
After completion of the initialization procedure, serial data can be transmitted by
selecting the 'master transmitter' mode. If the device is connected to a multi-master bus
system, the state of the I2C Bus Busy bit (IBB) must be tested to check whether the serial
bus is free.
If the bus is free (IBB=0), the start condition and the first byte (the slave address) can be
sent. The data written to the data register comprises the slave calling address and the
LSB, which is set to indicate the direction of transfer required from the slave.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1531
Initialization/application information
The bus free time (i.e., the time between a STOP condition and the following START
condition) is built into the hardware that generates the START cycle. Depending on the
relative frequencies of the system clock and the SCL period, it may be necessary to wait
until the I2C is busy after writing the calling address to the IBDR before proceeding with
the following instructions. This is illustrated in the following example.
An example of the sequence of events which generates the START signal and transmits
the first byte of data (slave address) is shown below:
while (IBSR[IBB]==1) // wait in loop for IBB flag to clear
IBCR[MS/MSL] and IBCR[]Tx/Rx] = 1 // master and transmit mode, that is,
// generate start condition
IBDR = calling_address // send the calling address to the data register
while (bit 5, IBSR ==0) // wait in loop for IBB flag to be set
26.7.3.2 Transmit/receive sequence
The following tables present the sequences for:
• Master transmit
• Master receive
• Slave transmit
• Slave receive
Table 26-15. Master transmit sequence
Step Action
a Use I2C Bus Frequency Divider Register (I2C_IBFD) to select the required division ratio to obtain SCL frequency
from Platform clock/2.
b Write 0 to the IBDIS field in I2C Bus Control Register (I2C_IBCR) to enable the I2C interface system.
c Use I2C Bus Control Register (I2C_IBCR) to select Master mode, Transmit mode, and interrupt enable.
d Write 0 to the IBIF field in I2C Bus Status Register (I2C_IBSR).
e Write data to I2C Bus Data I/O Register (I2C_IBDR).
f Observe changes in the TCF field of I2C Bus Status Register (I2C_IBSR) :
• When IBSR[TCF] becomes 0, the transfer is in progress.
• When IBSR[TCF] becomes 1, the transfer is complete.
g Wait until the IBIF field in I2C Bus Status Register (I2C_IBSR) becomes 1.
h Read the fields in I2C Bus Status Register (I2C_IBSR) to determine what happened:
• If TCF = 1, the transfer completed.
• If RXAK = 1, a No Acknowledge condition occurred.
• If IBB = 0, the bus transitioned from Busy to Idle state.
• If IBB = 1, you can ignore check of Arbitration Loss (IBAL = 1).
NOTE: You can ignore Address Detect (IAAS = 1) for master mode (it is valid only for slave mode).
i Examine the RXAK field in I2C Bus Status Register (I2C_IBSR) for an acknowledgment from the slave.
j Repeat steps d through i to transfer the next consecutive bytes of data.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1532 NXP Semiconductors
Chapter 26 Inter-Integrated Circuit (I2C)
Table 26-16. Master receive sequence
Step Action
a Follow steps a through i in Table 26-15 for address dispatch.
b Write 0 to the IBIF field in I2C Bus Status Register (I2C_IBSR).
c Write 0 to the TXRX field in I2C Bus Control Register (I2C_IBCR) to select Receive mode.
d Perform a dummy read of I2C Bus Data I/O Register (I2C_IBDR) to initiate the receive operation.
e Wait until the TCF field in I2C Bus Status Register (I2C_IBSR) becomes 1. (This proves that the transfer is
complete.)
f Wait until the IBIF field in I2C Bus Status Register (I2C_IBSR) becomes 1.
g Read the fields in I2C Bus Status Register (I2C_IBSR) to determine what happened:
• If TCF = 1, the reception completed.
• If IBB = 0, the bus transitioned from Busy to Idle state.
• If IBB = 1, you can ignore check of Arbitration Loss (IBAL = 1).
NOTE: You can ignore the No Acknowledge condition (RXAK = 1) for receive mode.
h Read I2C Bus Data I/O Register (I2C_IBDR) to determine the data received from the slave.
Table 26-17. Slave transmit sequence
Step Action
a Use I2C Bus Address Register (I2C_IBAD) to define the slave address.
b Write 0 to the IBDIS field in I2C Bus Control Register (I2C_IBCR) to enable the I2C interface system.
c Examine fields in I2C Bus Status Register (I2C_IBSR) as follows:
• If IAAS = 1, examine IBSR[SRW].
• If IAAS = 1 and SRW = 1, write 1 to IBCR[TXRX] to select Transmit mode.
d Write data to I2C Bus Data I/O Register (I2C_IBDR).
e Wait until the IBIF field in I2C Bus Status Register (I2C_IBSR) becomes 1.
f Wait until the RXAK field in I2C Bus Status Register (I2C_IBSR) becomes 0.
g Write 0 to the IBIF field in I2C Bus Status Register (I2C_IBSR).
h Repeat steps d through g for the next consecutive data transfers.
Table 26-18. Slave receive sequence
Step Action
a Use I2C Bus Address Register (I2C_IBAD) to define the slave address.
b Write 0 to the IBDIS field of I2C Bus Control Register (I2C_IBCR) to enable the I2C interface system.
c Examine fields in I2C Bus Status Register (I2C_IBSR) as follows:
• If IAAS = 1, examine IBSR[SRW].
• If IAAS = 1 and SRW = 0, write 0 to IBCR[TXRX] to select Receive mode.
d Write 0 to the IBIF field of I2C Bus Status Register (I2C_IBSR).
e Perform a dummy read of I2C Bus Data I/O Register (I2C_IBDR) to initiate the receive operation.
f Wait until the TCF field of I2C Bus Status Register (I2C_IBSR) becomes 1. (This proves that the transfer is
complete.)
g Wait until the IBIF field of I2C Bus Status Register (I2C_IBSR) becomes 1.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1533
Initialization/application information
Table 26-18. Slave receive sequence (continued)
Step Action
h Read the fields in I2C Bus Status Register (I2C_IBSR) to determine what happened:
• If TCF = 1, the reception completed.
• If IBB = 0, the bus transitioned from Busy to Idle state.
• If IBB = 1, you can ignore check of Arbitration Loss (IBAL = 1).
NOTE: You can ignore the No Acknowledge condition (RXAK = 1) for receive mode.
i Read I2C Bus Data I/O Register (I2C_IBDR) to determine the data received from the master.
26.7.3.3 Generating STOP
A data transfer ends with a STOP signal generated by the 'master' device. A master
transmitter can simply generate a STOP signal after all the data has been transmitted. The
following is an example showing how a STOP condition is generated by a master
transmitter.
if (tx_count == 0) or // check to see if all data bytes have been transmitted
(bit 0, IBSR == 1) { // or if no ACK generated
clear bit 5, IBCR // generate stop condition
}
else {
IBDR = data_to_transmit // write byte of data to DATA register
tx_count -- // decrement counter
} // return from interrupt
If a master receiver wants to terminate a data transfer, it must inform the slave transmitter
by not acknowledging the last byte of data which can be done by setting the NOACK bit
in IBCR before reading the 2nd last byte of data. Before reading the last byte of data, a
STOP signal must first be generated. The following is an example showing how a STOP
signal is generated by a master receiver.
rx_count -- // decrease the rx counter
if (rx_count ==1) // 2nd last byte to be read ?
bit 3, IBCR = 1 // disable ACK
if (rx_count == 0) // last byte to be read ?
bit 5, IBCR = 0 // generate stop signal
else
data_received = IBDR // read RX data and store
26.7.3.4 Generating repeated START
At the end of data transfer, if the master still wants to communicate on the bus, it can
generate another START signal followed by another slave address without first
generating a STOP signal. A program example is as shown.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1534 NXP Semiconductors
Chapter 26 Inter-Integrated Circuit (I2C)
bit 2, IBCR = 1 // generate another start (restart)
IBDR == calling_address // transmit the calling address
26.7.3.5 Loss of arbitration
If several masters try to engage the bus simultaneously, only one master wins and the
others lose arbitration. The devices that lost arbitration are immediately switched to slave
mode by the hardware. Their data output to the SDA line is stopped, but SCL is still
generated until the end of the byte during which arbitration was lost. An interrupt occurs
at the falling edge of the ninth clock of this transfer with IBAL=1 and MS/SL=0. If one
master attempts to start transmission, while the bus is being engaged by another master,
the hardware will inhibit the transmission, switch the MS/SL bit from 1 to 0 without
generating a STOP condition, generate an interrupt to CPU, set the IBAL to indicate that
the attempt to engage the bus is failed, and not set the TCF due to the loss of data during
arbitration. When considering these cases, the slave service routine should test the IBAL
first and the software should clear the IBAL bit if it is set.
26.7.4 Programming guidelines specific to slave mode
In the slave interrupt service routine, the module addressed as slave bit (IAAS) should be
tested to check if a calling of its own address has just been received. If IAAS is set,
software should set the transmit/receive mode select bit (Tx/Rx bit of IBCR) according to
the R/W command bit (SRW). Writing to the IBCR clears IAAS automatically. Note that
the only time IAAS is read as set is from the interrupt at the end of the address cycle
where an address match occurred. Interrupts resulting from subsequent data transfers will
have IAAS cleared. A data transfer may now be initiated by writing information to IBDR
for slave transmits or dummy reading from IBDR in slave receive mode. The slave will
drive SCL low in-between byte transfers, SCL is released when the IBDR is accessed in
the required mode.
In slave transmitter routine, the received acknowledge bit (RXAK) must be tested before
transmitting the next byte of data. Setting RXAK means an "end of data" signal from the
master receiver, after which it must be switched from transmitter mode to receiver mode
by software. A dummy read then releases the SCL line so that the master can generate a
STOP signal.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1535
Initialization/application information
26.7.5 DMA application information
The DMA interface on the I2C is not completely autonomous and requires intervention
from the CPU to start and to terminate the frame transfer. DMA mode is only valid for
Master transmit and Master receive modes. Software must ensure that the DMAEN field
in I2C Bus Control Register (I2C_IBCR) is not set when the I2C module is configured in
slave mode.
The DMA controller must only transfer one byte of data per Tx/Rx request. This is
because there is no FIFO on the I2C block.
The CPU should also keep the I2C interrupt enabled during a DMA transfer to detect the
arbitration lost condition and take action to recover from this situation. The DMAEN
field in I2C Bus Control Register (I2C_IBCR) works as a disable for the transfer
complete interrupt. This means that during normal transfers (no errors) there will always
be either an interrupt or a request to the DMA controller, depending on the setting of the
DMAEN field. All error conditions will trigger an interrupt and require CPU
intervention. The address match condition will not occur in DMA mode as the I2C should
never be configured for slave operation.
The following sections detail how to set up a DMA transfer and what intervention is
required from the CPU. It is assumed that the system DMA controller is capable of
generating an interrupt after a certain number of DMA transfers have taken place.
The sections present the following topics:
• DMA mode, master transmit
• DMA mode, master reception
• Exiting DMA mode, system requirement considerations
26.7.5.1 DMA mode, master transmit
The following flow diagram details exactly the operation for using a DMA controller to
transmit "n" data bytes to a slave. The first byte (the slave calling address) is always
transmitted by the CPU. All subsequent data bytes (apart from the last data byte) can be
transferred by the DMA controller. The last data byte must be transferred by the CPU.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1536 NXP Semiconductors
Chapter 26 Inter-Integrated Circuit (I2C)
Config I2C for
Master TX
S ta rt
G e n e ra te d
C P U s e ts
IB C R [D M A E N ]
C P U w rite s c a llin g
a d d re s s to sla ve
in te rru p t
g e n e ra te d
yes C P U h a n d le s
A rb L o st o r
N o ack? co n d itio n
no
D M A re q u e s t
g e n e ra te d
no
D M A w rite s 1
b y te o f d a ta
D M A w ritte n
(n -1 ) b y te s o f
d a ta ?
yes
C P U c le a rs
IB C R [D M A E N ]
in te rru p t
g e n e ra te d
C P U w rite s la s t
d a ta b y te
in te rru p t
g e n e ra te d
C P U c le a rs S to p
M S /S L b it in C R g e n e ra te d
Figure 26-10. Flow-Chart of DMA mode master transmit
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1537
Initialization/application information
26.7.5.2 DMA mode, master reception
The following flow diagram details the exact operation for using a DMA controller to
receive "n" data bytes from a slave. The first byte (the slave calling address) is always
transmitted by the CPU. All subsequent data bytes (apart from the two last data bytes)
can be read by the DMA controller. The last two data bytes must be transferred by the
CPU.
C o n fig I 2 C fo r
M a s te r R X
S ta rt
G e n e ra te d
C P U w rite s ca llin g
a d d re s s to s la v e
in te rru p t
g e n e ra te d
yes C P U h a n d le s
A rb L o st o r
N o ack? c o n d itio n
no
S to p
g e n e ra te d
C P U se ts T X /R X
to R X
C P U c le a rs
M S /S L b it in C R
CPU: dum m y
re a d o f D A T A re g
C P U re a d s la st
d a ta b y te
C P U s e ts
IB C R [D M A E N ]
in te rru p t
g e n e ra te d
S la v e T X o n e S la ve T X la s t
b y te o f d a ta d a ta b y te
D M A re q u e st
g e n e ra te d
C P U se ts
no
D M A re a d s b yte TXACK
o f d a ta
C P U re a d s n -1
D M A re a d d a ta
(n -2 ) b y te s o f
d a ta ?
in te rru p t
yes g e n e ra te d
C P U cle a rs S la ve T X n -1
IB C R [D M A E N ] d a ta b y te
Figure 26-11. Flow-Chart of DMA mode master receive
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1538 NXP Semiconductors
Chapter 26 Inter-Integrated Circuit (I2C)
26.7.5.3 Exiting DMA mode, system requirement considerations
As described above, the final transfers of both TX and RX transfers need to be handled
via interrupt by the CPU. To change from DMA to interrupt driven transfers in the I2C
module, you have to disable the DMAEN bit in the IBCR register. The trigger to exit the
DMA mode is that the programmed DMA Transfer Control Descriptor (TCD) has
completed all its transfers to/from the I2C module.
After the last DMA write (TX mode) to the I2C the module will immediately start the
next I2C-bus transfer. The same is true for receive mode. After the DMA read from the
IBDR register the module initiates the next I2C-bus transfer. This results in two possible
scenarios in the DMA mode exiting scheme.
1. Fast reaction
The DMAEN bit is cleared before the next I2C-bus transfer completes. In this case
the module will raise an interrupt request to the CPU which can be serviced
normally.
2. Slow reaction
The DMAEN bit is cleared after the next I2C-bus transfer has already completed. In
this case, the module will not raise an interrupt request to the CPU. Instead the TCF
bit can be read to determine that the transfer completed and the module is ready for
further transfer.
What is fast/slow reaction?
The reaction time TR for the system to disable DMAEN after the last DMA controller
access to the I2C is the time required for one byte transfer over the I2C. For 'fast reaction'
the disabling has to occur before the 9th bit of the data transfer which is the ACK bit. So
the time available is eight times the SCL period.
In fast mode, with 400kbit/s, TSCL is 2.5µs, so TR is 20µs.
Depending on the system and DMA controller there are different possibilities for the de-
assertion of DMAEN. Three options are:
1. CPU intervention via Interrupt
The DMA controller is programmed to signal an interrupt to the CPU which is then
responsible for the de-assertion of DMAEN. This scheme should be supported by
most systems but it can result in a slow reaction time if other higher priority
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1539
Initialization/application information
interrupts interfere. Therefore the interrupt handling routine can become complicated
as it has to check which of the two cases happened (check TCF bit) and act
accordingly. In case of slow reaction you can force an interrupt for the I2C in the
interrupt controller to have the further transfer handled by the normal I2C interrupt
routine.
Note
The use of nested interrupts can still cause potential issues
in this scenario, if someone tries to stall the DMA interrupt
between the de-assertion and DMAEN bit and checks the
TCF bit.
2. DMA channel linking
If the Transfer control descriptor in the DMA controller that performs the data
transfer is linked to another channel that does a write to IBCR to disable the
DMAEN field, this might probably be the fastest system solution, but it uses two
DMA channels.
Note
Here you have to make sure on system level that no higher
priority DMA requests occur between the two linked TCDs
as those could again create a scenario of slow reaction.
3. DMA scatter/gather process
If the Transfer control descriptor in the DMA controller that performs the data
transfer has the scatter/gather feature activated, this feature will initiate a reload of
another TCD from system RAM after the completion of the first TCD. The new TCD
will have its start bit already set and immediately start the required write to the IBCR
to disable the DMAEN field. This TCD also has scatter/gather activated and is
programmed to reload the initial TCD upon completion, bringing the system back
into a "ready-for-I2C-transfer" state. The advantage over the two other solutions is
that this requires neither CPU intervention nor a second DMA channel. This comes at
the cost of 64 bytes RAM (two TCDs), some system bus transfer overhead and a
little increase in application code complexity.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1540 NXP Semiconductors
Chapter 26 Inter-Integrated Circuit (I2C)
Note
Here you have to make sure at system level that no higher
priority DMA requests occur during the scatter/gather
process, as those could again create a scenario of slow
reaction.
Example latencies for a 32 MHz system with a full speed 32-bit AHB bus and an I2C
connected via half speed IPI bus:
• Accessing the I2C from the DMA controller via IPI bus typically requires four cycles
(consecutive accesses to the I2C could be faster):
4×TIPI = 4/16 MHz = 250 ns
• Reloading a new TCD (8 x 32-bit) via AHB to the DMA controller (scatter/gather
process):
8×TAHD = 8/32 MHz = 250 ns
Example latencies for a 150 MHz system with a full speed 32-bit AHB bus and an I2C
connected via half speed IPI bus:
• Accessing the I2C from the DMA controller via IPI bus typically requires four cycles
(consecutive accesses to the I2C could be faster):
4×TIPI = 4/150 MHz = 26.6 ns
• Reloading a new TCD (4 x 64-bit) via AHB to the DMA controller (scatter/gather
process):
4×TAHD = 4/150 MHz = 26.6 ns
With the DMA scatter/gather process the required IBCR access can be done in 0.5 µs,
leaving a large margin of 19.5 µs for additional system delays. In this way, the slow
reaction case can be prevented. The system user needs to decide which usage model best
suits his overall requirement.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1541
Initialization/application information
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1542 NXP Semiconductors
Chapter 27
Low Power Universal asynchronous receiver/
transmitter (LPUART)
27.1 LPUART module integration
The following table describes the LPUART module integration into the chip:
Table 27-1. LPUART module integration
Module Module Base address
LPUART1 295_0000
LPUART2 296_0000
LPUART3 297_0000
LPUART4 298_0000
LPUART5 299_0000
LPUART6 29A_0000
Additionally:
• All modules have been integrated with identical parameters.
• The hardware flow control (CTS/RTS) is supported only on LPUART1, LPUART2,
and LPUART3.
• Selectable IrDA 1.4 return-to-zero-inverted (RZI) format is supported only on
LPUART1, LPUART2, and LPUART3.
• All LPUART interrupts from a single LPUART module are ORed together before
feeding to the GIC interrupt controller. Therefore, GIC has one interrupt port for
each LPUART instance.
The remainder of this chapter refers to a single LPUART module. Notes are included to
indicate variations for multiple instantiations.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1543
Chip LPUART signals
27.2 Chip LPUART signals
The following table lists the SoC signal names and their corresponding LPUART module
signal names used in this chapter:
Table 27-2. LPUART signals
Signal name LPUART module signal
LPUARTn_SOUT LPUART_TX
LPUARTn_SIN LPUART_RX
LPUARTn_RTS_B LPUART_RTS
LPUARTn_CTS_B LPUART_CTS
27.3 Chip LPUART module special consideration
The LPUART module implements the following parameter settings in the chip:
Table 27-3. LPUART parameter settings
LPUART parameters LS1043A parameter value
DATA_WD 32
TXFIFO_SZ 4
RXFIFO_SZ 4
Stop mode support Yes. Refers to the LPM20 low power mode
of the chip.
Doze mode support No
The following table provides the clock source for each LPUART module:
Table 27-4. LPUART clocking
LPUART module Clock source
LPUART1 SYS_REF_CLK
LPUART2 platform clock/2
LPUART3 platform clock/2
LPUART4 platform clock/2
LPUART5 platform clock/2
LPUART6 platform clock/2
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1544 NXP Semiconductors
Chapter 27 Low Power Universal asynchronous receiver/transmitter (LPUART)
27.4 Introduction
27.4.1 Features
Features of the LPUART module include:
• Full-duplex, standard non-return-to-zero (NRZ) format
• Programmable baud rates (13-bit modulo divider) with configurable oversampling
ratio from 4x to 32x
• Transmit and receive baud rate can operate asynchronous to the bus clock:
• Baud rate can be configured independently of the bus clock frequency
• Supports operation in Stop modes
• Interrupt, DMA or polled operation:
• Transmit data register empty and transmission complete
• Receive data register full
• Receive overrun, parity error, framing error, and noise error
• Idle receiver detect
• Active edge on receive pin
• Break detect supporting LIN
• Receive data match
• Hardware parity generation and checking
• Programmable 8-bit, 9-bit or 10-bit character length
• Programmable 1-bit or 2-bit stop bits
• Three receiver wakeup methods:
• Idle line wakeup
• Address mark wakeup
• Receive data match
• Automatic address matching to reduce ISR overhead:
• Address mark matching
• Optional 13-bit break character generation / 11-bit break character detection
• Selectable transmitter output and receiver input polarity
• Hardware flow control support for request to send (RTS) and clear to send (CTS)
signals
• Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse
width
• Independent FIFO structure for transmit and receive
• Separate configurable watermark for receive and transmit requests
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1545
Introduction
27.4.2 Modes of operation
27.4.2.1 Stop mode
The LPUART will remain functional during Stop mode, provided the asynchronous
transmit and receive clock remains enabled. The LPUART can generate an interrupt or
DMA request to cause a wakeup from Stop mode.
27.4.2.2 Wait mode
The LPUART can be configured to Stop in Wait modes, when the DOZEEN bit is set.
The transmitter and receiver will finish transmitting/receiving the current word.
27.4.3 Signal Descriptions
Signal Description I/O
LPUART_TX Transmit data. This pin is normally an I/O
output, but is an input (tristated) in single
wire mode whenever the transmitter is
disabled or transmit direction is
configured for receive data.
LPUART_RX Receive data. I
LPUART_CTS Clear to send. I
LPUART_RTS Request to send. O
27.4.4 Block diagram
The following figure shows the transmitter portion of the LPUART.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1546 NXP Semiconductors
Chapter 27 Low Power Universal asynchronous receiver/transmitter (LPUART)
Internal Bus
(Write-Only)
LOOPS
ASYNCH
MODULE LPUART_D – Tx Buffer RSRC
CLOCK
Loop
To Receive
BAUD 11-BIT Transmit Shift Register Control
M Data In
Divider
Start
Stop
To TxD Pin
H 8 7 6 5 4 3 2 1 0 L
OSR
Divider
lsb
SHIFT DIRECTION
TXINV
Load From LPUARTx_D
Preamble (All 1s)
Break (All 0s)
Shift Enable
T8
PE Parity
Generation
PT
LPUART Controls TxD
TE
SBK TO TxD
Transmit Control
TxD Direction Pin Logic
TXDIR
BRK13
TDRE
TIE
Tx Interrupt
TC
Request
TCIE
Figure 27-1. LPUART transmitter block diagram
The following figure shows the receiver portion of the LPUART.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1547
Register definition
INTERNAL BUS
SBR12:0 DATA BUFFER
ASYNCH
MODULE BAUDRATE
START
CLOCK GENERATOR VARIABLE 12-BIT RECEIVE M
STOP
SHIFT REGISTER M10
LBKDE
RE RECEIVE MSBF
RAF CONTROL
RXINV
SHIFT DIRECTION
RxD
LOOPS
RECEIVER
RSRC SOURCE
CONTROL PE PARITY WAKEUP
PT LOGIC LOGIC
From Transmitter
RxD DMA Requests
ACTIVE EDGE IRQ / DMA
DETECT LOGIC IRQ Requests
Figure 27-2. LPUART receiver block diagram
27.5 Register definition
The LPUART includes registers to control baud rate, select LPUART options, report
LPUART status, and for transmit/receive data. Access to an address outside the valid
memory map will generate a bus error.
LPUART memory map
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
295_0000 LPUART Baud Rate Register (LPUART1_BAUD) 32 R/W 0F00_0004h 27.5.1/1550
295_0004 LPUART Status Register (LPUART1_STAT) 32 R/W 00C0_0000h 27.5.2/1552
295_0008 LPUART Control Register (LPUART1_CTRL) 32 R/W 0000_0000h 27.5.3/1556
295_000C LPUART Data Register (LPUART1_DATA) 32 R/W 0000_0000h 27.5.4/1560
295_0010 LPUART Match Address Register (LPUART1_MATCH) 32 R/W 0000_0000h 27.5.5/1561
295_0014 LPUART Modem IrDA Register (LPUART1_MODIR) 32 R/W 0000_0000h 27.5.6/1562
295_0018 LPUART FIFO Register (LPUART1_FIFO) 32 R/W See section 27.5.7/1564
295_001C LPUART Watermark Register (LPUART1_WATER) 32 R/W 0000_0000h 27.5.8/1566
296_0000 LPUART Baud Rate Register (LPUART2_BAUD) 32 R/W 0F00_0004h 27.5.1/1550
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1548 NXP Semiconductors
Chapter 27 Low Power Universal asynchronous receiver/transmitter (LPUART)
LPUART memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
296_0004 LPUART Status Register (LPUART2_STAT) 32 R/W 00C0_0000h 27.5.2/1552
296_0008 LPUART Control Register (LPUART2_CTRL) 32 R/W 0000_0000h 27.5.3/1556
296_000C LPUART Data Register (LPUART2_DATA) 32 R/W 0000_0000h 27.5.4/1560
296_0010 LPUART Match Address Register (LPUART2_MATCH) 32 R/W 0000_0000h 27.5.5/1561
296_0014 LPUART Modem IrDA Register (LPUART2_MODIR) 32 R/W 0000_0000h 27.5.6/1562
296_0018 LPUART FIFO Register (LPUART2_FIFO) 32 R/W See section 27.5.7/1564
296_001C LPUART Watermark Register (LPUART2_WATER) 32 R/W 0000_0000h 27.5.8/1566
297_0000 LPUART Baud Rate Register (LPUART3_BAUD) 32 R/W 0F00_0004h 27.5.1/1550
297_0004 LPUART Status Register (LPUART3_STAT) 32 R/W 00C0_0000h 27.5.2/1552
297_0008 LPUART Control Register (LPUART3_CTRL) 32 R/W 0000_0000h 27.5.3/1556
297_000C LPUART Data Register (LPUART3_DATA) 32 R/W 0000_0000h 27.5.4/1560
297_0010 LPUART Match Address Register (LPUART3_MATCH) 32 R/W 0000_0000h 27.5.5/1561
297_0014 LPUART Modem IrDA Register (LPUART3_MODIR) 32 R/W 0000_0000h 27.5.6/1562
297_0018 LPUART FIFO Register (LPUART3_FIFO) 32 R/W See section 27.5.7/1564
297_001C LPUART Watermark Register (LPUART3_WATER) 32 R/W 0000_0000h 27.5.8/1566
298_0000 LPUART Baud Rate Register (LPUART4_BAUD) 32 R/W 0F00_0004h 27.5.1/1550
298_0004 LPUART Status Register (LPUART4_STAT) 32 R/W 00C0_0000h 27.5.2/1552
298_0008 LPUART Control Register (LPUART4_CTRL) 32 R/W 0000_0000h 27.5.3/1556
298_000C LPUART Data Register (LPUART4_DATA) 32 R/W 0000_0000h 27.5.4/1560
298_0010 LPUART Match Address Register (LPUART4_MATCH) 32 R/W 0000_0000h 27.5.5/1561
298_0014 LPUART Modem IrDA Register (LPUART4_MODIR) 32 R/W 0000_0000h 27.5.6/1562
298_0018 LPUART FIFO Register (LPUART4_FIFO) 32 R/W See section 27.5.7/1564
298_001C LPUART Watermark Register (LPUART4_WATER) 32 R/W 0000_0000h 27.5.8/1566
299_0000 LPUART Baud Rate Register (LPUART5_BAUD) 32 R/W 0F00_0004h 27.5.1/1550
299_0004 LPUART Status Register (LPUART5_STAT) 32 R/W 00C0_0000h 27.5.2/1552
299_0008 LPUART Control Register (LPUART5_CTRL) 32 R/W 0000_0000h 27.5.3/1556
299_000C LPUART Data Register (LPUART5_DATA) 32 R/W 0000_0000h 27.5.4/1560
299_0010 LPUART Match Address Register (LPUART5_MATCH) 32 R/W 0000_0000h 27.5.5/1561
299_0014 LPUART Modem IrDA Register (LPUART5_MODIR) 32 R/W 0000_0000h 27.5.6/1562
299_0018 LPUART FIFO Register (LPUART5_FIFO) 32 R/W See section 27.5.7/1564
299_001C LPUART Watermark Register (LPUART5_WATER) 32 R/W 0000_0000h 27.5.8/1566
29A_0000 LPUART Baud Rate Register (LPUART6_BAUD) 32 R/W 0F00_0004h 27.5.1/1550
29A_0004 LPUART Status Register (LPUART6_STAT) 32 R/W 00C0_0000h 27.5.2/1552
29A_0008 LPUART Control Register (LPUART6_CTRL) 32 R/W 0000_0000h 27.5.3/1556
29A_000C LPUART Data Register (LPUART6_DATA) 32 R/W 0000_0000h 27.5.4/1560
29A_0010 LPUART Match Address Register (LPUART6_MATCH) 32 R/W 0000_0000h 27.5.5/1561
29A_0014 LPUART Modem IrDA Register (LPUART6_MODIR) 32 R/W 0000_0000h 27.5.6/1562
29A_0018 LPUART FIFO Register (LPUART6_FIFO) 32 R/W See section 27.5.7/1564
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1549
Register definition
LPUART memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
29A_001C LPUART Watermark Register (LPUART6_WATER) 32 R/W 0000_0000h 27.5.8/1566
27.5.1 LPUART Baud Rate Register (LPUARTx_BAUD)
Address: Base address + 0h offset
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
RESYNCDIS
BOTHEDGE
R 0 0 0
RDMAE
TDMAE
MAEN1
MAEN2
M10 OSR
W
Reset 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
RXEDGIE
LBKDIE
SBNS SBR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
LPUARTx_BAUD field descriptions
Field Description
0 Match Address Mode Enable 1
MAEN1
0 Normal operation.
1 Enables automatic address matching or data matching mode for MATCH[MA1].
1 Match Address Mode Enable 2
MAEN2
0 Normal operation.
1 Enables automatic address matching or data matching mode for MATCH[MA2].
2 10-bit Mode select
M10
The M10 bit causes a tenth bit to be part of the serial transmission. This bit should only be changed when
the transmitter and receiver are both disabled.
0 Receiver and transmitter use 8-bit or 9-bit data characters.
1 Receiver and transmitter use 10-bit data characters.
3–7 Oversampling Ratio
OSR
This field configures the oversampling ratio for the receiver between 4x (00011) and 32x (11111). Writing
an invalid oversampling ratio (for example, a value not between 4x and 32x) will default to an
oversampling ratio of 16 (01111). The OSR field should only be changed when the transmitter and
receiver are both disabled. Note that the oversampling ratio = OSR + 1.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1550 NXP Semiconductors
Chapter 27 Low Power Universal asynchronous receiver/transmitter (LPUART)
LPUARTx_BAUD field descriptions (continued)
Field Description
8 Transmitter DMA Enable
TDMAE
TDMAE configures the transmit data register empty flag, LPUART_STAT[TDRE], to generate a DMA
request.
0 DMA request disabled.
1 DMA request enabled.
9 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
10 Receiver Full DMA Enable
RDMAE
RDMAE configures the receiver data register full flag, LPUART_STAT[RDRF], to generate a DMA request.
0 DMA request disabled.
1 DMA request enabled.
11 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
12–13 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
14 Both Edge Sampling
BOTHEDGE
Enables sampling of the received data on both edges of the baud rate clock, effectively doubling the
number of times the receiver samples the input data for a given oversampling ratio. This bit must be set for
oversampling ratios between x4 and x7 and is optional for higher oversampling ratios. This bit should only
be changed when the receiver is disabled.
0 Receiver samples input data using the rising edge of the baud rate clock.
1 Receiver samples input data using the rising and falling edge of the baud rate clock.
15 Resynchronization Disable
RESYNCDIS
When set, disables the resynchronization of the received data word when a data one followed by data
zero transition is detected. This bit should only be changed when the receiver is disabled.
0 Resynchronization during received data word is supported
1 Resynchronization during received data word is disabled
16 LIN Break Detect Interrupt Enable
LBKDIE
LBKDIE enables the LIN break detect flag, LBKDIF, to generate interrupt requests.
0 Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling).
1 Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1.
17 RX Input Active Edge Interrupt Enable
RXEDGIE
Enables the receive input active edge, RXEDGIF, to generate interrupt requests. Changing CTRL[LOOP]
or CTRL[RSRC] when RXEDGIE is set can cause the RXEDGIF to set.
0 Hardware interrupts from LPUART_STAT[RXEDGIF] disabled (use polling).
1 Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1.
18 Stop Bit Number Select
SBNS
SBNS determines whether data characters are one or two stop bits. This bit should only be changed when
the transmitter and receiver are both disabled.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1551
Register definition
LPUARTx_BAUD field descriptions (continued)
Field Description
0 One stop bit.
1 Two stop bits.
19–31 Baud Rate Modulo Divisor.
SBR
The 13 bits in SBR[12:0] set the modulo divide rate for the baud rate generator. When SBR is 1 - 8191,
the baud rate equals "baud clock / ((OSR+1) × SBR)". The 13-bit baud rate setting [SBR12:SBR0] must
only be updated when the transmitter and receiver are both disabled (LPUART_CTRL[RE] and
LPUART_CTRL[TE] are both 0).
27.5.2 LPUART Status Register (LPUARTx_STAT)
Address: Base address + 4h offset
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
RXEDGIF
LBKDIF
RDRF
TDRE
IDLE
OR
NF
RAF TC
FE
PF
R
RWUID
LBKDE
BRK13
RXINV
MSBF
W w1c w1c w1c w1c w1c w1c w1c
Reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
LPUARTx_STAT field descriptions
Field Description
0 LIN Break Detect Interrupt Flag
LBKDIF
LBKDIF is set when the LIN break detect circuitry is enabled and a LIN break character is detected.
LBKDIF is cleared by writing a 1 to it.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1552 NXP Semiconductors
Chapter 27 Low Power Universal asynchronous receiver/transmitter (LPUART)
LPUARTx_STAT field descriptions (continued)
Field Description
0 No LIN break character has been detected.
1 LIN break character has been detected.
1 LPUART_RX Pin Active Edge Interrupt Flag
RXEDGIF
RXEDGIF is set whenever the receiver is enabled and an active edge, falling if RXINV = 0, rising if
RXINV=1, on the LPUART_RX pin occurs. RXEDGIF is cleared by writing a 1 to it.
0 No active edge on the receive pin has occurred.
1 An active edge on the receive pin has occurred.
2 MSB First
MSBF
Setting this bit reverses the order of the bits that are transmitted and received on the wire. This bit does
not affect the polarity of the bits, the location of the parity bit or the location of the start or stop bits. This bit
should only be changed when the transmitter and receiver are both disabled.
0 LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the
start bit is identified as bit0.
1 MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the
setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is
identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE].
3 Receive Data Inversion
RXINV
Setting this bit reverses the polarity of the received data input.
NOTE: Setting RXINV inverts the LPUART_RX input for all cases: data bits, start and stop bits, break,
and idle.
0 Receive data not inverted.
1 Receive data inverted.
4 Receive Wake Up Idle Detect
RWUID
For RWU on idle character, RWUID controls whether the idle character that wakes up the receiver sets the
IDLE bit. For address match wakeup, RWUID controls if the IDLE bit is set when the address does not
match. This bit should only be changed when the receiver is disabled.
0 During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle
character. During address match wakeup, the IDLE bit does not get set when an address does not
match.
1 During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character.
During address match wakeup, the IDLE bit does get set when an address does not match.
5 Break Character Generation Length
BRK13
BRK13 selects a longer transmitted break character length. Detection of a framing error is not affected by
the state of this bit. This bit should only be changed when the transmitter is disabled.
0 Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS =
0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1).
1 Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS =
0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 16 (if M10 = 1, SNBS = 1).
6 LIN Break Detection Enable
LBKDE
LBKDE selects a longer break character detection length. While LBKDE is set, receive data is not stored
in the receive data buffer.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1553
Register definition
LPUARTx_STAT field descriptions (continued)
Field Description
0 Break character is detected at length 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M
= 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1).
1 Break character is detected at length of 11 bit times (if M = 0, SBNS = 0) or 12 (if M = 1, SBNS = 0 or
M = 0, SBNS = 1) or 14 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 15 (if M10 = 1, SNBS = 1).
7 Receiver Active Flag
RAF
RAF is set when the receiver detects the beginning of a valid start bit, and RAF is cleared automatically
when the receiver detects an idle line.
0 LPUART receiver idle waiting for a start bit.
1 LPUART receiver active (LPUART_RX input not idle).
8 Transmit Data Register Empty Flag
TDRE
When the transmit FIFO is enabled, TDRE will set when the number of datawords in the transmit FIFO
(LPUART_DATA) is equal to or less than the number indicated by LPUART_WATER[TXWATER]). To
clear TDRE, write to the LPUART data register (LPUART_DATA) until the number of words in the transmit
FIFO is greater than the number indicated by LPUART_WATER[TXWATER]. When the transmit FIFO is
disabled,TDRE will set when the transmit data register (LPUART_DATA) is empty. To clear TDRE, write to
the LPUART data register (LPUART_DATA).
TDRE is not affected by a character that is in the process of being transmitted, it is updated at the start of
each transmitted character.
0 Transmit data buffer full.
1 Transmit data buffer empty.
9 Transmission Complete Flag
TC
TC is cleared when there is a transmission in progress or when a preamble or break character is loaded.
TC is set when the transmit buffer is empty and no data, preamble, or break character is being
transmitted. When TC is set, the transmit data output signal becomes idle (logic 1). TC is cleared by
writing to LPUART_DATA to transmit new data, queuing a preamble by clearing and then setting
LPUART_CTRL[TE], queuing a break character by writing 1 to LPUART_CTRL[SBK].
0 Transmitter active (sending data, a preamble, or a break).
1 Transmitter idle (transmission activity complete).
10 Receive Data Register Full Flag
RDRF
When the receive FIFO is enabled, RDRF is set when the number of datawords in the receive buffer is
greater than the number indicated by LPUART_WATER[RXWATER]. To clear RDRF, read
LPUART_DATA until the number of datawords in the receive data buffer is equal to or less than the
number indicated by LPUART_WATER[RXWATER]. When the receive FIFO is disabled, RDRF is set
when the receive buffer (LPUART_DATA) is full. To clear RDRF, read the LPUART_DATA register.
A character that is in the process of being received does not cause a change in RDRF until the entire
character is received. Even if RDRF is set, the character will continue to be received until an overrun
condition occurs once the entire character is received.
0 Receive data buffer empty.
1 Receive data buffer full.
11 Idle Line Flag
IDLE
IDLE is set when the LPUART receive line becomes idle for a full character time after a period of activity.
When ILT is cleared, the receiver starts counting idle bit times after the start bit. If the receive character is
all 1s, these bit times and the stop bits time count toward the full character time of logic high, 10 to 13 bit
times, needed for the receiver to detect an idle line. When ILT is set, the receiver doesn't start counting
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1554 NXP Semiconductors
Chapter 27 Low Power Universal asynchronous receiver/transmitter (LPUART)
LPUARTx_STAT field descriptions (continued)
Field Description
idle bit times until after the stop bits. The stop bits and any logic high bit times at the end of the previous
character do not count toward the full character time of logic high needed for the receiver to detect an idle
line.
To clear IDLE, write logic 1 to the IDLE flag. After IDLE has been cleared, it cannot become set again until
after a new character has been stored in the receive buffer or a LIN break character has set the LBKDIF
flag . IDLE is set only once even if the receive line remains idle for an extended period.
0 No idle line detected.
1 Idle line was detected.
12 Receiver Overrun Flag
OR
OR is set when software fails to prevent the receive data register from overflowing with data. The OR bit is
set immediately after the stop bit has been completely received for the dataword that overflows the buffer
and all the other error flags (FE, NF, and PF) are prevented from setting. The data in the shift register is
lost, but the data already in the LPUART data registers is not affected. If LBKDE is enabled and a LIN
Break is detected, the OR field asserts if LBKDIF is not cleared before the next data character is received.
While the OR flag is set, no additional data is stored in the data buffer even if sufficient room exists. To
clear OR, write logic 1 to the OR flag.
0 No overrun.
1 Receive overrun (new LPUART data lost).
13 Noise Flag
NF
The advanced sampling technique used in the receiver takes three samples in each of the received bits. If
any of these samples disagrees with the rest of the samples within any bit time in the frame then noise is
detected for that character. NF is set whenever the next character to be read from LPUART_DATA was
received with noise detected within the character. To clear NF, write logic one to the NF.
0 No noise detected.
1 Noise detected in the received character in LPUART_DATA.
14 Framing Error Flag
FE
FE is set whenever the next character to be read from LPUART_DATA was received with logic 0 detected
where a stop bit was expected. To clear FE, write logic one to the FE.
0 No framing error detected. This does not guarantee the framing is correct.
1 Framing error.
15 Parity Error Flag
PF
PF is set whenever the next character to be read from LPUART_DATA was received when parity is
enabled (PE = 1) and the parity bit in the received character does not agree with the expected parity
value. To clear PF, write a logic one to the PF.
0 No parity error.
1 Parity error.
16–31 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1555
Register definition
27.5.3 LPUART Control Register (LPUARTx_CTRL)
This read/write register controls various optional features of the LPUART system. This
register should only be altered when the transmitter and receiver are both disabled.
Address: Base address + 8h offset
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
TXDIR
TXINV
R8T9 R9T8 ORIE NEIE FEIE PEIE TIE TCIE RIE ILIE TE RE RWU SBK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0
DOZEEN
LOOPS
WAKE
RSR
M ILT PE PT
C
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
LPUARTx_CTRL field descriptions
Field Description
0 Receive Bit 8 / Transmit Bit 9
R8T9
R8 is the ninth data bit received when the LPUART is configured for 9-bit or 10-bit data formats. When
reading 9-bit or 10-bit data, read R8 before reading LPUART_DATA.
T9 is the tenth data bit received when the LPUART is configured for 10-bit data formats. When writing 10-
bit data, write T9 before writing LPUART_DATA. If T9 does not need to change from its previous value,
such as when it is used to generate address mark or parity, they it need not be written each time
LPUART_DATA is written.
1 Receive Bit 9 / Transmit Bit 8
R9T8
R9 is the tenth data bit received when the LPUART is configured for 10-bit data formats. When reading
10-bit data, read R9 before reading LPUART_DATA
T8 is the ninth data bit received when the LPUART is configured for 9-bit or 10-bit data formats. When
writing 9-bit or 10-bit data, write T8 before writing LPUART_DATA. If T8 does not need to change from its
previous value, such as when it is used to generate address mark or parity, they it need not be written
each time LPUART_DATA is written.
2 LPUART_TX Pin Direction in Single-Wire Mode
TXDIR
When the LPUART is configured for single-wire half-duplex operation (LOOPS = RSRC = 1), this bit
determines the direction of data at the LPUART_TX pin. When clearing TXDIR, the transmitter will finish
receiving the current character (if any) before the receiver starts receiving data from the LPUART_TX pin.
0 LPUART_TX pin is an input in single-wire mode.
1 LPUART_TX pin is an output in single-wire mode.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1556 NXP Semiconductors
Chapter 27 Low Power Universal asynchronous receiver/transmitter (LPUART)
LPUARTx_CTRL field descriptions (continued)
Field Description
3 Transmit Data Inversion
TXINV
Setting this bit reverses the polarity of the transmitted data output.
NOTE: Setting TXINV inverts the LPUART_TX output for all cases: data bits, start and stop bits, break,
and idle.
0 Transmit data not inverted.
1 Transmit data inverted.
4 Overrun Interrupt Enable
ORIE
This bit enables the overrun flag (OR) to generate hardware interrupt requests.
0 OR interrupts disabled; use polling.
1 Hardware interrupt requested when OR is set.
5 Noise Error Interrupt Enable
NEIE
This bit enables the noise flag (NF) to generate hardware interrupt requests.
0 NF interrupts disabled; use polling.
1 Hardware interrupt requested when NF is set.
6 Framing Error Interrupt Enable
FEIE
This bit enables the framing error flag (FE) to generate hardware interrupt requests.
0 FE interrupts disabled; use polling.
1 Hardware interrupt requested when FE is set.
7 Parity Error Interrupt Enable
PEIE
This bit enables the parity error flag (PF) to generate hardware interrupt requests.
0 PF interrupts disabled; use polling).
1 Hardware interrupt requested when PF is set.
8 Transmit Interrupt Enable
TIE
Enables STAT[TDRE] to generate interrupt requests.
0 Hardware interrupts from TDRE disabled; use polling.
1 Hardware interrupt requested when TDRE flag is 1.
9 Transmission Complete Interrupt Enable for
TCIE
TCIE enables the transmission complete flag, TC, to generate interrupt requests.
0 Hardware interrupts from TC disabled; use polling.
1 Hardware interrupt requested when TC flag is 1.
10 Receiver Interrupt Enable
RIE
Enables STAT[RDRF] to generate interrupt requests.
0 Hardware interrupts from RDRF disabled; use polling.
1 Hardware interrupt requested when RDRF flag is 1.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1557
Register definition
LPUARTx_CTRL field descriptions (continued)
Field Description
11 Idle Line Interrupt Enable
ILIE
ILIE enables the idle line flag, STAT[IDLE], to generate interrupt requests.
0 Hardware interrupts from IDLE disabled; use polling.
1 Hardware interrupt requested when IDLE flag is 1.
12 Transmitter Enable
TE
Enables the LPUART transmitter. TE can also be used to queue an idle preamble by clearing and then
setting TE. When TE is cleared, this register bit will read as 1 until the transmitter has completed the
current character and the LPUART_TX pin is tristated.
0 Transmitter disabled.
1 Transmitter enabled.
13 Receiver Enable
RE
Enables the LPUART receiver. When RE is written to 0, this register bit will read as 1 until the receiver
finishes receiving the current character (if any).
0 Receiver disabled.
1 Receiver enabled.
14 Receiver Wakeup Control
RWU
This field can be set to place the LPUART receiver in a standby state. RWU automatically clears when an
RWU event occurs, that is, an IDLE event when CTRL[WAKE] is clear or an address match when
CTRL[WAKE] is set with STAT[RWUID] is clear.
NOTE: RWU must be set only with CTRL[WAKE] = 0 (wakeup on idle) if the channel is currently not idle.
This can be determined by STAT[RAF]. If the flag is set to wake up an IDLE event and the
channel is already idle, it is possible that the LPUART will discard data. This is because the data
must be received or a LIN break detected after an IDLE is detected before IDLE is allowed to be
reasserted.
0 Normal receiver operation.
1 LPUART receiver in standby waiting for wakeup condition.
15 Send Break
SBK
Writing a 1 and then a 0 to SBK queues a break character in the transmit data stream. Additional break
characters of 10 to 13, or 13 to 16 if LPUART_STATBRK13] is set, bit times of logic 0 are queued as long
as SBK is set. Depending on the timing of the set and clear of SBK relative to the information currently
being transmitted, a second break character may be queued before software clears SBK.
0 Normal transmitter operation.
1 Queue break character(s) to be sent.
16–23 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
24 Loop Mode Select
LOOPS
When LOOPS is set, the LPUART_RX pin is disconnected from the LPUART and the transmitter output is
internally connected to the receiver input. The transmitter and the receiver must be enabled to use the
loop function.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1558 NXP Semiconductors
Chapter 27 Low Power Universal asynchronous receiver/transmitter (LPUART)
LPUARTx_CTRL field descriptions (continued)
Field Description
0 Normal operation - LPUART_RX and LPUART_TX use separate pins.
1 Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input
(see RSRC bit).
25 Doze Enable
DOZEEN
0 LPUART is enabled in Doze mode.
1 LPUART is disabled in Doze mode.
26 Receiver Source Select
RSRC
This field has no meaning or effect unless the LOOPS field is set. When LOOPS is set, the RSRC field
determines the source for the receiver shift register input.
0 Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not
use the LPUART_RX pin.
1 Single-wire LPUART mode where the LPUART_TX pin is connected to the transmitter output and
receiver input.
27 9-Bit or 8-Bit Mode Select
M
0 Receiver and transmitter use 8-bit data characters.
1 Receiver and transmitter use 9-bit data characters.
28 Receiver Wakeup Method Select
WAKE
Determines which condition wakes the LPUART when RWU=1:
• Address mark in the most significant bit position of a received data character, or
• An idle condition on the receive pin input signal.
0 Configures RWU for idle-line wakeup.
1 Configures RWU with address-mark wakeup.
29 Idle Line Type Select
ILT
Determines when the receiver starts counting logic 1s as idle character bits. The count begins either after
a valid start bit or after the stop bit. If the count begins after the start bit, then a string of logic 1s preceding
the stop bit can cause false recognition of an idle character. Beginning the count after the stop bit avoids
false idle character recognition, but requires properly synchronized transmissions.
NOTE: In case the LPUART is programmed with ILT = 1, a logic 0 is automatically shifted after a
received stop bit, therefore resetting the idle count.
0 Idle character bit count starts after start bit.
1 Idle character bit count starts after stop bit.
30 Parity Enable
PE
Enables hardware parity generation and checking. When parity is enabled, the bit immediately before the
stop bit is treated as the parity bit.
0 No hardware parity generation or checking.
1 Parity enabled.
31 Parity Type
PT
Provided parity is enabled (PE = 1), this bit selects even or odd parity. Odd parity means the total number
of 1s in the data character, including the parity bit, is odd. Even parity means the total number of 1s in the
data character, including the parity bit, is even.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1559
Register definition
LPUARTx_CTRL field descriptions (continued)
Field Description
0 Even parity.
1 Odd parity.
27.5.4 LPUART Data Register (LPUARTx_DATA)
This register is actually two separate registers. Reads return the contents of the read-only
receive data buffer and writes go to the write-only transmit data buffer. Reads and writes
of this register are also involved in the automatic flag clearing mechanisms for some of
the LPUART status flags.
Address: Base address + Ch offset
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
PARITYE
FRETSC
NOISY
R 0
R9T9 R8T8 R7T7 R6T6 R5T5 R4T4 R3T3 R2T2 R1T1 R0T0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1560 NXP Semiconductors
Chapter 27 Low Power Universal asynchronous receiver/transmitter (LPUART)
LPUARTx_DATA field descriptions
Field Description
0–15 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
16 The current received dataword contained in DATA[R9:R0] was received with noise.
NOISY
0 The dataword was received without noise.
1 The data was received with noise.
17 The current received dataword contained in DATA[R9:R0] was received with a parity error.
PARITYE
0 The dataword was received without a parity error.
1 The dataword was received with a parity error.
18 Frame Error
FRETSC
The current received dataword contained in DATA[R9:R0] was received with a frame error.
19–21 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
22 Read receive data buffer 9 or write transmit data buffer 9.
R9T9
23 Read receive data buffer 8 or write transmit data buffer 8.
R8T8
24 Read receive data buffer 7 or write transmit data buffer 7.
R7T7
25 Read receive data buffer 6 or write transmit data buffer 6.
R6T6
26 Read receive data buffer 5 or write transmit data buffer 5.
R5T5
27 Read receive data buffer 4 or write transmit data buffer 4.
R4T4
28 Read receive data buffer 3 or write transmit data buffer 3.
R3T3
29 Read receive data buffer 2 or write transmit data buffer 2.
R2T2
30 Read receive data buffer 1 or write transmit data buffer 1.
R1T1
31 Read receive data buffer 0 or write transmit data buffer 0.
R0T0
27.5.5 LPUART Match Address Register (LPUARTx_MATCH)
Address: Base address + 10h offset
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0
MA2 MA1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1561
Register definition
LPUARTx_MATCH field descriptions
Field Description
0–7 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
8–15 Match Address 2
MA2
The MA1 and MA2 registers are compared to input data addresses when the most significant bit is set and
the associated BAUD[MAEN] bit is set. If a match occurs, the following data is transferred to the data
register. If a match fails, the following data is discarded. Software should only write a MA register when the
associated BAUD[MAEN] bit is clear.
16–23 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
24–31 Match Address 1
MA1
The MA1 and MA2 registers are compared to input data addresses when the most significant bit is set and
the associated BAUD[MAEN] bit is set. If a match occurs, the following data is transferred to the data
register. If a match fails, the following data is discarded. Software should only write a MA register when the
associated BAUD[MAEN] bit is clear.
27.5.6 LPUART Modem IrDA Register (LPUARTx_MODIR)
The MODEM register controls options for setting the modem configuration.
Address: Base address + 14h offset
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0
IREN TNP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
TXRTSPOL
R 0
RXRTSE
TXRTSE
TXCTSE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
LPUARTx_MODIR field descriptions
Field Description
0–12 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
13 Infrared enable
IREN
Enables/disables the infrared modulation/demodulation.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1562 NXP Semiconductors
Chapter 27 Low Power Universal asynchronous receiver/transmitter (LPUART)
LPUARTx_MODIR field descriptions (continued)
Field Description
0 IR disabled.
1 IR enabled.
14–15 Transmitter narrow pulse
TNP
Enables whether the LPUART transmits a 1/OSR, 2/OSR, 3/OSR or 4/OSR narrow pulse.
00 1/OSR.
01 2/OSR.
10 3/OSR.
11 4/OSR.
16–27 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
28 Receiver request-to-send enable
RXRTSE
Allows the RTS output to control the CTS input of the transmitting device to prevent receiver overrun.
NOTE: Do not set both RXRTSE and TXRTSE.
0 The receiver has no effect on RTS.
1 RTS assertion is configured by the RTSWATER field
29 Transmitter request-to-send polarity
TXRTSPOL
Controls the polarity of the transmitter RTS. TXRTSPOL does not affect the polarity of the receiver RTS.
RTS will remain negated in the active low state unless TXRTSE is set.
0 Transmitter RTS is active low.
1 Transmitter RTS is active high.
30 Transmitter request-to-send enable
TXRTSE
Controls RTS before and after a transmission.
0 The transmitter has no effect on RTS.
1 When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the
start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer
and shift register are completely sent, including the last stop bit.
31 Transmitter clear-to-send enable
TXCTSE
TXCTSE controls the operation of the transmitter. TXCTSE can be set independently from the state of
TXRTSE and RXRTSE.
0 CTS has no effect on the transmitter.
1 Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send
a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in
the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is
being sent do not affect its transmission.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1563
Register definition
27.5.7 LPUART FIFO Register (LPUARTx_FIFO)
This register provides the ability for the programmer to turn on and off FIFO
functionality. It also provides the size of the FIFO that has been implemented. This
register may be read at any time. This register must be written only when CTRL[RE] and
CTRL[TE] are cleared/not set and when the data buffer/FIFO is empty.
Address: Base address + 18h offset
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
RXEMPT
TXEMPT
RXUF
TXOF
R 0 0
W w1c w1c
Reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 TXFIFOSIZE RXFIFOSIZE
RXUFE
TXOFE
TXFE RXFE
RXFLUSH
TXFLUSH
Reset 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1
LPUARTx_FIFO field descriptions
Field Description
0–7 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
8 Transmit Buffer/FIFO Empty
TXEMPT
Asserts when there is no data in the Transmit FIFO/buffer. This field does not take into account data that
is in the transmit shift register.
0 Transmit buffer is not empty.
1 Transmit buffer is empty.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1564 NXP Semiconductors
Chapter 27 Low Power Universal asynchronous receiver/transmitter (LPUART)
LPUARTx_FIFO field descriptions (continued)
Field Description
9 Receive Buffer/FIFO Empty
RXEMPT
Asserts when there is no data in the receive FIFO/Buffer. This field does not take into account data that is
in the receive shift register.
0 Receive buffer is not empty.
1 Receive buffer is empty.
10–13 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
14 Transmitter Buffer Overflow Flag
TXOF
Indicates that more data has been written to the transmit buffer than it can hold. This field will assert
regardless of the value of TXOFE. However, an interrupt will be issued to the host only if TXOFE is set.
This flag is cleared by writing a 1.
0 No transmit buffer overflow has occurred since the last time the flag was cleared.
1 At least one transmit buffer overflow has occurred since the last time the flag was cleared.
15 Receiver Buffer Underflow Flag
RXUF
Indicates that more data has been read from the receive buffer than was present. This field will assert
regardless of the value of RXUFE. However, an interrupt will be issued to the host only if RXUFE is set.
This flag is cleared by writing a 1.
0 No receive buffer underflow has occurred since the last time the flag was cleared.
1 At least one receive buffer underflow has occurred since the last time the flag was cleared.
16 Transmit FIFO/Buffer Flush
TXFLUSH
Writing to this field causes all data that is stored in the transmit FIFO/buffer to be flushed. This does not
affect data that is in the transmit shift register.
0 No flush operation occurs.
1 All data in the transmit FIFO/Buffer is cleared out.
17 Receive FIFO/Buffer Flush
RXFLUSH
Writing to this field causes all data that is stored in the receive FIFO/buffer to be flushed. This does not
affect data that is in the receive shift register.
0 No flush operation occurs.
1 All data in the receive FIFO/buffer is cleared out.
18–21 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
22 Transmit FIFO Overflow Interrupt Enable
TXOFE
When this field is set, the TXOF flag generates an interrupt to the host.
0 TXOF flag does not generate an interrupt to the host.
1 TXOF flag generates an interrupt to the host.
23 Receive FIFO Underflow Interrupt Enable
RXUFE
When this field is set, the RXUF flag generates an interrupt to the host.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1565
Register definition
LPUARTx_FIFO field descriptions (continued)
Field Description
0 RXUF flag does not generate an interrupt to the host.
1 RXUF flag generates an interrupt to the host.
24 Transmit FIFO Enable
TXFE
When this field is set, the built in FIFO structure for the transmit buffer is enabled. The size of the FIFO
structure is indicated by TXFIFOSIZE. If this field is not set, the transmit buffer operates as a FIFO of
depth one dataword regardless of the value in TXFIFOSIZE. Both CTRL[TE] and CTRL[RE] must be
cleared prior to changing this field.
0 Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support).
1 Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE.
25–27 Transmit FIFO. Buffer Depth
TXFIFOSIZE
The maximum number of transmit datawords that can be stored in the transmit buffer. This field is read
only.
101 Transmit FIFO/Buffer depth = 16 datawords.
28 Receive FIFO Enable
RXFE
When this field is set, the built in FIFO structure for the receive buffer is enabled. The size of the FIFO
structure is indicated by the RXFIFOSIZE field. If this field is not set, the receive buffer operates as a FIFO
of depth one dataword regardless of the value in RXFIFOSIZE. Both CTRL[TE] and CTRL[RE] must be
cleared prior to changing this field.
0 Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)
1 Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.
29–31 Receive FIFO. Buffer Depth
RXFIFOSIZE
The maximum number of receive datawords that can be stored in the receive buffer before an overrun
occurs. This field is read only.
101 Receive FIFO/Buffer depth = 32 datawords.
27.5.8 LPUART Watermark Register (LPUARTx_WATER)
This register provides the ability to set a programmable threshold for notification of
needing additional transmit data. This register may be read at any time but must be
written only when CTRL[TE] is not set.
Address: Base address + 1Ch offset
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R RXCOUNT TXCOUNT
RXWATER TXWATER
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1566 NXP Semiconductors
Chapter 27 Low Power Universal asynchronous receiver/transmitter (LPUART)
LPUARTx_WATER field descriptions
Field Description
0–7 Receive Counter
RXCOUNT
The value in this register indicates the number of datawords that are in the receive FIFO/buffer. If a
dataword is being received, that is, in the receive shift register, it is not included in the count. This value
may be used in conjunction with FIFO[RXFIFOSIZE] to calculate how much room is left in the receive
FIFO/buffer.
8–15 Receive Watermark
RXWATER
When the number of datawords in the receive FIFO/buffer is greater than the value in this register field, an
interrupt or a DMA request is generated. For proper operation, the value in RXWATER must be set to be
less than the receive FIFO/buffer size as indicated by FIFO[RXFIFOSIZE] and FIFO[RXFE] and must be
greater than 0.
16–23 Transmit Counter
TXCOUNT
The value in this register indicates the number of datawords that are in the transmit FIFO/buffer. If a
dataword is being transmitted, that is, in the transmit shift register, it is not included in the count. This
value may be used in conjunction with FIFO[TXFIFOSIZE] to calculate how much room is left in the
transmit FIFO/buffer.
24–31 Transmit Watermark
TXWATER
When the number of datawords in the transmit FIFO/buffer is equal to or less than the value in this register
field, an interrupt or a DMA request is generated. For proper operation, the value in TXWATER must be
set to be less than the size of the transmit buffer/FIFO size as indicated by FIFO[TXFIFOSIZE] and
FIFO[TXFE].
27.6 Functional description
The LPUART supports full-duplex, asynchronous, NRZ serial communication and
comprises a baud rate generator, transmitter, and receiver block. The transmitter and
receiver operate independently, although they use the same baud rate generator. The
following describes each of the blocks of the LPUART.
27.6.1 Baud rate generation
A 13-bit modulus counter in the baud rate generator derive the baud rate for both the
receiver and the transmitter. The value from 1 to 8191 written to SBR[12:0] determines
the baud clock divisor for the asynchronous LPUART baud clock. The SBR bits are in
the LPUART baud rate registers, BDH and BDL. The baud rate clock drives the receiver,
while the transmitter is driven by the baud rate clock divided by the over sampling ratio.
Depending on the over sampling ratio, the receiver has an acquisition rate of 4 to 32
samples per bit time.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1567
Functional description
Modulo Divide By
OSR
(1 through 8191)
Divide By Tx Baud Rate
LPUART ASYNCH
SBR[12:0] (OSR+1)
Module Clock
Baud Rate Generator Rx Sampling Clock
Off If [SBR12:SBR0] =0 [(OSR+1) × Baud Rate]
LPUART ASYNCH Module Clock
Baud Rate =
SBR[12:0] × (OSR+1)
Figure 27-3. LPUART baud rate generation
Baud rate generation is subject to two sources of error:
• Integer division of the asynchronous LPUART baud clock may not give the exact
target frequency.
• Synchronization with the asynchronous LPUART baud clock can cause phase shift.
27.6.2 Transmitter functional description
This section describes the overall block diagram for the LPUART transmitter, as well as
specialized functions for sending break and idle characters.
The transmitter output (LPUART_TX) idle state defaults to logic high, CTRL[TXINV] is
cleared following reset. The transmitter output is inverted by setting CTRL[TXINV]. The
transmitter is enabled by setting the CTRL[TE] bit. This queues a preamble character that
is one full character frame of the idle state. The transmitter then remains idle until data is
available in the transmit data buffer. Programs store data into the transmit data buffer by
writing to the LPUART data register.
The central element of the LPUART transmitter is the transmit shift register that is 10-bit
to 13 bits long depending on the setting in the CTRL[M], BAUD[M10] and
BAUD[SBNS] control bits. For the remainder of this section, assume CTRL[M],
BAUD[M10] and BAUD[SBNS] are cleared, selecting the normal 8-bit data mode. In 8-
bit data mode, the shift register holds a start bit, eight data bits, and a stop bit. When the
transmit shift register is available for a new character, the value waiting in the transmit
data register is transferred to the shift register, synchronized with the baud rate clock, and
the transmit data register empty (STAT[TDRE]) status flag is set to indicate another
character may be written to the transmit data buffer at LPUART_DATA.
If no new character is waiting in the transmit data buffer after a stop bit is shifted out the
LPUART_TX pin, the transmitter sets the transmit complete flag and enters an idle
mode, with LPUART_TX high, waiting for more characters to transmit.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1568 NXP Semiconductors
Chapter 27 Low Power Universal asynchronous receiver/transmitter (LPUART)
Writing 0 to CTRL[TE] does not immediately disable the transmitter. The current
transmit activity in progress must first be completed (that could include a data character,
idle character or break character), although the transmitter will not start transmitting
another character.
27.6.2.1 Send break and queued idle
The LPUART_CTRL[SBK] bit sends break characters originally used to gain the
attention of old teletype receivers. Break characters are a full character time of logic 0,
10-bit to 12-bit times including the start and stop bits. A longer break of 13-bit times can
be enabled by setting LPUART_STAT[BRK13]. Normally, a program would wait for
LPUART_STAT[TDRE] to become set to indicate the last character of a message has
moved to the transmit shifter, write 1, and then write 0 to the LPUART_CTRL[SBK] bit.
This action queues a break character to be sent as soon as the shifter is available. If
LPUART_CTRL[SBK] remains 1 when the queued break moves into the shifter,
synchronized to the baud rate clock, an additional break character is queued. If the
receiving device is another LPUART, the break characters are received as 0s in all data
bits and a framing error (LPUART_STAT[FE] = 1) occurs.
A break character can also be transmitted by writing to the LPUART_DATA register
with bit 13 set and the data bits clear. This supports transmitting the break character as
part of the normal data stream and also allows the DMA to transmit a break character.
When idle-line wakeup is used, a full character time of idle (logic 1) is needed between
messages to wake up any sleeping receivers. Normally, a program would wait for
LPUART_STAT[TDRE] to become set to indicate the last character of a message has
moved to the transmit shifter, then write 0 and then write 1 to the LPUART_CTRL[TE]
bit. This action queues an idle character to be sent as soon as the shifter is available. As
long as the character in the shifter does not finish while LPUART_CTRL[TE] is cleared,
the LPUART transmitter never actually releases control of the LPUART_TX pin.
An idle character can also be transmitted by writing to the LPUART_DATA register with
bit 13 set and the data bits also set. This supports transmitting the idle character as part of
the normal data stream and also allows the DMA to transmit a break character.
The length of the break character is affected by the LPUART_STAT[BRK13],
LPUART_CTRL[M], LPUART_BAUD[M10] and LPUART_BAUD[SNBS] bits as
shown below.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1569
Functional description
Table 27-5. Break character length
BRK13 M M10 SBNS Break character
length
0 0 0 0 10 bit times
0 0 0 1 11 bit times
0 1 0 0 11 bit times
0 1 0 1 12 bit times
0 X 1 0 12 bit times
0 X 1 1 13 bit times
1 0 0 0 13 bit times
1 0 0 1 13 bit times
1 1 0 0 14 bit times
1 1 0 1 14 bit times
1 X 1 0 15 bit times
1 X 1 1 15 bit times
27.6.2.2 Hardware flow control
The transmitter supports hardware flow control by gating the transmission with the value
of CTS. If the clear-to-send operation is enabled, the character is transmitted when CTS
is asserted. If CTS is deasserted in the middle of a transmission with characters remaining
in the receiver data buffer, the character in the shift register is sent and LPUART_TX
remains in the mark state until CTS is reasserted.
If the clear-to-send operation is disabled, the transmitter ignores the state of CTS.
The transmitter's CTS signal can also be enabled even if the same LPUART receiver's
RTS signal is disabled.
27.6.2.3 Transceiver driver enable
The transmitter can use LPUART_RTS as an enable signal for the driver of an external
transceiver. See Transceiver driver enable using LPUART_RTS for details. If the
request-to-send operation is enabled, when a character is placed into an empty transmitter
data buffer, LPUART_RTS asserts one bit time before the start bit is transmitted.
LPUART_RTS remains asserted for the whole time that the transmitter data buffer has
any characters. LPUART_RTS deasserts one bit time after all characters in the
transmitter data buffer and shift register are completely sent, including the last stop bit.
Transmitting a break character also asserts LPUART_RTS, with the same assertion and
deassertion timing as having a character in the transmitter data buffer.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1570 NXP Semiconductors
Chapter 27 Low Power Universal asynchronous receiver/transmitter (LPUART)
The transmitter's LPUART_RTS signal asserts only when the transmitter is enabled.
However, the transmitter's LPUART_RTS signal is unaffected by its LPUART_CTS
signal. LPUART_RTS will remain asserted until the transfer is completed, even if the
transmitter is disabled mid-way through a data transfer.
27.6.2.4 Transceiver driver enable using LPUART_RTS
RS-485 is a multiple drop communication protocol in which the LPUART transceiver's
driver is 3-stated unless the UART is driving. The LPUART_RTS signal can be used by
the transmitter to enable the driver of a transceiver. The polarity of LPUART_RTS can
be matched to the polarity of the transceiver's driver enable signal.
UART RS-485 TRANSCEIVER
TXD DI Y
TRANSMITTER RTS_B DRIVER Z
DE
RXD RO A
RECEIVER RECEIVER B
RE_B
Figure 27-4. Transceiver driver enable using LPUART_RTS
In the figure, the receiver enable signal is asserted. Another option for this connection is
to connect LPUART_RTS to both DE and RE_B. The transceiver's receiver is disabled
while driving. A pullup can pull LPUART_RX to a non-floating value during this time.
This option can be refined further by operating the LPUART in single wire mode, freeing
the LPUART_RX pin for other uses.
27.6.3 Receiver functional description
In this section, the receiver block diagram is a guide for the overall receiver functional
description. Next, the data sampling technique used to reconstruct receiver data is
described in more detail. Finally, different variations of the receiver wakeup function are
explained.
The receiver input is inverted by setting LPUART_STAT[RXINV]. The receiver is
enabled by setting the LPUART_CTRL[RE] bit. Character frames consist of a start bit of
logic 0, eight to ten data bits (msb or lsb first), and one or two stop bits of logic 1. For
information about 9-bit or 10-bit data mode, refer to 8-bit, 9-bit and 10-bit data modes.
For the remainder of this discussion, assume the LPUART is configured for normal 8-bit
data mode.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1571
Functional description
After receiving the stop bit into the receive shifter, and provided the receive data register
is not already full, the data character is transferred to the receive data register and the
receive data register full (LPUART_STAT[RDRF]) status flag is set. If
LPUART_STAT[RDRF] was already set indicating the receive data register (buffer) was
already full, the overrun (OR) status flag is set and the new data is lost. Because the
LPUART receiver is double-buffered, the program has one full character time after
LPUART_STAT[RDRF] is set before the data in the receive data buffer must be read to
avoid a receiver overrun.
When a program detects that the receive data register is full (LPUART_STAT[RDRF] =
1), it gets the data from the receive data register by reading LPUART_DATA. Refer to
Interrupts and status flags for details about flag clearing.
27.6.3.1 Data sampling technique
The LPUART receiver supports a configurable oversampling rate of between 4× and 32×
of the baud rate clock for sampling. The receiver starts by taking logic level samples at
the oversampling rate times the baud rate to search for a falling edge on the
LPUART_RX serial data input pin. A falling edge is defined as a logic 0 sample after
three consecutive logic 1 samples. The oversampling baud rate clock divides the bit time
into 4 to 32 segments from 1 to OSR (where OSR is the configured oversampling ratio).
When a falling edge is located, three more samples are taken at (OSR/2), (OSR/2)+1, and
(OSR/2)+2 to make sure this was a real start bit and not merely noise. If at least two of
these three samples are 0, the receiver assumes it is synchronized to a received character.
If another falling edge is detected before the receiver is considered synchronized, the
receiver restarts the sampling from the first segment.
The receiver then samples each bit time, including the start and stop bits, at (OSR/2),
(OSR/2)+1, and (OSR/2)+2 to determine the logic level for that bit. The logic level is
interpreted to be that of the majority of the samples taken during the bit time. If any
sample in any bit time, including the start and stop bits, in a character frame fails to agree
with the logic level for that bit, the noise flag (LPUART_STAT[NF]) is set when the
received character is transferred to the receive data buffer.
When the LPUART receiver is configured to sample on both edges of the baud rate
clock, the number of segments in each received bit is effectively doubled (from 1 to
OSR×2). The start and data bits are then sampled at OSR, OSR+1 and OSR+2. Sampling
on both edges of the clock must be enabled for oversampling rates of 4× to 7× and is
optional for higher oversampling rates.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1572 NXP Semiconductors
Chapter 27 Low Power Universal asynchronous receiver/transmitter (LPUART)
The falling edge detection logic continuously looks for falling edges. If an edge is
detected, the sample clock is resynchronized to bit times (unless resynchronization has
been disabled). This improves the reliability of the receiver in the presence of noise or
mismatched baud rates. It does not improve worst case analysis because some characters
do not have any extra falling edges anywhere in the character frame.
In the case of a framing error, provided the received character was not a break character,
the sampling logic that searches for a falling edge is filled with three logic 1 samples so
that a new start bit can be detected almost immediately.
27.6.3.2 Receiver wakeup operation
Receiver wakeup and receiver address matching is a hardware mechanism that allows an
LPUART receiver to ignore the characters in a message intended for a different receiver.
During receiver wakeup, all receivers evaluate the first character(s) of each message, and
as soon as they determine the message is intended for a different receiver, they write
logic 1 to the receiver wake up control bit (LPUART_CTRL[RWU]). When RWU bit
and LPUART_S2[RWUID] bit are set, the status flags associated with the receiver, with
the exception of the idle bit, IDLE, are inhibited from setting, thus eliminating the
software overhead for handling the unimportant message characters. At the end of a
message, or at the beginning of the next message, all receivers automatically force
LPUART_CTRL[RWU] to 0 so all receivers wake up in time to look at the first
character(s) of the next message.
During receiver address matching, the address matching is performed in hardware and the
LPUART receiver will ignore all characters that do not meet the address match
requirements.
Table 27-6. Receiver Wakeup Options
RWU MA1 | MA2 WAKE:RWUID Receiver Wakeup
0 0 X Normal operation
1 0 00 Receiver wakeup on idle line,
IDLE flag not set
1 0 01 Receiver wakeup on idle line,
IDLE flag set
1 0 10 Receiver wakeup on address
mark
0 1 X0 Address mark address match,
IDLE flag not set for discarded
characters
0 1 X1 Address mark address match,
IDLE flag set for discarded
characters
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1573
Functional description
27.6.3.2.1 Idle-line wakeup
When wake is cleared, the receiver is configured for idle-line wakeup. In this mode,
LPUART_CTRL[RWU] is cleared automatically when the receiver detects a full
character time of the idle-line level. The LPUART_CTRL[M] and
LPUART_BAUD[M10] control bit selects 8-bit to 10-bit data mode and the
LPUART_BAUD[SBNS] bit selects 1-bit or 2-bit stop bit number that determines how
many bit times of idle are needed to constitute a full character time, 10 to 13 bit times
because of the start and stop bits.
When LPUART_CTRL[RWU] is one and LPUART_STAT[RWUID] is zero, the idle
condition that wakes up the receiver does not set the LPUART_STAT[IDLE] flag. The
receiver wakes up and waits for the first data character of the next message that sets the
LPUART_STAT[RDRF] flag and generates an interrupt if enabled. When
LPUART_STAT[RWUID] is one, any idle condition sets the LPUART_STAT[IDLE]
flag and generates an interrupt if enabled, regardless of whether LPUART_CTRL[RWU]
is zero or one.
The idle-line type (LPUART_CTRL[ILT]) control bit selects one of two ways to detect
an idle line. When LPUART_CTRL[ILT] is cleared, the idle bit counter starts after the
start bit so the stop bit and any logic 1s at the end of a character count toward the full
character time of idle. When LPUART_CTRL[ILT] is set, the idle bit counter does not
start until after the stop bit time, so the idle detection is not affected by the data in the last
character of the previous message.
27.6.3.2.2 Address-mark wakeup
When LPUART_CTRL[WAKE] is set, the receiver is configured for address-mark
wakeup. In this mode, LPUART_CTRL[RWU] is cleared automatically when the
receiver detects a logic 1 in the most significant bit of a received character.
Address-mark wakeup allows messages to contain idle characters, but requires the MSB
be reserved for use in address frames. The logic 1 in the MSB of an address frame clears
the LPUART_CTRL[RWU] bit before the stop bits are received and sets the
LPUART_STAT[RDRF] flag. In this case, the character with the MSB set is received
even though the receiver was sleeping during most of this character time.
27.6.3.2.3 Address Match operation
Address match operation is enabled when the LPUART_BAUD[MAEN1] or
LPUART_BAUD[MAEN2] bit is set and LPUART_BAUD[MATCFG] is equal to 00. In
this function, a character received by the LPUART_RX pin with a logic 1 in the bit
position immediately preceding the stop bit is considered an address and is compared
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1574 NXP Semiconductors
Chapter 27 Low Power Universal asynchronous receiver/transmitter (LPUART)
with the associated MATCH[MA1] or MATCH[MA2] field. The character is only
transferred to the receive buffer, and LPUART_STAT[RDRF] is set, if the comparison
matches. All subsequent characters received with a logic 0 in the bit position immediately
preceding the stop bit are considered to be data associated with the address and are
transferred to the receive data buffer. If no marked address match occurs then no transfer
is made to the receive data buffer, and all following characters with logic zero in the bit
position immediately preceding the stop bit are also discarded. If both the
LPUART_BAUD[MAEN1] and LPUART_BAUD[MAEN2] bits are negated, the
receiver operates normally and all data received is transferred to the receive data buffer.
Address match operation functions in the same way for both MATCH[MA1] and
MATCH[MA2] fields.
• If only one of LPUART_BAUD[MAEN1] and LPUART_BAUD[MAEN2] is
asserted, a marked address is compared only with the associated match register and
data is transferred to the receive data buffer only on a match.
• If LPUART_BAUD[MAEN1] and LPUART_BAUD[MAEN2] are asserted, a
marked address is compared with both match registers and data is transferred only on
a match with either register.
27.6.3.3 Hardware flow control
To support hardware flow control, the receiver can be programmed to automatically
deassert and assert LPUART_RTS.
• LPUART_RTS remains asserted until the transfer is complete, even if the transmitter
is disabled midway through a data transfer. See Transceiver driver enable using
LPUART_RTS for more details.
• If the receiver request-to-send functionality is enabled, the receiver automatically
deasserts LPUART_RTS if the number of characters in the receiver data register is
full or a start bit is detected that will cause the receiver data register to be full.
• The receiver asserts LPUART_RTS when the number of characters in the receiver
data register is not full and has not detected a start bit that will cause the receiver data
register to be full. It is not affected if STAT[RDRF] is asserted.
• Even if LPUART_RTS is deasserted, the receiver continues to receive characters
until the receiver data buffer is overrun.
• If the receiver request-to-send functionality is disabled, the receiver LPUART_RTS
remains deasserted.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1575
Functional description
27.6.3.4 Infrared decoder
The infrared decoder converts the received character from the IrDA format to the NRZ
format used by the receiver. It also has a OSR oversampling baud rate clock counter that
filters noise and indicates when a 1 is received.
27.6.3.4.1 Start bit detection
When STAT[RXINV] is cleared, the first falling edge of the received character
corresponds to the start bit. The infrared decoder resets its counter. At this time, the
receiver also begins its start bit detection process. After the start bit is detected, the
receiver synchronizes its bit times to this start bit time. For the rest of the character
reception, the infrared decoder's counter and the receiver's bit time counter count
independently from each other.
27.6.3.4.2 Noise filtering
Any further rising edges detected during the first half of the infrared decoder counter are
ignored by the decoder. Any pulses less than one oversampling baud clock can be
undetected by it regardless of whether it is seen in the first or second half of the count.
27.6.3.4.3 Low-bit detection
During the second half of the decoder count, a rising edge is decoded as a 0, which is sent
to the receiver. The decoder counter is also reset.
27.6.3.4.4 High-bit detection
At OSR oversampling baud rate clocks after the previous rising edge, if a rising edge is
not seen, then the decoder sends a 1 to the receiver.
If the next bit is a 0, which arrives late, then a low-bit is detected according to Low-bit
detection. The value sent to the receiver is changed from 1 to a 0. Then, if a noise pulse
occurs outside the receiver's bit time sampling period, then the delay of a 0 is not
recorded as noise.
27.6.4 Additional LPUART functions
The following sections describe additional LPUART functions.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1576 NXP Semiconductors
Chapter 27 Low Power Universal asynchronous receiver/transmitter (LPUART)
27.6.4.1 8-bit, 9-bit and 10-bit data modes
The LPUART transmitter and receiver can be configured to operate in 9-bit data mode by
setting the LPUART_CTRL[M] or 10-bit data mode by setting LPUART_CTRL[M10].
In 9-bit mode, there is a ninth data bit in 10-bit mode there is a tenth data bit. For the
transmit data buffer, these bits are stored in LPUART_CTRL[T8] and
LPUART_CTRL[T9]. For the receiver, these bits are held in LPUART_CTRL[R8] and
LPUART_CTRL[R9]. They are also accessible via 16-bit or 32-bit accesses to the
LPUART_DATA register.
For coherent 8-bit writes to the transmit data buffer, write to LPUART_CTRL[T8] and
LPUART_CTRL[T9] before writing to LPUART_DATA[7:0]. For 16-bit and 32-bit
writes to the LPUART_DATA register all 10 transmit bits are written to the transmit data
buffer at the same time.
If the bit values to be transmitted as the ninth and tenth bit of a new character are the
same as for the previous character, it is not necessary to write to LPUART_CTRL[T8]
and LPUART_CTRL[T9] again. When data is transferred from the transmit data buffer to
the transmit shifter, the value in LPUART_CTRL[T8] and LPUART_CTRL[T9] is
copied at the same time data is transferred from LPUART_DATA[7:0] to the shifter.
The 9-bit data mode is typically used with parity to allow eight bits of data plus the parity
in the ninth bit, or it is used with address-mark wakeup so the ninth data bit can serve as
the wakeup bit. The 10-bit data mode is typically used with parity and address-mark
wakeup so the ninth data bit can serve as the wakeup bit and the tenth bit as the parity bit.
In custom protocols, the ninth and/or tenth bits can also serve as software-controlled
markers.
27.6.4.2 Idle length
An idle character is a character where the start bit, all data bits and stop bits are in the
mark postion. The CTRL[ILT] register can be configured to start detecting an idle
character from the previous start bit (any data bits and stop bits count towards the idle
character detection) or from the previous stop bit.
27.6.4.3 Loop mode
When LPUART_CTRL[LOOPS] is set, the LPUART_CTRL[RSRC] bit in the same
register chooses between loop mode (LPUART_CTRL[RSRC] = 0) or single-wire mode
(LPUART_CTRL[RSRC] = 1). Loop mode is sometimes used to check software,
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1577
Functional description
independent of connections in the external system, to help isolate system problems. In
this mode, the transmitter output is internally connected to the receiver input and the
LPUART_RX pin is not used by the LPUART.
27.6.4.4 Single-wire operation
When LPUART_CTRL[LOOPS] is set, the RSRC bit in the same register chooses
between loop mode (LPUART_CTRL[RSRC] = 0) or single-wire mode
(LPUART_CTRL[RSRC] = 1). Single-wire mode implements a half-duplex serial
connection. The receiver is internally connected to the transmitter output and to the
LPUART_TX pin (the LPUART_RX pin is not used).
In single-wire mode, the LPUART_CTRL[TXDIR] bit controls the direction of serial
data on the LPUART_TX pin. When LPUART_CTRL[TXDIR] is cleared, the
LPUART_TX pin is an input to the receiver and the transmitter is temporarily
disconnected from the LPUART_TX pin so an external device can send serial data to the
receiver. When LPUART_CTRL[TXDIR] is set, the LPUART_TX pin is an output
driven by the transmitter, the internal loop back connection is disabled, and as a result the
receiver cannot receive characters that are sent out by the transmitter.
27.6.5 Infrared interface
The LPUART provides the capability of transmitting narrow pulses to an IR LED and
receiving narrow pulses and transforming them to serial bits, which are sent to the
LPUART. The IrDA physical layer specification defines a half-duplex infrared
communication link for exchanging data. The full standard includes data rates up to 16
Mbits/s. This design covers data rates only between 2.4 kbits/s and 115.2 kbits/s.
The LPUART has an infrared transmit encoder and receive decoder. The LPUART
transmits serial bits of data that are encoded by the infrared submodule to transmit a
narrow pulse for every zero bit. No pulse is transmitted for every one bit. When receiving
data, the IR pulses are detected using an IR photo diode and transformed to CMOS levels
by the IR receive decoder, external from the LPUART. The narrow pulses are then
stretched by the infrared receive decoder to get back to a serial bit stream to be received
by the LPUART. The polarity of transmitted pulses and expected receive pulses can be
inverted so that a direct connection can be made to external IrDA transceiver modules
that use active high pulses.
The infrared submodule receives its clock sources from the LPUART. One of these two
clocks are selected in the infrared submodule to generate either 1/OSR, 2/OSR, 3/OSR, or
4/OSR narrow pulses during transmission.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1578 NXP Semiconductors
Chapter 27 Low Power Universal asynchronous receiver/transmitter (LPUART)
27.6.5.1 Infrared transmit encoder
The infrared transmit encoder converts serial bits of data from transmit shift register to
the LPUART_TX signal. A narrow pulse is transmitted for a zero bit and no pulse for a
one bit. The narrow pulse is sent at the start of the bit with a duration of 1/OSR, 2/OSR,
3/OSR, or 4/OSR of a bit time. A narrow low pulse is transmitted for a zero bit when
LPUART_CTRL[TXINV] is cleared, while a narrow high pulse is transmitted for a zero
bit when LPUART_CTRL[TXINV] is set.
27.6.5.2 Infrared receive decoder
The infrared receive block converts data from the LPUART_RX signal to the receive
shift register. A narrow pulse is expected for each zero received and no pulse is expected
for each one received. A narrow low pulse is expected for a zero bit when
LPUART_STAT[RXINV] is cleared, while a narrow high pulse is expected for a zero bit
when LPUART_STAT[RXINV] is set. This receive decoder meets the edge jitter
requirement as defined by the IrDA serial infrared physical layer specification.
27.6.6 Interrupts and status flags
The LPUART transmitter has two status flags that can optionally generate hardware
interrupt requests. Transmit data register empty LPUART_STAT[TDRE]) indicates when
there is room in the transmit data buffer to write another transmit character to
LPUART_DATA. If the transmit interrupt enable LPUART_CTRL[TIE]) bit is set, a
hardware interrupt is requested when LPUART_STAT[TDRE] is set. Transmit complete
(LPUART_STAT[TC]) indicates that the transmitter is finished transmitting all data,
preamble, and break characters and is idle with LPUART_TX at the inactive level. This
flag is often used in systems with modems to determine when it is safe to turn off the
modem. If the transmit complete interrupt enable (LPUART_CTRL[TCIE]) bit is set, a
hardware interrupt is requested when LPUART_STAT[TC] is set. Instead of hardware
interrupts, software polling may be used to monitor the LPUART_STAT[TDRE] and
LPUART_STAT[TC] status flags if the corresponding LPUART_CTRL[TIE] or
LPUART_CTRL[TCIE] local interrupt masks are cleared.
When a program detects that the receive data register is full (LPUART_STAT[RDRF] =
1), it gets the data from the receive data register by reading LPUART_DATA. The
LPUART_STAT[RDRF] flag is cleared by reading LPUART_DATA.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1579
LPUART changes
The IDLE status flag includes logic that prevents it from getting set repeatedly when the
LPUART_RX line remains idle for an extended period of time. IDLE is cleared by
writing 1 to the LPUART_STAT[IDLE] flag. After LPUART_STAT[IDLE] has been
cleared, it cannot become set again until the receiver has received at least one new
character and has set LPUART_STAT[RDRF].
If the associated error was detected in the received character that caused
LPUART_STAT[RDRF] to be set, the error flags - noise flag (LPUART_STAT[NF]),
framing error (LPUART_STAT[FE]), and parity error flag (LPUART_STAT[PF]) - are
set at the same time as LPUART_STAT[RDRF]. These flags are not set in overrun cases.
If LPUART_STAT[RDRF] was already set when a new character is ready to be
transferred from the receive shifter to the receive data buffer, the overrun
(LPUART_STAT[OR]) flag is set instead of the data along with any associated NF, FE,
or PF condition is lost.
At any time, an active edge on the LPUART_RX serial data input pin causes the
LPUART_STAT[RXEDGIF] flag to set. The LPUART_STAT[RXEDGIF] flag is
cleared by writing a 1 to it. This function depends on the receiver being enabled
(LPUART_CTRL[RE] = 1).
27.7 LPUART changes
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1580 NXP Semiconductors
Chapter 28
PCI Express Interface Controller
28.1 The PCI Express controller as implemented on the chip
This section provides details about how the PCI Express controller is integrated into this
chip.
The following table describes the PCI Express controller integration into this chip:
Table 28-1. PCI Express controller integration
Controller Base address Maximum number of lanes
PEX1 340_0000h 4
PEX1_LUT 341_0000h —
PEX2 350_0000h 2
PEX2_LUT 351_0000h —
PEX3 360_0000h 2
PEX3_LUT 361_0000h —
The remainder of this chapter refers to a single PCI Express controller offering up to a x4
link interface. Notes are included to indicate variations for multiple instantiations.
NOTE
The LS1043A chip is compatible with the PCI Express Base
Specification, Revision 3.0; however, the physical layer
operates at Gen2 data rates (2.5 or 5 Gbits/s).
NOTE
The EP mode is not supported in LS1043A; any references to
that should be ignored.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1581
The PCI Express controller as implemented on the chip
28.1.1 PCI Express MSI implementation
The following steps describe the flow sequence of PCI Express MSI implementation:
• Write to SCFG_GnMSIIR[IBS] sets the index and triggers the corresponding Group
MSI interrupt. For example, write to G0MSIIR with a value 0x7800_0000 triggers
the Group 0 MSI interrupt line (148) with MSI interrupt index (15th bit) set in
G0MSIR.
• The SCFG_GnMSIR[SHn] indicates one or more corresponding shared MSI
interrupts are pending with the bit numbers selected by the SCFG_GnMSIIR[IBS] bit
field.
• The status register and the MSI interrupt line is cleared on read access to
SCFG_GnMSIR register.
See SCFG_GnMSIIR and SCFG_GnMSIR for more information.
SCFG_G0MSIR1 SPI-148
SCFG_G0MSIIR
0:7 Rsvd
SCFG_G0MSIR2 SPI-143
Rsvd 8:15 Rsvd
SCFG_G0MSIR3 SPI-144
Rsvd 16:23 Rsvd
SCFG_G0MSIR4 SPI-145
Rsvd 24:31
SCFG_G1MSIR1 SPI-158
SCFG_G1MSIIR
0:7 Rsvd
SCFG_G1MSIR2 SPI-153
Rsvd 8:15 Rsvd
SCFG_G1MSIR3 SPI-154
Rsvd 16:23 Rsvd
SCFG_G1MSIR4 SPI-155
Rsvd 24:31
SCFG_G2MSIR1 SPI-192
SCFG_G2MSIIR
0:7 Rsvd
SCFG_G2MSIR2 SPI-187
Rsvd 8:15 Rsvd
SCFG_G2MSIR3 SPI-188
Rsvd 16:23 Rsvd
SCFG_G2MSIR4 SPI-189
Rsvd 24:31
Figure 28-1. PCI Express MSI implementation
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1582 NXP Semiconductors
Chapter 28 PCI Express Interface Controller
28.1.2 PCI Express soft reset support
The PEX_LUT_PEXLDBG provides the software configurability to reset PCI Express
controllers.
• Write to PEX_LUT_PEXLDBG[SR] bit resets the PCI Express 1 controller. This bit
needs to be cleared for the reset to be de-asserted.
28.1.3 PCI Express PM turnoff message support
The PEX PME control register (SCFG_PEXPMECR) provides the software
configurability for PM turnoff message. Software needs to set and clear
SCFG_PEXPMECR[PEXnPME] to generate PM turnoff message for power management
support for PCI Express controllers.
28.1.4 Additional PCI Express events connected to GIC-400
interrupt
The PCI Express controller sideband signals which signify these events are connected to
Interrupt lines of GIC-400 interrupt controller. There are no status registers available
inside PCI Express controller to indicate these events and the interrupt service routine
does not need access to the PCI Express controller CCSR space to clear these events.
These Interrupts are to be configured as edge-interrupts.
Internal interrupt ID Interrupt Source Comments
235 PEX1 link-down This is edge triggered interrupt.
It detects link down condition. For
example, assertion of soft reset triggers
this interrupt.
236 PEX1 link-up This is edge triggered interrupt.
239 PEX2 link-down This is edge triggered interrupt.
It detects link down condition. For
example, assertion of soft reset triggers
this interrupt.
240 PEX2 link-up This is edge triggered interrupt.
This interrupt is set when link is trained
to L0 state. Memory and config
accesses should happen after this
interrupt is set.
243 PEX3 link-down This is edge triggered interrupt.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1583
Introduction
Internal interrupt ID Interrupt Source Comments
It detects link down condition. For
example, assertion of soft reset triggers
this interrupt.
244 PEX3 link-up This is edge triggered interrupt.
This interrupt is set when link is trained
to L0 state. Memory and config
accesses should happen after this
interrupt is set.
28.2 Introduction
The PCI Express interface is compatible with the PCI Express™ Base Specification,
Revision 3.0 (available from http://www.pcisig.org). It is beyond the scope of this manual
to document the intricacies of the PCI Express protocol. This chapter describes the PCI
Express controller of this device and provides a basic description of the PCI Express
protocol. The specific emphasis is directed at how the device implements the PCI Express
specification. Designers of systems incorporating PCI Express devices should refer to the
specification for a thorough description of PCI Express.
NOTE
Much of the available PCI Express literature refers to a 16-bit
quantity as a WORD and a 32-bit quantity as a DWORD. Note
that this is inconsistent with the terminology in the rest of this
manual where the terms 'word' and 'double word' refer to a 32-
bit and 64-bit quantity, respectively. Where necessary to avoid
confusion, the precise number of bits or bytes is specified.
28.2.1 Overview
The PCI Express controller connects the internal platform to a serial interface.
As both an initiator and a target device, the PCI Express interface is capable of high-
bandwidth data transfer and is designed to support next generation I/O devices. Upon
coming out of reset, the PCI Express interface performs link width negotiation and
exchanges flow control credits with its link partner. Once link autonegotiation is
successful, the controller is in operation.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1584 NXP Semiconductors
Chapter 28 PCI Express Interface Controller
Internally, the design contains queues to keep track of inbound and outbound
transactions. There is control logic that handles buffer management, bus protocol,
transaction spawning and tag generation. In addition, there are memory blocks used to
store inbound and outbound data.
The PCI Express controller operates as a PCI Express Root Complex (RC) device. An
RC device connects the host CPU/memory subsystem to I/O devices. In RC mode, the
PCI Express type 1 configuration header is used.
This figure shows a high-level block diagram of the PCI Express controller.
Internal Platform Interface
RX TX
Transaction Layer
Configuration Registers
RX TX
Data Link Layer
RX TX
MAC Layer
SerDes Interface
PCI Express Link
Figure 28-2. PCI Express Controller Block Diagram
As an initiator, the PCI Express controller supports memory read and write operations. In
addition, configuration and I/O transactions are supported. As a target interface, the PCI
Express controller accepts read and write operations to local memory space. Message
generation and acceptance are supported. Locked transactions and inbound I/O
transactions are not supported.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1585
Introduction
28.2.1.1 Outbound Transactions
Outbound internal platform transactions to PCI Express are first mapped to a translation
window to determine what PCI Express transactions are to be issued. A transaction from
the internal platform can become a PCI Express Memory, I/O, or Configuration
transaction depending on the window attributes.
A transaction may be broken up into smaller sized transactions depending on the original
request size, transaction type, and either the PCI Express Device Control register
[MAX_PAYLOAD_SIZE] field for write requests or the PCI Express Device Control
register [MAX_READ_SIZE] field for read requests. The controller performs PCI
Express ordering rule checking to determine which transaction is to be sent on the PCI
Express link.
In general, transactions are serviced in the order that they are received from the internal
platform . Only when there is a stalled condition does the controller apply PCI Express
ordering rules to outstanding transactions. For posted write transactions, once all data has
been received from the internal platform , the data is forwarded to the PCI Express link
and the transaction is considered as done. For non-posted write transactions, the
controller waits for the completion packets to return before considering the transaction
finished. For non-posted read transactions, the controller waits for all completion packets
to return and then forwards all data back to the internal platform before terminating the
transaction.
Note that after reset or when recovering from a link down condition, external transactions
should not be attempted until the link has successfully trained. Software can poll the
LTSSM state status to check the status of link training before issuing external requests.
In EP mode, after reset or when recovering from a link down condition, the SoC must not
generate any outbound memory or I/O transactions until the remote host has configured
the Bus Master Enable bit in the PCI Command register.
28.2.1.2 Inbound Transactions
Inbound PCI Express transactions to internal platform are first mapped to a translation
window to determine what internal platform transactions are to be issued.
A transaction may be broken up into smaller sized transactions when sending to the
internal platform depending on the original request size, byte enables and starting/ending
addresses. The controller performs PCI Express ordering rule checking to determine what
transaction is to be sent next to the internal platform.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1586 NXP Semiconductors
Chapter 28 PCI Express Interface Controller
In general, transactions are serviced in the order that they are received from the PCI
Express link. Only when there is a stalled condition does the controller apply PCI
Express ordering to outstanding transactions. For posted write transactions, once all data
has been received from the PCI Express link, the data is forwarded to the internal
platform and the transaction is considered as done. For non-posted read transactions, the
controller forwards internal platform data back to the PCI Express link.
Note that the controller splits transactions at the crossing of every 256-byte-aligned
boundary when sending data back to the PCI Express link.
28.2.2 Features
The following is a list of features supported by the PCI Express controller:
• Compatible with the PCI Express™ Base Specification, Revision 3.0
• Supports Root Complex (RC) mode
• 32- and 64-bit PCI Express address support
• 40-bit internal platform address support
• x4, x2, and x1 link support.
• Supports accesses to all PCI Express memory and I/O address spaces (requestor
only)
• Supports posting of processor-to-PCI Express and PCI Express-to-memory writes
• Supports strong and relaxed transaction ordering rules
• Enforces outbound PCI Express ordering rules and inbound internal platform priority
• PCI Express configuration registers (type 1)
• Baseline and advanced error reporting support
• One virtual channel (VC0)
• 256-byte maximum payload size (MAX_PAYLOAD_SIZE)
• Supports 64-bit MSI interrupts. Note that MSI support is provided in the SCFG
module.
• Credit-based flow control management handled by PCI Express core.
• Supports PCI Express messages and interrupts
• Accepts up to 256-byte transactions from the internal platform
• Supports Expansion ROM.
28.2.3 Modes of Operation
Several parameters that affect the PCI Express controller modes of operation are
determined at power-on reset (POR) by reset configuration word (RCW) fields
configured depending on SoC product.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1587
External Signal Descriptions
Table 28-2. POR Parameters for PCI Express Controller
RCW Parameter Description
SerDes Protocol Select Determines the link width
SRDS_PRTCL
SerDes frequency divider for PCI Determines the link speed
Express
28.2.3.1 Link Width
The initial link width is determined by the SerDes protocol configuration field
(RCW[SRDS_PRTCL_Sn]). See Reset Configuration Word (RCW) for more
information. The specific configurations are detailed in SerDes Lane Assignments and
Multiplexing.
28.2.3.2 Link Speed
The initial link speed is determined by the SerDes frequency divider for PCI Express
field (RCW[SRDS_DIV_PEX_Sn]).
See RCW Field Definitions for more information. The specific configurations are
detailed in Reference Clocks for SerDes Protocols.
28.3 External Signal Descriptions
The PCI Express specification defines the connection between two devices as a link,
which can be composed of a single or multiple lanes. Each lane consists of a differential
pair for transmitting (TX[n]_P and TX[n]_N) and a differential pair for receiving
(RX[n]_P and RX[n]_N) with an embedded data clock.
Table 28-3. PCI Express Interface Signals—Detailed Signal Descriptions
Signal I/O Description
SD_RX[n]_P I Receive data, positive. The receive data signals carry PCI Express packet information.
State Asserted/Negated—Represents data being received from the PCI Express interface.
Meaning
Timing Assertion/Negation—As described in the PCI Express Base Specification, Revision 3.0.
SD_RX[n]_N I Receive data, negative. The receive data signals carry PCI Express packet information.
State Asserted/Negated—Represents the inverse of data being received from the PCI Express
Meaning interface.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1588 NXP Semiconductors
Chapter 28 PCI Express Interface Controller
Table 28-3. PCI Express Interface Signals—Detailed Signal Descriptions
(continued)
Signal I/O Description
Timing Assertion/Negation—As described in the PCI Express Base Specification, Revision 3.0.
SD_TX[n]_P O Transmit data, positive. The transmit data signals carry PCI Express packet information.
State Asserted/Negated—Represents data being transmitted to the PCI Express interface.
Meaning
Timing Assertion/Negation—As described in the PCI Express Base Specification, Revision 3.0.
SD_TX[n]_N O Transmit data, negative. The transmit data signals carry PCI Express packet information.
State Asserted/Negated—Represents the inverse of data being transmitted to the PCI Express
Meaning interface.
Timing Assertion/Negation—As described in the PCI Express Base Specification, Revision 3.0.
28.4 Memory map/register overview
28.4.1 PCI Express configuration registers
The PCI Express module supports the same configuration registers in both the internal
memory map and in PCI Express configuration space. They differ only in whether they
are accessed from an internal initiator or from an external initiator on the PCI Express
interface. With the exception of the registers in the PEX module internal configuration
space, the configuration registers are specified by the PCI Express specification for every
PCI Express device. The registers in the PEX module internal configuration space are
used for chip-specific functionality and are not defined by the PCI Express specification.
Table 28-4. PCI Express memory map
Register space Offset NEXT pointer Notes
Type 1 configuration header 0x000 0x40 RC use Type 1
Power management capability structure 0x040 0x50
PCI Express capability structure 0x070 0x000 (NULL)
Advanced error reporting capability 0x100 0x148
structure
Secondary PCI Express capability structure 0x148 0x000 (NULL)
PEX module internal configuration space 0x700 —
BAR Mask Registers 0x1000 —
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1589
Memory map/register overview
28.4.2 PEX register descriptions
28.4.2.1 PCI_Express_Configuration_Registers Memory map
PEX1 base address: 340_0000h
PEX2 base address: 350_0000h
PEX3 base address: 360_0000h
Offset Register Width Access Reset value
(In bits)
0h PCI Express Vendor ID Register (Vendor_ID_Register) 16 RO 1957h
2h PCI Express Device ID Register (Device_ID_Register) 16 RO 8080h
4h PCI Express Command Register (Command_Register) 16 RW 0000h
6h PCI Express Status Register (Status_Register) 16 W1C 0010h
8h PCI Express Revision ID Register (Revision_ID_Register) 8 RO 11h
9h PCI Express Class Code Register (Class_Code_Register) 24 RO 0B_2000h
Ch PCI Express Cache Line Size Register (Cache_Line_Size_Register) 8 RW 00h
Dh PCI Express Latency Timer Register (Latency_Timer_Register) 8 RO 00h
Eh PCI Express Header Type Register (Header_Type_Register) 8 RO 01h
10h PCI Express Base Address Register 0 (BAR0) 32 RW 0000_0000h
18h PCI Express Primary Bus Number Register (Primary_Bus_Number_R 8 RW 00h
egister)
19h PCI Express Secondary Bus Number Register (Secondary_Bus_Nu 8 RW 00h
mber_Register)
1Ah PCI Express Subordinate Bus Number Register (Subordinate_Bus_ 8 RW 00h
Number_Register)
1Ch PCI Express I/O Base Register (IO_Base_Register) 8 RW 01h
1Dh PCI Express I/O Limit Register (IO_Limit_Register) 8 RW 01h
1Eh PCI Express Secondary Status Register (Secondary_Status_Registe 16 W1C 0000h
r)
20h PCI Express Memory Base Register (Memory_Base_Register) 16 RW 0000h
22h PCI Express Memory Limit Register (Memory_Limit_Register) 16 RW 0000h
24h PCI Express Prefetchable Memory Base Register (Prefetchable_ 16 RW 0001h
Memory_Base_Register)
26h PCI Express Prefetchable Memory Limit Register (Prefetchable_Mem 16 RW 0001h
ory_Limit_Register)
28h PCI Express Prefetchable Base Upper 32 Bits Register (Prefetchable 32 RW 0000_0000h
_Base_Upper_32_Bits_Register)
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1590 NXP Semiconductors
Chapter 28 PCI Express Interface Controller
Offset Register Width Access Reset value
(In bits)
2Ch PCI Express Prefetchable Limit Upper 32 Bits Register (Prefetchable 32 RW 0000_0000h
_Limit_Upper_32_Bits_Register)
30h PCI Express I/O Base Upper 16 Bits Register (IO_Base_Upper_16_ 16 RO 0000h
Bits_Register)
32h PCI Express I/O Limit Upper 16 Bits Register (IO_Limit_Upper_16_Bi 16 RO 0000h
ts_Register)
34h Capabilities Pointer Register (Capabilities_Pointer_Register) 8 RO 40h
38h PCI Express Expansion ROM Base Address Register (RC-Mode) 32 RW 0000_0000h
(Expansion_ROM_BAR_Type1)
3Ch PCI Express Interrupt Line Register (Interrupt_Line_Register) 8 RW FFh
3Dh PCI Express Interrupt Pin Register (Interrupt_Pin_Register) 8 RO 01h
3Eh PCI Express Bridge Control Register (Bridge_Control_Register) 16 RW 0000h
40h PCI Express Power Management Capability ID Register (Power_Ma 8 RO 01h
nagement_Capability_ID_Register)
42h PCI Express Power Management Capabilities Register (Power_Ma 16 RO 7E23h
nagement_Capabilities_Register)
44h PCI Express Power Management Status and Control Register (Powe 16 RW 0000h
r_Management_Status_and_Control_Register)
47h PCI Express Power Management Data Register (Power_Manage 8 RO 00h
ment_Data_Register)
70h PCI Express Capability ID Register (Capability_ID_Register) 8 RO 10h
72h PCI Express Capabilities Register (Capabilities_Register) 16 RO 0042h
74h PCI Express Device Capabilities Register (Device_Capabilities_Regi 32 RO 0000_8001h
ster)
78h PCI Express Device Control Register (Device_Control_Register) 16 RW 2810h
7Ah PCI Express Device Status Register (Device_Status_Register) 16 W1C 0000h
7Ch PCI Express Link Capabilities Register (Link_Capabilities_Register) 32 RO 0073_F483h
80h PCI Express Link Control Register (Link_Control_Register) 16 RW 0008h
82h PCI Express Link Status Register (Link_Status_Register) 16 W1C 1000h
84h PCI Express Slot Capabilities Register (Slot_Capabilities_Register) 32 RO 0000_0000h
88h PCI Express Slot Control Register (Slot_Control_Register) 16 RW 03C0h
8Ah PCI Express Slot Status Register (Slot_Status_Register) 16 W1C 0008h
8Ch PCI Express Root Control Register (Root_Control_Register) 16 RW 0000h
8Eh PCI Express Root Capabilities Register (Root_Capabilities_Register) 16 RW 0000h
90h PCI Express Root Status Register (Root_Status_Register) 32 RW 0000_0000h
94h PCI Express Device Capabilities 2 Register (Device_Capabilities_2_ 32 RO 0000_001Fh
Register)
98h PCI Express Device Control 2 Register (Device_Control_2_Register) 16 RW 0000h
9Ch PCI Express Link Capabilities 2 Register (Link_Capabilities_2_Regi 32 RO 0000_000Eh
ster)
A0h PCI Express Link Control 2 Register (Link_Control_2_Register) 16 RW 0003h
A2h PCI Express Link Status 2 Register (Link_Status_2_Register) 16 RO 0000h
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1591
Memory map/register overview
Offset Register Width Access Reset value
(In bits)
100h PCI Express Advanced Error Reporting Capability ID Register (Adva 16 RO 0001h
nced_Error_Reporting_Capability_ID_Register)
104h PCI Express Uncorrectable Error Status Register (Uncorrectable_Er 32 W1C 0000_0000h
ror_Status_Register)
108h PCI Express Uncorrectable Error Mask Register (Uncorrectable_Er 32 RW 0000_0000h
ror_Mask_Register)
10Ch PCI Express Uncorrectable Error Severity Register (Uncorrectable_Er 32 RW 0046_2030h
ror_Severity_Register)
110h PCI Express Correctable Error Status Register (Correctable_Error_St 32 W1C 0000_0000h
atus_Register)
114h PCI Express Correctable Error Mask Register (Correctable_Error_Ma 32 RW 0000_2000h
sk_Register)
118h PCI Express Advanced Error Capabilities and Control Register (Adva 32 RW 0000_00A0h
nced_Error_Capabilities_and_Control_Register)
11Ch PCI Express Header Log Register 1 (Header_Log_Register_DWOR 32 RO 0000_0000h
D1)
120h PCI Express Header Log Register 2 (Header_Log_Register_DWOR 32 RO 0000_0000h
D2)
124h PCI Express Header Log Register 3 (Header_Log_Register_DWOR 32 RO 0000_0000h
D3)
128h PCI Express Header Log Register 4 (Header_Log_Register_DWOR 32 RO 0000_0000h
D4)
12Ch PCI Express Root Error Command Register (Root_Error_Command_ 32 RW 0000_0000h
Register)
130h PCI Express Root Error Status Register (Root_Error_Status_Regist 32 W1C 0000_0000h
er)
134h PCI Express Correctable Error Source ID Register (Correctable_Erro 16 RO 0000h
r_Source_ID_Register)
136h PCI Express Error Source ID Register (Error_Source_ID_Register) 16 RO 0000h
148h Secondary PCI Express Extended Capability Header (SPCIE_CAP_ 32 RO 0001_0019h
HEADER_REG)
14Ch Link Control 3 Register (LINK_CONTROL3_REG) 32 RW 0000_0000h
150h Lane Error Status Register (LANE_ERR_STATUS_REG) 32 W1C 0000_0000h
154h - 15Ah Lane Equalization Control Register (LANE0_EQUALIZATION_C 16 RO 7F7Fh
ONTROL - LANE3_EQUALIZATION_CONTROL)
71Ch Symbol Timer Register and Filter Mask 1 Register (SYMBOL_TIMER 32 RW 0000_0280h
_FILTER_1_OFF)
8BCh DBI Read-only Write Enable Register (MISC_CONTROL_1_OFF) 32 RW 0000_0000h
8E0h Coherency Control Register 1 (COHERENCY_CONTROL_1_OFF) 32 RW 0000_0000h
8E4h Coherency Control Register 2 (COHERENCY_CONTROL_2_OFF) 32 RW 0000_0000h
8E8h Coherency Control Register 3 (COHERENCY_CONTROL_3_OFF) 32 RU 0000_0000h
900h iATU Index Register (IATU_VIEWPORT_OFF) 32 RW 0000_0000h
904h iATU Region Control 1 Register (IATU_REGION_CTRL_1_OFF_I 32 RW 0000_0000h
NBOUND_0)
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1592 NXP Semiconductors
Chapter 28 PCI Express Interface Controller
Offset Register Width Access Reset value
(In bits)
904h iATU Region Control 1 Register (IATU_REGION_CTRL_1_OFF_O 32 RW 0000_0000h
UTBOUND_0)
908h iATU Region Control 2 Register (IATU_REGION_CTRL_2_OFF_I 32 RW 0000_0000h
NBOUND_0)
908h iATU Region Control 2 Register (IATU_REGION_CTRL_2_OFF_O 32 RW 0000_0000h
UTBOUND_0)
90Ch iATU Lower Base Address Register (IATU_LWR_BASE_ADDR_O 32 RW 0000_0000h
FF_INBOUND_0)
90Ch iATU Lower Base Address Register (IATU_LWR_BASE_ADDR_O 32 RW 0000_0000h
FF_OUTBOUND_0)
910h iATU Upper Base Address Register (IATU_UPPER_BASE_ADDR_ 32 RW 0000_0000h
OFF_INBOUND_0)
910h iATU Upper Base Address Register (IATU_UPPER_BASE_ADDR_ 32 RW 0000_0000h
OFF_OUTBOUND_0)
914h iATU Limit Address Register (IATU_LIMIT_ADDR_OFF_INBOUND_ 32 RW 0000_0FFFh
0)
914h iATU Limit Address Register (IATU_LIMIT_ADDR_OFF_OUTBOUND 32 RW 0000_0FFFh
_0)
918h iATU Region#N Lower Offset Address Register (IATU_LWR_TAR 32 RW 0000_0000h
GET_ADDR_OFF_INBOUND_0)
918h iATU Outbound Region#N Lower Offset Address Register (IATU_ 32 RW 0000_0000h
LWR_TARGET_ADDR_OFF_OUTBOUND_0)
91Ch iATU Upper Target Address Register (IATU_UPPER_TARGET_AD 32 RW 0000_0000h
DR_OFF_INBOUND_0)
91Ch iATU Upper Target Address Register (IATU_UPPER_TARGET_AD 32 RW 0000_0000h
DR_OFF_OUTBOUND_0)
1010h Base Address Register 0 Mask (BAR0_MASK) 32 WO 00FF_FFFFh
1014h Base Address Register 1 Mask (BAR1_MASK) 32 WO 03FF_FFFFh
1038h Expansion ROM Base Address Register Mask (RC mode) (EXP_ 32 WO 00FF_FFFFh
ROM_BAR_MASK_RC)
28.4.2.2 PCI Express Vendor ID Register (Vendor_ID_Register)
28.4.2.2.1 Offset
Register Offset
Vendor_ID_Register 0h
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1593
Memory map/register overview
28.4.2.2.2 Function
The vendor ID register is used to identify the manufacturer of the device.
NOTE
This register is writeable using internal accesses, but is read-
only from inbound configuration accesses by an external host.
28.4.2.2.3 Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Vendor_ID
W
Reset 0 0 0 1 1 0 0 1 0 1 0 1 0 1 1 1
28.4.2.2.4 Fields
Field Function
15-0 Vendor ID
Vendor_ID 0x1957 (NXP)
28.4.2.3 PCI Express Device ID Register (Device_ID_Register)
28.4.2.3.1 Offset
Register Offset
Device_ID_Register 2h
28.4.2.3.2 Function
The device ID register is used to identify the device.
NOTE
This register is writeable using internal accesses, but is read-
only from inbound configuration accesses by an external host.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1594 NXP Semiconductors
Chapter 28 PCI Express Interface Controller
28.4.2.3.3 Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Device_ID
W
Reset 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
28.4.2.3.4 Fields
Field Function
15-0 Device ID
1000000010000000b - LS1043A with security
Device_ID
1000000010000001b - LS1043A without security
1000000010001000b - LS1023A with security
1000000010001001b - LS1023A without security
28.4.2.4 PCI Express Command Register (Command_Register)
28.4.2.4.1 Offset
Register Offset
Command_Register 4h
28.4.2.4.2 Function
The command register provides control over the ability to generate and respond to PCI
Express cycles.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1595
Memory map/register overview
28.4.2.4.3 Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IO_space
R
Parity_error_response
Interrupt_Disable
Memory_space
Bus_master
Reserved
Reserved
Reserved
Reserved
SER
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
28.4.2.4.4 Fields
Field Function
15-11 Reserved
—
10 Interrupt disable
Interrupt_Disabl Controls the ability to generate INTx interrupt messages.
e
Any INTx emulation interrupts already asserted by this device must be deasserted when this bit is set.
0b - Enables INTx interrupt messages
1b - Disables INTx interrupt messages
9 Reserved
—
8 SERR# enable
SERR Controls the reporting of fatal and non-fatal errors detected by the device to the Root Complex.
NOTE: The error control and status bits in the command and status registers control PCI-compatible
error reporting. PCI Express advanced error reporting is controlled by the PCI Express device
control register described in PCI Express Device Control Register (Device_Control_Register)
and the advanced error reporting registers (offsets 100h through 137h).
0b - Disables reporting
1b - Enables reporting
7 Reserved
—
6 Parity error response
Parity_error_res Controls whether this PCI Express controller responds to parity errors.
ponse
NOTE: The error control and status bits in the command and status registers control PCI-compatible
error reporting. PCI Express advanced error reporting is controlled by the PCI Express device
control register described in PCI Express Device Control Register (Device_Control_Register)
and the advanced error reporting registers (offsets 100h through 137h).
0b - Parity errors are ignored and normal operation continues.
1b - Parity errors cause the appropriate bit in the PCI Express status register to be set. However,
note that errors are reported based on the values set in the PCI Express error enable and detection
registers.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1596 NXP Semiconductors
Chapter 28 PCI Express Interface Controller
Field Function
5-3 Reserved
—
2 Bus master enable
Bus_master Indicates whether this PCI Express device is configured as a master.
RC mode: Clearing this bit disables the ability of the device to forward memory transactions upstream.
This causes any inbound memory transaction to be treated as an unsupported request.
0b - Disables the ability to generate PCI Express accesses
1b - Enables this PCI Express controller to behave as a PCI Express bus master
1 Memory space enable
Memory_space Controls whether this PCI Express device (as a target) responds to memory accesses.
RC mode: This bit is ignored. It does not affect outbound memory transaction
0b - This PCI Express device does not respond to PCI Express memory space accesses.
1b - This PCI Express device responds to PCI Express memory space accesses.
0 I/O space enable
IO_space RC mode: This bit is ignored. It does not affect outbound IO transaction.
0b - This PCI Express device (as a target) does not respond to PCI Express I/O space accesses.
1b - This PCI Express device (as a target) does respond to PCI Express I/O space accesses.
28.4.2.5 PCI Express Status Register (Status_Register)
28.4.2.5.1 Offset
Register Offset
Status_Register 6h
28.4.2.5.2 Function
The status register is used to record status information for PCI Express related events.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1597
Memory map/register overview
28.4.2.5.3 Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W1C Master_data_parity_error_detected
Received_master_abort
Signaled_system_error
Received_target_abort
Signaled_target_abort
Detected_parity_error
Capabilities_List
Interrupt_Status
R
Reserved
Reserved
Reserved
W1C
W1C
W1C
W1C
W1C
W1C
W1C
W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
28.4.2.5.4 Fields
Field Function
15 Detected parity error
Detected_parity Set whenever a device receives a poisoned TLP regardless of the state of bit 6 in the command register.
_error 1
14 Signaled system error
Signaled_syste Set whenever a device sends a ERR_FATAL or ERR_NONFATAL message and the SERR enable bit in
m_error the command register is set.1
13 Received master abort
Received_maste Set whenever a requestor receives a completion with unsupported request completion status.1
r_abort
12 Received target abort
Received_target Set whenever a device receives a completion with completer abort completion status.1
_abort
11 Signaled target abort
Signaled_target Set whenever a device completes a request using completer abort completion status.1
_abort
10-9 Reserved
—
8 Master data parity error
Master_data_pa Set by the requestor (primary side for Type1 headers) when either the requestor receives a completion
rity_error_detect marked poisoned or the requestor poisons a write request. Note that the parity error enable bit (bit 6) in
ed the command register must be set for this bit to be set.1
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1598 NXP Semiconductors
Chapter 28 PCI Express Interface Controller
Field Function
7-5 Reserved
—
4 Capabilities list
Capabilities_List All PCI Express devices are required to implement the PCI Express capability structure.
3 Interrupt status
Interrupt_Status Set when an INTx interrupt message is pending internally to the device.
Note that this bit is associated with INTx messages and not Message Signaled Interrupts.
2-0 Reserved
—
1. The error control and status bits in the command and status registers control PCI-compatible error reporting. PCI Express
advanced error reporting is controlled by the PCI Express device control register described in PCI Express Device Control
Register (Device_Control_Register) and the advanced error reporting capability structure starting at offset 100h.
28.4.2.6 PCI Express Revision ID Register (Revision_ID_Register)
28.4.2.6.1 Offset
Register Offset
Revision_ID_Register 8h
28.4.2.6.2 Function
The revision ID register is used to identify the revision of the device.
NOTE
This register is writeable using internal accesses, but is read-
only from inbound configuration accesses by an external host.
For Si 1.1, the revision ID is 0x11.
For Si 1.0, the revision ID is 0x10.
28.4.2.6.3 Diagram
Bits 7 6 5 4 3 2 1 0
R Revision_ID
W
Reset 0 0 0 1 0 0 0 1
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1599
Memory map/register overview
28.4.2.6.4 Fields
Field Function
7-0 Revision ID
Revision_ID Revision specific.
28.4.2.7 PCI Express Class Code Register (Class_Code_Register)
28.4.2.7.1 Offset
Register Offset
Class_Code_Register 9h
28.4.2.7.2 Function
The class code register is comprised of three single-byte fields—base class (offset 0x0B),
sub-class (offset 0x0A), and programming interface (offset 0x09)—that indicate the basic
functionality of the function.
NOTE
This register is writeable using internal accesses, but is read-
only from inbound configuration accesses by an external host.
28.4.2.7.3 Diagram
Bits 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8
R Base_Class Sub_Class
W
Reset 0 0 0 0 1 0 1 1 0 0 1 0 0 0 0 0
Bits 7 6 5 4 3 2 1 0
R Programming_Interface
W
Reset 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1600 NXP Semiconductors
Chapter 28 PCI Express Interface Controller
28.4.2.7.4 Fields
Field Function
23-16 Base Class
Base_Class 0x0B-Processor
15-8 Sub-Class
Sub_Class
7-0 Programming_Interface
Programming_In
terface
28.4.2.8 PCI Express Cache Line Size Register (Cache_Line_Size_
Register)
28.4.2.8.1 Offset
Register Offset
Cache_Line_Size_Regi Ch
ster
28.4.2.8.2 Function
The cache line size register is provided for legacy compatibility purposes (PCI 2.3); it is
not used for PCI Express device functionality.
28.4.2.8.3 Diagram
Bits 7 6 5 4 3 2 1 0
R
Cache_Line_Size
W
Reset 0 0 0 0 0 0 0 0
28.4.2.8.4 Fields
Field Function
7-0 Cache Line Size
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1601
Memory map/register overview
Field Function
Cache_Line_Siz Represents the cache line size of the processor in terms of 32-bit words (8 32-bit words = 32 bytes). Note
e that for PCI Express operation this register is ignored.
28.4.2.9 PCI Express Latency Timer Register (Latency_Timer_Regist
er)
28.4.2.9.1 Offset
Register Offset
Latency_Timer_Register Dh
28.4.2.9.2 Function
The latency timer register is provided for legacy compatibility purposes (PCI 2.3); it is
not used for PCI Express device functionality.
28.4.2.9.3 Diagram
Bits 7 6 5 4 3 2 1 0
R Latency_Timer
W
Reset 0 0 0 0 0 0 0 0
28.4.2.9.4 Fields
Field Function
7-0 Latency_Timer
Latency_Timer Note that for PCI Express operation this register is ignored.
28.4.2.10 PCI Express Header Type Register (Header_Type_Register)
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1602 NXP Semiconductors
Chapter 28 PCI Express Interface Controller
28.4.2.10.1 Offset
Register Offset
Header_Type_Register Eh
28.4.2.10.2 Function
The PCI Express header type register is used to identify the layout of the PCI compatible
header.
28.4.2.10.3 Diagram
Bits 7 6 5 4 3 2 1 0
Header_Layout
Multifunction
W
Reset 0 0 0 0 0 0 0 1
28.4.2.10.4 Fields
Field Function
7 Multifunction
Multifunction Identifies whether a device supports multiple functions
0b - Single function device
1b - Multiple function device
6-0 Header Layout
Header_Layout All other encodings reserved.
0000001b - Root Complex - Type 1 layout.
28.4.2.11 PCI Express Base Address Register 0 (BAR0)
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1603
Memory map/register overview
28.4.2.11.1 Offset
Register Offset
BAR0 10h
28.4.2.11.2 Function
The PCI Express base address registers (BARs) point to the beginning of distinct address
ranges which the device should claim.
28.4.2.11.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
ADDRESS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ADDRES
Reserved
MemSp
PRE
TYP
W
E
S
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
28.4.2.11.4 Fields
Field Function
31-12 Base address
ADDRESS Indicates the base address of the inbound memory window 0. The default size is 16 MB.
11-4 Reserved
—
3 Prefetchable
PREF
2-1 Type
00b - Locate anywhere in 32-bit address space.
TYPE
0 Memory space indicator
MemSp Base Address registers that map to Memory Space must return a 0 in bit 0.
Base Address registers that map to I/O Space must return a 1 in bit 0.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1604 NXP Semiconductors
Chapter 28 PCI Express Interface Controller
28.4.2.12 PCI Express Primary Bus Number Register (Primary_Bus_
Number_Register)
28.4.2.12.1 Offset
Register Offset
Primary_Bus_Number_R 18h
egister
28.4.2.12.2 Function
This register is present only in the Type 1 Header (RC mode).
28.4.2.12.3 Diagram
Bits 7 6 5 4 3 2 1 0
R
Primary_Bus_Number
W
Reset 0 0 0 0 0 0 0 0
28.4.2.12.4 Fields
Field Function
7-0 Primary Bus Number
Primary_Bus_N Bus that is connected to the upstream interface. Note that this register is programmed during system
umber enumeration; in RC mode this register should remain 0x00.
28.4.2.13 PCI Express Secondary Bus Number Register (Secondary_
Bus_Number_Register)
28.4.2.13.1 Offset
Register Offset
Secondary_Bus_Number 19h
_Register
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1605
Memory map/register overview
28.4.2.13.2 Function
This register is present only in the Type 1 Header (RC mode).
28.4.2.13.3 Diagram
Bits 7 6 5 4 3 2 1 0
R
Secondary_Bus_Number
W
Reset 0 0 0 0 0 0 0 0
28.4.2.13.4 Fields
Field Function
7-0 Secondary Bus Number
Secondary_Bus Bus that is directly connected to the downstream interface. Note that this register is programmed during
_Number system enumeration; in RC mode, this register is typically programmed to 0x01.
28.4.2.14 PCI Express Subordinate Bus Number Register (Subordin
ate_Bus_Number_Register)
28.4.2.14.1 Offset
Register Offset
Subordinate_Bus_Numb 1Ah
er_Register
28.4.2.14.2 Function
This register is present only in the Type 1 Header (RC mode).
28.4.2.14.3 Diagram
Bits 7 6 5 4 3 2 1 0
R
Subordinate_Bus_Number
W
Reset 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1606 NXP Semiconductors
Chapter 28 PCI Express Interface Controller
28.4.2.14.4 Fields
Field Function
7-0 Subordinate Bus Number
Subordinate_Bu Highest bus number that is on the downstream interface.
s_Number
28.4.2.15 PCI Express I/O Base Register (IO_Base_Register)
28.4.2.15.1 Offset
Register Offset
IO_Base_Register 1Ch
28.4.2.15.2 Function
This register is present only in the Type 1 Header (RC mode).
Note that this device does not support inbound I/O transactions.
28.4.2.15.3 Diagram
Bits 7 6 5 4 3 2 1 0
Address_Decode_Type
IO_Start_Address
W
Reset 0 0 0 0 0 0 0 1
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1607
Memory map/register overview
28.4.2.15.4 Fields
Field Function
7-4 I/O Start Address
IO_Start_Addres Specifies bits 15:12 of the I/O space start address
s
3-0 Address Decode Type
Address_Decod Specifies the number of I/O address bits.
e_Type
All other settings are reserved.
0000b - 16-bit I/O address decode
0001b - 32-bit I/O address decode
28.4.2.16 PCI Express I/O Limit Register (IO_Limit_Register)
28.4.2.16.1 Offset
Register Offset
IO_Limit_Register 1Dh
28.4.2.16.2 Function
This register is present only in the Type 1 Header (RC mode).
Note that this device does not support inbound I/O transactions.
28.4.2.16.3 Diagram
Bits 7 6 5 4 3 2 1 0
Address_Decode_Type
IO_Limit_Address
W
Reset 0 0 0 0 0 0 0 1
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1608 NXP Semiconductors
Chapter 28 PCI Express Interface Controller
28.4.2.16.4 Fields
Field Function
7-4 I/O Limit Address
IO_Limit_Addres Specifies bits 15:12 of the I/O space ending address
s
3-0 Address Decode Type
Address_Decod Specifies the number of I/O address bits.
e_Type
All other settings are reserved.
0000b - 16-bit I/O address decode
0001b - 32-bit I/O address decode
28.4.2.17 PCI Express Secondary Status Register (Secondary_Status
_Register)
28.4.2.17.1 Offset
Register Offset
Secondary_Status_Reg 1Eh
ister
28.4.2.17.2 Function
This register is present only in the Type 1 Header (RC mode).
28.4.2.17.3 Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W1C MDPE
RMA
RTA
STA
R
SS
DP
Reserved
Reserved
E
E
W1C
W1C
W1C
W1C
W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1609
Memory map/register overview
28.4.2.17.4 Fields
Field Function
15 Detected parity error
DPE This bit is set whenever the secondary side receives a poisoned TLP regardless of the state of the parity
error response bit.
14 Signaled system error
SSE This bit is set when a device sends a ERR_FATAL or ERR_NONFATAL message, provided the SERR
enable bit in the command register is set to enable reporting.
13 Received master abort
RMA This bit is set when the secondary side receives an unsupported request (UR) completion.
12 Received target abort
RTA This bit is set when the secondary side receives a completer abort (CA) completion.
11 Signaled target abort
STA This bit is set when the secondary side issues a CA completion.
10-9 Reserved
—
8 Master data parity error
MDPE This bit is set when the parity error response bit is set and the secondary side requester receives a
poisoned completion or poisons a write request. If the parity error response bit is cleared, this bit is never
set.
7-0 Reserved
—
28.4.2.18 PCI Express Memory Base Register (Memory_Base_Regi
ster)
28.4.2.18.1 Offset
Register Offset
Memory_Base_Register 20h
28.4.2.18.2 Function
This register is present only in the Type 1 Header (RC mode).
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1610 NXP Semiconductors
Chapter 28 PCI Express Interface Controller
28.4.2.18.3 Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Memory_Base Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
28.4.2.18.4 Fields
Field Function
15-4 Memory base address
Memory_Base Specifies bits 31:20 of the non-prefetchable memory space start address. Typically used for specifying
memory-mapped I/O space.
NOTE: Inbound posted transactions hitting into the mem base/limit range are ignored; inbound non-
posted transactions hitting into the mem base/limit range results in an unsupported request
response.
3-0 Reserved
—
28.4.2.19 PCI Express Memory Limit Register (Memory_Limit_Registe
r)
28.4.2.19.1 Offset
Register Offset
Memory_Limit_Register 22h
28.4.2.19.2 Function
This register is present only in the Type 1 Header (RC mode).
28.4.2.19.3 Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Memory_Limit Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1611
Memory map/register overview
28.4.2.19.4 Fields
Field Function
15-4 Memory limit address
Memory_Limit Specifies bits 31:20 of the non-prefetchable memory space ending address. Typically used for specifying
memory-mapped I/O space.
NOTE: Inbound posted transactions hitting into the mem base/limit range are ignored; inbound non-
posted transactions hitting into the mem base/limit range results in unsupported request
response.
3-0 Reserved
—
28.4.2.20 PCI Express Prefetchable Memory Base Register (Prefetch
able_Memory_Base_Register)
28.4.2.20.1 Offset
Register Offset
Prefetchable_Memory_ 24h
Base_Register
28.4.2.20.2 Function
This register is present only in the Type 1 Header (RC mode).
28.4.2.20.3 Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Address_Decode_Type
PF_Memory_Base
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1612 NXP Semiconductors
Chapter 28 PCI Express Interface Controller
28.4.2.20.4 Fields
Field Function
15-4 Prefetchable memory base address
PF_Memory_Ba Specifies bits 31:20 of the prefetchable memory space start address.
se
3-0 Address Decode Type
Address_Decod Specifies the number of prefetchable memory address bits.
e_Type
All other settings reserved.
0000b - 32-bit memory address decode
0001b - 64-bit memory address decode
28.4.2.21 PCI Express Prefetchable Memory Limit Register (Prefetch
able_Memory_Limit_Register)
28.4.2.21.1 Offset
Register Offset
Prefetchable_Memory_ 26h
Limit_Register
28.4.2.21.2 Function
This register is present only in the Type 1 Header (RC mode).
28.4.2.21.3 Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Address_Decode_Type
PF_Memory_Limit
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1613
Memory map/register overview
28.4.2.21.4 Fields
Field Function
15-4 Prefetchable memory limit address
PF_Memory_Li Specifies bits 31:20 of the prefetchable memory space ending address.
mit
3-0 Address decode type
Address_Decod Specifies the number of prefetchable memory address bits.
e_Type
All other settings reserved.
0000b - 32-bit memory address decode
0001b - 64-bit memory address decode
28.4.2.22 PCI Express Prefetchable Base Upper 32 Bits Register (Pref
etchable_Base_Upper_32_Bits_Register)
28.4.2.22.1 Offset
Register Offset
Prefetchable_Base_Up 28h
per_32_Bits_Register
28.4.2.22.2 Function
This register is present only in the Type 1 Header (RC mode).
28.4.2.22.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
PF_Base_Upper_32_Bits
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
PF_Base_Upper_32_Bits
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1614 NXP Semiconductors
Chapter 28 PCI Express Interface Controller
28.4.2.22.4 Fields
Field Function
31-0 Prefetchable memory base address (upper portion)
PF_Base_Upper Specifies bits 64:32 of the prefetchable memory space start address when the address decode type field
_32_Bits in the prefetchable memory base register is 0x01.
28.4.2.23 PCI Express Prefetchable Limit Upper 32 Bits Register (Pref
etchable_Limit_Upper_32_Bits_Register)
28.4.2.23.1 Offset
Register Offset
Prefetchable_Limit_U 2Ch
pper_32_Bits_Register
28.4.2.23.2 Function
This register is present only in the Type 1 Header (RC mode).
28.4.2.23.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
PF_Limit_Upper_32_Bits
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
PF_Limit_Upper_32_Bits
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
28.4.2.23.4 Fields
Field Function
31-0 Prefetchable memory limit address (upper portion)
PF_Limit_Upper Specifies bits 64-32 of the prefetchable memory space ending address when the address decode type
_32_Bits field in the prefetchable memory limit register is 0x01.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1615
Memory map/register overview
28.4.2.24 PCI Express I/O Base Upper 16 Bits Register (IO_Base_
Upper_16_Bits_Register)
28.4.2.24.1 Offset
Register Offset
IO_Base_Upper_16_Bit 30h
s_Register
28.4.2.24.2 Function
This register is present only in the Type 1 Header (RC mode).
Note that this device does not support inbound I/O transactions.
28.4.2.24.3 Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R IO_Base_Upper_16_Bits
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
28.4.2.24.4 Fields
Field Function
15-0 I/O base address (upper portion)
IO_Base_Upper Specifies bits 31-16 of the I/O space start address when the address decode type field in the I/O base
_16_Bits register is 0x01.
28.4.2.25 PCI Express I/O Limit Upper 16 Bits Register (IO_Limit_Upp
er_16_Bits_Register)
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1616 NXP Semiconductors
Chapter 28 PCI Express Interface Controller
28.4.2.25.1 Offset
Register Offset
IO_Limit_Upper_16_Bits_ 32h
Register
28.4.2.25.2 Function
This register is present only in the Type 1 Header (RC mode).
Note that this device does not support inbound I/O transactions.
28.4.2.25.3 Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R IO_Limit_Upper_16_Bits
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
28.4.2.25.4 Fields
Field Function
15-0 I/O limit address (upper portion)
IO_Limit_Upper Specifies bits 31-16 of the I/O space ending address when the address decode type field in the I/O limit
_16_Bits register is 0x01.
28.4.2.26 Capabilities Pointer Register (Capabilities_Pointer_Registe
r)
28.4.2.26.1 Offset
Register Offset
Capabilities_Pointer_Reg 34h
ister
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1617
Memory map/register overview
28.4.2.26.2 Function
The capabilities pointer identifies additional functionality supported by the device.
28.4.2.26.3 Diagram
Bits 7 6 5 4 3 2 1 0
R Capabilities_Pointer
W
Reset 0 1 0 0 0 0 0 0
28.4.2.26.4 Fields
Field Function
7-0 Capabilities Pointer
Capabilities_Poi The capabilities pointer provides the offset for additional PCI-compatible registers above the common 64-
nter byte header.
28.4.2.27 PCI Express Expansion ROM Base Address Register (RC-
Mode) (Expansion_ROM_BAR_Type1)
28.4.2.27.1 Offset
Register Offset
Expansion_ROM_BAR_ 38h
Type1
28.4.2.27.2 Function
The Expansion ROM Base Address register is located at offset 0x38 in the Type 1
Header (RC mode).
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1618 NXP Semiconductors
Chapter 28 PCI Express Interface Controller
28.4.2.27.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
ROM_Base_Address
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ROM_Base_Address
ROMBAR_EN
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
28.4.2.27.4 Fields
Field Function
31-11 Expansion ROM base address
ROM_Base_Ad Specifies bits 31:11 of the non-prefetchable expansion ROM space start address. Typically used for
dress specifying memory-mapped I/O space. The default size is 16M.
10-1 Reserved
—
0 Expansion ROM enable
ROMBAR_EN This bit controls whether or not the device accepts accesses to its expansion ROM
0b - The expansion ROM address space is disabled.
1b - Address decoding is enabled.
28.4.2.28 PCI Express Interrupt Line Register (Interrupt_Line_Regis
ter)
28.4.2.28.1 Offset
Register Offset
Interrupt_Line_Register 3Ch
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1619
Memory map/register overview
28.4.2.28.2 Function
The interrupt line register is used by device drivers and OS software to communicate
interrupt line routing information. Values in this register are programmed by system
software and are system specific.
28.4.2.28.3 Diagram
Bits 7 6 5 4 3 2 1 0
R
Interrupt_Line
W
Reset 1 1 1 1 1 1 1 1
28.4.2.28.4 Fields
Field Function
7-0 Interrupt line
Interrupt_Line Used to communicate interrupt line routing information.
28.4.2.29 PCI Express Interrupt Pin Register (Interrupt_Pin_Register)
28.4.2.29.1 Offset
Register Offset
Interrupt_Pin_Register 3Dh
28.4.2.29.2 Function
The interrupt pin register identifies the legacy interrupt (INTx) messages the device (or
function) uses.
28.4.2.29.3 Diagram
Bits 7 6 5 4 3 2 1 0
R Interrupt_pin
W
Reset 0 0 0 0 0 0 0 1
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1620 NXP Semiconductors
Chapter 28 PCI Express Interface Controller
28.4.2.29.4 Fields
Field Function
7-0 Interrupt pin
Interrupt_pin Legacy INTx message used by this device.
All other settings reserved.
00000000b - This device does not use legacy interrupt (INTx) messages.
00000001b - INTA
28.4.2.30 PCI Express Bridge Control Register (Bridge_Control_R
egister)
28.4.2.30.1 Offset
Register Offset
Bridge_Control_Register 3Eh
28.4.2.30.2 Function
This register is present only in the Type 1 Header (RC mode).
28.4.2.30.3 Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Scnd_RST
VGA_EN
Reserved
Reserved
SERR_E
ISA_E
PE
W R
N
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
28.4.2.30.4 Fields
Field Function
15-7 Reserved
—
6 Secondary bus reset
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1621
Memory map/register overview
Field Function
Scnd_RST
5-4 Reserved
—
3 VGA enable
VGA_EN
2 ISA enable
ISA_EN
1 SERR enable
SERR_EN This bit controls the propagation of ERR_COR, ERR_NONFATAL, and ERR_FATAL responses received
on the secondary side.
0 Parity error response
PER This bit controls the logging of poisoned TLPs in the Master Data Parity Error bit in the Secondary Status
register.
28.4.2.31 PCI Express Power Management Capability ID Register
(Power_Management_Capability_ID_Register)
28.4.2.31.1 Offset
Register Offset
Power_Management_ 40h
Capability_ID_Register
28.4.2.31.2 Diagram
Bits 7 6 5 4 3 2 1 0
R Power_Mgmt_Capability_ID
W
Reset 0 0 0 0 0 0 0 1
28.4.2.31.3 Fields
Field Function
7-0 CAP_ID
Power_Mgmt_C Power Management = 0x01
apability_ID
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1622 NXP Semiconductors
Chapter 28 PCI Express Interface Controller
28.4.2.32 PCI Express Power Management Capabilities Register
(Power_Management_Capabilities_Register)
28.4.2.32.1 Offset
Register Offset
Power_Management_ 42h
Capabilities_Register
28.4.2.32.2 Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PME_Support
PME_CLK
AUX_Curr
Version
Reserved
R
D2
D1
DS
I
W
Reset 0 1 1 1 1 1 1 0 0 0 1 0 0 0 1 1
28.4.2.32.3 Fields
Field Function
15-11 PME support
PME_Support Indicates the power states that this device supports
10 D2 support
D2
9 D1 support
D1
8-6 AUX Current
AUX_Curr
5 Device Specific Initialization
DSI
4 Reserved
—
3 PME clock
PME_CLK Does not apply to PCI Express.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1623
Memory map/register overview
Field Function
2-0 Version
Version
28.4.2.33 PCI Express Power Management Status and Control
Register (Power_Management_Status_and_Control_Regi
ster)
28.4.2.33.1 Offset
Register Offset
Power_Management_Sta 44h
tus_and_Control_Regi
ster
28.4.2.33.2 Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W1C PME_STAT
Power_State
Data_Select
Data_Scale
R
Reserved
PME_E
N
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
28.4.2.33.3 Fields
Field Function
15 PME Status
PME_STAT
14-13 Data Scale
Data_Scale Obtained directly from the PCI Express base specification.
12-9 Data Select
Data_Select Obtained directly from the PCI Express base specification.
8 PME_En
PME_EN PME Enable.
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1624 NXP Semiconductors
Chapter 28 PCI Express Interface Controller
Field Function
NOTE: Bitfield access is sticky.
7-2 Reserved
—
1-0 Power State
Power_State Indicates the current power state of the function.
00b - D0
01b - D1
10b - D2
11b - D3
28.4.2.34 PCI Express Power Management Data Register (Power_Ma
nagement_Data_Register)
28.4.2.34.1 Offset
Register Offset
Power_Management_Dat 47h
a_Register
28.4.2.34.2 Diagram
Bits 7 6 5 4 3 2 1 0
R Data
W
Reset 0 0 0 0 0 0 0 0
28.4.2.34.3 Fields
Field Function
7-0 Data
Data Obtained from the PCI Express base specification.
28.4.2.35 PCI Express Capability ID Register (Capability_ID_Register)
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1625
Memory map/register overview
28.4.2.35.1 Offset
Register Offset
Capability_ID_Register 70h
28.4.2.35.2 Diagram
Bits 7 6 5 4 3 2 1 0
PCI_Express_Capability_ID
W
Reset 0 0 0 1 0 0 0 0
28.4.2.35.3 Fields
Field Function
7-0 Capability ID
PCI_Express_C PCI Express = 0x10
apability_ID
28.4.2.36 PCI Express Capabilities Register (Capabilities_Register)
28.4.2.36.1 Offset
Register Offset
Capabilities_Register 72h
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1626 NXP Semiconductors
Chapter 28 PCI Express Interface Controller
28.4.2.36.2 Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Interrupt_Message_Number
Device_Port_Type
Capability_Version
Reserved
Slot
R
W
Reset 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0
28.4.2.36.3 Fields
Field Function
15-14 Reserved
—
13-9 Interrupt Message Number
Interrupt_Messa If this function is allocated more than one MSI interrupt number, then this register is required to contain
ge_Number the offset between the base Message Data and the MSI Message that is generated when any of the
status bits in either the Slot Status register or the Root Port Status register, of this capability structure, are
set.
8 Slot Implemented
Slot (RC mode only)
7-4 Device/Port Type
0100b - (RC mode)
Device_Port_Ty
pe
3-0 Capability Version
Capability_Versi Indicates the defined PCI Express capability structure version number.
on
28.4.2.37 PCI Express Device Capabilities Register (Device_Capabilit
ies_Register)
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1627
Memory map/register overview
28.4.2.37.1 Offset
Register Offset
Device_Capabilities_Regi 74h
ster
28.4.2.37.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSPLV
CSPL
Reserved
Reserved
R
FLR
C
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAX_PL_SIZE_SUP
EP_L0s_LAT
EP_L1_LAT
PHAN_FCT
Reserved
RBE
E
T
R
W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
28.4.2.37.3 Fields
Field Function
31-29 Reserved
—
28 Function Level Reset Capability
FLRC For RC mode, the reset value for this bit is 0.
27-26 Captured Slot Power Limit Scale
CSPLS
25-18 Captured Slot Power Limit Value
CSPLV For RC mode, the reset value for this field is 00h.
17-16 Reserved
—
15 Role-Based Error Reporting
RBER
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1628 NXP Semiconductors
Chapter 28 PCI Express Interface Controller
Field Function
14-12 Reserved. System software must ignore the value read from these bits. System software is permitted to
write any value to these bits.
—
11-9 Endpoint L1 Acceptable Latency
EP_L1_LAT
8-6 Endpoint L0s Acceptable Latency
EP_L0s_LAT
5 Extended Tag Field Supported
ET
4-3 Phantom Functions Supported
PHAN_FCT
2-0 Max_Payload_Size Supported
MAX_PL_SIZE_ Maximum payload size supported. 001 = 256-bytes
SUP
28.4.2.38 PCI Express Device Control Register (Device_Control_R
egister)
28.4.2.38.1 Offset
Register Offset
Device_Control_Register 78h
28.4.2.38.2 Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MAX_PAYLOAD_SIZE
MAX_READ_SIZE
RO
NFE
EN
IFL
PF
ET
UR
FE
CE
AP
W
E
E
S
R
R
Reset 0 0 1 0 1 0 0 0 0 0 0 1 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1629
Memory map/register overview
28.4.2.38.3 Fields
Field Function
15 Initiate Function Level Reset
IFLR
14-12 Maximum_Read_Request_Size
MAX_READ_SI
ZE
11 Enable No Snoop
ENS
10 AUX Power PM Enable
APE
9 Phantom Functions Enable
PFE
8 Extended Tag Field Enable
ETE
7-5 Max_Payload_Size
MAX_PAYLOAD Maximum payload size
_SIZE
4 Enable Relaxed Ordering
RO
3 Unsupported Request Reporting Enable
URR
2 Fatal Error Reporting Enable
FER
1 Non-Fatal Error Reporting Enable
NFER
0 Correctable Error Reporting Enable
CER
28.4.2.39 PCI Express Device Status Register (Device_Status_Regist
er)
28.4.2.39.1 Offset
Register Offset
Device_Status_Register 7Ah
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1630 NXP Semiconductors
Chapter 28 PCI Express Interface Controller
28.4.2.39.2 Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W1C URD
CED
APD
W1C NFE
R
TP
Reserved
FE
D
D
W1C
W1C
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
28.4.2.39.3 Fields
Field Function
15-6 Reserved
—
5 Transactions Pending
TP
4 AUX Power Detected
APD
3 Unsupported Request Detected
URD
2 Fatal Error Detected
FED
1 Non-Fatal Error Detected
NFED
0 Correctable Error Detected
CED
28.4.2.40 PCI Express Link Capabilities Register (Link_Capabilities_
Register)
28.4.2.40.1 Offset
Register Offset
Link_Capabilities_Regist 7Ch
er
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1631
Memory map/register overview
28.4.2.40.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SD_ERR_RPT_CA
L1_EX_LAT
Port_Number
DLLARC
LBWN
Reserved
CPM
AOC
R
P
W
Reset 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAX_LINK_SP
MAX_LINK_W
L0s_EX_LAT
L1_EX_LAT
ASPM
W
Reset 1 1 1 1 0 1 0 0 1 0 0 0 0 0 1 1
28.4.2.40.3 Fields
Field Function
31-24 Port Number
Port_Number This field indicates the PCI Express Port number for the given PCI Express Link
23 Reserved
—
22 ASPM Optionality Compliance
AOC Software is permitted to use the value of this bit to help determine whether to enable ASPM or whether to
run ASPM compliance tests.
21 Link Bandwidth Notification Capability
LBWN In RC-mode it is hardwired to 1.
20 Data Link Layer Active Reporting Capable
DLLARC Set to 1 when in RC.
19 Surprise Down Error Reporting Capable
SD_ERR_RPT_
CAP
18 Clock Power Management
CPM
17-15 L1 Exit Latency
L1_EX_LAT
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1632 NXP Semiconductors
Chapter 28 PCI Express Interface Controller
Field Function
14-12 L0s Exit Latency
L0s_EX_LAT
11-10 Active State Power Management (ASPM) Support
ASPM
9-4 Maximum Link Width
MAX_LINK_W
3-0 Maximum Link Speed
0001b - 2.5 GT/s link
MAX_LINK_SP
0010b - 5.0 GT/s
28.4.2.41 PCI Express Link Control Register (Link_Control_Register)
28.4.2.41.1 Offset
Register Offset
Link_Control_Register 80h
28.4.2.41.2 Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
HW_AUTO_WIDTH_DIS
ASPM_CTL
EXT_SYN
Reserved
Reserved
LBMIE
LABIE
ECPM
RCB
CCC
LD
W
R
L
C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
28.4.2.41.3 Fields
Field Function
15-12 Reserved
—
11 Link Autonomous Bandwidth Interrupt Enable
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1633
Memory map/register overview
Field Function
LABIE
10 Link Bandwidth Management Interrupt Enable
LBMIE
9 Hardware Autonomous Width Disable
HW_AUTO_WID
TH_DIS
8 Enable Clock Power Management
ECPM
7 Extended Synch
EXT_SYNC
6 Common Clock Configuration
CCC
5 Retrain Link
RL In RC mode, setting this bit initiates link retraining by directing the Physical Layer LTSSM to the Recovery
state; reads of this bit always return 0.
4 Link Disable
LD
3 Read Completion Boundary (RCB)
RCB
2 Reserved
—
1-0 Active State Power Management (ASPM) Control
ASPM_CTL
28.4.2.42 PCI Express Link Status Register (Link_Status_Register)
28.4.2.42.1 Offset
Register Offset
Link_Status_Register 82h
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1634 NXP Semiconductors
Chapter 28 PCI Express Interface Controller
28.4.2.42.2 Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NEG_LINK_W
LINK_SP
LBMS
SCC
R
LAB
LT
Reserved
Reserved
S
W1C
W1C
Reset 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
28.4.2.42.3 Fields
Field Function
15 Link Autonomous Bandwidth Status
LABS NOTE: This bit is write-1-clear in RC mode
14 Link Bandwidth Management Status
LBMS NOTE: This bit is write-1-clear in RC mode.
13 Reserved
—
12 Slot Clock Configuration
SCC
11 Link Training
LT
10 Reserved.
—
9-4 Negotiated link width
NEG_LINK_W All other encodings are reserved. The value in this field is undefined when the link is not up.
000001b - x1
000010b - x2
000100b - x4
3-0 Current Link Speed
0001b - 2.5 GT/s
LINK_SP
0010b - 5.0 GT/s
28.4.2.43 PCI Express Slot Capabilities Register (Slot_Capabilities_
Register)
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1635
Memory map/register overview
28.4.2.43.1 Offset
Register Offset
Slot_Capabilities_Regist 84h
er
28.4.2.43.2 Function
This register is supported only for RC mode.
28.4.2.43.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Physical_Slot_Number
NOCMDCPLSUP
EMIP
SPL
R
S
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MRLS
HPD
PCP
ABP
PIP
SPL
AIP
R
SPL
HP
S
S
P
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
28.4.2.43.4 Fields
Field Function
31-19 Physical Slot Number
Physical_Slot_N This field indicates the physical slot number attached to this Port. This field must be hardware initialized
umber to a value that assigns a slot number that is globally unique within the chassis. This field must be
initialized to 0 for Ports connected to devices that are either integrated on the system board or integrated
within the same silicon as the Switch device or Root Port.
18 No Command Completed Support
NOCMDCPLSU
P
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1636 NXP Semiconductors
Chapter 28 PCI Express Interface Controller
Field Function
17 Electromechanical Interlock Present
EMIP
16-15 Slot Power Limit Scale
SPLS
14-7 Slot Power Limit Value
SPLV
6 Hot-Plug Capable
HPD Note: This chip does not support hot-plug capabilities.
5 Hot-Plug Surprise
HPS Note: This chip does not support hot-plug capabilities.
4 Power Indicator Present
PIP Note: This chip does not support hot-plug capabilities.
3 Attention Indicator Present
AIP Note: This chip does not support hot-plug capabilities.
2 MRL Sensor Present
MRLSP Note: This chip does not support hot-plug capabilities.
1 Power Controller Present
PCP Note: This chip does not support hot-plug capabilities.
0 Attention Button Present
ABP Note: This chip does not support hot-plug capabilities.
28.4.2.44 PCI Express Slot Control Register (Slot_Control_Register)
28.4.2.44.1 Offset
Register Offset
Slot_Control_Register 88h
28.4.2.44.2 Function
This register is supported only for RC mode.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1637
Memory map/register overview
28.4.2.44.3 Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLLSTCHGEN
Reserved
EMICTL
MRLSC
PDCE
CCIE
PCC
PIC
AIC
PFD
ABP
HPI
W
E
E
Reset 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0
28.4.2.44.4 Fields
Field Function
15-13 Reserved
—
12 Data Link Layer State Changed Enable
DLLSTCHGEN Note: This chip does not support hot-plug capabilities.
11 Electromechanical Interlock Control
EMICTL Note: This chip does not support hot-plug capabilities.
10 Power Controller Control
PCC Note: This chip does not support hot-plug capabilities.
9-8 Power Indicator Control
PIC Note: This chip does not support hot-plug capabilities.
7-6 Attention Indicator Control
AIC Note: This chip does not support hot-plug capabilities.
5 Hot-Plug Interrupt Enable
HPIE Note: This chip does not support hot-plug capabilities.
4 Command Completed Interrupt Enable
CCIE Note: This chip does not support hot-plug capabilities.
3 Presence Detect Changed Enable
PDCE Note: This chip does not support hot-plug capabilities.
2 MRL Sensor Changed Enable
MRLSCE Note: This chip does not support hot-plug capabilities.
1 Power Fault Detected Enable
PFDE Note: This chip does not support hot-plug capabilities.
0 Attention Button Pressed Enable
ABPE Note: This chip does not support hot-plug capabilities.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1638 NXP Semiconductors
Chapter 28 PCI Express Interface Controller
28.4.2.45 PCI Express Slot Status Register (Slot_Status_Register)
28.4.2.45.1 Offset
Register Offset
Slot_Status_Register 8Ah
28.4.2.45.2 Function
This register is supported only for RC mode.
28.4.2.45.3 Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W1C DLLSTCHG
EM_IL_ST
MRLSC
MRLS
PDC
PFD
ABP
CC
R
PD
Reserved
W1C
W1C
W1C
W1C
W1C
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
28.4.2.45.4 Fields
Field Function
15-9 Reserved
—
8 Data Link Layer State Changed
DLLSTCHG
7 Electromechanical Interlock Status
EM_IL_ST
6 Presence Detect State
PDS This bit indicates the presence of an adapter in the slot, reflected by the logical OR of the Physical Layer
in-band presence detect mechanism and, if present, any out-of-band presence detect mechanism defined
for the slotâs corresponding form factor. Note that the in-band presence detect mechanism requires that
power be applied to an adapter for its presence to be detected. Consequently, form factors that require a
power controller for hot-plug must implement a physical pin presence detect mechanism.
This register must be implemented on all Downstream Ports that implement slots. For Downstream Ports
not connected to slots (where the Slot Implemented bit of the PCI Express Capabilities register is 0b), this
bit must return 1b.
Defined encodings are:
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1639
Memory map/register overview
Field Function
0b - Slot Empty
1b - Card Present in slot
5 MRL Sensor State
0b - MRL closed
MRLSS
1b - MRL open
4 Command Completed
CC
3 Presence Detect Changed
PDC
2 MRL Sensor Changed
MRLSC
1 Power Fault Detected
PFD
0 Attention Button Pressed
ABP
28.4.2.46 PCI Express Root Control Register (Root_Control_Register)
28.4.2.46.1 Offset
Register Offset
Root_Control_Register 8Ch
28.4.2.46.2 Function
This register is supported only for RC mode.
28.4.2.46.3 Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CRSSWV
Reserved
SENFE
SEFE
SECE
PMEI
W
E
E
E
E
E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1640 NXP Semiconductors
Chapter 28 PCI Express Interface Controller
28.4.2.46.4 Fields
Field Function
15-5 Reserved
—
4 CRS Software Visibility Enable
CRSSWVE
3 PME Interrupt Enable
PMEIE
2 System Error on Fatal Error Enable
SEFEE
1 System Error on Non-Fatal Error Enable
SENFEE
0 System Error on Correctable Error Enable
SECEE
28.4.2.47 PCI Express Root Capabilities Register (Root_Capabilities_
Register)
28.4.2.47.1 Offset
Register Offset
Root_Capabilities_Regist 8Eh
er
28.4.2.47.2 Function
This register is supported only for RC mode.
28.4.2.47.3 Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
CRSSW
W
V
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1641
Memory map/register overview
28.4.2.47.4 Fields
Field Function
15-1 Reserved
—
0 CRS Software Visibility
CRSSWV
28.4.2.48 PCI Express Root Status Register (Root_Status_Register)
28.4.2.48.1 Offset
Register Offset
Root_Status_Register 90h
28.4.2.48.2 Function
This register is supported only for RC mode.
28.4.2.48.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
W1C PME
R
Reserved
PMEP
S
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
PME_requester_ID
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
28.4.2.48.4 Fields
Field Function
31-18 Reserved
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1642 NXP Semiconductors
Chapter 28 PCI Express Interface Controller
Field Function
—
17 PME Pending
PMEP
16 PME Status
PMES
15-0 PME Requester ID
PME_requester
_ID
28.4.2.49 PCI Express Device Capabilities 2 Register (Device_Capab
ilities_2_Register)
28.4.2.49.1 Offset
Register Offset
Device_Capabilities_2_ 94h
Register
28.4.2.49.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPL_TO_RS
CPL_TO_DS
ARI_FWD
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1
28.4.2.49.3 Fields
Field Function
31-6 Reserved
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1643
Memory map/register overview
Field Function
—
5 ARI Forwarding Supported
ARI_FWD
4 Completion Timeout Disable Supported
CPL_TO_DS
3-0 Completion Timeout Ranges Supported
CPL_TO_RS
28.4.2.50 PCI Express Device Control 2 Register (Device_Control_2_
Register)
28.4.2.50.1 Offset
Register Offset
Device_Control_2_Reg 98h
ister
28.4.2.50.2 Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
IDO_REQ_EN
IDO_CPL_EN
CPL_TO_VAL
CPL_TOD
Reserved
Reserved
ARIF
W
E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
28.4.2.50.3 Fields
Field Function
15-10 Reserved
—
9 IDO Completion Enable
IDO_CPL_EN
8 IDO Request Enable
IDO_REQ_EN
Table continues on the next page...
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1644 NXP Semiconductors
Chapter 28 PCI Express Interface Controller
Field Function
7-6 Reserved
—
5 ARI Forwarding Enable
ARIFE Must be set when RC is communicating with ARI devices. When set will allow RC to issue configuration
type 0 cycles with device number != 0.
4 Completion Timeout Disable
CPL_TOD
3-0 Completion Timeout Value
CPL_TO_VAL
28.4.2.51 PCI Express Link Capabilities 2 Register (Link_Capabilitie
s_2_Register)
28.4.2.51.1 Offset
Register Offset
Link_Capabilities_2_Regi 9Ch
ster
28.4.2.51.2 Function
The PCI Express link capability 2 register is shown below.
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1645
Memory map/register overview
28.4.2.51.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Support_Link_Speed_Vector
Crosslink_Supported
Reserved
Reserved
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0
28.4.2.51.4 Fields
Field Function
31-9 Reserved
—
8 Crosslink Supported
Crosslink_Supp
orted
7-1 Supported Link Speeds Vector
Support_Link_S This field indicates the supported Link speed(s) of the associated Port. For each bit, a value of 1 indicates
peed_Vector that the corresponding Link speed is supported; otherwise, the Link speed is not supported. Bit definitions
are:
Bit 1 2.5 GT/s
Bit 2 5.0 GT/s
Bit 3 8.0 GT/s
Bits 7:4 Reserved
0 Reserved
—
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1646 NXP Semiconductors
Chapter 28 PCI Express Interface Controller
28.4.2.52 PCI Express Link Control 2 Register (Link_Control_2_Regis
ter)
28.4.2.52.1 Offset
Register Offset
Link_Control_2_Register A0h
28.4.2.52.2 Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HWASD
CDE
EMC
CSO
TxM
T_L
SD
C
E
W
S
S
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
28.4.2.52.3 Fields
Field Function
15-12 Compliance Preset/De-emphasis
CDE
11 Compliance SOS
CSOS
10 Enter Modified Compliance
EMC
9-7 Transmit Margin
TxM
6 Selectable De-emphasis
SDE
5 Hardware Autonomous Speed Disable
HWASD
4 Enter Compliance
EC
3-0 Target Link Speed
T_LS
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1647
Memory map/register overview
28.4.2.53 PCI Express Link Status 2 Register (Link_Status_2_Regist
er)
28.4.2.53.1 Offset
Register Offset
Link_Status_2_Register A2h
28.4.2.53.2 Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DE_LVL
Reserved
EP3
EP2
EP1
R
LE
C
E
R
S
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
28.4.2.53.3 Fields
Field Function
15-6 Reserved
—
5 Link Equalization Request
LER
4 Equalization Phase 3 Successful
EP3S
3 Equalization Phase 2 Successful
EP2S
2 Equalization Phase 1 Successful
EP1S
1 Equalization Complete
EC
0 Current De-emphasis Level
DE_LVL
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
1648 NXP Semiconductors
Chapter 28 PCI Express Interface Controller
28.4.2.54 PCI Express Advanced Error Reporting Capability ID
Register (Advanced_Error_Reporting_Capability_ID_Regis
ter)
28.4.2.54.1 Offset
Register Offset
Advanced_Error_Repor 100h
ting_Capability_ID_Regis
ter
28.4.2.54.2 Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Capability_ID
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
28.4.2.54.3 Fields
Field Function
15-0 PCI Express Extended Capability ID
Capability_ID 0x0001 = Advanced error reporting capability
28.4.2.55 PCI Express Uncorrectable Error Status Register (Uncorrec
table_Error_Status_Register)
28.4.2.55.1 Offset
Register Offset
Uncorrectable_Error_Stat 104h
us_Register
QorIQ LS1043A Reference Manual, Rev. 4, 6/2018
NXP Semiconductors 1649
Memory map/register overview
28.4.2.55.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
W1C MTLP
W1C ECRC
RXO
UC
R
UR
Reserved
You might also like
- The Linux Terminal for Advanced Users - The Command Line Made Easy: First EditionFrom EverandThe Linux Terminal for Advanced Users - The Command Line Made Easy: First EditionNo ratings yet
- Securing ChatGPT: Best Practices for Protecting Sensitive Data in AI Language ModelsFrom EverandSecuring ChatGPT: Best Practices for Protecting Sensitive Data in AI Language ModelsNo ratings yet
- Qoriq Ls1043A Design Checklist: 1 About This DocumentNo ratings yetQoriq Ls1043A Design Checklist: 1 About This Document69 pages
- The First Science Fiction Novel MEGAPACK®: 6 Great Science Fiction NovelsFrom EverandThe First Science Fiction Novel MEGAPACK®: 6 Great Science Fiction NovelsNo ratings yet
- The Sandy Steele Mystery MEGAPACK®: 6 Young Adult Novels (Complete Series)From EverandThe Sandy Steele Mystery MEGAPACK®: 6 Young Adult Novels (Complete Series)No ratings yet
- CAN Bus for Beginners: A Practical Guide to Automotive NetworkingFrom EverandCAN Bus for Beginners: A Practical Guide to Automotive NetworkingNo ratings yet
- Options Trading for Income: Learn the strategies and techniques for maximizing returns and minimizing risk in the options market (2023 Guide for Beginners)From EverandOptions Trading for Income: Learn the strategies and techniques for maximizing returns and minimizing risk in the options market (2023 Guide for Beginners)No ratings yet
- Qoriq Ls1028A Reference Design Board Reference Manual: Supports Ls1028Ardb Revision CNo ratings yetQoriq Ls1028A Reference Design Board Reference Manual: Supports Ls1028Ardb Revision C107 pages
- Fly Fishing Guide to the Battenkill: Complete Guide to Locations, Hatches, and HistoryFrom EverandFly Fishing Guide to the Battenkill: Complete Guide to Locations, Hatches, and HistoryNo ratings yet
- Cybersecurity for Executives: A Guide to Protecting Your BusinessFrom EverandCybersecurity for Executives: A Guide to Protecting Your BusinessNo ratings yet
- Advanced Multiplayer Game Development with Ureal Engine 5: A Comprehensive Guide to C++ ScriptingFrom EverandAdvanced Multiplayer Game Development with Ureal Engine 5: A Comprehensive Guide to C++ ScriptingNo ratings yet
- VPX3 1703 NXP Layerscape Quad Single Board Computer Product Sheet - 1No ratings yetVPX3 1703 NXP Layerscape Quad Single Board Computer Product Sheet - 110 pages
- The Off-Grid Blueprint: DIY Survival Projects for Modern Self-Reliance: DIY Survival Projects for Modern Self-Reliance: DIY Survival Projects for Modern Self-RelianceFrom EverandThe Off-Grid Blueprint: DIY Survival Projects for Modern Self-Reliance: DIY Survival Projects for Modern Self-Reliance: DIY Survival Projects for Modern Self-RelianceNo ratings yet
- Blog Smarter, Not Harder: SEO, Blogging, and AI Strategies to Skyrocket Your TrafficFrom EverandBlog Smarter, Not Harder: SEO, Blogging, and AI Strategies to Skyrocket Your TrafficNo ratings yet
- 'Ware the Dark-Haired Man: The Hieromonk's Tale, Book ThreeFrom Everand'Ware the Dark-Haired Man: The Hieromonk's Tale, Book ThreeNo ratings yet
- Technical Reference Manual: Am335X Arm Cortex™-A8 Microprocessors (Mpus)No ratings yetTechnical Reference Manual: Am335X Arm Cortex™-A8 Microprocessors (Mpus)4,110 pages
- ARM Cortex-R4 Technical Reference ManualNo ratings yetARM Cortex-R4 Technical Reference Manual570 pages
- MC9S12C Family Device User Guide V01.05: Original Release Date: 25 JAN 2003 Revised: 11 FEBRUARY 2004No ratings yetMC9S12C Family Device User Guide V01.05: Original Release Date: 25 JAN 2003 Revised: 11 FEBRUARY 2004136 pages
- 9691 Computing: MARK SCHEME For The October/November 2008 Question PaperNo ratings yet9691 Computing: MARK SCHEME For The October/November 2008 Question Paper6 pages
- Presantation - Chapter 07-Decrease and ConquerNo ratings yetPresantation - Chapter 07-Decrease and Conquer41 pages
- Week1 - Introduction To Enterprise SystemsNo ratings yetWeek1 - Introduction To Enterprise Systems56 pages
- Sharp Sharp Cash Register Xe A207 Users Manual 284068No ratings yetSharp Sharp Cash Register Xe A207 Users Manual 2840681 page
- Conformity Analysis of HTTP Strict Transport Security HSTS Configuration and Implementation Using Bettercap ToolsNo ratings yetConformity Analysis of HTTP Strict Transport Security HSTS Configuration and Implementation Using Bettercap Tools6 pages
- Autodesk Revit 2015 BIM Management Template and Family Creation PDF0% (1)Autodesk Revit 2015 BIM Management Template and Family Creation PDF82 pages
- VHDL Code: Top Level QDR SRAM ControllerNo ratings yetVHDL Code: Top Level QDR SRAM Controller14 pages
- A Bms Client and Gateway Using Bacnet Protocol: Abstract. A Building Management System (BMS) Is A Computer-Based ControlNo ratings yetA Bms Client and Gateway Using Bacnet Protocol: Abstract. A Building Management System (BMS) Is A Computer-Based Control2 pages
- Skylark Skylark Skylark Skylark AAT AAT AAT AAT Suite Suite Suite SuiteNo ratings yetSkylark Skylark Skylark Skylark AAT AAT AAT AAT Suite Suite Suite Suite12 pages
- Axis T8133 30 W Midspan: Widely Used For Poe-Based DevicesNo ratings yetAxis T8133 30 W Midspan: Widely Used For Poe-Based Devices2 pages
- Curriculam Vitae: Anand Kumar - Peela: 91-9030189253 ObjectiveNo ratings yetCurriculam Vitae: Anand Kumar - Peela: 91-9030189253 Objective3 pages
