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Timing Analyzer Clock Multiplexer Examples

The document provides examples of using Synopsys Design Constraint (SDC) commands to manage complex clock structures, specifically multiplexed clocks in FPGA designs. It illustrates three circuits with corresponding SDC commands to create and constrain multiple clocks while ensuring exclusivity between them. The examples highlight how to handle different clock periods and the necessity of indicating which clocks cannot be active simultaneously.

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amith nayak
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12 views

Timing Analyzer Clock Multiplexer Examples

The document provides examples of using Synopsys Design Constraint (SDC) commands to manage complex clock structures, specifically multiplexed clocks in FPGA designs. It illustrates three circuits with corresponding SDC commands to create and constrain multiple clocks while ensuring exclusivity between them. The examples highlight how to handle different clock periods and the necessity of indicating which clocks cannot be active simultaneously.

Uploaded by

amith nayak
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Timing Analyzer Clock Multiplexer Examples

The Timing Analyzer makes it easy to use Synopsys® Design Constraint (SDC) commands to constrain complex
clock structures, such as multiplexed clocks. The following shows three example circuits and the appropriate SDC
commands to constrain them.

Figure 1. Shows a simple register-to-register circuit clocked by the clk port.

Assume that the clk port is driven by an off-chip multiplexer that selects between two clocks, one with a 10 ns period
and one with an 8 ns period. The following SDC commands show how to assign multiple clocks to the clk port. It
also shows how to add an exception indicating that the two clocks will never be active at the same time in the FPGA.

# Create the two clocks on the port


create_clock -name clk_100 -period 10 [get_ports clk]
create_clock -name clk_125 -period 8 [get_ports clk] -add
# Set the two clocks as exclusive clocks
set_clock_groups -exclusive -group {clk_100} -group {clk_125}
Figure 2. Shows a simple register-to-register circuit with a clock multiplexer on the FPGA, with two clock ports: clkA
and clkB.

Assume that the clkA port is driven by a clock with a 10 ns period, and that the clkB port is driven by a clock with an
8 ns period. The following SDC commands show how to assign the clocks. This example is similar to the previous
example, but the clocks are assigned to separate ports.

# Create a clock on each port


create_clock -name clk_100 -period 10 [get_ports clkA]
create_clock -name clk_125 -period 8 [get_ports clkB] -add
# Set the two clocks as exclusive clocks
set_clock_groups -exclusive -group {clk_100} -group {clk_125}

Figure 3. Shows a more complex clocking circuit with linked clock multiplexers on the FPGA.
In this case, you must use the set_clock_groups command to indicate that clocks A and D, A and B, C and D, and
B and C, can never be active at the same time.

create_clock -name A -period 10 [get_ports clkA]


create_clock -name B -period 8 [get_ports clkB]
create_clock -name C -period 8 [get_ports clkC]
create_clock -name D -period 10 [get_ports clkD]
# cut paths between clocks
set_clock_groups -exclusive -group {A C} -group {B D}

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