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Mod 1

The document outlines the VLSI Circuit Design course, focusing on various design methodologies including ASIC and FPGA designs, and the evolution of microelectronics. It discusses the advantages of integration, types of ASICs, and the significance of System on Chip (SoC) technology. Additionally, it covers design flows, speed, power, and area considerations essential for VLSI design.

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6 views57 pages

Mod 1

The document outlines the VLSI Circuit Design course, focusing on various design methodologies including ASIC and FPGA designs, and the evolution of microelectronics. It discusses the advantages of integration, types of ASICs, and the significance of System on Chip (SoC) technology. Additionally, it covers design flows, speed, power, and area considerations essential for VLSI design.

Uploaded by

gamy74632
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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ECT 304 VLSI CIRCUIT DESIGN

MODULE-1

PREPARED BY MINNU JAYAN C


ASST PROFESSOR,DEPT OF ECE,
MARIAN ENGINEERING COLLEGE
VLSI Design Methodologies.
 Introduction: Moore’s law
 ASIC design, Full custom ASICs, Standard cell based ASICs, Gate Array based ASICs
 SoCs
 FPGA devices
 ASIC and FPGA Design flows
 Top-Down and Bottom-Up design methodologies
 Logical and Physical design
 Speed power and area considerations in VLSI

SYLLABUS
Information services
 High processing power
 Bandwidth
 Making more personalized
 More intelligent
 Portability
Complex functions to be integrated in a small package

INTRODUCTION
Advantages of Integration
 Less area/Volume makes compact
 Less power consumption
 Less testing requirements at system level
 Higher reliability due to improved on chip interconnects
 Higher speed due to reduced interconnection length
 Significant cost savings

INTRODUCTION
EVOLUTION
 Speed and capability of computers increase every
MOORE’S LAW couple of years and we pay less.
APPLICATION SPECIFIC INTEGRATED CIRCUITS
 For specific use
 For large production run
 Large part of electronics needed on a single IC
 Eg:chip for a toy bear,chip for a satellite
 ASSP-Application Specific StandardProducts in which controller
chip for a PC and chip for a MODEM.Though appln specific they
are sold to many vendors.

ASIC DESIGN
TYPES OF ASIC
 ICs are made on a thin, circular silicon wafer with each wafer
holding hundreds of die.
 Transistors and wiring are made from many layers built on top of
one another.
 Each successive mask layer defined using a mask similar to glass
photographic slide
 1st Half dozen defines transistors and last half dozen define
interconnect

TERMS USED
 Some/all Logic cells that are customized and all mask layers that are
customized.
Eg: microprocessor
 Customizing all of the IC features in this way allows designers to include analog
circuits, optimized memory cells, or mechanical structures on an IC.
 Full-custom ICs are the most expensive to manufacture and to design.
 Manufacturing lead time (the time required just to make an IC not including
design time) is typically eight weeks.
 Engineer designs some or all of the logic cells, circuits, or layout specifically for
one ASIC thus designer avoids using pretested and pre characterized cells for all
or part of that design.
 Used when no suitable existing cell libraries are available that can be used for
the entire design.
 Or existing cell libraries are not fast enough, or the logic cells are not small
enough or consume too much power.
 growing member of this family, is the Mixed Analog/digital ASIC

FULL CUSTOM ASIC


 all logic cells are predesigned and some/all mask layers are customized
 predesigned cells from a cell library makes the design , much easier
Two types of semicustom ASICs
(i) Standard-cell–based ASICs (ii)Gate-array–based ASICs.

SEMICUSTOM ASIC
 Cell Based IC (CBIC)uses predesigned logic cells known as Standard cells
 The Standard-cell areas (also called flexible blocks) in a CBIC are built of rows of standard
cells
 used in combination with microcontrollers or even microprocessors, known as Mega cells
 Also called Mega functions, full-custom blocks, system-level macros (SLMs), fixed blocks,
cores, or Functional Standard Blocks (FSBs).
 ASIC designer defines only the placement of the standard cells and the interconnect in a
CBIC
 Standard cells can be placed anywhere on the silicon; this means that all the mask layers
of a CBIC are customized

(A)STANDARD-CELL BASED ASICS


 Advantage: Designers save time, money,and reduce risk by using a predesigned,
pretested, and pre characterized standard-cell library
 Each standard cell can be optimized individually. During the design of the cell
library each and every transistor in every standard cell can be chosen to
maximize speed or minimize area.
 Disadvantage: Time or expense of designing or buying the standard-cell library
and the time needed to fabricate all layers of the ASIC for each new design.

ADVANTAGES & DISADVANTAGE OF CBIC


 The transistors are predefined on the silicon wafer
 Predefined pattern of transistors on a gate array is the base array
 The smallest element that is replicated to make the base array is the base cell(primitive cell)
 Top few layers of metal, which define the interconnect between transistors, are defined by
the designer using custom masks.
 To distinguish this type of gate array from other types of gate array, it is often called a
Masked Gate Array ( MGA ).
 The designer chooses from a gate-array library of predesigned and pre-characterized logic
cells
 The logic cells in a gate-array library are often called macros.
 Only the interconnect (inside cells and between cells) is customized

(B)GATE-ARRAY BASED ASICS (GA)


 Channeled gate arrays.
 Channelless gate arrays.
 Structured gate arrays.

TYPES OF MGA OR GATE-ARRAY BASED ASICS


 Space is left between the rows of transistors for wiring
 similar to a CBIC. Both use the rows of cells separated by channels used for
interconnect.
 One difference is that the space for interconnect between rows of cells are
fixed in height in a channeled gate array, whereas the space between rows of
cells may be adjusted in a CBIC.

CHANNELED GATE ARRAYS


 more widely used
 Routing uses rows of unused transistors.
 Difference -there are no predefined areas set aside for routing
between cells on a channel less gate array
 Instead we route over the top of the gate-array devices.
 we customize the contact layer that defines the connections
between metal 1, the first layer of metal, and the transistors.

CHANNELLESS GATE ARRAY


STRUCTURED GATE ARRAY
IMPACT OF DIFFERENT VLSI DESIGN STYLES
 An System on Chip (SoC) is an integrated circuit that implements most or all of the
function of a complete electronic system.
 Four vital areas of SoC Advantages of SoC
Low power.
 Higher levels of abstraction(entire system) Low cost.
 IP and platform re-use High reliability.
Small form factor
 IP creation High integration levels.
Fast operation.
 Earlier software development and integration Greater design.
Embedded system applications make use of SoC Small size.
Disadvantages of SoC
Fabrication cost.
Increased complexity.
SOC(SYSTEM ON CHIP) Time to market demands.
More verification.
 Intellectual Property Cores are fundamental building blocks of SoC
 Reusable layout of IC design that is provided by companies like ARM
 IP Cores can be Soft cores or Hard cores.
 Soft cores are generally RTL schematics written in some hardware description
language. They are called so because they can be subjected to small changes
suiting the design.
 Hard cores are mostly analog components and certain digital cores whose
function cannot be changed by designers.
 Most common methods for fabricating SoCs are as a standard cell, full custom
designing or using FPGAs
 Most of the SoCs available in the market today are ARM based. Some examples
among SoCs in smartphone industry are Qualcomm's Snapdragon SoCs, Apple
A4, and Nvidia Tegra series.

FEATURES
EVOLUTION OF MICROELECTRONICS:
THE SOC PARADIGM
PROGRAMMABLE ASIC
PROGRAMMING TECHNOLOGIES
PROGRAMMABLE LOGIC DEVICES
FEATURES CONTD…..
1-4 logical design,5-9 physical design(overlap also)
DIFFERENCE BETWEEN ASIC AND FPGA
FPGA DESIGN FLOW(ASSIGNMENT)
This is a Top Down Design
methodology where parts
with known behaviour are
decomposed into smaller
blocks with simpler
behaviour and an
interconnection
structure.This continues until
a sufficiently low level of
abstraction is reached.If it is
specified in a Bottom Up
fashion:transistors grouped
to form cells,cells to
modules,etc

VLSI DESIGN FLOW


 For designing,1st requirement is to realize a given specification
 Optimization of different entities are also necessary
 Area
 Speed
 Power Dissipation
 Design Time
 Testability

SPEED,POWER AND AREA CONSIDERATIONS IN VLSI


THANK YOU

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