Sixteen Week Plan

Department of Computer Science

Faculty of Computing & Information Technology
Hafiz Hayat Campus, University of Gujrat

Title Digital Logic Design

Code CS-152
Credit hours 3.0
Prerequisite None
Category Computing Core
Course Description --
A one semester course that provides Computer Science and Information Technology students with material fundamen-
tal to the design and analysis of digital circuits. This course introduces the logic operators and gates to lay the frame-
work for strengthening the understanding of computer building blocks. Combinational and sequential circuits are stud-
Aims & Objectives ied along with their constituent elements comprising adders, encoders and multiplexers as well as flip-flops, latches and
registers etc. The course provides necessary information to the students for future study of computer Architecture, Or-
ganization, Embedded Systems, Industrial Robots and Control.
 How to analyze digital logic circuits
 Analysis of Combinational Circuits.
 Hands on Practice of Combinational Circuits
 Analysis of Sequential Circuits
Learning Outcomes
 Design of Sequential Circuits.
 How to design digital logic circuits
 Use modern CAD tools and languages

 Logic and Computer Design Fundamentals Fourth Edition M.Morris Mano, Charles R Kime
Text Book
 Introduction to Logic and Computer Design By Marcovitz Alan B McGraw Hill.
 R. H. Katz, Contemporary Logic Design, Prentice-Hall.
 Hayes, Introduction to Digital Logic Design, Addison-Wesley.
Reference Books
 M. Mano, Digital Design, 2nd Ed., Prentice-Hall.
&
 C. H. Roth, Jr., Fundamentals of Logic Design, 3rd Ed.
Material
 Digital Fundamentals (Eighth Edition), by Floyd.
 Digital Systems: Principles and Applications (Seventh Edition) by Tocci. Widmer
Grading Breakup and Policy Assignment/Presentation (s): 10%
Quizzes: 5%
 Project: 10%
Midterm Examination: 25%
Final Examination: 50%

Recommendations
for Learning
Activities
Week Source
Lecture # TOPICS (Mention Assignments,
(Book, Chapter No)
Test, Case Study,
Projects, Lab Work or
Reading Assignments)

Chapter 1: Sections 1-2 Distribution

through 1-7 of course
1 Introduction, Digital Systems and Information,
outline
1
Chapter 1: Sections 1-2
2 Digital World ,Analog Vs Digital
through 1-7
Number Systems; Base 2 , Chapter 1: Sections 1-2
3
Base 8, Base 16 through 1-7
2 Binary Conversion Between Different Bases,
Two’s Complement Chapter 1: Sections 1-2
4
Binary Arithmatic through 1-7
Codes
Combinational Logic Circuits, Chapter 2: Sections 2-1 Assignment #
5 Gates through 2-5 1
AND, OR, XOR etc. Quiz 1
3
Chapter 2: Sections 2-1
Combinational Logic Circuits
6 through 2-5
Boolean Algebra, Duality Principle

4 Combinational Logic Chapter 2: Sections 2-1

Standard Forms. through 2-5
7
SOP and POS Forms
MINTERM MAX TERM
8 Canonical SOP Chapter 2: Sections 2-1
 Canonical POS through 2-7
Multiple Level Circuit Optimization
K-MAP Chapter 2: Sections 2-1
9
K-MAP Manipulation through 2-7
5
Chapter 2: Sections 2-1
10 Three Four Variable MAP
through 2-7
Chapter 2: Sections 2-1
11 NAND NOR Gate Implementation
through 2-7
6
Chapter 2: Sections 2-1
12 XOR Gate Implementation, Odd Function
through 2-7
Chapter 3: Sections 3-7
Combinational Logic Design Using Building Blocks:
13 through 3-9
Multiplexers, Demultiplexers
7
Chapter 3: Sections 3-7
Combinational Logic Design Using Building Blocks:
14 through 3-9
Decoders, Encoders

Chapter 4: Sections 4-1

15 Arithmetic Functions(Continued): Adders-Subtractors through Section 4-5) Quiz 2
8
Chapter 4: Sections 4-1
Assignment
16 Arithmetic Functions: Adders-Subtractors through Section 4-5)
#2

Mid Term Exam

Chapter 4: Sections 4-1
17 Arithmetic Functions (continued): Binary Multiplication, Contraction through Section 4-5)
9
Chapter 4: Sections 4-1
18 Arithmetic Functions (continued): Incrementing through Section 4-5)

Chapter 4: Sections 4-1

19 Arithmetic Functions (continued): Decrementing through Section 4-5)
10
Chapter 5: Sections 5-1,
20 Sequential Circuits: Basic Latches 5-2, 5-3, 5-6
 Chapter 5: Sections 5-1,
21 S-R Latch 5-2, 5-3, 5-6
11
22 Master –Slave Flip-Flops.
Chapter 5: Sections 5-1,
23 Edge Triggered Flip-Flops 5-2, 5-3, 5-6
12
Chapter 5: Sections 5-1,
Sequential Circuits: Flip-Flops.
24 5-2, 5-3, 5-6
D FFs,

Chapter 5: Sections 5-1,

25 Sequential Circuits: JK and T Flip Flops 5-2, 5-3, 5-6
13
Chapter 5: Section 5-4
26 Finite State Machines: Analysis Quiz3

Chapter 5: Section 5-4

27 Finite State Machines: State Table Assignment 3
14 Chapter 5: Section 5-5,
28 Finite State Machines: Design, State Diagram 5-7;

Chapter 5: Section 5-5,

29 Finite State Machines: Applications , Diagram Model 5-7;
15
Section 6-8
30 Building Blocks (continued); Programmable Implementation of Functions: PLA, PAL, ROM

31 Review
16
32 Future of DLD
Final Exam