SYSTEM SOFTWARE

CS2304
UNIT I INTRODUCTION

UNIT II ASSEMBLERS

UNIT III LOADERS AND LINKERS

UNIT IV MACRO PROCESSORS

UNIT V SYSTEM SOFTWARE TOOLS

INTRODUCTION

⚫ System software and machine

architecture
⚫ The Simplified Instructional Computer
(SIC)
⚫ Machine architecture
⚫ Data and instruction formats
⚫ Addressing modes
⚫ Instruction sets
⚫ I/O and programming
SYSTEM SOFTWARE

● The subject introduces the design and

implementation of system software
⚫ System software consists of a variety of
programs that support the operation of a
computer
● Operating system, compiler, assembler,
macro processor, loader or linker,
debugger, text editor, database
management systems, software
engineering tools, ….
SOFTWARE ITS CLASSIFICATION
⚫ Software is set of instructions or programs
written to carry out certain task on digital
computers
⚫ Classified into system software and
application software
⚫ System software consists of a variety of
programs that support the operation of a
computer
⚫ Application software focus on an
application or problem to be solved
THIS CHAPTER GIVES YOU…

⚫ System Software & Machine Architecture

⚫ The Simplified Instructional Computer
SIC and SIC/XE
⚫ Traditional (CISC) Machines
⚫ Complex Instruction Set Computers
⚫ RISC Machines
⚫ Reduced Instruction Set Computers
 SYSTEM SOFTWARE & MACHINE
ARCHITECTURE

⚫ Machine Dependent
⚫ Machine Independent
MACHINE INDEPENDENT

◦There are aspects of system software

that do not directly depend upon the type
of computing system
◦general design and logic of an assembler
◦general design and logic of a compiler
◦code optimization techniques
MACHINE DEPENDENT

◦System software – support operation and

use of computer
◦Application software - solution to a
problem
◦Assembler translate mnemonic
instructions into machine code
◦Compilers must generate machine
language code
THE SIMPLIFIED INSTRUCTIONAL
COMPUTER (SIC)
⚫ SIC is a hypothetical computer that
includes the hardware features most often
found on real machines
⚫ Two versions of SIC
◦standard model (SIC)
◦extension version (SIC/XE)
●(extra equipment or extra expensive)
SIC MACHINE ARCHITECTURE

⚫ Memory and Registers

⚫ Data Formats
⚫ Instruction Formats
⚫ Addressing Modes
⚫ Instruction Set
⚫ Input and Output
MEMORY

◦215 bytes in the computer memory

◦32,768 bytes
◦Uses Little Endian
◦3 consecutive bytes form a word
◦8-bit bytes
Registers - Five registers each 24 bits in
length
DATA FORMATS

◦Integers are stored as 24-bit binary

numbers
◦2’s complement representation is used
for negative values
◦No floating-point hardware
INSTRUCTION FORMATS

opcode x address
(8) (15)
INSTRUCTION SET

◦load and store:

◦LDA, LDX, STA, STX, etc.
◦integer arithmetic operations:
◦ADD, SUB, MUL, DIV, etc.
●All arithmetic operations involve register
A and a word in memory, with the result
being left in the register
INSTRUCTION SET

◦comparison:
●COMP - compares the value in
register A with a word in memory,
this instruction sets a condition code
CC to indicate the result
INSTRUCTION SET

◦Conditional jump instructions:

◦JLT, JEQ, JGT
●These instructions test the setting of
CC and jump accordingly
INSTRUCTION SET

◦subroutine linkage: JSUB, RSUB

●JSUB jumps to the subroutine, placing
the return address in register L
●RSUB returns by jumping to the
address contained in register L
INPUT AND OUTPUT

◦Input and Output are performed by

transferring 1 byte at a time to or from
the rightmost 8 bits of register A
(accumulator)
◦The Test Device (TD) instruction tests
whether the addressed device is ready to
send or receive a byte of data
◦Read Data (RD), Write Data (WD)
DATA MOVEMENT

⚫ 3-byte word:
◦LDA, STA, LDL, STL, LDX, STX
◦ A- Accumulator, L – Linkage
Register, X – Index Register
⚫ 1-byte: LDCH, STCH
⚫ No memory-memory move instruction
STORAGE DEFINITION

◦WORD - ONE-WORD CONSTANT

◦RESW - ONE-WORD VARIABLE
◦BYTE - ONE-BYTE CONSTANT
◦RESB - ONE-BYTE VARIABLE
 EXAMPLE PROGRAMS (SIC)

Example 1
LDA FIVE
STA ALPHA
LDCH CHARZ
STCHC1
.
ALPHA RESW 1
FIVE WORD 5
CHARZ BYTE C’Z’
C1 RESB 1
 EXAMPLE PROGRAMS (SIC)
Example 2
LDA ALPHA
All arithmetic operations
ADD INCR are performed using register
SUB ONE A, with the result being left
in register A.
STA BEETA

ONE WORD 1
ALPHA RESW 1
BEETA RESW 1
INCR RESW 1
 SIC/XE MACHINE ARCHITECTURE

•Memory
Maximum memory available on a SIC/XE
system is 1 Megabyte (220 bytes)

•Registers
Additional B, S, T, and F registers are
provided by SIC/XE
REGISTERS

Mnemonic Number Special use

B 3 Base register
S 4 General working register
T 5 General working register
F 6 Floating-point accumulator (48
bits)
FLOATING-POINT DATA TYPE

• There is a 48-bit floating-point data type

1 11 36
s exponent fraction

F*2(e-1024
)
 INSTRUCTION FORMATS

Format 1 (1 byte) 8
op

8 4 4
Format 2 (2 bytes)
op r1 r2
Formats 1 and 2 are instructions do not reference
memory at all
 CONTINUED…
Format 3 (3 bytes)
6 1 11111 12
op n i xbpe disp
Format 4 (4 bytes)
6 1 11111 20
op n i xbpe address
 ADDRESSING MODES & FLAG BITS

•e - e = 0 means format 3, e = 1
means format 4

•Bits x,b,p: Used to calculate the target address

using relative, direct, and indexed addressing
Modes

•Bits i and n: Says, how to use the target address

 ADDRESSING MODES

Format 3
Mode Indicatio Target address calculation
n
TA=(B)+ disp
Base relative b=1,p=0
(0≤disp ≤4095)
TA=(PC)+ disp
Program-counte
b=0,p=1 (-2048≤disp ≤2047)
r relative
 FLAG BITS CONTINUED…

•b and p - both set to 0, disp field from format

3 instruction is taken to be the target address.
For a format 4 bits b and p are normally set to
0, 20 bit address is the target address
•x - x is set to 1, X register value is added
for target address calculation
 FLAG BITS CONTINUED…

Format 3 or 4

•i=1, n=0 Immediate addressing, TA: TA is

used as the operand value, no memory
reference
•i=0, n=1 Indirect addressing, ((TA)): The word
at the TA is fetched. Value of TA is taken as
the address of the operand value
•i=0, n=0 or i=1, n=1 Simple addressing,
(TA):TA is taken as the address of the operand
value
 INSTRUCTION SET

•Instructions to load and store the new

registers LDB, STB, etc.
•Floating-point arithmetic operations
ADDF, SUBF, MULF, DIVF
•Register move instruction : RMO
•Register-to-register arithmetic operations
ADDR, SUBR, MULR, DIVR
•Supervisor call instruction : SVC
 INPUT AND OUTPUT

•There are I/O channels that can be used to

perform input and output while the CPU is
executing other instructions
•Allows overlap of computing and I/O, resulting
in more efficient system operation
• The instructions SIO, TIO, and HIO are used
 EXAMPLE PROGRAMS (SIC/XE)

Example 1 LDA #5
STA ALPHA
LDA #90
STCHC1
.
.
ALPHA RESW 1
C1 RESB 1
 EXAMPLE PROGRAMS (SIC/XE)

Example 2 LDS INCR

LDA ALPHA
All arithmetic operations are ADD S,A
performed using register A,
with the result being left in
SUB #1
register A. STA BEETA
……..
…………..
ALPHA RESW 1
BEETA RESW 1
INCR RESW 1
 DIFFERENT ARCHITECTURES

•Traditional (CISC) machines

- VAX Architecture
- Pentium Pro Architecture
•RISC machines
- UltraSPARC Architecture
- Cray T3E Architecture
 COMPARISON OF THESE
•Memory
•Registers
•Data Formats
•Instruction Formats
•Addressing Modes
•Instruction Set
•Input and Output
 TRADITIONAL (CISC) MACHINES

•Complex Instruction Set Computers

•Has relatively large and complex instruction
set
•Different instruction formats, different lengths,
different addressing modes
•Implementation of hardware is complex
• VAX and Intel x86 processors are examples
 VAX ARCHITECTURE

Memory - The VAX memory consists of 8-bit

bytes. All addresses used are byte addresses.
•Two consecutive bytes form a word, Four bytes
form a longword, eight bytes form a quadword,
sixteen bytes form a octaword.
•All VAX programs operate in a virtual address
space of 232 bytes , One half is called system
space, other half process space
 REGISTERS

•16 GPRs, 32 bits each, R0 to R15, PC (R15),

SP (R14), Frame Pointer FP ( R13),
Argument Pointer AP (R12) ,Others available
for general use
•Process status longword (PSL) – for flags
 DATA FORMATS

•Integers are stored as binary numbers in byte,

word, longword, quadword, octaword
•2’s complement for negative numbers
•Characters 8-bit ASCII codes
•Four different floating-point data formats
 INSTRUCTION FORMATS

•Uses variable-length instruction formats – op

code 1 or 2 bytes, maximum of 6 operand
specifiers depending on type of instruction
•Tabak – Advanced Microprocessors (2nd
edition) McGraw-Hill, 1995
 ADDRESSING MODES

•VAX provides a large number of addressing

modes
•Register mode, register deferred mode,
autoincrement, autodecrement, base relative,
program-counter relative, indexed, indirect,
immediate
 INSTRUCTION SET

• Symmetric with respect to data type - Uses

prefix – type of operation, suffix – type of
operands, a modifier – number of operands
• ADDW2 - add, word length, 2 operands,
MULL3 - multiply, longwords, 3 operands
CVTCL - conversion from word to longword
•VAX provides instructions to load and store
multiple registers
 INPUT AND OUTPUT

• Uses I/O device controllers

• Device control registers are mapped to separate
I/O space
•Software routines and memory management
routines are used
 PENTIUM PRO ARCHITECTURE

•Introduced by Intel in 1995

•Memory - consists of 8-bit bytes, all
addresses used are byte addresses. Two
consecutive bytes form a word, four bytes
form a double word (dword)
• Viewed as collection of segments -
address = segment number + offset
• code, data, stack , extra segments
 REGISTERS
•32-bit, eight GPRs, EAX, EBX, ECX, EDX,
ESI, EDI, EBP, ESP
•EAX, EBX, ECX, EDX – are used for data
manipulation, other four are used to hold
addresses
•EIP – 32-bit contains pointer to next
instruction to be executed
•FLAGS – 32 - bit flag register
• CS, SS, DS, ES, FS, GS – Six 16-bit
segment registers
 DATA FORMATS

•Integers – 8, 16, or 32 bit binary numbers

•2’s complement for negative numbers
•BCD is also used – unpacked BCD, packed
BCD
• There are three floating point data formats –
single, double, and extended-precision
• Characters – one per byte – ASCII codes
 INSTRUCTION FORMATS
•Uses prefixes – to specify repetition count,
segment register
•Following prefix (if present), an opcode ( 1 or 2
bytes), then number of bytes to specify
operands, addressing modes
•Instruction formats varies in length from 1 byte
to 10 bytes or more
•Opcode is always present in every instruction
 ADDRESSING MODES

•A large number of addressing modes are

available
•Immediate mode, register mode, direct
mode, relative mode
•Use of base register, index register with
displacement is also possible
 INSTRUCTION SET

•Has a large and complex instruction set,

approximately 400 different machine
instructions
•Each instruction may have one, two or three
operands
•Register-to-register, register-to-memory,
memory-to-memory, string manipulation, etc…
 INPUT AND OUTPUT

•Input is from an I/O port into register EAX

•Output is from EAX to an I/O port
 RISC MACHINES

•Reduced Instruction Set Computers

•Intended to simplify the design of processors.
Greater reliability, faster execution and less
expensive processors
•Standard and fixed instruction length
•Number of machine instructions, instruction
formats, and addressing modes relatively small
 ULTRASPARC ARCHITECTURE

•Introduced by Sun Microsystems

•SPARC – Scalable Processor ARChitecture,
•SPARC, SuperSPARC, UltraSPARC - upward
compatible and share the same basic structure
 MEMORY

•Consists of 8-bit bytes, all addresses used

are byte addresses. Two consecutive bytes
form a halfword, four bytes form a word ,
eight bytes form a double word

•Uses virtual address space of 264 bytes,

divided into pages
 REGISTERS

•More than 100 GPRs, with 64 bits length

each ( Register file)
•64 double precision floating-point registers,
in a special floating-point unit (FPU)
•PC, condition code registers, and control
registers
 DATA FORMATS

•Integers – 8, 16, 32 or 64 bit binary numbers

•Signed, unsigned for integers and 2’s
complement for negative numbers
•Supports both big-endian and little-endian byte
orderings
•Floating-point data formats – single, double and
quad-precision
•Characters – 8-bit ASCII value
 INSTRUCTION FORMATS

•32-bits long, three basic instruction formats

•First two bits identify the format
•Format 1 used for call instruction
•Format 2 used for branch instructions
•Format 3 used for load, store and for arithmetic
operations
 ADDRESSING MODES

•Immediate mode,
•register-direct mode,
•PC-relative,
•Register indirect with displacement,
•Register indirect indexed
 INSTRUCTION SET

•Has fewer than 100 machine instructions

•The only instructions that access memory
are loads and stores. All other instructions
are register-to-register operations
•Instruction execution is pipelined – results
in faster execution, speed increases
 INPUT AND OUTPUT

•Communication through I/O devices is

accomplished through memory
•A range of memory locations is logically
replaced by device registers
•When a load or store instruction refers to this
device register area of memory, the
corresponding device is activated
•There are no special I/O instructions
 CRAY T3E ARCHITECTURE
•Announced by Cray Research Inc., at the end
of 1995
•Is a massively parallel processing (MPP)
system, contains a large number of processing
elements (PE), arranged in a
three-dimensional network
•Each PE consists of a DEC Alpha EV5 RISC
processor, and local memory
 MEMORY

•Each PE in T3E has its own local memory

with a capacity of from 64 megabytes to 2
gigabytes

•Consists of 8-bit bytes, all addresses used

are byte addresses. Two consecutive bytes
form a word, four bytes form a longword ,
eight bytes form a quadword
 REGISTERS

•32 GPRs, with 64 bits length each called R0

through R31, contains value zero always
•32 floating-point registers, 64 bits long
•64-bit PC, stauts , and control registers
 DATA FORMATS

•Integers –long and quad word binary numbers

•2’s complement for negative numbers
•Supports little-endian byte orderings
•Two different floating-point data formats –
VAX and IEEE standard
•Characters – 8-bit ASCII value
 INSTRUCTION FORMATS

•32-bits long, five basic instruction formats

•First six bits always identify the opcode
 ADDRESSING MODES

•Immediate mode,
•register-direct mode,
•PC-relative,
•Register indirect with displacement,
 INSTRUCTION SET

•Has approximately 130 machine instructions

•There are no byte or word load and store
instructions
•Smith and Weiss – “PowerPC 601 and
Alpha 21064: A Tale of TWO RISCs “ –
Gives more information
 INPUT AND OUTPUT

•Communication through I/O devices is

accomplished through multiple ports and I/O
channels
•Channels are integrated into the network that
interconnects the processing elements
•All channels are accessible and controllable
from all PEs
 EXAMPLE PROGRAMS (SIC)

LDX ZERO : X=0

MOVECH LDCH STR1, X : LOAD A FROM STR1
STCH STR2, X : STORE A TO STR2
TIX ELEVEN : ADD 1 TO X, TEST
JLT MOVECH
.
.
.
STR1 BYTE C ‘HELLO WORLD’
STR2 RESB 11
ZERO WORD 0
ELEVEN WORD 11
 EXAMPLE PROGRAMS (SIC/XE)

LDT #11
LDX #0 : X=0
MOVECH LDCH STR1, X : LOAD A FROM STR1
STCH STR2, X : STORE A TO STR2
TIXR T : ADD 1 TO X, TEST (T)
JLT MOVECH
.
Looping .
and .
Indexing STR1 BYTE C ‘HELLO WORLD’
operation STR2 RESB 11
 EXAMPLE PROGRAMS (SIC)

INLOOP TD INDEV : TEST INPUT DEVICE

JEQ INLOOP : LOOP UNTIL DEVICE IS READY
RD INDEV : READ ONE BYTE INTO A
STCH DATA : STORE A TO DATA
.
.
OUTLP TD OUTDEV : TEST OUTPUT DEVICE
JEQ OUTLP : LOOP UNTIL DEVICE IS READY
LDCH DATA : LOAD DATA INTO A
WD OUTDEV : WRITE A TO OUTPUT DEVICE
.
.
INDEV BYTE X ‘F5’ : INPUT DEVICE NUMBER
OUTDEV BYTE X ‘08’ : OUTPUT DEVICE NUMBER
DATA RESB 1 : ONE-BYTE VARIABLE
 EXAMPLE PROGRAMS (SIC)
LDX ZERO
CLOOP TD INDEV
JEQ CLOOP
To transfer two
hundred bytes of
RD INDEV
data from input STCH RECORD, X
device to memory
TIX B200
JLT CLOOP
.
.
INDEV BYTE X ‘F5’
RECORD RESB 200
ZERO WORD 0
B200 WORD 200
 EXAMPLE PROGRAMS (SIC/XE)

LDT #200
LDX #0
CLOOP TD INDEV
JEQ CLOOP
To transfer two RD INDEV
hundred bytes of
data from input STCH RECORD, X
device to memory
TIXR T
JLT CLOOP
.
.
INDEV BYTE X ‘F5’
RECORD RESB 200
 EXAMPLE PROGRAMS (SIC)
JSUB READ
.
READ LDX ZERO
CLOOP TD INDEV
Subroutine to
JEQ CLOOP
transfer two RD INDEV
hundred bytes of STCH RECORD, X
data from input TIX B200 : add 1 to index compare 200 (B200)
device to memory
JLT CLOOP
RSUB
.
INDEV BYTE X ‘F5’
RECORD RESB 200
ZERO WORD 0
B200 WORD 200
 EXAMPLE PROGRAMS (SIC/XE)
JSUB READ
.
.
READ LDT #200
LDX #0
CLOOP TD INDEV
JEQ CLOOP
RD INDEV
Subroutine to STCH RECORD, X
transfer two
hundred bytes of TIXR T : add 1 to index compare T
data from input JLT CLOOP
device to memory RSUB
.
.
INDEV BYTE X ‘F5’
RECORD RESB 200