V.

PRAKASH
Asst. Professor(Sr.), SENSE,
VIT Chennai

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 Microprocessor Architecture and Interfacing: Intel x86

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 3

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 FEATURES
 It is a 16-bit μp. It’s ALU, internal registers works with 16-bit binary word.
 A 40 pin dual in line package and it requires +5V power supply.
 8086 has a 20-bit address bus can access up to 220= 1 MB memory locations.
 8086 has a 16-bit data bus and can read/write data either 16-bits or 8-bit at a time.
 Frequency range of 8086 is 6-10 MHz
 It can support up to 64K I/O ports.
 It provides 14, 16 -bit registers.
 It has multiplexed address and data bus AD0- AD15 and A16 – A19.
 It can pre-fetch upto 6 instruction bytes from memory to speed up instruction execution.
 8086 is designed to operate in two modes, Minimum mode and Maximum mode
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 Fetch

Decode
Execute

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 BUS INTERFACE UNIT (BIU)
 BIU provides the interface of 8086 to external memory and I/O devices.

 BIU performs the following functions:

 It generates the 20 bit physical address for memory access.
 It fetches instruction from memory.
 It transfers data to and from the memory and I/O.
 It supports pipelining using the 6 byte instruction queue.

 The main components of the BIU are:

 Segment registers
 Instruction Pointer (IP)
 Address Generation Circuit
 6 Byte Pre-fetch Queue

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 BUS INTERFACE UNIT (BIU)
 Segment registers: It is a set of four 16-bit registers used for addressing starting memory
location of various segment of the memory.
 Code Segment (CS) register: It holds the base address for the Code Segment
 Stack Segment (SS) register: SS holds the base address for the Stack Segment
 Data Segment (DS) register: DS holds the base address for the Data Segment
 Extra Segment (ES) register: ES holds the base address for the Extra Segment

 Instruction Pointer (IP):

 It is a 16-bit register used to hold offset address of the next instructions to be
executed in the Code Segment.
 Address of the next instruction is calculated as: CS x 10H + IP.
 IP is incremented after every instruction byte is fetched.
 IP gets a new value whenever a branch occurs.

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 BUS INTERFACE UNIT (BIU)
 Address Generation Circuit:
 This circuit generates the 20 bit physical address using Segment and Offset
addresses using the formula:
Physical Address = Segment Address x 10H + Offset Address
 6-Byte Pre-fetch Queue:
 It is a 6-byte first in first out (FIFO) based RAM used to implement pipelining.
 Fetching the next instruction while executing the current instruction is called
pipelining.
 BIU fetches the next six instruction bytes from the Code Segment and stores it into
the queue.
 Then, Execution Unit (EU) decode each instructions from the queue and executes.
 The queue is refilled when at least 2-bytes are empty as 8086 has a 16-bit data
bus.
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 EXECUTION UNIT (EU)
 Execution Unit (EU):
 It fetches instructions from the Queue in BIU, decodes and executes them
 It performs arithmetic, logic and internal data transfer operations within the μP
 It sends request signals to the BIU to access the external module.

 The main components of the EU are as follows:

 Control Unit
 Arithmetic Logic Unit
 Operand register
 General purpose registers
 Special purpose registers
 Flag register
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 EXECUTION UNIT (EU)
 Control Unit (CU):
 It produces control signal after decoding the opcode to inform the general
purpose register to release the value stored in it.
 Also signals the ALU to perform the desired operation.

 Arithmetic Logic Unit(ALU):

 It has a 16 bit ALU that can performs 8 and 16 bit arithmetic and logic operations
(like add, subtract, OR, AND, NOT) according to the signal generated by the CU.

 Operand register:
 It is a 16-bit temporary register used by the processor to hold the temporary
values at the time of operation.
 It is not available to the programmer.

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 EXECUTION UNIT (EU)
 General purpose registers:
 8086 has four 16 bit general purpose registers AX, BX, CX and DX.
 These are available to the programmer for storing values during programs.
 Each of these can be divided into two 8 bit registers such as AH, Al; BH, BL; etc.
 Beside their general use, these registers also have some specific functions.
 AX Accumulator register:
 It holds operands and results during multiplication and division operations.
 All I/O data transfers using IN and OUT instructions use A register (AL/AH or AX).
 Preferred register to use in arithmetic, logic and data transfer instructions.
 BX Base register:
 It holds the memory address (offset address) in indirect addressing modes.

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 EXECUTION UNIT (EU)
 CX Count register:
 It holds count for instructions like loop, rotate, shift and string operations.
 DX Data register:
 It is used with AX to hold 32 bit values during multiplication and division.
 It is used to hold the address of the I/O port in indirect I/O addressing mode.

 Special purpose registers (16-Bit):

 Stack Pointer (SP):
 It holds offset address of the top of the Stack.
 Stack is a set of memory locations operating in LIFO manner.
 Stack is present in the memory in Stack Segment.
 It is used during instructions like PUSH, POP, CALL, RET etc.

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 EXECUTION UNIT (EU)
 Base Pointer (BP):
 BP can hold offset address of any location in the stack segment.
 It is used to access random locations of the stack.

 Source Index (SI):

 It is normally used to hold the offset address for Data Segment but can also be
used for other segments using Segment Overriding.
 It holds offset address of source data in Data Segment during string operations.

 Destination Index (DI):

 It is normally used to hold the offset address for Extra Segment but can also be
used for other segments using Segment Overriding.
 It holds offset address of destination in Extra Segment during string operations.

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 EXECUTION UNIT (EU)
 Flag register: It has 9 flags that show the different conditions of the result.
 6 Status flags namely carry flag, parity flag, auxiliary carry flag, zero flag, sign flag are affected by
the ALU after every arithmetic or logic operation. They give the status of the current result.
 3 Control flags namely trap flag, interrupt flag and direction flag are used to control certain
operations. They are changed by the programmer.

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 FLAG REGISTER

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 FLAG REGISTER EXAMPLE-1
 Show how the flag register is affected by the addition of 38H and 2FH.
MOV BH,38H
ADD BH,2FH

Solution: MOV BH,38H ;BH=38H

ADD BH,2FH ;BH = BH + 2F = 38 + 2F= 67H

38 0011 1000
+ 2F 0010 1111
67 0110 0111
• CF = 0 since there is no carry beyond d7
• PF = 0 since there is odd number of 1`s in the result
• AF = 1 since there is a carry from d3 to d4
• ZF = 0 since the result is not zero
• SF = 0 since d7 of the result is zero
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 FLAG REGISTER EXAMPLE-2
 Show how the flag register is affected by the addition of 38H and 2FH.
MOV AX,34F5H
ADD AX,95EBH

Solution: MOV AX,34F5H ; AX =34F5H

ADD AX,95EBH ; AX = CAE0H
34F5 0011 0100 1111 0101
+ 95EB 1001 0101 1110 1011
CAE0 1100 1010 1110 0000
• CF = 0 since there is no carry beyond d15
• PF = 0 since there is odd number of 1s in the lower byte
• AF = 1 since there is a carry from d3 to d4
• ZF = 0 since the result is not zero
• SF = 1 since d15 of the result is 1
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 18

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 MEMORY ORGANIZATION IN 8086
 In memory, data is stored as bytes and each byte has a specific address/memory location

 Intel 8086 has 20 lines address bus and it can address to a memory location of 220 bytes,
220=1048576 bytes (1MB)

 In 8086, 20-bit address is expressed as 5 hex digits ranging from 00000h to FFFFFH

 Physical address is 20 bits long and corresponds to the actual binary code output by the
BIU on the address bus lines.

 Problem: 20-bit addresses are TOO BIG to fit in 16-bit registers of 8086;
Solution: Memory Segment
 Segmentation is the process in which the main memory of the computer is logically divided
into different segments and each segment has its own base address
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 SEGMENT REGISTERS
 Memory segmentation is the methods where whole memory is divided into small parts
called segments of various sizes.

 Why Memory segmentation? It is used to enhance the speed of execution, so that the
processor is able to fetch and execute the data from the memory easily and fast.

 The 1MB memory interfaced with 8086 is divided into 16 logical segments, each with a
memory of 64KB

 In 8086, memory has four different types of segments these are:

 Code Segment : Used to store executable program
 Stack Segment : Used to store stack operation related data
 Data Segment : Used to store data
 Extra Segment : Used similar to Data segment to store data
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 LOGICAL AND PHYSICAL ADDRESS
 Each of these segments are addresses by an address stored in the corresponding segment
register called the base address (starting address)

 The starting address of the segment should be such that it can be evenly divided by 16.

 An address within a segment used to specify particular memory location is called an

offset or logical address it can range from 0000H to 0FFFFH.

 A logical address gives the displacement from the base address of the segment to the
desired location within it.

 A logical address, as opposed to its “real” address, which maps directly anywhere into
1MB of memory space. The “real” address is called physical address.

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 SEGEMNT REGISTER

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 PHYSICAL ADDRESS GENERATION
 If the data segment starts at location 1000H and a data reference contains the address 0029H where is the
actual data?
Physical address = (Segment register x 10H) + offset address

Offset: 0000000000101001 Offset value (16 bits)

Segment: 0001000000000000 0000 Segment Registers (16 bits) 0000

Adder
Address: 0001000000000010 1001

Physical Address (20 Bits)

Physical address is obtained by shifting the segment address 4 bits to the left and adding the offset address

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 EXAMPLE-1

 What is the physical address of the logical address A4FB:4872

 Offset is 4872
 Segment address is A4FB
A 4 F B 0
A4FB0
1010 0100 1111 1011 0000

4 8 7 2

+ 4872
0100 1000 0111 0010

A 9 8 2 2

A9822
1010 1001 1000 0010 0010

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 EXAMPLE-2

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 EXAMPLE-3
0H
4000H
CS: 0400H
CS:IP = 400:56
4056H Logical Address
IP 0056H

Segment Register Memory

0400 0
Offset
+ 0056
Physical or 0FFFFFH

Absolute Address 04056H

The offset is the distance in bytes from the start of the segment.
The offset is given by the IP for the Code Segment.
Instructions are always fetched with using the CS register.

The physical address is also called the absolute address.

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 EXAMPLE-4
0H

0A000H
SS: 0A00
0A100H
SP 0100 SS:SP

Segment Register
Memory
0A00 0
Offset
+ 0100
Physical Address
0FFFFFH
0A100H
The offset is given by the SP register.
The stack is always referenced with respect to the stack segment register.
The stack grows toward decreasing memory locations.
The SP points to the last or top item on the stack.

PUSH - pre-decrement the SP

POP - post-increment the SP
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 28

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  Vcc (Pin 40):The external power supply of + 5V is provided to
the processor.

 Vss (Pin 1 & 20): These two pins acts as the ground.

 CLK (Pin 19) - Clock signal: It provides timing to the processor to

perform its operations

 AD0 – AD15 (Pin 2 to 16, 39) - Multiplexed Address/ Data Bus:

 Either address or data bus will be enable from multiplexed bus
 16 lines of the address and data bus are multiplexed together so
as to reduce the number of lines inside the IC.
 During the first clock cycle, it carries 16-bit address and after that
it carries 16-bit data.

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  A16/S3 – A19/S6 (Pin 35 to 38) - Address/Status Bus:
 Out of 20 address bits, higher 4-bit address lines are multiplexed
with status signals
 During memory operations, these pins act as address bus and
contain memory address of instruction or data
 During I/O operations these pins are low that shows the status of
the processor.
 S6 shows whether the 8086 is the bus master or any other
proficient device is acting as the bus
 S5 indicate the status of the interrupt flag in the microprocessor.
 S3 and S4 show which memory segment is currently accessed by
the microprocessor.
S4 S3 Function
0 0 Extra segment access
0 1 Stack segment access
1 0 Code segment access
1 1 Data segment access

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  BHE’/S7 (Pin 34) – Bus High Enable:
 S7 currently not been used for any purpose
 The combination of the BHE signal and A0 status informs
about different combinations of the data present on the bus.
BHE A0 Data Access
0 0 Word
0 1 Upper Byte from ODD address
1 0 Lower Byte from EVEN address
1 1 None

 MN/MX’ (Pin 33) - Minimum/Maximum Mode: It indicates what

mode the processor is to operate in minimum (single processor)
mode (HIGH) or Maximum (Multiprocessor) Mode (LOW)

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  RD’ (Pin 32) – Read: An active low signal at this pin shows that
the microprocessor is performing read operation with either
memory or I/O devices.

 TEST (Pin 23): This pin basically shows the wait instruction. (0
means the processing inside the processor continues, 1 means the
processor has to wait for the disabling of this pin)

 READY (Pin 22): It used by the peripherals and memory devices

in order to show the readiness for the next operation. When it is
high, it indicates that the device is ready to transfer data. When
it is low, it indicates wait state.

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  RESET (Pin 22): Whenever this pin is enabled then it resets the
processor and other devices connected to the system by
immediately terminating the executing task.

 NMI (Pin 17) - Non-Maskable Interrupt: It is a uncontrollable

interrupts generated inside the processor. When an NMI occurs,
then an interrupt service routine is generated by the interrupt
vector table.

 INTR (Pin 18) – Interrupt request: The processor after each clock
cycle samples the INTR and if the signal at this pin is found to be
high then the processor controls that interrupt internally.

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 MINIMUM MODE PINS

 HOLD (Pin 31): When an external device enables this pin then
the processor stops accessing the buses immediately after the
recent task gets over.

 HLDA (Pin 30): This pin is used as a response pin for the hold
request. Once request for accessing the buses is produced by an
external entity. Then the microprocessor acknowledges the device
that its request will be considered once it gets over by the current
operation.

 WR’ (Pin 29) Write: An active low signal at this pin indicates that
the processor is performing write operation from either memory
or I/O devices.

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 MINIMUM MODE PINS
 M/IO’ (Pin 28) Memory or I/O devices: This pin indicates
whether the processor is performing an operation with memory
or I/O devices. Whenever a high is present at this pin then it
shows the operation is carried out through the memory. While a
low signal shows operation through I/O devices.

 DT/R’ (Pin 27) Data Transmit/Receive : This pin is used to show

whether the data is getting transmitted or is received. A high
signal at this pin provides the information regarding the
transmission of data. While a low indicates reception of data.

 DEN’ (Pin 26) – Data ENable: This is an active low pin that
means whenever 0 is present at this pin then the transceiver gets
enabled and it separates the data from the multiplexed address
and data bus.
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 MINIMUM MODE PINS

 ALE (Pin 25) Address Latch Enable: Whenever an address is

present in the multiplexed address and data bus, then the
microprocessor enables this pin. This is done to inform the
peripherals and memory devices about fetching of the data or
instruction at that memory location.

 INTA’ (Pin 24) Interrupt Acknowledge: Whenever an INTR signal

is generated, then the microprocessor generates INTA signal, as
a response to that interrupt.

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 MAXIMUM MODE PINS

 RQ’/ GT0‘ and RQ’/ GT1‘ (Pin 30 and 31) Request/Grant: Due
to the involvement of multiple processors, these pins indicate the
request and grant permission signals used by the other
processors requesting the CPU to access the buses, memory and
peripherals. When the signal is received by CPU, then it sends
acknowledgment. RQ/GT0 has a higher priority than RQ/GT1.

 LOCK’ (Pin 29): when a single processor is accessing the buses

and peripherals then it locks the resources being used by it. while
LOCK’ is active low(0) no other entity can access it until the
recent processor frees it.

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 MAXIMUM MODE PINS

 S0‘, S1‘ and S2‘ (Pin 26 to 28) Status Pins: These are used by
the 8288 bus controller for generating all the memory and I/O
operation access control signals.
S2 S1 S0 Status
0 0 0 Interrupt acknowledgement
0 0 1 I/O Read
0 1 0 I/O Write
0 1 1 Halt
1 0 0 Opcode fetch
1 0 1 Memory read
1 1 0 Memory write
1 1 1 Passive state

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 MAXIMUM MODE PINS

 QS1,QS0 (Pin 24 and 25) Queue Status: These signals indicate

the status of the internal 8086 instruction queue

QS1 QS0 Status

0 0 No operation
0 1 First byte of op code from queue
1 0 Empty the queue
1 1 Subsequent byte from queue

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 MINIMUM MODE vs MAXIMUM MODE
Minimum Mode Maximum Mode
There can be only one processor, i.e.8086 There can be multiple processors with 8086, like 8087 and 8089
Mn/Mx’ is 1 to indicate minimum mode Mn/Mx’ is 0 to indicate maximum mode
ALE for the latch is given by 8086 as it is the ALE for the latch is given by 8288 bus controller as there can be
only processor in the circuit. multiple processors in the circuit.
DEN’ and DT/R’ for the transceivers are given by DT/R’ for the transceivers are given by8288 bus controller.
8086 itself.
Direct control signals M/IO’ , RD’ and WR’ are Instead of control signals each processor generates status signals
given by 8086 called S2’, S1’ and S0’.
Control signals M/IO’ , RD’ and WR’ are Status signals called S2’, S1’ and S0’ are decoded by a bus
decoded by 3:8 decoder like 74138 controller like 8288 to produce control signals
INTA’ is given by 8086 in response to an INTA’ is given by bus controller 8288 in response to an interrupt on
interrupt on INTR line INTR line
HOLD and HLDA signals are used for bus request RQ’ or GT’ lines are used for bus request by other processors like
with a DMA controller like 8237 8087, 8089

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 41

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 INTRODUCTION
 An instruction is a basic command given to a microprocessor to perform a specified
operation with given data.

 Each instruction has two groups of bits. OPCODE OPERAND

Specify the operation to Specify the data to be

be performed operated

 Example: MOV AX, 4000H – Here MOV is operation, AX and 4000H are operands

 Different format of specifying operand or data in an instruction is called addressing mode

 There are different types of addressing modes depending upon the location of data in
the 8086 processor.
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 IMMEDIATE ADDRESSING MODE
 In this mode, the source operand is an 8-bit or 16-bit data is specified as part of the
instruction.

 You cannot use this addressing mode to load immediate value into segment registers.

 To move any value into segment registers, first load that value into a general-purpose
register then load the value into segment register.

 Example:
MOV DL, 08H ; The immediate 8-bit data (08H) given in the instruction is moved to DL

MOV AX, 0A9FH ; The immediate 16-bit data (0A9FH) given in the instruction is moved to AX

Destination Source

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 REGISTER ADDRESSING MODE
 In this mode, operands are specified using registers (8-bit or 16-bit) in the instruction.
 This addressing mode is normally preferred because the instructions are compact and
fastest executing of all instruction forms.
 Important Rules:
 Never mix an 8-bit register with 16-bit, it is not allowed in microprocessor.
 Code segment register (CS) is never used as destination.
 Segment to segment MOV instruction is not allowed.
 Example:
MOV AL, BL ; Copies 8-bit content of BL into AL
MOV AX, CX ; Copies 16-bit content of CX into AX
MOV ES, DS ; Not allowed (segment to segment)
MOV BL, DX ; Not allowed (mixed size)
MOV CS, AX ; Not allowed (Code segment register may not be destination register)
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 MEMORY ADDRESSING MODE
 In 8086, Memory Address is represented in the form Seg : Offset (Eg - 89AB:F012)
since largest register is only 16-bits.

 When processor wants to access memory, it uses contents of segment and offset register to
compute the Physical Address (PA) using below formula.
Physical Address = Segment Address x 10H + Offset Address
 The offset of a memory operand is called the operand’s effective address (EA).

 EA is an unsigned 16 bit no., that expresses the operands distance in byte from the
beginning of the segment.

 To access memory we use following four registers:

Base Register: BX, BP; Index Register: SI, DI
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 MEMORY ADDRESSING MODE
 EU calculates EA by summing a Content of Base register, Content of Index register and
Displacement.

 Displacement (also known as relative) is an 8 or 16 bit no., and it is generally specified in

the operand field of the instruction.

 So by combining these registers inside [ ] symbols, we can get different memory locations
(Effective Address, EA)
Physical address

Segment address Offset address

INDEX
Contents of
DISPLACEMENT BASE
Index register (SI or DI)
8 bit or 16bit value Contents of
Base register (BX or BP)
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 MEMORY ADDRESSING MODE (Supported combinations)

Direct Addressing Mode d16 (variable offset only)

[SI]
[DI]
Register Indirect Addressing Mode
[BX]
[BP]
[SI + d8] [SI + d16]
[DI + d8] [DI + d16]
Register Relative Addressing Mode
[BP + d8] [BP + d16]
[BX + d8] [BX + d16]
[BX + SI]
[BX + DI]
Base Indexed Addressing Mode
[BP + SI]
[BP + DI]
[BX + SI + d8] [BX + SI + d16]
[BX + DI + d8] [BX + DI + d16]
Relative Base Indexed Addressing Mode
[BP + SI + d8] [BP + SI + d16]
[BP + DI + d8] [BP + DI + d16]

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 DIRECT ADDRESSING MODE
 In this mode, a 16-bit memory address (offset) where the operand is present is directly
given in the instruction.
 Here only the offset address is specified, the segment being indicated by the instruction.
 Example: MOV BX, [5221H] ; Moves data from location 5221H in the DS into CL
MOV CX, [4320H] ; Moves data from 4320H and 4321H; in the DS into CL and CH
Note : Register/memory enclosed
in [ ] brackets refer to content of
register/ memory

Assume DS = 5000H; 16-bit address is 5221H

∴ PA= 50000 + 5221 = 52221H.

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 REGISTER INDIRECT ADDRESSING MODE
 In this mode, the effective address of the memory will be taken directly from one of the
base register or index register specified by instruction.
 If register is SI, DI and BX then DS is by default segment register, If BP is used, then SS is
default segment register.
 Example: MOV CX, [BX] ; Copies the word contents of the DS memory location addressed by BX into CX.
MOV [BP], DL ; Copies DL into SS memory location addressed by BP.

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 REGISTER RELATIVE ADDRESSING MODE
 In this mode, the data is available at an effective address is formed by adding an 8-bit
or 16-bit displacement value with the content of any one of the register BX, BP, SI & DI
given in the instruction.
 Example:
MOV AX, [DI+100H] ; Copies the word content of the DS memory addressed by DI plus 100H into AX.
MOV CL, [BX + 04H] ; Copy a byte from the address pointed by BX + 4 in data segment to CL. CL ←
DS: [BX + 04H]. Physical address can be calculated as DS * 10H + BX + 4H.

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 BASE INDEXED ADDRESSING MODE
 In this mode, Effective address is sum of the base register and index register, both of
which are specified by the instruction.
 The base register often holds the beginning location of a memory array, whereas the
index register holds the relative position of an element in the array
 Example: MOV CX, [BX+DI] ; Copies the word content of the DS addressed by BX plus DI into CX.
MOV [BP+DI], CL ; Moves a byte from CL into the address pointed by BP+DI in Stack Segment.
Physical Address: SS * 10H + BP + DI

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 RELATIVE BASE INDEXED ADDRESSING MODE
 In this mode, effective address is sum of the base register, index register and 8/16-bit
displacement value, all of them are specified in the instruction itself.

 Example: MOV CL, [BX+DI+10] ; Moves a byte from the address pointed by BX+SI+10H in DS to CL.
MOV [BP+SI+4000], CL ; Moves a byte from CL into the location pointed by BP+SI+4000H in
SS. Physical Address: SS * 10H + BP+SI+4000H

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 53

 STRING ADDRESSING MODE
 In this mode, the effective address (EA) of source data is stored in SI register and the EA
of destination is stored in DI register.
 In this the value of SI and DI are auto incremented and decremented depending upon the
value of directional flag (DF).
 Segment register for calculating base address of source data is DS and that of the
destination data is ES
 Example: MOVSW ; Moves a word from the address pointed DS:SI to ES:DI.
MOVSB ; Moves a byte from the address pointed DS:SI to ES:DI.

Calculation of source memory location Calculation of destination memory location

EA = (SI) BA = (DS) x 10H PA = BA + EA EA = (DI) BA = (ES) x 10H PA = BA + EA

If DF = 1, then (SI)  (SI) – 1 and (DI) = (DI) - 1

If DF = 0, then (SI)  (SI) +1 and (DI) = (DI) + 1

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 DIRECT & INDIRECT I/O PORT ADDRESSING MODE
 It can be either direct or indirect. These addressing modes are used to access data from
standard I/O mapped devices or ports.

 In direct I/O port addressing, the I/O address is specified in the instruction.

 Example: IN AL, [09H] ; Content of port with address 09H is moved to AL register
Operations: PORTaddr = 09H, (AL)  (PORT)

 In indirect I/O port addressing, the instruction will specify the name of the register which
holds the port address. In 8086, the 16-bit port address is stored in the DX register.

 Example: OUT [DX], AX ; Content of AX is moved to port address is specified by DX

Operations: PORTaddr = (DX), (PORT)  (AX)

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 IMPLIED ADDRESSING MODE
 Instructions using this mode have no operands.

 The instruction itself will specify the data to be operated by the instruction.

 Example: STC ; Sets the Carry Flag.

CLD ; Clears the Direction Flag
CLC ; Clears the carry flag to zero.
DAA ; Decimal adjust for addition

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 GUESS THE ADDRESSING MODE

 MOV AX, [0002H] - Direct addressing mode

 MOV CX, 037AH - Immediate addressing mode
 MOV DL, [BX] - Register indirect addressing mode
 XCHG DL,[BP+200H] - Register relative addressing mode
 POP BX - Register addressing mode
 MOV SI , [BX+DI+2H] - Relative Base indexed addressing mode
 OUT [3BH], AL - Direct I/O Port addressing mode
 DAS - Implied addressing mode
 MOV SI , [BX+DI] - Base indexed addressing mode

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 58

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 58

  An instruction is a binary pattern designed inside a microprocessor to perform a specific
function.

 The entire group of instructions that a microprocessor supports is called Instruction Set.

 The 8086 microprocessor supports 6 types of instructions

1. Data Transfer Instructions - General purpose, special purpose, I/O Port, Flag
2. Arithmetic Instructions - Addition, Subtraction, Multiplication, Division
3. Bit Manipulation Instructions – Logical, Shift, Rotate
4. String Instructions
5. Program Execution Transfer Instructions
6. Processor Control Instructions
MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 59
 DATA TRANSFER INSTRUCTIONS
DATA TRANSFER INSTRUCTIONS
 These instructions are used to transfer data from source to destination.

 The source/destination data may be a register, memory location, port etc.

 Data transfer instructions are classified into four groups.

General Purpose Data Special Address Input / Output Port Flag Transfer
Transfer Instructions Transfer Instructions Transfer Instructions Instructions
MOV LEA IN LAHF
XCHG LDS OUT SAHF
XLAT LES PUSHF
PUSH POPF
POP

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 60

 DATA TRANSFER INSTRUCTIONS
GENERAL PURPOSE DATA TRANSFER INSTRUCTIONS
MOV Instructions
 Copies a word or a byte of data from a specified source to a specified destination.
 Size of source and destination must be the same, no flags affected.
 Source can be register, memory, or immediate data and Destination can be register or memory location.
 Both Source and Destination cannot be memory location or segment registers at the same time.

Mnemonic Meaning Format Operation Flags Effected

MOV Move MOV D,S (S) → (D) None

 Example:
 MOV CX, 037AH ; Move 037AH into the CX; 037A → CX
 MOV AX, BX ;Copy the contents of register BX to AX ; BX → AX
 MOV DL, [BX] ;Copy byte from memory at BX to DL ; DS*10+BX →DL
MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 61
 DATA TRANSFER INSTRUCTIONS
GENERAL PURPOSE DATA TRANSFER INSTRUCTIONS
XCHG Instruction
 Exchanges the contents of the register with the contents of another register (or) the
contents of the register with the contents of the memory location.
 Direct memory to memory exchanges are not supported.
 The both operands must be the same size and one of the operand must always be a register.

Mnemonic Meaning Format Operation Flags Effected

XCHG Exchange MOV D↔S (D) ↔ (S) None

 Example:
 XCHG CX, [037AH] ;[ (DS* 10)+ 037A]↔ CX
 XCHG AX, [BX] ;[(DS* 10)+ BX]↔ AX
 XCHG DL,[BP+200H] ; [(SS* 10)+ BP+200]↔DL

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 DATA TRANSFER INSTRUCTIONS
GENERAL PURPOSE DATA TRANSFER INSTRUCTIONS

For the figure below. What is the result of executing the following instruction?
XCHG AX, [0002]

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 63

 DATA TRANSFER INSTRUCTIONS
GENERAL PURPOSE DATA TRANSFER INSTRUCTIONS
XLAT Instruction - Translate a byte in AL
 XLAT exchanges the byte in AL register from the user table index to the table entry,
addressed by BX.
 The no-operands form (XLATB) provides a "short form" of the XLAT instructions.
 Translate instruction is used to find out codes in case of code conversion

Mnemonic Meaning Format Operation Flags Effected

XLAT Translate XLAT AL ←(DS*10+(AL)+(BX)) None

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 64

 DATA TRANSFER INSTRUCTIONS
GENERAL PURPOSE DATA TRANSFER INSTRUCTIONS

For the figure below, what is the result of executing the following instruction?
XLAT

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 65

 DATA TRANSFER INSTRUCTIONS
GENERAL PURPOSE DATA TRANSFER INSTRUCTIONS
PUSH and POP Instructions
 The PUSH and POP instructions are important instructions that store and retrieve data from
the LIFO (Last In First Out) stack memory.
 PUSH instruction is used to write word to the stack
 When a word is to be pushed onto the top of the stack, The value of SP is first automatically
decremented by two and then the contents of the register written into the stack.
 POP instruction is used to read word from the stack..
 When a word is to be popped from the top of the stack, the contents are first moved out the stack to
the specific register then the value of SP is incremented by two.
Mnemonic Meaning Format Operation Flags Effected
PUSH Push word onto the PUSH S (SP) ← (SP-2) None
stack ((SP)) ← (S)
POP Pop word off stack POP D D ← ((SP)) None
(SP) ← (SP+2)
MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 66
 DATA TRANSFER INSTRUCTIONS
GENERAL PURPOSE DATA TRANSFER INSTRUCTIONS

Let AX=1234H,SS=0105H and SP=0006H. Figure below shows the state of stack prior
and after the execution of next program instructions?
PUSH AX
POP BX
POP AX

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 67

 DATA TRANSFER INSTRUCTIONS
SPECIAL ADDRESS TRANSFER INSTRUCTIONS
LEA, LDS, and LES Instructions
 These instructions load a segment and general purpose registers with an address directly
from memory.
 LEA transfers the offset of the source operand to a destination operand.
 LDS transfers 32-bit pointer variable from source operand to destination operand and DS
 LES transfers 32-bit pointer variable from source operand to destination operand and ES.
Mnemonic Meaning Format Operation Flags Effected
LEA Load register with Effective LEA reg16, EA EA → (reg16) None
Address
LDS Load register and DS with LDS reg16, EA [PA] → (reg16) None
words from memory [PA+2] → (DS)
LES Load register and ES with LES reg16, EA [PA] → (reg16) None
words from memory [PA+2] → (ES)

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 68

 DATA TRANSFER INSTRUCTIONS
SPECIAL ADDRESS TRANSFER INSTRUCTIONS

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 69

 DATA TRANSFER INSTRUCTIONS
SPECIAL ADDRESS TRANSFER INSTRUCTIONS

Assuming that (BX)=100H, DI=200H, DS=1200H, SI= F002H, AX= 0105H, and the following
memory content. what is the result of executing the following instructions?
a. LEA SI , [ DI + BX +2H]
b. MOV SI , [DI+BX+2H]
c. LDS CX, [300]
d. LES BX , [DI+AX]

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 70

 DATA TRANSFER INSTRUCTIONS
GENERAL PURPOSE DATA TRANSFER INSTRUCTIONS
IN/OUT Instructions
 IN transfers a byte or word from an input port to the AL register or AX register.
 OUT transfers a byte or a word from AL register or AX register respectively, to an output port.
 IN/OUT instruction has two formats:
 Fixed port: port number is specified directly in the instruction (port no: 0-255).
 Variable port: port number is loaded into the DX before IN/OUT instruction (port no : 0 – 65535).

Mnemonic Meaning Format Operation Flags Effected

IN Input direct IN Acc, Port (Acc) ← (Port) None
Input variable IN Acc, DX (Acc) ← (DX)
OUT Output direct OUT Port, Acc (Port)← (Acc) None
Output variable OUT DX , Acc (DX) ← (Acc)

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 71

 DATA TRANSFER INSTRUCTIONS
GENERAL PURPOSE DATA TRANSFER INSTRUCTIONS

 Example:
 IN AL,0C8H ;Input a byte from port 0C8H to AL
 IN AX, 34H ;Input a word from port 34H to AX
 OUT 3BH, AL ;Copy the contents of the AL to port 3Bh
 OUT 2CH, AX ;Copy the contents of the AX to port 2Ch

INPUT OPERATION OUTPUT OPERATION

MOV DX, 0FF78H ;Initialize DX point to port MOV DX, 0FFF8H ;Load desired port address in DX
IN AL, DX ;Input a byte from a 8 bit port 0FF78H to AL OUT DX, AL ; Copy the contents of AL to FFF8h
IN AX, DX ;Input a word from 16 bit port to 0FF78H to AX. OUT DX, AX ;Copy content of AX to port FFF8H

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 72

 DATA TRANSFER INSTRUCTIONS
FLAG TRANSFER INSTRUCTIONS
 LAHF Instruction - Load Register AH From Flags : It copies the value of SF,
ZF, AF, PF, and CF, into bits of 7, 6, 4, 2, 0 respectively of AH register.

 SAHF instruction - Store AH Register into FLAGS: It transfers the bits 0-7 of
AH of SF, ZF, AF, PF, and CF, into the Flag register.

 PUSHF Instruction - Push flag register on the stack: It decrements the SP by

2 and copies the word in flag register to the memory pointed to by SP.

 POPF Instruction - Pop word from top of stack to flag register: It copies a
word from the two memory location at the top of the stack to flag register
and increments the stack pointer by 2.
MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 73
 ARITHMETIC INSTRUCTIONS
ARITHMETIC INSTRUCTIONS
 These instructions are those which are useful to perform Arithmetic calculations, such as
addition, subtraction, multiplication and division.

 Arithmetic instructions are classified into four groups.

Addition Subtraction Multiplication Division
Instructions Instructions Instructions Instructions
ADD SUB MUL DIV
ADC SBB IMUL IDIV
INC DEC AAM AAD
AAA NEG CBW
DAA CMP CWD
AAS
DAS

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 74

 ARITHMETIC INSTRUCTIONS
SIGNED & UNSIGNED NUMBERS
 An 8 bit number system can be used to create 256 combinations (from 0 to 255), and the
first 128 combinations (0 to 127) represent positive numbers and next 128 combinations
(128 to 255) represent negative numbers.

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 ARITHMETIC INSTRUCTIONS
SIGNED & UNSIGNED NUMBERS
 In Decimal in order to get -2, we subtract 2 from the number of combinations (256), which
gives, 256 - 2 = 254.

 In Binary all the Signed Numbers have a '1' in the Most Significant Bit (MSB) position which
represents a negative number and a '0' in the Most Significant Bit (MSB) position which
represents a positive number.

 Also, in Binary, the 2's Complement of a number is the negative equivalent of the positive
number. So, +2 = 0000 0010 and the 2's Complement is 1111 1110 which is - 2.

 A 16 bit number system can be used to create 65536 combinations (from 0 to 65535),
and the first 32768 combinations (0 to 32767) represent positive numbers and next
32768 combinations (32768 to 65536) represent negative numbers.

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 76

 ARITHMETIC INSTRUCTIONS
ADDITION INSTRUCTIONS
ADD Instructions
 This instruction adds the contents of source operand with the contents of destination
operand. The result is stored in destination operand.
 The source may be immediate data, memory location or register.
 The destination may be memory location or register.
Mnemonic Meaning Format Operation Flags Effected
ADD Addition ADD D, S (S)+(D) → (D), carry → (CF) O, S, Z, A, P, C

 Example: (Addition of Un Signed numbers)  Example: (Addition of Signed numbers)

ADD CL, BL ADD CL, BL
 Assume that CL = 01110011 =115 decimal  Assume that CL = 01110011 = + 115 decimal
and BL = 01001111 = 79 decimal and BL = 01001111 = +79 decimal
 Result in CL = 11000010 = - 62 decimal
 Result in CL = 11000010 = 194 decimal  Incorrect since result is too large to fit in 7-bits.
MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 77
 ARITHMETIC INSTRUCTIONS
ADDITION INSTRUCTIONS
ADC Instructions
 This instruction adds the contents of source operand with the contents of destination
operand with carry flag (CF) bit. The result is stored in destination operand.
 The source may be immediate data, memory location or register.
 The destination may be memory location or register.

Mnemonic Meaning Format Operation Flags Effected

ADC Add with carry ADC D, S (S)+(D) +(CF)→ (D), carry → (CF) O, S, Z, A, P, C

 Example:
ADC CL, BL
 Assume that CL = 01110011 =115 decimal, BL = 01001111 = 79 decimal and CF=1

 Result in CL = 11000011 = 195 decimal

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 78

 ARITHMETIC INSTRUCTIONS
ADDITION INSTRUCTIONS
INC Instruction
 Increment the byte or word contents of source operand by 1.
 The source may be memory location or register.
 The source can not be immediate data.
 The result is stored in the same place.

Mnemonic Meaning Format Operation Flags Effected

INC Increment by 1 INC S (S)+1 → S O, S, Z, A, P

 Example:
INC AX
 Assume AX = 7FFFh. After this instruction AX = 7FFFh + 1 = 8000h

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 79

 ARITHMETIC INSTRUCTIONS
ADDITION INSTRUCTIONS
DAA Instruction
 Convert the result of the addition operation of 2 packed BCD numbers to a valid BCD.
 It is used immediately after normal addition instruction operating on BCD codes.
 It assumes the AL register as the source and the destination, and hence it requires no operand.

Mnemonic Meaning Format Operation Flags Effected

Decimal adjust If lower nibble of AL > 9 or AF = 1 then : AL=AL+6 & AF = 1
DAA DAA S, Z, A, P, C
for addition else if AL > 9Fh or CF = 1 then : AL = AL + 60h & CF = 1

 Example:

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 80

 ARITHMETIC INSTRUCTIONS
ADDITION INSTRUCTIONS
AAA Instruction
 Used to adjust the result of the two ASCII values that range from 30h (“0”) to 39h (“9”)
after addition
 Numerical data coming into a computer from a terminal is usually in ASCII code, the numbers 0 to 9 are
represented by the ASCII codes 30H to 39H.
 AAA instruction should be executed immediately after the ADD instruction that adds ASCII data
 It assumes the AL register as the source and the destination, and hence it requires no operand.

Mnemonic Meaning Format Operation Flags Effected

If low nibble of AL > 9 or AF = 1 then :
• AL = AL + 6, AH = AH + 1, AF = 1,CF = 1
ASCII adjust
AAA AAA else AF=0, CF=0 A, C
for addition
• Higher nibble of AL is cleared
(To convert it to ASCII , OR it with 3030h)

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 ARITHMETIC INSTRUCTIONS
ADDITION INSTRUCTIONS
AAA Instruction
 Example:

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 82

 ARITHMETIC INSTRUCTIONS
SUBTRACTION INSTRUCTIONS
SUB Instructions
 This instruction subtract the contents of source operand with the contents of destination
operand. The result is stored in destination operand.
 The source may be immediate data, memory location or register.
 The destination may be memory location or register.
Mnemonic Meaning Format Operation Flags Effected
SUB Subtraction SUB D,S (S)-(D) → (D), borrow → (CF) O, S, Z, A, P, C

 Example: (Subtraction of Unsigned numbers)  Example: (Subtraction of Signed numbers)

SUB BH,CL SUB BH,CL
 CL = 10011100 = 156 decimal and BH =  Assume that CL = 00101110 = + 46 decimal
00110111 = 55 decimal and BH = 01001010= + 74 decimal
 Result in CL = 01100101 = 101 decimal  Result in CL = 11100100 = - 28 decimal
 CF, AF, SF, ZF = 0, OF, PF = 1  CF = 1, AF, ZF =0,SF = 1 result negative
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 ARITHMETIC INSTRUCTIONS
SUBTRACTION INSTRUCTIONS
SUBB Instructions
 This instruction subtract the contents of source operand with the contents of destination
operand with carry flag (CF) bit as borrow. The result is stored in destination operand.
 The source may be immediate data, memory location or register.
 The destination may be memory location or register.

Mnemonic Meaning Format Operation Flags Effected

SBB Subtract with borrow SBB D,S (S)-(D) - (CF)→ (D), borrow → (CF) O, S, Z, A, P, C

 Example:
SUBB CL, BL
 Assume that CL = 01110011 =115 decimal, BL = 01001111 = 79 decimal and CF=1

 Result in CL = 00100011 = 35 decimal

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 ARITHMETIC INSTRUCTIONS
SUBTRACTION INSTRUCTIONS
DEC Instruction
 Decrement the byte or word contents of source operand by 1.
 The source may be memory location or register.
 The source can not be immediate data.
 The result is stored in the same place.

Mnemonic Meaning Format Operation Flags Effected

DEC Decrement by 1 DEC S (S)-1 → S O, S, Z, A, P

 Example:
DEC AX
 Assume AX = 7FFFh. After this instruction AX = 7FFFh - 1 = 7FFEh

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 ARITHMETIC INSTRUCTIONS
SUBTRACTION INSTRUCTIONS
DAS Instruction
 Convert the result of the subtraction operation of 2 packed BCD numbers to a valid BCD.
 It is used immediately after normal subtraction instruction operating on BCD codes.
 It assumes the AL register as the source and the destination, and hence it requires no operand.

Mnemonic Meaning Format Operation Flags Effected

Decimal adjust If lower nibble of AL > 9 or AF = 1 then : AL=AL-6 & AF = 1
DAS DAA S, Z, A, P, C
for Subtraction else if AL > 9Fh or CF = 1 then : AL = AL - 60h & CF = 1

 Example:

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 86

 ARITHMETIC INSTRUCTIONS
SUBTRACTION INSTRUCTIONS
AAS Instruction
 Used to adjust the result of the two ASCII values that range from 30h (“0”) to 39h (“9”)
after subtraction
 Numerical data coming into a computer from a terminal is usually in ASCII code, the numbers 0 to 9 are
represented by the ASCII codes 30H to 39H.
 AAA instruction should be executed immediately after the SUB instruction that subtracts ASCII data
 It assumes the AL register as the source and the destination, and hence it requires no operand.

Mnemonic Meaning Format Operation Flags Effected

If low nibble of AL > 9 or AF = 1 then :
• AL = AL - 6, AH = AH - 1, AF = 1,CF = 1
ASCII adjust
AAS AAA else AF=0, CF=0 A, C
for subtraction
Higher nibble of AL is cleared
(To convert it to ASCII , OR it with 3030h)

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 87

 ARITHMETIC INSTRUCTIONS
SUBTRACTION INSTRUCTIONS
AAS Instruction
 Example:

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 88

 ARITHMETIC INSTRUCTIONS
SUBTRACTION INSTRUCTIONS
NEG Instruction
 Performs the two’s complement of a given number
 It changes the sign of a number, positive number become negative and vice versa
 The source may be memory location or register.
 It gives the same result as the invert each bit and add one algorithm.

Mnemonic Meaning Format Operation Flags Effected

0 – (S)→ (S)
NEG Negate NEG S O, S, Z, A, P, C
1 → (CF)

 Example:
MOV AX , 2CBh
NEG AX ;after executing NEG result AX =FD35h.

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 89

 ARITHMETIC INSTRUCTIONS
SUBTRACTION INSTRUCTIONS
CMP Instruction
 Compares a byte/word in the specified source with a byte/word in the specified
Destination
 The source can be an immediate number, a register, or a memory location and the destination can be a
register or a memory location. But, the source and the destination cannot both be memory locations.
 The comparison is done by subtracting the source byte/word from the destination byte/word.
 The source/destination are not changed, but the flags are set to indicate the results of the comparison.
Mnemonic Meaning Format Operation Flags Effected
CMP Compare CMP D,S (D)-(S), Affects only flags O, S, Z, A, P, C

 Example:
CMP CX, BX

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 90

 ARITHMETIC INSTRUCTIONS
MULTIPLICATION INSTRUCTIONS
MUL Instruction
 Multiple unsigned operand 8-bit/16-bit with AL/AX and store the result in AX/DX-AX.
 The unsigned byte or word may be in any one of the general purpose registers or memory locations.
 Immediate operand is not allowed. All flags are modified depending upon the result.
 If operand is of 8-bit then multiply it with contents of AL. If 16-bit then multiply it with contents of AX.
 Result is stored in accumulator AX in 8 bit operation and DX-AX in 16bit operation.
Mnemonic Meaning Format Operation Flags Effected
(AL)*(S8) → (AX)
MUL Multiply (Unsigned) MUL S Undefined
(AX)*(S16) → (DX)(AX)

 Example: (8-Bit Multiplication)  Example: (16-Bit Multiplication)

MUL BL MUL BX
 Assume AL=FCH, BL=04H, AH=0H  Assume AX= F000H, BX= 9015H, DX= 0000H
 MUL BL=AL.BL=FCH *04H=03F0H→AX  MUL BX =AX.BX=F000H*9015H=8713H→DX, B000H→AX
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 ARITHMETIC INSTRUCTIONS
MULTIPLICATION INSTRUCTIONS
IMUL Instruction
 Multiply signed operand 8-bit/16-bit with AL/AX and store the result in AX/DX-AX.
 This instruction is same as MUL instruction, except it works on signed numbers

Mnemonic Meaning Format Operation Flags Effected

(AL)*(S8) → (AX)
IMUL Integer Multiply (Signed) IMUL S Undefined
(AX)*(S16) → (DX)(AX)

 Example: (8-Bit Multiplication)  Example: (16-Bit Multiplication)

MOV AL, 25 ; AL=19H MOV AX, 25 ; AX=0064H
MOV BL, -4 ; BL=FCH (2’s Complement of 4) MOV BX, -3 ; BX=00FDH (2’s Comp. of 3)
IMUL BL IMUL BX
 IMUL BL=19H *FCH=FF9CH (-100 in dec.)→AX  IMUL BX=64H*FDH=FFFFH →DX, FED4H→AX(-300 in Dec.)
 Since result is negative SF=1  Since result is negative SF=1
 Also result is valid hence CF=0, OF=0  Also result is valid hence CF=0, OF=0
MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 92
 ARITHMETIC INSTRUCTIONS
MULTIPLICATION INSTRUCTIONS
AAM Instruction
 Used to adjust the result of the two ASCII values that range from 30h (“0”) to 39h (“9”)
after multiplication
 Numerical data coming into a computer from a terminal is usually in ASCII code, the numbers 0 to 9 are
represented by the ASCII codes 30H to 39H.
 AAM instruction should be executed immediately after the MUL instruction that Multiply ASCII data
 works on the content of the AL register, and hence it requires no operand.
Mnemonic Meaning Format Operation Flags Effected
ASCII adjust for AH = AL / 10, AL = remainder
AAM AAM Z, A, S
Multiplication (To convert it to ASCII , OR it with 3030h)
 Example:
MOV AL, 04 ; AL=04
MOV BL, 09 ; BL=09
MUL BL ; AX=0024H, AH=00, AL=24H (36 in decimal)
AAM ; AH=AL/10=24H/10= 03 →AH (Q), 06 →AL(R)
MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 93
 ARITHMETIC INSTRUCTIONS
DIVISION INSTRUCTIONS
DIV Instruction
 Divide unsigned operand AX/DX-AX by 8-bit/16-bit number and store the result in
AX/DX-AX.
 Operand may be general purpose register or memory location.
Mnemonic Meaning Format Operation Flags Effected
Q((AX)/(S8)) → (AL) ; R((AX)/(S8)) → (AH)
DIV Division (Unsigned) DIV S Undefined
Q((DX,AX)/(S16)) → (AX) ; R((DX,AX)/(S16)) → (DX)

 Example: (8-Bit Division)  Example: (16-Bit Division)

MOV AX, 00F3H ; AX=00F3H MOV AX, 1250H ; AX=1250H
MOV BL, 91H ; BL=91H MOV BL, 90H ; BL=90H
DIV BL DIV BX
 DIV BL =00F3H/91H = 62H (Reminder) →AH,  DIV BX =1250H/90H = 50H (Reminder) →AH,
01H (Quotient) → AL. 20H (Quotient) → AL.

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 94

 ARITHMETIC INSTRUCTIONS
DIVISION INSTRUCTIONS
IDIV Instruction
 Divide a signed word by a signed byte, or to divide a signed double word by a signed word.
 The locations of quotients, remainders, dividends and divisors are the same as in the DIV instruction
 The sign of the remainder is the same as that of the dividend.
 8086 will automatically generate a type 0 interrupt:
 If an attempt is made to divide by 0
 Quotient > +127 (7FH) or <–127 (81H) for signed word by a signed byte
 Quotient > +32,767 (7FFFH) or <–32,767 (8001H) for signed double word by a signed word

Mnemonic Meaning Format Operation Flags Effected

Integer Divide Q((AX)/(S8)) → (AL) ; R((AX)/(S8)) → (AH)
IDIV IDIV S Undefined
(Signed) Q((DX,AX)/(S16)) → (AX) ; R((DX,AX)/(S16)) → (DX)

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 95

 ARITHMETIC INSTRUCTIONS
DIVISION INSTRUCTIONS

 Example: (8-Bit Division)

 Assume AH = 00H, AL = F3H, BL = 91H (Negative number)
𝐴𝑋 00𝐹3𝐻 00𝐹3𝐻
𝑰𝑫𝑰𝑽 𝑩𝑳 = = ′ = = 2𝐻 𝑄𝑢𝑜𝑡𝑖𝑒𝑛𝑡(𝑄) 𝑎𝑛𝑑 15𝐻 𝑅𝑒𝑚𝑖𝑛𝑑𝑒𝑟(𝑅)
𝐵𝐿 2 𝑠(91𝐻) 6𝐹𝐻

AH (R) AL (Q) AH (R) AL (Q) AH (R) AL (Q)

𝑷𝒐𝒔𝒊𝒕𝒊𝒗𝒆
15 02 but 𝑵𝒆𝒈𝒂𝒕𝒊𝒗𝒆
= 𝑵𝒆𝒈𝒂𝒕𝒊𝒗𝒆 15 2’s (02) → 15 FE

 Example: (16-Bit Division)

 Assume DX=0000H, AX=FFF0H, BX=9000H (Negative number)

𝐷𝑋 𝐴𝑋 0000 𝐹𝐹𝐹0𝐻 0000 𝐹𝐹𝐹0𝐻

𝑰𝑫𝑰𝑽 𝑩𝑿 = = ′ = = 2𝐻 𝑄𝑢𝑜𝑡𝑖𝑒𝑛𝑡(𝑄) 𝑎𝑛𝑑 1𝐹𝐹0𝐻 𝑅𝑒𝑚𝑖𝑛𝑑𝑒𝑟(𝑅)
𝐵𝑋 2 𝑠(9000𝐻) 7000𝐻

DX (R) AX (Q) DX (R) AX (Q) DX (R) AX (Q)

𝑷𝒐𝒔𝒊𝒕𝒊𝒗𝒆
1FF0 0002 but 𝑵𝒆𝒈𝒂𝒕𝒊𝒗𝒆
= 𝑵𝒆𝒈𝒂𝒕𝒊𝒗𝒆 1FF0 2’s (0002) → 1FF0 00FE

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 96

 ARITHMETIC INSTRUCTIONS
DIVISION INSTRUCTIONS
AAD Instruction
 Converts two unpacked BCD digits in AH and AL to the equivalent binary number in AL
 This adjustment must be made before dividing the two unpacked BCD digits in AX by an unpacked BCD
byte.
 After the BCD division, AL will contain the unpacked BCD quotient and AH will contain the unpacked
BCD remainder.

Mnemonic Meaning Format Operation Flags Effected

ASCII Adjust before
AAD AAD AL = (AL + (10 * AH)) then set AH = 00H S, P, Z
Division

 Example:
MOV AX, 0206H ; AX=0206H
MOV BL, 05H ; BL=09
AAD ; AL = (AL + (10 * AH)) = (06+(10*02))=1AH (26 in decimal), AH=00H
DIV BL ; DIV BL =AX/BL =001AH/05H = 01H (Reminder) →AH, 05H (Quotient) → AL.

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 97

 ARITHMETIC INSTRUCTIONS
DIVISION INSTRUCTIONS
CBW Instruction
 Converts the signed value in the AL register into an equivalent 16 bit signed value in the
AX register by duplicating the sign bit to the left.
 This instruction copies the sign of a byte in AL to all the bits in AH.

 AH is then said to be the sign extension of AL.

Mnemonic Meaning Format Operation Flags Effected
CBW Convert signed Byte to signed word CBW extends the sign of AL into all of AH None

 Example:
CBW

 If AH=00H, AL=9BH (-155 in Decimal or 10011011 in Binary)

 After CBW execution, AX = 11111111 10011011 = - 155 decimal

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 98

 ARITHMETIC INSTRUCTIONS
DIVISION INSTRUCTIONS
CWD Instruction
 Converts the 16 bit signed value in the AX register into an equivalent 32 bit signed value
in DX: AX register pair by duplicating the sign bit to the left.
 This instruction copies the sign of a byte in AX to all the bits in DX.
 The effect is to create a 32-bit signed result that has same integer value as the original 16-bit operand.

Mnemonic Meaning Format Operation Flags Effected

Convert Signed Word to - Signed
CWD CWD extends the sign of AX into all of DX None
Double word

 Example:
CWD

 If DX=00H, AX=F0C7H (-3897 in Decimal or 11110000 11000111 in binary)

 After CWD, DX= FFFFH:AX=F0C7H (-3897 in Decimal or 11111111 11111111 11110000 11000111 in binary)
MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 99
 BIT MANIPULATION INSTRUCTIONS
BIT MANIPULATION INSTRUCTIONS
 These instructions are used to perform Bit wise operations and classified into Three
groups.
Logical Instructions Shift Instructions Rotate Instructions
NOT SHL / SAL ROL
AND SHR ROR
OR SAR RCL
XOR RCR
TEST

 Logical instructions to perform bit by bit logic operation on the specified source and
destination operands.
 Shift instructions can perform two basic types of shift operations; the logical shift and the
arithmetic shift. Also, each of these operations can be performed to the right or to the left.
 Rotate instructions, rotate the contents from 1 to 255 bit positions to the left or to the right.
MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 100
 BIT MANIPULATION INSTRUCTIONS
LOGICAL INSTRUCTIONS
NOT Instruction
 Inverts each bit (forms the 1’s complement) of a byte or word in the specified destination.
 The destination can be a register or a memory location.

Mnemonic Meaning Format Operation Flags Effected

NOT Logical NOT NOT D (D’) → (D) None

 Example:
NOT AL

 If AL=0DH (0000 1101 in Binary)

 NOT AL = (0DH)’ or 1’s complement of 0000 1101 = 1111 0010 = F2H

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 101

 BIT MANIPULATION INSTRUCTIONS
LOGICAL INSTRUCTIONS
AND Instruction
 Performs bit-wise AND operation on Destination and Source operand.
 used to clear certain bits in the operand(masking). Ex.: Clear the high nibble of BL register
AND BL, 0FH ; (xxxx xxxx AND 0000 1111 = 0000 xxxx)
Mnemonic Meaning Format Operation Flags Effected
AND Logical AND AND D, S (S) . (D) → (D) O, S, Z, P, C

 Example: (Perform AL AND BL)  Example: (Clear bit 4 of DH register)

MOV AL, 45H ; AL=45H AND DH,EFH ; (xxxxxxxx AND 11101111 = xxx0xxxx)
MOV BL, 25H ; BL=25H  If DH=9FH (1001 1111 in Binary)
AND AL, BL ; AL = 45H AND 25H = 05H  AND DH, EFH = (9FH) . (EFH) = 1000 1111 = 8FH

TEST Instruction
 Similar to AND instruction but result is not stored anywhere, affects only flag bits.
MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 102
 BIT MANIPULATION INSTRUCTIONS
LOGICAL INSTRUCTIONS
OR Instruction
 Performs bit-wise OR operation on Destination and Source operand.
 Used to set certain bits. Ex.: Set the lower three bits of BL register
OR BL, 07H ; (xxxx xxxx OR 0000 0111 = xxxx x111)
Mnemonic Meaning Format Operation Flags Effected
OR Logical OR OR D, S (S) + (D) → (D) O, S, Z, P, C

 Example: (Perform AL OR BL)  Example: (Set bit 7 of AL register)

MOV AL, 45H ; AL=45H OR AL,80H ; (xxxx xxxx OR 1000 0000= 1xxx xxxx)
MOV BL, 25H ; BL=25H  If AL=6FH (0110 1111 in Binary)
OR AL, BL ; AL = 45H OR 25H = 65H  OR AL, 80H= (6FH) . (80H) = 1110 1111= EFH

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 103

 BIT MANIPULATION INSTRUCTIONS
LOGICAL INSTRUCTIONS
XOR Instruction
 Performs bit-wise XOR operation on Destination and Source operand.
 Used to invert certain bits (toggling bits). Ex.: Invert bit 2 of DL register
XOR BL, 04H ; (xxxxxxx XOR 0000 0100 = xxxxxxxx)
 Used to clear a register by XORed it with itself. Ex.: Clear DX register
XOR DX, DX (DX will be 0000H)
Mnemonic Meaning Format Operation Flags Effected
XOR Logical XOR XOR D, S (S) ⊕ (D) → (D) O, S, Z, P, C

 Example: (Perform AL XOR BL)

MOV AL, 45H ; AL=45H
MOV BL, 25H ; BL=25H
XOR AL, BL ; AL = 45H XOR 25H = 60H

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 104

 BIT MANIPULATION INSTRUCTIONS
SHIFT INSTRUCTIONS
 Shift instructions can perform two basic types of shift operations; the logical shift and the
arithmetic shift. Also, each of these operations can be performed to the right or to the left.

 Shift instructions are used to

 Align data
 Isolate bit of a byte of word so that it can be tested
 Perform simple multiply and divide computations

 The source can specified in two ways

 Value of 1 : Shift by One bit
 Value of CL register : Shift by the value of CL register

 Note that the amount of shift specified in the source operand can be defined explicitly if it
is one bit or should be stored in CL if more than 1.
MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 105
 BIT MANIPULATION INSTRUCTIONS
SHIFT INSTRUCTIONS

Mnemonic Meaning Format Operation Flags Effected

C, P, S, Z
Shift arithmetic Shift the (D) left by the number of bit positions equal
SAL D, Count A undefined
SAL/SHL left /shift logical to Count and fill the vacated bits positions on the
SHL D,Count O undefined if
left right with zeros
count ≠1
C, P, S, Z
Shift the (D) right by the number of bit positions
A undefined
SHR shift logical right SHR D,Count equal to Count and fill the vacated bit positions
O undefined if
on the left with zeros
count ≠1
C, P, S, Z
Shift the (D) right by the number of bit positions
Shift arithmetic A undefined
SAR SAR D,Count equal to Count and fill the vacated bit positions
right O undefined if
on the left with the original most significant bit
count ≠1

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 106

 BIT MANIPULATION INSTRUCTIONS
SHIFT INSTRUCTIONS

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 107

 BIT MANIPULATION INSTRUCTIONS
SHIFT INSTRUCTIONS

 Example for SHL/SAL:

MOV AX, 1234H ; AX=1234H
SHL AX,1 ; AX=2468H

 Example for SHR:

MOV AX, 1234H ; AX=1234H
MOV CL, 2H ; CL=2H
SHR AX, CL ; AX=048DH

 Example for SAR:

MOV AX, 091AH ; AX=091AH
MOV CL, 2H ; CL=2H
SAR AX, CL ; AX=0246H
MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 108
 BIT MANIPULATION INSTRUCTIONS
ROTATE INSTRUCTIONS
 They have the ability to rotate the contents from 1 to 255 bit positions to the left or to the
right of either an internal register or a storage location in memory.
 Moreover, in the case of a multibit rotate, the number of bit positions to be rotated is
specified by the value in CL.
Mnemonic Meaning Format Operation Flags Effected
Rotate the (D) left by the number of bit positions equal
C, O undefined
ROL Rotate left ROL D, Count to Count. Each bit shifted out from the leftmost bit goes
if count ≠1
back into the rightmost bit position.
Rotate the (D) right by the number of bit positions equal
C, O undefined
ROR Rotate right ROR D, Count to Count. Each bit shifted out from the rightmost bit goes
if count ≠1
back into the leftmost bit position
Rotate left C, O undefined
RCL RCL D, Count Same as ROL except carry is attached to (D) for rotation
through carry if count ≠1
Rotate right C, O undefined
RCR RCR D, Count Same as ROR except carry is attached to (D) for rotation
through carry if count ≠1
MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 109
 BIT MANIPULATION INSTRUCTIONS
ROTATE INSTRUCTIONS

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 110

 BIT MANIPULATION INSTRUCTIONS
ROTATE INSTRUCTIONS

 Example for ROL:

MOV AX, 1234H ; AX=1234H
ROL AX,1 ; AX=2468H, CF=0

 Example for ROR:

MOV AX, 1234H ; AX=1234H
MOV CL, 4H ; CL=4H
ROR AX, CL ; AX=4243H, CF=0

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 111

 BIT MANIPULATION INSTRUCTIONS
ROTATE INSTRUCTIONS

 Example for RCL:

 Example for RCR:

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 112

 STRING INSTRUCTIONS
 The string instructions function easily on blocks of memory, can speed up the manipulating
code also the size of the program is considerably reduced.

 They are useful in array handling, tables and records.

 Five basic String Instructions define operations on one element of a string:

 Move byte or word string - MOVSB/MOVSW
 Compare string - CMPSB/CMPSW
 Scan string - SCASB/SCASW
 Load string - LODSB/LODSW
 Store string - STOSB/STOSW

 Along with above string instructions 8086 uses auto-indexing and prefix instructions in
order to perform effective block transfer of memory content from DS to ES.

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 113

 STRING INSTRUCTIONS
STRING INSTRUCTIONS
Mnemonic Meaning Format Operation Flags Effected
((DS)*10+(SI))→((ES)*10+ (DI))
MOVSB/
MOVS Move string (SI)± 1 → (SI); (DI) ± 1 → (DI) [byte] None
MOVSW
(SI) ± 2 → (SI); (DI) ± 2 → (DI) [word]
((DS)*10+ (SI))→(AL) or (AX)
LODSB/
LODS Load string (SI) ± 1 →(SI) [byte] None
LODSW
(SI) ± 2 → (SI) [word]
(AL) or (AX) →((ES)*10+ (DI))
STOSB/
STOS Store string (DI) ± 1 → (DI) [byte] None
STOSW
(DI) ± 2 → (DI) [word]
((DS)*10+(SI))-((ES)*10+ (DI))
CMPSB/
CMPS Compare string (SI) ± 1 → (SI); (DI) ± 1 → (DI) [byte] O, S, Z, A, P, C
CMPSW
(SI) ± 2 → (SI); (DI) ± 2 → (DI) [word]
(AL) or (AX) -((ES)*10+ (DI))
SCASB/
SCAS Scan string (DI) ± 1 → (DI) [byte] O, S, Z, A, P, C
SCASW
(DI) ± 2 → (DI) [word]

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 114

 STRING INSTRUCTIONS
AUTO-INDEXING OF STRING INSTRUCTIONS

 Execution of a string instruction causes the address indices in SI and DI to be either

automatically incremented or decremented.

 The decision to increment or decrement is made based on the status of the direction flag.

 The direction Flag: Selects the auto increment (D=0) or the auto decrement (D=1)
operation for the DI and SI registers during string operations.

Mnemonic Meaning Format Operation Flags Effected

CLD Clear DF CLD 0→(DF) DF
STD Set DF STD 1→(DF) DF

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 115

 STRING INSTRUCTIONS
PREFIXES FOR STRING INSTRUCTIONS
 In most applications, the string operations must be repeated in order to process arrays of
data hence following repeat prefixes can be to used along with string instructions.
Mnemonic Used with Meaning
REP MOVS, STOS, LODS Repeat while not end of string CX≠0
REPE/REPZ CMPS, SCAS Repeat while not end of string and strings are equal CX≠0&ZF=1
REPNE/REPNZ CMPS, SCAS Repeat while not end of string and strings are not equal CX≠0 &ZF=0

 For example, REP, caused the basic string operation to be repeated until the contents of
register CX become equal to 0.
 Each time the instruction is executed, it causes CX to be tested for 0.
 If CX is found not to be 0, it is decremented by 1 and the basic string operation is repeated.
 If it is 0, the repeat string operation is done and the next instruction in the program is executed.
 The repeat count must be loaded into CX prior to executing the repeat string instruction.
MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 116
 STRING INSTRUCTIONS

Example for MOVSB:

Write a program to copy a block of 32 consecutive bytes Example for STOSB:
from the block of memory locations starting at address 2000H
Write a program Store the block of memory
in the current DS to a block of locations starting at address
locations from 0A000H through 0A00FH
3000H in the current ES.
CLD with number 5H.
MOV AX, 4000H
MOV DS, AX MOV AX, 0H
MOV AX, 5000H MOV ES, AX
MOV ES, AX MOV AL, 05
MOV CX, 20H MOV DI, A000H
MOV SI, 2000H MOV CX, 0FH
MOV DI, 3000H CLD
REP AGAIN: STOSB
MOVSB LOOP AGAIN
HLT

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 117

 CONTROL TRANSFER INSTRUCTIONS
 These instructions transfer the program control from one address to other address. (Not in
a sequence).

 They are classified into four groups.

Unconditional Conditional Transfer Iteration Control Interrupt
Transfer Instructions Instructions Instructions Instructions
JA / JNBE JLE / JNG
JAE / JNB JNC
JB / JNAE JNE / JNZ LOOP
JMP JBE / JNA JNO LOOPE / INT
CALL JC JNP / JPO LOOPZ INTO
RET JE / JZ JNS LOOPNE / IRET
JG / JNLE JO LOOPNZ
JGE / JNL JP / JPE
JL / JNGE JS

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 118

 CONTROL TRANSFER INSTRUCTIONS
UNCONDITIONAL TRANSFER INSTRUCTIONS
JMP Instruction (Unconditional)
 JMP (Jump) unconditionally transfers control from one CS to another or within CS.
 These locations can be within the same code segment (near control transfers) or in
different code segments (far control transfers).
 There are two basic kinds of unconditional jumps:
• Intrasegment Jump: is limited to addresses within the current code segment. This type of jump is
achieved by just modifying the value in IP.
• Intersegment Jump: permit jumps from one code segment to another. Implementation of this type of
jump requires modification of the contents of both CS and IP.
Mnemonic Meaning Format Operation Flags Effected
Jump to the target address mentioned in the
JMP Unconditional Jump JMP target None
instruction
MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 119
 CONTROL TRANSFER INSTRUCTIONS
UNCONDITIONAL TRANSFER INSTRUCTIONS

Type
Iteration Control
Mnemonics
JMP Instruction Operation Example
Instructions
Short Jump Jump to address location specified as 8-bit constant
JMP 8-bit JMP 45H
[8-bit] value (8-bit) → (IP)
Jump to address location specified as 16-bit constant
JMP 16-bit JMP 1234H
Intersegment value (16-bit) → (IP)
Jump Near Jump Jump to the address location given in the register
JMP Reg. JMP SI
[16-bit] (Reg.) → (IP)
Jump to the address location pointed by the content
JMP [Reg.] JMP [SI]
present in the register [(Reg.)] → (IP)
Jump to address location specified as 16-bit constant JMP
JMP 16-bit:16-bit
value (First 16-bit) → (IP), (Second 16-bit) → (CS) 2000:1234
Intersegment
Far Jump Jump to the address location given in the registers
Jump
[32-bit] [(Reg.1)] → (IP), [(Reg.2)] → (CS)
JMP [Reg.1][Reg.2] JMP [BX][SI]

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 120

 CONTROL TRANSFER INSTRUCTIONS
UNCONDITIONAL TRANSFER INSTRUCTIONS
JMP Instruction (Unconditional)
Example: Assume the following state of 8086:(CS)=1075H, (IP)=0300H, (SI)=A00H, (BH)=20H,
(BL)=70H, (DS)=400H, (DS:A00)=10H, (DS:A01)=B3H, (DS:A20)=22H, (DS:A70)=1AH. To what
address is program control passed if each of the following JMP instruction is execute?.
Example Logical Address Jump Type
(a) JMP 85 ⇒ 1075:85 ⇒Short jump
(b) JMB 1000H ⇒ 1075:1000 ⇒Near jump
(c) JMP SI ⇒ 1075:0A00 ⇒Near jump
(d) JMP [SI] ⇒ 1075: B310 ⇒Near jump
(e) JMP 3000:1000 ⇒3000:1000 ⇒ Far jump
(f) JMP [BX][SI] ⇒1A22: B310 ⇒ Far jump

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 121

 CONTROL TRANSFER INSTRUCTIONS
UNCONDITIONAL TRANSFER INSTRUCTIONS
CALLL and RET Instruction
 A subroutine is a special segment of program that can be called for execution form any
point in program.
 There two basic instructions for subroutine :
• CALL instruction is used to call the subroutine
• RET instruction is used to initiate the return sequence to the main program environment.

Mnemonic Meaning Format Operation Flags Effected

Execution continues from the target
CALL Subroutine call CALL target address of the subroutine specified in the None
instruction.
Return to the main program by restoring IP
RET Return RET None
(and CS for far-proc).

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 122

 CONTROL TRANSFER INSTRUCTIONS
UNCONDITIONAL TRANSFER INSTRUCTIONS
 Just like the JMP instruction, CALL allows implementation of two types of operations: the
intrasegment call and intersegment call.
 The operand of the call instruction initiates an intersegment or intrasegment call.
 Intrasegment call causes contents of IP to be saved on Stack. The Operand specifies new
value in the IP that is the first instruction in the subroutine.
 Intersegment call causes contents of IP and CS to be saved in the stack and new values to
be loaded in IP and CS that identifies the location of the first instruction of the subroutine.
 Every subroutine must end by executing an instruction that returns control to the main
program. This is the return (RET).
 Execution of RET instruction at the end of the subroutine causes the original values of IP
and CS to be POPed from stack.
MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 123
 CONTROL TRANSFER INSTRUCTIONS
UNCONDITIONAL TRANSFER INSTRUCTIONS
Main program

Subroutine A

First Instruction
Call subroutine A Example for CALL:
Next instruction CALL 1234h
CALL BX
CALL [BX]
CALL DWORD PTR [DI]

Return
Call subroutine A
Next instruction

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 CONTROL TRANSFER INSTRUCTIONS
UNCONDITIONAL TRANSFER INSTRUCTIONS
Example CALL and RET :
Write a program that computes y = (AL)2+ (AH)2+ (DL)2, places the result in CX. Make use of the SQUARE
subroutine defined in the previous example. (Assume result y doesn’t exceed 16 bit) .

MOV CX, 0000H

MOV BL,AL
CALL SQUARE SQUARE: PUSH AX
ADD CX, BX MOV AL, BL
MOV BL,AH MUL BL
CALL SQUARE MOV BX, AX
ADD CX, BX POP AX
MOV BL,DL RET
CALL SQUARE
ADD CX, BX
HLT

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 CONTROL TRANSFER INSTRUCTIONS
CONDITIONAL TRANSFER INSTRUCTIONS
Jxx Instruction (Conditional)
 The conditional jump instructions test the following flag bits: S, Z, C, P, and O.

 If the condition under test is true, a branch to the label associated with jump instruction
occurs.

 If the condition is false, the next sequential step in the program executes.

Mnemonic Meaning Format Operation Flags Effected

If the condition is true, Jump to the target
Jxx Conditional Jump Jxx target address mentioned in the instruction else next None
instruction is executed

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 CONTROL TRANSFER INSTRUCTIONS
CONDITIONAL TRANSFER INSTRUCTIONS
Unsigned Conditional Transfer
Mnemonic Meaning (Jump if….) Condition
JA/JNBE Above/Not Below nor Equal CF=0 or ZF=0
JAE/JNB Above or Equal/Not Below CF=0
JB/JNAE Below/Not Above nor Equal CF=1
JBE/JNA Below or Equal/Not Above CF=1 or ZF=1
JC Carry CF=1
JE/JZ Equal/Zero ZF=1
JNC Not carry CF=0
JNE/JNZ Not Equal/Not Zero ZF=0
JNP/JPO Not Parity/ Not Parity Odd PF=0
JP/JPE Parity/Parity Even PF=1
JCXZ CX register is Zero CX=0 or ZF=0
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 CONTROL TRANSFER INSTRUCTIONS
CONDITIONAL TRANSFER INSTRUCTIONS
Signed Conditional Transfer
Mnemonic Meaning (Jump if….) Condition
JG/JNLE Greater/Not Less nor Equal ((SF xor OF) or ZF) = 0
JGE/JNL Greater or Equal/Not Less (SF xor OF) = 0
JL/JNGE Less/not Greater nor Equal (SF xor OF) = 1
JLE/JNG Less or Equal/Not Greater ((SF xor OF) or ZF) = 1
JNO Not Overflow OF = 0
JNS Not Sign (positive, including 0) SF = 0
JO Overflow OF = 1
JS Sign (negative) SF = 1

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 CONTROL TRANSFER INSTRUCTIONS
ITERATION CONTROL INSTRUCTIONS
LOOP Instructions
 These instructions can be use in place of certain conditional jump instruction and give the
programmer a simpler way of writing loop sequences.

Mnemonic Meaning Format Operation

(CX)  (CX) – 1
LOOP Loop LOOP short-label Jump to location given by short-label if CX ≠ 0;
otherwise, execute next instruction
(CX)  (CX) – 1
LOOPE/ Loop while equal/ LOOPE
LOOPZ loop while zero Jump to location given by short-label if CX ≠ 0
/LOOPZ short-label
and ZF=1; otherwise, execute next instruction
LOOPNE (CX)  (CX) – 1
LOOPNE/ Loop while not equal/
LOOPNZ loop while not zero /LOOPNZ short- Jump to location given by short-label if CX ≠ 0
label and ZF=0; otherwise, execute next instruction

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 CONTROL TRANSFER INSTRUCTIONS
ITERATION CONTROL INSTRUCTIONS
Example for LOOP :
Write a program to move a block of 100 consecutive bytes of data starting at offset address 400H in
memory to another block of memory locations starting at offset address 600H. Assume both block at the same
data segment 0000H. Use loop instructions.
MOV AX,0000H
MOV DS,AX
MOV ES,AX
MOV SI,0400H
MOV DI,0600H
MOV CX, 64H
NEXTPT: MOV AH,[SI]
MOV [DI], AH
INC SI
INC DI
LOOP NEXTPT
HLT

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 PROCESS CONTROL INSTRUCTIONS
 Process control instruction are used to change the process with the stored information. They
are again classified into two groups. They are:
1. Flag Control Instructions
2. External Hardware Synchronization Instructions

FLAG CONTROL INSTRUCTIONS

Mnemonic Meaning Operation Flag Effected

CLC Clear Carry Flag (CF)  0 CF
STC Set Carry Flag (CF)  1 CF
CMC Complement Carry Flag (CF)  (CF)l CF
CLD Clear Direction Flag (DF)  0 DF
STD Set Direction Flag (DF)  1 DF
CLI Clear Interrupt Flag (IF)  0 IF
STI Set Interrupt Flag (IF)  1 IF
MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 131
 PROCESS CONTROL INSTRUCTIONS
EXTERNAL HARDWARE SYNCHRONIZATION INSTRUCTIONS

Mnemonic Meaning Operation

Cause the 8086 to stop fetching and executing instructions until
HLT Halt processor valid INTR/NMI/RESET is received
The 8086 enters an idle condition where it is doing no processing
WAIT Wait for TEST pin activity until valid INTR/NMI is received

It pass instructions to a coprocessor and the coprocessor decodes

Escape to external the instruction and carries out the action specified by the 6-bit
ESC
processor interface code specified in the instruction.
Lock bus during next The 8086 will assert its bus lock signal output which then
LOCK prevents any other processor from taking over the system bus.
instruction
Used to fill in time delays by not performing any operation
NOP No operation except fetch and decode.

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 ASSEMBLER DIRECTIVES
 Assembler directives are the commands to the assembler that direct the assembly process. They indicate how
an operand is treated by the assembler and how assembler handles the program. No machine code is
generated for assembler directives
Assembler
Meaning Operation Example
Directives
IMPORTANT ASSEMBLER DIRECTIVES
Assume logical It provides information to the assembler
ASSUME ASSUME CS:CODE
segment name regarding the name of the data segment
It directs the assembler to start the memory
Origin ORG 1000H
ORG allotment from the address in the ORG
used to reserve byte or bytes of memory
DB Define Byte MARKS DB 35H,30H,35H,40H
locations in the available memory
Similar to DB, but it reserve word or words of
DW Define Word WORDS DW 1234H,4567H,2367H
memory locations instead of bytes.
It is used to assign a label with a value or
EQU Equate LABEL EQU 0500H
symbol
It indicate end of program, instruction after
END End of Program END
END will be ignored by the assembler.
MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 133
 134

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 134

 EXAMPLE – 1 ADDITION OF TWO 32-BIT NUMBERS
 To write 8086 Assembly Language Program to add two 32-bit numbers.

MOV AX,5000H ; Initialize DATA SEGMENT

MOV DS,AX ; to 5000H
MOV AX,[1000H] ; take lower 16-bit of NUM1 in AX
MOV BX,[2000H] ; take lower 16-bit of NUM2 in BX
ADD AX,BX ; AX = AX + BX
MOV [3000H],AX ; Store lower 16-bit result at NUM3
MOV AX,[1002H] ; take higher 16-bit of NUM1 in AX
MOV BX,[2002H] ; take higher 16-bit of NUM2 in BX
ADC AX,BX ; AX = AX + BX + CF (add with carry)
MOV [3002H],AX ; Store higher 16-bit result at NUM3
HLT ; Halt 8086

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 EXAMPLE – 2 TRANSFER BLOCK OF DATA IN REVERSE ORDER
 A block of 10 words is present in the memory location from address 5000: 1500h. Write
an 8086 ALP to arrange this block in reverse order from 6000: 4500h.
MOV AX, 5000h
MOV DS, AX
MOV AX, 6000h
MOV ES, AX
MOV SI, 1500h
MOV DI, 4500h
MOV CX, 0AH ; MOV CX, 10
CLD ; DF = 0
LODSW
L1: STD ; DF = 1
STOSW
LOOP L1
HLT
MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 136
 EXAMPLE – 3 FIND NUMBER OF 1’S AND 0’S IN A GIVEN DATA
 Write a 8086 assembly language program to find number of 1’s and 0’s in the given 8-
bit data and store it’s count value in BX and DX registers respectively.

MOV AX, 0100H ; INITIALIZE THE DATA SEGMENT

MOV DS, AX
MOV AL, 31H ; GET BYTE
MOV CX, 08H ; SET COUNTER
BACK: ROR AL, 1 ; MOVE MSB IN CARRY
JNC ZERINC ; CHECK BYTE FOR 0 AND 1
INC BX ; IF 1, INCREMENT ONE COUNT
JMP NEXT
ZERINC: INC DX ; IF 0, INCREMENT ZERO COUNTER
NEXT: DEC CX ; REPEAT UNIT CX = 0
JNZ BACK
HLT
MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 137
 EXAMPLE – 4 FIBONACCI SERIES
 Write an 8086 assembly language program to generate Fibonacci series. Assume memory
location 2000:0100H holds the count of Fibonacci series and consecutive memory location stored
with Fibonacci series values.
Fibonacci numbers : 0, 1, 1, 2, 3, 5, 8, 13, 21, 34, 55, …. Address Data
Counter to generate
In mathematical terms, Fn = Fn-1 + Fn-2 2000:0100 0A Fibonacci Series
2000:0101 00
MOV AX, 2000H 2000:0102 01
MOV DS, AX ...............
2000:0103 01
MOV SI, 0100H SUB CL, 02H
GENERATE: MOV AL,[SI-1] 2000:0104 02
MOV CL,[SI]
INC SI ADD AL,[SI] 2000:0105 03 Fibonacci Series
DAA in Decimal
MOV AL, 00H 2000:0106 05
MOV [SI], AL INC SI 2000:0107 08
INC SI MOV [SI],AL
2000:0108 13
INC AL LOOP GENERATE
HLT 2000:0109 21
MOV [SI], AL
............. 2000:010A 34
MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 138
 EXAMPLE – 5 CONVERT BCD TO HEX
 Write an 8086 assembly language program to convert given BCD (Decimal) value into Equivalent
Hexadecimal Value. Assume memory location 2000:1000H holds the BCD value and store the converted
Hex value in 2000:1001H.
MOV AX, 2000H
MOV DS, AX
MOV SI,1000H
MOV BL,[SI]
AND BL,0FH Decimal: 45 = (4x10) + (5x1)
MOV AL,[SI]
AND AL,0F0H Hexadecimal: (4x0AH) + (5x01H) = 2DH
MOV CL,04
ROR AL,CL
MOV DL,0AH
MUL DL
ADD AL,BL
INC SI
MOV [SI],AL
HLT
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 140

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 140

 INTRODUCTION
 Microprocessor based system design involves interfacing of the processor with one or
more peripheral devices for the purpose of communication with various I/O devices.

 I/O ports or input/output ports are the devices through which the microprocessor
communicates with other devices or external devices

 8255 is a programmable I/O device that acts as interface between peripheral devices
and the microprocessor for parallel data transfer.

 8255 PPI (programmable peripheral interface) is programmed in a way so as to have

transfer of data in different conditions according to the need of the system.

 Intel 8255 is a widely used general purpose parallel I/O interface which provides three
I/O port (Port A, Port B and Port C).
MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 141
 INTRODUCTION
 Features of 8255:
 It is available in 40 pin DIP.
 It contains 24 programmable I/O pins arranged as two 8-bit ports and two 4-bit ports.
 It has 3, 8-bit ports: Port A, Port B and Port C, which are arranged in two group of 12
pins.
 Fully compatible with Intel microprocessor families.
 Direct bit set/reset capability is available for port C.
 It can operate in 3 Modes: Mode 0 : Simple I/O, Mode 1 : Strobed I/O, Mode 2 :
Strobed bi-directional I/O.

 To program the function to all three i/O ports it contains a register called as control word
registers (CWR).

 CWR defines the function of each I/O port and in which mode they should operate.

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 INTRODUCTION

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 143

 8255 WORKING
Request Permission
8-Bit Port-A
Step-1: Assuming the connected device to be an input
8086 Data Bus 8255 I/O
device. Initially, the Input device seeks for permission Port-B
from PPI so that it can send data. μP PPI Devices
Port-C

8-Bit Port-A
Step-2: PPI permits Input devices to send data, only when
there is no left data in 8255 which should be sent to the 8086 Data Bus 8255 I/O
Port-B
8086. Once 8255 permits input device, data is received μP PPI Devices
Port-C
and stored in temporary registers in 8255.
Grant Permission

Transfer Data
Step-3: Once 8255 holds some data, then it send signal Port-A
8-Bit
to 8086. Whenever 8086 is free to receive the data, Data Bus
then 8086 sends back a signal , after that data 8086 8255 Port-B I/O
transmission happens between 8255 and 8086. μP PPI Devices
Port-C

All the signal in the above diagrams represented using dotted curved arrow are known as handshake signals.
MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 144
 Pin Name Function
D0-D7 Data Bus Carry data or control word to/from the microprocessor.
A “low” on this input pin enables communication between 8255
CS’ Chip Select
and μP
A “low” on this input pin enables 8255 to send the data or status
RD’ Read
information to the μP on the data bus.
A “low” on this input pin enables the μP to write data or control
WR’ Write
words into the 8255
Decide which 8255 Port (A,B,C)/Control word register will be
A0-A1 Address Pins
selected for transferring the data
When 8255 is reset, it clears the control word register and all
RESET Reset
ports are set to input mode.
These are 8-bit bidirectional I/O pins used to send data to the
PA0-PA7 Port A pins
peripheral or to read data from the peripheral.
PB0-PB7 Port B pins These are 8-bit bidirectional I/O pins used the same as PA0-PA7
These are 8-bit bidirectional I/O pins. These lines are divided
PC0-PC7 Port C pins
into 2 sections i.e. PC0-PC3 and PC4-PC7.

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 INTERFACING 8086 WITH 8255

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 146

 • Tristate means three states
viz. Logic 0, Logic 1 and high
impedance states. ... In high
impedance state, this pin is
disconnected from internal
circuit of microprocessor
electrically but not physically.
In this state, the processor is
disconnected from the bus

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MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 148
 8255 - INTERNAL ARCHITECTURE
 The internal architecture of 8255 consists of five blocks:
1. Data bus buffer
2. Read/Write control logic
3. Group A and Group B control
4. Port A, B and C
1. Data Bus Buffer:
 The 8-bit bidirectional tristate data bus buffer is used to interface 8255 internal data bus
with system data bus of the processor.
 The direction of data buffer is decided by read and write control signals.
 The buffer allows the passing of data from ports or control register to the system data bus
of CPU in case of write operation and from system data bus of CPU to ports or status
register in case of read operation.

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 8255 - INTERNAL ARCHITECTURE
2. Read/Write control logic:
 The function of this block is to manage all of the internal and external transfers of both
Data and Control or Status words.

 Whenever there exists a need for data fetch then it accepts the address provided by the
processor through the bus and immediately generates command to the two control groups.

3. Group A and Group B Control:

 Each of the Control blocks (Group A and Group B) accepts "commands" from the CPU as
"control word" and configure the ports (Port A, Port B and Port C) accordingly.

 Group A send the control signal to port A and Port C (Upper) PC7-PC4.

 Group B send the control signal to port B and Port C (Lower) PC3-PC0.

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 8255 - INTERNAL ARCHITECTURE
4. Ports A, B, and C:
 8255 has three 8-bit I/O ports labelled as PA0-PA7 (Port-A), PB0-PB7 (Port-B) and PC0-
PC7 (Port-C) and each one can be connected to the physical lines of an external device.
 All ports can be configured to a wide variety of functions by the system software.
 The function of ports A and B are independent of the mode of operation.
 The direct but set/reset capability is provided by port C only.

 The port C divided into 2 sections, port C upper (PCU) and port C lower (PCL). These two
sections can be programmed and used separately as a 4-bit I/O port.
 Port C can be used as (i)Simple I/O (ii) handshake signals (iii) status signal inputs.
 For handshake signals and status signals, it is used in coordination with port A and port B.

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 8255 – MODE OF OPERATION
 8255 can be configured in two modes:
1. BSR (Bit Set/Reset) Mode
2. I/O (Input-Output) Mode
 8255 Modes are configured by Control Word. A Control Word is an 8-bit data that
stored in control register. Control Words are two types:
(a) BSR Control Word (b) I/O Mode Control Word

1. BSR (Bit Set/Reset) Mode:

 The BSR mode affects port C only one bit of at a time. If a BSR mode is selected, it will not
affect I/O mode.
 The individual bits of port C (PC0 - PC7) can be set/reset by loading the command word
register using OUT instruction.

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 BSR MODE CONTROL WORD FORMAT

Problems:
(a) Write a control word to reset PC5. (Ans: 0AH)
(b) Write a Control Word to Set PC2. (Ans: 05H)
MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 153
 8255 – I/O MODE
2. I/O mode:
 Mode-0: (Simple I/O)
 In this mode, the ports can be used for simple input/output operations without
handshaking.

 If both port A and B are initialized in mode 0, port C can be either used together as
an additional 8-bit port, or they can be used as two individual 4-bit ports.

 Any port can be used as an input or output port.

 Output ports are latched but Input ports are not latched (buffered).

 Port do not have handshake or interrupt capability.

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 8255 – I/O MODE
 Mode-1: (Strobed I/O or I/O with handshaking)
 Ports A and B are programmed as I/O ports and Port C is used for handshaking

 If port A is initialized in mode 1 as handshake input port, then pins PC3, PC4 and
PC5 function as handshake signals. (PC6 and PC7 are available)

 If port A is initialized as handshake output port, then PC3, PC6 and PC7 function as
handshake signals. (PC4 and PC5 are available)

 Port B is initialized in mode 1 for either input or output, Pins PC0, PC1 and PC2
function as handshake signals.

 Interrupt logic is supported, Input and Output data are latched.

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 8255 – I/O MODE
 Mode-2: (Strobed Bidirectional I/O or Bidirectional I/O with handshaking)
 Port A is programmed to be bi-directional, Port C is for handshaking and Port B can
be either input or output in mode 0 or mode 1.

 In mode 2, port A can be used for “bi-directional handshake” data transfer i.e. data
can be input or output on the same eight lines. Pins PC3, PC4, PC5, PC6, PC7 used as
handshake lines for port A.

 Port B is operating in either mode 0 or mode 1. If port B is in mode 0, then PC0, PC1
and PC2 used for I/O, If port B is in mode 1, then PC0, PC1 and PC2 used as
handshake lines.

 Both inputs and outputs are latched.

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 8255 – MODE OF OPERATION SUMMARY

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 I/O MODE CONTROL WORD FORMAT

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 158

 8255 - PROBLEMS
 Problem-1: Write a control word to configure port A as input port in mode 0 and port B in
mode 1 as output port.

The control word is 94H.

 Problem-2: A I/O mode control word is given CW=CDH. Explain the conditions of ports of
8255A.

I/O Mode: Port-A is output port in Mode-2, Port-B is output port in Mode-1, Port-
C(Upper) and Port-C (Lower) are input Port.
 Exercise: Configure Port A in Mode 2, Port B as o/p in mode 1. (Ans: C4H / C5H)
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 8255 - PROBLEMS
 Problem-3: Write an 8086 assembly language procedure to read an ASCII character
from a keyboard via PORT A of an 8255 PPI when PORT C bit PC4 is strobed low.
Assume a base address of 20H.
Solution:
PORTA EQU 20H
PORTC EQU 24H
CONTROL EQU 26H
MOV AL, 98H ; 1001 1000
OUT CONTROL, AL ; Initialize PORTS
READ1: IN AL, PORTC ; Is Strobe PC4 Low?
TEST AL, 10H ; 0001 0000
JNZ READ1
IN AL, PORTA ; Read ASCII Character
RET
MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 160
 8255 - PROBLEMS
 Problem-4: Write an 8086 assembly language procedure to read 12 switches and display switch
condition on 12 LEDs with 8255 as shown in below figure. Assume base address is 00H.
Solution:
PORTA EQU 00H
PORTB EQU 02H
PORTC EQU 04H
CREG EQU 06H
MOV AL, 98H ; 1001 1000
OUT CREG, AL ; Initialize PORTS
REPEAT: IN AL, PORTA
OUT PORTB, AL
IN AL, PORTC
AND AL, 0F0H
MOV CL, 04H
ROR AL,CL
OUT PORTC, AL
JMP REPEAT
HLT
MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 161
 162

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 162

 INTRODUCTION
 Timer is a specialized type of device that is used to generate timing intervals.

 Applications of Timer:
 Real time clock
 Event-counter
 Programmable rate generator
 Complex waveform/ Square wave generator

 Timers may be designed in software or in hardware.

 Software: When the microprocessor needs to generate a time delay, the processor can elapse
time simply using a delay routine.
 Hardware: A specialized IC is used for the generation of delays and waveforms of different
frequencies
MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 163
 INTRODUCTION
 Microprocessor based computing systems usually have at least one hardware timer since it
makes microprocessor free from timer realted tasks and this minimizes the software
overhead of the processor.
 8254 is a hardware timer, typically a digital counters which counts down from a specified
value based on required time interval and generate a interrupt to μP on reaching zero.
 Features of 8254:
 Single +5V supply, 24 Pin dual in-line package.
 Compatible with Intel and other microprocessor.
 Operating frequency upto 10 MHz.
 Three independent 16 bit down counters.
 Counters can be programmed in 6 different programmable counter modes.
 Counting facility in both binary or BCD number system.
 Support READ BACK COMMAND to check the current status of the counter.
MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 164
 Pin Name Function
D0-D7 Data Bus Carry data or control word to/from the microprocessor.
Chip A “low” on this input pin enables communication between
CS’
Select 8254 and μP
A “low” on this input pin enables 8254 to send data from
RD’ Read
appropriate counter or status to μP on the data bus.
A “low” on this input pin enables the μP to load counter value
WR’ Write
or control words into the 8254
Address Decide which 8254 Counter (0,1,2)/Control word register
A0-A1
Pins will be selected for timer operation
These are clock inputs to 3 independent counters, the pulse
CLK0- Clock
applied at these pins will be counted by the respective
CLK2 Input
counter.
These are active high, input signals used to allow external
GATE0- Gate
hardware to control the respective counter. The function of
GATE2 Control
gate input is dependent on the operating mode.
OUT0- These Lines are active high, output lines. The output is
Output
OUT2 dependent on operating modes.

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 8254 – INTERFACING WITH 8086

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 166

 8254 – INTERNAL ARCHITECTURE

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 167

 8254 – INTERNAL ARCHITECTURE
 The internal architecture of 8254 consists of four blocks:
1. Data bus buffer
2. Read/Write control logic
3. Control Word Register
4. Counters
1. Data Bus Buffer:
 It is tristate, bidirectional 8-bit data bus buffer and it is used to interface 8254 data bus
with system data bus.

 It is internally connected to internal data bus and its outer pins D0-D7 are connected to
system data bus.

 The direction of data buffer is decided by read and write control signals.
MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 168
 8254 – INTERNAL ARCHITECTURE
2. Read/Write control logic:
 This block accepts inputs from system control bus and address bus.
 8254 operation is enables/disabled by CS’ signal. CS’ is connected to address decoder.
 The control word registers and the counters are selected according to the signals on line A0
and A1. A0 and A1 are directly connected to address lines A1 and A2 lines of μp.
 In I/O mapped I/O, the signals RD’ and WR’ are connected to IOR’ and IOW’. In
memory mapped I/O, RD’ and WR’, are connected to MEMR’ and MEMW’.
A1 A0 Selection
0 0 Counter 0
0 1 Counter 1
1 0 Counter 2
1 1 Control word register
MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 169
 8254 – INTERNAL ARCHITECTURE
3. Control Word Register:
 This register of 8254 programmable interval timer gets selected when A0=1 and A1=1.

 It is used to specify the BCD or binary counter to be used, its mode of operation and the
data transfer to be used i.e read or write the data bytes.

 If the CPU performs a write operation, the data is stored in the control word register and
is offered to as control word. It is used to define counter operation.

 The data can only be written into control word register, no read operation is allowed.

 Status information is available with the help of read back command.

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 170

 8254 – INTERNAL ARCHITECTURE
4. Counters:
 There are three independent, 16-bit down counters – Counter 0, 1, 2.

 They can be programmed through control word register to decide mode of counter.

 The loaded count value in counter will be decremented by counter at each clock pulse.

 The programmer can read counter without disturbing counter operation.

 Each timer contains:

– a CLK input which provides the basic operating frequency to the timer
– a Gate input pin which controls the timer in some modes.
– an Output (OUT) connection to obtain the output of the timer.
MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 171
 8254 - OPERATIONS FOR VARIOUS CONTROL INPUTS

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 172

 8254 – WRITE OPERATION
 8254 Write operation:

1. Decide on which counter(s) to be used and it’s mode of operation

2. Compose individual Control Word (CW) for every counter planned to use in step-1

3. Sent these CWs to 8254 by setting A1A0 as 11

4. Calculate the count value to be loaded into individual counter as per the requirement

5. Send these count value to respective counters by specifying its address

6. Send a CLK and an appropriate GATE signal to start the counter

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 173

 8254 – CONTROL WORD FORMAT

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 174

 8254 – CONTROL WORD FORMAT
Example-1: Counter-1 Mode 0, Binary, N= 3A98H. Assume counter-0 address is 40.
MOV AL, 70H
OUT 46H, AL
MOV AL, 98H
OUT 42H, AL
MOV AL, 3AH
OUT 42H, AL

Example-2: Counter-2 Mode 5, BCD, N= 50 (only LSB). Assume counter-0 address is 40

MOV AL, 9BH;
OUT 46H, AL
MOV AL, 50H
OUT 44H, AL

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 175

 8254 – READ OPERATION
 8254 Read Operations (3 possible methods):
1. Simple read operation
2. Counter Latch Command
3. Read-Back Command.
1. Simple Read Operation:
 This operation read the counter after stopping.
 To read the Counter, the CLK input of the selected Counter must be stopped by
using either the GATE input or external logic.
 Otherwise, the count may be in the process of changing when it is read, giving an
undefined result.
 Two I/O read operation are performed by the MPU; The first I/O operation reads
the low order byte, then the second I/O operation reads high order byte.
MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 176
 8254 – READ OPERATION
2. Counter Latch Command:
 This allows reading the contents of the Counters “on
the fly'' without affecting counting in progress.

 The selected Counter's output latch latches the count Example: Read the Counter 1 count value
at the time the Counter Latch Command is received. using counter latch command

 This count is held in the latch until it is read by the ; Latching counter1
CPU (or until the Counter is reprogrammed). MOV DX, C_REG
MOV AL, 40H ; To latch counter 1
 The count is then unlatched automatically and OUT DX, AL
Counter Latch Commands do not affect the
programmed Mode of the Counter in any way. ;Reading counter1
MOV DX, CNTR0
IN AL, DX
MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 177
 8254 – READ OPERATION
3. Read-Back Command:
 This command is used to read several counters at a time hence it eliminates the need
of writing separate counter-latch commands for different counters.
 It allows the user to check the count value, programmed Mode, and current states of
the OUT pin and Null Count flag of the selected counter/ counters.
 The read back command is written to the Control Word Register as per the format
shown in Figure.
 The read-back command may be used to latch multiple counter output latches (OL) by
setting the COUNT bit D5 =0 and selecting the desired counter(s).
 Each counter's latched count is held in the OL until it is read (or the counter is
reprogrammed). The counter is automatically unlatched when read, but other counters
remain latched until they are read.
MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 178
 8254 – READ-BACK COMMAND CONTROL WORD FORMAT

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 179

 8254 – READ OPERATION
 The read-back command may also be used to latch status information of selected
counter(s) by setting STATUS bit D4 = 0.

 Status must be latched to be read; status of a counter is accessed by a read from that
counter.

 Bits D5 through D0 contain the counter's programmed Mode exactly as written in the last
Mode Control Word.

 OUTPUT bit D7 contains the current state of the OUT pin.

 This allows the user to monitor the counter's output via software, possibly eliminating some
hardware from a system.

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 8254 – STATUS REGISTER CONTROL WORD FORMAT

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 181

 8254 – READ-BACK COMMAND CONTROL WORD FORMAT
Example:
; Count and Status latched for count 0
MOV DX, C_REG
MOV AL, 11000010B ; count latched for count 0
OUT DX, AL

; Reading the latched status for count 0

MOV DX, TRM0
IN AL, DX ; Reading Status
MOV AH, AL

; Reading the latched count for counter 0

IN AL, DX ; Reading LSB of counter 0
MOV BL, AL
IN AL, DX ; Reading MSB of counter 0
MOV BH, AL
MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 182
 8254 – MODES OF OPERATION
 The 8254 can be operated in following 6 modes

 Mode 0: Interrupt on terminal count

 Mode 1: Hardware Retriggerable One-Shot

 Mode 2: Rate Generator

 Mode 3: Square Wave Mode

 Mode 4: Software Triggered Mode

 Mode 5: Hardware Triggered Mode

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 183

 8254 – MODES OF OPERATION (Mode 0: Interrupt on terminal count)
 Mode 0 is typically used for generation of accurate time delay.

 After the Control Word is written, OUT is initially low. Once count is loaded, the counter
is decremented after every cycle and when count reaches zero, the OUT goes high.

 The OUT remains high until a new count or command word is loaded. High output used to
interrupt the processor, by setting terminal count.

 GATE =1 enables counting; GATE = 0 disables counting.

 GATE has no effect on OUT. If G becomes a logic 0 in the middle of the count, the
counter will remain stop until G again becomes a logic 1.

 If a new count is written to the Counter, it will be loaded on the next CLK pulse and
counting will continue from the new count.
MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 184
 8254 – MODES OF OPERATION (Mode 0: Interrupt on terminal count)

* N stands for an undefined count.

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 185

 8254 – MODES OF OPERATION (Mode 1: Hardware Retriggerable One-Shot)
 Causes the counter to function as a retriggerable, monostable multivibrator (one-shot).

 OUT is initially (after loading CW) high. Also remain high when count is written.

 When GATE is triggered, the OUT goes low and at the end of count it goes high again,
thus generating a one shot pulse.

 If the GATE input occurs within the duration of counting, the counter is again reloaded
with the count and start counting from the beginning.

 At the rising edge of WR(CW) OUT becomes high.

 At the first falling edge of clock after first rising edge of GATE counter starts counting.

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 186

 8254 – MODES OF OPERATION (Mode 1: Hardware Retriggerable One-Shot)

* N stands for an undefined count.

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 187
 8254 – MODES OF OPERATION (Mode 2: Rate Generator)
 Allows the counter to generate a series of continuous pulses that are one clock pulse wide.

 When a count N is loaded, the OUT stays high until count reaches N-1 and then OUT
goes low for 1 clock period then gets reloaded automatically and this is how pulse gets
generated continuously.

 For example, for a count of 10, the output is a logic 1 for nine clock period and low for 1
clock period. This cycle is repeated until the counter is programmed with a new count or
until G pin is placed at a logic 0 level.

 At the rising edge of WR(CW) OUT becomes high.

 At the first falling edge of clock after first rising edge of WR(LSB), counter starts
counting.
MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 188
 8254 – MODES OF OPERATION (Mode 2: Rate Generator)

* N stands for an undefined count.

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 189
 8254 – MODES OF OPERATION (Mode 3: Square Wave Mode)
 Generates a continuous square wave at the OUT pin connection and Mode 3 is similar to
Mode 2 except for the duty cycle of OUT.
 If the count (N) is even, the output is high for one half (N/2) of the count and low for one
half (N/2) of the count.
 If the count (N) is odd, the output is high for one clocking period longer than it is low i.e.
high for (N+1)/2 clock pulses and low for (N-1)/2 clock pulses.
 For example, if the count is programmed for a count of 5, the output is high for three
clocks and low for two clocks.
 At the rising edge of WR(CW) OUT becomes high.
 At the first falling edge of clock after first rising edge of WR(LSB), counter starts
counting.
MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 190
 8254 – MODES OF OPERATION (Mode 3: Square Wave Mode)

* N stands for an undefined count.

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 191

 8254 – MODES OF OPERATION (Mode 4: Software Triggered Mode)
 Allows the counter to produce a single pulse at the output.

 If count of N is loaded, then OUT will be high for N clock cycles and low for one clock
cycle at the end of count.

 The cycle does not begin until the counter is loaded again.

 G input must be maintained at logic 1 throughout the operation.

 This mode operates as a software triggered one-shot(similar to Mode-1).

 At the rising edge of WR(CW) OUT becomes high.

 At first falling edge of clock after first rising edge of WR(LSB), counter starts counting.
MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 192
 8254 – MODES OF OPERATION (Mode 4: Software Triggered Mode)

* N stands for an undefined count.

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 193
 8254 – MODES OF OPERATION (Mode 5: Hardware Triggered Mode)

 A hardware triggered one-shot that function as mode 4, except that it is started by a

trigger pulse on the G pin instead of by software.

 When the GATE pulse is triggered from low to high the count begins.

 At the end of the count OUT goes low for one clock period.

 This mode is also called HARDWARE TRIGGERED STROBE (RETRIGGERABLE)

 At the rising edge of WR(CW) OUT becomes high.

 At the first falling edge of clock after first rising edge of GATE , counter starts counting.

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 194

 8254 – MODES OF OPERATION (Mode 5: Hardware Triggered Mode)

* N stands for an undefined count.

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 195
 8254 – EXAMPLE PROBLEM

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 196

 8254 – EXAMPLE PROBLEM

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 197

 8254 – EXAMPLE PROBLEM

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 198

 8254 – EXAMPLE PROBLEM

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 199

 8254 – EXAMPLE PROBLEM

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 200

 201

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 201

 INTRODUCTION
 Memory is an integral part of a microprocessor system, and the Memory Interfacing in
8086 is used to access memory to read/write instructions and data stored in memory.
 Memory Types:
1. Random access memory (RAM) – Volatile (Lose all data when power is off)
 Static RAM - Storage cells are made of flips, require 4 or 6 transistor for one bit
 Dynamic RAM - Use MOS capacitors to store bit, require refreshing circuit

2. Read only Memory (ROM) – Non-Volatile (Retain all data even when power is off)
 Programmable ROM (PROM) – One-time programmable memory
 Erasable PROM (EPROM) – Rewrite option is allowed upto 1000 times, time consuming
 Electrically EPROM (EEPROM) – Erasing can be done in byte using electrical method
 Flash Memory – Entire content can be erased in one second
MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 202
 MEMORY STRUCTURE
 A general form of memory device consist of an array of registers, in which each register
has unique address. The size of the memory is N x M, where N is the number of registers
and M is the word length, in number of bits. For example: 2K X 8 means, it has 2048
memory locations which can store 8 bits in each memory location.

Logic diagram of RAM Logic diagram of EPROM

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 203
 STANDARD EPROM ICs

EPROM Density Capacity

ICs (bits) (Bytes)
2716 16K 2Kx8
2732 32K 4Kx8
27C64 64K 8Kx8
27C128 128K 16Kx8
27C256 256K 32Kx8
27C512 512K 64Kx8
27C010 1M 128Kx8
27C020 2M 256Kx8
27C040 4M 512Kx8
EPROM ICs 8Kx8 EPROM IC 27C64 8Kx8 EPROM IC 27C64 Pin Function Table

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 204

 STANDARD SRAM ICs

SRAM Density Capacity

ICs (bits) (Bytes)
6208 8K 1Kx8
6216 16K 2Kx8
6232 32K 4Kx8
6264 64K 8Kx8
62128 128K 16Kx8
62256 256K 32Kx8

SRAM ICs 8Kx8 SRAM IC 6264 8Kx8 SRAM IC 6264 Pin Function Table

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 205

 MEMORY STRUCTURE
 To interface with 8086, the memory device consist of following pins
1. Address Pins – Used to select the memory location within the memory device
 Number of address lines indicates the total memory capacity of the memory device.
 1KB memory = 1 X 1024 = 20 X 210 = 10 address lines
 2KB memory = 2 X 1024 = 21 X 210 = 11 address lines
 4KB memory = 4 X 1024 = 22 X 210 = 12 address lines
 8KB memory = 8 X 1024 = 23 X 210 = 13 address lines
 16 KB memory = 16 X 1024 = 24 X 210 = 14 address lines
 32 KB memory = 32 X 1024 = 25 X 210 = 15 address lines
 64 KB memory = 32 X 1024 = 26 X 210 = 16 address lines

2. Data Pins – Used to transfer data in both direction, referred as D0 to DN. Size of the memory
locations is dependent upon the number of data bits.
3. Control Pins – Used to activate Read/Write operation. For ROM – OE’. For RAM – RD’, WR’
4. Selection Pins - Used to select the memory device or enable, usually it is called chip
select(CS), chip enable (CE) or simply select (S) input.
MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 206
 MEMORY INTERFACING STEPS
 In memory interfacing, 16-bit data line, 20 bit address line , control signals are connected
to corresponding lines of memory IC.

 Steps to interfacing 8086 with memory chips are as follows:

 Step-1: Arrange the available memory chips to obtain 16-bit data bus width. The upper 8-bit
bank is called "odd address memory bank" and the lower 8-bit bank is called "even address
memory bank”.
 Step-2: Connect available memory address lines (“P” address lines) of memory chips with
those of the microprocessor and connect the memory RD’ and WR’ to the corresponding
processor control signals.
 Step-3: The remaining address lines (“N-P” address lines) of the µP, BHE bar, A0 used for
decoding the required chip select signals for the odd and even memory banks. Decoding
circuit can be implemented using a decoder circuit or using basic logic gates.

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 207

 Where the memory device is present in 8086 microprocessor kit?
Timer/Counter Interface (8253)

FRC interface pins

8086 Microprocessor

Programmable peripheral
interface (8255)
Universal Synchronous
EEPROM (ODD & EVEN Asynchronous Receiver
Memory locations) Transmitter (USART) (8251)

USB interface
RAM (ODD & EVEN
Memory locations)

LCD Display RESET INTERRUPT

switch switch
MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 208
 ODD & EVEN MEMORY BANKING IN 8086
 Problem: The 8086 provides a 16-bit data bus hence it is capable of transferring 16 bits
in one cycle but each memory location is only of a byte(8 bits), therefore we need two
cycles to access 16 bits(8 bit each) from two different memory locations.
 Solution: Memory Banking. Through Memory banking, it is possible to access two
consecutive memory locations in one cycle (transfer 16 bits).
 The memory chip is equally divided into two parts(banks). One of the banks contains even
addresses called Even bank and the other contains odd addresses called Odd bank.
 Even bank always gives lower byte So Even bank is also called Lower bank(LB) and Odd
bank is also called Higher bank(HB).
 This banking scheme allows to access two aligned memory locations from both banks
simultaneously and process 16-bit data transfer.
MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 209
 ODD & EVEN MEMORY BANKING IN 8086
 The memory address space of the 8086-based microcomputers has different logical and
physical organizations.
 Logically, memory is implemented as a single 1M × 8 memory bank. The byte-wide storage
locations are assigned consecutive addresses over the range from 00000H through FFFFFH.
 Physically, memory is implemented as two independent 512Kx8 banks: the low (even) bank
and the high (odd) bank

 To distinguish between odd and even bytes, the CPU provides a signal called BHE’ (bus
high enable). BHE’ and A0 are used to select the odd and even byte.

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 210

 INTRODUCTION

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 211

 IMPORTANT POINTS
 For Memory Interfacing in 8086, following important points are to be kept in mind.
 8086 can access 1MB of memory since address bus is 20-bit, but it is not necessary to use full
1MB address space. The capacity of program and data memory depends on the application.
 Generally EPROM is used as a program memory and RAM (or RAMs) as a data memory.
When both, EPROM and RAM are used, the total address space 1MB is shared by them.
 It is not always necessary to select 1 EPROM and 1 RAM. We can have multiple EPROMs and
multiple RAMs as per the requirement of application.
 EPROM/RAM can be placed anywhere in full 1MB address space. But program memory
(EPROM) preferably located from address FFFF0H since reset address of 8086 is FFFF0H.
 It is not necessary to locate EPROM and RAM in consecutive memory For example : If the
mapping of EPROM is from 00000H to 0FFFFH, it is not must to locate RAM from 10000H.
We can locate it anywhere between 10000H and FFFFFH.
MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 212
 EXAMPLE - 1
 Interface two 4Kx8 of EPROMs and two 4Kx8 of RAM chips with 8086 microprocessor.
Assume address maps for RAM and EPROM are continuous. Use decoder for Chip Select.
Solution: After reset, the IP and CS are initialised to form address FFFF0H. Hence, this address must lie in
the EPROM. The address of RAM may be selected any where in the 1MB address space of 8086, but we
will select the RAM address such that the address map of the system is continuous, as shown in table.

Memory IC A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address
4KB EPROM-1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFFFH
(Higher Byte)
1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 FE001H
4KB EPROM-2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 FFFFEH
(Lower Byte)
1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 FE000H
4KB RAM-1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 FDFFFH
(Higher Byte)
1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 FC001H
4KB RAM-2 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 FD00EH
(Lower Byte)
1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FC000H

Memory Map Table

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 213
 EXAMPLE - 1
 Total 8K bytes of EPROM need 13 address lines Ao-A12 (since 213 = 8K). Address lines A13 - A19
are used for decoding to generate the chip select.

 The memory system in this example contains in total four 4K x 8 memory chips. The two 4K x 8
chips of RAM and ROM are arranged in parallel to obtain 16-bit data bus width.

 The BHE’ signal goes low when a transfer is at odd address or higher byte of data is to be
accessed.

 If A0, is 0, i.e. the address is even and is in RAM, then the lower RAM chip is selected indicating 8-
bit transfer at an even address.
 If A, is 1, i.e. the address is odd and is in RAM, the BHE’ goes low, the upper RAM chip is selected,
further indicating that the 8-bit transfer is at an odd address.

 If the selected addresses are in ROM, the respective ROM chips are selected. If at a time A0, and
BHE’ both are 0, both the RAM or ROM chips are selected, i.e. the data transfer is of 16 bits.
MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 214
 EXAMPLE - 1

Decoder Input A2 A1 A0 Memory Bank Selection

Address/BHE’ A13 A0 BHE’
Word Transfer on D0-D15 0 0 0 Even and odd address in RAM
Byte Transfer on D7-D0 0 0 1 Only Even address in RAM
Byte Transfer on D8-D15 0 1 0 Only odd address in RAM
No data transfer 0 1 1 No Bank Selection
Word Transfer on D0-D15 1 0 0 Even and odd address in ROM
Byte Transfer on D7-D0 1 0 1 Only Even address in ROM
Byte Transfer on D8-D15 1 1 0 Only odd address in ROM
No data transfer 1 1 1 No Bank Selection
Memory Chip Selection Table

Memory devices mapped with Physical addresses

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 215

 EXAMPLE - 1

8086 & Memory Chip Interfacing

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 216
 EXAMPLE - 2
 Design an interface between 8086 CPU and two chips of 16K X 8 EPROM and two chips
of 32K X 8 RAM. Select the starting address of EPROM suitably. The RAM address must
start of 00000H. Use basic logic circuit for Chip Select.
Solution: After reset, the IP and CS are initialised to form address FFFF0H. Hence, this address must lie in
the EPROM. RAM requires 16 address lines, (i.e) A0 to A15 address lines are used and EPROM requires 15
address lines, (i.e) A0 to A14 address lines are used.
Memory IC A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address
16KB EPROM-1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFFFH
(Higher Byte)
1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 F8001H
16KB EPROM-2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 FFFFEH
(Lower Byte)
1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F8000H
32KB RAM-1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0FFFFH
(Higher Byte)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 00001H
32KB RAM-2 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0FFFEH
(Lower Byte)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00000H

Memory Map Table

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 217
 EXAMPLE - 2

 Since the address map is not continuous, we don’t need to use

decoder, we can go with simple logic circuit

 In the case of EPROM, A15 to A19 will be used to select CS’

 In the case of RAM, A16 to A19 will be used to select CS’

 Combination of A0, BHE’ and remaining address pins are used

to form chip select signal

Memory devices mapped with Physical addresses

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 218

 EXAMPLE - 2

8086 & Memory Chip Interfacing

MODULE-2 BECE204L – MICROPROCESSORS AND MICROCONTROLLERS 219