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Instruction Set of 8086

An instruction is a binary pattern designed inside a
microprocessor to perform a specific function.
The entire group of instructions that a microprocessor
supports is called Instruction Set.
8086 has more than 20,000 instructions.

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 Classification of Instruction Set
1. Arithmetic Instructions
2. Logical Instruction
3. Data Transfer Instructions
4. Branch and Loop Instruction
5. M/C control Instruction
6. Flag Manipulation Instructions
7. Shift and Rotate Instruction
8. String Instructions
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1. Arithmetic Instructions
 Arithmetic Instructions
ADD Des, Src:
 It adds a byte to byte or a word to word.
 It effects AF, CF, OF, PF, SF, ZF flags.
 Both the source and the destination operands cannot be memory operands.
 Contents of segment registers cannot be added.
 E.g.:
 ADD AL, 74H

 ADD DX, AX

 ADD AX, [BX]

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 Arithmetic Instructions
ADC Des, Src:
 It adds the two operands with CF.
 It effects AF, CF, OF, PF, SF, ZF flags.
 E.g.:
 ADC AL, 74H
 ADC DX, AX
 ADC AX, [BX]

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 Arithmetic Instructions
SUB Des, Src:
 It subtracts a byte from byte or a word from word.(Dst=Dst-Src)
 It affects AF, CF, OF, PF, SF, ZF flags.
 For subtraction, CF acts as borrow flag.
 E.g.:
 SUB AL, 74H
 SUB DX, AX
 SUB AX, [BX]

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 Source operand can be a register, memory or immediate data
 Destination operand may be register or memory
 Both source and destination operands cannot be memory locations
 Arithmetic Instructions
SBB Des, Src:
 It subtracts the two operands and also the borrow from the result.
 It affects AF, CF, OF, PF, SF, ZF flags.
 E.g.:
 SBB AL, 74H
 SBB DX, AX
 SBB AX, [BX]

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 Arithmetic Instructions
 MUL Src:
 It is an unsigned multiplication instruction.
 It multiplies two bytes to produce a word or two words to produce a double word.
 AX = AL * Src (When src is 8 bits)
 DX : AX = AX * Src ( When src is 16 bits)
 This instruction assumes one of the operand in AL or AX.
 Src can be a register or memory location.
 Immediate operand is not used
 Flags-OF, CF will be set if the MSB of byte or word of the result is zero
 Unused bits of destination register is always filled with sign bit
 IMUL Src:
 It is a signed multiplication instruction. 13
 Arithmetic Instructions
 DIV Src:
 It is an unsigned division instruction.
 It divides word by byte or double word by word.
 The operand is stored in AX, divisor is Src and the result is stored
as:
 AH = remainder, AL = quotient (for word/byte) for AX/src
 DX=remainder, AX=quotient (for Double word/word) for DXAX/src

 IDIV Src:
 It is a signed division instruction.
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DIV BL ; AX/BL Q= AL ; R= AH

DIV BX ; DXAX/BX Q=AX ; R=DX

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 Arithmetic Instructions
 CBW (Convert Byte to Word):
 This instruction converts byte in AL to word in AX.
 The conversion is done by extending the sign bit of AL throughout AH.

 CWD (Convert Word to Double Word):

 This instruction converts word in AX to double word in DX : AX.
 The conversion is done by extending the sign bit of AX throughout DX.

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 Arithmetic Instructions
INC Src:
 The operand can be a register or memory location.
 It increments the contents of the register or memory location by 1
 All the condition codes are affected except the carry flag
 Immediate data cannot be the operand
 E.g.: INC AX
 INC [SI] // content of address pointed by si
 INC [5000H] //content of address pointed by 5000h
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 Arithmetic Instructions
DEC Src:
 The operand can be a register or memory location.
 It increments the contents of the register or memory location by 1
 Immediate data cannot be a part of the operand.
 All the condition codes are affected except the carry flag.
 E.g.: DEC AX
DEC [SI]
DEC [5000H]
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 Arithmetic Instructions
 CMP Des, Src:
 It compares the src and the destination .
 The Src and Des can be a constant, register or memory location.
 Both operands cannot be a memory location at the same time.
 The comparison is done simply by internally subtracting the source from
destination. (Dst-Src)
 The value of source and destination does not change, but the flags CF, ZF, SF
are modified to indicate the result.
 Dst>Src CF=0
 Dst<Src,CF=1;
 Dst=Src, ZF=1
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 Arithmetic Instructions
NEG Src:
It creates 2’s complement of a given number.
That means, it changes the sign of a number.

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 Arithmetic Instructions
 DAA (Decimal Adjust after Addition)
 It is used to make sure that the result of adding two BCD numbers is adjusted
to be a correct BCD number.
 It only works on AL register.

 For Subtraction : DAS (Decimal Adjust after Subtraction)

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2. Logical Instructions

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 Logical Instructions
 NOT Src:
 It complements each bit of Src to produce 1’s complement of the specified
operand.
 The operand can be a register or memory location.
 e,.g NOT AX

Content of 5000h complemented

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 Logical Instructions
 AND Des, Src:
 It performs AND operation of Des and Src.
 Src can be immediate number, register or memory location.
 Des can be register or memory location.
 Both operands cannot be memory locations at the same time.
 CF and OF become zero after the operation.
 PF, SF and ZF are updated.

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 Logical Instructions
 OR Des, Src:
 It performs OR operation of Des and Src.
 Src can be immediate number, register or memory location.
 Des can be register or memory location.
 Both operands cannot be memory locations at the same time.
 CF and OF become zero after the operation.
 PF, SF and ZF are updated.

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 Logical Instructions
 XOR Des, Src:
 It performs XOR operation of Des and Src.
 Src can be immediate number, register or memory location.
 Des can be register or memory location.
 Both operands cannot be memory locations at the same time.
 CF and OF become zero after the operation.
 PF, SF and ZF are updated.

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 Logical Instructions
 TEST Des, Src:
 It performs AND operation of Des and Src.
 Src can be immediate number, and src/Des can be register or memory
location.
 It is Non-Destructive And means Dest is not modified only flags are affected.
 Both operands cannot be memory locations at the same time.
 CF and OF become zero after the operation.
 PF, SF and ZF are updated.

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2. Data Transfer Instructions

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 Data Transfer Instructions
 MOV Des, Src:
 It is used to copy the content of Src to Des
 Src operand can be register, memory location or immediate operand.
 Des can be register or memory operand.
 Both Src and Des cannot be memory location at the same time.
 E.g.:
 MOV CX, 037A H
 MOV AL, BL
 MOV BX, [0301 H]

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 Data Transfer Instructions
 PUSH Operand:
 It pushes the operand into
top of stack.
 E.g.: PUSH AX

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 Data Transfer Instructions
 POP Des:
 It pops the operand from
top of stack to Des.
 Des can be a general
purpose register, segment
register (except CS)
 E.g.: POP AX

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 Data Transfer Instructions
 XCHG Des, Src:
 This instruction exchanges Src with Des.
 It cannot exchange two memory locations directly.
 E.g.: XCHG DX, AX

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 Data Transfer Instructions
 IN Accumulator, Port Address:
 It transfers the operand from specified port to accumulator register.

 E.g.: IN AX, 0028 H

 OUT Port Address, Accumulator:

 It transfers the operand from accumulator to specified port.

 E.g.: OUT 0028 H, AX

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 Data Transfer Instructions
LEA Register, Src:
It loads a 16-bit register with the offset address of the data
specified by the Src.
E.g.: LEA BX, [DI] // this instruction loads the contents
of DI into the BX register.

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 Data Transfer Instructions
 LDS Des, Src:
 It loads 32-bit pointer from memory source to destination register and DS.
 This instruction Copies the word at the lower memory address to the Des reg
and the word at the higher address to the segment reg i.e. DS.
 E.g.: LDS BX, [1000 H]

1000 11
1001 22 11 22 33 44
1002 33
1003 44 BX DS

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 Data Transfer Instructions
 LES Des, Src:
 It loads 32-bit pointer from memory source to destination register and ES.
 The Word is placed in the destination register and the segment is placed in
ES.
 This instruction is very similar to LDS except that it initializes ES instead of
DS.
 E.g.: LES BX, [0300 H]

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 Data Transfer Instructions
 LAHF:
LAHF
 It copies the lower byte of flag register to AH. AH F

 SAHF:
 It copies the contents of AH to lower byte of flag register.

 PUSHF:
 Pushes flag register to top of stack.

 POPF:
 Pops the stack top to flag register.

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 3. Branch/Program Execution Transfer Instructions
 These instructions cause change in the sequence of the execution of
instruction.
 This change can be a conditional or sometimes unconditional.
 The conditions are represented by flags.

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 Branch Instructions
 CALL Des:
 This instruction is used to call a subroutine or function or procedure.
 The address of next instruction after CALL is saved onto stack.

 RET:
 It returns the control from procedure to calling program.
 Every CALL instruction should have a RET.

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 Branch Instructions
 JMP Des:
 This instruction is used for unconditional jump from one place to another.

 Jxx Des (Conditional Jump):

 All the conditional jumps follow some conditional statements or any
instruction that affects the flag.

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 Mnemonic Meaning Jump Condition

JA Jump if Above CF = 0 and ZF = 0

JAE Jump if Above or Equal CF = 0 Conditional Jump

JB Jump if Below CF = 1 Table
JBE Jump if Below or Equal CF = 1 or ZF = 1

JC Jump if Carry CF = 1

JE Jump if Equal ZF = 1

JNC Jump if Not Carry CF = 0

JNE Jump if Not Equal ZF = 0

JNZ Jump if Not Zero ZF = 0

JPE Jump if Parity Even PF = 1

JPO Jump if Parity Odd PF = 0

JZ Jump if Zero ZF = 1 48
 Loop Instructions
 Loop Des:
 This is a looping instruction.
 The number of times looping is required is placed in the CX register.
 With each iteration, the contents of CX are decremented.
 ZF is checked whether to loop again or not.

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4. Machine Control Instructions
 Machine Control Instructions
HLT (Halt) :- It causes the processor to enter in to the halt state. It can be
stopped by INTR,NMI or RESET pin
NOP (No Operation) :- It causes the processor to enter in to the wait state for 3
Clock cycles.
WAIT :- It causes the processor to enter in to the idle state. Can be stopped by
TEST pin (Test’=1; idle state)
LOCK :- This instruction prevents other processors to take the control of
shared resources. For e.g LOCK IN AL,80H
ESC:- escape to external devices like co processor

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5. Flag Manipulation Instructions
 Flag Manipulation Instructions
 STC:
 It sets the carry flag to 1.

 CLC:
 It clears the carry flag to 0.

 CMC:
 It complements the carry flag.

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 Flag Manipulation Instructions
 STD:
 It sets the direction flag to 1.
 If it is set, string bytes are accessed from higher memory address to lower
memory address.

 CLD:
 It clears the direction flag to 0.
 If it is reset, the string bytes are accessed from lower memory address to
higher memory address.
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 Flag Manipulation Instructions
 STI:
 It sets the Interrupt flag to 1.

 CLI:
 It clears the Interrupt flag to 0.

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6. Shift And Rotate Instructions
 Shift And Rotate Instructions
 SHL/SAL Des, Count:
 It shift bits of byte or word left, by count.
 It puts zero(s) in LSBs.
 MSB is shifted into carry flag.
 If the number of bits desired to be shifted is 1, then the immediate number 1
can be written in Count.
 However, if the number of bits to be shifted is more than 1, then the count is
put in CL register. And recent bit to the CF (Carry flag)

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 Shift And Rotate Instructions
 SHR/SAR Des, Count:
 It shift bits of byte or word right, by count.
 It puts zero(s)(for SHL) and Sign bit (for SAL) in MSBs.
 LSB is shifted into carry flag.
 If the number of bits desired to be shifted is 1, then the immediate number 1
can be written in Count.
 However, if the number of bits to be shifted is more than 1, then the count is
put in CL register. And recent bit to the CF (Carry flag)

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 Shift And Rotate Instructions
 ROL Des, Count:
 It rotates bits of byte or word left, by count.
 LSB is transferred to MSB and also to CF.
 If the number of bits desired to be shifted is 1, then the immediate number 1
can be written in Count.
 However, if the number of bits to be shifted is more than 1, then the count is
put in CL register. And recent bit to the CF (Carry flag)

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 Shift And Rotate Instructions
 ROR Des, Count:
 It rotates bits of byte or word right, by count.
 MSB is transferred to LSB and also to CF.
 If the number of bits desired to be shifted is 1, then the immediate number 1
can be written in Count.
 However, if the number of bits to be shifted is more than 1, then the count is
put in CL register. And recent bit to the CF (Carry flag)

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 Shift And Rotate Instructions
 RCR Des, Count: // Rotate right through carry
 It rotates bits of byte or word right, by count.
 LSB to MSB then MSB is transferred to CF and CF to LSB.
 If the number of bits desired to be shifted is 1, then the immediate number 1
can be written in Count.
 However, if the number of bits to be shifted is more than 1, then the count is
put in CL register. And recent bit to the CF (Carry flag)

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 Shift And Rotate Instructions
 RCL Des, Count:
 It rotates bits of byte or word left, by count.
 MSB to LSB then LSB is transferred to CF and CF to MSB.
 If the number of bits desired to be shifted is 1, then the immediate number 1
can be written in Count.
 However, if the number of bits to be shifted is more than 1, then the count is
put in CL register. And recent bit to the CF (Carry flag)

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7. String Manipulation Instructions
 String Manipulation Instructions
 There are very strong set of string instructions in 8086.
 By using these string instructions, the size of the program is considerably
reduced.
 How to copy data from one segment to another?
 With 2 instructions , we can transfer upto 64 KB of data

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8086 Microprocessor

String Manipulation Instructions

String- String is a sequence of bytes stored sequentially in a memory location
( data Segment and Extra Segment)
 The source string is pointed by SI in DS
The destination string is pointed by DI in ES
When ever some instruction must be repeated, the count value must be loaded
in CX register. CX register size=16 bits. So we can transfer upto 64 KB of data

Depending on the status of DF, SI and DI registers are automatically updated.

DF = 0; SI and DI are incremented by 1 for byte and 2 for word.; Instruction
used:CLD

DF = 1;SI and DI are decremented by 1 for byte and 2 for word. Instruction used:
STD
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 String Manipulation Instructions
 MOVS(MOVSB / MOVSW):
 It causes moving of byte or word from data segment to extra segment.
 In this instruction, the source string is in Data Segment referred by DS:SI and
destination string is in Extra Segment referred by ES:DI.
 SI points to data segment; DI points to ES
 SI increment /decrement depends on DF
 REP MOVSB // moves byte of data from DS to ES and repeats till CX
becomes 0

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 String Manipulation Instructions
 LODS(LODSB / LODSW):
 In this instruction, the source string is in Data Segment referred by DS:SI
transferred to Accumulator.
 lodsb
AL
 lodsw DS:SI

SI points to Data segment

DF decides direction

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 String Manipulation Instructions
 STOS (STOSB / STOSW):
In this instruction, the string is in Extra Segment referred by ES:DI transferred to
Accumulator.
 stosb
AL
ES:DI
 stosw

DI points to Extra segment

DF decides direction

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 String Manipulation Instructions
 CMPS (CMPSB/CMPSW)
 It compares the bytes or words of DS with ES.
 SI points to DS, DI points to ES
 Direction flag decides the direction
 If both strings are completely equal , ZF is set

 SCAS (SCASB/SCASW)
 It compares the AL(byte) or AX(word) with data of extra segment
 DI points to ES
 Direction flag decides the direction
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 String Manipulation Instructions
 REP (Repeat):
 This is an instruction prefix.
 It causes the repetition of the instruction until CX becomes zero.
 E.g.: REP MOVSB
 It copies byte by byte contents.

 REP repeats the operation MOVSB until CX becomes zero.

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 Write an ALP to find the sum of corresponding elements of two
arrays
• MOV CX, 0005H
• MOV AX, 2000H
• MOV DS, AX
• MOV SI, 0100H
• MOV DI,0200H
• NEXT: MOV AL,[SI]
• ADD AL,[DI]
• MOV [SI], AL
• INC SI
• INC DI
• LOOP NEXT
• HLT

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Write an ALP to find the sum of N Consecutive numbers
mov si,2000h
mov cl,[si]
mov al,00h
mov bl,01h
l1:add al,bl
inc bl
dec cl
jnz l1
mov di,2002h
mov [di],ax
hlt 82
• Cmp-> dst operand-src operand
• If src operand > dst operand Carry flag is set

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 Factorial of a number
mov ax,05h
mov cx,ax
dec cx
back: mul cx
dec cx
jnz back
• mov dx,ax
• hlt

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 Descending order
• MOV AX, 2000H
• MOV DS,AX
• MOV CL,05
• DEC CL
• Z:MOV SI,0000H
• MOV DL,CL
• Y:MOV AL,[SI]
• INC SI
• MOV BL,[SI]
• CMP AL,BL
• JGE X
• MOV [SI],AL
• DEC SI
• MOV [SI],BL
• INC SI
• X: DEC DL
• JNZ Y
• LOOP Z
85
• HLT
 Ascending order
MOV AX, 2000H
MOV DS,AX
MOV CL,05
DEC CL
Z: MOV SI,0000H
MOV DL,CL
Y: MOV AL,[SI]
INC SI
MOV BL,[SI]
CMP AL,BL
JLE X
MOV [SI],AL
DEC SI
MOV [SI],BL
INC SI
X: DEC DL
JNZ Y
LOOP Z
HLT 86
• Data segment
• arr db 04,03,02,01,01
• data ends mov cx,0005h
• code segment
• assume cs:code,ds:data mov si,0100h
• start: mov dx,cx
• mov ax, data
• mov ds,ax mov bx,0000h
• mov cx,0005h l1:mov al,[si]
• mov dx,cx
• mov bx,0000h
mul al
• l1:mov al,arr[si] add bx,ax
• mul al
• add bx,ax
mov [si],al
• mov arr[si],al inc si
• inc si
• loop l1
loop l1
• mov ax,bx mov ax,bx
• div dl
div dl
• Mov ds:[0100h],ax
• hlt mov [si],ax
• code ends hlt 87
• end
8255- Programmable Peripheral Interface
 Need for 8255
• Very limited i/o handling capabilities.
• Cannot connect more devices to 8086.
• Features:
• Three 8 bit ports
 Features of 8255
• Also known as Programmable peripheral input-output port.
• It can work with various microprocessors like 8085,8086 etc.
• 8255 is designed to increase input output handling capability
• Has three 8 bit bidirectional IO ports. (24 input output lines)
• These can be programmed in two groups of 12 lines each or three groups of 8 lines
each.
• Has three IO modes
– Simple IO mode
– Handshake IO mode
– Bidirectional Handshake IO mode
• Handshake: Since clk is not an integral part of 8255, for synchronisation, handshake
is needed
• Has BSR mode whereby individual bits of port c can be altered
PIN DIAGRAM OF 8255
 Block diagram of 8255
It takes the control signals from the control word and forwards it to Ports

8086 can reset, Clear the CWR, All ports are set as input ports by default
High imp state; removes the port from ckt
 Modes of operation of 8255
• Two modes of operation
• IO Mode- 8255 ports work as programmable io ports
– Mode 0
– Mode 1
– Mode 2

• BSR Mode- only port C can be used to set / reset individual

bits.
 Control word of 8255 Which mode ?
• 8 bits of CW; When A0A1=11; CWR is selected
Which port?
• CW is written through D0-D7;
• It defines the working of the IO ports of 8255
 BSR Mode of 8255
• BSR Mode- Bit Set Reset Mode-Works with Port C
 I/O Mode- Mode 0
• Simple IO Mode
• Provides simple input / output capability to each of the three modes
• Data can be read or written into these ports after initialisation
Features:
4 ports available-Port A, Port B, Port CU(4 bits) & Port CL(4 bits) available
Any port can be used as input port/output port
A maximum of four ports are available so that overall 16 I/O configuration are
possible.
Output ports are latched
Input ports are not latched
Interrupt Handling capability is not provided
DIP Switches, Hexa key pad, LEDs, 7 segment LEDs
 I/O Mode- Mode 1
• Strobed I/O Mode
Features:
Two Groups
Each group has 8 bits for data
transfer and one 4 bits for control

Data port can be used as input

PC3-PC5 provides the handshake
port or as output port
signals for port A.
It controls the input output
Both inputs and outputs are action of port A
latched

PC0-PC2 & PC3-PC5 are used to PC0-PC2 provides the

generate the control signals handshake signals for port B.
It controls the input output
action of port B
PC6, PC7 – used as independent
data lines
Interrupt handling is supported
 I/O- Mode 2
• Strobed Bi directional IO
• Bidirectional 8 bit port with handshake
• Communicates with a peripheral device on a 8 bit data bus.
• Handshaking provided for synchronisation between the data transmitter and
receiver
• Rd’ and Wr’ decides whether the port operates in input /output mode.
• Interrupt handling is supported
Features:
• The Single 8 bit port in group A is available
• The 8 bit port is bidirectional and additionally a 5 bit control port is available
• Three io lines are available PC0-PC2
• Inputs and outputs are both latched
• The 5 bit control port C(PC3-PC7) is used for generating /accepting handshake signals
for the 8 bit data transfer on port A
 Example-1
• Interface an 8255 with 8086 to work as an I/O port. Initialize
Port A & C as O/P port and Port B as I/P port. Port A address
should be 0740H. Assume that switches(sw0-sw7) are
connected in Port B. LEDs are connected to Port A. Write a
program to display the sensed switch pattern in LED. Display
the number of switches ON to the Port C lower part.
• Step:1—Control Word– 82H
• Out of A0-A15:--Ao& A1 are directly used by 8255 for deriving
the port address and control word register value.
• A3-A15 are used for decoding address.
• 8086 is used in maximum mode.so active low IORD and IOWR
are readily available.
 Additional Programs
• Write an ALP to find the number of odd numbers in the given
array of 8 bit hexadecimal numbers

108
• mov cl,05h
• Mov si,0100h
• next:Mov ax,[si]
• ror ax,1
• JNC xx
• inc bx
• xx:inc si
• Dec cl
• jnz next
• hlt

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• Write an ALP to find the number of even numbers in the given
array of 8 bit hexadecimal numbers

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• mov cl,05h
• Mov si,0100h
• next:Mov ax,[si]
• ror ax,1
• JC xx
• inc bx
• xx:inc si
• Dec cl
• jnz next
• hlt

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• Write an ALP to find the sum of even numbers in the given
array of 8 bit hexadecimal numbers

112
• mov cl,05h
• Mov si,0100h
• next:Mov ax,[si]
• ror ax,1
• JC xx
• add dl,[si]
• inc bx
• xx:inc si
• Dec cl
• jnz next
• hlt

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• Write an ALP to find the sum of odd numbers in the given
array of 8 bit hexadecimal numbers

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• mov cl,05h
• Mov si,0100h
• next:Mov al,[si]
• ror ax,1
• JNC xx
• inc bx
• add dl,[si]
• xx:inc si
• Dec cl
• jnz next
• hlt

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• Write an ALP to perform one byte bcd addition/bcd
subtraction
• Determine whether the given number is odd parity or even
parity.
• Write a program to convert a 16 bit binary number to a BCD
number
• Square of a given array of numbers

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8254- programmable Interval timer
 Need for timer
• Generation of delay- pgms were executed- up was busy
• Accuracy of the delay
Features of 8254- Programmable Interval timer
• Can work with various microprocessors
• Can be used to generate hardware delay
• Hardware delay is more useful than software delay as microprocessor is
not actively involved in generating delay. So when delay is produced by
8254 at that time microprocessor is free to execute other programs.
• Can be used as a real time clk or for square wave generation
• 8254 has three independent 16 bit down counters
• These counters can take count in BCD or in binary
• Once the counter finishes count(required delay), 8254 interrupts the
microprocessor
 Block diagram of 8254
Bidirectional, exchanges data with system bus of 8086

Rd and wr data on Do to D7

A0, A1- Selection of counters and control word

CS- Selection of 8254 chip
 Operating modes of 8254
• Six modes of operation
• Mode 0(Interrupt On Terminal Count)
• Mode 1( Programmable monoshot)
• Mode 2(Rate generator)
• Mode 3(Square wave generator)
• Mode 4(Software Triggered Strobe)
• Mode 5(Hardware Triggered Strobe)
• Each timer requires a clock input.
• The counters are negative edge triggered down counter, i.e.,
whenever there is HIGH to LOW transition at the CLK input, the
count value is decremented by 1.
• The down counting is controlled by the gate. The output pin of
the timer may be used to generate different signals, e.g., an
interrupt request signal in the interrupt related modes.
GATE acts as the trigger input
 Reloaded with n value

A strobe signal is generated after 3 clock pulses

Count value can be reset and count generation starts all over again

Gate input is used for reset

Write operation acts as trigger

Strobe produced

If gate is low, counting can be delayed

 strobe

retriggerable

Gate is used as the trigger input; After GATE goes high , counting starts
Static RAM Interfacing

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