COMPUTER ORGANISATION & ARCHITECTURE LAB (BCS-352)

EXPERIMENT NO: 1

AIM: - Implementing HALF ADDER, FULL ADDER using basic logic gates.

APPARATUS REQUIRED: Power supply, IC’s, Digital Trainer, Connecting leads.

BRIEF THEORY: We are familiar with ALU, which performs all arithmetic and logic operation
but ALU doesn’t perform/ process decimal no’s. They process binary no’s.

Half Adder: It is a logic circuit that adds two bits. It produces the O/P, sum & carry. The Boolean
equation for sum & carry are:
SUM = A + B
CARRY = A. B
Therefore, sum produces 1 when A&B are different and carry is 1when A&B are 1. Application
of Half adder is limited.

Full Adder: It is a logic circuit that can add three bits. It produces two O/P sum & carry. The
Boolean Equation for sum & carry are:
SUM = A + B + C
CARRY = A.B + (A+B) C
Therefore, sum produces one when I/P is containing odd no’s of one & carry is one when there
are two or more one in I/P.

LOGIC DAIGRAM:

Half Adder Full Adder

PROCEDURE:
(a) Connect the ckt. as shown in fig. For half adder.
(b) Apply diff. Combination of inputs to the I/P terminal.
(c) Note O/P for Half adder.
(d) Repeat procedure for Full wave.
(e) The result should be in accordance with truth table.
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OBSERVATION TABLE:

HALF ADDER:

INPUTS OUTPUT
A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

FULL ADDER:
INPUTS OUTPUTS
A B C S CARRY
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

RESULT: The Half Adder & Full Adder circuits are verified.

PRECAUTIONS:
1) Make the connections according to the IC pin diagram.
2) The connections should be tight.
3) The Vcc and ground should be applied carefully at the specified pin only.
COMPUTER ORGANISATION & ARCHITECTURE LAB (BCS-352)

EXPERIMENT NO. 2
AIM: Implementing Binary -to -Gray, Gray -to -Binary code conversions.

APPARATUS REQUIRED: Digital board DB06, DC Power Supply +5 V from external source
or ST2611 Digital lab, Digital Multimeter or Digital Lab ST2611.

BRIEF THEORY: The availability of a large variety of codes for the same discrete elements of
information results in the use of different codes by different digital system. It is sometimes
necessary to use the output of one system as the input to another. A conversion circuit must be
inserted between the two systems if each uses different codes for the same information. Thus, a
code converter is a circuit that makes the two systems compatible even though each uses a
different binary code.

Logic diagram & Truth Table:

(Logic 1 = +5V & Logic 0= GND)

Binary to Gray Code Gray to Binary Code

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Binary Code Gray Code

RESULT: -
Procedure:

1. Connect +5 V and ground to their indicated position on experiment board from external
DC power supply or from DC power block.
2. Connect inputs B0, B1, B2, B3 as per truth table 2 to binary to gray
code Converter.
3. Switch ON the power supply.
4. Observe output G0, G1, G2, G3 on multimeter or on LED Display.
5. Repeat above step for remaining inputs and prove truth table.
6. Repeat above steps for gray to binary code converter and prove truth table.
COMPUTER ORGANISATION & ARCHITECTURE LAB (BCS-352)

EXPERIMENT NO. 3

AIM: Implementing 3–8-line DECODER

APPARATUSREQUIRED: Power Supply, Digital Trainer, Connecting Leads.

3-8 LINE DECODER

BRIEF THEORY:
LINE DECODER is designed to be used in high-performance memory-decoding or data-
routing applications requiring very short propagation delay times. In high-performance
memory systems, this decoder can be used to minimize the effects of system decoding.
When employed with high-speed memories utilizing a fast enable circuit, the delay times of
this decoder and the enable time of the memory are usually less than the typical access time
of the memory. This means that the effective system delay introduced by the decoder is
negligible. The conditions at the binary-select (A, B, C) inputs and the three enable (G1, G2A,
G2B) inputs select one of eight output lines. Two active-low and one active-high enable
inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can
be implemented without external inverters and a 32-line decoder requires only one inverter. An
enable input can be used as a data input for demultiplexing applications.

PIN CONFIGURATION:
COMPUTER ORGANISATION & ARCHITECTURE LAB (BCS-352)

OBSERVATION TABLE:

LOGIC SYMBOLS:

Logic diagram of 3-8 line decoders

LOGIC DIAGRAM:
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Logic diagram of 3–8-line decoders

PRECAUTIONS:
1) Make the connections according to the IC pin diagram.
2) The connections should be tight.
3) The Vcc and ground should be applied carefully at the specified pin only.
RESULT: - It is seen that all the observation tables are verified.

EXPERIMENT NO. 4

AIM: Implementing 4x1 and 8x1 MULTIPLEXERS.

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APPARATUSREQUIRED: Power Supply, Digital Trainer, Connecting Leads,

IC’s74153(4x1 multiplexer).

BRIEF THEORY:

MULTIPLEXER: Multiplexer generally means many into one. A multiplexer is a circuit with
many Inputs but only one output. By applying control signals we can steer any input to the
output .The fig. (1) Shows the general idea. The ckt. has n-input signal, control signal & one
output signal. Where 2n = m. One of the popular multiplexer is the 16 to 1 multiplexer, which has
16 input bits, 4 control bits & 1 output bit.

PIN CONFIGURATION:
IC 74153 (4x1 multiplexer)

(4x8 multiplexer)
COMPUTER ORGANISATION & ARCHITECTURE LAB (BCS-352)

PIN NAMES:

S0–S2 Select Inputs

E Enable (Active LOW) Input

I0–I7 Multiplexer Inputs

Z Multiplexer Output (Note b)

Z’ Complementary Multiplexer Output

LOGIC DIAGRAM:

Multiplexer (4x1) IC 74153

COMPUTER ORGANISATION & ARCHITECTURE LAB (BCS-352)

Multiplexer (8x1) IC 74153

OBSERVATION TABLE:

Truth Table of multiplexer (4x1) IC 74153

COMPUTER ORGANISATION & ARCHITECTURE LAB (BCS-352)

Truth Table of multiplexer (8x1) IC 74153

PROCEDURE:
1. Fix the IC's on the bread board &give the input supply.
2. Make connection according to the circuit.
3. Give select signal and strobe signal at respective pins.
4. Connect +5 V Vcc supply at pin no 24 & GND at pin no 12.
5. Verify the truth table for various inputs.

RESULT: Verify the truth table of multiplexer for various inputs.

COMPUTER ORGANISATION & ARCHITECTURE LAB (BCS-352)

EXPERIMENT NO. 5
AIM: Verify the excitation tables of various Flip-Flops.
APPARATUS REQUIRED: IC’ S 7400, 7402 Digital Trainer & Connecting leads.

BRIEF THEORY:

• RS FLIP-FLOP: There are two inputs to the flip-flop defined as R and S. When I/Ps R = 0
and S = 0 then O/P remains unchanged. When I/Ps R = 0 and S = 1 the flip-flop is
switches to the stable state where O/P is 1 i.e. SET. The I/P condition
is R = 1 and S = 0 the flip-flop is switched to the stable state where O/P is 0 i.e. RESET.
The I/P condition is R = 1 and S = 1 the flip-flop is switched to the stable state where O/P
is forbidden.

• JK FLIP-FLOP:For purpose of counting, the JK flip-flop is the ideal element to use. The
variable J and K are called control I/Ps because they determine what the flip- flop does
when a positive edge arrives. When J and K are both 0s, both AND gates are disabled
and Q retains its last value.

• D FLIP –FLOP: This kind of flip flop prevents the value of D from reaching the Q
output until clock pulses occur. When the clock is low, both AND gates are disabled
D can change value without affecting the value of Q. On the other hand, when the
clock is high, both AND gates are enabled. In this case, Q is forced to equal the value
of D. When the clock again goes low, Q retains or stores the last value of D. a D flip
flop is a bistable circuit whose D input is transferred to the output after a clock pulse
is received.

• T FLIP-FLOP: The T or "toggle" flip-flop changes its output on each clock

edge, giving an output which is half the frequency of the signal to the T input. It is
useful for constructing binary counters, frequency dividers, and general binary
addition devices. It can be made from a J-K flip-flop by tying both of its inputs high.

CIRCUIT DIAGRAM:

SR Flip Flop D Flip Flop

COMPUTER ORGANISATION & ARCHITECTURE LAB (BCS-352)

JK Flip Flop T Flip Flop

PROCEDURE:
1. Connect the circuit as shown in figure.
2. Apply Vcc & ground signal to every IC.
3. Observe the input & output according to the truth table.

TRUTH TABLE: SR F

LIP FLOP:
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RESULT: Truth table is verified on digital trainer.

PRECAUTIONS:

1) Make the connections according to the IC pin diagram.

2) The connections should be tight.
3) The Vcc and ground should be applied carefully at the specified pin only.
COMPUTER ORGANISATION & ARCHITECTURE LAB (BCS-352)

EXPERIMENT NO. 6

AIM: Design of an 8-bit Input/ Output system with four 8-bit Internal Registers.

BRIEF THEORY:
A universal shift register is an integrated logic circuit that can transfer data in three different
modes. Like a parallel register it can load and transmit data in parallel. Like shift registers it can
load and transmit data in serial fashions, through left shifts or right shifts. In addition, the
universal shift register can combine the capabilities of both parallel and shift registers to
accomplish tasks that neither basic type of register can perform on its own. For instance, on a
particular job a universal register can load data in series (e.g. through a sequence of left shifts)
and then transmit/output data in parallel.
Universal shift registers, as all other types of registers, are used in computers as memory
elements. Although other types of memory devices are used for the efficient storage of very large
volume of data, from a digital system perspective when we say computer memory we mean
registers. In fact, all the operations in a digital system are performed on registers. Examples of
such operations include multiplication, division, and data transfer.
In order for the universal shift register to operate in a specific mode, it must first select the mode.
To accomplish mode selection the universal register uses a set of two selector switches, S1 and
S0.
Operating Mode S1 S0
Locked 0 0
Shift-Right 0 1
Shift-Left 1 0
Parallel Loading 1 1
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LOGIC DIAGRAM:

The transfer of information from a bus into one of many destination registers can be
accomplished by connecting the bus lines to the inputs of all destination registers and activating
the load control of the particular destination register selected. The symbolic statement for a bus
transfer may mention the bus or its presence may be implied in the statement. When the bus is
includes in the statement, the register transfer is symbolized as follows:
BUS ← C, R1 ← BUS

The content of register C is placed on the bus, and the content of the bus is loaded into register
R1 by activating its load control input. If the bus is known to exist in the system, it may be
convenient just to show the direct transfer.
R1 ← C

From this statement the designer knows which control signals must be activated to produce
the transfer through the bus.
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PRECAUTIONS:

1) Make the connections according to the IC pin diagram.

2) The connections should be tight.
COMPUTER ORGANISATION & ARCHITECTURE LAB (BCS-352)

EXPERIMENT NO. 7
AIM: Design of an 8-bit ARITHMETIC LOGIC UNIT.

BRIEF THEORY:
The arithmetic micro-operations can be implemented in one composite arithmetic circuit. The
basic component of an arithmetic circuit is the parallel adder. By controlling the data inputs to
the adder, it is possible to obtain different types of arithmetic operations. It has four full-adder
circuits that constitute the 4-bit adder and four multiplexers for choosing different operations.
There are two 4-bit inputs A and B and a 4-bit output D. The four inputs from A go directly to
the X inputs of the binary adder. Each of the for inputs from B are connected to the data inputs of
the multiplexers. The multiplexer’s data inputs also receive the complement of B. The other two
data inputs are connected to logic-0 ad logic -1. Logic-0 is fixed voltage value (0 volts for TTL
integrated circuits) and the logic-1 signal can be generated through an inverter whose input is 0.
The four multiplexers are controlled by two selection inputs, S1 and S0. The input carry Cin goes
to the carry input of the FA in the least significant position. The other carries are connected from
one stage to the next. The output of the binary adder is calculated from the following arithmetic
sum:
D = A + Y + Cin

Where A is the 4-bit binary number at the X inputs and Y is the 4-bit binary number at the Y
inputs of the binary adder. Cin is the input carry, which can be equal to 0 or 1. Note that the
symbol + in the equation above denotes an arithmetic plus. By controlling the value of Y with
the two selection inputs S1 and S0 ad making Cin equal to 0 or 1, it is possible to generate the
eight arithmetic micro operations

When S1 S0 = 00, the value of B is applied to the Y inputs of the adder. If Cin = 0, the output
D = A + B. If Cin = 1, output D = A + B + 1. Both cases perform the add microoperation with or
without adding the input carry.
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When S1 S0 = 01, the complement of B is applied to the Y inputs of the adder. If Cin = 1, then
D =A +B+ 1. This produces A plus the 2’s complement of B, which is equivalent to a subtract
with borrow, that is, A – B – 1.

LOGIC DIAGRAM:

When S1S0 = 10, the input from B are neglected, and instead, all 0’s are inserted into the Y
inputs. The output becomes D = A + 0 +Cin. This gives D = A when Cin = 0 and D = A +1 when
Cin =1. In the first case we have a direct transfer from input A to output D. In the second case,
the value of A is incremented by 1.
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When S1 S0 = 11, all 1’s are inserted into the Y inputs of the adder to produce the decrement
operation D = A –1 when Cin. This is because a number with all 1’s is equal to the 2’s
complement of 1 (the 2’s complement of binary 0001 is 1111). Adding a number A to the 2’s
complement of 1 produces F = A +2’s complement of 1 = A – 1. When Cin = 1, then
D = A – 1 + 1 =A, which causes a direct transfer from input A to output D. Note that the
microoperation D = A is generated twice, so there are only seven distinct microoperations in the
arithmetic circuit.

IC -7432 (OR Gate)

PIN DIAGRAM

OBSERVATION TRUTH TABLE:-

A B Y=A+B

0 0

0 1

1 0

1 1

IC-7408(AND Gate)
COMPUTER ORGANISATION & ARCHITECTURE LAB (BCS-352)

PIN DIAGRAM

OBSERVATION TRUTH TABLE:-

A B Y=A.B

0 0

0 1

1 0

1 1

I-C 7404 (NOT Gate)

PIN DIAGRAM
COMPUTER ORGANISATION & ARCHITECTURE LAB (BCS-352)

OBSERVATION TRUTH TABLE:-

A Y’

IC-7402(NOR Gate)

PIN DIAGRAM

OBSERVATION TRUTH TABLE:-

A B Y=(A+B)’

0 0

0 1

1 0

1 1
COMPUTER ORGANISATION & ARCHITECTURE LAB (BCS-352)

IC-7400(NAND Gate)

PIN DIAGRAM

OBSERVATION TRUTH TABLE:-

A B Y=(A.B)’

0 0

0 1

1 0

1 1

RESULT: ------------------------------------------

PRECAUTIONS: -
1. IC pins must be properly identified.
2. All the connections must be tight.
3. Supply voltage must not exceed +5 volts.
4. Connection must be made with power supply off.
COMPUTER ORGANISATION & ARCHITECTURE LAB (BCS-352)

EXPERIMENT NO. 8
AIM: Design the data path of a computer from its register transfer language description.

Apparatus Required: -

S.No. Instrument Required Quantity Specification

01 8085 based microprocessor kit 01 8085

02 Key Board 01

BRIEF THEORY:
This datapath circuit to be built requires several components that we will design and implement
and test individually. To facilitate successful implementation, verification and documentation of
complex designs, one should proceed in an incremental, modular fashion whereby each
component of a circuit is built and verified independently. The components are then put together
and may form another, larger component at the next level of the design hierarchy.
These combined components may then be combined to form even larger components and so on.
This continues to the top level of the design. This practice applies to the design of hardware,
software or any other system for that matter! Our final goal here is to design and implement the
logic for a hardware data path that contains a simple arithmetic and logic unit (ALU) that can
perform low level processing.

Step 1 Decoder
The register file requires a 2‐line to 4‐line decoder with HI‐true outputs and one HI‐true enable
input as shown in the circuit of Step 4. This is similar to the decoder you designed in a previous
lab. Implement this component using the graphic design editor and test it in the MAX7000
device.
Step 2 Quad 4:1 MUX
The register file also requires a Quad 4:1 multiplexer. A Quad 4:1 MUX has four 4‐bit data

inputs, a 4‐bit data output and two select lines as shown below. Study the VHDL source code
given at the end of this lab that implements a Quad 4:1 multiplexer. Be sure you understand the
logic of the VHDL code. Compile this program, implement and test using the MAX7000 device.
Generate a symbol for this MUX which you will use later.

Step 3 Registers The four registers R0, R1, R2 and R3 in the diagram below are to be implemented using the
VHDL code at the end of this lab. Each register comprises 4 positive edge‐triggered D flipflops. Each register
COMPUTER ORGANISATION & ARCHITECTURE LAB (BCS-352)

has a 4‐bit input data and a 4‐bit output data. The clock input to all flipflops in the register is defined as Clk.
Compile this code and make a symbol for the register.
Step 4 Register File
Now we will design the register file using the graphic design editor by connecting the
multiplexer, decoder and four registers as shown below. Compile and test the register file circuit
in the MAX7000 chip to ensure that all four registers can be loaded using toggle switches on the
Data In lines, and read using LEDs connected at the Data Out lines. Be sure that you
understand the timing of the "load enable" input relative to all the other inputs and outputs.

Step 5 Datapath The register file forms the basis of a "datapath" which is a fundamental building block of a
computer. See the diagram below. Data is selected from any register then stored back into any other register in
the register file, all in a single clock cycle ( a lo‐hi‐lo pulse applied to the load enable LE input). A Quad 2:1
MUX included as shown below allows external data to be inserted into the datapath. Data can thus be
transferred between any two registers of our register file or any register can be loaded with external data. This
datapath can execute the following operations:

(a) any register can be loaded with external data from switches Rd ← data (4‐bits)
(where d=0,1,2 or 3)

(b) Any register can be loaded with the data contained in any one of the other registers,
including itself (register‐to‐register transfer) Rd ← Rs (where d, s = 0, 1, 2 or 3) the
implementation is shown below. The inputs [D1, D0, S1, S0, DS] form a 5‐bit "control" word
which specifies the source (S1, S0) and destination (D1, D0) registers of the register file and an
operation (DS) that is to take place. For DS=0, external data from switches is loaded into the
COMPUTER ORGANISATION & ARCHITECTURE LAB (BCS-352)

destination register; for DS=1, data is transferred from the source register to the destination
register. Once the control word and data input (if appropriate) are set on the level switches,
execution is achieved by applying a load enable (LE) input to the register file. This LE input may
be considered as the clock to the entire system. You can view the results of each operation
using four LEDs connected to the output of the register file as shown. Design this data path
using the graphic design editor. VHDL code for the Quad 2:1 MUX design is given at the end of
this lab. Test the circuit for various combinations of the register transfers summarized in the
following table.
Summary of register transfer operations

Note: (1) the first four lines of this table allow for initializing the register contents (DS = 0).
(2) This is not a complete table of all possible micro operations that can execute
COMPUTER ORGANISATION & ARCHITECTURE LAB (BCS-352)

EXPERIMENT NO. 9
AIM: Design the control unit of a computer using either hardwiring or microprogramming
based on its register transfer language description.

BRIEF THEORY
The purpose of this laboratory is to design and implement the control unit to provide control
signals to the 32-bit CPU data-path.

Most of the control unit outputs all the control signals for the Registers, ALU and MUXes in the
datapath. It accepts as input the status bits (Zero and Carry) and the INST for instruction
decisions (Note: the diagram shows the entire INST as input to the control unit. However, if we
refer back to the CPU specification document, only INST[31..28] - opcode - and INST[27..24] -
function code - arerequired). All instructions require 3 clock cycles to execute. Moreover, in
situations when we desire toinitialize or reset the CPU, an enable/reset input is needed.
Please note that a control signal required by the data-path, CLR PC is not produced by the
control unit.The clearing of the program counter occurs during initialization. Reset signal for the
CPU and CLR PC are generated by a reset circuit.
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When we investigate the internal structure of the control unit, it can be divided it into three parts
(VHDL processes), namely a sequential state generator (for T0, T1 and T2), a memory signal
generator (for wen and en setup and hold times), and a combinational circuit for the decoding
operations. A brief description of these processes is given below.

State Generator
The state generator circuit is the synchronous, sequential component of the control unit. It
generates appropriate state signals based on the clock and the current state of the system. It also
generates a set of pulse signals T that can be used to indicate the current state of the instruction
being executed. (shown here for three states).

Note: When ENABLE signal is not asserted, the circuit should go to state T0 and remain in
this state until the ENABLE signal is asserted again. At that point, the circuit resumes normal
operation.

Operation Decoder
The operation decoder is responsible for correctly setting the control signals being fed to the
data-path during instruction execution. It requires the current state, status bits (C and Z) and the
INST contents to determine which instruction to execute. Essentially, the operation decoder is
nothing more than an ifelse type of statement (MUX), which sets the control signals
appropriately. We have determined the correct settings of the control signals for each operation
in the data-path lab. Note that it is wise to use case statements to successfully synthesize the
VHDL for decoding all the CPU instructions.

Memory Signal Generator

To support the load and store instructions, the Write Enable (wen) and Enable (en) signals have
been included in the control unit specification. Assume the signal is active high; the signal must
be asserted correctly during the store and load operations as specified in memory lab manual and
cpu_specification document. The wen and en are sensitive to the Clk, mclk, and INST given.
The process template is given in the code on the next page for setting up "en" and "wen" in the
"Data Memory Instructions" process. Fill in the code with the appropriate values for "en" and
"wen" according to the template given in the specifications to achieve correct setup and hold
times for your CPU's memory operations.
COMPUTER ORGANISATION & ARCHITECTURE LAB (KCS-352)

EXPERIMENT NO. 10
OBJECT: Implement a simple instruction set computer with a control unit and a data path.
APPARATUS REQUIRED: 8085 based microprocessor kit, key board

THEORY:-
The data path includes the ALU, registers including program counter, memories (memory
bus paths), and multiplexers used in processing elements of the processor. All these
components of datapath perform various operations depending upon the instruction
encountered. The coordination among these components is the task of the control unit.

In Figure 1, the typical organization of a modern von Neumann processor is illustrated. Note that
the CPU, memory subsystem, and I/O subsystem are connected by address, data, and control
buses. The fact that these are parallel buses is denoted by the slash through each line that signifies
a bus.

Figure 1. Schematic diagram of a modern von Neumann processor, where the CPU is
denoted by a shaded box

it is worthwhile to further discuss the following components in Figure 1:

 Processor (CPU) is the active part of the computer, which does all the work of data
manipulation and decision making.
 Datapath is the hardware that performs all the required operations, for example, ALU,
registers, and internal buses.
 Control is the hardware that tells the datapath what to do, in terms of switching, operation
selection, data movement between ALU components, etc.

In MIPS, the ISA determines many aspects of the processor implementation. For example,
implementational strategies and goals affect clock rate and CPI. These implementational
constraints cause parameters of the components in Figure 2 to be modified throughout the design
process.
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Figure 2. Schematic diagram of MIPS architecture from an implementational perspective

Datapath Design and Implementation
The datapath is the "brawn" of a processor, since it implements the fetch-decode-execute cycle.
The general discipline for datapath design is to (1) determine the instruction classes and formats
in the ISA, (2) design datapath components and interconnections for each instruction class or
format, and (3) compose the datapath segments designed in Step 2) to yield a composite datapath.
Load/Store Datapath
The load/store datapath uses instructions such as lw $t1, offset($t2), where offset denotes a
memory address offset applied to the base address in register $t2. The lw instruction reads from
memory and writes into register $t1. The sw instruction reads from register $t1 and writes into
memory. In order to compute the memory address, the MIPS ISA specification says that we have
to sign-extend the 16-bit offset to a 32-bit signed value.
The load/store datapath is illustrated in Figure 3, and performs the following actions in the order
given:
1. Register Access takes input from the register file, to implement the instruction, data, or
address fetch step of the fetch-decode-execute cycle.
2. Memory Address Calculation decodes the base address and offset, combining them to
produce the actual memory address. This step uses the sign extender and ALU.
3. Read/Write from Memory takes data or instructions from the data memory, and
implements the first part of the execute step of the fetch/decode/execute cycle.
4. Write into Register File puts data or instructions into the data memory, implementing the
second part of the execute step of the fetch/decode/execute cycle.
The load/store datapath takes operand #1 (the base address) from the register file, and
sign-extends the offset, which is obtained from the instruction input to the register file.
The sign-extended offset and the base address are combined by the ALU to yield the
memory address, which is input to the Address port of the data memory. The MemRead
signal is then activated, and the output data obtained from the ReadData port of the data
memory is then written back to the Register File using its WriteData port, with RegWrite
asserted.
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Figure 3. Schematic diagram of the Load/Store instruction datapath. Note that the execute step
also includes writing of data back to the register file, which is not shown in the figure, for
simplicity [MK98].
OBSERVATION:
Code to multiply two number
LDA 2000 //Load multiplicant to accumulator
MOV B , A //Move multiplicant from ACC to B register
LDA 2001//Load multiplier to accumulator
MOV C , A//Move multiplier from A to C
MVI A , 00//Load immediate value 00 to a
L: ADD B//Add B (multiplier) with A
DCR C//Decrement C, it act as a counter
JNZ L//Jump to L if C reaches 0
STA 2010//Store result in to memory
HLT //End
RESULT:- It is seen that multiplication of numbers is done correctly.