Assignment-01

Class: BEE-7B Date: October 12, 2023

Subject: Digital System Design Instructor: Dr. Shahid Nawaz Khan
Submission Date: 23-October 2023 Max Marks: 20
Name: Muhammad Danyal Reg no: FA20-EEE-055

Using (a) case and (b) if statement, write an HDL description of an 8-bit arithmetic logic unit (ALU).
The circuit has a three bit select bus (Sel), 8-bit input data-paths A[7:0] and B[7:0], an 8-bit output
data- path y[7:0], and perform the arithmetic and logical operations listed below:
Sel Operation Description
000 y = 8’b0 Reset
001 y=A&B Bitwise AND
010 y =A | B Bitwise OR
011 y=A^B Bitwise XOR
100 y=A+B Add (A and B unsigned)
101 y=A-B Subtract
110 y = ~A Bitwise Complement
111 y=AxB Multiply

Write test bench and include Modelsim simulation results. Use your registration number as
input-1 in test bench while for input-2 use last two digits of your ID card. For second
input pattern, use (input + 5) while for third input pattern, use (input - 5) for input
numbers. (CLO-1)
Code using IF statement
Module Testbench
module alu ////test benchh ////
(
input wire [7:0]A,B,
input wire [2:0]sel, module tb_alu_if;
output reg [7:0]Y reg [7:0]in1,in2;
); reg[2:0] in3;
always@* wire[7:0]out;
if(sel==3'b000) alu_case alu(.A(in1),.B(in2),.sel(in3),.Y(out));
Y=8'b0; initial
else if(sel==3'b001) begin
Y=A&B; in1=8'b0011_0111;
else if(sel==3'b010) in2=8'b0100_0111;
Y=A|B; in3=8'b001;
else if(sel==3'b011)
Y=A^B;
else if(sel==3'b100) in1=8'b0011_1100;
Y=A+B; in2=8'b0100_1100;
else if(sel==3'b101) in3=8'b101;
Y=A-B;
else if(sel==3'b110)
Y=~A; in1=8'b0011_0010;
else Y=A*B; in2=8'b0100_0010;
endmodule in3=8'b100;
end
endmodule
Output

Code using CASE statement

////for case statement module tb_ALU_case;

module alu_case reg [7:0] in1,in2;
( reg [2:0] in3;
input wire [7:0]A,B, wire [7:0] out;
input wire [2:0]sel, ALU_case a0 (.A(in1),.B(in2),.S(in3),.Y(out));
output reg [7:0]Y initial
); begin
always@*
case (sel) in1=8'b0011_1010;in2=8'b0011_1111;in3=3'b1
3'b000:Y=8'b0; 01;
3'b001:Y=A&B; #5 in1='b0011_1111;
3'b010:Y=A|B; in2=8'b1000_0100;in3=3'b100;
3'b011:Y=A^B; #5
3'b100:Y=A+B; in1=8'b0011_0101;in2=8'b0011_1010;in3=3'b0
3'b101:Y=A-B; 11;
3'b110:Y=~A; #5 $Stop;
3'b111:Y=A*B; end
endcase endmodule
endmodule

Output
 1. Write a Verilog code for 4x1 Multiplexer using (CLO-1)
a. Conditional operator + assign statement.
Module Testbench
module mux_4to1 module tb_mux_4to1;
( reg in1,in2,in3,in4;
wire A,B,C,D,S0,S1 reg [1:0]in5;
input wire [1:0]s, wire f_out;
output wire f mux_4to1 mo
); (.i0(in1),.i1(in2),.i2(in3),.i3(in4),.s(in5),.f(f_out));
assign f= (s==2'b00)? i0 : initial
(s==2'b01)? i1 : begin
(s==2'b10)? i2 : i3; in1=1'b1; in2=1'b0; in3=1'b1; in4=1'b1;
endmodule in5=2'b01;
#5 $Stop;
end
endmodule
Output

b. Procedural Statements (If, Else)

 Module Testbench
module mux_4to1_if module tb_mux_4to1_if;
( reg in1,in2,in3,in4;
input wire i0,i1,i2,i3, reg [1:0]in5;
input wire [1:0]s, wire f_out;
output reg y mux_4to1_if mo
); (.i0(in1),.i1(in2),.i2(in3),.i3(in4),.s(in5),.y(f_out));
always @* initial
if(s==2'b00) begin
y=i0; in1=1'b1; in2=1'b0; in3=1'b1; in4=1'b1;
else if (s==2'b01) in5=2'b01;
y=i1; #5 in1=1'b1; in2=1'b0; in3=1'b1; in4=1'b1;
in5=2'b11;
else if (s==2'b10)
#5 $Stop;
y=i2;
end
else
endmodule
y=i3;
endmodule

Output

c. By instantiating 2to1 Multiplexers (write code of 2to1 Mux and then use
it to design 4to1 Mux)
Module Testbench
module mux2to1 module tb_mux4to1H;
( reg in1,in2,in3,in4,in5,in6;
input wire A,B,Sel, wire out;
output wire y mux4to1H
 ); m0(.A(in1),.B(in2),.C(in3),.D(in4),.Sel0(in5),.Sel1(in6),.y(o
wire w1,w2,w3; ut));
not n1(w1,Sel); initial
and a1(w2,A,w1); begin
and a2(w3,B,Sel); in1=1'b1; in2=1'b1; in3=1'b1; in4=1'b1; in5=1'b0;
in6=1'b0;
or o1(y,w3,w2);
#5 in1=1'b1; in2=1'b1; in3=1'b1; in4=1'b1; in5=1'b1;
endmodule
in6=1'b1;
#5 in1=1'b1; in2=1'b0; in3=1'b1; in4=1'b0; in5=1'b1;
module mux4to1H
in6=1'b0;
(
#5 $Stop;
input wire A,B,C,D,Sel0,Sel1,
end
output wire y
endmodule
);
wire w1,w2;
mux2to1
m1(.A(A),.B(B),.Sel(Sel0),.y(w1
));
mux2to1
m2(.A(C),.B(D),.Sel(Sel0),.y(w2
));
mux2to1
m3(.A(w1),.B(w2),.Sel(Sel1),.y(
y));
endmodule

Output
Q: 3 The binary-coded-decimal (BCD) format uses 4 bits to represent 10 decimal digits. For example,
(259)10 is represented as "0010 _0101_1001" in BCD format. A BCD incrementor adds 1 to a number in
BCD format. For example, after incrementing, “0010_0101_100 1 " (i.e., 25910) becomes "0010 _0110
_0000" (i.e., 26010). (CLO-1)

a. Design a three-digit 12-bit incrementor and derive the code.

Module Testbench
module BCD_12bit_inc module tb_BCD_12bit_inc;
( reg [11:0]in1;
input wire [11:0] A, reg in2;
input wire en, wire [11:0]S_out;
output reg [11:0] out BCD_12bit_inc m0(.A(in1),.en(in2),.out(S_out));
); initial
always @ * begin
if(en==1'b1) in1=12'b0000_0000_0000; in2= 1'b1;
begin #15 in1=12'b0000_0000_0001; in2= 1'b1;
case(A) #15 in1=12'b0000_0000_0011; in2 = 1'b0;
12'b0000_0000_0000: #15 $Stop;
out=12'b0000_0000_0001;//0 to 1 end
12'b0000_0000_0001: endmodule
out=12'b0000_0000_0010;//1 to 2
12'b0000_0000_0010:
out=12'b0000_0000_0011;//2 to 3
12'b0000_0000_0011:
out=12'b0000_0000_0100;//3 to 4
default: out = A;
endcase

end
else out = A;

endmodule

Output