DSP56367P/D

MOTOROLA Revision 0
SEMICONDUCTOR PRODUCT INFORMATION 09/00

Product Brief DSP56367

24-Bit Audio Digital Signal Processor
The DSP56367 supports digital audio applications requiring sound field processing, acoustic
equalization, and other digital audio algorithms. The DSP56367 uses the high performance,
single-clock-per-cycle DSP56300 core family of programmable CMOS digital signal processors
(DSPs) combined with the audio signal processing capability of the Motorola Symphony™ DSP
family, as shown in Figure 1. This design provides a two-fold performance increase over
Motorola’s popular Symphony family of DSPs while retaining code compatibility. Significant
architectural enhancements include a barrel shifter, 24-bit addressing, instruction cache, and
direct memory access (DMA). The DSP56367 offers 150 million instructions per second (MIPS)
using an internal 150 MHz clock at 1.8 V and 100 million instructions per second (MIPS) using an
internal 100 MHz clock at 1.5 V.

2 16 8 4
1 5
6
MEMORY EXPANSION AREA
DAX PROGRAM X MEMORY Y MEMORY
TRIPLE HOST ESAI SHI RAM RAM RAM
(SPDIF Tx.) /INSTR.
TIMER INTER- INTER- INTER- 13K X 24 7K X 24
INTER- CACHE
FACE FACE FACE 3K x 24 ROM ROM
FACE
PROGRAM 32K x 24 8K x 24
ESAI_1 ROM
40K x 24
Bootstrap
PIO_EB

PM_EB

YM_EB
XM_EB
PERIPHERAL
EXPANSION AREA
ADDRESS YAB
GENERATION EXTERNAL 18
XAB ADDRESS
UNIT PAB BUS
SIX CHANNELS DAB SWITCH ADDRESS
DMA UNIT
24-BIT DRAM &
DSP56300 SRAM BUS 10
Core
INTERFACE
& CONTROL
I - CACHE
DDB
YDB EXTERNAL
INTERNAL 24
XDB DATA BUS
DATA SWITCH
PDB
BUS DATA
GDB

POWER
MNGMNT
PLL DATA ALU
PROGRAM PROGRAM PROGRAM
INTERRUPT
24X24+56->56-BIT MAC
JTAG
4
CLOCK DECODE ADDRESS
CONTROLLER TWO 56-BIT ACCUMULATORS
GENERATOR CONTROLLE GENERATOR
BARREL SHIFTER OnCE™

EXTAL MODA/IRQA 24 BITS BUS

RESET MODB/IRQB
PINIT/NMI MODC/IRQC
MODD/IRQD

Figure 1 DSP56367 Block Diagram

This document contains information on a new product. Specifications and information herein are subject to change without notice.

Product Brief

©2000 MOTOROLA, INC.

DSP56367

DSP56367 Features

• DSP56300 modular chassis

• 150 Million Instructions Per Second (MIPS) with an 150 MHz clock at internal
logic supply (QVCCL) of 1.8V.
• 100 Million Instructions Per Second (MIPS) with an 100 MHz clock at internal
logic supply (QVCCL) of 1.5V.
• Object Code Compatible with the 56K core.
• Data ALU with a 24 x 24 bit multiplier-accumulator and a 56-bit barrel shifter.
16-bit arithmetic support.
• Program Control with position independent code support and instruction cache
support.
• Six-channel DMA controller.
• PLL based clocking with a wide range of frequency multiplications (1 to 4096),
predivider factors (1 to 16) and power saving clock divider (2 i: i=0 to 7). Reduces
clock noise.
• Internal address tracing support and OnCE for Hardware/Software debugging.
• JTAG port.
• Very low-power CMOS design, fully static design with operating frequencies
down to DC.
• STOP and WAIT low-power standby modes.
• On-chip Memory Configuration
• 7Kx24 Bit Y-Data RAM and 8Kx24 Bit Y-Data ROM.
• 13Kx24 Bit X-Data RAM and 32Kx24 Bit X-Data ROM.
• 40Kx24 Bit Program ROM.
• 3Kx24 Bit Program RAM and 192x24 Bit Bootstrap ROM. 1K of Program RAM
may be used as Instruction Cache or for Program ROM patching.
• 2Kx24 Bit from Y Data RAM and 5Kx24 Bit from X Data RAM can be switched
to Program RAM resulting in up to 10Kx24 Bit of Program RAM.
• Off-chip memory expansion
• External Memory Expansion Port.
• Off-chip expansion up to two 16M x 24-bit word of Data memory.
• Off-chip expansion up to 16M x 24-bit word of Program memory.
• Simultaneous glueless interface to SRAM and DRAM.
• Peripheral modules

Product Brief
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 DSP56367

• Serial Audio Interface (ESAI): up to 4 receivers and up to 6 transmitters, master

or slave. I2S, Sony, AC97, network and other programmable protocols.
• Serial Audio Interface I(ESAI_1): up to 4 receivers and up to 6 transmitters,
master or slave. I2S, Sony, AC97, network and other programmable protocols
The ESAI_1 shares four of the data pins with ESAI_0, and ESAI_1 does NOT
support HCKR and HCKT (high speed clocks)
• Serial Host Interface (SHI): SPI and I 2C protocols, multi master capability, 10-
word receive FIFO, support for 8, 16 and 24-bit words.
• Byte-wide parallel Host Interface (HDI08) with DMA support.
• Triple Timer module.
• Digital Audio Transmitter (DAX): 1 serial transmitter capable of supporting the
SPDIF, IEC958, CP-340 and AES/EBU digital audio formats.
• Pins of unused peripherals (except SHI) may be programmed as GPIO lines.
• Split power supply
• QVCCL and PVCC require 1.8 and 1.5 volt supply.
• Other supply pins DVCC, QVCCH,AVCC,CVCC and SVCC require 3.3 volts
supply.
• 144-pin plastic TQFP package.
Note: Note: AA3 pin is not bonded out in 144-pin plastic TQFP.

Documentation

Table 1 lists the documents that provide a complete description of the DSP56367 and are
required to design properly with the part. Documentation is available from a local Motorola
distributor, a Motorola semiconductor sales office, a Motorola Literature Distribution Center,
or through the Motorola DSP home page on the Internet (the source for the latest
information).

Table 1 DSP56367 Documentation

Document Name Description Order Number

DSP56300 Family Manual Detailed description of the 56000-family DSP56300FM/AD
architecture and the 24-bit core processor
and instruction set

Product Brief
MOTOROLA DSP56367 iii
DSP56367

Symphony and OnCE are registered trademarks of Motorola, Inc.

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes
no warranty, representation or guarantee regarding the suitability of its products for any particular purpose,
nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages.
“Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in
different applications and actual performance may vary over time. All operating parameters, including
“Typicals” must be validated for each customer application by customer’s technical experts. Motorola does
not convey any license under its patent rights nor the rights of others. Motorola products are not designed,
intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support life, or for any other application in which the failure of the Motorola product
could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola
products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages,
and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury
or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was
negligent regarding the design or manufacture of the part. Motorola and  are registered trademarks of
Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

Product Brief
iv DSP56367 MOTOROLA