A High Performance and Full Utilization Hardware

Implementation of Floating Point Arithmetic Units

Chen Yang*, Siwei Xiang, Jiaxing Wang, and Liyan Liang
School of Microelectronics, Xi’an Jiaotong University, Xi’an, Shaanxi, 710049, China
*Email: [email protected]

Abstract—Floating point operations are widely used in the an increased chip-area exposure of 53.54% [9]. Floating point
fields of communication algorithm, digital signal processing, divider is also a very common arithmetic unit, but it's usually
artificial intelligence and so on. However, the low computation very slow. If the reciprocal operation and multiplier are
speed and excessive resource consumption have become key combined to implement the divider, the performance can be
limitations on system performance and hardware overhead. optimized by designing them separately. Work [10] uses the
Thus, the area efficiency of floating point arithmetic units is
important to accelerate computation and reduce resources. This
least multiplier to fit the reciprocal quadratic equation, which
paper presents high performance and area efficient floating consumes at least two single precision multipliers and two
2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) | 978-1-7281-8281-0/21/$31.00 ©2021 IEEE | DOI: 10.1109/ICECS53924.2021.9665459

point arithmetic units, including adder, multiplier and single precision floating point adders. Work [11] adopts
reciprocal operator. The proposed floating point arithmetic Newton iteration method and has a long waiting period, which
units are evaluated based on a typical scenario of 4×4 matrix does not accord with the high throughput characteristic that
inversion in communication. Experimental results show that our GPU arithmetic unit outputs one result in one cycle after the
designs achieved improvements on both performance and pipeline is filled [12].
resource overhead. Compared with Xilinx Vivado IP, our Therefore, to realize high-speed and high-performance
designs save 20%-45% resources and only consumes 1/4 applications, a single precision floating point number adder,
computing latency. Compared to DesignWare IP, our designs reciprocal operation and a mixed precision floating point
need only 1/4 computing latency, as well as improving area number multiplier are proposed.
efficiency by 3.65 times.
Keywords—floating point arithmetic, mixed precision, Taylor II. ALGORITHM ANALYSIS
series, pipeline, matrix inversion
A. Floating Point Representation
I. INTRODUCTION TABLE I shows IEEE-754 form for floating point number.
The single precision point number consists of 32 bits and the
In computing system, floating point number is the most double precision point number consists of 64 bit [13]. And the
widely used form to represent real number. Floating point single precision floating point number is symbolized in (1). S
numbers use exponents to make the position of the decimal is the sign bit of A, 0 for positive and 1 for negative. E is the
point float up and down as needed to express a wider range of exponent bit of A, ranges from -127 to +128. M is the mantissa
real numbers flexibly. Compared with fixed point numbers, bit of A. Single precision floating point number includes 1 bit
floating point numbers can represent a wider range and have for sign, 8 bits for exponent and 23 bits for mantissa. Mantissa
higher accuracy, so they are widely used in the fields of is hoarded with one hidden bit as 1.M. The exponent requires
communication algorithm, digital signal processing, artificial a bias to represent negative number, which in single precision
intelligence and so on. However, the slow operation and high is 127. The representation of double precision floating point
resource consumption speed has become its limitation Taking number is similar, except the bit width of exponent and
the communication algorithm as an example, the channel mantissa. IEEE-754 also specifies some special formats, such
estimation [1] and MMSE algorithm [2] all need to use the as the representation of infinity and denormalization number,
operation of matrix, which inevitably requires floating point which will be ignored in this paper. That’s to say, all the 32-
adders, multipliers and dividers. Therefore, A high area bit number will be a real number according to (1). And number
efficiency floating point arithmetic unit is important to 0 is represented by 32’h00000000 or 32’h80000000.
improve the algorithm speed and reduce resources. In all kinds TABLE I IEEE-754 FORM
of matrix operations, addition, multiplication and division are
most used. Corresponding to floating point numbers, adders, Sign Exponent Mantissa
multipliers and divider are generally required. Single Precision 1-bit[31] 8-bit [30:23] 23-bit [22:0]
Floating point adder is one of the most frequently used
floating point operation. An analysis of real time applications Double Precision 1-bit[63] 11-bit [62:52] 52-bit [51:0]
indicate that signal processing algorithms require, on an
average 40% multiplication and 60% addition operations [3].  𝐴 = (−1) 𝑆 ∗ 2𝐸−127 ∗ (1. 𝑀) 
Leading one predictor and “far and close path” algorithms B. Floating Point Adder
achieve a good overall latency, but the resources used are 88% Fig. 1 show the standard floating point adder process.
higher than the standard adder [4]. A tremendous resource and Floating point number adder requires a series of processes,
latency overhead reduce the efficiency of floating point such as sign judgment, exponent subtractor, exponent
multipliers. A significant portion of the latency is attributed alignment, mantissa add/sub, mantissa normalization and so
mainly to the multiplication of the mantissa parts of the two on. And subtraction only needs to reverse the sign bit of the
multiplicands. In order to improve the efficiency of floating second operand. The function of sign judgment is judging
point multipliers, numerous fast-many algorithms have been whether the mantissa should be added or subtracted. Floating
put forth and modeled, such as array multiplier [5], Vedic point number addition needs to ensure the same exponent. The
multiplier [6] and Wallace tree multiplier [7], [8]. Among smaller number’s mantissa will be shifted by 𝐸 bits, which
them, Array multiplier consumes the least number of LUTs is the difference between the two operands. This requires steps
but suffers from increased latency, while the Wallace tree exponent subtractor and alignment. After add/sub the mantissa
multiplier provides the lowest input-output latency but suffers of the larger number and the mantissa of the smaller number

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 after shifting, the result may not conform to the rule of IEEE- accuracy of the final result will be. In this way, finding the
754, so the mantissa needs to be normalized. In general, the 1
and
1
by looking up a smaller table to get the
above steps are in order, while some steps can be implemented 1.𝑚0 1.𝑚02
reciprocal through (2) will be more convenient.
in parallel. Therefore, only using combinational logic to
1 1 1 1 1 0.0𝑛
implement floating point adder will lead to a long latency. And = −( − )= −( )
1. 𝑚𝑛 1. 𝑚0 1. 𝑚0 1. 𝑚𝑛 1. 𝑚0 1. 𝑚0 ∗ 1. 𝑚𝑛
pipeline is usually used to reduce latency. In order to unify the (2)
design and equalize the timing, the three kinds of arithmetic ≈
1
−(
1
∗ 0.0𝑛)
units all use three-stage pipeline. Some advanced algorithms 1. 𝑚0 1. 𝑚02
speed up the process by increasing the area, but the pipeline 𝑆1 𝐸1 𝑀1
can also improve the speedup ratio by evenly dividing the
hold 2 − 𝐸1 split
standard process.
𝑆1 𝑆2 𝐸1 𝐸2 𝑀1 𝑀2 underflow exponent look up table
judgment
sign judgment compare absolute value normal T= −2 
𝐸1 𝐸2 𝑀1 𝑀2 underflow flag
out=  -T
𝐸 = 𝐸1 − 𝐸2 −1

exponent sub out=

exponent alignment

END
mantissa add/sub
Fig. 3. Process of floating point reciprocal operation
mantissa normalization

exponent judgment
III. IMPLEMENTATION
underflow normal overflow A. High speedup adder with computation balance
overflow flag
underflow flag
In the standard addition process, exponent alignment and
mantissa normalization require the most complex operations.
END
The bit width of the fixed point adder required for mantissa
Fig. 1. Standard process of floating point adder add/sub is too large and requires a long latency. Therefore, the
C. Floating Point Multiplier three steps are divided into three different stages of the
Fig. 2 shows the floating point multiplier process. The pipeline. Fig. 4 shows the divided three-stage pipeline adder.
floating point multiplication process is relatively simple, but The first stage is mainly to complete the preparatory work.
the fixed point multiplier used in mantissa multiplication The inputs of the whole module are 𝑠𝑒𝑙𝑒𝑐𝑡 and 𝑆𝑥 /𝐸𝑥 /𝑀𝑥 .
consumes a lot of resources. In some application scenarios, The former determines whether operands are added or
such as channel estimation, the accuracy of the multiplier is subtracted, while the latter are the sign bit, exponent and
required to be high and low. Only low accuracy is required for mantissa of input data. And the core module is the comparator,
matrix multiplication, and high accuracy is required for matrix the function of which is to compare the absolute values of two
inversion. At present, advanced algorithms are studying how operands, which will be used to calculate 𝐸 to determine the
to optimize the multiplier. However, there is nothing they can number of bits to shift the mantissa, decide whether to add or
do for different accuracy requirements. The multiplication of subtract mantissa and determine the sign bit of the output
a pair of single precision floating point numbers requires a 24- result. Output 𝑀𝑆1 /𝑀𝐿1 is the mantissa of smaller/bigger input
bit multiplier to multiply the mantissa, while half precision data. The second stage mainly completes the mantissa add/sub,
requires a 12-bit multiplier. That’s to say, using a 12-bit and the latency can be balanced by putting the positive and
multiplier can not only directly realize half precision negative judgment of the smaller mantissa into the second
multiplication, but also realize single precision multiplication level. The key pf the third stage is the "leading 1" detection.
through time-sharing multiplexing, so as to save the resource Using dichotomy to detect "leading 1" can save area as much
consumption of the multiplier. as possible on the premise of faster speed. Moreover, it is of
𝑆1 𝑆2 𝐸1 𝐸2 𝑀1 𝑀2 little significance to simply reduce the latency of a certain
sign judgment exponent add mantissa multiply
stage in the pipeline, and the dichotomy will not lead to too
long latency of the third stage. Exponent judgment is used to
mantissa normalization
determine whether the result overflows or underflows. This is
because the single precision floating point number
exponent judgment representation has upper and lower restrictions and requires
underflow normal overflow additional judgment. Finally, the red font is the output signal,
underflow flag overflow flag including the sign bit, exponent and mantissa of the result. The
remaining two signals are overflow and underflow labels.
select 𝑆1 𝑆2 𝐸1 𝐸2 𝑀1 𝑀2
END
0 1 ALU
Fig. 2. Process of Floating point multiplier MUX MUX comparator MUX

D. Floating Point Reciprocal operation 𝑐 𝑆 1 MUX

𝐸
>> 𝑀𝐿1
𝐸 𝑀𝑆1
Fig. 3 shows the floating point reciprocal operation Register
1

process. A reciprocal operation based on look-up table method −𝑀𝑆1 𝑀𝑆1 𝑀𝐿1
MUX
and first-order Taylor series is proposed for floating point 𝑆 2 𝐸 2
𝑐
ALU

divider, whose key is the reciprocal of the mantissa. Assuming 𝑀 2

that the mantissa of X can be written as 1.MN, M is the higher 𝑀 2 𝐸

Register

𝑀 𝐸 𝑡 𝑀 𝑡
m bit, and N is the lower (23-m) bits, the reciprocal of the
2 2
dichotomy ALU >> exponent judgment

mantissa of a can be expressed in (2). 0 means that all 𝑠 𝐸 𝑡 𝑀 𝑡

𝑀 over under
corresponding bits are 0, and the accuracy of the (2) is poor Register

when M is small. However, the greater M is, the higher the Fig. 4. Divided three-stage pipeline adder

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 B. Highly-utilization multiplier for mixed precision The most important for reciprocal operation is the scale of
Usually, different multipliers are needed to achieve the table. TABLE II shows the verification results under three
multiplication with different precision. But this will lead to a conditions. According to the evaluation results, 60000 single
waste of resources. Fig. 5 is the pipeline diagram of multiplier precision floating points are randomly generated, which can
with mixed precision. Compared with the adder, the flow of meet the accuracy of 18-bit when m is 10-bit and the decimal
the multiplier is simpler. And the core module is the 12-bit place of the approximate result is 20-bit. Therefore, the width
fixed point multiplier in the second stage and the state of this table is 40-bit, the depth is 1024, and the total capacity
machines in the first and second stages. The input is similar to is 5KB.
adder, except that 𝑠𝑒𝑙𝑒𝑐𝑡 determines the precision of the TABLE II ACCURACY COMPARISON UNDER THREE CONDITIONS
multiplier. This signal will be used to control the state 𝟏 𝟏
m-bit / -bit accuracy
machines. When implementing half precision floating point 𝟏.𝒎𝟎 𝟏.𝒎𝟎𝟐

multiplication, the two state machines only need one cycle. 9 40-bit 93.96%
After the pipeline is full, the results can be calculated in each
10 20-bit 100%
cycle. When implementing single precision floating point
multiplication, each state machine needs four cycles. The 10 19-bit 99.83%
former prepares operands𝑚𝑎 /𝑚𝑏 for fixed point multiplier in
each cycle, and the latter stores the product result 𝑚𝑢𝑙 𝑡 one IV. RESULTS AND COMPARISONS
cycle behind. This implementation can calculate a half
precision floating point multiplication every cycle or a single A. Implementation setup
precision floating point multiplication every 4 cycles. To detect the overall area efficiency of floating point
Moreover, under different working modes, the utilization rate operation unit, take the inversion of matrix in communication
of resources is close to 100%. Another important advantage is algorithm as an example to analysis the performance of
that the multiplier implemented in this way can cooperate with our_adder, our_multiplier and our_reciprocal. The hardware
the reciprocal operation proposed later to realize single implementation of matrix inversion is difficult, it generally
precision division. One reciprocal operation and four single needs to be divided into several steps. They are triangular
precision multipliers can be used to realize four dividers, decomposition, inverse of triangular matrix/diagonal matrix,
which greatly improves the efficiency and resource utilization. multiplication of triangular matrix/diagonal matrix and
𝑆1 𝑆2 𝐸1 𝐸2 𝑀1 𝑀2 select conjugate [14]. These operations require a total of 128 adders,
128 multipliers and 4 reciprocal operations and it is executed
XOR ALU State machine in sequence.
𝑆 1 𝐸 1 𝑚 𝑚 𝑠𝑒𝑙𝑒𝑐𝑡 B. Comparisons
Register
1) Comparison with Vivado IP
𝑚 𝑚 𝑠𝑒𝑙𝑒𝑐𝑡 0 1 𝐸 1 𝑀 𝑡
We first evaluated the performance and resource overhead
* 2
of our designs on Xilinx xc7k325tffg900-2 FPGA device
12 𝑡
State machine MUX 𝑠
𝑆 2 𝑚𝑢𝑙 𝑡 ALU >>
Register
𝑀 2 𝑡 𝑠
𝐸 2
𝑀 2
using Vivado design suite. TABLE III shows the synthesis
Register results of this design and Xilinx floating point arithmetic IPs
𝐸 2 𝑀 2 [15]. The resources of adder, multiplier and reciprocal
exponent judgment
operation are far less than these of Xilinx IPs, and the latency
𝑀 over under and cycles are much lower. The reciprocal operation reduces
Register
the resources of LUT, FF and DSP by introducing ROM. In
Fig. 5. Divided three-stage pipeline multiplier most cases, a ROM can support several reciprocal operations
C. Reciprocal operator using look-up table and first-order at the same time. On average, this method is more meaningful
Taylor series than directly calculating the reciprocal.
The reciprocal operation will not be used alone. It is TABLE III SYNTHESIS RESULTS ON VIVADO
needed to realize the division operation together with the
Latency
multiplier. The existing reciprocal operations generally have Operation LUT FF ROM DSP
(ns)
Cycles
the problems of long latency and large area. In order to realize
our_adder 311 212 0 0 4.513 3
the overall optimization, the latency of reciprocal operation
only needs to be lower than that of adder and multiplier, and our_multiplier 167 285 0 1 5.174 3
meet a certain accuracy, so as to realize accurate and efficient our_reciprocal 24 111 5kB 0 6.393 3
division operation. Fig. 6 is the pipeline diagram of multiplier
with first-order Taylor series. Vivado adder 350 654 0 0 6.618 14
𝑆1 𝐸1 2 𝑀1 Vivado
244 444 0 1 6.515 13
multiplier
ALU Look up table Vivado
203 375 0 8 7.871 31
𝑆 𝐸  −1  −2
0.0
reciprocal
1 1

Register
According to the relevant conclusions of matrix inversion,
the longest path of matrix inversion of 4×4 needs 10 times
 −2

𝑆
0.0
 −1
addition, 5 times multiplication and 3 times division. The
𝐸 20 𝑡 *
division can be realized by a multiplication and a reciprocal
2 2

Register
operation. TABLE IV shows the comparison of resource and
 −1 𝐸 2
latency. According to the TABLE IV, the LUT required for
ALU
exponent judgment matrix inversion is saved by about 20%, and the FF is 45% of
𝑀 𝑡 𝑀 over under the standard IP. Since the tables required by the four reciprocal
Register operations are the same, only one ROM is required. By
Fig. 6. Divided three-stage pipeline reciprocal operation introducing ROM, DSP resources occupied by reciprocal

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 operation can be saved. The number of arithmetic units in this China under Grant 62176206, Special Project of Artificial
design is far less than the standard IP. At the same time, Intelligence of Aviation Science Foundation under Grant
because the slowest reciprocal operation is about 1.5ns faster 2020Z066070001, and Key-Area Research and Development
than the standard IP, the total latency to realize a 4×4 matrix Program of Guangdong Province under Grant
inversion only consumes less than 1/4 of the standard IP. 2019B010154002. (Corresponding author: Chen Yang.)
TABLE IV RESOURCES AND LATENCY
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