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Chapter 2 - Part2

The document discusses CMOS transistor theory, focusing on threshold voltage and body effects, as well as the phenomenon of latchup caused by parasitic bipolar transistors in CMOS circuits. It explains how latchup occurs, the conditions that trigger it, and the potential damage it can cause to integrated circuits. Additionally, it outlines prevention techniques such as using latchup-resistant processes and layout strategies to minimize resistance.

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13 views12 pages

Chapter 2 - Part2

The document discusses CMOS transistor theory, focusing on threshold voltage and body effects, as well as the phenomenon of latchup caused by parasitic bipolar transistors in CMOS circuits. It explains how latchup occurs, the conditions that trigger it, and the potential damage it can cause to integrated circuits. Additionally, it outlines prevention techniques such as using latchup-resistant processes and layout strategies to minimize resistance.

Uploaded by

zzzzzzz
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Introduction to

CMOS VLSI
Design

Chapter 2:
CMOS Transistor Theory
Part II
copyright@David Harris, 2004
Updated by Li Chen, 2010

Slide 1
Threshold voltage
Body Effects

Vt decreases with
negative substrate
voltage

CMOS VLSI Design Slide 2


Example

CMOS VLSI Design Slide 3


Example

CMOS VLSI Design Slide 4


Subthreshold Votlage

CMOS VLSI Design Slide 5


CMOS Latchup
 Latchup occurs due parasitic bipolar transistors that
exist in the basic inverter as shown below

CMOS VLSI Design


CMOS Latchup
 Once the parasitic thyristor latching circuit has triggered
(Vt= trigger voltage) snapback occurs and the integrated
circuit is latched.

CMOS VLSI Design


CMOS Latchup
 The configuration of
these bipolar
transistors create a
positive feedback
loop, and will cause
the logic gate to
latchup as shown to
the left
 By using heavily
doped material
where Rn and Rp
exist, there
resistance will be
lowered thereby
reducing the
chance of latchup
occurring

CMOS VLSI Design


CMOS Latchup

 Suppose a base current iBN begins to flow in the


base of the npn transistor. This base current is
amplified by the npn current gain N an must be
supplied from the base of the pnp transistor. The
pnp base current is then amplified further by the
current gain P of the pnp transistor, yielding a
collector current equal to
 iCP = PiBP = P(NiBN)

CMOS VLSI Design


CMOS Latchup
 Once the circuit has entered the latchup state, both
transistors saturate, and the voltage across the
structure collapses to one diode drop plus one
saturation voltage.
 V = VEB+VCESAT = VBE + VECSAT
 Large currents and power dissipation can rapidly
destroy most CMOS structures. e.g. electro-
migration will damage the metal lines.

CMOS VLSI Design


Chap 7 - 11

CMOS Latchup

 Latchup would not occur in an ideal structure for


which Rn = 0 = Rp – modern CMOS technology
uses special substrates and processing to
minimize the values of these two resistors.
 A fault or transient occurs that causes one of the
source or drain diffusions to momentarily exceed
the power supply voltage levels, the latchup can
be triggered.
 Ionizing radiation or intense optical illumination
are two other possible sources of latchup
initiation.

CMOS VLSI Design


Latch-up Prevention
 Latchup resistant CMOS processes – reduce the
gain the the parasitic transistors.
 Layout techniques - Use substrate contact to reduce
Rn & Rp.

CMOS VLSI Design

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