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Structural Model Codes

The document outlines the design and implementation of various digital circuits using VHDL, including full adders, full subtractors, and multiplexers (MUX). It details the structure of half adders and half subtractors, as well as 2x1, 4x1, and 8x1 multiplexers, demonstrating how to build more complex circuits from simpler components. The document serves as a comprehensive guide for creating these fundamental digital logic components.

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jean23122004
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
4 views

Structural Model Codes

The document outlines the design and implementation of various digital circuits using VHDL, including full adders, full subtractors, and multiplexers (MUX). It details the structure of half adders and half subtractors, as well as 2x1, 4x1, and 8x1 multiplexers, demonstrating how to build more complex circuits from simpler components. The document serves as a comprehensive guide for creating these fundamental digital logic components.

Uploaded by

jean23122004
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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FULL ADDER USING HALF ADDER:

library ieee;
use ieee.std_logic_1164.all;

entity xor_gate is
port (i1, i2: in std_logic;
o1: out std_logic);
end xor_gate;

architecture behavior of xor_gate is


begin
o1 <= i1 xor i2;
end behavior;

entity and_gate is
port (i1, i2: in std_logic;
o1: out std_logic);
end and_gate;

architecture behavior of and_gate is


begin
o1 <= i1 and i2;
end behavior;

entity or_gate is
port (i1, i2: in std_logic;
o1: out std_logic);
end or_gate;
architecture behavior of or_gate is
begin
o1 <= i1 or i2;
end behavior;

entity half_adder is
port (a, b: in std_logic;
sum, carry_out: out std_logic);
end half_adder;

architecture structure of half_adder is

component xor_gate
port (i1, i2: in std_logic;
o1: out std_logic);
end component;

component and_gate
port (i1, i2: in std_logic;
o1: out std_logic);
end component;

begin
u1: xor_gate port map (i1 => a, i2 => b, o1 => sum);
u2: and_gate port map (i1 => a, i2 => b, o1 => carry_out);

end structure;

entity full_adder is
port (a, b, cin: in std_logic;
sum, cout: out std_logic);
end full_adder;

architecture structure of full_adder is

component half_adder
port (a, b: in std_logic;
sum, carry_out: out std_logic);
end component;

signal s1, c1, c2: std_logic;

begin
ha1: half_adder port map (a => a, b => b, sum => s1, carry_out => c1);
ha2: half_adder port map (a => s1, b => cin, sum => sum, carry_out => c2);
cout <= c1 or c2;

end structure;

FULL SUB USING HALF SUB

library ieee;
use ieee.std_logic_1164.all;

entity xor_gate is
port (i1, i2: in std_logic;
o1: out std_logic);
end xor_gate;
architecture behavior of xor_gate is
begin
o1 <= i1 xor i2;
end behavior;

entity and_gate is
port (i1, i2: in std_logic;
o1: out std_logic);
end and_gate;

architecture behavior of and_gate is


begin
o1 <= i1 and i2;
end behavior;

entity not_gate is
port (i1: in std_logic;
o1: out std_logic);
end not_gate;

architecture behavior of not_gate is


begin
o1 <= not i1;
end behavior;

entity half_subtractor is
port (a, b: in std_logic;
diff, borrow_out: out std_logic);
end half_subtractor;

architecture structure of half_subtractor is

component xor_gate
port (i1, i2: in std_logic;
o1: out std_logic);
end component;

component and_gate
port (i1, i2: in std_logic;
o1: out std_logic);
end component;

component not_gate
port (i1: in std_logic;
o1: out std_logic);
end component;

signal not_a: std_logic;

begin
u1: xor_gate port map (i1 => a, i2 => b, o1 => diff);
u2: not_gate port map (i1 => a, o1 => not_a);
u3: and_gate port map (i1 => not_a, i2 => b, o1 => borrow_out);

end structure;

entity full_subtractor is
port (a, b, bin: in std_logic;
diff, bout: out std_logic);
end full_subtractor;

architecture structure of full_subtractor is

component half_subtractor
port (a, b: in std_logic;
diff, borrow_out: out std_logic);
end component;

signal d1, b1, b2, b3: std_logic;

begin
hs1: half_subtractor port map (a => a, b => b, diff => d1, borrow_out => b1);
hs2: half_subtractor port map (a => d1, b => bin, diff => diff, borrow_out => b2);
b3 <= (not a) and bin;
bout <= b1 or b2 or b3;

end structure;

4x1 MUX using 2x1 MUX:

library ieee;
use ieee.std_logic_1164.all;

entity and_gate is
port (i1, i2: in std_logic;
o1: out std_logic);
end and_gate;

architecture behavior of and_gate is


begin
o1 <= i1 and i2;
end behavior;

entity or_gate is
port (i1, i2: in std_logic;
o1: out std_logic);
end or_gate;

architecture behavior of or_gate is


begin
o1 <= i1 or i2;
end behavior;

entity not_gate is
port (i1: in std_logic;
o1: out std_logic);
end not_gate;

architecture behavior of not_gate is


begin
o1 <= not i1;
end behavior;

entity mux_2x1 is
port (in0, in1, s: in std_logic;
z: out std_logic);
end mux_2x1;

architecture structure of mux_2x1 is

component and_gate
port (i1, i2: in std_logic;
o1: out std_logic);
end component;

component or_gate
port (i1, i2: in std_logic;
o1: out std_logic);
end component;

component not_gate
port (i1: in std_logic;
o1: out std_logic);
end component;

signal not_s, and0, and1: std_logic;

begin
u1: not_gate port map (i1 => s, o1 => not_s);
u2: and_gate port map (i1 => in0, i2 => not_s, o1 => and0);
u3: and_gate port map (i1 => in1, i2 => s, o1 => and1);
u4: or_gate port map (i1 => and0, i2 => and1, o1 => z);

end structure;
entity mux_4x1 is
port (in0, in1, in2, in3: in std_logic;
s0, s1: in std_logic;
z: out std_logic);
end mux_4x1;

architecture structure of mux_4x1 is

component mux_2x1
port (in0, in1, s: in std_logic;
z: out std_logic);
end component;

signal m1, m2: std_logic;

begin
mux1: mux_2x1 port map (in0 => in0, in1 => in1, s => s0, z => m1);
mux2: mux_2x1 port map (in0 => in2, in1 => in3, s => s0, z => m2);
mux3: mux_2x1 port map (in0 => m1, in1 => m2, s => s1, z => z);

end structure;

8x1MUX using 2x1MUX

library ieee;
use ieee.std_logic_1164.all;

entity and_gate is
port (i1, i2: in std_logic;
o1: out std_logic);
end and_gate;

architecture behavior of and_gate is


begin
o1 <= i1 and i2;
end behavior;

entity or_gate is
port (i1, i2: in std_logic;
o1: out std_logic);
end or_gate;

architecture behavior of or_gate is


begin
o1 <= i1 or i2;
end behavior;

entity not_gate is
port (i1: in std_logic;
o1: out std_logic);
end not_gate;

architecture behavior of not_gate is


begin
o1 <= not i1;
end behavior;

entity mux_2x1 is
port (in0, in1, s: in std_logic;
z: out std_logic);
end mux_2x1;

architecture structure of mux_2x1 is

component and_gate
port (i1, i2: in std_logic;
o1: out std_logic);
end component;

component or_gate
port (i1, i2: in std_logic;
o1: out std_logic);
end component;

component not_gate
port (i1: in std_logic;
o1: out std_logic);
end component;

signal not_s, and0, and1: std_logic;

begin
u1: not_gate port map (i1 => s, o1 => not_s);
u2: and_gate port map (i1 => in0, i2 => not_s, o1 => and0);
u3: and_gate port map (i1 => in1, i2 => s, o1 => and1);
u4: or_gate port map (i1 => and0, i2 => and1, o1 => z);
end structure;

entity mux_8x1 is
port (in0, in1, in2, in3, in4, in5, in6, in7: in std_logic;
s0, s1, s2: in std_logic;
z: out std_logic);
end mux_8x1;

architecture structure of mux_8x1 is

component mux_2x1
port (in0, in1, s: in std_logic;
z: out std_logic);
end component;

signal m1, m2, m3, m4, m5, m6: std_logic;

begin
mux1: mux_2x1 port map (in0 => in0, in1 => in1, s => s0, z => m1);
mux2: mux_2x1 port map (in0 => in2, in1 => in3, s => s0, z => m2);
mux3: mux_2x1 port map (in0 => in4, in1 => in5, s => s0, z => m3);
mux4: mux_2x1 port map (in0 => in6, in1 => in7, s => s0, z => m4);
mux5: mux_2x1 port map (in0 => m1, in1 => m2, s => s1, z => m5);
mux6: mux_2x1 port map (in0 => m3, in1 => m4, s => s1, z => m6);
mux7: mux_2x1 port map (in0 => m5, in1 => m6, s => s2, z => z);

end structure;
8x1MUX using 4x1MUX:

library ieee;
use ieee.std_logic_1164.all;

entity and_gate is
port (i1, i2: in std_logic;
o1: out std_logic);
end and_gate;

architecture behavior of and_gate is


begin
o1 <= i1 and i2;
end behavior;

entity or_gate is
port (i1, i2: in std_logic;
o1: out std_logic);
end or_gate;

architecture behavior of or_gate is


begin
o1 <= i1 or i2;
end behavior;

entity not_gate is
port (i1: in std_logic;
o1: out std_logic);
end not_gate;
architecture behavior of not_gate is
begin
o1 <= not i1;
end behavior;

entity mux_2x1 is
port (in0, in1, s: in std_logic;
z: out std_logic);
end mux_2x1;

architecture structure of mux_2x1 is

component and_gate
port (i1, i2: in std_logic;
o1: out std_logic);
end component;

component or_gate
port (i1, i2: in std_logic;
o1: out std_logic);
end component;

component not_gate
port (i1: in std_logic;
o1: out std_logic);
end component;

signal not_s, and0, and1: std_logic;


begin
u1: not_gate port map (i1 => s, o1 => not_s);
u2: and_gate port map (i1 => in0, i2 => not_s, o1 => and0);
u3: and_gate port map (i1 => in1, i2 => s, o1 => and1);
u4: or_gate port map (i1 => and0, i2 => and1, o1 => z);

end structure;

entity mux_4x1 is
port (in0, in1, in2, in3: in std_logic;
s0, s1: in std_logic;
z: out std_logic);
end mux_4x1;

architecture structure of mux_4x1 is

component mux_2x1
port (in0, in1, s: in std_logic;
z: out std_logic);
end component;

signal m1, m2: std_logic;

begin
mux1: mux_2x1 port map (in0 => in0, in1 => in1, s => s0, z => m1);
mux2: mux_2x1 port map (in0 => in2, in1 => in3, s => s0, z => m2);
mux3: mux_2x1 port map (in0 => m1, in1 => m2, s => s1, z => z);
end structure;

entity mux_8x1 is
port (in0, in1, in2, in3, in4, in5, in6, in7: in std_logic;
s0, s1, s2: in std_logic;
z: out std_logic);
end mux_8x1;

architecture structure of mux_8x1 is

component mux_4x1
port (in0, in1, in2, in3: in std_logic;
s0, s1: in std_logic;
z: out std_logic);
end component;

signal m1, m2: std_logic;

begin
mux1: mux_4x1 port map (in0 => in0, in1 => in1, in2 => in2, in3 => in3, s0 => s0, s1 => s1, z
=> m1);
mux2: mux_4x1 port map (in0 => in4, in1 => in5, in2 => in6, in3 => in7, s0 => s0, s1 => s1, z
=> m2);
mux3: mux_2x1 port map (in0 => m1, in1 => m2, s => s2, z => z);

end structure;

16x1MUX using 4x1MUX:

library ieee;
use ieee.std_logic_1164.all;

entity and_gate is
port (i1, i2: in std_logic;
o1: out std_logic);
end and_gate;

architecture behavior of and_gate is


begin
o1 <= i1 and i2;
end behavior;

entity or_gate is
port (i1, i2: in std_logic;
o1: out std_logic);
end or_gate;

architecture behavior of or_gate is


begin
o1 <= i1 or i2;
end behavior;

entity not_gate is
port (i1: in std_logic;
o1: out std_logic);
end not_gate;

architecture behavior of not_gate is


begin
o1 <= not i1;
end behavior;

entity mux_2x1 is
port (in0, in1, s: in std_logic;
z: out std_logic);
end mux_2x1;

architecture structure of mux_2x1 is

component and_gate
port (i1, i2: in std_logic;
o1: out std_logic);
end component;

component or_gate
port (i1, i2: in std_logic;
o1: out std_logic);
end component;

component not_gate
port (i1: in std_logic;
o1: out std_logic);
end component;

signal not_s, and0, and1: std_logic;

begin
u1: not_gate port map (i1 => s, o1 => not_s);
u2: and_gate port map (i1 => in0, i2 => not_s, o1 => and0);
u3: and_gate port map (i1 => in1, i2 => s, o1 => and1);
u4: or_gate port map (i1 => and0, i2 => and1, o1 => z);

end structure;

entity mux_4x1 is
port (in0, in1, in2, in3: in std_logic;
s0, s1: in std_logic;
z: out std_logic);
end mux_4x1;

architecture structure of mux_4x1 is

component mux_2x1
port (in0, in1, s: in std_logic;
z: out std_logic);
end component;

signal m1, m2: std_logic;

begin
mux1: mux_2x1 port map (in0 => in0, in1 => in1, s => s0, z => m1);
mux2: mux_2x1 port map (in0 => in2, in1 => in3, s => s0, z => m2);
mux3: mux_2x1 port map (in0 => m1, in1 => m2, s => s1, z => z);

end structure;

entity mux_16x1 is
port (in0, in1, in2, in3, in4, in5, in6, in7, in8, in9, in10, in11, in12, in13, in14, in15: in
std_logic;
s0, s1, s2, s3: in std_logic;
z: out std_logic);
end mux_16x1;

architecture structure of mux_16x1 is

component mux_4x1
port (in0, in1, in2, in3: in std_logic;
s0, s1: in std_logic;
z: out std_logic);
end component;

signal m1, m2, m3, m4: std_logic;

begin
mux1: mux_4x1 port map (in0 => in0, in1 => in1, in2 => in2, in3 => in3, s0 => s0, s1 => s1, z
=> m1);
mux2: mux_4x1 port map (in0 => in4, in1 => in5, in2 => in6, in3 => in7, s0 => s0, s1 => s1, z
=> m2);
mux3: mux_4x1 port map (in0 => in8, in1 => in9, in2 => in10, in3 => in11, s0 => s0, s1 =>
s1, z => m3);
mux4: mux_4x1 port map (in0 => in12, in1 => in13, in2 => in14, in3 => in15, s0 => s0, s1 =>
s1, z => m4);
mux5: mux_4x1 port map (in0 => m1, in1 => m2, in2 => m3, in3 => m4, s0 => s2, s1 => s3,
z => z);

end structure;
1x4Demux using 1x2Demux:

library ieee;
use ieee.std_logic_1164.all;

entity and_gate is
port (i1, i2: in std_logic;
o1: out std_logic);
end and_gate;

architecture behavior of and_gate is


begin
o1 <= i1 and i2;
end behavior;

entity not_gate is
port (i1: in std_logic;
o1: out std_logic);
end not_gate;

architecture behavior of not_gate is


begin
o1 <= not i1;
end behavior;

entity demux_1x2 is
port (a, s: in std_logic;
y0, y1: out std_logic);
end demux_1x2;
architecture structure of demux_1x2 is

component and_gate
port (i1, i2: in std_logic;
o1: out std_logic);
end component;

component not_gate
port (i1: in std_logic;
o1: out std_logic);
end component;

signal not_s: std_logic;

begin
u1: not_gate port map (i1 => s, o1 => not_s);
u2: and_gate port map (i1 => a, i2 => not_s, o1 => y0);
u3: and_gate port map (i1 => a, i2 => s, o1 => y1);

end structure;

entity demux_1x4 is
port (a: in std_logic;
s0, s1: in std_logic;
y0, y1, y2, y3: out std_logic);
end demux_1x4;

architecture structure of demux_1x4 is


component demux_1x2
port (a, s: in std_logic;
y0, y1: out std_logic);
end component;

signal d1, d2: std_logic;

begin
demux1: demux_1x2 port map (a => a, s => s1, y0 => d1, y1 => d2);
demux2: demux_1x2 port map (a => d1, s => s0, y0 => y0, y1 => y1);
demux3: demux_1x2 port map (a => d2, s => s0, y0 => y2, y1 => y3);

end structure;

1x8Demux using 1x2Demux:

library ieee;
use ieee.std_logic_1164.all;

entity and_gate is
port (i1, i2: in std_logic;
o1: out std_logic);
end and_gate;

architecture behavior of and_gate is


begin
o1 <= i1 and i2;
end behavior;
entity not_gate is
port (i1: in std_logic;
o1: out std_logic);
end not_gate;

architecture behavior of not_gate is


begin
o1 <= not i1;
end behavior;

entity demux_1x2 is
port (a, s: in std_logic;
y0, y1: out std_logic);
end demux_1x2;

architecture structure of demux_1x2 is

component and_gate
port (i1, i2: in std_logic;
o1: out std_logic);
end component;

component not_gate
port (i1: in std_logic;
o1: out std_logic);
end component;

signal not_s: std_logic;


begin
u1: not_gate port map (i1 => s, o1 => not_s);
u2: and_gate port map (i1 => a, i2 => not_s, o1 => y0);
u3: and_gate port map (i1 => a, i2 => s, o1 => y1);

end structure;

entity demux_1x8 is
port (a: in std_logic;
s0, s1, s2: in std_logic;
y0, y1, y2, y3, y4, y5, y6, y7: out std_logic);
end demux_1x8;

architecture structure of demux_1x8 is

component demux_1x2
port (a, s: in std_logic;
y0, y1: out std_logic);
end component;

signal d1, d2, d3, d4, d5, d6: std_logic;

begin
demux1: demux_1x2 port map (a => a, s => s2, y0 => d1, y1 => d2);
demux2: demux_1x2 port map (a => d1, s => s1, y0 => d3, y1 => d4);
demux3: demux_1x2 port map (a => d2, s => s1, y0 => d5, y1 => d6);
demux4: demux_1x2 port map (a => d3, s => s0, y0 => y0, y1 => y1);
demux5: demux_1x2 port map (a => d4, s => s0, y0 => y2, y1 => y3);
demux6: demux_1x2 port map (a => d5, s => s0, y0 => y4, y1 => y5);
demux7: demux_1x2 port map (a => d6, s => s0, y0 => y6, y1 => y7);

end structure;

1x8 Demux using 1x4 Demux:

library ieee;
use ieee.std_logic_1164.all;

entity and_gate is
port (i1, i2: in std_logic;
o1: out std_logic);
end and_gate;

architecture behavior of and_gate is


begin
o1 <= i1 and i2;
end behavior;

entity not_gate is
port (i1: in std_logic;
o1: out std_logic);
end not_gate;

architecture behavior of not_gate is


begin
o1 <= not i1;
end behavior;
entity demux_1x2 is
port (a, s: in std_logic;
y0, y1: out std_logic);
end demux_1x2;

architecture structure of demux_1x2 is

component and_gate
port (i1, i2: in std_logic;
o1: out std_logic);
end component;

component not_gate
port (i1: in std_logic;
o1: out std_logic);
end component;

signal not_s: std_logic;

begin
u1: not_gate port map (i1 => s, o1 => not_s);
u2: and_gate port map (i1 => a, i2 => not_s, o1 => y0);
u3: and_gate port map (i1 => a, i2 => s, o1 => y1);

end structure;

entity demux_1x4 is
port (a: in std_logic;
s0, s1: in std_logic;
y0, y1, y2, y3: out std_logic);
end demux_1x4;

architecture structure of demux_1x4 is

component demux_1x2
port (a, s: in std_logic;
y0, y1: out std_logic);
end component;

signal d1, d2: std_logic;

begin
demux1: demux_1x2 port map (a => a, s => s1, y0 => d1, y1 => d2);
demux2: demux_1x2 port map (a => d1, s => s0, y0 => y0, y1 => y1);
demux3: demux_1x2 port map (a => d2, s => s0, y0 => y2, y1 => y3);

end structure;

entity demux_1x8 is
port (a: in std_logic;
s0, s1, s2: in std_logic;
y0, y1, y2, y3, y4, y5, y6, y7: out std_logic);
end demux_1x8;

architecture structure of demux_1x8 is

component demux_1x4
port (a: in std_logic;
s0, s1: in std_logic;
y0, y1, y2, y3: out std_logic);
end component;

signal d1, d2, d3, d4: std_logic;

begin
demux1: demux_1x4 port map (a => a, s0 => s2, s1 => s1, y0 => d1, y1 => d2, y2 => d3, y3
=> d4);
demux2: demux_1x2 port map (a => d1, s => s0, y0 => y0, y1 => y1);
demux3: demux_1x2 port map (a => d2, s => s0, y0 => y2, y1 => y3);
demux4: demux_1x2 port map (a => d3, s => s0, y0 => y4, y1 => y5);
demux5: demux_1x2 port map (a => d4, s => s0, y0 => y6, y1 => y7);

end structure;

1x16 Demux using 1x4 Demux:

library ieee;
use ieee.std_logic_1164.all;

entity and_gate is
port (i1, i2: in std_logic;
o1: out std_logic);
end and_gate;

architecture behavior of and_gate is


begin
o1 <= i1 and i2;
end behavior;

entity not_gate is
port (i1: in std_logic;
o1: out std_logic);
end not_gate;

architecture behavior of not_gate is


begin
o1 <= not i1;
end behavior;

entity demux_1x2 is
port (a, s: in std_logic;
y0, y1: out std_logic);
end demux_1x2;

architecture structure of demux_1x2 is

component and_gate
port (i1, i2: in std_logic;
o1: out std_logic);
end component;

component not_gate
port (i1: in std_logic;
o1: out std_logic);
end component;
signal not_s: std_logic;

begin
u1: not_gate port map (i1 => s, o1 => not_s);
u2: and_gate port map (i1 => a, i2 => not_s, o1 => y0);
u3: and_gate port map (i1 => a, i2 => s, o1 => y1);

end structure;

entity demux_1x4 is
port (a: in std_logic;
s0, s1: in std_logic;
y0, y1, y2, y3: out std_logic);
end demux_1x4;

architecture structure of demux_1x4 is

component demux_1x2
port (a, s: in std_logic;
y0, y1: out std_logic);
end component;

signal d1, d2: std_logic;

begin
demux1: demux_1x2 port map (a => a, s => s1, y0 => d1, y1 => d2);
demux2: demux_1x2 port map (a => d1, s => s0, y0 => y0, y1 => y1);
demux3: demux_1x2 port map (a => d2, s => s0, y0 => y2, y1 => y3);
end structure;

entity demux_1x16 is
port (a: in std_logic;
s0, s1, s2, s3: in std_logic;
y0, y1, y2, y3, y4, y5, y6, y7, y8, y9, y10, y11, y12, y13, y14, y15: out std_logic);
end demux_1x16;

architecture structure of demux_1x16 is

component demux_1x4
port (a: in std_logic;
s0, s1: in std_logic;
y0, y1, y2, y3: out std_logic);
end component;

signal d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12, d13, d14, d15: std_logic;

begin
demux1: demux_1x4 port map (a => a, s0 => s3, s1 => s2, y0 => d1, y1 => d2, y2 => d3, y3
=> d4);
demux2: demux_1x4 port map (a => d1, s0 => s1, s1 => s0, y0 => y0, y1 => y1, y2 => y2, y3
=> y3);
demux3: demux_1x4 port map (a => d2, s0 => s1, s1 => s0, y0 => y4, y1 => y5, y2 => y6, y3
=> y7);
demux4: demux_1x4 port map (a => d3, s0 => s1, s1 => s0, y0 => y8, y1 => y9, y2 => y10,
y3 => y11);
demux5: demux_1x4 port map (a => d4, s0 => s1, s1 => s0, y0 => y12, y1 => y13, y2 =>
y14, y3 => y15);
end structure;

1x4 DeMUX using 1x2 DeMUX

library ieee;
use ieee.std_logic_1164.all;

entity and_gate is
port (i1, i2: in std_logic;
o1: out std_logic);
end and_gate;

architecture behavior of and_gate is


begin
o1 <= i1 and i2;
end behavior;

entity not_gate is
port (i1: in std_logic;
o1: out std_logic);
end not_gate;

architecture behavior of not_gate is


begin
o1 <= not i1;
end behavior;

entity demux_1x2 is
port (a, s: in std_logic;
y0, y1: out std_logic);
end demux_1x2;

architecture structure of demux_1x2 is

component and_gate
port (i1, i2: in std_logic;
o1: out std_logic);
end component;

component not_gate
port (i1: in std_logic;
o1: out std_logic);
end component;

signal not_s: std_logic;

begin
u1: not_gate port map (i1 => s, o1 => not_s);
u2: and_gate port map (i1 => a, i2 => not_s, o1 => y0);
u3: and_gate port map (i1 => a, i2 => s, o1 => y1);

end structure;

entity demux_1x4 is
port (a: in std_logic;
s0, s1: in std_logic;
y0, y1, y2, y3: out std_logic);
end demux_1x4;

architecture structure of demux_1x4 is

component demux_1x2
port (a, s: in std_logic;
y0, y1: out std_logic);
end component;

signal d1, d2: std_logic;

begin
demux1: demux_1x2 port map (a => a, s => s1, y0 => d1, y1 => d2);
demux2: demux_1x2 port map (a => d1, s => s0, y0 => y0, y1 => y1);
demux3: demux_1x2 port map (a => d2, s => s0, y0 => y2, y1 => y3);

end structure;

1x8 DeMUX using 1x2 DeMUX

library ieee;
use ieee.std_logic_1164.all;

entity and_gate is
port (i1, i2: in std_logic;
o1: out std_logic);
end and_gate;

architecture behavior of and_gate is


begin
o1 <= i1 and i2;
end behavior;

entity not_gate is
port (i1: in std_logic;
o1: out std_logic);
end not_gate;

architecture behavior of not_gate is


begin
o1 <= not i1;
end behavior;

entity demux_1x2 is
port (a, s: in std_logic;
y0, y1: out std_logic);
end demux_1x2;

architecture structure of demux_1x2 is

component and_gate
port (i1, i2: in std_logic;
o1: out std_logic);
end component;

component not_gate
port (i1: in std_logic;
o1: out std_logic);
end component;

signal not_s: std_logic;

begin
u1: not_gate port map (i1 => s, o1 => not_s);
u2: and_gate port map (i1 => a, i2 => not_s, o1 => y0);
u3: and_gate port map (i1 => a, i2 => s, o1 => y1);

end structure;

entity demux_1x8 is
port (a: in std_logic;
s0, s1, s2: in std_logic;
y0, y1, y2, y3, y4, y5, y6, y7: out std_logic);
end demux_1x8;

architecture structure of demux_1x8 is

component demux_1x2
port (a, s: in std_logic;
y0, y1: out std_logic);
end component;

signal d1, d2, d3, d4, d5, d6: std_logic;

begin
demux1: demux_1x2 port map (a => a, s => s2, y0 => d1, y1 => d2);
demux2: demux_1x2 port map (a => d1, s => s1, y0 => d3, y1 => d4);
demux3: demux_1x2 port map (a => d2, s => s1, y0 => d5, y1 => d6);
demux4: demux_1x2 port map (a => d3, s => s0, y0 => y0, y1 => y1);
demux5: demux_1x2 port map (a => d4, s => s0, y0 => y2, y1 => y3);
demux6: demux_1x2 port map (a => d5, s => s0, y0 => y4, y1 => y5);
demux7: demux_1x2 port map (a => d6, s => s0, y0 => y6, y1 => y7);

end structure;

1x8 DeMUX using 1x4 DeMUX

library ieee;
use ieee.std_logic_1164.all;

entity and_gate is
port (i1, i2: in std_logic;
o1: out std_logic);
end and_gate;

architecture behavior of and_gate is


begin
o1 <= i1 and i2;
end behavior;

entity not_gate is
port (i1: in std_logic;
o1: out std_logic);
end not_gate;

architecture behavior of not_gate is


begin
o1 <= not i1;
end behavior;

entity demux_1x2 is
port (a, s: in std_logic;
y0, y1: out std_logic);
end demux_1x2;

architecture structure of demux_1x2 is

component and_gate
port (i1, i2: in std_logic;
o1: out std_logic);
end component;

component not_gate
port (i1: in std_logic;
o1: out std_logic);
end component;

signal not_s: std_logic;

begin
u1: not_gate port map (i1 => s, o1 => not_s);
u2: and_gate port map (i1 => a, i2 => not_s, o1 => y0);
u3: and_gate port map (i1 => a, i2 => s, o1 => y1);

end structure;
entity demux_1x4 is
port (a: in std_logic;
s0, s1: in std_logic;
y0, y1, y2, y3: out std_logic);
end demux_1x4;

architecture structure of demux_1x4 is

component demux_1x2
port (a, s: in std_logic;
y0, y1: out std_logic);
end component;

signal d1, d2: std_logic;

begin
demux1: demux_1x2 port map (a => a, s => s1, y0 => d1, y1 => d2);
demux2: demux_1x2 port map (a => d1, s => s0, y0 => y0, y1 => y1);
demux3: demux_1x2 port map (a => d2, s => s0, y0 => y2, y1 => y3);

end structure;

entity demux_1x8 is
port (a: in std_logic;
s0, s1, s2: in std_logic;
y0, y1, y2, y3, y4, y5, y6, y7: out std_logic);
end demux_1x8;
architecture structure of demux_1x8 is

component demux_1x4
port (a: in std_logic;
s0, s1: in std_logic;
y0, y1, y2, y3: out std_logic);
end component;

signal d1, d2, d3, d4: std_logic;

begin
demux1: demux_1x4 port map (a => a, s0 => s2, s1 => s1, y0 => d1, y1 => d2, y2 => d3, y3
=> d4);
demux2: demux_1x2 port map (a => d1, s => s0, y0 => y0, y1 => y1);
demux3: demux_1x2 port map (a => d2, s => s0, y0 => y2, y1 => y3);
demux4: demux_1x2 port map (a => d3, s => s0, y0 => y4, y1 => y5);
demux5: demux_1x2 port map (a => d4, s => s0, y0 => y6, y1 => y7);

end structure;

1x16demux using 1x4demux

library ieee;
use ieee.std_logic_1164.all;

entity and_gate is
port (i1, i2: in std_logic;
o1: out std_logic);
end and_gate;
architecture behavior of and_gate is
begin
o1 <= i1 and i2;
end behavior;

entity not_gate is
port (i1: in std_logic;
o1: out std_logic);
end not_gate;

architecture behavior of not_gate is


begin
o1 <= not i1;
end behavior;

entity demux_1x2 is
port (a, s: in std_logic;
y0, y1: out std_logic);
end demux_1x2;

architecture structure of demux_1x2 is

component and_gate
port (i1, i2: in std_logic;
o1: out std_logic);
end component;

component not_gate
port (i1: in std_logic;
o1: out std_logic);
end component;

signal not_s: std_logic;

begin
u1: not_gate port map (i1 => s, o1 => not_s);
u2: and_gate port map (i1 => a, i2 => not_s, o1 => y0);
u3: and_gate port map (i1 => a, i2 => s, o1 => y1);

end structure;

entity demux_1x4 is
port (a: in std_logic;
s0, s1: in std_logic;
y0, y1, y2, y3: out std_logic);
end demux_1x4;

architecture structure of demux_1x4 is

component demux_1x2
port (a, s: in std_logic;
y0, y1: out std_logic);
end component;

signal d1, d2: std_logic;

begin
demux1: demux_1x2 port map (a => a, s => s1, y0 => d1, y1 => d2);
demux2: demux_1x2 port map (a => d1, s => s0, y0 => y0, y1 => y1);
demux3: demux_1x2 port map (a => d2, s => s0, y0 => y2, y1 => y3);

end structure;

entity demux_1x16 is
port (a: in std_logic;
s0, s1, s2, s3: in std_logic;
y0, y1, y2, y3, y4, y5, y6, y7, y8, y9, y10, y11, y12, y13, y14, y15: out std_logic);
end demux_1x16;

architecture structure of demux_1x16 is

component demux_1x4
port (a: in std_logic;
s0, s1: in std_logic;
y0, y1, y2, y3: out std_logic);
end component;

signal d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12, d13, d14, d15: std_logic;

begin
demux1: demux_1x4 port map (a => a, s0 => s3, s1 => s2, y0 => d1, y1 => d2, y2 => d3, y3
=> d4);
demux2: demux_1x4 port map (a => d1, s0 => s1, s1 => s0, y0 => y0, y1 => y1, y2 => y2, y3
=> y3);
demux3: demux_1x4 port map (a => d2, s0 => s1, s1 => s0, y0 => y4, y1 => y5, y2 => y6, y3
=> y7);
demux4: demux_1x4 port map (a => d3, s0 => s1, s1 => s0, y0 => y8, y1 => y9, y2 => y10,
y3 => y11);
demux5: demux_1x4 port map (a => d4, s0 => s1, s1 => s0, y0 => y12, y1 => y13, y2 =>
y14, y3 => y15);

end structure;

3x8Decoder using 2x4 Decoder:

library ieee;
use ieee.std_logic_1164.all;

entity and_gate is
port (i1, i2: in std_logic;
o1: out std_logic);
end and_gate;

architecture behavior of and_gate is


begin
o1 <= i1 and i2;
end behavior;

entity not_gate is
port (i1: in std_logic;
o1: out std_logic);
end not_gate;

architecture behavior of not_gate is


begin
o1 <= not i1;
end behavior;
entity decoder_2x4 is
port (input: in std_logic_vector(1 downto 0);
en: in std_logic;
output: out std_logic_vector(3 downto 0));
end decoder_2x4;

architecture structure of decoder_2x4 is

component and_gate
port (i1, i2: in std_logic;
o1: out std_logic);
end component;

component not_gate
port (i1: in std_logic;
o1: out std_logic);
end component;

signal not_a, not_b: std_logic;

begin
-- Invert input bits
u1: not_gate port map (i1 => input(1), o1 => not_a);
u2: not_gate port map (i1 => input(0), o1 => not_b);

-- AND gates for each output condition


u3: and_gate port map (i1 => not_a, i2 => not_b, o1 => output(0));
u4: and_gate port map (i1 => not_a, i2 => input(0), o1 => output(1));
u5: and_gate port map (i1 => input(1), i2 => not_b, o1 => output(2));
u6: and_gate port map (i1 => input(1), i2 => input(0), o1 => output(3));

-- Enable logic for each output


u7: and_gate port map (i1 => output(0), i2 => en, o1 => output(0));
u8: and_gate port map (i1 => output(1), i2 => en, o1 => output(1));
u9: and_gate port map (i1 => output(2), i2 => en, o1 => output(2));
u10: and_gate port map (i1 => output(3), i2 => en, o1 => output(3));

end structure;

entity decoder_3x8 is
port (input: in std_logic_vector(2 downto 0);
output: out std_logic_vector(7 downto 0));
end decoder_3x8;

architecture structure of decoder_3x8 is

component decoder_2x4
port (input: in std_logic_vector(1 downto 0);
en: in std_logic;
output: out std_logic_vector(3 downto 0));
end component;

component and_gate
port (i1, i2: in std_logic;
o1: out std_logic);
end component;

component not_gate
port (i1: in std_logic;
o1: out std_logic);
end component;

signal not_c, d, e: std_logic_vector(3 downto 0);

begin
-- Invert c for the second decoder enable
u1: not_gate port map (i1 => input(2), o1 => not_c);

-- First 2x4 decoder with c as enable


dec1: decoder_2x4 port map (input => input(1 downto 0), en => input(2), output => d);

-- Second 2x4 decoder with NOT c as enable


dec2: decoder_2x4 port map (input => input(1 downto 0), en => not_c, output => e);

-- AND gates to combine outputs


u2: and_gate port map (i1 => d(0), i2 => input(2), o1 => output(0));
u3: and_gate port map (i1 => d(1), i2 => input(2), o1 => output(1));
u4: and_gate port map (i1 => d(2), i2 => input(2), o1 => output(2));
u5: and_gate port map (i1 => d(3), i2 => input(2), o1 => output(3));
u6: and_gate port map (i1 => e(0), i2 => not_c, o1 => output(4));
u7: and_gate port map (i1 => e(1), i2 => not_c, o1 => output(5));
u8: and_gate port map (i1 => e(2), i2 => not_c, o1 => output(6));
u9: and_gate port map (i1 => e(3), i2 => not_c, o1 => output(7));

end structure;
4x16Decoder using 2x4Decoder:

library ieee;
use ieee.std_logic_1164.all;

entity and_gate is
port (i1, i2: in std_logic;
o1: out std_logic);
end and_gate;

architecture behavior of and_gate is


begin
o1 <= i1 and i2;
end behavior;

entity not_gate is
port (i1: in std_logic;
o1: out std_logic);
end not_gate;

architecture behavior of not_gate is


begin
o1 <= not i1;
end behavior;

entity decoder_2x4 is
port (a, b: in std_logic;
en: in std_logic;
y0, y1, y2, y3: out std_logic);
end decoder_2x4;

architecture structure of decoder_2x4 is

component and_gate
port (i1, i2: in std_logic;
o1: out std_logic);
end component;

component not_gate
port (i1: in std_logic;
o1: out std_logic);
end component;

signal not_a, not_b: std_logic;

begin
-- Invert inputs
u1: not_gate port map (i1 => a, o1 => not_a);
u2: not_gate port map (i1 => b, o1 => not_b);

-- AND gates for each output


u3: and_gate port map (i1 => not_a, i2 => not_b, o1 => y0);
u4: and_gate port map (i1 => not_a, i2 => b, o1 => y1);
u5: and_gate port map (i1 => a, i2 => not_b, o1 => y2);
u6: and_gate port map (i1 => a, i2 => b, o1 => y3);

-- Enable logic for each output


u7: and_gate port map (i1 => y0, i2 => en, o1 => y0);
u8: and_gate port map (i1 => y1, i2 => en, o1 => y1);
u9: and_gate port map (i1 => y2, i2 => en, o1 => y2);
u10: and_gate port map (i1 => y3, i2 => en, o1 => y3);

end structure;

entity decoder_4x16 is
port (a, b, c, d: in std_logic;
y0, y1, y2, y3, y4, y5, y6, y7, y8, y9, y10, y11, y12, y13, y14, y15: out std_logic);
end decoder_4x16;

architecture structure of decoder_4x16 is

component decoder_2x4
port (a, b: in std_logic;
en: in std_logic;
y0, y1, y2, y3: out std_logic);
end component;

component and_gate
port (i1, i2: in std_logic;
o1: out std_logic);
end component;

signal not_d, d0, d1, d2, d3, e0, e1, e2, e3: std_logic_vector(3 downto 0);

begin
u1: not_gate port map (i1 => d, o1 => not_d);
dec1: decoder_2x4 port map (a => a, b => b, en => c, y0 => d0(0), y1 => d0(1), y2 => d0(2),
y3 => d0(3));
dec2: decoder_2x4 port map (a => a, b => b, en => not_d, y0 => e0(0), y1 => e0(1), y2 =>
e0(2), y3 => e0(3));
dec3: decoder_2x4 port map (a => c, b => d, en => '1', y0 => d1(0), y1 => d1(1), y2 =>
d1(2), y3 => d1(3));
dec4: decoder_2x4 port map (a => c, b => not_d, en => '1', y0 => e1(0), y1 => e1(1), y2 =>
e1(2), y3 => e1(3));

-- Combine outputs with AND gates


gen_and_gates: for i in 0 to 3 generate
u_and1: and_gate port map (i1 => d0(i), i2 => d1(i), o1 => y0 + i*4);
u_and2: and_gate port map (i1 => d0(i), i2 => e1(i), o1 => y1 + i*4);
u_and3: and_gate port map (i1 => e0(i), i2 => d1(i), o1 => y2 + i*4);
u_and4: and_gate port map (i1 => e0(i), i2 => e1(i), o1 => y3 + i*4);
end generate gen_and_gates;

end structure;

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