EX.

NO: DESIGN ENTRY, SIMULATION AND IMPLEMENTATION OF UP DOWN

AIM:
To design, Simulate and Implement Up Down Counter using XILINX ISE Software
and FPGA Board.

TOOLS REQUIRED:
1. Personal Computer
2. XILINX Software
3. FPGA Spartan-3E Starter Board(XC3S250E TQ144)

SIMULATION PROGRAM (UP DOWN COUNTER):

\\Up down counter

input clk,rst,mode;

output [3:0]q;

counterdddk a2(clk,rst,mode,q);

endmodule

\\Counter

module counterdddk(clk,rst,mode,q);

input clk,rst,mode;

output reg[3:0]q;

always@(posedge clk)

begin

if(rst)

q=4'b0000;

else if(mode==1'b0)

q=q+1;

else

Reg.No:61072112113
q=q-1;

end

endmodule

IMPLEMENTATION PROGRAM(UP DOWN COUNTER):

\\Updown counter
module updowncounter(clk,rst,mode,q);

input clk,rst,mode;

output [3:0]q;

clk_divdddk a1(clk,slow_clk);

counterdddk a2(clk,rst,mode,q);

endmodule

\\Clock division

module clk_div(

input clk,

output reg slow_clk);

reg [26:0] c;

initial c = 27'b0;

always @(posedge clk)

begin

c = c + 1;

slow_clk = c[25];

end

endmodule

Reg.No:61072112113
\\Counter

module counterdddk(clk,rst,mode,q);

input clk,rst,mode;

output reg[3:0]q;

always@(posedge clk)

begin

if(rst)

q=4'b0000;

else if(mode==1'b0)

q=q+1;

else

q=q-1;

end

endmodule

PIN ASSIGNMENTS:

//Pin Assignments(Locations Assigning) for Up Down Counter

Reg.No:61072112113
RTL SCHEMATIC(UP DOWN COUNTER):

TECHNOLOGY SCHEMATIC(UP DOWN COUNTER):

Reg.No:61072112113
SYNTHESIS SUMMARY:
Device utilization summary:

---------------------------

Selected Device : 7a100tcsg324-3

Slice Logic Utilization:

Number of Slice Registers: 4 out of 126800 0%

Number of Slice LUTs: 4 out of 63400 0%

Number used as Logic: 4 out of 63400 0%

Slice Logic Distribution:

Number of LUT Flip Flop pairs used: 8

Number with an unused Flip Flop: 4 out of 8 50%

Number with an unused LUT: 4 out of 8 50%

Number of fully used LUT-FF pairs: 0 out of 8 0%

Number of unique control sets: 1

IO Utilization:

Number of IOs: 7

Number of bonded IOBs: 7 out of 210 3%

Specific Feature Utilization:

Number of BUFG/BUFGCTRLs: 1 out of 32 3%

---------------------------

Partition Resource Summary:

---------------------------

Reg.No:61072112113
 No Partitions were found in this design.

---------------------------

=========================================================================

Timing Report

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT

GENERATED AFTER PLACE-and-ROUTE.

Clock Information:

------------------

-----------------------------------+------------------------+-------+

Clock Signal | Clock buffer(FF name) | Load |

-----------------------------------+------------------------+-------+

clk | BUFGP |4 |

-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:

----------------------------------------

No asynchronous control signals found in this design

Timing Summary:

---------------

Speed Grade: -3

Reg.No:61072112113
 Minimum period: 1.059ns (Maximum Frequency: 943.842MHz)

Minimum input arrival time before clock: 0.799ns

Maximum output required time after clock: 0.659ns

Maximum combinational path delay: No path found

Timing Details:

---------------

All values displayed in nanoseconds (ns)

=========================================================================

Timing constraint: Default period analysis for Clock 'clk'

Clock period: 1.059ns (frequency: 943.842MHz)

Total number of paths / destination ports: 10 / 4

-------------------------------------------------------------------------

Delay: 1.059ns (Levels of Logic = 1)

Source: a2/q_0 (FF)

Destination: a2/q_0 (FF)

Source Clock: clk rising

Destination Clock: clk rising

Data Path: a2/q_0 to a2/q_0

Gate Net

Cell:in->out fanout Delay Delay Logical Name (Net Name)

---------------------------------------- ------------

FDR:C->Q 5 0.361 0.298 a2/q_0 (a2/q_0)

INV:I->O 1 0.113 0.279 Result<0>1_INV_0 (Result<0>)

FDR:D 0.008 a2/q_0

Reg.No:61072112113
 ----------------------------------------

Total 1.059ns (0.482ns logic, 0.577ns route)

(45.5% logic, 54.5% route)

=========================================================================

Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'

Total number of paths / destination ports: 7 / 7

-------------------------------------------------------------------------

Offset: 0.799ns (Levels of Logic = 2)

Source: mode (PAD)

Destination: a2/q_3 (FF)

Destination Clock: clk rising

Data Path: mode to a2/q_3

Gate Net

Cell:in->out fanout Delay Delay Logical Name (Net Name)

---------------------------------------- ------------

IBUF:I->O 3 0.001 0.693 mode_IBUF (a2/mode_GND_2_o_equal_2_o_inv)

LUT5:I0->O 1 0.097 0.000 Result<3>1 (Result<3>)

FDR:D 0.008 a2/q_3

----------------------------------------

Total 0.799ns (0.106ns logic, 0.693ns route)

(13.3% logic, 86.7% route)

=========================================================================

Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'

Total number of paths / destination ports: 4 / 4

-------------------------------------------------------------------------

Reg.No:61072112113
Offset: 0.659ns (Levels of Logic = 1)

Source: a2/q_0 (FF)

Destination: q<0> (PAD)

Source Clock: clk rising

Data Path: a2/q_0 to q<0>

Gate Net

Cell:in->out fanout Delay Delay Logical Name (Net Name)

---------------------------------------- ------------

FDR:C->Q 5 0.361 0.298 a2/q_0 (a2/q_0)

OBUF:I->O 0.000 q_0_OBUF (q<0>)

----------------------------------------

Total 0.659ns (0.361ns logic, 0.298ns route)

(54.8% logic, 45.2% route)

=========================================================================

Cross Clock Domains Report:

--------------------------

Clock to Setup on destination clock clk

---------------+---------+---------+---------+---------+

| Src:Rise| Src:Fall| Src:Rise| Src:Fall|

Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|

---------------+---------+---------+---------+---------+

clk | 1.059| | | |

---------------+---------+---------+---------+---------+

Reg.No:61072112113
=========================================================================

Total REAL time to Xst completion: 9.00 secs

Total CPU time to Xst completion: 8.25 secs

-->

Total memory usage is 4616796 kilobytes

Number of errors : 0 ( 0 filtered)

Number of warnings : 2 ( 0 filtered)

Number of infos : 0 ( 0 filtered)

Reg.No:61072112113
SIMULATION OUTPUT:

RESULT:
Thus UpDown Counter is designed and Simulation is done using XILINX ISE
Software and Implementation is done using FPGA Spartan-3E Starter Board.

Reg.No:61072112113
Reg.No:61072112113