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Addressing Modes in 8085

The document discusses the addressing modes in the 8085 microprocessor, categorizing them into five types: Immediate, Direct, Register, Register Indirect, and Implied/Implicit Addressing Modes. Each mode is explained with its characteristics, instruction sizes, and examples of operations. This overview is aimed at understanding how data is transferred between registers and memory in the 8085 architecture.

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0% found this document useful (0 votes)
9 views3 pages

Addressing Modes in 8085

The document discusses the addressing modes in the 8085 microprocessor, categorizing them into five types: Immediate, Direct, Register, Register Indirect, and Implied/Implicit Addressing Modes. Each mode is explained with its characteristics, instruction sizes, and examples of operations. This overview is aimed at understanding how data is transferred between registers and memory in the 8085 architecture.

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lOMoARcPSD|17517997

Addressing Modes in 8085

Bachelor of Computer Applications (Mahatma Gandhi University)

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Addressing Modes in 8085

These are the instructions used to transfer the data from one
register to another register, from the memory to the register, and
from the register to the memory without any alteration in the
content. Addressing modes in 8085 is classified into 5 groups
1. Immediate Addressing Mode

In immediate addressing mode the source operand is always


data. If the data is 8-bit, then the instruction will be of 2
bytes, if the data is of 16-bit then the instruction will be of 3
bytes.
Examples:
MVI B 45 (move the data 45H immediately to register B)
LXI H 3050 (load the H-L pair with the operand 3050H
immediately)
JMP address (jump to the operand address immediately)

2. Direct addressing mode

In this mode, the data is directly copied from the given address
to the register,the data to be operated is available inside a
memory location and that memory location is directly specified
as an operand. The operand is directly available in the
instruction itself. The size of an instruction in the direct
addressing mode is 3 bytes. Input/output instructions in direct
addressing mode are 2 bytes.
Examples:
LDA 2050 (load the contents of memory location into
accumulator A)
LHLD address (load contents of 16-bit memory location into
H-L register pair)
IN 35 (read the data from port whose address is 35)

3. Register Addressing Mode


In this addressing mode, the instruction mentions a register
which stores some data
In register addressing mode, the data to be operated is
available inside the register and register is operands. The
instruction can also specify two registers. The size of the
instructions in register addressing mode is 1 byte. The
instruction’s opcode includes both the register and the

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lOMoARcPSD|17517997

operation to be performed .Therefore the operation is


performed within various registers of the microprocessor.
Examples:
MOV A, B (move the contents of register B to register A)
ADD B (add contents of registers A and B and store the result
in register A)
INR A (increment the contents of register A by one)
4. Register Indirect Addressing Mode –
In register indirect addressing mode, the data to be operated
is available inside a memory location and that memory
location is indirectly specified by a register pair.
Examples:
MOV A, M (move the contents of the memory location pointed
by the H-L pair to the accumulator)
LDAX B (move contents of B-C register to the accumulator)
STAX B (store accumulator contents in memory pointed by
register pair B-C)
.
5. Implied/Implicit Addressing Mode

In implied/implicit addressing mode the operand is hidden


and the data to be operated is available in the instruction
itself. That is the operand is described implicitly in the
definition of the instruction. The size of an implied addressing
mode instruction is 1 byte. The instructions generally operate
on data stored in the accumulator
Examples:
CMP
CMA (finds and stores the 1’s complement of the contents of
accumulator A in A)
RRC (rotate accumulator A right by one bit)
RLC (rotate accumulator A left by one bit)

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