Spring 2025

Computer Organization and Architecture

(CSE 214)

Topic – 4:
Arithmetic for Computers

Course Teacher:
Dr. Md. Tarek Habib
Assistant Professor
Department of Computer Science and Engineering
 Reference Book

• “Computer Organization and Design – The

Hardware/Software Interface,” David A.
Patterson and John L. Hennessy, 5th
Edt., Elsevier.

☞ Chapter 3 (Arithmetic for Computers)

2
 Topic Contents
• Introduction [Sec. – 3.1]

• Overview of Signed Numbers

• Addition and Subtraction [Sec. – 3.2]

• Multiplication [Sec. - 3.3]

• Division [Sec. – 3.4]

• Floating Point [Sec. – 3.5]

3
 The Five Classic
Components of A Computer

4
• Section 3.1:

Introduction

5
 Arithmetic
■ Where we've been:
■ evolution
■ performance
■ abstractions
■ instruction set architecture
■ assembly language and machine language
■ What's up ahead:
■ implementing the architecture
operation

32 ALU
result
32
b

32
6
 Numbers
■ Bits are just bits (no inherent meaning)
■ conventions define the relationship between bits and numbers
■ Binary integers (base 2)
■ 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001...

n
n bits
■ decimal: 0, …, 2 -1
■ How do we represent negative integers?
■ which bit patterns will represent which integers?

■ How do we represent real (fractional) numbers?

■ are finitely many bits enough for representing all real (fractional)
numbers?

7
• Section 3.X:

Overview of Signed Numbers

8
 Signed Numbers
■ Representations
■ Sign-magnitude
■ Two’s complement

9
Signed Numbers…

10
• Section 3.2:

Addition and Subtraction

11
Binary Addition and Subtraction

12
Binary Addition and Subtraction…

13
 Overflow
■ Overflow occurs when the result from an operation
cannot be represented with the available hardware,
in this case (MIPS32) a 32-bit word.
■ When adding operands with different signs,
overflow cannot occur.

■ The reason is the sum must be no larger than one

of the operands.
14
 Overflow…
■ In the case of subtraction, overflow cannot occur
when the signs of the operands are the same.
■ Knowing when overflow cannot occur in addition
and subtraction is all well and good, but how do we
detect it when it does occur?

■ Overflow occurs when adding two positive numbers

and the sum is negative, or vice versa.
15
 Overflow…
■ Overflow occurs in subtraction when we subtract a
negative number from a positive number and get a
negative result, or when we subtract a positive
number from a negative number and get a positive
result.

16
 Overflow…
■ What is about the overflow with unsigned integers?
■ Unsigned integers are commonly used for memory
addresses where overflows are ignored.
■ The computer designer must therefore provide a way
to ignore overflow in some cases and to recognize it in
others.
■ The MIPS solution is to have two kinds of arithmetic
instructions to recognize the two choices:
17
 Overflow…
■ The MIPS solution is to have two kinds of arithmetic
instructions to recognize the two choices:
■ Add (add), add immediate (addi), and subtract (sub)
cause exceptions on overflow.

■ Add unsigned (addu), add immediate unsigned (addiu),

and subtract unsigned (subu) do not cause exceptions on
overflow.

■
18
 Overflow…
■ Because C ignores overflows, the MIPS C compilers
will always generate the unsigned versions of the
arithmetic instructions addu, addiu, and subu, no
matter what the type of the variables.

■ The MIPS Fortran compilers, however, pick the

appropriate arithmetic instructions, depending on the
type of the operands.
19
 Overflow…
■ MIPS detects overflow with an exception, also called
an interrupt on many computers.
■ An exception or interrupt is essentially an
unscheduled procedure call to detect overflow for
which program execution is disrupted
■ An interrupt is an exception that comes from outside
of the processor. (Some architectures use the term
interrupt for all exceptions.)
20
 ALU
■ The hardware that performs addition, subtraction, and
usually logical operations such as AND and OR is
called an Arithmetic Logic Unit (ALU).

21
ALU…

22
23
• Section 3.3:

Multiplication

24
Operands in Multiplication

25
 Operands in Multiplication…
■ The first observation is that the number of digits in the product
is considerably larger than the number in either the
multiplicand or the multiplier.
■ In fact, if we ignore the sign bits, the length of the
multiplication of an n-bit multiplicand and an m-bit multiplier is
a product that is n + m bits long.
■ That is, n + m bits are required to represent all possible
products.
■ Hence, like add, multiply must cope with overflow because we
frequently want a 32-bit product as the result of multiplying
two 32-bit numbers.

26
The First
Multiplication
Algorithm
■ The requirement
of this algorithm
is that it takes n
steps to get the
proper product.

27
The Hardware for the First
Multiplication Algorithm

28
29
 Signed Multiplication
■ So far, we have dealt with positive numbers.
■ The easiest way to understand how to deal with
signed numbers is to first convert the multiplier and
multiplicand to positive numbers and then remember
the original signs.
■ The algorithms should then be run for 31 iterations,
leaving the signs out of the calculation.
■ We need negate the product only if the original signs
disagree. 30
 Multiplication in MIPS
■ MIPS provides a separate pair of 32-bit registers to
contain the 64-bit product, called Hi and Lo.
■ To produce a properly signed or unsigned product,
MIPS has two instructions:
▪ multiply (mult)
and
▪ multiply unsigned (multu)
31
 Multiplication in MIPS…
■ To fetch the integer 32-bit product, the programmer
uses move from lo (mflo).
■ The MIPS assembler generates a pseudoinstruction
for multiply that specifies three general-purpose
registers, generating mflo and mfhi instructions to
place the product into registers.

32
 Multiplication in MIPS…
■ The following code fragment which multiplies the
value in $t2 by the value in $t1, and stores the
result in $t0.
mult $t2, $t1
mflo $t0

33
 Multiplication in MIPS…
■ Example:
Let the variables i, j, m, and n be assigned to the registers
$s1, $s2, $s3, and $s4, respectively. What is the
compiled MIPS code for the following code fragment?
int i, j, m, n;
m = 2;
n = 1;
j = i % 2;
if (j == 0)
m = m * i;
else
n = n * i;
34
 Multiplication in MIPS…
■ Slon:
addi $s3, $zero, 2
addi $s4, $zero, 1
div $s1, $s3
mfhi $s2
bne $s2, $zero, L1
mult $s3, $s1
mflo $s3
j L2
L1:
mult $s4, $s1
mflo $s4
L2:
… 35
• Section 3.4:

Division

36
 Operands in Division
■ The reciprocal operation of multiply is divide, an
operation that is even less frequent and even more
quirky.
■ It even offers the opportunity to perform a
mathematically invalid operation: dividing by 0.

37
Operands in Division…

38
 A Division Algorithm
■ Let’s assume that both the dividend and the divisor
are positive and hence the quotient and the
remainder are nonnegative.
■ The division operands and both results are 32-bit
values, and we will ignore the sign for now.

39
A Division
Algorithm…
■ The surprising
requirement of
this algorithm is
that it takes n
+ 1 steps to
get the proper
quotient and
remainder!

40
The Hardware for the Division
Algorithm

41
42
 Signed Division
■ So far, we have ignored signed numbers in the
division.
■ The simplest solution is to remember the signs of the
divisor and dividend and then negate the quotient if
the signs disagree.
■ Thus the correctly signed division algorithm negates
the quotient if the signs of the operands are opposite
and makes the sign of the nonzero remainder match
the dividend.
43
44
45
 Division in MIPS
■ MIPS uses the 32-bit Hi and 32-bit Lo registers for
both multiply and divide.
■ Hi contains the remainder, and Lo contains the
quotient after the divide instruction completes.

■ To handle both signed integers and unsigned

integers, MIPS has two instructions:

divide (div) and divide unsigned (divu).

46
 Division in MIPS…
■ The following code fragment which divides the value
in $t3 by the value in $t2, and stores the quotient
in $t1 and the remainder in $t0.
div $t3, $t2
mflo $t1
mfhi $t0

47
 Division in MIPS…
■ Example:
Let the variables i and j be assigned to the registers $s0 and
$s1, respectively. What is the compiled MIPS code for the
following code fragment?
int i, j;
j = i % 2;
if (j == 0)
i = i + 2;
else
i = i + 1;
48
 Division in MIPS…
■ Slon:
addi $t0, $zero, 2
div $s0, $t0
mfhi $s1
bne $s1, $zero, L1
addi $s0, $s0, 2
j L2
L1:
addi $s0, $s0, 1
L2:
…
49
50
• Section 3.5:

Floating Point

51
 Floating-Point Representation
■ We need a way to represent
■ numbers with fractions, e.g., 3.1416
■ very small numbers (in absolute value), e.g., .00000000023
■ very large numbers (in absolute value) , e.g., –3.15576 × 1046
■ Representation:
■ Scientific : sign, exponent, significand form: binary
point
■ (–1)Sign × Significand × 2Exponent . E.g., –101.001101 × 2111001
■ more bits for significand gives more accuracy
■ more bits for exponent increases range
■ if 1 ≤ significand < 10two(= 2ten) then number is normalized , except
for number 0 which is normalized to significand 0
■ E.g., –101.001101 × 2111001 = –1.01001101 × 2111011 (normalized)
52
 Floating-Point Representation…
■ General form of floating-point numbers in MIPS:
■ single precision: one word

■ double precision: two words

53
 Floating-Point Representation…
■ Example: Represent 1.0two × 2-1 in single precision.

■ Example: Represent 1.0two × 2+1 in single precision.

54
 Floating-Point Representation…
■ These formats go beyond MIPS…
■ They are part of the IEEE 754 floating-point standard
■ found in virtually every computer invented since 1980
■ has greatly improved both the ease of porting floating-point
programs and the quality of computer arithmetic

55
 IEEE 754 Floating-Point Standard
■ IEEE 754 floating point standard:
■ single precision: one word
31 bits 30 to bits 22 to
23 0
sign 8-bit 23-bit
exponent significand
■ double precision: two words

31 bits 30 to bits 19 to
20 0
sign 11-bit exponent upper 20 bits of 52-bit significand

bits 31 to
0
lower 32 bits of 52-bit significand

56
IEEE 754 Floating-Point Standard…
■ Sign bit is 0 for positive numbers, 1 for negative numbers

■ Number is assumed normalized and leading 1 bit of significand left of

binary point (for non-zero numbers) is assumed and not shown
■ e.g., significand 1.1001… is represented as 1001…,
■ exception is number 0 which is represented as all 0s (see next slide)
■ for other numbers:
value = (–1)sign × (1 + significand) × 2exponent value

■ Exponent is biased to make sorting easier

■ all 0s is smallest exponent, all 1s is largest
■ bias of 127 for single precision and 1023 for double precision
■ therefore, for non-0 numbers: equals exponent
value = (–1)sign × (1 + significand) × 2value
(exponent – bias)

57
IEEE 754 Floating-Point Standard…
■ Special treatment of 0:
■ if exponent is all 0 and significand is all 0, then the value is
0 (sign bit may be 0 or 1)
■ if exponent is all 0 and significand is not all 0, then the value is
(–1)sign * (1 + significand) * 2-127
■ therefore, all 0s is taken to be 0 and not 2-127 (as would be for a non-zero
normalized number); similarly, 1 followed by all 0’s is taken to be 0 and not
- 2-127

■ Example: Represent –0.75ten in IEEE 754 single precision.

■ decimal: –0.75 = –3/4 = –3/22
■ binary: –11/100 = –.11 = –1.1 × 2-1
■ IEEE single precision floating point exponent = bias + exponent value
= 127 + (-1) = 126ten = 01111110two
■ IEEE single precision: 10111111010000000000000000000000
exponent signifi
sig cand
n
58
Floating Point
Addition
■ Algorithm:

59
Floating Point
Addition
■ Hardware:

60
Floating Point
Multpication
■ Algorithm:

61
Floating Point Complexities
■ In addition to overflow we can have underflow (number too
small)
■ Accuracy is the problem with both overflow and underflow
because we have only a finite number of bits to represent
numbers that may actually require arbitrarily many bits
■ limited precision ⇒ rounding ⇒ rounding error
■ IEEE 754 keeps two extra bits, guard and round
■ four rounding modes
■ positive divided by zero yields infinity
■ zero divide by zero yields not a number
■ other complexities
■ Implementing the standard can be tricky
■ Not implementing the standard can be even worse
■ see text for discussion of Pentium bug!
62
MIPS Floating Point
■ MIPS has a floating point coprocessor (numbered 1, SPIM) with
thirty-two 32-bit registers $f0 - $f31. Two of these are required
to hold doubles. Floating point instructions must use only
even-numbered registers (including those operating on single
floats). SPIM simulates MIPS floating point.

■ Floating point arithmetic: add.s (single addition), add.d

(double addition), sub.s, sub.d, mul.s, mul.d, div.s,
div.d

■ Floating point comparison: c.x.s (single), c.x.d (double),

where x may be eq, neq, lt, le, gt, ge

■ Other instructions…

63