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The document discusses various designs of approximate adders and filters aimed at reducing power consumption and improving performance in image processing and computing tasks. Key features include significant energy savings, area reduction, and speed improvements, though some designs face challenges with accuracy loss and increased complexity. Overall, these innovations are tailored for specific applications where power efficiency and speed are prioritized over precision.

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8 views2 pages

Literature

The document discusses various designs of approximate adders and filters aimed at reducing power consumption and improving performance in image processing and computing tasks. Key features include significant energy savings, area reduction, and speed improvements, though some designs face challenges with accuracy loss and increased complexity. Overall, these innovations are tailored for specific applications where power efficiency and speed are prioritized over precision.

Uploaded by

raunsekar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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TOPIC:A Low-Power Yet High-Speed Configurable Adder for Approximate Computing

This circuit minimizes power usage by 42.7% when it is compared to a conventional carry
look-ahead adder,and also minimizes critical path delay by 56.9% for better performance.It is
an compact design which achieves optimization with only an 14.5% area as it compared to
conventional carry look-ahead adder.And also has better image processing.But there is an
potential loss of accuracy when the power is reduced.There is an complexiy in the design
when it compared to traditional approximate adders due to accuracy-configurable
mechanism

Topic: Energy-Efficient Gaussian Filter for Image Processing using Approximate Adder
Circuits
This paper gives the information about an energy-efficient approach for implementing
Gaussian filters by using approximate adder circuits.It saves 40% energy for 3x3 gaussian
filter and 25% for 5x5 gaussian filter.Reduces hardware area usage by 45%.The approximate
3x3 gaussian filter achieves 16.67% timing improvement, while the 5x5 filter achieves a 5.26
%improvement.The loss of accuracy,approximate computing causes some level of error in
image processing.Choosing approximation levels requires detaile simulation and testung to
maintain results.

Topic: Area Efficient Nearly Accurate Approximate Adder Design

This paper introduces an approximate adder that decreases power and area by above 50%
while lowering delay by eliminating carry propagation. It works efficiently for 8-bit,126-bit,
and 32-bit adders with minor accuracy loss. It will face some precision loss, is fitted for
specific applications, and includes design complexity for optimal performance.

Topic: Design of Low Power, Area Efficient, and High-Speed Approximate Adders for
Inexact Computing
This paper introduces a 32-bit approximate adder minimized for low power consumption,
lower delay, and decline in transistor count, gaining 8% power saving using 45-nm
technology. It is approximate computing, lower output voltage swing, and design complexity,
specific application uses only.

Topic: Design and analysis of majority logic-based Approximate Adders and Multipliers
The proposed ML-based approximate computing design enhances working speed, minimizes
usage of power, and optimizes hardware efficiency, making it suitable for scalabale, error
resilient applications like image and pattern recognition. It contains computational errors,
and minimizing it’s use in precision-critical tasks and requiring careful circuit design for
optimal changes. Moreover, error propagation in large-scale circuits can be impacted in total
reliability.

Topic: Power-efficient, high-PSNR Approximate Full Adder Applied in Error-Resilient


Computations Based on CNTFETs
The proposed CNTFET-based adders is suitable for low power consumption, and ha an
improvement in image quality metrics and performs with high speed. It efficiently improves
arithmetic circuit but has minor computation errors and high power dissipation. Moreover,
its design complexity requires careful transistor optimization, and making
implementation problems.

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