ECE16 VLSI Testing and Verification

T.O. GEETHA RANI

Associate Professor
Dept. of E & C Engineering
Siddaganga Institute of Technology
Tumakuru – 572 103

ECE16 VLSI Testing and Verification VIII Semester

 Course Objectives
This course will enable students to:
• Analyze and model, faults in logic circuits
• Identify test patterns for BIST and to detect faults
present in combinational logic circuits
• Analyze test algorithms for memory and compare
various testable approaches for sequential circuits
• Illustrate different verification tools and simulators

2
Syllabus

Pre-requisites : Digital Electronic Circuits and CMOS VLSI Design

Course Outcomes:
On completion of this course students should be able to :
CO 1: Apply the knowledge of engineering fundamentals to analyze and model
faults in logic circuits (L2)
CO 2: Analyze and design test patterns for combinational logic circuits (L3)
CO 3: Choose and design testable sequential circuits. (L3)
CO 4: Analyze test pattern for BIST and design test algorithms for memory (L3)
CO 5: Analyze and compare different verification tools and Simulators (L3)
CO 6: Demonstrate capability of self learning, team work and communication
skills through presentation (L3)
(Knowledge levels : L1:Remembering, L2: Understanding, L3: Applying,
L4:Analyzing, L5:Evaluating, L6:Creating)

ECE16 VLSI Testing and Verification VIII Semester

Contd.
CO – PO Mapping

PO-10

PO-11

PSO-1

PSO-2
PO-12
PO-1

PO-2

PO-5

PO-6

PO-9
PO-3

PO-4

PO-7

PO-8
PO →
CO 

CO-1 3 2 2

CO-2 3 2 2 2 2 2 2 2

CO-3 3 2 2

CO-4 3 2 2

CO-5 3 2 2

CO-6 3 2 2 2 2 2 2

Avg. 3 2 2 2 2 2 2

Attainment levels : 1- Slight (Low), 2-Moderate (Medium), 3-Substantial (High)

(PO: PO-1:Engineering Knowledge, PO-2:Problem Analysis, PO-3: Design/Development
of solutions, PO-4:Conduct Investigations of Complex Problems, PO-5: Modern tool
usage, PO-6: Engineer and Society, PO-7: Environment and Sustainability, PO-8: Ethics,
PO-9: Individual and Team work, PO-10: Communication, PO-11: Project Management
and Finance, PO-12: Life long learning, PSO-1: Professional Skills, PSO-2: Problem
Solving Skills)

ECE16 VLSI Testing and Verification VIII Semester

Contd.
Unit – 1 Introduction to Testing
Unit – 2 Test Generation for Combinational Logic Circuits
Unit – 3 Design of Testable Sequential Logic Circuits
Unit – 4 Built In Self Test and Memory Testing
Unit – 5 Importance of Design Verification, Verification Tools and
Simulators

Text Books

“An Introduction to Logic Circuit Testing,” Morgan and

1 Parag K. Lala
Claypool Publishers, 2009

“Essentials of Electronic Testing for Digital, Memory

M. L. Bushnell and
2 and Mixed-Signal VLSI Circuits,” Kluwer Academic
V. D. Agrawal
Publishers, 2002

“Writing test benches: functional verification of HDL

3 Janick Bergeron
models,” 2nd Edition, Kluwer Academic Publishers, 2003

ECE16 VLSI Testing and Verification VIII Semester

Contd.

Reference Books

M. Abramovici, M.A.
"Digital Systems Testing and Testable Design", Jaico
1 Breuer and A.D.
Publishing House, 2002.
Friedman

J. Bhasker, Rakesh “Static Timing Analysis for Nanometer Designs A

2
Chadha practical approach,” Springer publications, 2009

Prakash Rashinkar,
“System on a Chip Verification”, Kluwer Academic
3 Peter Paterson,
Publishers, 2002
Leena Singh

ECE16 VLSI Testing and Verification VIII Semester

Unit-1 Introduction
Introduction :

CO-1: Apply the knowledge of engineering fundamentals

to analyze and model faults in logic circuits (L2)

At the end of this topic, the students will be able to

TLO1: analyze testing philosophy, and VLSI technology trends affecting testing.
TLO2: Identify faults in logic circuits and modeling the faults

https://nptel.ac.in/courses/117103125/

https://www.youtube.com/watch?v=-4XBm5t7_Jg

ECE16 VLSI Testing and Verification VIII Semester

Contd.

Introduction to Testing: Testing Philosophy

Role of Testing, Digital and Analog VLSI Testing
VLSI Technology Trends Affecting Testing
Faults: Faults in logic circuits
Breaks and Transistors Stuck-Open and Stuck-On or Stuck-Open Faults in CMOS
Basic concepts of fault detection,
Fault modeling: Fault equivalence
Fault collapsing and fault dominance 7 Hrs

ECE16 VLSI Testing and Verification VIII Semester

Introduction to Testing
➢ “To err is human”
➢ How an imperfect product turn out a perfect product?

Algorithm : Perfect
Repeat until tested perfect:
{
Redesign;
Remake;
}
➢ Two relevant points
(i) Test should be designed to truly indicate the desired perfection
(ii) Repeat loop should repeat indefinitely until correct the errors found

ECE16 VLSI Testing and Verification VIII Semester

Testing Philosophy
Analogy : Test in any subject for students
➢ Teacher sets a domain of knowledge for testing (Syllabus)
➢ In VLSI One should know the specifications
➢ Teacher asks questions and analyzes the response (matching answers to correct
ones)
➢ Device tests such that the object produces the expected response
➢ Quality of test depends on how well the questions cover the syllabus
➢ Test vectors should be designed such that it covers the functionality very well
➢ Since there is no indefinite time, number of questions should be limited and
cleverly asked
➢ All possible test vectors cannot be tested
➢ Certain assumptions are made, like typical mistakes which students do usually,
questions are asked to cover such topics
➢ Electronic testing uses fault modeling and tests are generated for the assumed
fault models

ECE16 VLSI Testing and Verification VIII Semester

Cont.

➢ Finally if you fail, you must repeat the course

➢ Similar to redesign and remake
➢ The performance can be better in test
➢ If the syllabus is clearly known (specifications)
➢ Error models are known
➢ In VLSI this is called “Design for Testability”

ECE16 VLSI Testing and Verification VIII Semester

Example

➢ Testing of students : In a course assume 70% of the students deserve passing,

call them as “pass quality students” and 30% deserve failing, call them as “fail
quality students”. Assume number of students taking that course is large hence
for randomly selected students we define the following events.
➢ PQ : Students is pass quality P : Students passes the test
➢ FQ : Students is fail quality F : Student fails the test
➢ Assume only pass/fail grades are awarded
➢ So, Prob(PQ) = 0.7 and Prob(FQ) = 0.3
➢ It is impossible to design a perfect test
➢ After testing 95% of the pass quality students are actually passed and 95% of
the fail quality students actually fail
➢ Prob(P/PQ) = 0.95 and Prob(F/PQ)=0.05
➢ This scenario can be pictorially represented as

ECE16 VLSI Testing and Verification VIII Semester

Cont.

70% Pass quality Prob(P/PQ)=0.95

Prob(PQ) = 0.7 68% Passed

All Students

30% Fail quality

32%FAILED
Prob(FQ) = 0.3
Prob(F/FQ)=0.95

The total probability of passing is

ECE16 VLSI Testing and Verification VIII Semester

Cont.

ECE16 VLSI Testing and Verification VIII Semester

Cont.
➢ Testing of electronic systems are almost of similar type
➢ The difference is a student can pass the exam by answering correctly to most of
the question (Not necessarily all the questions)
➢ The student can learn correct answers in future
➢ But this is impossible in VLSI chip
➢ So even a single incorrect response will fail a VLSI chip
➢ However electronic tests are also not perfect, they may not cover some faults
and some bad chips will pass
➢ To prevent such bad chips “non-functional” tests will be conducted, but these
tests fail some good chips also (Example IDDQ test)
➢ In VLSI failing of good chips by tests is known as “Yield loss”
➢ In electronic testing
➢ Teacher’s risk → Consumer’s risk
➢ Student’s risk → Manufacturer’s risk

ECE16 VLSI Testing and Verification VIII Semester

Role of Testing
➢ If a product is designed, fabricated and fails when tested may have the
following reasons
➢ the test maybe wrong
➢ the fabrication process may be faulty
➢ design may be incorrect
➢ specifications might have problem
➢ Anything can be wrong or everything can be wrong
➢ The role of testing is to detect whether something went wrong
➢ The role of diagnosis is to determine exactly what went wrong and where the
process to be altered
➢ Correctness and effectiveness of testing is most important for quality products
(perfect products)
➢ Distributed testing along the product realisation process catches the defect
producing causes as soon as they become active and before they damage much

ECE16 VLSI Testing and Verification VIII Semester

Cont.
➢ The benefits of testing are quality and economy (both are dependent)
➢ Quality means satisfying the user’s needs at a minimum cost
➢ A good test process can remove all the bad products before they reach user
➢The number of bad products heavily rise the cost of good products
➢ But if too many bad products are produced the cost of these products should be
recovered from good ones

ECE16 VLSI Testing and Verification VIII Semester

Cont.

ECE16 VLSI Testing and Verification VIII Semester

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Verification and Test

ECE16 VLSI Testing and Verification VIII Semester

VLSI Testing

ECE16 VLSI Testing and Verification VIII Semester

Digital and Analog VLSI Testing
➢ A crude natural process of realising VLSI chips is given as

Customer

Determine
Requirements

Write specifications

Failure mode analysis Design and Test

development

Fabrication

Manufacturing Testing

Faulty chips
Good chips to customer

ECE16 VLSI Testing and Verification VIII Semester

Cont.
Customer
➢ Requirements are the user needs satisfied
Determine by the chip which are derived from the
Requirements
function of the particular application
➢ Specifications are set
Write
specifications ➢ Function (Input output characteristics)
➢ Operating characteristics (power

Failure mode Design and Test

frequency noise etc.)
analysis development
➢ Physical characteristics (Packaging)
➢ Environmental characteristics
Fabrication (temperature, humidity, reliability)
➢ Other characteristics (Volume, cost,
availability)
Manufacturing
Testing ➢ Objective of design is to produce data
Faulty chips
necessary for next step of fabrication and
Good chips to customer
testing

ECE16 VLSI Testing and Verification VIII Semester

Cont.
Customer
➢ Design has several stages
Determine ➢ Architectural design → System level
Requirements
structure of realisable blocks to
implement the functional specification
Write
specifications ➢ Logic design → further decomposes
blocks in to logic gates

Failure mode Design and Test

➢ Finally the gates are implemented as
analysis development
physical devices (transistors) and a
chip layout is implemented
Fabrication ➢ Fabrication consists of processing silicon
wafers through a series of steps involving
photoresist, exposure through mask, etching
Manufacturing
Testing ion implantation etc.
Faulty chips

Good chips to customer

ECE16 VLSI Testing and Verification VIII Semester

Cont.
➢ Impurities and defects in materials,
Customer
equipment malfunctions and human errors are
Determine
Requirements some causes of defects
➢ These defects are the main reasons for
Write testing
specifications
➢ Another important function of testing is the
process diagnosis means
Failure mode Design and Test
analysis development ➢ What went wrong with each faulty chip
➢ is it in fabrication, in design or in
testing
Fabrication
➢ or is it unrealizable specification
➢ The faulty chip analysis is called failure
Manufacturing mode analysis (FMA) which include
Testing
Faulty chips examination through optical and electron

Good chips to customer microscopes to determine the failure cause

and fix the process
ECE16 VLSI Testing and Verification VIII Semester
Cont.
Customer ➢ The arrows out of the FMA block represent
Determine the corrective actions applied to the faulty
Requirements
steps of the realisation process
➢ In this approach the effort between the
Write
specifications point where error occurred and point of testing
is wasted
➢ Testing should be done close to the
Failure mode Design and Test
analysis development
point of error
➢ Many companies emphasize on doing it right

Fabrication
the first time or pursuing the goal of zero
defects
➢ These goals are achievable in an error prone
Manufacturing
Testing environment, when errors are detected and
Faulty chips
corrected before damage occurs
Good chips to customer

ECE16 VLSI Testing and Verification VIII Semester

Realistic VLSI realisation process
Customer ➢ Distributed form of testing
➢ Dotted lines shows testing (screening)
Determine
Requirements ➢ Each testing level performs two functions and
involves different technical personnel
Audits
➢ The work done so far follows the objective of
Write
specifications
previous levels and meets customer
Audits requirement
Design and Test ➢ Things have been done according to the
development
capabilities of the later process levels
Design
Verification ➢ Finally verification of design and test procedures
Fabrication should ensure that the design meets all functional and

Process Test
other specifications and is also manufacturable,
and FMA
testable and repairable
Manufacturing
Testing

FMA

Good chips to customer

ECE16 VLSI Testing and Verification VIII Semester

Cont.

➢ Figure shows the level of involvement of various types of engineering personnel

through the life time of a VLSI device (ASIC)
➢ Discussion between customer and marketing engineer → specifications are
prepared (Involvement of design, manufacturing and test engineers is necessary
to ensure realisable specifications)

ECE16 VLSI Testing and Verification VIII Semester

Cont.

➢ System engineer → constructing an architectural block diagram verified by high

level simulation, logic circuit simulation, tested (test bench (HDL))
➢ VLSI design engineer → generates layout and verifies the timing against
specification

ECE16 VLSI Testing and Verification VIII Semester

Cont.

➢ Manufacturing and test engineer → fabricate and test wafers, package and test
chips
➢ Sales and field application engineers → interaction with the customer

ECE16 VLSI Testing and Verification VIII Semester

VLSI Technology trend affecting testing

➢ Complexity of VLSI chip has reached to an extent millions (> 100) of transistors
on chip and clock frequency of GHz (>1)

ECE16 VLSI Testing and Verification VIII Semester

Rising Chip Clock Rates

➢ Microprocessor clock rates have increased drastically, The exponential rise in

clock rate indicates several changes in testing
At Speed Testing
➢ Stuck fault tests are more effective when applied at the circuit’s rated clock
speed rather than at a lower speed
➢ Stuck fault testing covers all signals assuming that a faulty signal may be
permanently stuck at logic ‘0’ or ‘1’
➢ For a reliable high speed test, the automatic test equipment (ATE) must operate
as fast as or faster than the circuit under test

Automatic Test Equipment (ATE) Cost

➢ The cost of an ATE tester operating at 1GHz increases roughly at the rate of
$ 3,000 per pin
➢ A fixed cost of function generators for mixed signal circuits can range between
0.5 – 1.2 million dollars

ECE16 VLSI Testing and Verification VIII Semester

 Automatic Test
Equipment (ATE)

•ATE is a multimillion dollar

instrument.
•Cost of testing a chip in an
ATE is dependent on
–time a chip is tested,
–the number of
inputs/outputs pins
–frequency the test patters
are to be applied
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Cont.

➢ Semiconductor industry faces two types of problems

➢ The installed test capability in many factories around the world will be
lesser than the present clock rate, by the time these equipment are replaced
by new, clock rates of chips will be further increased
➢ The clock rate of microcontrollers will be always exceeding the present
state of the art of the ATE
➢ As the development of faster ATE continues, other test methods are also
emerging
➢ An Embedded ATE method : ATE functions such as high speed vector
generation and response analysis are added to the chip hardware
➢ Controllable delays are inserted in the chip hardware such that the critical
path delay can be measured by a slow speed tester

ECE16 VLSI Testing and Verification VIII Semester

Cont.

Electro Magnetic Interference (EMI)

➢ A chip operating in GHz frequency range must be tested for electro magnetic
interference
➢ This is a problem because inductance in the wiring becomes very active at these
high frequencies, where they can be ignored at low frequencies
➢ Ringling in signal transition along the wiring, because signal transition are
reflected from the ends of a bus and bounce back to the source, where they
are reflected again
➢ Interference with signal propagation through the wiring caused by the
dielectric permeability and the dielectric permittivity.
➢ Delay testing of paths requires propagation of sharp signal transition
resulting in high frequency currents through interconnects, causing radiation
coupling

ECE16 VLSI Testing and Verification VIII Semester

Increasing Transistor Density

➢ Transistor feature sizes on VLSI chip reduces roughly by 10.5% per year
➢ Transistor density increases roughly 22.1% every year
➢ Nearly 44% increase in transistors on microprocessor chips every year

Test Complexity
➢ Testing difficulty increases as the transistor density increases
➢ Internal chip modules (embedded memories) becomes very difficult to access
➢ Test patterns for sub assemblies on the chip interfere with each other, due to
the need to observe sub assembly ‘A’ through sub assembly ‘B’ while stimulating
both through circuit inputs

Feature Scaling and Power Dissipation

➢ Power dissipation per unit area of a CMOS chip is given by
➢ Objective of shrinking (scaling) the device features is to increase the circuit
speed and transistor density

ECE16 VLSI Testing and Verification VIII Semester

Cont.
➢ If dimensions are divided by a constant  > 1, speed increases by a factor ,
because node capacitance decreases by 1 / , transistor density increases by  2
resulting in increase in C by 
➢ Hence the electric field within transistor increases and degrades reliability
➢ To keep electric field constant supply voltage will be reduced by factor 1 / 
➢ But the threshold voltage will not be scaled down in constant electric field
scaling, hence the switching speed drops
➢ Verification must check power buses overloaded by excessive current, this
causes a brown out in the chip
➢ This may cause the chip power bus lines to burn out due to metal migration
➢ Application of the test vectors may cause excessive power dissipation on
the chip and burn it out, so the vectors must be adjusted to reduce power
➢ Shrinking features will eventually require design of transistors with reduced
threshold voltage, these devices will have higher leakage current which
reduces the effectiveness of IDDQ testing

ECE16 VLSI Testing and Verification VIII Semester

Cont.
Current Testing
➢ Successful recent approach is to check for elevated quiescent current (IDDQ)
➢ While switching CMOS circuits exhibits an elevated current in the digital logic,
which dies out quickly to a small current after the gate output settles to a steady
state
➢ Faults such as transistor stuck on, shorted wires, short from transistor gates to
drains etc. elevate the quiescent current
➢ IDDQ testing marks the chips as faulty if the measured quiescent current exceeds
a specified threshold

ECE16 VLSI Testing and Verification VIII Semester

Faults in Logic Circuits
➢ A failure is said to have occurred in a logic circuit or system if it deviates from
its specified behavior
➢ A fault refers to a physical defect in a circuit, example : short between two
signal lines or a break in a signal line (physical defect) t-2-11
➢ An Error is usually the symptom of a fault in the circuit, thus a fault may
change the value of a signal in a circuit from ‘0’ to ‘1’ or vice versa
➢ A fault does not always cause an error in that case the fault is considered to be
latent (hidden)
➢ A fault is characterized by its nature, value, extent and duration
➢ The nature of the fault can be classified as logical or non-logical
➢ A logical fault causes the logic value at a point in a circuit to become
opposite to the specified value
➢ Non logical faults include the rest of the faults such as the malfunction of
the clock signal, power failure etc.

ECE16 VLSI Testing and Verification VIII Semester

Cont.
➢ The value of a logical fault at a point in the circuit indicates whether the fault
creates fixed or varying erroneous logical values
➢ The extent of a fault specifies whether the effect of the fault is localized or
distributed
➢ A local fault affects only a single variable whereas a distributed fault affects
more than one
➢ A logical fault for example is a local fault, whereas the malfunction of the
clock is a distributed fault
➢ The duration of a fault refers to whether the fault is permanent or temporary

Stuck–At Fault
➢ The most common model used for logical faults is the single stuck-at fault
➢ It assumes that a fault in a logic gate results in one of its inputs or the output is
fixed at either a logic 0 (stuck-at-0) or at logic 1 (stuck-at-1). Stuck-at-0 and
stuck-at-l faults are often abbreviated to s-a-0 and s-a-1, respectively.

ECE16 VLSI Testing and Verification VIII Semester

Cont.
➢ Let us assume that in figure the A input of the NAND gate is s-a-1.

➢ If input A=0 and B=1 the output should be Z=1 (in the absence of fault)
➢ If input A is s-a-1 then output will be 0 for A=0 and B=1 (in the presence of
fault)
➢ Thus, AB=01 can be considered as the test for the A input s-a-l, since there is a
difference between the output of the fault-free and faulty gate.

ECE16 VLSI Testing and Verification VIII Semester

Defects, Faults and errors in Logic Circuits

ECE16 VLSI Testing and Verification VIII Semester

Defects, Faults and errors in Logic Circuits contd..

ECE16 VLSI Testing and Verification VIII Semester

Functional testing

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Switch level fault model

73
Cont.
➢ Figure illustrates CMOS realisation of NAND gate

➢ The number 1 in the figure indicates an open, whereas the numbers 2 and 3
identify the short between the output node and the VDD and the short between
the output node and the ground, respectively.
➢ A short in a CMOS results if not enough metal is removed by the
photolithography, whereas over-removal of metal results in an open circuit

ECE16 VLSI Testing and Verification VIII Semester

NAND 2 layout

75
Cont.
➢ Fault 1 in figure will disconnect input A
from the gate of transistors T1 and T3.
➢ In such a situation one transistor may
conduct and the other remain non
conducting
➢ Thus, the fault can be represented by a
stuck at value of A; if A is s-a-0, T1 will
be ON and T3 OFF, and if A is s-a-l, T1
will be OFF and T3 ON.
➢ Fault 2 forces the output node to be shorted to VDD, that is, the fault can be
considered as s-a-l fault.
➢ Fault 3 forces the output node to be s-a-0.
➢ The stuck-at model is also used to represent multiple faults in circuits.
➢ In a multiple stuck-at fault, it is assumed that more than one signal line in the
circuit are stuck at logic 1 or logic 0

ECE16 VLSI Testing and Verification VIII Semester

Cont.
➢ A group of stuck-at faults exist in the circuit at the same time.
➢ A multiple fault is unidirectional if all of its constituent faults are either s-a-0 or
s-a-l but not both simultaneously.
➢ The stuck-at model has gained wide acceptance in the past mainly because of
its relative success with small scale integration.
➢ However, it is not very effective in accounting for all faults in present day very
large scale integrated (VLSI), circuits which mainly uses CMOS technology.
➢ Faults in CMOS circuits do not necessarily produce logical faults that can be
described as stuck-at faults.

ECE16 VLSI Testing and Verification VIII Semester

78
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Cont.
➢ Consider CMOS implementation of the Boolean function

➢ Two possible shorts numbered 1 and 2 and two possible opens numbered 3 and
4 are indicated in the diagram.

ECE16 VLSI Testing and Verification VIII Semester

Cont.
➢ Short number 1 can be modeled by s-a-1 of
input E; open number 3 can be modeled by
s-a-0 of input E or input F, or both.
➢ Short number 2 and open number 4 cannot
be modeled by any stuck-at fault because they
involve a modification of the network function.
➢ For example, in the presence of short
number 2, the network function will change to:

➢ Open number 4 will change the function to:

ECE16 VLSI Testing and Verification VIII Semester

Cont.

➢ A short between the output of the two gates cannot be modeled by a stuck-at
fault.
➢ Without a short, the outputs of gates Z1 and Z2 are:
➢ With the short

ECE16 VLSI Testing and Verification VIII Semester

Cont.
➢ Figure shows the CMOS logic realization of the Boolean function:

➢ A short between two lines, as indicated by the dotted line in the diagram will
change the function of the circuit.

ECE16 VLSI Testing and Verification VIII Semester

Bridging Faults
➢ Bridging faults form an important class of permanent faults that cannot be
modeled as stuck-at faults.
➢ A bridging fault is said to have occurred when two or more signal lines in a
circuit are accidentally connected together.
➢ Bridging faults at the gate level has been classified into two types: input
bridging and feedback bridging.
➢ An input bridging fault corresponds to the shorting of a certain number of
primary input lines.
➢ A feedback bridging fault results if there is a short between an output and
input line.
➢ A feed-back bridging fault may cause a circuit to oscillate, or it may convert
it into a sequential circuit.

ECE16 VLSI Testing and Verification VIII Semester

AND bridging fault

85
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Delay Faults
➢ Not all manufacturing defects in VLSI circuits can be represented by the stuck-
at fault model.
➢ Smaller defects, which are likely to cause partial open or short in a circuit, have
a higher probability of occurrence due to the variations in the manufacturing
process.
➢ These defects result in the failure of a circuit to meet its timing specifications
without any alteration of the logic function of the circuit.
➢ A small defect may delay the transition of a signal on a line either from 0 to 1,
or vice versa.
➢ This type of malfunction is modeled by a delay fault.

ECE16 VLSI Testing and Verification VIII Semester

Cont.
➢ Two types of delay faults are observed: gate delay fault and path delay fault.
➢ Gate delay faults have been used to model defects that cause the actual
propagation delay of a faulty gate to exceed its specified worst case value.
➢ For example, if the specified worst case propagation delay of a gate is x
units and the actual delay is x+Δx units, then the gate is said to have a delay
fault of size Δx.
➢ The main deficiency of the gate delay fault model is that it can only be used
to model isolated defects, not distributed defects.
➢ The path delay fault model can be used to model isolated as well as
distributed defects.
➢ In this model, a fault is assumed to have occurred if the propagation delay
along a path in the circuit under test exceeds the specified limit.

ECE16 VLSI Testing and Verification VIII Semester

Breaks and Transistors Stuck Open and Stuck On or Stuck
Open Faults in CMOS
➢ Breaks and transistor stuck-ons are two other types of defects that may remain
undetected if testing is performed based on the stuck-at fault assumption.
➢ These defects have been found to constitute a significant percentage of defects
occurring in CMOS circuits

Breaks
➢ Breaks or opens in CMOS circuits are caused either by missing conducting
material or extra insulating material.
➢ Breaks can be either of the following two types:
➢ Intragate breaks
➢ Signal line breaks.

ECE16 VLSI Testing and Verification VIII Semester

Cont.
➢ An intragate break occurs internal to a gate.
Such a break can disconnect the source, the
drain, or the gate from a transistor, identified
by b1, b2, and b3, respectively
➢ The presence of b3, will have no logical
effect on the operation of a circuit, but it will
increase the propagation delay; that is, the
break will result in a delay fault.
➢ Similarly, the break at b1 will also produce a
delay fault without changing the function of the
circuit.
➢ The break at b2 will make the p-transistor
nonconducting; that is, the transistor can be
assumed to be stuck-open.

ECE16 VLSI Testing and Verification VIII Semester

Cont.
➢ An intragate break can also disconnect the p-
network, the n-network, or both networks (b4,
b5, and b6) from the circuit.
➢ The presence of b4 or b5 will have the same
effect as the output node getting stuck-at-0 or
stuck-at-1, respectively.
➢ In the presence of b6, the output voltage
may have an intermittent stuck-at-1 or stuck-
at-0 value; if the output node simultaneously
drives a p-transistor and an n-transistor, then
one of the transistors will be ON for some
unpredictable period of time.

ECE16 VLSI Testing and Verification VIII Semester

Cont.

➢ Signal line breaks can force the gates of

transistors in static CMOS circuits to float. Such a
break can make the gate of only a p-transistor
and an n- transistor to float.
➢ It is also possible, depending on the position of
a break, that the gates of both transistors may
float, in which case one transistor may conduct
and the other remain in a nonconducting state.
➢ This type of break can be modeled as a stuck-at
fault.

➢ If a transistor with a floating gate remains in a nonconducting state due to a

signal line break, the circuit will behave similarly as in the presence of the
intragate break b2.

ECE16 VLSI Testing and Verification VIII Semester

Stuck On and Stuck Open Faults

➢ A stuck-on transistor fault implies the permanent closing of the path between
the source and the drain of the transistor.
➢ A stuck-on transistor has the same drain-source resistance as the on resistance
of a fault-free transistor, whereas a stuck-closed transistor exhibits a drain-source
resistance that is significantly lower than the normal on-resistance.
➢ A transistor stuck-on (stuck-closed) fault may be modeled as a bridging fault
from the source to the drain of a transistor.
➢ A stuck-open transistor implies the permanent opening of the connection
between the source and the drain of a transistor.
➢ The drain-source resistance of a stuck-open transistor is significantly higher
than the off-resistance of a nonfaulty transistor.
➢ If the drain-source resistance of a faulty transistor is approximately equal to
that of a fault-free transistor, then the transistor is considered to be stuck-off.

ECE16 VLSI Testing and Verification VIII Semester

Cont.
Two input CMOS NOR gate and truth table with and without stuck open fault

➢ A stuck-open fault causes the output to be connected neither to GND nor to

VDD.
➢ If T2 is open-circuited, for input AB=00, the pull-up circuit will not be active
and there will be no change in the output voltage and retains its previous logic
state; the length of time the state is retained is determined by the leakage
current at the output node.
ECE16 VLSI Testing and Verification VIII Semester
Cont.

➢ In truth table the fault-free output is shown in column Z; and the remaining
columns represent the outputs in presence of the three stuck-open (s-op) faults.
➢ The first, As-op, is caused by any input, drain, or source missing connection to
the pull-down FET T3.
➢ The second, Bs-op, is caused by any input, drain, or source missing connection
to the pull-down FET T4.

ECE16 VLSI Testing and Verification VIII Semester

Cont.

➢ The third, VDDs-op, is caused by an open anywhere in the series, p-channel

pull-up connection to VDD.
➢ The symbol Zt indicate that the output state retains the previous logic value.

ECE16 VLSI Testing and Verification VIII Semester

Basic Concepts of Fault Detection
➢ Fault detection in a logic circuit is carried out by applying a sequence of tests
and observing the resulting outputs.
➢ A test is an input combination that specifies the expected response that a fault-
free circuit should produce. If the observed response is different from the
expected response, a fault is present in the circuit
➢ The aim of testing at the gate level is to verify that each logic gate in the circuit
is functioning properly and the interconnections are good.
➢ If only a single stuck-at fault is assumed to be present in the circuit under test,
then the problem is to construct a test set that will detect the fault by utilizing
only the inputs and the outputs of the circuit.

ECE16 VLSI Testing and Verification VIII Semester

Cont.
➢ Assume that input a of the NAND gate shown in figure is stuck-at-1. The output
responses of the gate to all input combinations for both fault-free and fault-
present conditions are shown in truth table

➢ In order to detect a fault in a circuit, the fault must first be excited; that is, a
certain input combination must be applied to the circuit so that the logic value
appearing at the fault location is opposite to the fault value.
➢ Next, the fault must be sensitized; that is, the effect of the fault is propagated
through the circuit to an observable output

ECE16 VLSI Testing and Verification VIII Semester

Cont.

➢ In the figure shown, the input combination abc=111 must be applied for the
excitation of the fault, and d=1 for sensitizing the fault to output Z.
➢ The test for the s-a-1 fault is abcd=1111. This input combination is also a test
for other faults (e.g., gate 1 s-a-0, gate 3 s-a-1, and input a s-a-0, etc.).

ECE16 VLSI Testing and Verification VIII Semester

Controllability and Observability
➢ As discussed, in order to generate a test for a stuck-at fault on a signal line, it
must first be forced to a value that is opposite to the stuck-at value on the line.
➢ ability to apply input patterns to the primary inputs of a circuit to set up
appropriate logic value at desired locations of a circuit is known as controllability.
➢ For example, in the presence of a stuck-at-0 fault, the location of the fault must
be set to logic 1 via the primary inputs; this is known as 1-controllability.
➢ Similarly, for a stuck-at-1 fault, the location of the fault must be set to logic 0 to
excite the fault; this is known as 0-controllability.
➢ The sensitization part of the test generation process requires application of
appropriate input values at the primary inputs so the effect of the fault is
observable at the primary outputs.

ECE16 VLSI Testing and Verification VIII Semester

102
AND 25 with and without control
and observation points

103
Cont.

➢ For example, in figure shown, the effect of the stuck-at-1 fault can observed at
output Z if input d is set at 1; if d is set to 0, the output will be 0 and the effect of
the fault will be masked (i.e., the fault will not be detected).
➢ The ability to observe the response of a fault on an internal node via the
primary outputs of a circuit is denoted as observability.

ECE16 VLSI Testing and Verification VIII Semester

Undetectable Faults
➢ A fault is considered to be undetectable if it is not possible to activate the fault
or to sensitize its effect to primary outputs. In other words, a test for detecting
the fault does not exist.

➢ Consider the  s-a-0 fault shown in figure, It is not possible to set the node  to
logic 1. Therefore, the fault cannot be excited and thus undetectable.
➢ The fault β s-a-0 can be excited by making ab=10, but no sensitized path is
available for propagating the effect of the fault to the output; hence, the fault is
undetectable.
➢ A combinational circuit is denoted as redundant if it has an undetectable fault.

ECE16 VLSI Testing and Verification VIII Semester

Cont.
➢ A test set for a circuit is derived based on the assumption that only a single
fault is present in the circuit when the tests are applied.
➢ The simultaneous presence of an undetectable fault and a detectable fault
violates this assumption. The presence of an undetectable fault may prevent the
detection of a detectable fault.

ECE16 VLSI Testing and Verification VIII Semester

Equivalent Faults
➢ A test, in general, can detect more than one fault in a circuit, and many tests in
a set detect the same faults.
➢ A major objective in test generation is to reduce the total number of faults to be
considered by grouping equivalent faults in subsets.
➢ It is then sufficient only to test one fault from each equivalent set to cover all
faults in the set, thus avoiding redundancy in the test generation process.
➢ In an m-input gate, there can be 2(m+1) stuck-at faults.
➢ The total number of single stuck-at faults in a two-input NOR gate shown in
figure is 6 (=2×3), e.g,. a s-a-0, b s-a-0, a s-a-1, b s-a-1, c s-a-0 and c s-a-1.

➢ A stuck-at fault on an input may be indistinguishable from a stuck-at fault at the

output. For example, in a NOR gate, any input s-a-1 fault is indistinguishable from
the output s-a-0

ECE16 VLSI Testing and Verification VIII Semester

Cont.
➢ Two faults are considered to be equivalent if every test for one fault also detects
the other.
➢ In the two-input NOR gate a stuck-at-1 fault on one of the inputs a or b is
equivalent to output c stuck-at-0, thus all three faults belong to the same
equivalence set.
➢ A test for any of these three faults will also detect the presence of the other
two. The equivalence sets for the NOR gate are:

ECE16 VLSI Testing and Verification VIII Semester

Cont.
➢ In a NAND gate, an input s-a-0 fault is indistinguishable from the output s-a-1.

➢ The equivalence sets for the NAND gate are:

➢ Because there are three equivalence fault sets for both NOR and NAND gates, it
is sufficient to derive tests for three faults only in each case, i.e., one fault from
each set.

ECE16 VLSI Testing and Verification VIII Semester

Temporary Faults
➢ A temporary fault can result in an intermittent or a transient error.
➢ Transient errors are nonrecurring and are not repairable because there is no
physical damage to the hardware.
➢ The reduction of transistor sizes also reduces their noise margins. hence they
become more vulnerable to noise, cross-talk, etc., which in turn result in transient
errors.
➢ Intermittent faults can occur due to loose connections, partially defective
components, or poor designs.
➢ Intermittent faults occurring due to deteriorating or aging components may
eventually become permanent.
➢ Some intermittent faults also occur due to environmental conditions such as
temperature, humidity, vibration, etc.
➢ The likelihood of such intermittent faults depends on how well the system is
protected from its physical environment through shielding, filtering, cooling, etc.
➢ Intermittent faults are random, they can be modeled only by using probabilistic
methods
ECE16 VLSI Testing and Verification VIII Semester
Defect →Fault → Test pattern → Fault coverage
Fault modeling Test pattern generation Fault simulation

• Test process
• What faults to test? (fault modeling)
• How are test pattern obtained? (test pattern
• generation)
• How is test quality (fault coverage) measured?
• (fault simulation)?
• How are test vectors applied and results evaluated?
• (ATE/BIST)
111
Fault Equivalence
➢ Consider a single output combinational circuit with ‘n’ input variables with its
output function as f0(V), where V is an n-bit Boolean vector
➢ Considering two faults, let the output function in the presence of fault-1 be f1(V)
➢ The output function in the presence of fault-2 be f2(V)
➢ Any test ‘V’ for fault-1 must produce different values for f0(V) and f1(V) which
can be expressed as f0(V)  f1(V) = 1
➢ Similarly a test for fault-2 must satisfy f0(V)  f2(V) = 1
➢ If fault-1 and fault-2 have exactly the same tests then
[f0(V)  f1(V)]  [f0(V)  f2(V)] = 0
➢ Which can be written as f1(V)  f2(V) = 0
➢ Which is known as indistinguishability condition, which says that the two faulty
functions are identical when the fault have the same set of tests
➢ Fault Equivalence : Two faults of a Boolean circuit are called equivalent only if
two faulty circuits have identical output functions. Equivalent faults are also called
indistinguishable and will have exactly the same set of tests

ECE16 VLSI Testing and Verification VIII Semester

Cont.
➢ For example consider the following gates

➢ Consider a two input AND gate, the s-a-0 of any of the input leads to the output to
be 0, hence the s-a-0 faults are equivalent
➢ No such equivalence relation is found among s-a-1 faults

ECE16 VLSI Testing and Verification VIII Semester

114
• For 2-input gate ,
• Total s-a-f = 2(m+1)= 6
• By applying fault equivalent collapsing, only 4
s-a-f are retained( i.e 2 s-a-f can be deleted)

115
Fault Collapsing
➢ The faults in a circuit can be grouped into equivalence sets
➢ The process of selecting one fault from each equivalence test is called fault
collapsing
➢ The set of selected faults is known as equivalence collapsed set
➢ The relative size of the equivalence collapsed set with respect to the set of all
faults is the collapse ratio

ECE16 VLSI Testing and Verification VIII Semester

Cont.
➢ Example-1 : Tree circuit

➢ No of faults deleted by equivalence collapsing with fault at output gate

➢ Fault collapsing is performed in a level-by-level pass from inputs to output using
local gate fault equivalences
➢ The procedure begins at primary inputs and a gate is not processed until all gates
feeding its inputs have been processed.
➢ At a gate, first input faults are examined. Only one among the equivalent faults is
retained. Then any input faults that are equivalent to some output fault are deleted.

ECE16 VLSI Testing and Verification VIII Semester

Cont.

ECE16 VLSI Testing and Verification VIII Semester

• Number of lines=15
• Total number of faults= 2X15= 30
• Number of faults retained = 16

119
Compute fault collapsing ratio

o/p

Total faults= 7X2=14

CR= 8/14

120
Total s-a-f =14 After applying equivalent fault collapsing,
Number of s-a-f=8

Collapse ratio=8/14

121
For the tree circuit shown in figure, demonstrate fault
collapsing by equivalence and find collapse ratio.

122
Compute the collapse ratio using
equivalent fault collapsing

123
Total s-a-f=2X6=12

124
Set of collapsed faults = 8

Collapse ratio= 8/12

125
Show that the two faults c s-a-0 and f s-a-1 are equivalent in the circuit shown.

with s-a-0 fault at C the o/p function = a’b

With s-a-1 fault at f the o/p function = a’b
Since the o/p function with s-a-0 fault at C and s-a-1 fault at f are same, the two
Faults are equivalent
126
Cont.
➢ Example-2 : Circuit with reconvergent fanouts

➢ No of faults deleted by equivalence collapsing with fault at output gate

ECE16 VLSI Testing and Verification VIII Semester

128
Cont.
➢ Example-3 : Show that faults F1 and F4 are equivalent faults and F2 and F3 are also
equivalent faults (by functional equivalence)

➢ Functional fault collapsing can further reduce the number of faults, the s-a-1 faults
F1 and F4 are equivalent, and so are the s-a-1 faults on F2 and F3.

ECE16 VLSI Testing and Verification VIII Semester

 Example-3 contd..

Faulty output functions corresponding to four s-a-1 faults, F1, F2, F3, and F4 are
shown in k-map hence F1 and F4 are equivalent and F2 and F3 are equivalent.

130
Fault dominance

131
Fault Dominance
➢ Consider a three input AND gate

➢ Assume two stuck at faults F1 and F2 (s-a-1)

➢ T(F1) test vector for F1 and T(F2) is the set of all tests for vector F2
➢ T(F2) is larger and completely contains T(F1)
➢ Fault F2 dominates fault F1, hence fault F2 can be eliminated
➢ The three input AND gate with four faults after dominance fault collapsing
➢ Because the output s-a-0 is equivalent to any input s-a-0 fault

ECE16 VLSI Testing and Verification VIII Semester

Cont.

ECE16 VLSI Testing and Verification VIII Semester

Cont.

ECE16 VLSI Testing and Verification VIII Semester

Dominance Fault collapsing summary

135
136
137
138
139
Problems
1. Write all the stuck at faults for a two input NAND gate?
2. For the gate shown, write one test vector required to detect the fault.

3. For the circuit shown find the test vector to detect the fault.

ECE16 VLSI Testing and Verification VIII Semester

Problems
4. Find the test vector for the circuit shown.

5. In the above circuit show that fault c s-a-1 and f s-a-1 are equivalent

ECE16 VLSI Testing and Verification VIII Semester

142
143
144
Check the two faults are equivalent
or not

145
146
147
Recap
➢ Introduction to testing
➢ Testing philosophy
➢ Role of testing
➢ Digital and analog VLSI testing
➢ VLSI technology trends affecting testing

➢ Faults
➢ Faults in logic circuits
➢ Breaks and transistor stuck open and stuck on faults
➢ Basic concepts of fault detection

➢ Fault modeling
➢ Fault equivalence
➢ Fault collapsing
➢ Fault dominance
➢ Problems

ECE16 VLSI Testing and Verification VIII Semester