Random Access Memory
Random Access Memory
Random Access Memory (RAM) is a type of computer data storage. Its mainly used as main memory of a computer. RAM allows to access the data in any order, i.e random. The word random thus refers to the fact that any piece of data can be returned in a constant time, regardless of its physical location and whether or not it is related to the previous piece of data. You can access any memory cell directly if you know the row and column that intersect at that cell. Most of the RAM chips are volatile types of memory, where the information is lost after the power is switched off. There are some non-volatile types such as, ROM, NOR-Flash. SRAM: Static Random Access Memory SRAM is static, which doesn't need to be periodically refreshed, as SRAM uses bistable latching circuitry to store each bit. SRAM is volatile memory. Each bit in an SRAM is stored on four transistors that form two cross-coupled inverters. This storage cell has two stable states which are used to denote 0 and 1. Two additional access transistors serve to control the access to a storage cell during read and write operations. A typical SRAM uses six MOSFETs to store each memory bit. As SRAM doesnt need to be refreshed, it is faster than other types, but as each cell uses at least 6 transistors it is also very expensive. So in general SRAM is used for faster access memory units of a CPU. DRAM: Dynamic Random Access Memory In a DRAM, a transistor and a capacitor are paired to create a memory cell, which represents a single bit of data. The capacitor holds the bit of information. The transistor acts as a switch that lets the control circuitry on the memory chip read the capacitor or change its state. As capacitors leak charge, the information eventually fades unless the capacitor charge is refreshed periodically. Because of this refresh process, it is a dynamic memory. The advantage of DRAM is its structure simplicity. As it requires only one transistor and one capacitor per one bit, high density can be achieved. Hence DRAM is cheaper and slower, when compared to SRAM. Other types of RAM FPM DRAM: Fast page mode dynamic random access memory was the original form of DRAM. It waits through the entire process of locating a bit of data by column and row and then reading the bit before it starts on the next bit. EDO DRAM: Extended data-out dynamic random access memory does not wait for all of the processing of the first bit before continuing to the next one. As soon as the address of the first bit is located, EDO DRAM begins looking for the next bit. It is about five percent faster than FPM. SDRAM: Synchronous dynamic random access memory takes advantage of the burst mode concept to greatly improve performance. It does this by staying on the row containing the requested bit and moving rapidly through the columns, reading each bit as it goes. The idea is that most of the time the data needed by the CPU will be in sequence. SDRAM is about five percent faster than EDO RAM and is the most common form in desktops today.
DDR SDRAM: Double data rate synchronous dynamic RAM is just like SDRAM except that is has higher bandwidth, meaning greater speed. DDR2 SDRAM: Double data rate two synchronous dynamic RAM. Its primary benefit is the ability to operate the external data bus twice as fast as DDR SDRAM. This is achieved by improved bus signaling, and by operating the memory cells at half the clock rate (one quarter of the data transfer rate), rather than at the clock rate as in the original DDR SRAM.
Functioning (Follow the timing diagram for better understanding). Whenever there is a IO request (IOREQ) for memory access from a IO device. The DMA controller sends a Halt signal to microprocessor. Generally halt signal (HALT) is active low. Microprocessor then acknowledges the DMA controller with a bus availability signal (BA). As soon as BA is available, then DMA controller sends an IO acknowledgment to IO device (IOACK) and chip enable (CE - active low) to the memory unit. The read/write control (R/W) signal will be give by the IO device to memory unit. Then the data transfer will begin. When the data transfer is finished, the IO device sends an end of transfer (EOT - active low) signal. Then the DMA controller will stop halting the microprocessor. ABUS and DBUS are address bus and data bus, respectively, they are included just for general information that microprocessor, IO devices, and memory units are connected to the buses, through which data will be transferred.
The setup time is the interval before the clock where the data must be held stable. The hold time is the interval after the clock where the data must be held stable. Hold time can be negative, which means the data can change slightly before the clock edge and still be properly captured. Most of the current day flip-flops has zero or negative hold time.
In the above figure, the shaded region is the restricted region. The shaded region is divided into two parts by the dashed line. The left hand side part of shaded region is the setup time period and the right hand side part is the hold time period. If the data changes in this region, as shown the figure. The output may, follow the input, or many not follow the input, or may go to metastable state (where output cannot be recognized as either logic low or logic high, the entire process is known as metastability).
The above figure shows the restricted region (shaded region) for a flip-flop whose hold time is negative. The following diagram illustrates the restricted region of a D flip-flop. D is the input, Q is the output, and clock is the clock signal. If D changes in the restricted region, the flip-flop may not behave as expected, means Q is unpredictable.
The combinational logic between the flip-flops should be optimized to get minimum delay. Redesign the flip-flops to get lesser setup time. Tweak launch flip-flop to have better slew at the clock pin, this will make launch flipflop to be fast there by helping fixing setup violations. Play with clock skew (useful skews).
By adding delays (using buffers). One can add lockup-latches (in cases where the hold time requirement is very huge, basically to avoid data slip).
* may be expected one: which means output is not sure, it may be the one you expect. You can also say "may not be expected one". "may" implies uncertainty. Thanks for the readers for their comments.
SoC : System-On-a-Chip
System-on-a-chip (SoC) refers to integrating all components of an electronic system into a single integrated circuit (chip). A SoC can include the integration of:
y y y y y y y
Ready made sub-circuits (IP) One or more microcontroller, microprocessor or DSP core(s) Memory components Sensors Digital, Analog, or Mixed signal components Timing sources, like oscillators and phase-locked loops Voltage regulators and power management circuits
The blocks of SoC are connected by a special bus, such as the AMBA bus. DMA controllers are used for routing the data directly between external interfaces and memory, by-passing the processor core and thereby increasing the data throughput of the SoC. SoC is widely used in the area of embedded systems. SoCs can be fabricated by several technologies, like, Full custom, Standard cell, FPGA, etc. SoC designs are usually power and cost effective, and more reliable than the corresponding multi-chip systems. A programmable SoC is known as PSoC. Advantages of SoC are:
y y y y y y
Small size, reduction in chip count Low power consumption Higher reliability Lower memory requirements Greater design freedom Cost effective
Design Flow SoC consists of both hardware and software( to control SoC components). The aim of SoC design is to develop hardware and software in parallel. SoC design uses pre-qualified hardware, along with their software (drivers) which control them. The hardware blocks are put together using CAD tools; the software modules are integrated using a software development environment. The SoC design is then programmed onto a FPGA, which helps in testing the behavior of SoC. Once SoC design passes the testing it is then sent to the place and route process. Then it will be fabricated. The chips will be completely tested and verified.
CPLDs are ideal for critical, high-performance control applications. CPLD can be used for digital designs which perform boot loader functions. CPLD is used to load configuration data for an FPGA from non-volatile memory. CPLD are generally used for small designs, for example, they are used in simple applications such as address decoding. CPLDs are often used in cost-sensitive, battery-operated portable applications, because of its small size and low-power usage.
Architecture A CPLD contains a bunch of programmable functional blocks (FB) whose inputs and outputs are connected together by a global interconnection matrix. The global interconnection matrix is reconfigurable, so that we can change the connections between the FBs. There will be some I/O blocks which allow us to connect CPLD to external world. The block diagram of architecture of CPLD is shown below.
The programmable functional block typically looks like the one shown below. There will be an array of AND gates which can be programed. The OR gates are fixed. But each manufacturer has their way of building the functional block. A registered output can be obtained by manipulating the feedback signals obtained from the OR ouputs.
CPLD Programming The design is first coded in HDL (Verilog or VHDL), once the code is validated (simulated and synthesized). During synthesis the target device(CPLD model) is selected, and a technologymapped net list is generated. The net list can then be fitted to the actual CPLD architecture using a process called place-and-route, usually performed by the CPLD company's proprietary placeand-route software. Then the user will do some verification processes. If every thing is fine, he will use the CPLD, else he will reconfigure it.
PLA - Programmable Logic Array PAL - Programmable Array Logic CPLD - Complex Programmable Logic Device (Click here for more details) FPGA - Field-Programmable Gate Array (Click here for more details)
PLA: Programmable Logic Array is a programmable device used to implement combinational logic circuits. The PLA has a set of programmable AND planes, which link to a set of programmable OR planes, which can then be conditionally complemented to produce an output. This layout allows for a large number of logic functions to be synthesized in the sum of products canonical forms. Suppose we need to implement the functions: X = A'BC + ABC + A'B'C' and Y = ABC + AB'C. The following figures shows how PLA is configured. The big dots in the diagram are connections. For the first AND gate (left most), A complement, B, and C are connected, which is first minterm of function X. For second AND gate (from left), A, B, and C are connected, which forms ABC. Similarly for A'B'C', and AB'C. Once the minterms are implemented. Now we have to combine them using OR gates to the functions X, and Y.
One application of a PLA is to implement the control over a data path. It defines various states in an instruction set, and produces the next state (by conditional branching). Note that the use of the word "Programmable" does not indicate that all PLAs are fieldprogrammable; in fact many are mask-programmed during manufacture in the same manner as a ROM. This is particularly true of PLAs that are embedded in more complex and numerous integrated circuits such as microprocessors. PLAs that can be programmed after manufacture are called FPLA (Field-programmable logic array).