V7-M ARCHITECTURE

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V7-M ARCHITECTURE
V7-A/R/M profiles
Increasing complexity
Increasing number of gates
Increasing performance
Increasing consumption V7-A (Cortex-A5/A8/A9MP/A15MP)

ARM1136
ARM7TDMI ARM926 ARM1176
V7-R (Cortex-R4,R5,R7)
V4T V5TE V6(Z)

V7-M (Cortex-M3, Cortex-M4)

V6-M (Cortex-M0, Cortex-M1)

ARM has identified 3 different markets requiring different core features (around 2005)
Application
Real-Time
Microcontroller

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V7-M ARCHITECTURE
V7-A/R/M profiles

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V7-M ARCHITECTURE
Thumb v2
V4T V5TE V6(Z) V7-A, V7-R V7-M V7-EM
ARM
Thumb v1
Jazelle (V7-A) option
SIMD using regular R0-R12 regs SIMD using regular R0-
R12 regs
TrustZone (V7-A only)
Thumb v2 is a superset of Thumb v1
Thumb-2 EE (V7-A)
VFPv3 option (Simple FPv4-SP option (Simple
and Double Precision) Precision)
NEON (V7-A) option

V7-A and V7-R are compatible with previous ARM architectures

ARM has decided to not maintain this compatibility for V7-M in order to
Simplify the design of the cores
Allow determinism
The exception mechanism of the V7-M architecture describes a nesting mechanism
that enables the accurate calculation of the worst case latency time

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V7-M ARCHITECTURE
Instruction sets
Instruction set Features Architecture Processors

ARM Code machines are all 32-bit long V4T ARM7XX

All instructions can be executed conditionnally, V5TE ARM9XX
except BLX and BKPT V6 ARM1136/1176
V7-R Cortex-R4
V7-A Cortex-A8/A9
Thumb-1 Code machines are all 16-bit long V4T ARM7XX
Interworking is necessary, because exceptions V5TE ARM9XX
cause the transition to ARM state and return from V6 ARM1136/1176
exceptions must be done in ARM state

Thumb-2 Code machines are either 16- or 32-bit long V6 ARM1156

The processor still supports the T-bit, but attempt V7-M / V7-EM Cortex-M3/M4
to perform the transition to ARM state will cause a V7-A Cortex-A5/A8/A9
Usage Error V7-R Cortex-R4
Regarding the V6-M architecture, it is subset of the V6-M Cortex-M1
Thumb-2 instruction set

Thumb-2 is a mix of 16- and 32-bit instructions

IT IS A SUPERSET OF THUMB-1

A key factor is that the application level is consistent across all profiles

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V7-M ARCHITECTURE
Code Size and Performance

Thumb-2 is a mix of 16- and 32-bit instructions

Relative Dhrystone performance and code size for ARM, Thumb and Thumb-2

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V7-M ARCHITECTURE
Cortex-M Instruction Set Evolution

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V7-M ARCHITECTURE
SIMD instructions
The Cortex-M4 implements the V7-EM architecture
Compared to Cortex-M3, DSP-oriented instructions are supported
Example of a SIMD instruction

SMLADX Rd,Rn,Rm,Ra

31 16 15 0
Rn

Rm

* *
31 0
Ra +

CPSR[Q]

Rd

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V7-M ARCHITECTURE
SIMD instructions

A library provided in source format has been developed by ARM and partners
It is called CMSIS 2.0 (Cortex Microcontroller Software Interface Standard)
Standard mathematic functions are supported
FFT, FIR, biquad
Complex arithmetic
Sin, Cos
Matrix calculation
Statistics functions

For instance, let us compare the performance of a 16-bit complex FFT, 1024 samples
with and without DSP instructions

Assembler FFT for Cortex-M3 119_424 clocks

Compiling using V7-M instructions 342_978 clocks
Compiling using V7-EM instructions 88_772 clocks

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CORTEX-M3 BLOCK DIAGRAM

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BLOCK DIAGRAM
Core main features

Harvard Architecture

No cache, No MMU, no coprocessors

All control and status registers are memory-mapped
SCB = System Control Block

The whole code, including boot and exception handlers can be developed in C

Efficient interrupt handling

Automatic register saving / restoring
The vector table contains pointers to exception handlers, not code
Priority level is encoded by a number of bits defined at synthesis stage, from 3 to 8 bits

Hardwired divide instruction

Max 12 clocks to execute a divide

Low power modes

Rely on an external power manager
The Cortex-M3 supports the WFI exception (informs the outer world of the transition to low power state)

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BLOCK DIAGRAM
Harvard Architecture and Bus Matrix

Cortex-M3 core
3-stage pipeline

I D

PPB
(APB)
matrix

AHB-lite
Bus

I-code bus
AHB-lite
Emulation D-code bus
Probe AHB-lite
System bus

Cortex-M3 CPU

AHB (Advanced High-performance Bus): Burst transfers, pipelined operations, etc.

APB (Advanced Peripheral Bus): Designed for low bandwidth control accesses (Register interfaces on
system peripherals for example)

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 BLOCK DIAGRAM
Multilayer Bus Matrix

Contention occurs only if Master 0 & Master 1

try to access same slave

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BLOCK DIAGRAM
Core peripherals
Address Core peripheral

0xE000E008 - 0xE000E00F System control block

0xE000E010 - 0xE000E01F System timer

Sleep Cortex-M3 core 0xE000E100 - 0xE000E4EF Nested Vectored Interrupt Controller
INTNMI
3-stage pipeline 0xE000ED00 - 0xE000ED3F System control block
INTISR[239:0]
NVIC 0xE000ED90 - 0xE000EDB8 Memory Protection Unit
SLEEPING
Interrupts I D 0xE000EDF0 - 0xE000EEFF Debug control and configuration
SLEEPDEEP
0xE000EF00 - 0xE000EF03 Nested Vectored Interrupt Controller

Systick MPU

PPB

PPB
SCB
matrix

AHB-lite
Bus

I-code bus
AHB-lite
Emulation D-code bus
Probe AHB-lite
System bus

Cortex-M3 CPU

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BLOCK DIAGRAM
3-State pipeline

Fetch Decode Execute

Address Data Phase

Phase & Load Store
writeback and Branch

Instruction Decode
FETCH and
Register read Multiply and Divide WR

ALU
Shift And
Branch
Branch

Branch forward and speculation

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BLOCK DIAGRAM
3-State pipeline: Data Path

Instruction
HDATA_I
decode Byte select &
HRDATA_D
Sign extend

Address Byte / Halfword

HWDATA_D
incrementer permute

B
Address
HADDR_D
register
Register
Bank
MUL Barrel
R0-R15 DIV shifter
Address
incrementer xPSR ALU
A

HADDR_I

Address
register Writeback

ExceptionVector

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BLOCK DIAGRAM
Power Management: Sleep Modes
The Wait For Interrupt (WFI) or the Wait For Event (WFE) instructions request the
sleep-now model
Cause the NVIC to put the processor into the low-power state pending a new exception

The Cortex-M3 supports the following sleep modes reducing power consumption:
Sleep Mode
Internal Clock gating
The Cortex-M3 main clock is stopped
Deep Sleep Mode
Indicated to an external power management Unit
Effects are Implementation defined
• Some SoC power domains could be turned of for example

To detect interrupts, the NVIC must remain clocked at all times

Unless the Wake-up Interrupt Controller (WIC) is used (optional)
Provides significantly reduced gate count interrupt detection logic that can take over
and emulate the full NVIC during sleep modes

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BLOCK DIAGRAM
Power Management: Sleep Modes
The NVIC controls the low power modes :

Sleep now Wait for interrupt, reset or debug event

Sleep on exit Sleep immediately on return from last ISR

Deep sleep – Leakage only Power On, most clocks off
Deep sleep – State Retention Most Power off, all clocks off
Wake-up through WIC

ALWAYS POWERED DOMAIN LOW POWER STATE RETENTION DOMAIN

Power
Management Unit
WIC NVIC Cortex-M3 core

Always powered
Stimulus
peripheral
Clamps RAM

The power management relies on an external unit, which is in charge of

Clock gating
Turning power on/off SoC power domains

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 BLOCK DIAGRAM
Power Management: Sleep Modes

Sleep-on-exit Mode:
When SLEEPONEXIT bit of the System Control Register (SCR) is set, the processor
completes the execution of an exception handler and immediately enters sleep mode
IRQ Return from Exception

Sleep Mode IRQ Handler Sleep Mode

WFE as same effect as WFI, but cortex-M3 will also wakes up from a pulse on the event
input pin (what is connected ther is implementation defined)

When SEVONPEND is enabled in the System Control Register (SCR)

Causes WFE to wake up on interrupt, even if the interrupt is not enabled
So the first instruction executed after Wake up, is the one following the WFE
instruction (not the first one of the IRQ Handler)

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BLOCK DIAGRAM
Debug Features

Sleep Cortex-M3 core

INTNMI
Debug
3-stage pipeline
INTISR[239:0] ETM
NVIC Trigger
SLEEPING
Interrupts I D
SLEEPDEEP

Trace port
Systick MPU
DWT ITM TPIU (serial wire
or multi-pin)
PPB

PPB APB APB ROM

SCB I/F table
matrix

AHB-lite
Bus

FPB I-code bus

AHB-lite
Emulation D-code bus
Probe AHB-lite
System bus

Cortex-M3 CPU

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 BLOCK DIAGRAM
Debug Features

Sleep Cortex-M3 core

INTNMI
3-stage pipeline
INTISR[239:0] Debug ETM
NVIC Trigger
SLEEPING
Interrupts I D
SLEEPDEEP

Trace port
Systick MPU
DWT ITM TPIU (serial wire
or multi-pin)
PPB

PPB APB APB ROM

SCB I/F table

matrix
AHB-lite

Bus
FPB I-code bus
AHB-lite
Emulation D-code bus
Probe AHB-lite
System bus

Cortex-M3 CPU

Runtime code can be instrumented in order to track what happens in the core
The ITM unit contains memory mapped FIFOs whose contents are exported through
TPIU to the outer world
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BLOCK DIAGRAM
Debug Features

Sleep Cortex-M3 core

INTNMI
Debug
3-stage pipeline
INTISR[239:0] ETM
NVIC Trigger
SLEEPING
Interrupts I D
SLEEPDEEP

Trace port
Systick MPU
DWT ITM TPIU (serial wire
or multi-pin)
PPB

PPB APB APB ROM

SCB I/F table
matrix

AHB-lite
Bus

FPB I-code bus

AHB-lite
SW/ SW/ APB D-code bus
AHB-AP
JTAG SWJ-DP AHB-lite
System bus

Cortex-M3 CPU

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BLOCK DIAGRAM
Debug Features: SW/SWJ-DPWJ-DP
Invasive debug can be done through either JTAG or Serial Wire
Serial Wire Debug technology (part of the CoreSight Debug Access Port) provides a
2-pin debug port (Low pin count and high-performance alternative to JTAG (5-pin))

Host Host
system Cortex-M3 system Cortex-M3

USB, 2 USB, 5
Ethernet SW Ethernet JTAG
SWJ SWJ
probe probe

Or Host
system Cortex-M3

USB, 2
Ethernet SW
SW
probe

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BLOCK DIAGRAM
Debug Features: TPIU
Non invasive (with ETM) debug can be done through either Serial Wire Viewer or
Parallel Trace port

Cortex-M3 Host
1
system
SWV
TPIU
Port analyzer USB,
SWO Ethernet

Cortex-M3 Host
system
4
Trace
TPIU
Port analyzer USB,
Ethernet
TraceData

Trace is configured by registers accessed through the APB output bus

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 BLOCK DIAGRAM
Summary
Interrupts
INTNMI Cortex-M3 core
3-stage pipeline
INTISR[239:0] Sleep ETM
NVIC Trigger
SLEEPING
Debug
SLEEPDEEP I D

MPU Trace port

DWT ITM TPIU (serial wire
or multi-pin)
PPB

PPB APB APB ROM

I/F table

matrix
AHB-lite
FPB

Bus
I-code bus
AHB-lite
APB D-code bus
SW/ SW/ AHB
AHB-AP
JTAG SWJ-DP AHB-lite
System bus

Cortex-M3 CPU

NVIC Nested Vectored Interrupt Controller DW T Data W atchpoint and Trace SW Serial W ire

MPU Memory Protection Unit ITM Instrumentation Trace Macrocell SW J-DP Serial W ire JTAG Debug Port

AHB Advanced High Performance Bus ETM Embedded Trace Macrocell AHB-AP AHB Access Port

APB Advanced Peripheral Bus FPB Flash Patch and Breakpoint TPIU Trace Port Interface Unit

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BLOCK DIAGRAM
Implementation options

Number of interrupt requests 1-240

Number of exception priority bits 3-8

Optional blocks MPU

ETM

Debug blocks which can be SWJ-DP

replaced with custom IPs TPIU

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REGISTER TYPES

The Cortex-M3 supports 3 families of registers:

General Purpose core registers

16 registers: R0-15
3 of them have a dedicated utilization:
R13 is the Stack Pointer [SP]
R14 is the Link Register [LR]
R15 is the Program Counter [PC]
Arithmetic and logical operations can be done only by using these registers

Special core registers

There are special registers like the status register or the ones to configure
the exception masks for example
They are accessed only by two instructions: MRS [Move To Register from
Special] and MSR [Move to Special from Register]

Memory-mapped registers
As seen before, the core peripherals are configured through memory-mapped
registres
They are accessed by the load and store instructions

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PRIVILEGE LEVELS

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PRIVILEGE LEVELS

Cortex-M3 implement two Privilege Levels

Privileged (Supervisor)
Non-Privileged (User)

The privilege attribute is reflected on interconnect buses

The idea is to protect specific address ranges (datas, I/O registers, etc.) against non-
privileged accesses (placing the Core in the Non-privileged level)

The access rights:

Can be defined by the SOC designer
Can be dynamically configured by the application, using the MPU

Note: The System Control Block registers are all privileged registers

Accessing an address without the right to do it will cause an Exception Fault

When using a RTOS and the MPU

Kernel datas and structures can be protected during a thread execution
More informations on next diagrams

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PRIVILEGE LEVELS
System / User Land
System
Kernel data

Kernel code

Any exception, Cortex-M3 control and status registers

including exception Through a Special
core Register
caused by SVC
execution Some I/O peripherals
(Software Interrupt)

Application data

Application code

Arithmetic and logic flags

Other I/O peripherals

User land

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PRIVILEGE LEVELS

Application Appli Appli

Boot RTOS RTOS RTOS RTOS
task task task

t
Reset Interrupt

Non- Non- Non-

Priv Priv Priv Priv
privilege privilege privilege

The tasks are not permitted to access privilege resources

For instance, a task cannot modify the settings of interrupt controller or MPU

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DOCUMENTATION

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DOCUMENTATION

Software specifications
Hardware specification
V7-M
AMBA v3 (Advanced Microcontroller
AAPCS (ARM Architecture Procedure
Bus Architecture)
Call Standard)

Cortex-M3
Technical
Reference
Manual
(TRM) one per
core version

Debug specification

Coresight

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