CO-526-B

Electronics Lab

Fall Semester 2024

Course Electronics Lab – CO-526-B

Instructors - Uwe Pagel, Res.I Room 37 Tel.: +49 421 200 3114
- upagel (at) constructor.university
- Dr.-Ing. Mojtaba Joodaki Tel.: +49 421 200-3215
- mjoodaki (at) constructor.university

Website - http://uwp-cu-lab.my-board.org/

August 6, 2024
Contents

I General remarks on the course 3

1 Experiments and Schedule 4

2 Lab Guidelines 5
2.1 Grading Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Attendance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3 Prelab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.4 Lab Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.5 Cheating & Copying . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.6 Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.7 Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 Manual Guideline 7
3.1 Circuit Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 Values in Circuit Diagrams . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3 Reading before the first Lab Session . . . . . . . . . . . . . . . . . . . 9

II Experiments 10

4 Experiment 1 : LTSpice Tutorial 11

4.1 Objective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2 Installation of the Simulator . . . . . . . . . . . . . . . . . . . . . . . 11
4.3 LTSpice Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5 Experiment 2 : Diode 22
5.1 Introduction to the Experiment . . . . . . . . . . . . . . . . . . . . . 22
5.2 Prelab Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.3 Execution Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.4 Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

6 Experiment 3 :
Bipolar Junction Transistor (BJT) 40
6.1 Introduction to the Experiment . . . . . . . . . . . . . . . . . . . . . 40
6.2 Prelab BJT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.3 Execution Bipolar Junction Transistor (BJT) . . . . . . . . . . . . . 52
6.4 Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

1
7 Experiment 4 :
Properties of the Differential Amplifier
Introduction to Operational Amplifier 56
7.1 Introduction to the Experiment . . . . . . . . . . . . . . . . . . . . . 56
7.2 Prelab Operation Amplifier . . . . . . . . . . . . . . . . . . . . . . . 67
7.3 Execution Operation Amplifier . . . . . . . . . . . . . . . . . . . . . . 68
7.4 Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

8 Experiment 5 : Metal Oxide Field Effect Transistor 71

8.1 Introduction to the Experiment . . . . . . . . . . . . . . . . . . . . . 71
8.2 Prelab Field Effect Transistor . . . . . . . . . . . . . . . . . . . . . . 80
8.3 Execution Field Effect Transistor . . . . . . . . . . . . . . . . . . . . 82
8.4 Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

9 Experiment 6 : CMOS Inverter and Logic Gates 85

9.1 Introduction to the Experiment . . . . . . . . . . . . . . . . . . . . . 85
9.2 Prelab CMOS Inverters and Logic Gates . . . . . . . . . . . . . . . . 94
9.3 Execution CMOS Inverters and Logic Gates . . . . . . . . . . . . . . 96
9.4 Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

III Additional Information 99

A Appendix 100
A.1 Hardcopy from oscilloscope screen . . . . . . . . . . . . . . . . . . . . 100
A.2 Books and other Tools . . . . . . . . . . . . . . . . . . . . . . . . . . 100

2
 Part I

General remarks on the course

3
1. Experiments and Schedule
1. Week

(a) Introduction to the Lab

Introduction to LTSpice and tutorial
(b) Diode

2. Week

(a) Bipolar Junction Transistor - BJT

(b) Operational Amplifier

3. Week

(a) Metal Oxide Field Effect Transistor

(b) CMOS Inverters and Logic Gates

4
2. Lab Guidelines
2.1 Grading Scheme
1. The lab is a part of the module CO-526 and counts 50%. The grade is in %
and composed of the submitted lab reports and prelabs.

2. Distribution of the grades:

Action Involved Grade

5 Prelabs (Exp.2-6) each 8% Individual 40%
3 Lab Reports each 20% Individual 60%

2.2 Attendance
Attendance to the course is mandatory. Missing an experiment without valid excuse
will subtract 1/6 from the grade.

2.3 Prelab
The experiments must be prepared by each student before they are carried out. The
manual provides a theoretical overview. In the prelab section, questions are asked
which must be prepared in writing before the date. Without the Prelab or at least a
good knowledge of the experiment, the student may be excluded from participation.
The prelab becomes the theory part of the respective report. The prelabs of the
experiments on which no report is written must also be submitted!

2.4 Lab Report

It is mandatory to write three lab reports.The general structure of a report is known
from the first year. Now it should become like this:

ˆ Cover Sheet - as before

ˆ Introduction - prelab belonging to the experiment

ˆ Experimental Set-up and Results - as before

ˆ Evaluation
Conclusion - is now a combined summary including error discussion

ˆ References - as before

ˆ Data from this week’s second experiment.

ˆ Additional: The prelab from this week’s second experiment!!

5
The submission of the report should be by email to [email protected].
Of course in case of computer problems hand written reports are also accepted.
Deadline is the Sunday after the experiment at 23:59. If you miss it, the experiment
will be downgraded or even reduced to 0%!!! As already stated before lab reports
are individual work.

2.5 Cheating & Copying

In case of cheating or plagiarism (marked citations are allowed but no complete
copies from a source) we will follow ’The Code of Academic Integrity’. The
report will be counted as not submitted 0%.
Note that there can be more consequences of a disciplinary nature de-
pending on the circumstances.

2.6 Supplies
All equipment, cabling and component you need should be in your work area. If
you cannot find it, ask your lab instructor or teaching assistant, do not take it from
another group. Before leaving the lab, put everything back, where you found it!
Please bring your laptop so that you can record the readout the oscilloscope.

2.7 Safety
Recall the Safety Session from first semester!

6
3. Manual Guideline
The manual and the course website contain all the necessary information about the
laboratory. In addition, the manual contains a description of all experiments. Each
experiment is divided into the section ”Objective” and one (or more) subsection(s)
with ”Preparation”, ”Execution” and ”Evaluation”.

The Objective Section should give an introduction to the problem. In some

cases it also contains theory not completely covered in the lecture.

The Preparation Section describes the electrical setup.

The Execution Section is a detailed description on what to do and how and

what to measure.

The Evaluation Section should deepen the understanding of the topic. There
are questions about the experiment. You should solve these with help of the taken
data and compare the results to theory.

Before starting the experiment, read the complete description and try to understand
the problem. If something is not clear, read again and/or ask the TA/instructor.
Follow the preparations carefully to have the proper setup(s) and not to destroy
any component. Be sure to record -ALL- required data. All group members should
document the experiment! If data is missing you will have problems evaluating the
experiment!!

3.1 Circuit Diagrams

Next is an overview about the used symbols in circuit diagrams.

Connections

connected not connected

wire
wires wires

Connection are usually made using 1 or 0.5m flexible lab wires to connect the setup
to an instrument or voltage source and short solid copper wires on the breadboard.
In most of our experiments we consider these connections as ideal, i.e. a wire is a
real short with no ’Impedance’. In the following semesters you will see that this is
not true.

7
 Instruments

+ +
A ammeter V voltmeter

Since we use multimeters this symbol tells you how to connect and configure the
instrument. Take care of the polarity. Be careful, in worst case you blow it!!!

Voltage/Current Sources

+ +
V ~

fixed variable real ideal AC source pulse

real ideal current source signal generator generator
voltage source

These are the symbols used in the manual. If you check the web and look into
different books there are also other symbols in use!

Lumped Circuit Elements

+ +

variable electrolytic
resistor capacitor inductor
resistor capacitor

There is a different symbol for every lumped circuit element. Depending which
standard is used (DIN or IEC).

Semiconductors

NPN PNP N-channel P-channel diode zener diode

Transistor JFET

Same as with the symbols before you may find different representations for every
component!

8
3.2 Values in Circuit Diagrams
As you will see in the lab, we use resistors with colored rings. These rings represent
numbers or a multiplier. Most of the resistors have five rings. Three digits for the
value, one multiplier for the dimension, and one for the tolerance. In the circuit
diagrams we have a similar scheme. There are three digits and a dimension. The
letter of the dimension also acts as the comma i.e.:

1R00, 10R0, 100R for 1 Ω, 10 Ω, 100 Ω (= Value ∗ 100 )

1K20, 10K0, 100K for 1.2 KΩ, 10 KΩ, 100 KΩ (= Value ∗ 103 )
1M00, 10M0 for 1 MΩ, 10 MΩ (= Value ∗ 106 )

The numbering for capacitors in the circuit diagram is similar. Only the dimension
differs. Instead R, K, M (Ω, KΩ, MΩ) we have µ, n, or p (µF, nF, pF) (i.e. 1n5
means 1.5nF). The value is printed as number on the component.

3.3 Reading before the first Lab Session

As preparation for the first lab session read the description of the workbench, es-
pecially the parts about the power supply and the multimeter. You will find the
document on the course Web page in ’GeneralEELab I & II Files’
’Instruments used for the Experiments’.

9
 Part II

Experiments

10
4. Experiment 1 : LTSpice Tutorial
4.1 Objective
In this session you should explore the basic functions of the LTSpice program. First
use the hints given with the different problems. If you do not understand something
use the build-in help of the program. Discuss with your group mates. If you come
to no solution ask the instructor or the TA’s.
Before you start with a problem read it completely until the end!

4.2 Installation of the Simulator

The prerequisite for the course and this tutorial is the introduction to Spice and
an operational copy of the program on your computer. Download LTSpice from
’–Analog Devices–’. It is available as Windows and MAC OS X 10.9+ version! As
Linux user either use a virtual machine on your system running Windows (e.g. Or-
acle VM VirtualBox) or install ’Wine’. Install LTSpice with the suggested options.
There is also a ’Getting Started Tutorial’ and a lot other material on this page!

Although the simulator includes a lot of elements in it’s libraries some components
for the course are missing. Download the following file from the course WebSite:

ˆ AdvEE Components.zip
An analog library with all needed components.

Use the install procedure attached to the zip file.

A second way to include the external libraries is to unpack the archives somewhere
and to announce the path in ’Control Panel->Sym&Lib Search Path’ of LTSpice.

11
4.3 LTSpice Exercises
4.3.1 Problem 1 : Simulate a circuit using a Netlist
Abstract
The circuit to be analyzed is described by a text file called a netlist. Following rules
count for the lines in the netlist:
ˆ Letter case, leading spaces, blanks, and tabs are ignored.

ˆ The first non-blank character of a line defines the type of the of the line. Either
comment, circuit element, continuation of line, or simulation directive.
The very first line in the list is ignored. It is reserved for a title or comment and it
is not used for the simulation! The remaining lines describe the circuit. The order
is optional! The whole list is ended by the ’.END’ statement. Anything behind will
be ignored. In LTSPice it can be omitted. The meaning of the lines is as follows:
ˆ A line starting with ’*’ is a comment.
Note : A semicolon ’;’ somewhere in a line also starts a comment.

--- Example
* This is a full line comment
.op ; this is a comment at the end of a simulation directive

ˆ A line starting with a plus sign ’+’ is a continuation from a previous line.
Sometimes lines become very long. So it is used to make the list better read-
able.

--- Example
Rrout ; not very long line ...
+ node1 node2 value ; ... but continued on a second line

ˆ A line starting with a letter from ’A’ to ’X’ describes the type of a compo-
nent with its connections and values. Components are devices like resistors,
inductors etc. and dependent/independent current or voltage sources. E.g. R
stands for resistor, L for inductor, and V for an independent voltage source.
The descriptive letter is followed by a name, the node names and the value (in
case of a component) or value/function (in case of a source).
See the LTSpice help file for the different available elements and syntax. (un-
der ’Content/LTspice/General Structure and Conventions’ and ’../Circuit El-
ement Quick Reference’).

--- Example
Rrout n1 n2 1K ; a resistor with name ’rout’
; two nodes (of course) named ’n1’ and ’n2’
; and the value ’1k’ Ohm
V1 1 0 sin(0 1 1k) ; an independent voltage source named ’1’
; has two nodes named 1 and 0. Node name 0 is
; reserved for the ground node
; AC source sin(offset amplitude frequency)

12
 ˆ A line starting with a dot ’.’ is a simulation directive.

--- Example
.DC ; Perform a DC Source Sweep Analysis
.lib MyParts.mod ; tells the simulator to use a special library

See the LTSpice help file for the different dot commands and their syntax.
(under ’Content/LTspice/Dot Commands’).

Numbers can be expressed in scientific notation; e.g., 1e3, in normal format 1000;
but can also use engineering multipliers. So 1000 may be written as 1K. Below is a
table of understood multipliers:

Suffix Multiplier
T 1012
G 109
Meg 106
K 103
Mil 25.4 ∗ 10−6
M, m 10−3
u(or µ) 1−6
n 10−9
p 10−12
f 10−15

Table 4.1: SI decimal multipliers

The suffixes are not case sensitive. Unrecognized letters immediately following a
number or engineering multiplier are ignored. Hence, 10, 10 V, 10 Volts, and 10 Hz
all represent the same number, and M, MA, MSec, and MMhos all represent the
same scale factor (.001). A common error is to draft a resistor with value of 1 M,
thinking of a one Megaohm resistor, however, 1 M is interpreted as a one Milliohm
resistor. This is necessary for compatibility with standard SPICE practice. LTSpice
will accept numbers written in the form 6 K34 to mean 6.34 KΩ. This works for any
of the multipliers above.
Nodes names may be arbitrary character strings. Global circuit common node
(ground) is ’0’, though ’GND’ is special synonym. Note that since nodes are char-
acter strings, ’0’ and ’00’ are distinct nodes.

13
Next a complete example:

.ac dec 5 10 10e6

;tran 0 500us 0 5u
1 R1 Vo
Vo
1k
V1 C1

100n
0 SINE(0 1 2kHz) 0
AC 1

E_Lab\Electronic_Devices_Lab\Exp
Figure 4.1: Netlist example circuit

Now the commented netlist for the circuit above:

LPFILTER.CIR - SIMPLE RC LOW-PASS FILTER - 1. Line header
* Comments follows
* V = voltage source named V1
* positive end of source at node 1, negative end at node 0 (Gnd)!
* for .tran analysis sin with 0V offset, 1V Amplitude f=2KHz
* for .ac analysis 1V Amplitude
V1 1 0 SIN(0 1 2KHZ) AC 1
*
* Resistor 1 connected to node 1 and Vo with 1KOhm
R1 1 Vo 1K
*
* Capacitor 1 connected to node Vo and Gnd
C1 Vo 0 100n
*
* .ac AC analysis in decades (10, 100, 1k, 10KHz ...)
* 5 points per decade, starting from 10Hz to 10M(ega)Hz
* finally displays a bode plot
.AC DEC 5 10 10MEG
*
* .tran transient analysis
* stepsize, zero means program will determine the optimal
* simulate for 500us, start to save at 0s shortest step 5us
* !!!!!
* this directive is taken as a comment! LTSpice is not able
* to make several analysis methods at a time. So include
* whatever you need, but uncomment to get one single methode
*
;.TRAN 0 500US 0 5u
.END

To create a netlist you may use any editor which creates a pure ASCII file or LTSpice
itself. In general it is not very common to use a netlists for simulating a circuit.
This method is mostly used if you need to create a .model or .subcircuit.

14
Preparation
Start the simulation program. Open a new ’*.cir’ file (use File/Open). A window
with header line end ’.END’ statement will appear. Create a netlist for the following
circuit. The simulator should perform a DC operation point analysis (’.op’).
Before you start preparing the net list first number all nodes in the schematic!
That will avoid errors when defining the connection points for the elements. Again:
ground is node ’0’ !!!

R1 R3
11k 1e3
R5
V1
5V 1k
R2 R4
1k 1000

edEE_Lab\Electronic_Devices_Lab\Expe
Execution
Run the simulation for the created netlist. Check if the values make sense!

Evaluation
For the DC operation point you get a window with all node currents and voltages.
This problem is solved if you show the correct values to the instructor/TA’s.

15
4.3.2 Problem 2 : Perform a DC Sweep Simulation
Preparation

In the problem before we used a netlist to describe the circuit. From now on we use
the usual way to use a simulator. Open a new schematic (use the ’New Schematic’
button in the toolbar or the ’File’ menu). Sketch the following circuit:

;op
.dc v1 0 25 0.1 i1 0 100u 10u
V1
Q1
100µ 2N2222
10V

I1

Some hints: dEE_Lab\Electronic_Devices_Lab\Exper

ˆ Use the ’Component’ button from the toolbar, or the ’Edit/Component’ menu
to find the two sources and the transistor.

ˆ In the select component box use the symbol ’voltage’ to get the voltage source
and the symbol ’current’to get the current source. Place the cursor over the
sources and right click if you see the pointing hand. Now you can insert the
static values from the schematic. For later usage, if you select ’advanced’ you
can define different functions as signal. E.g. like with a function generator.

ˆ Be careful with placing the current source. Current flow is in direction of the
pointing arrow. You can rotate the symbol with ’Cntrl R’ !

ˆ To get the transistor select ’npn’ from the select component box. This is a
generic type already usable for a simulation. But here we want a specific type.
Place the cursor over the transistor symbol. If you get the pointing hand right
click again. Select ’Pick New Transistor’ and find the 2N2222.

ˆ Now place the ’Ground’ symbol/s.

ˆ Connect all components using the ’Wire’ button from the toolbar.
Important, do not forget : Use the ground symbol!! It is not enough to
connect all components. You need at least one net which is declared to be the
’official’ ground.

ˆ Do not forget to save the circuit! Use a descriptive name!!!

16
Execution
ˆ First do a DC operation point analysis. The operation point is the steady state
for direct currents and voltages. During calculation capacitances are open-
circuited and inductances short-circuited. Select ’Simulate/Edit Simulation
Cmd’ from file menu . In the opening window select ’DC op pnt’. After ’OK’
place the appearing rectangle somewhere in the window (’.op’ appears). Now
run the simulation.
Use the cursor in the schematic. Values for voltage, current, and power will
appear in the bottom status line. Measure and record IB and IC . Do the
values make sense? If yes continue!

ˆ The main task is to show the output characteristic of the transistor. To do this
we have to perform a ’DC sweep’. The DC sweep function varies one or more
of the static sources to verify the behavior of a circuit under different/changing
static conditions. E.g. another task would be to check the operation point for
an amplifier at changing supply voltage.
Again open the simulation command menu. Now select ’Dc sweep’. To visu-
alize the output characteristic we have to vary the base current in big steps
and the collector voltage in fine steps to find the collector current. The value
of the ’1st Source’ tab in the window becomes the x axis of the created plot.
UCE should become x axis. V1 is the source for UCE . Vary UCE from 0 to 25 V
in 0.01 V steps. This variation is done for every step of the ’2nd Source’. Vary
IB from 0 to 100µ A in 20µ A steps. After ’OK’ place the appearing rectangle
somewhere in the window (.dc v1 0 25 0.01 i1 0 100u 20u should appear). If
the ’.dc’ command is placed watch the ’.op’ command. It will be commented
out automatically !

ˆ Now run the simulation. After the first run without an elected node or current
only an empty plot window will appear. X axis is the voltage of V1. Activate
the schematic window. Now you can select voltage potentials with the cursor.
Whenever you touch a wire line the cursor changes to a probe symbol. If
you click this signal will be displayed. Close to a pin (e.g. the collector pin)
the cursor changes to a clamp on ammeter, if you click the current will be
displayed. We need IC . If you select IC the output characteristic becomes
visible.

Evaluation
This problem is solved if you show the correct values of the ’.op’ simulation and the
output characteristic to the instructor/TA’s.

17
4.3.3 Problem 3 : Perform a Transient Analysis
Preparation
Sketch the following circuit:

C1 L1

1µF 10mH
V1
R1
SINE(0 1V 2KHZ)
1k2
AC 1V

.tran 0 10m 5m
;ac dec 100 10 100Kz

Some hints: cedEE_Lab\Electronic_Devices_Lab\Experim

ˆ Use the same methods to place the components as before.

ˆ With a right click into the voltage source and selecting ’advanced’ you can
define the function.
Sine, 0 V offset 1 V amplitude, f = 2 KHz.
These inputs are only valid for a transient analysis. To prepare also the next
problem define the ’AC Amplitude’ in the ’Small signal AC analysis(AC)’ box.
AC amplitude should be 1 V.

ˆ For capacitor, inductor, and resistor the generic component is in the top tool-
bar and not in the add component menu. Select and place the component. If
you place the cursor over these components you get the pointing hand again.
With a right click you can choose a specific type and value. Similar on how
you choose the transistor type.

ˆ Again do not forget the ground symbol!!

Execution
ˆ This time we want to perform a transient (.tran) analysis. This is a direct
simulation of a circuit. Comparable what happens when you build the circuit
on the breadboard use a function generator as source and the oscilloscope to
measure.
Open the simulation command menu and open the ’Transient’ tab. Set the
stop time to 10ms. Set ’Time to Start Saving Data’ to 5ms. After ’OK’
place the appearing rectangle somewhere in the window (’.tran 0 10ms 5ms ’
appears). The simulation will start at t = 0 and will last until t = 10ms. Data
for all(!) signals somewhere in the circuit will be taken starting at t = 5ms.
Now run the simulation. An empty plot window will appear. X axis is the
time.

18
 ˆ Activate the schematic window. Use the cursor to select the wanted signals.
Display the following:

– Voltage over R1 relative to ground.

This is simple since the reference is ground by default! If the cross cursor
is close to the wire at R1 the symbols will change to a probe icon. A left
click will select the signal and display the graph in the plot window.
– Voltage over L1.
To display the voltage over L1 we need to define a reference point first.
In the given schematic place the cursor on the wire to the right of the
inductor. If the probe symbol appears press the -right- mouse button.
A drop down menu will show up. Select ’Mark Reference’. A dark grey
probe symbol is now displayed at this wire. Every selected signal from
now on is referenced to this point (until you change again). To get the
voltage over L1 you have to select the other end of the inductor with the
normal left click when the ’red’ probe is displayed.
– Current through R1.
Place the cursor over R1. A clamp on ammeter symbol appears. A left
click will display the current on the right side of the plot pane!
– You should see about ten periods in the plot area. Now zoom into the
signal. Left click on the x scale. A window will open. Change the display
that you can see only two periods.
– Measure the period of the sine.
Activate the plot window. Right click on the label for the voltage over
R1. In the opening window select the ’Attached Cursor’ to first and
second. After ’OK’ the cursors and a window with values appear. Use
the mouse to position the cursors. In the small window you can read the
time and voltage values, this is similar to the usage of the cursors in the
oscilloscope. To make things easier you can switch on grid lines if you
right click inside the plot and select them from the drop down menu.

Evaluation
This problem is solved if you show the plot with the requested diagrams and the
measured frequency to the instructor/TA’s.

19
4.3.4 Problem 4 : Export Data to Matlab
Preparation
In general it is possible to export the data. As example you should plot some of the
signals with MatLab. Use the circuit from the problem before.

Execution
ˆ Run the simulation again. Plot the voltage over and the current through R1.

ˆ Activate the plot window. Select ’File/Export data as text’. In the open
window set the destination filename. All available signals are visible. Two
should be selected already. Add ’V(n001)’ by ’Ctrl-Click’. Three highlighted
signal should be visible now. With ’OK’ you export the data to a text file.
ˆ Now open Matlab. Look at following code fragment:
% 1. Clear the MatLab environment
clear; clc; close all

% 2. Read the data from the LTSpice file.

% Use the command ’dlmread’. In our case the syntax is:
% M = dlmread(filename,delimiter,R1,C1)
% ’M’ is the matrix, ’filename’ is your file, ’delimiter’ is the
% delimiting character between the columns, ’R1’ is the first row
% in your file to read, and ’C1’ is the first column in your file.
% Read the values from file ’YourFile.txt’ into matrix ’y_arr’.
% Delimiting character is a TAB (\t). Start importing data from the
% second line (first is header, no numbers) and the first column.
% Line and column count starts from 0!!!
y_arr = dlmread(’YourFile.txt’, ’\t’, 1, 0);

% 3. Read every column of the matrix into a separate array for time,
% voltage 1, and voltage 2 and the current
t = y_arr(1:end, 1); % start reading column 2 (first is empty!)
v1 = y_arr(1:end, 2);
v2 = y_arr(1:end, 3);
i = y_arr(1:end, 4);

% 4. Plot the different properties

plot (t, v1);
hold on
plot (t, ...)
...

Depending on your file use this fragment and plot the three exported signals.

Evaluation
This problem is solved if you can show the MatLab plot with all three signals to the
instructor/TA’s.

20
4.3.5 Problem 5 : Perform a AC Analysis
Preparation
The AC analysis will show you the behavior of a circuit with changing frequency at a
source. Together with our resonance/filter circuit it is comparable to the frequency
sweep we did in the RLC circuit breadboard experiment last semester. Use the
circuit from before:

C1 L1

1µF 10mH
V1
R1
SINE(0 1V 2KHZ)
1k2
AC 1V

;tran 0 10m 5m
.ac dec 100 10 100Kz

cedEE_Lab\Electronic_Devices_Lab\Experim
Execution
ˆ Add the simulation command for ’AC Analysis’. Use a ’decade’ sweep with
about 10 to 100 points per decade. Start frequency is 10Hz stop frequency is
100KHz. Beside the source you should read ’AC 1’. If not open the property
menu for V1 and add 1V for ’AC Amplitude’ in the ’Small signal AC analy-
sis(AC)’ box. After ’OK’ and placing the label you should see ’.ac dec 100 10
100K’. Run the simulation.

ˆ Select the voltage over R1 and over C1/L1. You get the Bode plot for both
signals.

Evaluation
This problem is solved if you can show the plot to the instructor/TA’s.

21
 Electronics Lab, Advanced Electrical Engineering Lab course II, Spring 2010, Jacobs University Bremen

5. Experiment
Objectives 2 : Diode
of the Experiment

5.1 Introduction
The objective of experimentto1 the
of theExperiment
Electronics Lab (Advanced Electrical
Engineering Lab Course II) is to become familiar with semiconductor diodes and
5.1.1 Objective
their application. of the introduces
The handout Experiment the properties and the device behavior
of different
The diodes
objective like rectifier
of experiment 1 isdiodes and familiar
to become Zener diodes.
with semiconductor diodes and
their application. The handout introduces the properties and the device
Throughout the experiment, several applications like rectifiers, voltagebehavior of
regulators,
different
clampersdiodes like rectifier
and clippers diodes
will be and Zener diodes. Throughout the experiment,
examined.
several applications like rectifiers, voltage regulators, clampers and clippers will be
examined.
Introduction
5.1.2
A diode isIntroduction
one of the simplest electronic devices, which has the characteristic of
passing current in only one direction. However, unlike a resistor, a diode does not
A diode linearly
behave is one of therespect
with simplestto electronic devices,(the
applied voltages which hashas
diode theancharacteristic
exponentialofI-V
passing
relationship) and hence is not simply described by an equation such does
current in only one direction. However, unlike a resistor, a diode not
as Ohm's
behave
law for linearly
resistors. with respect to applied voltages (the diode has an exponential I-V
relationship) and hence is not simply described by an equation such as Ohm’s law
The diode is considered a passive element; we do not expect it to amplify power.
for resistors. The diode is considered a passive element; we do not expect it to
There are two operating regions for the diode, reverse biased region, and forward
amplify power. There are two operating regions for the diode, reverse biased region,
biased region.
and forward biased region. The diode is a semiconductor pn junction. In addition
The
to diode
being is a semiconductor
applied as a diode, the pnpn junction. Inthe
junction is addition to beingofapplied
basic element as a diode,
bipolar-junction
the pn junction
transistors (BJTs)is andthe field-effect
basic element of bipolar-junction
transistors (FETs). Thus,transistors (BJTs) and
an understanding of
the physical operation of pn junctions is important to understand the operation of of
field-effect transistors (FETs). Thus, an understanding of the physical operation
pn junctions
diodes, BJTs is important
and FETs. to understand the operation of diodes, BJTs and FETs.

5.1.3 Theoretical
Theoretical Background
Background
Diode Structure
Structure
The semiconductor
The semiconductordiode
diodeisisa apnpnjunction
junctionasasshown
shown
in in Fig.5.1.
Fig. 1.1.AsAsindicated,
indicated, the
the
pn junction consists of p-type semiconductor material in contact with
pn junction consists of p-type semiconductor material in contact with n-type semi- n-type
semiconductor
conductor material.
material. A variety of semiconductor materials can be used to form pn

n-type p-type
region region
Cathode Anode
Metal
Metal
PN junction contact
contact
Fig. 1.1 pn junction diode structure
Figure 5.1: pn junction diode structure
A variety of semiconductor materials can be used to form pn junctions like silicon,
germanium, or gallium arsenide…etc. However,
22 we will concentrate on silicon, as
this is the most widely used material in microelectronics.
 Electronics
Electronics Lab, Advanced
Lab, Advanced Electrical
Electrical Engineering
Engineering Lab course
Lab course II, 2010,
II, Spring SpringJacobs
2010, Jacobs University
University BremenBremen
Electronics Lab, Advanced Electrical Engineering Lab course II, Spring 2010, Jacobs University Bremen

In actual
In junctions
actual practice,practice, both
the pthe
both germanium, andp nand n regions part are of
parttheofHowever,
the same silicon crystal.
like silicon, orregions
galliumare arsenide...etc. same silicon
we willcrystal.
con-
The The
Incentrate
actual pn
pn junction junction
practice, is
is formed
bothformed
byisp
the by
creating creating
andmost n regions regions
of
are of different
different
part of doping doping
theinsame (p and (p and n
n regions)
silicon regions)
crystal.
within on
a silicon,
single as this
peace of the
silicon. Thewidely used
material material
is doped microelectronics.
by bringing in additional
within
The a
In atoms single
pn junction
actual peace
is formed
practice, of silicon.
bothThe by creating
the The material
p and n regionsregions is
of doped
aredifferent by bringing
doping
part ofdonors
the same (p andin
siliconadditional
n regions)
crystal.
atoms
within a single(impurities).
(impurities). peace impurities
Theof impurities
silicon. Thecan can be
be either
material either
donors or or acceptors
acceptors atoms. atoms.
TheThepn junction
words is formed
acceptor andby donor
creating can regions
be ofisdifferent
doped
associated
by
with
bringing
doping (p and
donating
in nadditional
and regions)
accepting
The
atomswords acceptor The
(impurities). and donor can can be associated with donating and accepting
within a single
electrons. In peace
the caseof impurities
silicon.
of donor Theatoms,
be either
material
the material
donors
is doped gets
or acceptors
by bringing
n-type
atoms.
in additional
doped, whereas
electrons.
The words In acceptor
the case and of donor
donor atoms,
can theassociated
be material gets withn-type doped,
donating and whereas
accepting in in
atoms
the (impurities).
case of acceptor The atoms
impuritiesthe can be either
material gets donors External
p-type. or acceptors wire atoms.
connectionsThe to
the case of In
electrons. acceptor
the caseatoms of donorthe material
atoms, the gets p-type.gets
material External
n-typewire connections
doped, whereastoin
thewords
pthe
and acceptor
p and
n n and
regions donor
regions
(diode can
(diode beterminals)
terminals)associated
are withmade
are
made donating
through and
through
metal accepting
metal
(e.g. electrons.
(e.g. aluminum)
aluminum)
the case of acceptor atoms the material gets p-type. External wire connections to
In the case
contacts.
contacts. of donor atoms, the material gets n-type doped, whereas in the case of
the p and n regions (diode terminals) are made through metal (e.g. aluminum)
acceptor atoms the material gets p-type. External wire connections to the p and n
contacts.
regions (diode terminals) are made through metal (e.g. aluminum) contacts.
pn Junction
pn Junction
pn
To pnJunction
To understand
Junction
understand how a howpn ajunction
pn junction is formed
is formed westart
we will will start by imagining
by imagining two separate
two separate
pieces
To pieces of semiconductor,
of semiconductor, oneis n-type
one n-type and theand the other
other p-type p-type as shown
as shown in Fig.1.2.
in Fig.1.2.
Tounderstand
understand
Now we
how
how
bring
aa pn
the pn
two
junction
junction
pieces is formed
formed to
together
we will
will start
wemake start
one
by
by imagining
imagining
piece of
two
two separate
semiconductor.separate This
Now
pieceswe ofbring the two pieces
semiconductor, together
onen-type
n-type to make one piece of semiconductor. This
pieces of semiconductor,
results in the formation oneof a pn andand
junction thethe other
other
(Fig.1.3).
p-type
p-type as shown
as shown in Fig.in5.2. Fig.1.2.
Now
results in the formation of a pn junction (Fig.1.3).
Now we bring the two pieces together to make one piece of semiconductor. This
we bring the two pieces together to make one piece of semiconductor. This results
results in the formation of a pn junction (Fig.1.3).
in the formation of a pn junction (Fig. 5.3).
free electronsdonordonor
free electrons atoms atomsfree holesfree holesacceptor acceptor
atoms atoms
free electrons donor atoms free holes acceptor atoms
n-typen-type p-typep-type
n-type p-type
CB CB
CB CB CB
CB BandBand
gap gap
BandBand
gap gap Band
VB gap
VB
Band gap VB
VB VB
VB
Fig. Fig.5.2:
Figure
1.2: 1.2:Separate
Separate
Separate pieces
pieces
pieces Fig.
Fig. 1.3: Figure 1.3:5.3:
pn-junction
pn-junction pn-junction
Fig. 1.2: Separate pieces Fig. 1.3: pn-junction
The periodic structure of the semiconductor (in our case silicon) leads to the for-
The The
periodic
mation periodic
of energystructurestructure
levels.of Only
theof semiconductor
the
two semiconductor
of these energy (in our(in ourarecase
case
levels silicon) silicon)
of interest leads toleads
to the
us: theto the
The formation
formation
periodic
conduction of energy
andof energy
thelevels.
structure levels.
Only
of the
valence band. Only
two two
of these
semiconductor
These of these
energyenergy(in energy
levels
ourcan
levels caselevels
are
be now of
silicon)are of
interest
occupied interest
leadsorto to us:
the
unoc- to us:
the the conduction
conduction
formation
cupied. of energy
The and the
conductionand the
valence
levels.band valence
Only inband.
atwo band.
These
of these
semiconductor These
energy energy
energy
(the levels levels
levels can
arebe
semiconductor can
ofnow beassumed
now
occupied
interest
is occupied
to us:
to
or
the or unoccupied.
unoccupied.
conduction The
and The
the conduction
conduction
valence band
band. band
in a
These in a semiconductor
semiconductor
energy levels (the
can (the semiconductor
semiconductor
be now occupied is is
be undoped) is typically empty, whereas the valence band is completely filled with
assumed
assumed
orelectrons.
unoccupied. to betoThe be conduction
undoped)undoped) is typically
is typically
band inempty, empty,
whereas
a semiconductor whereas the the
(the valence valence
semiconductor bandband isis is
completely
completely
assumed filled
to bewith filled with electrons.
electrons.
undoped) is typically
By introducing donors or acceptors, theempty,
situation whereas
can be the changed. valence band is
Introducing
completely
By By introducing
introducing
donors leads filled with
todonors
an electrons.
donors or the
or acceptors,
increase of acceptors, the situation
the situation
concentration can be
of electrons canin be
thechanged.
changed. conduction Introducing
Introducing
band.
donorsdonors
Electronsleads leads
are to an
free to
to an
increase
move increase
in of
the the of the
conduction concentration
concentration
By introducing donors or acceptors, the situation can be changed. Introducing band upof on of electrons
electrons
an electric in the
field. in the conduction
conduction
Introducing
band. band.
Electrons
acceptors
donors leadsElectrons
leads toareto are
anafree free
to
decrease
increase move to
of move
of the
the the inconduction
inelectrons the concentration
concentration conductionofband band
up onup
in the
electrons anon
valence
in the an
electricelectric
band, thefield.
field.
conduction
Introducing
Introducing
missing
band. acceptors
electrons
Electrons acceptors
are leads
in free
the leads
to a band
valence
to move to a
decrease
in thedecrease
areconduction
the of
of holes, the
the electrons
which electrons
band are now
on an concentration
upconcentration
free to move
electric the in the
in field.
in
thevalence
valence
Introducing band,
valence band, the missing
the missing
acceptors
band. leads toelectrons
electrons in theinvalence
a decrease the valence
of the band
electronsband
are the areholes,
the holes,
concentration whichinwhich
the are
are
now now
free free
to move to move in the valence band.
valence
Free band,
electrons oninthe
the the
missingvalence
n-side electrons
and freeband. in the
holes onvalence
the p-side band are the holes,
can initially which the
diffuse across are
now free
Free
junction
Free electronsto move
electrons
because inthe
on of then-side
on
the valence
the n-side
presence and band.
of aand free
holesholes
concentration
free on p-side
on difference
the the p-side
at can can initially
the boundary.
initially Holes
diffuse diffuse
willacross
across
Free diffuse the
the junction
electrons from junction
onp-side
becausebecause
to n-side
the n-side theofleaving
of and the presence
presence
free uncompensated
holes of on ofthea concentration
a concentration boundcan
p-side negative difference
difference
initially at theat the
acceptor
diffuse
boundary.
ions behind.
boundary.
across theHoles Holes
Thus,
junction will thewill
diffuse
because diffuse
region from
of from
directly
thep-side p-side
to to
presencethen-sideto
right n-side
of aofleaving leaving
the boundary
concentration uncompensated
will
uncompensated be negatively
difference bound
at thebound
boundary. Holes will diffuse from p-side to n-side leaving uncompensated bound
23
4 4
4
 Electronics Lab,
Electronics
AdvancedLab,
Electrical
AdvancedEngineering
Electrical Lab
Engineering
course II,Lab
Spring
course
2010,
II, Spring
Jacobs2010,
University
JacobsBremen
University Bremen

Electronics
Electronics
Lab,
Lab,
Advanced
AdvancedElectrical
Electrical
Engineering
Engineering
LabLab
course
courseII,II,
Spring
Spring2010,
2010,
Jacobs
Jacobs
University
University
Bremen
Bremen
negative negative
acceptor acceptor
ions behind.
ions behind.
Thus, theThus, region the directly
region to
directly
the right
to the of right
the of the
boundaryboundary
will be negatively
will be negatively
charged.charged.
Similarly,Similarly,
a positively a positively
charged charged layer in the layer in the
charged.
n-side ofn-side Similarly,
the boundary a
of the boundarypositively
will be built charged
willupbefrom layer
built the
up from in the
donorthe n-side
ions. of
donor ions. the boundary will be
negative
negative acceptor
acceptor ions ions behind.
behind. Thus,Thus, the the regionregion directly
directly toto the the rightright ofof the the
Whenbuilt
boundary
up
freefrom
a When
boundary will
will
the
electron
a befree donor
electron
meets
benegatively
ions.acharged.
negatively meets
free hole
charged. aSimilarly,
free
recombination
Similarly, hole recombination
aapositively
positivelyoccurs
charged (Fig.
charged occurs 1.4),
layer
layer (Fig.
ininthis
the 1.4), this
the
When
n-side
meansn-side
the aof
of
means free
the
hole electron
theboundary
boundary
the
and hole meets
will
electron
andwillbe a built
be free
electron
cancel hole
builtupup
each recombination
from
from
cancel thethe
other. donor
eachdonor occurs
ions.
aions.
Asother. As a(Fig.
result, the
result,5.4),the
free thisfree
electronsmeans electrons
the
nearWhen
the hole
near and
junctionthe electron
junction
tend to cancel
cancel
tend each
to each other.
cancel other,
each As a result,
producing
other, the
producing
a freeadepleted
region electrons
region near
depleted
of any the of any
Whenaafree freeelectron
electronmeetsmeetsaafree freeholeholerecombination
recombinationoccurs occurs(Fig. (Fig.1.4),
1.4),this this
junction
moving charges.
moving tendcharges.
to cancel
This creates
This each
what other,
creates producing
is called
what is
the called a the
depletionregion depleted of any moving
means
means the
theholehole and
and electron
electron cancel
cancel each
each other.
other. Asadepletion
As region
aresult, (Fig.
result,the region
the 1.5).
free
free (Fig.
electrons1.5).
electrons
charges.
near
nearthe
This
thejunction
creates
junctiontend
what cancel
tendtotocancel
is called
each
the other,
eachother,
depletion region (Fig.
producing
producingaaregion
5.5).depleted
regiondepleted
The chargesofofanyany
on
moving
movingcharges.
charges.This
Thiscreates
createswhat
whatisiscalled
calledthe
thedepletion
depletionregion
region(Fig.
(Fig.1.5).
1.5).
DepletionDepletion
region region

Depletion
Depletionregion
region
CB CB
CB CB
CB
BandCB
gapBand gap
Band gap
CBBand gap
CB

Band
Bandgap
gap Band
Band
VBgap
gap VB
VB VB
VB
VB
VB
VB
Fig. 1.4 Electrons-holes
Figure Fig. Electrons-holes
5.4: 1.4 Electrons-holes recombination Fig.Figure
recombination
recombina- 1.5 Depletion
Fig.
5.5:1.5 Depletion
regionregion
Depletion region
tion
Fig.
Fig.1.4
1.4Electrons-holes
Electrons-holesrecombination
recombination Fig.
Fig.1.5
1.5Depletion
Depletionregion
region

Theboth
charges
The
sidescharges
on both
of the on
sides
depletion both ofregion
sides
the depletion
of theandepletion
cause region field
electric cause
region
to an
because
electric an field
established electricto be
across field
the to be
established
The established
region;
Thecharges across
hence
charges aon
on the
across
bothregion;
potential
both sides
sidestheofof hence
differenceregion;
the ahence
results
thedepletion potential
depletion a potential
across
region
region difference
the difference
depletion
cause
cause ananresults
region,
electric
electric across
results
withtoto
field
field the
across
n-side
be be the
depletion depletion
region,
established
atestablished with
region,
across n-side
acrossrelative
positive voltage the with at
theregion; n-side
region;positive
hence
to p-side at
hence voltage
positive relative
aapotential
(Fig. voltage
potential
5.6). Thus, to
relative
p-side
difference
difference to(Fig.
p-side
results 1.6).
resultsacross
the resulting (Fig.
acrossthe
electric 1.6).
the
field
depletion
Thus,depletion
opposes
theThus, region,
region,
thethe
resulting with
diffusionwith
resulting
electric n-side
n-side
of holes
field at
electricat positive
positive
into
opposes voltage
voltage
the n-region
field opposes relative
the diffusion relative
and toto
the electronsp-side
p-side
of holesinto
diffusion of(Fig.
(Fig.
into the
holes 1.6).
1.6).
thep-region.
into
n-regionthe In n-region
andThus,
electrons
fact,
Thus,and
the
the
theelectrons
into
voltage
resulting the
resulting drop into
p-region.
electric the
across
electric fieldp-region.
In fact,
theopposes
field depletion
opposes the
In thefact,
voltage
region
the the
diffusion drop
voltage
act of
diffusion as across
aholesdrop
barrier
ofholes the
across
intothat
into the depletion
has the
then-region to be
n-region depletion
region act
region
overcome
and
and asforaact
electrons
electrons barrier
as the
holes
into
into toathethat
barrier
diffuse has
p-region.
p-region. that
intotoInthebe
Inhas overcome
to
n-region
fact,
fact, the
thebevoltage
overcome
and for
voltage holes
dropfor
electrons
drop totoholes
across
across diffuse
diffuse
the
thetodepletion
into
diffuse
into the p-
the
depletion into the
n-region
regionn-region
region, and
regionact electrons
and
actasasaaany
blocking electrons
barrier
barrierto
charge diffuse
that
that has
flow to
has into
diffuse
totobe
(current) the into
p-region,
beovercome
overcome the
across thefor p-region,
blocking
forholes
holesThe
barrier. blocking
any
totodiffusecharge
diffusethe
larger any
into
intoflow
charge
the
the
barrier flow
(current) (current)
voltageacross
n-region
n-region and
the and the
across
barrier.
electronsthethe
electrons
smaller toThe
barrier.
to
number larger
diffuse of The
diffuse thelarger
into
into
carrier barrier
the
the
that the voltage
p-region,barrier
p-region,
will the
voltage
tosmaller
blocking
be ableblocking anythecharge
any
overcome the
smaller
charge
thenumber the
flownumber
flow
barrier,
(current)
(current)
of carrierof across
that across
carrier
will the
that
bethe barrier.
barrier.
able
will beto TheThe larger
overcome
able larger
to the
the
overcome
the barrier
barrier
barrier,
and hence the lower the magnitude of diffusion current. We represent this barrier voltage
voltage
the and the
the
barrier, smaller
hence smaller
and the the
the
hence number
lower number
the the lower the
of
ofcarrier
magnitudecarrier that
magnitude
by bending that
of the will
will
diffusion be be able
of diffusion
conduction able
current. toto overcome
overcome
andcurrent.
Wevalence the
represent
We the barrier,
barrier,
bandsrepresent
asthis and
and
theybarrier hence
hence
this the
cross by the
barrier the lower
bending
depletionlower the
by bending the
the
region the
magnitude
magnitude
conductionconduction
and ofof diffusion
diffusion
valence
and bands
valencecurrent.
current.
as bands
they We We
cross
as represent
represent
they the cross this
depletionthis depletion
the barrier
barrier by
region by
(Fig. bending
region bending
1.7).(Fig. the
the
1.7).
(Fig. 5.7).
conduction
conductionand andvalence
valencebands bandsasasthey theycross
crossthe thedepletion
depletionregionregion(Fig.(Fig.1.7).1.7).
E E
EE
Emax Emax n-type n-type
p-type p-type
EE max Y
max Y
n-type
n-type p-type
p-type
YY X X
XX
+ − + −
++ −−
+ +
++− −−
−
Barrier Barrier
+ ++− Barrier
Barrier
−+− −
+ ++− −+− − Energy
EnergyEnergy
Energy
+ ++− −+− −

Fig.Fig.
1.6 Generated
Fig.
Fig.1.6
1.6 1.6 Generated
electric field
electric fieldFig. 1.7 Bending
Fig. 1.7 Bending
ofofof
the energy
of thebands
energy bands
Figure 5.6:Generated
Generatedelectric
Generatedelectricfield
electric field
field FigureFig.
Fig.1.7
1.7
5.7:Bending
Bending
Bending ofthe
the
theenergy
energy
energybands
bands
bands
A free charge
AAfree A charge
free freenow
charge
charge requires
now
now now requires
some
requires
requiressomeextra
some some
extraenergy
extra extra
energy toenergy
energy overcome
toto to overcome
overcome
overcome thethebarrier
the thetobarrier
barrier
barrier tobe able
to be able
beable
able
A
to crossfree
to
totocross charge
thecross
crossthe now
depletion
the requires
depletion
region.
thedepletion
depletionregion.some
A extra
region.
suitable
A
region.AAsuitable energy
suitable
positive
suitablepositiveto overcome
positive
voltage
positivevoltage the
(forward
voltage
voltage(forward barrier
(forward
bias)
(forwardbias) to be able
applied
applied applied
bias)
bias)applied
to cross the depletion region. A suitable positive voltage (forward bias) applied
between the two ends of the pn junction diode can supply free electrons and holes

5 524
5 5
 Electronics
Electronics
Lab, Advanced
Lab, Advanced
Electrical
Electrical
Engineering
Engineering
Lab course
Lab course
II, Spring
II, Spring
2010, Jacobs
2010, Jacobs
University
University
BremenBremen

with the energy required. However, applying a negative voltage (reverse bias) results
in pulling
between
between thetwo
the freetwo
the charges
endsends away
of the
of pnfrom
the pn the
junction junction.
junction
diode
diode
can can
supply
supply
free free
electrons
electrons
and and
holesholes
with with
the energy
the energyrequired.
required.
However,
However,
applying
applying
a negative
a negative
voltage
voltage
(reverse
(reverse
bias)bias)
results
results
in pulling
in pulling
the free
the free
charges
charges
awayaway
fromfrom
the junction.
the junction.
Forward/Reverse Bias Characteristics

Forward/Reverse
If a Forward/Reverse
negative voltage Bias isBias
Characteristics
Characteristics
applied to the pn junction, the diode is reverse biased. In
Ifresponse,
a negative freevoltage
If a negative holes and
voltage electrons
is applied to are
is applied thetopulled
pn pntowards
thejunction, thethe
junction, theend
diode ofreverse
diode
is the crystal
is reverse and
biased. away
biased.
In In
fromresponse,
response, the junction.
free free The
andresult
holesholes and is that
electrons areall
electrons available
pulled
are pulled
towards carriers
towards are end
the end
the attracted
of the theaway
of crystal
crystal
andfrom
and
the junction,
awayaway fromfrom and the
the junction. depletion
the junction.
The The region
result
result is
is that extended.
is that
all available There
all available is
carriersno current
carriers
are attractedflow through
are attracted
awayaway
from
underfrom
the junction,
suchtheconditions.
junction,
and and
the
Wedepletion
the
are depletion
regionregion
here considering is extended.
is extended.
an There
ideal diode. There
is no
In iscurrent
real no
life,current
theflow flow
diode
throughthrough
cannot under
be under
suchsuch
perfect, conditions.
and conditions.
some We are
current We here
are here
(reverse considering
considering
current) doesan flow.
ideal
an ideal
diode.
This diode.
is In real
known In real
as
life, life,
the diode
the diode
cannot
cannot
be perfect,
be perfect,
and and
some some
currentcurrent
(reverse
(reverse
reverse bias applied to the semiconductor diode (Fig. 5.8). If the applied voltage current)
current)
does does
flow. flow.
This This
is known
is known
as reverse
as reverse
bias bias
applied
applied
to thetosemiconductor
the semiconductor diode diode
(Fig.1.8).
(Fig.1.8).

Depletion
Depletion
region
region Depletion
Depletion
region
region

_ _ _ _
+ + + +

Fig. Fig.
1.8 Reverse
1.8 Reverse
bias bias Fig. Fig.
1.9 Forward
1.9 Forward bias bias
Figure 5.8: Generated electric field Figure 5.9: Bending of the energy
If theIf applied
the appliedvoltage
voltage
is positive,
is positive,
the diode
the diode bands
operates
operates
in forward
in forwardbias.bias.
This This
has has
the the
effecteffect
of shrinking
of shrinking the depletion
the depletion region.region.
As theAs applied
the applied voltagevoltage
supplies
supplies
enough
enough
energyenergy
to the
is positive, to
thefree
the free
charge
diode charge
to overcome
operates toinovercome the barrier,
forward the barrier,
bias. carriers
This carriers
has of both
the of both
types
effect oftypes
can cross
can cross
shrinking the
the junction
the junction
into the
into opposite
the opposite endsends of theof crystal.
the crystal.
Now,Now,electrons
electrons
in thein p-type
the p-type
end end
depletion region. As the applied voltage supplies enough energy to the free charge to
are attracted
are attracted to the to positive
the positiveappliedapplied
voltage,
voltage,
whilewhile
holesholes in the in n-type
the n-type
end end
are are
overcome
attracted tothethe
attracted barrier,
to negativecarriers
the negative appliedof both
applied types
voltage.
voltage.canThis
This cross
is isthe
the thejunction
condition ofinto
condition of the
forward opposite
forward
bias bias
ends(Fig.
(Fig. of the
1.9). 1.9).crystal. Now, electrons in the p-type end are attracted to the positive
applied voltage, while holes in the n-type end are attracted to the negative applied
Because
Becauseof this
voltage. Thisofisbehavior,
this behavior,
the conditionan electrical
an electrical
of forward currentcurrent
bias can flow
(Fig.can flow
through
5.9). through
the junction
the junction
in the
in the
forward
forward
direction,
direction,
but not
but innotthein reverse
the reverse direction.
direction.
This Thisis the is basic
the basic
naturenature
of anof an
Because
ordinary of this
ordinary
semiconductorbehavior,
semiconductor andiode.
diode. electrical current can flow through the junction in the
forward direction, but not in the reverse direction. This is the basic nature of an
Diode Diode
Characteristics
Characteristics
ordinary semiconductor diode.
FigureFigure
1.101.10
shows shows
the diode
the diode
I-V characteristics.
I-V characteristics.
Where,Where,
Diode Characteristics
Vf Vf Forward Forward voltageIf If Forward
voltage Forward
current
current
Vr Vr Reverse Reverse
voltage
voltageIr Ir Reverse
Reverse
current
current
When forward-biased,
Cut-in
Vcut-inVcut-in Cut-in
voltage a cut-in voltage
voltage VB VBBreakdown Vcut−in
Breakdown has
Voltage to be overcome for the diode to
Voltage
start conduction. In silicon, this voltage is about 0.7 volts. When reverse-biased, the
IS IS Saturation
Saturation
current
current
current is limited to IS . For higher reverse voltages Vr , the junction breaks down.
Figure 5.10 shows the diode I-V characteristics.

6 25 6
 Electronics Lab, Advanced Electrical Engineering Lab course II, Spring 2010, Jacobs University Bremen

When forward-biased, a cut-in voltage Vcut-in has to be overcome for the diode to
start conduction. In silicon, this voltage is about 0.7 volts. When reverse-biased,
the current is limited to IS. For higher reverse voltages Vr, the junction breaks
down.
If

Vf = Forward voltage
VB Vf
Is If = If Forward current
Vr = Reverse voltage
Vr Vcut-in Ir = Reverse current
Vcut−in = Cut-in voltage
VB = Breakdown Voltage
IS = Saturation current

Ir

Fig. 1.10: I-V Characteristics of a diode

Figure 5.10: I-V Characteristics of a diode
Diode Equation
Diode
The diode equation Equation
gives a reasonably good approximated representation of the
diode I-V characteristics.
The diode equation gives a reasonably good approximated representation of the
diode I-V characteristics.
Forward Bias Condition
In the forward bias condition current through a diode varies exponentially with the
applied voltageForward
and the I-V Bias Condition
relationship is closely approximated by
  V In  the  forward bias condition current through a diode varies exponentially with the
I = IS  exp  − 1
 (1.1)
  n ⋅ VTapplied
  voltage and the I-V relationship is closely approximated by
Where IS is the saturation current, which is constant for a given diode at a given
  !
V
temperature. The voltage nVTthe thermal voltage, given by
is called
I = I VTexp s −1 (5.1)
kT
VT = (1.2)
q
Where Is is the saturation current, which is constant for a given diode at a given
-23
k = Boltzmann’stemperature.
constant = 1.38The
x 10 voltage
joules/Kelvin
VT is called the
thermal voltage, given by
T = the absolute temperature in Kelvin
kT charge = 1.602 x 10-19 As.
q = the magnitude of electronic
At room temperatureVT (300K),
= the value of VT is taken to be 26mV. (5.2)
q
In the diode equation, the constant n varies between 1 and 2, depending on the
material, the temperature and the physical
k = Boltzmann’s structure of the diode.= 1.38 ∗ 10−23 joules/Kelvin
constant
q = the magnitude of electronic charge = 1.602 ∗ 10−19 As
T = the absolute temperature in Kelvin
7
At room temperature (300K), the value of VT is taken to be 26mV .
In the diode equation, the constant n varies between 1 and 2, depending on the
material, the temperature and the physical structure of the diode.
Note that this equation characterizes the basic features of the diode I-V curve, but
leaves out some details like reverse breakdown (the equation says nothing about the
possibility of reverse bias breakdown), junction capacitance...etc. For V ≫ VT in
Eq. (5.1), the exponential relationship can be approximated by
 
V
nVT
I = Is exp (5.3)

26
Reverse Bias Condition
Using Eq. (5.1) we can predict that the diode current is approximated by

I∼
= −Is for V ≪ 0 (5.4)

Where V is negative and a few times larger than VT (26mV ) in magnitude so the
exponential term becomes negligibly small compared to unity.

Breakdown Region
The breakdown region is entered when the magnitude of the reverse voltage ex-
ceeds a threshold value specific to the particular diode and called the breakdown
voltage. As we can see from Fig. 5.10, in the breakdown region the reverse current
increases rapidly. For a general-purpose diode, we should avoid reaching the break-
down region. If the power dissipated exceeds the diode’s power rating, immediate
destruction of the diode can result. While for the general-purpose diode it is very
important to operate below this voltage, special diodes are manufactured to operate
in the breakdown region and are called Zener diodes. The Zener diodes can handle
breakdown without failing completely as in the case of general-purpose diodes.

Zener Diode
The Zener diode is like a general-purpose diodes consisting of a silicon pn junction.
When forward-biased it behaves like general-purpose diodes. In case of reverse-
biased, if the reverse voltage is increased the saturation current remains essentially
constant until the breakdown voltage is reached where the current increases dramat-
Electronics Lab, Advanced Electrical Engineering Lab course II, Spring 2010, Jacobs University Bremen
ically. This breakdown voltage is the Zener voltage for Zener diodes. When reverse

Fig. 1.11 Zener diode

Figure 5.11: Zener diode
Diode Equivalent Circuit
A small signal equivalent model for forward biased diode is shown in Fig.1.12.
voltages greater than the breakdown voltage are applied the voltage drop across the
junction (Zener diode) remains almost constant over a wide range of currents. From
the I-V characteristics in Fig. 5.11 after the breakdown voltage the I-V curve is
almost a straight line providing almost constant voltage as its current changes. The
fact that in the breakdown region the voltage across the diode is almost constant

27
Fig. 1.12 Equivalent model Fig. 1.13 Accurate model

The resistor rd models the change in the diode voltage Vd that occurs when Id
changes.
turns out to be an important application of diodes that is the voltage regulator. Ba-
sically, the function of the regulator is to provide constant output voltage to a load
connected in parallel in spite of the ripples in the supply voltage and the variation
in the load current.

Fig. 1.11
Fig. Zener
1.11 Zener
diodediode
Diode Equivalent Circuit
DiodeDiode
Equivalent
Equivalent
Circuit
Circuit
A small signal equivalent model for forward biased diode is shown in Fig. 5.12.
A small
A small
signalsignal
equivalent
equivalent
modelmodel
for forward
for forward
biased
biased
diodediode
is shown
is shown
in Fig.1.12.
in Fig.1.12.

Fig. 1.12
Fig. Equivalent
1.12 Equivalent
modelmodel Fig. 1.13
Fig. Accurate
1.13 Accurate
modelmodel
Figure 5.12: Equivalent model Figure 5.13: Accurate model

The resistor
The resistor
r models
r models
the change
the change
in theindiode
the diode
voltage
voltage
V that
V occurs
that occurs
when when
I I
The resistor
changes. rdd models
changes.
d d
the change in the diode voltage Vdd that occurs dwhend Id
changes. When differentiating Eq. (5.1) we get
Differentiating
Differentiating
equation
equation
1.1 we1.1
getwe get
Vd Vd
1 dI expVdV/VT I
1 =dI1d d dI=dexp
I
V
expId
T T
Id d
= (5.5)
=
rr d dV == I =sI = = (1.5) (1.5)
rdVddV V V V VT
S S T
d dd d T VV TT T

TheThe capacitor
The capacitor
capacitor CdCisd is Ccalled
d is the
called called
thediffusion
diffusion
the diffusion
capacitance.
capacitance.
capacitance. This capacitive
This capacitive
This capacitive
effect
effecteffect
is is
is present
present
present
when when
the junction
the junction
is forward
is forward
biased.
biased.
It is called
It is called
diffusion
diffusion
capacitance
when the junction is forward biased. It is called diffusion capacitance to account for capacitance
to to
account
account
for thefortime
the delay
time delay
in moving
in moving
charges
charges
across across
the junction
the junction
by diffusion
by diffusion
theprocess.
timeprocess.
delay in
It varies moving
It varies
directly charges
directly
with the across
withmagnitude the
of junction
the magnitude forward by current.
of forward diffusion process. It varies
current.
directly with the magnitude of forward current.
The capacitor Cj is called the junction capacitance. A reverse-biased pn junction
can be compared to a charged capacitor. The p and n regions act as the plates of
the capacitor while the depleted region9as the 9 insulating dielectric. The value of the
capacitance depends on the width of the space charge region. Thus, it depends on
reverse voltage. As the reverse voltage increases, the space charge region becomes
wider, effectively increasing the plate separation and decreasing the capacitance.
For more accurate modeling of the diode, it is necessary to add a series resistance
due to the bulk (p-and n-type semiconductors material of which the diode is made
of) and the metal contacts. In addition, a shunt resistance is added due to parasitic
effects in the material. The shunt resistance of crystalline silicon diodes is typically
very high. The Equivalent circuit of the accurate model is shown in Fig. 5.13.
Where,

V = voltage across the entire real diode in forward bias

I = current through the entire real diode in forward bias
Vd = voltage across the ideal diode (due to the drop across the pn-junction)
Id = current through the ideal diode

28
 Fig. 1.17 Biased clipper Fig. 1.18 positive Clamper

5.1.4 Practical Background

Practical Background
Diode Identification
Diode Identification
The cathode terminal of a diode is identified with a dark line on its package as
Many diodes
indicated in are
Fig.identified
5.14. as 1Nxxxx. The cathode terminal of a diode is
identified with a dark line on its package as indicated in Fig. 1.19.

_
+

Fig. 1.19 Standard diode symbol

Figure 5.14: Standard diode symbol
Safety Precautions
The following
Meter Check is aoflist of some of the special safety precautions that should be
Diode
taken into consideration when working with diodes:
Using the multimeter as an ohmmeter, place the positive lead of the multimeter on
1. Never remove or insert a diode into a circuit with voltage applied.
the anode of the diode and the negative lead of the multimeter on the cathode of the
2.diode.
When testing
Record thearesistance
diode, ensure thatmeasure,
value you the testthevoltage does not
meter should showexceed the
a very low
diode's maximum allowable voltage.
resistance (forward resistance). Be sure to have the multimeter on the most sensitive
3.scale the meter
Ensure will allow.diode
a replacement Theninto
reverse the leads.
a circuit Record
is in the thedirection.
correct resistance value you
measure, the meter should show a very high resistance (reverse resistance).
Two high-value resistance measurements indicate that the diode is open or has a
Meter Check of
high forward Diode Two low-value resistance measurements indicate that the
resistance.
diodethe
Using is shorted or has
multimeter as aanlow reverse resistance.
ohmmeter, place theApositive
normallead
set of
ofmeasurements
the multimeterwill
on
show a high resistance in the reverse direction and a low resistance
the anode of the diode and the negative lead of the multimeter on the cathode of in the forward
direction.
The function ’Diode Test’ of the multimeter tests the semiconductor junction by
sending a current through the junction, 12 then measuring the junction’s voltage drop.
A good silicon junction drops between 0.5V and 0.8V .

Safety Precautions
The following is a list of some of the special safety precautions that should be taken
into consideration when working with diodes:
1. Never remove or insert a diode into a circuit with voltage applied.
2. When testing a diode, ensure that the test voltage does not exceed the diode’s
maximum allowable voltage.
3. Ensure a replacement diode into a circuit is in the correct direction.

5.1.5 Diode Application

A. Rectifier Circuit
A diode rectifies an ac voltage, so that it can be smoothed and converted into a dc
voltage. The basic half wave rectifier is shown in Fig. 5.15. The diode eliminates

29
 the negative
Electronics
Electronics cycles
Lab, Lab,
Advanced of the
Advanced
Electrical input
Electrical voltage.
Engineering
Engineering
Lab courseThe
Lab course capacitor
II, Spring
II, Spring
2010,2010, acts
Jacobs
Jacobsas a Bremen
University smoothing
University Bremen filter so
that the output is nearly a dc voltage. As filtering is not perfect, there will be a
remaining voltage fluctuation known as ripple, on the output voltage.

Fig.Fig.
1.141.14
HalfHalf
wavewave
rectifier
rectifier Fig.Fig.
1.151.15
FullFull
wavewave
rectifier
rectifier
Figure 5.15: Half wave rectifier Figure 5.16: Full wave rectifier

Electronics Lab, AdvancedIn case of

Electrical half wave
Engineering rectifier,
Lab course an2010,
II, Spring approximate expression
Jacobs University Bremen for the peak-to-peak ripple
voltage is given by
B. B.Voltage
Voltage
VpRegulator
RegulatorCircuit
Circuit
Vr = (5.6)
A voltage
A voltage
f CRregulator
Lregulator
is designed
is designed to keep
to keep the the
output
output
voltage
voltage of aof circuit
a circuit
at aat a
constant
constant value,
value,
independent
independent of the
of the
input
input
voltage
voltage
andandalsoalso
independent
independent of the
of the
where
loadload Vpcurrent.
current.is the peak
A Zener
A Zenervalue
diode of
diode the
connectedinputinsinusoidal
connected parallel tovoltage,
in parallel the
to the RisL the
loadload isisthe
the load
simplestresistance
simplest
formform
and
of off such
such is athe afrequency
voltage
voltage of the
regulator
regulator input
circuit asvoltage.
circuit shown
as shown inAFig.
more
in Fig.precise
1.16. calculation of the peak-
1.16.
to-peak ripple voltage is given by
r !
Vp Ri
Vr = 1− 4 (5.7)
f CRL RL
Fig. 1.14 Half wavewhere
rectifier
Ri is the internal Fig. 1.15 Full
resistance wave
of the rectifier
voltage supply. The amount of ripple can
be reduced by a factor of two by using the full wave rectifier shown in Fig. 5.16.
Here, four diodes are connected as a bridge, to invert the negative cycles and make
them positive. See reference [1] for more information on how to derive the ripple
voltage equation. Fig.Fig.
1.161.16
Voltage
Voltage
regulator
regulator
B. Voltage Regulator Circuit
A voltage regulatorIf isIfVoltage
B.the designed
the
voltage
voltage toacross
Regulator
across keep the
Circuit
the the output
loadloadtriestriestovoltage
rise
to rise ofthe
thenthen a the
circuit
Zener
Zener at takes
takesa more morecurrent.
current.
constant value, independent
TheThe increase of
increase the input
in current
in current voltage
through
through and
the thealso
resistor independent
resistorR causes
R causes of
an an the
increase
increase in voltage
in voltage
A voltage
load current. A Zener diodeacross
dropped
dropped regulator
connected
across isindesigned
the the parallel
resistor
resistor
R and Rto
toandkeep
causesthethe
thecauses
load output
isthe voltage
thevoltage
voltagesimplest
across of a circuit
form
acrossthe the
loadload atremain
to a constant
to remain
value,
of such a voltage regulator
at its independent
at correct
its circuit
correct as
value. of the
shown
value.
Similarly, input
in Fig.
Similarly,if theifvoltage
1.16.
the
voltageand
voltage also
across
across independent
the the
loadload of
to the
triestries fall, load
to fall, current.
thenthenthe the
ZenerZener takestakes
lesslesscurrent.
current. TheThe current
current
through
throughAtheZener
the diode
resistor
resistor
R andconnected
R and the the in
voltage paral-
voltage
across
across the the
resistor
resistorbothbothfall.fall.
TheThe voltage
voltage
across lelthe
across tothe
theload
load load
remains is the
remains at itssimplest
at correct form
its correct
value.
value. of such a voltage regulator circuit as
C. C. Clipper
ClipperCircuit
Circuit shown in Fig. 5.17. If the voltage
across the load tries to rise then the
TheseThese circuits
circuits
clipclip
off portions
off portions of signal
of signal
voltages
voltages above
Zener aboveor below
takes ormore
belowcertain
certain
current. limits,
limits,
i.e.in-
The i.e.
the thecircuits
circuits
limitlimit
the the
rangerange of the
of the output
output
signal.
signal.
TheThe level
level
at which
at which the thesignal
signal
is is
crease in current through the resis-
clipped
clipped cancanbe beadjusted
adjusted by adding
by adding a dca bias
dc bias voltage
voltagein series
in series withwiththe the
diodediode
as as
shownshown in Fig.
in Fig.
1.17.1.17. tor R causes an increase in voltage
dropped across the resistor R and
causes the voltage across the load to
Fig. 1.16
Figure Voltage
5.17: Voltageregulator
regulator
remain at its correct value. Simi-

If the voltage across the load tries to rise then the Zener 30 takes more current.
The increase in current through the resistor R causes an increase in voltage
dropped across the resistor R and causes the voltage across 11 11 the load to remain
at its correct value. Similarly, if the voltage across the load tries to fall, then the
Zener takes less current. The current through the resistor R and the voltage
 Electronics Lab, Advanced Electrical Engineering Lab course II, Spring 2010, Jacobs University Bremen

D. Clamper Circuit
There are circuits used to add a dc voltage level to a signal. A positive clamper
circuit (Fig. 1.18) adds positive dc voltage level (the output waveform will be
larly, if the voltage across the load tries to fall, then the Zener takes less current.
identical to that of the input but the lowest peak clamped to zero) while negative
The current through the resistor R and the voltage across the resistor both fall. The
clamper circuit adds negative dc voltage level. A dc bias voltage can be added to
voltage across the load remains at its correct value.
raised or lowered the signal to a reference voltage. The clamper circuits can be
used to restore dc levels in communication circuits that have passed different
C. Clamper
filters. Circuit
There are circuits used to add a dc volt-
age level to a signal. A positive clamper
circuit (Fig. 5.18) adds positive dc voltage
Electronics Lab, Advanced Electrical Engineering Lab course II, Spring 2010, Jacobs University Bremen
level (the output waveform will be identi-
cal to that of the input but the lowest peak
clamped
D. Clamper to zero) while negative clamper
Circuit
circuit adds negative dc voltage level. A
There are circuits used to add a dc voltage level to a signal. A positive clamper
dc bias voltage can be added to raised or
circuit (Fig. 1.18) adds positive dc voltage level (the output waveform will be
lowered
identical thetosignal
that ofto the
a reference
input butvoltage.
the lowest peak clamped to zero) while negative
The clamper
clamper circuits
circuit addscan be used
negative dc to re- level.Figure
voltage 5.18: Positive clamper
A dc bias voltage can be added to
store dc levels
Fig. in communication
1.17 Biased circuits
clipper that have
raised or lowered the signal to a reference voltage. The clamper passed
Fig. different
1.18 positivefilters.
Clamper
circuits can be
used to restore dc levels in communication circuits that have passed different
D.filters.
Clipper Circuit

Practical Background These circuits clip off portions of signal

voltages above or below certain limits, i.e.
Diode Identification the circuits limit the range of the output
Many diodes are identified as 1Nxxxx. signal.
The The levelterminal
cathode at which
of athe signal
diode is is
clipped can be adjusted by adding
identified with a dark line on its package as indicated in Fig. 1.19. a dc bias
voltage in series with the diode as shown in
Fig. 5.19. _
+
Figure 5.19: Biased clipper
Fig. 1.17 Biased clipper Fig. 1.19 Standard
Fig.diode
1.18 positive
symbol Clamper

Safety Precautions
The following
Practical is a list of some of the special safety precautions that should be
Background
taken into consideration when working with diodes:
Diode Identification
1. Never remove or insert a diode into a circuit with voltage applied.
Many diodes are identified as 1Nxxxx. The cathode terminal of a diode is
2. When testing a diode, ensure that the test voltage does not exceed the
identified with a dark line on its package as indicated in Fig. 1.19.
diode's maximum allowable voltage.
3. Ensure a replacement diode into a circuit is in the correct direction.
_
+
Meter Check of Diode
Using the multimeter as an
Fig.ohmmeter, placediode
1.19 Standard the positive
symbollead of the multimeter on
the anode of the diode and the negative lead of the multimeter on the cathode of
Safety Precautions
The following is a list of some of the special12safety precautions that should be
taken into consideration when working with diodes:
31
1. Never remove or insert a diode into a circuit with voltage applied.
2. When testing a diode, ensure that the test voltage does not exceed the
diode's maximum allowable voltage.
5.1.6 References
1. Adel S. Sedra, Kennth C. Smith, Microelectronic Circuits, Saunders College
Publishing, 3rd ed., ISBN: 0-03-051648-X, 1991.

2. David J. Comer, Donald T. Comer, Fundamentals of Electronic Circuit Design,

John Wiley & Sons Canada, Ltd.; ISBN: 0471410160,2002

32
5.2 Prelab Diodes
5.2.1 Problem 1 : Current/voltage characteristic of a diode
Implement the following circuit using LTSpice:

R
1K00

Vdc 1N4001

Perform a DC sweep analysis:

1. Plot the diode characteristic If = f (Vf ).

2. Plot the diode characteristic log(If ) = f (Vf ).

Hint: Just format the y scale in the LTSpice plot.

3. Extract the values of ideality or diode factor, n, and the saturation current Is
from the graph. See Eq. (5.3). The voltage VT can be assumed to be 26mV .

5.2.2 Problem 2 : Halfwave rectifier

Implement the following circuit using LTSpice:

I_D D1

1N4001

Vin =20Vpp
R_L
Sine, 100Hz ~ C1 47uF U_L
2K20
Rser=50Ohm

Perform a transient analysis (4 cycles of the sinusoidal input) for all following cases.
Use the following parameters: .tran 0 1 960m .05m

1. Simulate the circuit without C1. Plot V L, Vin and I D. Measure the peak
voltage at R L and the peak current I D.
Hint: Use the cursors from the LTSpice display.

2. Simulate the circuit with C1 connected. Plot V L, Vin and I D. Measure the
peak voltage at R L, the peak current I D, and the ripple of the voltage VL
at the load resistor. Use the formula from the handout to calculate the ripple
value. Compare!

33
5.2.3 Problem 3 : Fullwave rectifier
Implement the following circuit using LTSpice:
I_D

Vin =20Vpp
DF02M-E
Sine, 100Hz ~ Rectifier
Rser=50Ohm

R_L
C1 47uF U_L
2K20

Hint : In real life the DF02M rectifier is an integrated element. In LTSpice it is not
available. The additional library includes a single diode from the rectifier. Assemble
the full rectifier using four single diodes.

Perform a transient analysis (4 cycles of the sinusoidal input) for all following cases.
Use the following parameters: .tran 0 1 960m .05m

1. Simulate the circuit without C1. Plot V L, Vin and I D. Measure the peak
voltage at R L and the peak current I D.
Hint: Use the cursors from the LTSpice display.

2. Simulate the circuit with C1 connected. Plot V L, Vin and I D. Measure the
peak voltage at R L, the peak current I D, and the ripple of the voltage VL
at the load resistor. Use the formula from the handout to calculate the ripple
value. Compare!

5.2.4 Problem 4 : Rectifier

Explain the general function of the rectifier circuit with capacitor. Use simple prin-
ciple circuit diagrams and the hard copies from the simulation to prove your state-
ments!

1. What are the maximum peak voltages without a capacitor at the load for each
rectifier (in our case!)? Why are these values different from the input sine
amplitude? Why is there a difference between half- and full-wave rectifier?

2. Explain the differences of the current I D for all cases. What is the consequence
for the used diode in a rectifier circuit?

3. What is the influence of the ratio C ∗ RL to the quality of the output DC?

34
5.2.5 Problem 5 : Zener Diode
Implement the following circuit using LTSpice:

R1
500

Vin = 10Vpp
50Hz ~
BZX55C5V6 RL 500

Vin = 20V

1. Perform a transient analysis (5 cycles of the sinusoidal input). Plot the input
voltage (DC + AC voltage) and the output voltage across the load resistor
RL.

2. Explain the operation of the circuit.

35
5.3 Execution Diodes
5.3.1 Problem 1 : Diode Switching Characteristic
The goal of the experiment is to investigate the reverse/forward and forward/reverse
transition behavior of a rectifier and a signal diode. Assemble the following circuit
on the breadboard:
R1
Uout
1K00

Vin =5Vpp
square, 10KHz ~ 1N4001

There is a delay time during reverse/forward transition and a storage time after
forward/reverse transition.

Vin

Uout td ts

1. Measure td and ts for the 1N4001 rectifier diode.

2. Replace the 1N4001 rectifier diode by a 1N4148 signal diode. Repeat the td
and ts measurement.

Hint: Since we want to know the behavior and not the accurate
timing use 50% levels for all reference points!

36
5.3.2 Problem 2 : Rectifier
1. Half-wave rectifier.
The following half rectifier should be realized:

I_D D1

1N4001

Vin =20Vpp
R_L
Sine, 100Hz ~ C1 47uF U_L
2K20
Rser=50Ohm

(a) Remove C1 and display and measure the peak voltage of Vin and VL .
Take a hard copy of the signals together with the measurements.
(b) Insert C1 and display and measure the peak voltage of Vin and VL . Take
a hard copy of the signals together with the measurements.
(c) Zoom into the ripple voltage on top of VL . Measure the peak to peak
voltage of the ripple. Take a hard copy of the signal together with the
measurements.
Hint: Use AC-Coupling in the channel menu of the oscilloscope

2. Full-wave rectifier.
The following full wave rectifier should be realized:

I_D

Vin =20Vpp
DF02M-E
Sine, 100Hz ~ Rectifier
Rser=50Ohm

R_L
C1 47uF U_L
2K20

(a) Remove C1 and display and measure the peak voltage of VL . Take a hard
copy of the signals together with the measurements.
(b) Insert C1 and display and measure the peak voltage of VL . Take a hard
copy of the signal together with the measurements.
(c) Zoom into the ripple voltage on top of VL . Measure the peak to peak
voltage of the ripple. Take a hard copy of the signal together with the
measurements.

Hint: Be careful with the oscilloscope when measuring the input

and output signals of the full wave rectifier circuit at the same
time. The different channels of the oscilloscope are NOT floating.
Contact a TA if this hint is unclear to you.

37
5.3.3 Problem 3 : Zener diode
Implement the following circuit:

Vin =20Vpp DF02M-E R1

sine, 100Hz ~ Rectifier 100R

C1 BZX
100uF RL 39K0
85C5V6

Measure DC and ripple voltage at C1 , the output DC voltage and the ripple across
the load resistor RL. Take a hard copies of the signals together with the measure-
ments.

5.3.4 Problem 4 : Voltage Multiplier

Assemble the following circuit on the breadboard:

C1 A C2 B

1uF 1uF
Uin=20Vpp
Sine, 10KHz ~ D1 D2 D3 D4 4 x 1N4148

C3 C4
Uout
1uF C 1uF
C5 R1
1uF 100K

1. Use the oscilloscope to measure...

... the voltage at ’A’ and ’C’. Take a hardcopy with both signals together with
the measurements.
... the voltage at ’B’ and ’Uout ’. Take a hardcopy with both signals together
with the measurements.

2. Measure the ripple voltage at ’Uout ’. Take a hardcopy of the signal together
with the measurement.

3. Measure and record the voltages at ’C’ and ’Uout ’ using a multimeter.

38
5.4 Evaluation
5.4.1 Problem 1 : Diode Switching Characteristic
1. Compare the two storage times. What is the reason why the diodes needs that
long time to switch off?

2. What are the consequences for using these diodes in different applications?
Think of the AM demodulation experiment when using several 100KHZ!

5.4.2 Problem 2 : Rectifier

1. Draw a schematic diagram showing the building blocks of a DC power supply
and explain the needs of each building block.

2. Compare the measured values of the peak-to-peak ripple voltages with the
prelab values from simulation and calculation. Discuss the differences.

5.4.3 Problem 3 : Zener diode

1. Calculate the approximate current through the Z-diode!

5.4.4 Problem 4 : Voltage Multiplier

1. From which circuits in the Diode Application part of the handout this circuit
is composed?

2. Explain the function.

3. What is the multiplication factor between input amplitude and output voltage?
Compare the measured to the ideal one. Why is there a difference?

4. For which maximum voltage each element has to be selected?

5. What happens to Uout if the frequency of the input voltage is reduced to 100 Hz
(Voltage & ripple!)? Explain in words!!! Show a prove of your statement using
PSpice!

39
6. Experiment 3 :
Bipolar Junction Transistor (BJT)
6.1 Introduction to the Experiment
6.1.1 Objectives of the Experiment
The goal of the experiment is to become familiar with BJTs. The handout intro-
duces the characteristics and behavior of BJTs. During the experiment, the output
characteristics of a common emitter based BJT circuit will be determined. The
transistor will be used as an amplifier. Also, the voltage gain (AV ), frequency re-
sponse, phase relationship phase relationship between the input voltage and the
output voltage of a common emitter amplifier circuit will be studied.

6.1.2 Introduction
A BJT is a semiconductor component with three connections. It is used in both
discrete and integrated circuits. The main applications are analog circuits, for ex-
ample amplifiers, especially high-speed amplifiers. There are three modes of BJT
operation: active mode (amplifier mode), cut-off mode and saturation mode. To use
a BJT as an amplifier, it must operate in active mode. In a digital circuit element,
the BJT operates in cut-off and saturation mode.

6.1.3 Theoretical Background

Device structure of bipolar junction transistors
Each BJT consist of two anti serial connected diode. The BJT can be either imple-
mented as a NPN or a PNP transistor. In both cases, the center region forms the
base (B) of the transistor, while the external regions form the collector (C) and the
emitter (E). External wire connections to the p and n regions (transistor terminals)
are made through metal (e.g. Aluminum) contacts. A cross section of the two types
of BJTs consisting of a emitter-base
Electronics Lab, Advanced junction
Electrical Engineering Lab and2010,
course II, Spring a collector-base
Jacobs University Bremenjunction is shown

in Fig. 6.1.

Emitter Collector Emitter Collector

(E) (C) (E) (C)

n p n p n p

Collector-base Emitter-base
Emitter-base Base Base Collector-base
junction junction
junction (B) (B) junction

Fig.6.1:
Figure 2.1: NPN
npn and pnpPNP
and BJTs BJTs
structures
structures

Circuit Configurations
40

Figure 2.2 shows the symbol for the npn transistor whereas the pnp symbol is
shown in figure 2.3.The emitter of the BJT is always marked by an arrow, which
indicates whether the transistor is a npn or a pnp transistor.
NPN or PNP transistors are called bipolar transistors because both types of carriers
(electrons and holes) contribute to the overall current. In the case of a field effect
transistor either the electronics or the holes determine the current flow. Therefore
a field effect transistor is a unipolar device. The current and voltage amplification
of a BJT is controlled by the geometry of the device (for example width of the
base region) and the doping concentrations in the individual regions of the device.
In order to achieve a high current amplification the doping concentration in the
emitterElectronics
regionLab,
is typically higher
Advanced Electrical thanLab
Engineering that ofII,the
course base
Spring region.
2010, Jacobs TheBremen
University base is a lightly
doped very thin region between the emitter and the collector and it controls the
flow ofcondition
charge carriers
(forward(electrons
or reverse)orofholes) each from
of thethe BJTemitter to collector
junctions, differentregion.
modes of
operation of the BJT are obtained. The three modes are defined as follows:
Circuit Configurations
Active: Emitter junction is forward biased, collector junction is reverse biased.
Figure 6.2 andoperates
The BJT Fig. 6.3 in the active
show mode and
the symbols the BJT
for NPN can
and PNPbe used as an amplifier.
transistor. The emitter
of the BJT is marked with an arrow, which indicates whether it is a NPNIforthe
Saturation: Both the emitter and collector junctions are forward biased. BJT
a PNP
is used
transistor. as a switch, the saturation mode corresponds to the on state of the BJT.
Cut-off: Both the emitter and collector junction are reverse biased. If the BJT is
C
used as a switch, the cut-off mode corresponds to the off state ofCthe BJT.
Inverted mode:
B
A fourth mode exists under which theB emitter base is reverse
biased and the base collector junction is forward biased. Under these conditions,
the BJT could be used as voltage or current amplifier. However, the amplification
E E
is small in comparison to the active mode so that this mode is typically not used
for applications. The difference in the amplification can be explained by the
Figure 6.2:
different npn
doping BJT symbol
profiles Figure
in the individual regions of the6.3: pnp BJT symbol
transistor.
The correct biasing of a BJT is achieved by using a suitable biasing circuit. The
Therebiasing
are three basic
circuit ways
allows in which
defining a BJT can
the operating be configured.
conditions In each case, one
of a transistor.
terminal is common to both the input and output circuit (Fig. 6.4).

Output Input Output Output

Input Input

Common Emitter Common Base Common collector

FigureFig.
6.4:2.4:
BJT circuit
BJT circuitconfigurations
configurations

ˆ The common emitter configuration is used for voltage and current amplifi-
cation and is the most common configuration for transistor amplifiers.
Currents in Transistor
ˆ The common collector configuration often called an emitter follower since
Now, the behavior of a npn BJT operating in active mode will be discussed. The
its output
BJT is said is
to taken from
be in the the mode
active emitterof resistor.
operation It is useful
under as an impedance
the conditions that the
base-emitter voltage (VBE) is positive (forward biased) and thethan
matching device since its input impedance is much higher baseits output
collector
impedance.
voltage (VBC) is negative (reverse biased). There will be internal current flow in
the device due to both the emitter-base and the base-collector junctions. The
ˆ electron
The common base
and hole configuration
currents is used regions
in the individual for highoffrequency applications
the device are shown be-in
cause 2.5.
figure the base separates the input and output, minimizing oscillations at high
frequency.first
Consider It the
has base-emitter
a high voltage gain, relatively
junction. Since it islow inputbiased,
forward impedance and high
electrons will
output
be impedance
injected from the compared to theincommon
emitter terminal collector.
the collector, and holes are injected in the
base region via the base terminal. The number of injected electrons is much
higher than the number of injected holes.
41 The most important reason for this is
that the emitter is much more heavily doped than the base (There are more free
electrons in the emitter than free holes in the base).
Biasing of Bipolar Junction transistors
In most of the cases, the BJT is used as an amplifier or switch. In order to perform
these functions, the transistor must be correctly biased. Depending on the bias
condition (forward or reverse) of each of the BJT junctions, different modes of
operation of the BJT are obtained. The three modes are defined as follows:
ˆ Active: Emitter junction is forward biased, collector junction is reverse bi-
ased. The BJT operates in the active mode and the BJT can be used as an
amplifier.
ˆ Saturation: Both the emitter and collector junctions are forward biased. If
the BJT is used as a switch, the saturation mode corresponds to the on state
of the BJT.
ˆ Cut-off: Both the emitter and collector junction are reverse biased. If the
BJT is used as a switch, the cut-off mode corresponds to the off state of the
BJT.
ˆ Inverted mode: A fourth mode exists under which the emitter base is re-
verse biased and the base collector junction is forward biased. Under these
conditions, the BJT could be used as voltage or current amplifier. However,
the amplification is small in comparison to the active mode so that this mode
is typically not used for applications. The difference in the amplification can
be explained by the different doping profiles in the individual regions of the
transistor.
The correct biasing of a BJT is achieved by using a suitable biasing circuit. The
biasing circuit allows defining the operating conditions of a transistor.

Currents in Transistor
The BJT is said to be in the active mode of operation under the conditions that
the base-emitter voltage (VBE ) is positive (forward biased) and the base collector
voltage (VBC ) is negative (reverse biased). There will be internal current flow in the
device due to both the emitter-base and the base-collector junctions. The electron
and hole currents in the individual regions of the device are shown in Fig. 6.5.

Injected Injected Diffusing Recombined Collected

Electrons Holes Electrons Electrons Electrons

n+ p n
IE IC IC
IE { IB
}

Emitter-Base IB Collector-Base
Junction Junction

Figure 6.5: BJT circuit configurations

42
Consider first the base-emitter junction. Since it is forward biased, electrons will
be injected from the emitter terminal in the collector, and holes are injected in the
base region via the base terminal. The number of injected electrons is much higher
than the number of injected holes. The most important reason for this is that the
emitter is much more heavily doped than the base (There are more free electrons
in the emitter than free holes in the base). Electrons injected via the emitter will
recombine with holes injected via the base at the interface between the emitter and
base regions. However, not all electrons will find a recombination partner in the
base. Furthermore, the base region of a BJT is very thin (100nm-3000nm), so that
most of the electrons will reach the base-collector depletion region. Since most of
the electrons manage to reach the collector, the recombination current in the base
is small in comparison to the electrons flowing from the emitter to the collector.
There will also be current flowing due to the reverse biased base-collector depletion
region. However, this current (the reverse saturation current) is small compared to
the currents discussed above and will be ignored.
There are three external currents in a transistor: emitter current IE , base current
IB , and collector current IC , shown in Fig. 6.6 for NPN transistor. From our pre-
vious discussion, the emitter current is the sum of the
electrons and the hole current in the emitter region. C
IC
The same holds true for the base and the collector cur-
rent. The base current consists of two components, the B
holes that recombine with the electrons in the base and
IB
the holes that reach the emitter region of the transis- IE
tor. The reverse current of the base collector junction E
is small in comparison to the forward current flowing
in the base-emitter junction so that this current com- Figure 6.6: Current flow
ponent is ignored in Fig. 6.5. Finally, the collector current is mainly determined by
the electrons that reached the collector.
The three currents are related by the following equation:

IE = IC + IB (6.1)

As the base current is small compared to the emitter current IE and the collector
current IC ,it can be safely assumed that IB ≪ IC so that

IC ≈ IE (6.2)

One of the important parameters to evaluate the transistor performance is the cur-
rent gains α and β.
The current gain α corresponds to the common base current gain. The gain is
calculated by
IC
α= ≤1 (6.3)
IE
The current gain βs corresponds to the common emitter current gain. The gain is
calculated by
IC α
β= = (6.4)
IB 1−α

43
The transistor performance is typically described using three graphs. The input
characteristic curve, a transfer characteristic curve and an output characteristic
curve. All necessary information can be extracted from these curves. The most
useful for amplifier design is the output characteristics curve.
Typical output characteristics for a common-emitter BJT are shown in Fig. 2.7.
Characteristic Curves
The vertical axis shows the collector current (IC), the horizontal axis shows the
collector-emitter
The transistor bias (VCE). The
performance is base current
typically (IB) has using
described been varied as a parameter.
three graphs. The input
Some of the important characteristics that can be noted from Fig. 2.7
characteristic curve, a transfer characteristic curve and an output characteristicare:
1.curve.
For aAll
givennecessary information
base current, can be extracted
the collector-emitter from
voltage these
(VCE ) hascurves. Theon
little effect most
the collector
useful current
for amplifier (IC) as
design it rises
is the smoothly
output with it. curve.
characteristics
Typical output characteristics for a common-emitter
2. Collector current (IC) changes appreciably only with BJTthearechange
shown in in Fig.
base6.7.
The vertical
current (IB).axis shows the collector current (IC ), the horizontal axis shows the

Fig.2.7: Output curves of the BJT

Figure 6.7: Output curves of the BJT

collector-emitter bias (VCE ). The base 7current (IB ) has been varied as a parameter.
Some of the important characteristics that can be noted from Fig. 6.7 are:
1. For a given base current, the collector-emitter voltage (VCE ) has little effect
on the collector current (IC ) as it rises smoothly with it.

2. Collector current (IC ) changes appreciably only with the change in base current
(IB ).

Circuit Analysis
The analysis of the BJT circuits is a systematic process. Initially, the operating
point of a transistor circuit is determined then the small signal BJT model param-
eters are calculated. Finally, the dc sources are eliminated, the BJT is replaced
with an equivalent circuit model and the resulting circuit is analyzed to determine
the voltage amplification (AV ), current amplification (Ai ), Input impedance (Zi ),
Output Impedance (Zo ) and the phase relation between the input voltage (Vi ) and
the output voltage (Vo ).

DC Analysis
The DC analysis is done to determine the mode of operation of the BJT and to
determine the voltages at all nodes and currents in all branches. The operating
point of a transistor circuit can be determined by mathematical or graphical (using
transistor characteristic curves) means. Here we will describe only the mathematical
solution.

44
 VCC VCC

RB1 RC RC

R th
V th

RB2 RE RE

Figure 6.8: Biasing circuit

We will use the most commonly applied biasing circuit to operate the BJT as an
amplifier (Fig. 6.8). A single power supply is used and the voltage divider network
consisting of RB1 and RB2 is used to adjust the base voltage. Using the Thévenin
equivalent, the voltage divider network is replaced by Vth and Rth where,
RB2 RB1 RB2
Vth = VCC and Rth =
RB1 + RB2 RB1 + RB2

RC is used to adjust the collector voltage. Finally, RE is used to stabilize the dc

biasing point (operating point).
The dc analysis of the circuit is simple by applying two KVL’s at the input and the
output loop.

Vth = IB Rth + VBE + IE RE = IB (Rth + (β + 1)RE ) + VBE (6.5)

 
RE
VCC = IC RC + VCE + IE RE = IC RC + + VCE (6.6)
α

If the BJT is in the active mode the following typical values can be observed:

VBE ≈ 0.7V and IC ≈ βIB

. The conditions for saturation mode of operation are

VBE = VBESAT = 0.8V and VCE = VCESAT = 0.1 − 0.3V and IC > βIB

.
Note: It is a good idea to set the bias for a single stage amplifier to half the
supply voltage, as this allows maximum output voltage swing in both directions of
an output waveform. For maximum symmetrical swing, it is clear from the figures
that VCEQ should be VCEQ ≈ VCC /2.

AC Analysis
The aim of the ac analysis is to determine the voltage amplification (AV ), current
amplification (Ai ), input impedance (Zi ), output Impedance (Zo ) and the phase re-
lation between the input voltage (Vi ) and the output voltage (Vo ). After performing
the dc analysis, we will now calculate the small signal parameters depending on the

45
model being used, draw the small signal equivalent circuit and then perform the
ac analysis. The analysis is done assuming that the signal frequency is sufficiently
high. Subsequently it can be assumed that all the coupling capacitors (C1 and C2 )
and the bypass capacitor (CE ) act as perfect short circuits. Such a frequency is
said to be in the midband of the amplifier. The hybrid-π model Fig. 6.9 and the
T-model Fig. 6.10 can be used for the ac analysis. Those models are valid only for
small signals.

ib ic ib ic
B C B C
+ +
v be rπ gmvbe v be rπ β ib
- -

ie ie
E E

Figure 6.9: The hybrid-π model

Where, Transconductance
IC kT
gm = with VT =
VT q
Common emitter input resistance
β
rπ =
gm
Common base input resistance
α
re =
gm

C C
ic ic

gmvbe α ie
ib ib
B B
+ +
v be re v be re
- -

ie ie
E E

Figure 6.10: The T-model

46
Example: A common emitter single stage BJT amplifier is shown in Fig. 6.11. In
the following we will use the hybrid-π model to determine the voltage amplification
(AV ), current amplification (Ai ), input impedance (Zi ), output Impedance (Zo ) and
the phase relation between the input voltage (Vi ) and the output voltage across the
load resistor RL .

RB1 RC
C2
C1
VCC

Vout
+
~ Vin RB2 RE CE RL

Figure 6.11: Common emitter single stage BJT amplifier

Redraw the circuit after replacing the BJT with its hybrid-π model as shown in
Fig. 6.12. Since,
vo
vo = −gm vbe (RC ||RL ) and vin = vbe =⇒ Av = = −gm (RC ||RL )
vi

Since,

RC vbe io RC (RB ||rπ )

io = −gm vbe and iin = =⇒ Ai = = −gm
RC + RL RB ||rπ iin RC + RL

For the input and output impedance

Zin = (RB ||rπ ) and Zo = RC

The negative sign in the voltage gain expression means that vin and vo are ∠ 180◦
out of phase.

iin iout
+ +
+ gmvbe
RB v be rπ RC RL
Vin - Vout
Zin Zout
- -

Figure 6.12: The hybrid-π model

47
 Electronics Lab, Advanced Electrical Engineering Lab course II, Spring 2010, Jacobs University Bremen

Frequency Response
Frequency Response

The
Thefrequency
frequencyresponse
responseofofthe
theamplifier
amplifiercircuits
circuits can
can be
be divided to three
divided to three regions
regions
(Fig. 6.13): low
(Fig.2.13): low frequency,
frequency,midband andand
midband highhigh
frequency.
frequency.

Low Midband High

Av frequency frequency frequency

-3dB

ωC1 ωC2 ω

Fig. 2.13:
Figure 6.13: Frequency response
Frequency response

Finite values of C1, C2 and CE cause the amplifier gain to drop for low
Finite values ofThe
frequencies. C1 , amplifier
C2 and CEgaincause the amplifier
decreases gain frequencies
for high to drop for low
as frequencies.
well due to a
The amplifier
physical gain decreases
phenomena for high
(Miller frequencies
effect) that isas well due to aas
modelled physical phenomena
transistor internal
(Miller effect) that is modeled as transistor internal capacitances. There
capacitances. There are designs that can remove the low-frequency drop-off and are designs
that
alsocan remove
to push thethe low-frequency
drop-off drop-off and
at high frequencies also to
further push the drop-off at high
out.
frequencies further out.

Practical
6.1.4 Background
Practical Background
BJT Identification
BJT Identification
Transistors can be identified from the code printed directly on the case of the tran-
Transistors can be identified from the code printed directly on the case of the
sistor. The first number indicates the number of junctions. The letter ”N” following
transistor. The first number indicates the number of junctions. The letter "N"
the first number tells us that the component is a semiconductor. And, the 2- or
following the first number tells us that the component is a semiconductor. And, the
3-digit number following the N is the manufacturer’s identification number. If a
2- or 3-digit number following the N is the manufacturer's identification number. If
letter follows
a letter the last
follows the number, it indicates
last number, a later, improved
it indicates version of version
a later, improved the device.
of the
device.
Safety and Precautions

Safety and
Transistors Precautions
are sensitive to be damaged by electrical overloads, heat, humidity, and
radiation. Damage of this nature often occurs by applying the incorrect polarity
Transistors are sensitive to be damaged by electrical overloads, heat, humidity,
voltage to the collector circuit or excessive voltage to the input circuit. One of the
and radiation. Damage of this nature often occurs by applying the incorrect
most frequent
polarity causes
voltage of damage
to the collectortocircuit
a transistor is the electrostatic
or excessive voltage to discharge
the input from
circuit.
the human body when the device is handled.

4812
Coupling and Bypass Capacitors
For the ac operation of the common-emitter BJT amplifier circuit as shown in
Fig. 6.11, three capacitors C1 , C2 and CE are connected to the base, collector and
emitter terminals, respectively. These capacitors are used to connect the BJT ter-
minals to the input signal, the load resistance or the ground. C1 and C2 are used
to couple the input signal and the load to the BJT (ac coupling). AC coupling does
not affect the biasing of the BJT. CE is used to short circuit the emitter to ground
at signal frequencies. Thus, the signal current in the emitter flows through C2 to
ground, thus bypassing the resistance RE .

49
6.2 Prelab BJT
6.2.1 Problem 1 : Biasing of Bipolar Junction Transistors
Analyze the following common emitter circuit:

R1 RC
V_C
22K0 1K00

Q1 V_CE Vcc
20V

R2 RE
V_B V_E
10K0 470R

β = 150 and VBE = 0.7 V

1. (a) Calculate VB , VE , VCE , and VC .
(b) Calculate IB , IE , and IC .
Hint: You may use LTSpice to check the results!!

6.2.2 Problem 2 : Constant Current Source

1. Given is following constant current circuit:

RL
R1 0 to ?? Ohm

I = 4mA

Q2 Vcc
2N2222 9V

1N750A R2

VBE = 0.7V
2. Find the values for R1 and R2 to get a constant current of IC ≈ 4mA.
Hint: The 1N750A diode is a Zener diode! See data sheet for elec-
trical Properties
3. What is the maximum value for RL to still get IC ≈ 4mA?
4. Implement the circuit in LTSpice and verify your calculations! Use the .step
command to vary RL .
5. Explain the function principle of the circuit!

50
6.2.3 Problem 3 : Amplifier circuit
1. Use ’LTSpice’ to implement the following circuit:

R2 R4
22K0 1K00 C2
1u
C1 Vo
1u
Vi Q2 Vcc
2N2222 20V
R1
Rg 1K00 RL
50R 1K00
Vs
Rt R3 R5 + C3
Sine 1KHz ~ 50R 10K0 470R 100u
50mV Ampl.

2. Determine the DC operation point values for VB , VBE , VC , VCE , VE , IC and

IB .

3. Perform a transient analysis for about 2 cycles of a sinusoidal input signal.

Use VS = 50 mV input amplitude and f = 1 KHz. Display Vi , VB , VBE , and
the voltage across the load resistance Vo . Determine the voltage gain Vo /Vi .

4. Determine the quality of the amplified signal at Vo . Use the .step command
to vary the amplitude VS by 50 mV, 100 mV, and 200 mV. Use a FFT or
determine the harmonic distortion to give a statement.
Hint: The FFT plot is available from the ’VIEW’ menu if the plot window
is selected. The harmonic distortion is calculated using the .four command
of LTSpice. Use the LTSpice help! There is an example among the LTSpice
examples (File Menu - Open Examples..!) called ’audioamp.asc’.

5. Carry out an AC analysis. Set the AC amplitude to 50 mV. Vary the frequency
from 100 Hz to 10 MHz with 10 points per decade and display the voltage across
Vo .

6. Use the LTSpice ’.MEASURE’ command (see help file and example ’Mea-
sureBW.asc’) to determine the lower and upper −3 dB frequencies and the
bandwidth.

51
 NPN switching transistors 2N2222; 2N2222A

FEATURES PINNING
6.3 Execution Bipolar Junction Transistor (BJT)
• High current (max. 800 mA) PIN DESCRIPTION
• Low voltage
6.3.1 Problem 1
: Determine Type and 1Pin Assignment
(max. 40 V). emitter of
a Bipolar Transistors 2 base
APPLICATIONS 3 collector, connected to case
The following
• Linear procedure
amplification will help to determine the type of bipolar junction transistor
and switching.
and to identify the three terminals of the BJT. Usually the same procedure is used
toDESCRIPTION
identify a BJT if the data sheet is not available orhandbook, halfpage 3
1
to test a BJT while troubleshooting a printed circuit 2
NPN switching transistor in a TO-18 metal package.
board. Assign pin numbers
PNP complement: 2N2907A. to the BJT terminals as 2
shown in the drawing below. This is the bottom 3
MAM264
view of the transistor! 1

1. First find the base terminal. Fig.1 Simplified outline (TO-18) and symbol.
Set the multimeter to diode testing function. Measure and record the values
between every combination of two terminals. Use the following table:
QUICK REFERENCE DATA

SYMBOL
Multimeter Leads
PARAMETER
Diode Check value
CONDITIONS MIN. MAX. UNIT
connected to BJT (reading or .0L)
VCBO collector-base voltage open emitter
+ Terminal Gnd Terminal —
2N2222 − 60 V
1 2
2N2222A 2 1 − 75 V
VCEO collector-emitter 1voltage open3base
2N2222 3 1 − 30 V
2N2222A 2 3 − 40 V
IC collector current 3(DC) 2 − 800 mA
Ptot total power dissipation Tamb ≤ 25 °C − 500 mW
hFE
Find the two terminals that Igive
DC current gain
overload ’OL’ with both polarities of the−
C = 10 mA; VCE = 10 V 75
fT
multimeter applied. The
transition frequency
remaining terminal is the base.
IC = 20 mA; VCE = 20 V; f = 100 MHz
Record the base
terminal2N2222
number into the table behind step 3. 250 − MHz
2. Next is to2N2222A
determine the type of the transistor. 300 − MHz
toff Connectturn-off
thetime
common lead ofICon
the= 150 mA; IBon = 15
multimeter to mA;
the IBoff
base= −15 mA
terminal −and the250 ns
positive lead to each one of the other two terminals one by one. Reading
should be either ’OL’ or a diode forward voltage drop for both cases. In case
of ’OL’ the transistor is ’NPN’. Otherwise it is a ’PNP’ type. Record the type
into the table behind step 3.
3. Finally determine the emitter and collector terminals.
Use the previously recorded taken table above. The lower of the two measured
values between BE and CE indicates the base collector junction. The other
value is the base emitter junction. Enter the numbers of the connections in
the following table.

Transistor Type
1997 May 29 Base Terminal 2
Emitter Terminal
Collector Terminal

52
6.3.2 Problem 2 : Operating point of BJTs
The purpose of this problem is to check that the BJT is correctly biased to work in
the active mode of operation.

1. This is the circuit for the following experiments. For the moment assemble
only the components inside the dashed area.

R2 R4
22K0 1K00
C2
1u
Vc
C1 Vo
1u
Vb Q2 Vcc
Vi
2N2222 20V
R1 Ve RL
1K00 1K00

R3 R5 + C3
Vs 10K0 470R 100u
Rt
Sine 1KHz ~ 50R
50mV Ampl.

2. Switch on the power supply. Use a multimeter to measure and record the
voltages VCC , Vb , VBE , Vc , VCE , and Ve .

6.3.3 Problem 3 : Common emitter circuit

The purpose of this problem is to demonstrate the BJT amplification of small signals
when it is correctly biased to work in the active mode of operation.

1. Assemble the remaining parts from the circuit above. Connect the oscilloscope
to Vi and Vo . Set the signal generator to VS = 50 mVPP and f = 1 KHz.

2. Measure f , Vi , and Vo . Use the measure function and take a hardcopy! Now
get the FFT of Vo . Use 10 kS/s sampling rate. Measure the magnitude of the
first and maybe second peak (cursors!). Take a hardcopy.
Note: To avoid trigger problems use the ’SYNC’ of the function generator
and external triggering at the oscilloscope.

3. Repeat the previous two measurements with VS = 100 mVPP , and VS =

200 mVPP .

53
6.3.4 Problem 4 : Bandwidth of amplifier circuit
The purpose of this problem is to determine the bandwidth of the BJT amplifier
circuit and to observe how the voltage gain of a BJT is affected with changing the
frequency of the input signal.

1. Set VS = 50 mVPP . Enable the sweep mode of the function generator with the
following settings:

1: START F : 100 Hz
2: STOP F : 1 MHz
3: SWP TIME : 500 ms
4: SWP MODE : logarithmic

Note: Use the ’SYNC’ output of the generator as trigger source for the oscil-
loscope.

2. Adjust the oscilloscope to observe the full sweep of the output signal. Take a
hardcopy.

3. Disable the sweep mode of the function generator. Without changing the
amplitude of VS , manually change the frequency of the function generator to
obtain the lower and upper −3 dB cut-off frequencies.

54
6.4 Evaluation
6.4.1 Problem 1 : Determine Type and Pin Assignment of
a Bipolar Transistors
1. In Problem 6.4.1.(1), explain why the remaining terminal is the base when the
other two terminals give overload .0L with both polarities of the multimeter
applied?

2. Explain why Problem 6.4.1.(2) can be used to determine whether the transistor
is ’NPN’ or ’PNP’.

3. Explain why Problem 6.4.1.(3) can be used to determine the collector and the
emitter terminals.

6.4.2 Problem 2 : Operating point of BJTs

1. Compare the measured values with the theoretical ones. Discuss the differ-
ences.

2. Calculate the common emitter current gain β. Use only measured values!

3. Determine the error sources and check the plausibility of the calculated β value
by comparing it to the simulation. If the error is to high what is the reason
and is there a way to avoid it?

6.4.3 Problem 3 : Common emitter circuit

1. In what region of the output characteristic is the circuit for a distorted positive
or negative amplitude? Explain!

2. Using the measurements taken in the lab, calculate the voltage gain AV of the
amplifier. Compare to simulation.

3. Determine from the hard copies, what is the phase relationship between the
input and the output signals? Explain the reason for such a relation.

4. Compare the FFTs with the different input signals to the simulation.

6.4.4 Problem 4 : Bandwidth of amplifier circuit

1. In Problem 6.4.4.(2), explain your observation.

2. Using the measurements made in the lab, calculate the amplifier bandwidth.

3. Compare to the simulation! What are the reasons for the different cutoff
frequencies?

55
7. Experiment 4 :
Properties of the Differential Amplifier
Introduction to Operational Amplifier
7.1 Introduction to the Experiment
7.1.1 Objective of the Experiment
The aim of the experiment is to familiarize students with the basic functioning of
differential amplifiers. The manual also provides an overview of how these amplifiers
are used in op-amps.
The differential amplifier is introduced and the circuit characteristics are examined.
The different modes of the input signals are presented. In addition, the perfor-
mance of differential amplifiers is analyzed with regard to operating mode and noise
suppression.
Parameters of operational amplifiers (op-amps) such as input bias current, offset
voltage, slew rate and bandwidth are explained. A number of applications for the
operational amplifier as an inverting amplifier, non-inverting amplifier, adder and
integrator are presented.

7.1.2 Introduction
The differential amplifiers have several advantages over single-stage amplifiers based
on bipolar junction transistors (BJTs). In order to amplify ac signals single-stage
amplifiers require ac coupling capacitors on the input and output side (to insure
stable biasing point). As a consequence the low-end frequency response is reduce
and the amplifier becomes unusable as a dc amplifier. Another limiting factor is the
trade-off between gain and bias stability with variations in operating temperature
(e.g. the added emitter resistor RE to insure the bias stability against temperature
increases the input resistance but reduces the gain).
In contrast, the differential amplifier solves many of these problems. The main
characteristics that make differential amplifiers so useful are their large gain, ability
to reject noise and the fact that they amplify the difference between two signals.
For these reasons, the differential amplifier is used in most of the analog (discrete
and integrated) circuits. Also, the dc coupled differential amplifier design eliminates
large coupling capacitors used in single-stage amplifier configuration.
The Op-Amp is one of the most widely used components in analog electronics.
Every Op-Amp has a differential amplifier as its core. Although the Op-Amps basic
characteristics are simple, it can be used for a wide range of functions by adding
external components.

56
7.1.3 Theoretical Background
The Differential Amplifier Circuit
The differential amplifier can be implemented using bipolar junction transistors
(BJTs) or metal oxide semiconductor field effect transistor (MOSFETs). The basic
differential amplifier circuit using BJTs is shown in Fig. 7.1. The circuit consists
of two common-emitter amplifiers sharing an emitter resistor. The symbol of the
differential amplifier (Fig. 7.2) shows that it is a two-input / two-output device. The
two inputs are the base terminal of transistors Q1 and Q2 and the two outputs are
taken from the collector terminals of the transistors.

1 1 _ _ 1 1
Q1Q1 Q2Q2 Inputs Outputs
Inputs Outputs
2 2 ++ 2 2

Figure 7.2: Circuit symbol

Fig.
Fig. 1.2:
1.2: Circuit
Circuit symbol
symbol
Fig.
Fig.
Figure 1.1:
1.1:
7.1: Basic
Basic
Basic Differential
Differential
Differential Amplifier
Amplifier
Amplifier

Differential
Differential Amplifier
Amplifier Operation
Operation
Differential Amplifier
In In
thethe following,
following, thethe operation
operation of of differential
differential amplifiers
amplifiers willwill
bebe discussed
discussed based
based ononthethe
BJTBJT
The differential
operation
differential amplifier
ofamplifier
differential shown in in
amplifiers
shown figure 1.1.
will1.1.
figure be Initially,
discussed
Initially, we
based
we mustmust ensure
onensure
the BJT that thatQ1Qand
differen-1 and Q2Q2
areare in
tial amplifier the
in the active active
shown mode mode
in Fig. of of operation
7.1.operation
Initially, we (forward-biased
must ensure that
(forward-biased base-emitter
Q1 and Q2 are
base-emitter junction
in the and
junction and
reverse
active
reverse mode biased
biased base-collector
of operation
base-collector junction).
(forward-biased
junction). So, when
base-emitter
So, when designing
junction our
designing our
and amplifier,
reverse
amplifier, wewe
biased mustmust
make
make sure that
sure thatjunction).
base-collector our transistors
our transistors
So, when are not
aredesigning in saturation.
not in saturation. Usually
Usually
the amplifier, R
RC and
we must and
C make I
IC are are
Csure that soso
chosen
chosen
that
our thethecollector
transistors collector
are not potential of ofthethetwo
in saturation. twotransistors
Usually transistors
RC andisICisVare VC≈V /2 /2toso
chosen toallowallow
that forforthethe
the
that potential C≈V CCCC
maximum
collector
maximum required
potential
required output
ofoutput
the two voltage
transistors
voltage swing.
swing. is VC ≈ VCC/2 to allow for the maximum
required
When output
inputs voltage swing.
When inputs of ofthethe differential
differential amplifier
amplifier areare grounded
grounded (V(V
i1 i1=V
=V i2=0V),
i2=0V), thethe emitters
emitters of of
When
the inputs
two BJTsof the differential amplifier are grounded (V i1 = V i2 = 0V ), the emitters
the two BJTs
oftransistors
the two BJTs areare
are
applied
applied
applied
to
to to a potential
a potential
a potential
of
of of -0.7V
-0.7V
−0.7V (V(V
E(V
≈ -0.7V).
≈E -0.7V).
≈ −0.7V
It is
It is
).
assumed
assumed
It is assumed
that
that thethe
E
transistors
that the areare
transistors
identically
identically matched
matched
are identically byby
matched
careful
careful process
process
by careful
control
control
process
during
during
control
manufacturing
manufacturing
during man-
so so that
that their
their dc dc emitter
emitter currents
currents are
are thethe same
same when
when there
there is is
no no input
input signal.
signal. Thus,
Thus,
ufacturing so that their dc emitter currents are the same when there is no input
I = I= IThus,
Isignal. (1.1)
E1 E1 E2 E2 (1.1)
Since both emitter currents flow through R
Since = IE2emitter currents flow through Re e
IE1 both (7.1)
IE1I=I =I=I
E1E2 =IRe
E2Re /2 /2 (1.2)
(1.2)
Since both emitter currents flow through Re
Where,
Where,
IE1==(VIEE2- V = IRe /2 (7.2)
I IRe
Re = (V - V EE
E EE )/R)/Re
e
(1.3)
(1.3)
Since
Since IC I≈E,IE,
IC ≈ 57
I IC1
C1 = I= IC2
≈ I≈ IRe
C2 /2 /2
Re
(1.4)
(1.4)
Since
Since both
both collector
collector currents
currents and
and both
both collector
collector resistors
resistors areare equal
equal (when
(when thethe input
input
voltage is zero)
voltage is zero)
Where,

IRe = (VE − VEE )/Re (7.3)

Since IC ≈ IE ,

IC1 = IC2 ≈ IRe /2 (7.4)

Since both collector currents and both collector resistors are equal (when the input
voltage is zero)

VC1 = VC2 = VCC − IC1 RC1 = VCC − IC2 RC2 (7.5)

When a positive bias voltage is applied to input Vi1 while input Vi2 is still grounded,
the positive voltage on the base of Q1 increases IC1 and raises the emitter voltage.
This action reduces the forward bias VBE of Q2 because its base is grounded, thus
causing IC2 to decrease. The net result is that the increase in IC1 causes a decrease
in VC1 , and the decrease in IC2 causes an increase in VC2 .
If the positive bias voltage is applied to input Vi2 instead of input Vi1 while input
Vi1 is grounded, the result is that the increase in IC2 causes a decrease in VC2 , and
the decrease in IC1 causes an increase in VC1 .
Note: Symmetry is an important aspect of the differential amplifier design. Differ-
ences between the transistors or between the other components of the differential
leads to incorrect output signals.

Differential Amplifier Output Signals

There are two possibilities for taking the output of the differential amplifier.
ˆ A. Single-Ended Output
The output is measured between one of the output terminals (either Vo1 or
Vo2 ) and the ground. This is the most common case.

Vo = Vo1 or Vo = Vo2 (7.6)

ˆ B. Differential Output
The output is measured between the two output terminals Vo1 and Vo2 .

Vo = Vo2 − Vo1 (7.7)

Differential Amplifier Modes of Operation

The mode of operation of the differential amplifier can be distinguished in terms of
the input signal.
ˆ A. Single-Ended Input
In this mode, one input is grounded and the signal voltage is applied only to
the other input.
ˆ B. Differential Input
In this mode, two signals of opposite polarity (out of phase) are applied to the
inputs.

58
 ˆ C. Common-mode Input
In this mode, two signals of the same phase, frequency and amplitude are
applied to the two inputs.
Common-mode signals generally are the result of noise. The noise can be picked-up
by radiated energy on the input lines, from the adjacent lines, or the 50HZ power
line, or other sources. Those unwanted signals appear with the same polarity on
both input lines (Common-Mode Input). Desired signals appear on only one input
(Single-Ended Input) or with opposite polarities on both input lines (Differential
Input).
Ideally, differential amplifiers provide a very high gain for desired signals, and zero
gain for common-mode signals (the output signal for common-mode input should be
zero). However this is not the case. Practical differential amplifiers exhibit a very
small common mode gain (less than 1), while providing a high differential voltage
gain (several thousands).

Common-Mode Rejection Ratio (CMRR) in single-ended output mode

The ratio of the differential voltage gain Avdif f = Vod /Vid to the common mode
gain Avcm = Voc /Vic is called the Common-Mode Rejection Ratio (CMRR), which
provides a convenient measure of a differential amplifiers performance in rejecting
unwanted common-mode signals (unwanted signals will not appear on the outputs
to distort the desired signal). The higher the CMRR, the better the performance of
the differential amplifier.
Avdif f Re
CM RR = = for Re >> re (7.8)
Avcm re
The CMRR is often expressed in decibels (dB) as
Avdif f Re
CM RR = 20 log = 20 log dB for Re >> re (7.9)
Avcm re
Where,
Vid = differential input voltage = Vi1 − Vi2
Vic = common-mode input voltage = (Vi1 + Vi2 )/2
Vod = single-ended output voltage with differential input
Voc = single-ended output voltage with common-mode input
Vi1 and Vi2 are expressed in terms of Vid and Vic by

Vi1 = Vic + (Vid /2) & Vi2 =V ic −(Vid /2)

re is the small-signal input resistance between the base terminal and the emitter
terminal, looking into the emitter. For example, a CMRR of 10, 000 means that the
desired input signal (differential) is amplified 10, 000 times more than the unwanted
noise (common-mode). So, if the amplitudes of the differential input signal and the
common-mode noise are equal, the desired signal will appear on the out side 10, 000
times large in amplitude than the noise. Thus, the noise on the output side has
been drastically reduced.

59
 Differential Amplifier Improvement

As seen from the calculation for the CMRR, a large value of Re is desirable to in-
crease the amplification quality of a differential amplifier. Another way to increase
the CMRR is to replace Re by a con-
stant current source. By definition, an
ideal current source has an infinite out-
put resistance (∆v/∆i = ∆v/0 = ∞).
Replacing Re with a current Q1 source Q2
as
Q1 Q2
shown in Fig. 7.3 would greatly im-
prove the differential amplifier’s perfor-
mance. A simple current source consists
of an npn BJT and a biasing scheme
similar to the common-emitter ampli- Q3
Q3
fier. The resistance Re is chosen for
the specified biasing current and insures
that the transistor Q3 stays in the active
mode of operation. The large effective
impedance of the current source when Fig. Figure 7.3: Differential Amplifier using a tran-
1.3: Differential Amplifier using a transistor current source
used in the emitter circuit of the differ- sistor current source
ential input
Fig.amplifier stage substantially
1.3: Differential reduces
Amplifier using the common
a transistor mode
current gain and thus
source
increases the common mode rejection
Op-Amp ratio (CMRR).
Building Blocks
Op-Amp Building Blocks We are now moving from the differential amplifier to the operational amplifier. F
3.4 shows the building blocks of an Op-Amp. The Op-Amp has three stages
Op-Amp Building Blocks first stage is a differential input differential output amplifier. The differential outp
We are now moving from the differential amplifier
the first stage to into
are fed the operational
a differential amplifier. Fig- output differ
input single-ended
We are now moving from the differential
amplifier. amplifier to the
the operational amplifier. Figure
ure 7.4 shows the building blocks of anThe output of
Op-Amp. Thesecond
Op-Amp stagehasdrives an emitter
three stages.follower to achiev
3.4 shows the building blocks ofoutput an Op-Amp.
impedance. The Op-Amp
The first has to
stage serves three stages.
increase Theimpedance. Th
the input
The first stage is a differential and
input differential
second stages output amplifier. TheAlldifferential
first stage is a differential input differential outputprovide a high
amplifier. voltage
The gain.
differential stages are biased
outputs of through c
outputs of the first stage are fedsources.
into a differential input single-ended output differ-
the first stage are fed into a differential input single-ended output differential
ential amplifier.
amplifier. The outputTheofoutput of the second
the second stage stage
drivesdrives an emitter
an emitter follower
follower to achieve
to achieve low
low output impedance. The first
output impedance. The first stage servesstage +
serves to increase the input impedance.
to increase the input impedance. The firstThe
Vin
andfirst and second
second stagesstages
provideprovide
a highavoltage
high voltage
gain. gain.
All All stages
stages are biased
are biased through
through current Vou
current sources. V
- Diff-Amp Diff-Amp Emitter
sources. in
Follower

+
Vin Current Sources
Vout
Vin
- Diff-Amp Diff-Amp Emitter
Fig. 1.4: Op-Amp building blocks
Follower

Op-Amp Symbol and Terminals

The circuit symbol of an Op-Amp is shown in figure 1.5. The Op-Amp usuall
two for the power supply (Vs+ and Vs-) which are often not sho
Current Sources
five connections:
circuit diagrams for simplicity, an inverting input (Vin-), a non-inverting input (Vin+
an output (Vout).
Fig. 7.4:
Figure 1.4: Basic
Op-Amp building Amplifier
Differential blocks

8
Op-Amp Symbol and Terminals
The circuit symbol of an Op-Amp is shown in figure 1.5. The Op-Amp usually has
five connections: two for the power supply60(Vs+ and Vs-) which are often not shown in
circuit diagrams for simplicity, an inverting input (Vin-), a non-inverting input (Vin+) and
an output (Vout).
 Op-Amp Symbol and Terminals
An Op-Amp is basically a differential amplifier that amplifies the voltage difference at
its The
two circuit
inputs.symbol
The Op-Amp,
of an Op-Amptherefore like in
is shown differential amplifiers,
Fig. 7.5. The Op-Amp has two inputs
usually has
marked (-) and (+). The (-) terminal is
five connections: two for the power supply the inverting
(Vs and Vs ) which are often not shown (-)
+ input.
− A signal applied to the
o
terminal will diagrams
in circuit be shifted
forinsimplicity,
phase byan180 at theinput
inverting output.
(Vin−The (+) input is the
), a non-inverting inputnon-
inverting
+ input. A signal applied
(Vin ) and an output (Vout ). to the (+) terminal will appear in phase with the input
signal.

Fig. 1.5: Operational amplifier symbol

Figure 7.5: Basic Differential Amplifier

An Op-Amp is basically a differential amplifier that amplifies the voltage difference

Op-Amp
at its twoApplications
inputs. The Op-Amp, therefore like differential amplifiers, has two inputs
A. marked
Inverting and(+).
(-) and Non-Inverting Amplifier
The (-) terminal is the inverting input. A signal applied to the
◦
(-) terminal
Figure 1.6 showswill abebasic
shifted in phase
Op-Amp by 180
circuit, at the aoutput.
including negativeThe (+) input
feedback is the
loop. Note
noninverting input. A signal applied to the (+) terminal will appear in phase
that the output is fed back to the inverting input terminal in order to provide negative with
the input
feedback forsignal.
the amplifier. The input signal is applied to the inverting input. As a
result, the output signal will be out of phase by 180o (inverted signal). Such an
amplifier
7.1.4 is Op-Amp
called an inverting amplifier. If we assume the Op-Amp to be ideal, the
Applications
output of the amplifier is given by the equation
A. Inverting and Non-Inverting Amplifier

Figure R
Vout = −7.6F shows
Vin a basic Op-Amp circuit, including a negative feedback loop.(1.10)
Note
that theR output
R is fed back to the inverting input terminal in order to provide
negative feedback for the ampli- RF
fier. The input signal is applied
Note: Theinverting
to the minus sign indicates
input. As a that
re- the sign of the output is inverted as compared to
thesult,
input.
the output signal will be out RR
◦ Vin -
of phase
Thus by 180
the gain (inverted
of this signal).
inverting amplifier is given by Vout
Such an amplifier is called an in- +
verting amplifier.
Vout R F
Gain = = (1.11)
Vin R R Figure 7.6: Negative feed loop for inverting amplifier

If we assume the Op-Amp to be ideal, the output is given by the equation

RF
Vout = − Vin (7.10)
RR

61

9
The minus sign indicates that the sign of the output is inverted as compared to the
input.
Thus the gain of this inverting amplifier is given by
Vout RF
Gain = = (7.11)
Vin RR
It is possible to operate Op-Amps as non-inverting amplifiers by applying the signal
to the non-inverting (+) input, as shown in Fig. 7.7.

RF

RR
-
Vout
Vin +

Figure 7.7: Non-inverting amplifier

Note that the feedback is still connected to the inverting input. If we assume the
Op-Amp to be ideal, the output voltage for a non-inverting amplifier is given by
 
RF
Vout = + 1 Vin (7.12)
RR
corresponding gain is
 
Vout RF
Gain = = +1 (7.13)
Vin RR
In this case, the input and the output are in phase.

B. Adder and Subtractor

By adding additional input resistors to the basic inverting circuit in Fig. 7.6, we can
realize an adder as shown in Fig. 7.8. If we assume the Op-Amp to be again ideal,
the output voltage is given by
 
V1 V2 V3
Vout = −RF + + (7.14)
R1 R2 R3

Vout = −(V1 + V2 + V3 ) if R1 = R2 = R3 = RF (7.15)

A useful feature of this circuit is that there is no interaction between inputs. There-
fore, the different inputs of the adder do not affect each other. This is possible due
to the virtual ground at the summing connection (check the practical hints for more
information regarding the virtual ground).
A subtractor circuit is shown in Fig. 7.9.The output signal can be calculated by
RF
Vout = (V2 − V1 ) where, R1 = R2 = R (7.16)
R

62
 R1
V1 RF
R2
V2
R3
V3 -
Vout
+

Figure 7.8: Adder Amplifier

RF

R1
V1 -
R2 Vout
V2 +

RF

Figure 7.9: Adder/Subtractor Amplifier Configuration

C. Integrator and Differentiator

Integrators are widely used in practice because their frequency response has lowpass
characteristics. Therefore, integrators can be used as filters, which filter out the
high frequency components of a signal (e.g. noise).
Fig. 7.10 shows the Op-Amp configuration of an Integrator. Assuming that the
capacitor is uncharged at t = 0, the output voltage of the integrator is given by
Z t
1
Vout (t) = − Vin (t)dt (7.17)
RC 0

R
Vin -
Vout
+

Figure 7.10: Integrator Amplifier Configuration

63
Integrators have the disadvantage that dc component of the input voltage are in-
tegrated as well. If the input voltage has a non-zero average value (dc term), the
output signal of the integrator becomes a linear ramp, which over time will saturate
the Op-Amp. The same is true for small dc voltages and currents present at the
inputs of the Op-Amp (known as input offset voltages and currents). The dc signals
will get integrated and they could over time saturate the Op-Amp.
By reversing the resistor and the capacitor the integrator, we have a differentiator
as shown in Fig. 7.11. The output voltage is given by

dVin (t)
Vout (t) = −RC (7.18)
dt

C
Vin -
Vout
+

Figure 7.11: Integrator Amplifier Configuration

Differentiators have high-pass filter characteristics and may have excessive gain at
high frequencies where noise may be present. For this reason modifications may by
used to roll-off the gain beyond the corner frequency.

7.1.5 Practical Background

Op-Amp Characteristics
The ideal Op-Amp has infinite voltage gain, infinite bandwidth, infinite input impedance
and zero output impedance. The practical Op-Amp has voltage and current limita-
tions. Peak-to-peak output voltage, for example, is usually limited to slightly less
than the two supply voltages. Output current is also limited by internal restrictions
such as power dissipation and component ratings. Therefore, the practical Op-Amp
characteristics are high voltage gain, wide bandwidth, high input impedance and
low output impedance.

A. Input offset Voltage

Ideally, the Op-Amp output is 0V if the voltage between the inverting and nonin-
verting inputs is 0V . In reality, the output voltage has a small dc voltage offset
when no differential input is applied. This output voltage is caused by internal
mismatches (between the base-emitter voltages of the differential input stage, which
causes a small difference in the collector currents that results in a nonzero value
of the output voltage), tolerances and so on. In other words, even if the invert-

64
 ing and non-inverting input are shorted
- to eliminate the effect of input bias, as
Vout shown in Fig. 7.12, the output may have
+
a slight offset. Therefore, the input off-
set voltage can be defined as the differ-
ential dc voltage required between the
Figure 7.12: Input offset voltage
inputs to force the differential output to
zero volts. Typical values of input offset voltage are in the range of 2mV or less.

B. Input Bias Current

In order to determine the input bias current of an Op-Amp, the inputs (inverting and
non-inverting) are grounded through equal resistances RB (Fig. 7.13). The input
current flowing into the two bases may
not be the same. The slightly unequal -
Vout
base currents flowing through the exter- +
nal resistance produce small differential
input voltage; this represents a false in- RB RB
put signal. When amplified, this small
input produces the offset in the output
voltage. The input bias current shown Figure 7.13: Input bias current
on data sheets is the average of the two input currents. It corresponds approxi-
mately to the values of the currents into the two bases. The smaller the input bias
current, the smaller the possible unbalance.

C. Bandwidth
The slew rate distortion of a sine wave starts at the point where the initial slope
of the sine wave equals the slew rate of the Op-Amp. The maximum frequency at
which the Op-Amp can be operated without distortion is
SR
fmax = (7.19)
2πVp
Where,
fmax : Highest undistorted frequency,
SR : Slew rate of Op-Amp
Vp : Peak voltage of the output sine wave.

D. Slew Rate

Slew rate is one of most important characteristics of an Op-Amp as it places a severe

limit on large-signal operation.
It is defined as the maximum
rate of change of the output
voltage in response to a step in-
put voltage. The LM741 Op-
Amp, for instance, has a typi-
cal slew rate of 0.5V /µs. This Fig.Figure
1.16: Overdrive produces
7.14: Overdrive slew-rate
produces limiting
slew rate limiting

65
D. Bandwidth
The slew rate distortion of a sine wave starts at the point where the initial slope of
the sine wave equals the slew rate of the Op-Amp. The maximum frequency at which
the Op-Amp can be operated without distortion is
is the ultimate speed of a typical LM741; its output voltage cannot change faster
than that. If we drive a LM741 with a large step input, the output slew (rises
linearly) as shown in Fig. 7.14. A certain time interval (20µs) is required for the
output to change from 0 to 10 volts.

Circuit Analysis
In practice, there are assumptions for analysis and design of Op-Amp circuits where
the Op-Amp can be considered to be ideal. These are:

1. The current flowing into the Vin+ and Vin− inputs is negligible (Iin
+ −
= Iin = 0).
+ −
The currents Iin and Iin are the input currents of the Op-Amp.

2. The open loop gain of the amplifier is assumed to be A = ∞. The open

loop gain (the output to input voltage ratio of the Op-Amp without external
feedback) is very large, and is effectively infinity.

3. For the inverting closed loop configuration, as the open loop gain (A) ap-
proaches infinity, the voltage V − approaches V + (V + ≈ V − ). As V + is con-
nected to ground; thus V + = 0 and V − ≈ 0. That is why this situation is
called the virtual ground.

7.1.6 References
1. Floyd, Electronics Fundamentals, Prentice-Hall, Fifth edition, 2001.

2. Sedra / Smith, Microelectronic Circuits, Saunders College Publishing (1991),

Third edition.

3. P. Horowitz, W. Hill, The Art of Electronics, Cambridge University (1989).

66
7.2 Prelab Operation Amplifier
7.2.1 Problem 1 : Simulate a Differential Amplifier
Sketch the following circuit in LTSpice:

+10V

R1 R2 +10V
2K20 2K20
VC1 VC2
V3
R4 T1 T2 R5 10V
Input 1 4K70 4K70 Input 2
2 x 2N2222

V4
10V
V1 ~ ~ V2

R3
2K20 -10V

-10V

1. Perform a dc operation point analysis for the above circuit. Determine the
values for VBE (T 1, T 2), VC (T 1, T 2) , IC (T 1, T 2), IE (T 1, T 2), and IRE . What
would happen with the values in the two branches if the transistors are not
absolute identical.
Hint: To get an idea, replace one 2N2222 transistor -temporarily- with a
2N3904 from the library.

2. Perform a transient analysis. Use single ended input mode. Set V1 at input
1 to Sine, f = 1KHz, û = 50mV , and V2 at input 2 to GND. Display and
measure the two collector voltages! Calculate AV dif f in dB.

3. Perform a simulation with common mode input. Set V1 and V2 at input 1

and 2 to Sine, f = 1KHz, û = 50mV , and V2 to Gnd. Display and measure
the two collector voltages. Calculate AV cm in dB.

4. Calculate the common-mode rejection ratio in dB!

5. Replace the resistor R3 by a current source. Use the same current you got
from the .op analysis in step 1 for IR3 .
Note : Use the PSpice current source! Take care of the flow direction of the
current. If you set it wrong the simulator runs ’forever’ !!

6. Repeat step 1 - 4 for the new circuit.

67
7.3 Execution Operation Amplifier
7.3.1 Problem 1 : Differential amplifier using a fixed emitter
resistor
The following experiment should show the differences between the simulation (the
more or less ideal case) and what happens if using real components.
Assemble the following circuit:

+10V

R1 R2 +10V
2K20 2K20
VC1 VC2
V3
R4 T1 T2 R5 10V
Input 1 4K70 4K70 Input 2
2 x 2N2222

V4
10V
V1 ~ ~ V2

R3
2K20 -10V

-10V

1. Measure the dc bias values.

Connect both inputs to ground (V1 = V2 = 0 V). Measure VC (T1,T2),
VB (T1,T2), VBE (T1,T2), IC (T1,T2) for each transistor and IRE .

2. Determine differential-mode gain Avdm .

Use single ended input mode. Set V2 = 0 V and V1 to Sine, f = 1 KHz,
û = 50 mV. Display and measure the two collector voltages. Take a hardcopy.

3. Determine common-mode gain Avcm ).

Use common input mode. Set V1 and V2 to Sine, f = 1 KHz, û = 50 mV.
Display and measure the two collector voltages. Take a hardcopy.

68
7.3.2 Problem 2 : Implement a Current Source
Use the constant current circuit from the prelab of the BJT experiment (Problem
2!).

from Emitter
T1,2
Iz = 10mA
R1
I = 4mA

Q2 Vcc
2N2222 10V

R2 1N750A

1. Calculate R1 and R2 to get about the same IRE as in the circuit with the fixed
emitter resistor.

2. Implement the circuit on the breadboard. Check the current!

3. Connect the current source to the differential amplifier. Check if the circuit is
operational!

7.3.3 Problem 3 : Differential amplifier using a Current

Source
1. Measure the dc bias values.
Connect both inputs to ground (V1 = V2 = 0 V). Measure VC (T1,T2),
VB (T1,T2), VBE (T1,T2), IC (T1,T2) for each transistor and IRE .

2. Determine differential-mode gain Avdm .

Use single ended input mode. Set V2 = 0 V and V1 to Sine, f = 1 KHz,
û = 50 mV. Display and measure the two collector voltages. Take a hardcopy.

3. Determine common-mode gain Avcm ).

Use common input mode. Set V1 and V2 to Sine, f = 1 KHz, û = 50 mV.
Display and measure the two collector voltages. Take a hardcopy.

69
7.4 Evaluation
7.4.1 Problem 1 : Differential amplifier using a fixed emitter
resistor
1. Compare the experimentally taken DC bias values by the simulation. Name
at least three important reasons for differences!

2. Calculate Avdm , Avcm , and the CMRR.

7.4.2 Problem 3 : Differential amplifier using a Current

Source
1. Compare the experimentally taken DC bias values by the simulation. Name
at least three important reasons for differences!

2. Calculate Avdm , Avcm , and the CMRR.

3. Compare the performance of the circuit with the fixed emitter resistor and the
constant current source.

70
8. Experiment 5 : Metal Oxide Field Ef-
fect Transistor
8.1 Introduction to the Experiment
8.1.1 Objective of the Experiment
The objective of experiment is to become familiar with the characteristics and ap-
plications of Field Effect Transistors (MOSFETs). The experiment includes the
investigation of the I-V characteristics and the implementation of MOSFETs as
amplifiers and switches.

8.1.2 Introduction
The most common transistor types are the Metal Oxide Semiconductor Field Effect
Transistors (MOSFETs) and the Bipolar Junction Transistors (BJT). BJTs based
circuits dominated the electronics market in the 1960’s and 1970’s. Nowadays most
electronic circuits, particularly integrated circuits (ICs), are made of MOSFETs.
The BJTs are mainly used for specific applications like analog circuits (e.g. ampli-
fiers), high-speed circuits or power electronics.
There are two main differences between BJTs and FETs. The first is that FETs are
charge-controlled devices while BJTs are current or voltage controlled devices. The
second difference is that the input impedance of the FETs is very high while that
of BJT is relatively low.
As for the FET transistors, there are two main types: the junction field-effect tran-
sistor (JFET) and the metal oxide semiconductor field effect transistor (MOSFET).
The power dissipation of a JFET is high in comparison to MOSFETs. Therefore,
JFETs are less important if it comes to the realization of ICs, where transistors are
densely packed. The power dissipation of a JFET based circuit would be simply too
high. MOSFETs became the most popular field effect device in the 1980’s.
The combination of n-type and p-type MOSFETs allow for the realization of the
Complementary Metal Oxide Semiconductor (CMOS) technology, which is nowadays
the most important technology in electronics. All microprocessors and memory
products are based on CMOS technology. The very low power dissipation of CMOS
circuits allows for the integration of millions of transistors on a single chip. In this
experiment, we will concentrate on the MOSFET transistor. We will investigate its
characteristics and study it’s behaviour when used as an amplifier or a switch.

8.1.3 Theoretical Background

MOSFETs Structure and Physical Operation
The MOSFETs are the most widely used FETs. Strictly speaking, MOSFET devices
belong to the group of Insulated Gate Field Effect Transistor (IGFETs). As the

71
 or the channel is physically implemented and whether the current flowing in the
name implies,
channel is anthe gate is
electron insulated
current fromcurrent.
or a hole the channel by an insulator. In most of the
cases, the insulator is formed by a silicon dioxide (SiO2 ), which
If the channel between the drain and the source is an induced
leads to the term
channel, the transistor
MOSFET. MOSETs liketransistor.
is called enhancement all other IfIGFETs has three
the channel between terminals,
the drainwhich are called
and source is
Gate (G), Source (S), and Drain (D). In certain cases, the transistors
physically implemented then the transistor is called depletion transistor. If the current have a fourth
terminal,
flowing which
in the is called the
channel is an bulk or the current,
electron body terminal. In PMOS,
the transistor the body
is called terminal
an n-type or
is held at the most positive voltage in the circuit and in NMOS, it is held at p-
NMOS transistor. If the current flow is a hole current then the transistor is called the
typenegative
most or PMOSvoltage transistor.
in the circuit.
Throughout
There are fourthetypes handout we will concentrate
of MOSFETs: on analyzing
enhancement n-type the enhancement
MOSFET, n-type
enhancement
MOSFET.
p-type MOSFET, The cross sectionn-type
depletion of an enhancement
MOSFET, and NMOS transistor
depletion is shown
p-type MOSFET. in figure
The
2.1.
type depends whether the channel between the drain and source is an induced chan-
nelIf or
wetheput channel
the drainisand source on
physically ground potential
implemented and applythe
and whether a positive
currentvoltage
flowingtointhe the
gate, the free holes (positive charges)
channel is an electron current or a hole current. are repelled from the region of the substrate
If under the gate (channel region) due to the positive voltage applied to the gate. The
the channel between the drain and the source is an induced channel, the transistor
holes are pushed away downwards into the substrate leaving behind a depletion
is region.
called At enhancement
the same time, transistor.
the positiveIf the
gatechannel betweenelectrons
voltage attracts the drain intoand source is
the channel
physically
region. When implemented then theof transistor
the concentration electrons nearis called depletion
the surface of thetransistor.
substrate under If the
current
the gate flowing
is higherin the
thanchannel is an electron
the concentration current,
of holes, an n the
regiontransistor is called
is created, an n-
connecting
theor
type source
NMOS and the drain If
transistor. regions. The induced
the current flow is n-region thus forms
a hole current then the
the channel
transistor foris
current flow from
called ptype or PMOS transistor.drain to source. The channel is only a few nanometres wide.
Nevertheless,
Throughout thethe entire current
handout we will transport occurson
concentrate in this thin channel
analyzing between drainn-
the enhancement
and source. Now if a voltage is applied between drain and source electrodes an
type MOSFET.
electron current The crossthrough
can flow sectiontheofinduced
an enhancement
channel. NMOS transistor is shown
in Fig. 8.1. If we put the drain and source on ground potential and apply a positive

Fig. 2.1: Schematic cross section of an enhancement-type NMOS transistor

Figure 8.1: Schematic cross section of an enhancement-type NMOS transistor

Increasing
voltage to thethe voltage
gate, applied
the free holes to the gate
(positive aboveare
charges) a repelled
certain threshold voltageof
from the region
enhances the channel. In the case of an enhancement type NMOS transistor
the substrate under the gate (channel region) due to the positive voltage applied theto
thethreshold voltage is positive, whereas an enhancement type PMOS transistor has a
gate. The holes are pushed away downwards into the substrate leaving behind
negative threshold voltage. So, in order for the current to flow from drain to source,
a depletion region.
the condition At the
that should besame time,
satisfied is Vthe positive gate voltage attracts electrons
G > Vth, where VG is the gate voltage and Vth
into the channel region. When the concentration
is the minimum voltage required to form a channel between of electrons
drain near the surface
and source so thatof
the substrate under the gate is higher than the concentration of holes, an n region
is created, connecting the source and the 5drain regions. The induced n-region thus
forms the channel for current flow from drain to source. The channel is only a
few nanometers wide. Nevertheless, the entire current transport occurs in this thin

72
channel between drain and source. Now if a voltage is applied between drain and
source electrodes an electron current can flow through the induced channel.
Increasing the voltage applied to the gate above a certain threshold voltage enhances
the channel. In the case of an enhancement type NMOS transistor the threshold
voltage is positive, whereas an enhancement type PMOS transistor has a negative
threshold voltage. So, in order for the current to flow from drain to source, the
condition that should be satisfied is VG > Vth , where VG is the gate voltage and Vth
is the minimum voltage required to form a channel between drain and source so that
carriers can flow through the channel. By changing the applied gate voltage, we can
carriers can flow through the channel. By changing the applied gate voltage, we can
modulate
modulatethetheconductance
conductance of of the channel. Depletion type MOSFETs use a different
the channel.
approach. The channel is already conductive for gate voltages of 0V . Such kinds
Depletion type MOSFETs use a different approach. The channel is already
ofconductive
MOS transistors are realized by the physical implantation of an n-type region
for gate voltages of 0V. Such kinds of MOS transistors are realized by the
between
physicalthe drain andofthe
implantation an source.
n-type region between the drain and the source.
Figure 8.2 shows several symbols used for describing the enhancement NMOS and
Figure 4.2 shows several symbols used for describing the enhancement NMOS and
PMOS
PMOStransistors.
transistors.

Figure
Fig.8.2:
2.2: Symbols for Enhancement
Symbols for EnhancementNMOS
NMOS and
and PMOS
PMOS transistors
transistors

MOSFET
MOSFET I-VCharacteristic
I-V Characteristic
Based on the physical foundation briefly established so far, we will introduce now the
Based on theofphysical
description foundation briefly
the I-V characteristics established n-type
of enhancement so far,MOSFETs.
we will introduce
The outputnow
the description of the I-V characteristics of enhancement n-type
curves of an enhancement n-type MOSFET are shown in figure 2.3. The curves are MOSFETs. The
output
called curves of an enhancement
output curves, n-typecurrent
because the drain MOSFET are shown
ID is shown as a in Fig. 8.3.
function The
of drain
source voltage, V . The drain current is shown for different gate voltage
curves are called output curves, because the drain current ID is shown as a function
DS V GS . Based
ofon the output
drain sourcecurves
voltage,three
VDSdifferent devicecurrent
. The drain regionsisofshown
operation
for can be distinguished:
different gate voltage
cut-off region, linear (triode) region and saturation region. Digital circuits usually
VGS . Based on the output curves three different device regions of operation can be
make excursions into all three regions, whereas analog circuits such as amplifiers
distinguished: cut-off
typically only use region, linear
the saturation (triode) region and saturation region. Digital
region.
circuits usually make excursions into all three regions, whereas analog circuits such
as amplifiers typically only use the saturation region.

73
 Figure 8.3: Output curves of an n-type enhancement MOSFET [3]
Fig. 2.3: Output curves of an n-type enhancement MOSFET [3].

MOSFET Regions of Operation

InMOSFET
order for theRegions
MOSFET to ofwork
Operation
in any of the three regions, some conditions should
beInsatisfied
order forwhich in turn to
the MOSFET control
work inthe performance
any of the three of the transistor,
regions, as follows:
some conditions should
be satisfied which in turn control the performance of the transistor, as follows:
1. Cut-off Region
MOSFETs are in the cut-off region when there is no current flow between
1. Cut-off
sourceRegion
and drain terminals. This happens when the gate-to-source voltage is
less than
MOSFETs arethe threshold
in the voltage,
cut-off region i.e.,there
when VGSis<noVthcurrent
. flow between source and
drain terminals. This happens when the gate-to-source voltage is less than the
2. Linear
threshold (Triode)
voltage, i.e., VRegion
GS<Vth.
For voltages higher than the threshold voltage, the transistor operates in the
linear or triode region if at the same time the voltage VDS is smaller than
2. Linear
VGS −(Triode)
Vth . InRegion
this case, the current flow is a function of both gate-to-source
For voltages higher
voltage and thethan the threshold voltage,
drain-to-source voltage, the transistor
as we will seeoperates
below. in the linear or
triode region if at the same time the voltage VDS is smaller than VGS-Vth. In this case,
the
3. current flow isRegion
Saturation a function of both gate-to-source voltage and the drain-to-source
voltage,
The MOSFET is below.
as we will see in the saturation region if VDS > VGS − Vth . In this case,
the drain current is primarily a function of the gate-to-source voltage, as we
will see below.
3. Saturation Region In the linear region of the transistor the drain current can be
described by:
The MOSFET is in the saturation region if VDS>VGS-Vth. In this case, the drain current
is primarily a function
W of the gate-to-source

1 voltage,
 as we will see below.
ID = µn CG VGS − Vth − VDS VDS (8.1a)
In the linear region of
L the transistor the2 drain current can be described by:
where, µn is the free carrier mobility, which is in this case (n-channel device)
the electron mobility. CG is the gate7 capacitance of the MOS transistor. In
most of the cases, the gate dielectric is realized by silicon dioxide. The gate

74
 capacitance is determined by the dielectric constant of the silicon dioxide and
the thickness of the dielectric. W and L are the width and the length of the
transistor. Therefore, W and L define the lateral dimensions of the transistor.
The third transistor dimension is defined by the thickness of the dielectric,
which determines the gate capacitance. The voltages VGS and VDS are the
gate-source and the drain-source voltages respectively.
If VDS is sufficiently small,
W
ID = µn CG (VGS − Vth ) VDS (8.1b)
L
Based on Eq. (8.1b) it can be easily seen that the drain current increases
linearly with the drain-source voltage.
For drain source voltages larger than VGS − Vth the channel region is not
continuous anymore. In this case, the channel is pinched off. Pinch off is
observed for VDS = VGS − Vth . For higher voltages, the transistor operates
in saturation region. Substituting the drain source voltage in Eq. (8.1a) by
VDS = VGS − Vth leads to the following expression for the drain current in the
saturation region:
W
ID = µn CG (VGS − Vth )2 (8.2)
2L
As it can be seen based on these equations, the drain current gets independent
of the drain source voltage. The gate voltage determines the drain current. A
more detailed description of the I-V characteristic of MOS field effect transis-
tors is given in the references [2,3,4].

Threshold Voltage
It is important to note that the threshold voltage Vth of MOSFETs can be controlled
by the fabrication process and can be made either positive or negative for both types
of MOSFETs.
In the case of enhancement type transistors the channel is formed (induced) by the
applied gate voltage and the threshold voltage is defined in the following way:
ˆ Enhancement type NMOS: Vth > 0

ˆ Enhancement type PMOS: Vth < 0

In the case of a depletion type transistor the channel is already physically imple-
mented by doping the region so that already a drain current can flow for VGS = 0V .
ˆ Depletion Mode NMOS: Vth < 0

ˆ Depletion Mode PMOS: Vth > 0

8.1.4 Applications
MOSFET can be used in several applications including amplifiers, logic circuits,
memories and power electronics applications.

75
1. MOSFET as a Switch
Fig. 2.5: Load line for the amplifier in figure 2.4
A common application of MOSFETs is switches in analog and digital circuits.
Switches in analog circuits can be used for example in data acquisition systems,
where they2. serve
MOSFET as a Switch:
as analog multiplexors, which allow the selection of one of several
data inputs. In otherapplication
A common applications, they mayis change
of MOSFETs switchesgain of an operational
in analog amplifier
and digital circuits.
Switches in analog circuits can be used for example in data
or an attenuation ratio by switching different resistors, depending on the control acquisition systems,
where they serve as analog multiplexers, which allow the selection of one of several
voltage levels set usually
data inputs. byapplications,
In other digital circuits.
they may change gain of an operational amplifier
A simple example of a switching
or an attenuation ratio circuit based
by switching on resistors,
different an n-typedepending
enhancement on the transistor
control
voltage levels set usually by digital circuits.
and a resistor is shown in Fig. 8.4. The voltage applied to the gate controls the
A simple
conductance example
of the of a switching
channel. A zero circuit
or low based
valueon of
an Vn-type enhancement transistor
GS the conductance is very
and a resistor is shown in figure 2.7. The voltage applied to the gate controls the
low so that is the transistor acts like an open circuit and no current flows through
conductance of the channel. A zero or low value of VGS the conductance is very low
the load resistor RL .transistor
so that is the Whenacts VGSlikeexceeds
an openthe threshold,
circuit the flows
and no current channel conductance
through the load
resistor R . When V exceeds the threshold, the channel
becomes higher and the transistor acts like a closed switch. The channel resistance
L GS conductance becomes
higher and the transistor acts like a closed switch. The channel resistance is not
is not getting zero but the resistance is getting small so that the output voltage V
getting zero but the resistance is getting small so that the output voltage Vout is out
is gettinggetting
small.small.
Figure 8.4a
Figure 2.7ashows
shows an NMOSswitching
an NMOS switching
FET FET
and it’sand it’sfor
models models
Vin = 0 for
Vin = 0 (Fig. 8.4b)
(figure 2.7b)andandVVinin = +5V
= +5 (Fig. 2.7c).
V (figure 8.4c).InIn each
each case,
case, thethe
FETFET is modeled
is modelled as a as
mechanical
a mechanical switch. switch.

Fig. 2.7: An NMOS transistor switch

Figure 8.4: An NMOS transistor switch
10

As for PMOS, a negative value of VGS has to be applied to turn the transistor on.
The operation can be described using the curves shown in Fig. 8.5. When the input
voltage, VGS , of the transistor shown in Fig. 8.5 is zero, the MOSFET conducts
virtually no current, and the output voltage, Vout , is equal to VDD . When VGS is
equal to 5V , the MOSFET Q-point moves from point A to point B along the load
line, with VDS = 0.5V . Thus, the circuit acts as an inverter. The inverter forms the
basis of all MOS logic gates.
Another example of MOSFETs as switches is shown in Fig. 8.6. Here two transis-
tors form a transmission gate. In this circuit, the channels of NMOS and PMOS
transistors are connected in parallel. The signal applied to the input (A) is being
transmitted if the voltage applied to the NMOS transistor is positive (a logic high)
and the voltage applied to the PMOS transistor is negative (logic low). Both tran-
sistors are turned on so that the output signal is equal to the input signal. The
transmission gate actually acts as a bidirectional switch, where signal can be trans-
mitted from the input to the output side and vice versa. If the voltage applied to

76
 The operation can be described using the curves shown in figure 4.8. When the input
voltage, Vin, of the transistor shown in figure 4.7 is zero, the MOSFET conducts
virtually no current, and the output voltage, Vout, is equal to VDD. When Vin is equal to
5 V, the MOSFET Q-point moves from point A to point B along the load line, with VDS
= 0.5 V. Thus, the circuit acts as an inverter. The inverter forms the basis of all MOS
logic gates.

Fig. 2.8: MOSFET switching characteristic

Figure 8.5: MOSFET switching characteristic
Another example of MOSFETs as switches is shown in figure 2.9. Here two
the PMOStransistors form a transmission
transistor is positive and gate.the voltage applied to the NMOS transistor is
negativeIn both transistors
this circuit, are turns
the channels off andand
of NMOS no PMOS
signalstransistors
can be transmitted.
are connected in
parallel. The
It is relatively signal applied
obvious to see to the such
that input (A) is being
circuit cantransmitted
be used iffor
theseveral
voltage applications
applied
to the NMOS transistor is positive (a logic high) and the voltage applied to the PMOS
like thetransistor
implementation
is negativeof(logic
logiclow).
circuits. The implementation
Both transistors are turned on of
so logic circuits
that the output based
on transmission gatesto isthecalled
signal is equal input ”Pass
signal. Transistor logic”gate
The transmission (PLT).
actually acts as a bi-
directional switch, where signal can be transmitted from the input to the output side
and vice versa. If the voltage applied to the PMOS transistor is positive and the
voltage applied to the NMOS transistor is negative both transistors are turns off and
no signals can be transmitted.
It is relatively obvious to see that such circuit can be used for several applications
like the implementation of logic circuits. The implementation of logic circuits based
on transmission gates is called “Pass Transistor logic” (PLT).

11

Fig. 2.9: Transmission gate Fig. 2.10: 2-to-1 multiplexer using PTL
Figure 8.6: Transmission
Fig. 2.9: Transmission gate
gate Fig.Figure
2.10: 2-to-1
8.7: multiplexer using PTL
2-to-1 multiplexer using
PTL
Using PTL as logic circuit will be clarified with an example. In this example, a simple
Using
multiplexer
Using PTL
isPTLas as
build logic circuit
oflogic
PTLs. will will
Figure
circuit be 4.10
clarified
shows withawith
be clarified an example.
two-to-one
an example. In this
In example,
multiplexer.
this Based a simple
example, on a
the multiplexer
simple multiplexer is build of PTLs. Figure 8.7 shows a two-to-one multiplexer.on
logic value is
of build
C, of
either PTLs.
A or B Figure
is 4.10
connected shows
to the a two-to-one
output Y. multiplexer. Based
the logic on value of C, either A or Beither
is connected toconnected
the output toY.
MOS Based
transistors thearelogic value of
easier to C,fabricate A than
or B isbipolar the output
transistors, whichY. makes
MOS transistors
production economicalare easiervolume.
in large to fabricate
On the thanother bipolar
hand, MOS transistors, which
transistors makes
cannot
production
provide as much economical
current
2. MOSFET as an Amplifier asin large
BJTs, volume.
and theirOn the
switching other hand,
speeds MOS
are nottransistors
quite as cannot
fast.
Thisprovide as much
is at least true current
in termsasofBJTs, and their switching
the underlying physical speeds are not
principles. quite itasisfast.
Overall,
This is
A MOSFET
certainly trueat that,
leastthroughout
true in terms
amplifier circuit
the lastof
is the
shownunderlying
20 years in itFig.
has8.8.physical
The principles.
become MOSFET is Overall,
increasingly used as ita is
common
certainly
to design
common true
logic that,amplifier.
circuits
source throughout
based on The the
MOS lasttechnology.
voltage 20divider
years based
it In
has become
particular,
on increasingly
the
two resistors R1 andcommon
application Rof2 is
CMOSto design logic circuits
(Complementary based
Metal Oxide on MOS technology. technology
Semiconductor) In particular, the application
- where both p- of
andCMOS (Complementary
n-channel enhancement-type Metal MOSFETs
Oxide Semiconductor)
77 are used - has technology
lead to - tremendous
where both p-
and n-channel
progress in terms enhancement-type
of power dissipation MOSFETs are usedof- logic
and complexity has lead to tremendous
circuits. CMOS
progress
inverters and in MOS termslogicofgates
power willdissipation
be discussed andincomplexity
experimentof3 logicof thecircuits.
ElectronicsCMOS
Lab.inverters and MOS logic gates will be discussed in experiment 3 of the Electronics
Lab.
OSFET amplifier circuit is shown in figure 2.4. The MOSFET is used as a
on source amplifier. The voltage divider based on two resistors R1 and R2 is
to define the Q-point or the operating point of the gate-to-source voltage VGSQ.
Q-point on the input side will then define the Q-point of the drain-to-source
e VDSQ on the output side.
used to define the Q-point or the oper-
ating point of the gate-to-source voltage
VGSQ . The Q-point on the input side will
then define the Q-point of the drain-to-
source voltage VDSQ on the output side.
The operating point of the MOSFET cir-
cuit can be graphically extracted from
the graph in Fig. 8.9. In this amplifier
circuit, cut-off occurs when ID = 0. Sub-
sequently, the output voltage reaches its
maximum value Vout = VDD . On the
other hand, if the input voltage increases,
the output voltage swings along the line
to reached the Vout = VDSmin = VGS −VT ,
Figure 8.8: A common-source amplifier the pinch-off value. As an amplifier op-
Fig. 2.4: A common-source amplifier
erates in the saturation region, the Q-point of the drain-to-source voltage has to be
in the range between VDSmin and VDSmax .
perating point of the MOSFET circuit can be graphically extracted from the
in figure 2.5. In this amplifier circuit, cut-off occurs when ID=0. Subsequently,
utput voltage reaches its maximum value Vout=VDD. On the other hand, if the
voltage increases, the output voltage swings along the line to reached the
VDSmin= VGS-VT, the pinch-off value. As an amplifier operates in the saturation
n, the Q-point of the drain-to-source voltage has to be in the range between
and VDSmax.

Fig. 2.5: Load line for the amplifier in figure 2.4

Figure 8.9: Output curves of an n-type enhancement MOSFET [3]

2. MOSFET as a Switch:
A common application of MOSFETs is switches in analog and digital circuits.
Switches in analog 9circuits can be used for example in data acquisition systems,
where they serve as analog multiplexers, which allow the selection of one of several
data inputs. In other applications, they may change gain of an operational amplifier
or an attenuation ratio by switching different resistors, depending on the control
voltage levels set usually by digital circuits.
A simple example of a switching circuit based on an n-type enhancement transistor
and a resistor is shown in figure 2.7. The voltage applied to the gate controls the
conductance of the channel. A zero or low value of VGS the conductance is very low
so that is the transistor acts like an open circuit and no current flows through the load
resistor RL. When VGS exceeds the threshold, the channel conductance becomes
higher and the transistor acts like a closed switch. The channel resistance is not
getting zero but the resistance is getting small so that the output voltage Vout is
getting small. Figure 2.7a shows an NMOS switching FET and it’s models for Vin = 0
(figure 2.7b) and Vin = +5 V (figure 2.7c). In each case, the FET is modelled as a
mechanical switch.
78
MOS transistors are easier to fabricate than bipolar transistors, which makes pro-
duction economical in large volume. On the other hand, MOS transistors cannot
provide as much current as BJTs, and their switching speeds are not quite as fast.
This is at least true in terms of the underlying physical principles. Overall, it is
certainly true that, throughout the last 20 years it has become increasingly common
to design logic circuits based on MOS technology. In particular, the application of
CMOS (Complementary Metal Oxide Semiconductor) technology - where both pand
n-channel enhancement-type MOSFETs are used - has lead to tremendous progress
in terms of power dissipation and complexity of logic circuits.

8.1.5 References
1. A.S. Sedra, K.C. Smith, Microelectronic Circuits, Oxford University Press
(1998).

2. J. Keown, ORCAD PSpice and Circuit Analysis, Prentice Hall Press (2001).

3. P. Horowitz, W. Hill, The Art of Electronics, Cambridge University Press

(1989).

4. David Comer & Donald Comer, ”Fundamentals of Electronic Circuit Design”

79
8.2 Prelab Field Effect Transistor
8.2.1 Problem 1 : Metal Oxide Semiconductor Field Effect
Transistors (MOSFET)
1. Explain the differences between an enhanced and depletion MOSFET.

2. Explain the differences between an NMOS and PMOS transistor.

8.2.2 Problem 2 : MOSFET as Amplifier

Following common source amplifier circuits is given:

R1 R_D
1M00 6K00

D
V_DD
G
S 10V

R2 R_S
1M00 6k00

It is assumed that the transistor operates in saturation, so that the drain source
current can be described by:
W
IDS = µn CG (VGS − Vth )2 = k ∗ (VGS − Vth )2
2L
The prefactor k is given by k = 0.5 mA/V2 . Vth = 1 V

1. Determine the gate-source and drain-source voltage and the drain current for
the MOSFET amplifier.

2. Show that the MOSFET indeed operates in the saturation region.

80
8.2.3 Problem 3 : MOSFET as Switch
Determine the operating points of the MOSFET circuit shown.

R_D
125R

D
V_DD
G
S 10V
U_in
0 - 2.4V

The MOSFET is used as a switch. The input signal of the circuit varies between
0 V and 2.4 V. Determine the operating point for both input voltages.
Hint Use the output characteristic below to determine the operating point.

81
8.3 Execution Field Effect Transistor
8.3.1 Problem 1 : I/V Characteristic of a MOSFET
The purpose of this problem is to measure the current/voltage characteristics of a
NMOS Field Effect Transistor.

1. Use the following circuit to determine Uth .

R_D
50Ohm

A
+
250uA
2N7000

+
V_D
V
V_GS

Uth = UGS = UDS when ID = 250µ A. Measure and record Uth and ID .

2. Use the following circuit to measure the transfer characteristic.

R_D
50Ohm

+ A
+
I_D
2N7000
V
+ V_DS
V_D
V_GS V
V_GS

The gate source voltage should be scanned from 0 V to 3 V.

Ensure that the drain source voltage UDS is kept constant at 5 V while changing
UGS !!

3. Use the circuit from before and measure the output characteristic for gate
source voltages of 2 V, 2.2 V, 2.4 V, and 2.6 V. The drain source voltage should
be scanned from 0 V to 4 V.
Note: All important features of the current / voltage characteristic should be
captured: Off region, sub threshold region, linear region, saturation region.

82
8.3.2 Problem 2 : MOSFET as Amplifier
Goal of the problem is to design and realize an amplifier circuit using a MOSFET.

1. We want to use the following circuit:

R1 R_D
?? ??

V_out
C1
100nF V_DD
2N7000
10V

V_in
R2
sine f=1KHz ~ 100K
200mVpp

VGS = 2.7 V, VDS = 5 V, k = 72.2 mA/V2 , Uth = use measured value!

Determine the values for R1 and RD .

Note: It can be assumed that the gate source current is zero.

2. Assemble the circuit.

3. Apply a sinusoidal input signal with an amplitude of 100 mV and a frequency

of 1 KHz to the input of the circuit.

4. Take hard copies showing the input and the output signals and the phase
relation between them.

83
8.4 Evaluation
8.4.1 Problem 1 : I/V Characteristic of a MOSFET
1. Plot the measured transfer characteristic.

2. Plot the measured output characteristic for the different gate source voltages.

3. Insert the VDS = VGS − Vth line into the output characteristic.

8.4.2 Problem 2 : MOSFET as Amplifier

1. In which mode (linear or saturation) does the transistor operate during am-
plification? Provide an explanation.

2. If the amplitude of the sinusoidal input voltage is too large clipping of the
output voltage is observed. Determine the largest possible input voltage for
which no clipping is observed.

3. Provide a mathematical expression for the voltage gain (theoretical voltage

gain) of the circuit.

4. Determine the measured voltage gain and compare the measured voltage gain
with the theoretical voltage gain.

5. Explain the phase relation between the input and the output.

84
9. Experiment 6 : CMOS Inverter and
Logic Gates
9.1 Introduction to the Experiment
9.1.1 Objective of the Experiment
The objective of experiment 6 of the Electronics Lab course is to become familiar
with the characterization and simulation of CMOS inverters and simple logic gates.
The experiment includes the implementation of CMOS inverters and the character-
ization of voltage transfer curves (VTC). Furthermore, the propagation delay time
and the power dissipation of CMOS inverters will be analyzed. Finally, the behavior
of simple logic gates will be characterized and simulated.

9.1.2 Introduction
Any digital circuit can be reduced to basic building blocks. The simplest building
block in digital circuitry is a logic inverter. Therefore, the understanding of the
operating principle of inverters is essential for the analysis and the design of complex
digital circuitry. When the operation of an inverter is truly understood the results
can be extended to NAND and NOR gates or more complex logic circuits.
During this experiment we will introduce the basics of inverters and simple logic
gates. We will focus on complementary MOS or CMOS technology, as this tech-
nology is the standard technology in digital microelectronics. A major advantage
of CMOS technology is the low power dissipation, which makes the technology in-
teresting for very large-scale integration of electronics (VLSI) or ultra large-scale
integration of electronics (ULSI).

9.1.3 Theoretical Background

Fundamentals of CMOS Inverters
The basic CMOS inverter design is shown in Fig. 9.1(a). The circuit consists of two
matched enhancement type MOSFETs, one transistor (Qn ) is an NMOS transistor
and the other transistor (Qp ) is a PMOS transistor. As the bulk of the wafer and
the source electrode of the transistors are connected, the circuit can be simplified as
shown in Fig. 9.1(b). First we will discuss the circuit operation based on its extreme
cases, meaning a logical level of 0 or 1 is applied to the input of the inverter. The
logic level of 0 is in most of the cases associated with 0V , whereas a logic level of
1 corresponds to the operating voltage VDD . In both cases, we shall consider the
NMOS transistor (Qn ) to be the driving transistor and the PMOS transistor (Qp ) to
be the load. As the circuit is symmetric a definition of a load and a driver transistor
is not necessary, because the reverse definition would lead to the same results.

85
 The basic CMOS inverter design is shown in figure 3.1a. The circuit consists of two
matched enhancement type MOSFETs, one transistor (Qn) is an NMOS transistor
and the other transistor (Qp) is a PMOS transistor. As the bulk of the wafer and the
source electrode of the transistors are connected, the circuit can be simplified as
shown in figure 3.1b.

First we will discuss the circuit operation based on its extreme cases, meaning a
logical level of 0 or 1 is applied to the input of the inverter. The logic level of 0 is in
most of the cases associated with 0V, whereas a logic level of 1 corresponds to the
operating voltage VDD. In both cases, we shall consider the NMOS transistor (Qn) to
be the driving transistor and the PMOS transistor (Q p) to be the load. As the circuit is
Fig. 3.1: (a) CMOS inverter circuit and (b) simplified circuit description
symmetric a definition of a load and a driver transistor is not necessary, because the
Figure 9.1: (a) CMOS inverter circuit and (b) simplified circuit description
reverse definition would lead to the same results.
Figure 3.2 illustrates the behavior of an inverter for a logic 1 signal applied to the
Figure
input of9.2the
illustrates
inverter.the Thebehavior
operatingof an inverter
point for a logic 1 signal applied to the
4 can be determined by imposing the output
input
curves of of
thetheinverter. The operating
two transistors. As thepoint
inputcan be determined
voltage is V DD thebyvoltage
imposing VGSthefor the
output curves of the two transistors. As the input
PMOS transistor (Qp) is getting 0V. As the transistor Qp DD voltage is V the voltage
is an enhanced VGSPMOS
for the PMOS
transistor transistor
the drain (Qpis
current ) is getting
almost 0V .AsAsa the
zero. transistor Q
consequence p is
the an enhanced
current (i) is getting
PMOS transistor the drain current is almost zero. As a consequence
zero as well. The NMOS transistor behaves differently. The voltage VGS is equal the current (i) to
isVgetting
DD and zero
the as well. The
transistor NMOS
turns on.transistor
As the behaves
operatingdifferently.
point isThe voltage
determined VGSby the
isintersection
equal to VDD of the
andtwo
the imposing
transistoroutput curves
turns on. of the
As the transistors
operating point theis output voltage of
determined
bythethe
overall circuit gets
intersection of theclose
two to zero. output curves of the transistors the output
imposing
voltage of the overall circuit gets close to zero.

Figure 9.2: Operation of a CMOS inverter. The operating voltage VDD (logical 1)
isFig. 3.2: to
applied Operation
the inputofofathe
CMOS inverter.
inverter. The operating
A graphical voltage
construction VDDoperating
of the (logical 1) is
applied
point to the The
is shown. inputinverter
of the inverter. A graphical
can be described construction
by the of the circuit
simple equivalent operating point is
shown
shown. The
on the right [3].inverter can be described by the simple equivalent circuit shown on the
right [3].
The other extreme case is shown in Fig. 9.3. The input voltage is now 0V . In this
case the NMOS transistor is turned off as the voltage VGS is getting zero. Hence,
The other extreme case is shown in figure 3.3. The input voltage is now 0V. In this
the output
case curve istransistor
the NMOS almost a is
straight
turnedline
off and thevoltage
as the currentVlevelisisgetting
close tozero.
zero.Hence,
The the
GS
PMOS transistor, however, is turned on, as the
output curve is almost a straight line and the currentvoltage V is getting V
GS level is close . In this The
DD to zero.
case
PMOSthe transistor,
operationalhowever,
voltage is is
getting
turnedclose
on,toasVDD
the. voltage VGS is getting VDD. In this
Note: The
case the fact that the
operational current
voltage flow throughout
is getting close to VDDstatic
. operation is close to zero

86
Note: The fact that the current flow throughout static operation is close to zero
makes CMOS technology so attractive for microelectronics. As always one transistor
is in the off state the current flow through the circuit is close to zero and the power
dissipation is very low.
makes CMOS technology so attractive for microelectronics. As always one transistor
is in the off state the current flow through the circuit is close to zero and the power
dissipation is very low.

Fig. 3.3:
Figure 9.3: Operation
Operation of of aa CMOS
CMOSinverter.
inverter.The
Theoperating
operating voltage
voltage 0V (logical
0V (logical 0) is 0) is
appliedtotothe
applied theinput
inputofofthe
theinverter.
inverter.AAgraphical
graphical construction
construction of of
thethe operating
operating point is
point
is shown. The inverter can be described by the simple equivalent circuit shown onon the
shown. The inverter can be described by the simple equivalent circuit shown
right
the [3]. [3].
right

Based on the above described device behavior we can conclude the ideal behavior
of the CMOS inverter:
1. The output levels should either be 0V or VDD. As a consequence the signal
swing between the two levels is maximized.
2. The static power dissipation of an inverter is close to zero, if the leakage
current of the transistors is negligible. As a CMOS inverter is symmetric the
power dissipation is independent of the logical output state.
3. A low resistance path exists between the output terminal and ground (in the 0
state) or VDD (in the 1 state). The low resistance path ensures that the output
voltage is independent of the transistor dimensions. As we use identical
transistors for the driver and the load of the CMOS inverter a change of the
dimensions of the MOSFETs has no impact on the output voltage of the inverter.
4. The input resistance of the inverter is infinite, because the input current is
close to zero. Thus a large number of similar inverters can be driven with no loss
of the signal level.

Static Behavior and Power Dissipation

In order to compare the static behavior of different inverters the voltage transfer
characteristic (VTC) is used. The voltage transfer characteristic (VTC) shown in
figure 5.4 can be seen as a measure for performance of an inverter.
Where,
VOH: The minimum voltage that will be available at the inverter output when the
output is supposed to be logic 1(high).
VOL: The maximum voltage that will87 be available at the inverter output when the
output is supposed to be logic 0 (low).
Based on the above described device behavior we can conclude the ideal behavior
of the CMOS inverter:
1. The output levels should either be 0V or VDD . As a consequence the signal
swing between the two levels is maximized.
2. The static power dissipation of an inverter is close to zero, if the leakage current
of the transistors is negligible. As a CMOS inverter is symmetric the power
dissipation is independent of the logical output state.
3. A low resistance path exists between the output terminal and ground (in the
0 state) or VDD (in the 1 state). The low resistance path ensures that the
output voltage is independent of the transistor dimensions. As we use identical
transistors for the driver and the load of the CMOS inverter a change of the
dimensions of the MOSFETs has no impact on the output voltage of the
inverter.
4. The input resistance of the inverter is infinite, because the input current is
close to zero. Thus a large number of similar inverters can be driven with no
loss of the signal level.

Static Behavior and Power Dissipation

In order to compare the static behavior of different inverters the voltage transfer
characteristic (VTC) is used. The voltage transfer characteristic shown in Fig. 9.4
can be seen as a measure for performance of an inverter.
Vout
VOH - the minimum output voltage
Vmax
VOH which indicates a logic 1
Slope  1
VOL - the maximum output voltage
which indicates a logic 0

Slope  1 VIH - the minimum input voltage to

output a logic 0
VM

Slope  1
VIL - the maximum input voltage
to output a logic 1
NML NMH
N ML - Noise Margin for low input
VOL
Vmin
voltage VIL − VOH
Vin
0
VIL VM VIH VDD N MH - Noise Margin for high input
voltage VIH − VOL
Figure 9.4: Voltage transfer characteristic
VM - the voltage at which the input
(VTC) of a CMOS inverter. Qn and Qp
and output voltages are equal
are matched [3].

The VTC describes the transition from the off to the on state (or vice versa) of an
inverter as a function of the input voltage. The voltage transfer characteristic can

88
be deduced by imposing the output curves of the two transistors. The transition
from the on to the off states and vice versa should be as sharp as possible. The
slope of the curve is a measure of the inverter performance. The slope should be as
high as possible.
The fact that the output voltage of a CMOS inverter (in the on as well as in the off
state) is independent of the device dimensions (assuming a symmetric inverter with
identical NMOS and PMOS transistors) makes CMOS inverter technology different
from other MOS based inverter technologies, where only NMOS or PMOS transistors
are used to realize an inverter.
The static power dissipation (power dissipation while the circuit is in a static or
steady state) of a CMOS inverter is negligible as always one of the two transistors is
in the off state. The dissipation is independent of the input state of the inverter. The
static power dissipation of CMOS inverters is distinctly lower than the dissipation of
alternative inverter circuits (e.g. NMOS enhanced or depletion mode load inverters).

Dynamic Behavior and Power Dissipation

While switching the inverter from one state to another state a current is flowing
through the two transistors. In this case none of the two transistors is turned off for
a short period of time. The power dissipation of an inverter while switching is called
dynamic power dissipation. The power dissipation is maximized for Vi = VDD /2.
Another significant component of dynamic power dissipation results from the current
that flows in Qn and Qp when the inverter is loaded by a capacitor C. The capacitive
load represents the input capacitance of another logic gate or the capacitance of a
wire connected to the output of the inverter.
The dynamic operation of a capacitive loaded CMOS inverter is shown in Fig. 9.5.
The transient response of an inverter is comparable with the transient response of
an RC circuit. The RC circuit is formed by the load capacitance and the channel
resistance of the transistor in the on state. An equivalent circuit of the CMOS
inverter during the discharge of the capacitor is shown in Fig. 9.5(d). During the
discharge, C will discharge through the channel resistance of the NMOS transistor,
thus power is dissipated. As the static power dissipation of digital electronic circuits
is almost zero, the power dissipation is limited by the dynamic power dissipation.
The dynamic power dissipation can be determined by:

2
PD = f ∗ C ∗ VDD (9.1)

where f is the switching frequency, C is the load capacitance and VDD is the supply
voltage.

89
Fig. 3.5: Dynamic operation of a capacitive loaded CMOS inverter (a) circuit, (b) input
Figure 9.5:waveforms,
and output Dynamic (c)
operation
trajectoryof
of athecapacitive loaded
operating point CMOS
as the input inverter
goes high(a)
andcircuit,
C discharges
(b) input andthrough
outputQn, (d) equivalent
waveforms, (c)circuit during of
trajectory thethe
capacitor discharge.
operating point as the input
goes high and C discharges through Qn , (d) equivalent circuit during the capacitor
discharge.

It can be followed from Eq. (9.1) that the power dissipation can be minimizing by
Dynamic Behavior Evaluation
reducing C. It is an even more effective strategy to reduce the operating voltages
of Ring oscillators
the digital are typically
circuit. Based used
on Eq.to determine
(9.1) it isthe propagation
getting evidentdelay
whyofmicroelectronic
inverters.
Ring oscillators can be realized by a serial connection of several stages of inverters.
manufactures try to reduce the operating voltage of their circuits.
The ring oscillator is triggered by a voltage pulse, which is applied to one of the
Hint: Forstages.
inverter more information onthe
In the following tP HL and
pulse tP LH , you
propagates canone
from check the toCD4007C
inverter the next Dual
Complementary
inverter. Based Pair Plus
on the Inverter
transient data sheet
response of theon ring
the oscillator
course homepage.
the delay of an
individual inverter stage can be determined.
The delay Behavior
Dynamic time of the inverter can be determined by:
Evaluation
Ring 1
t d =oscillators are typically used to determine the propagation delay of inverters.
(3.2)
2⋅ N⋅f
Ring oscillators can be realized by a serial connection of several stages of inverters.
The ring oscillator is triggered by a voltage pulse, which is applied to one of the
where f is the oscillating frequency of the ring oscillator and N the number of inverter
inverter
stages.stages. In the following the pulse propagates from one inverter to the next
inverter. Based on the transient response of the ring oscillator the delay of an
9
individual inverter stage can be determined by
1
td = (9.2)
2∗N ∗f
where f is the oscillating frequency of the ring oscillator and N the number of inverter
stages.

90
A simple ring oscillator based on three inverters is shown in Fig. 9.6. Since
the circuit is symmetric the rise and the fall time of the inverters are identi-
cal. The dynamic behavior
of the inverters defines the
M1 M3 M5
oscillation frequency of the
circuit. The most important
V DD
factors are the input capaci- M2 M4 M6
tance of the driver transistor
and the channel resistance of
the load transistor. With
increasing input capacitance Figure 9.6: 3-stage ring oscillator based CMOS inverters
and/or increasing channel resistance of the load the time constant is increased to
switch the inverter. To increase the oscillation frequency the input capacitance
should be reduced. As the power dissipation increased with the switching frequency
and the delay time decreases with the switching frequency we can define a ”Power
delay product”. The power delay product of an inverter is typical constant. An
increase of the switching time can only be accomplished by an increase of the power
dissipation.

Logic Gates
Inverters are elementary components of digital logic circuits. All circuits can be
reduced to simple inverter circuits. In the following the knowledge on CMOS invert-
ers will be used to design simple logic CMOS circuits. We will concentrate here on
basic structure, where the output signal is a direct combination of the input signals.
Memory elements will not be taken into account.
In general, a CMOS inverter can be described by a NMOS pull-down transistor and
a PMOS pull-up transistor, which operate in a complementary fashion. We will
now apply the pull-up and pull-down concept to logical gates with more than one
input signals. Therefore, we define two networks, a pull-down network (PDN) and
a pull-up network (PUN). The networks operate in a complementary fashion. A
schematic sketch of a pull-up and pull-down circuit is shown in Fig. 9.7.
Let us assume that we want to realize a logic gate with three input signals. As
a consequence, both networks (pull-up and the pull-down network) will have three
input signals. The number of output states is still two (0 and 1). The pull-down
network is able to pull down the output signal for all negative or low states. The
opposite applies for the pull-up network. The network is able to pull-up the output
signals for all positive or high states.
Since the PDN comprises of NMOS transistors and the NMOS transistors conduct
when the input signals is high, the PDN is active when the input signals are high.
In a complementary manner, the PUN comprises PMOS transistors and PMOS
transistors conduct when the input signal is low. Therefore, the PUN is active for
low input signals. Based on this scheme we can deduce the operation of logic gates
like OR, AND, NOR, or NAND.

91
Fig.Figure 9.7: Basic
3.7: Basic implementation
implementation of a digital
of a digital logiclogic
gategate by using
by using pull-up
pull-up andand a pull-
a pull-down
down circuit
circuit.

The implementation of a NOR gate is shown in Fig. 9.8. The NOR gate can be
Letdescribed
us assume thatfollowing
by the we wantequation:
to realize a logic gate with three input signals. As a
consequence,
′
both networks (pull-up and the pull-down network) will have three
input Ysignals.
= A + The B number of output states is still two (0 and 1). The pull-down (9.3)
network is ablesignals
The output to pullgetdownlow iftheone
output
of thesignal
input for all negative
signals gets high.or low
The states. The
circuit in
opposite applies for the pull-up network. The network is able to
Fig. 9.8 can be described as follows. If A or B or both signals gets high one or two pull-up the output
signals
of theforNMOSall positive or highpulls
transistors states.
the output signal down. At the same time one or
both of the PMOS transistors
Since the PDN comprises of NMOS are in the off state,and
transistors so that
the the output
NMOS signal gets
transistors low.
conduct
when
ThetheNAND inputgate
signals is high,
in Fig. the be
9.9 can PDN is active
described bywhen the input signals are high. In a
complementary manner, the PUN comprises PMOS transistors and PMOS
Y ′ = AB (9.4)
transistors conduct when the input signal is low. Therefore, the PUN is active for low
input
Thesignals.
output Based
signalson getthis
lowscheme
if both we caninput
of the deduce the operation
signals get high. ofIn logic
termsgates like
of the
OR, AND,inNOR,
circuit or NAND.
Fig. 9.9 it can be described as follows. If A and B signals gets high both
TheNMOS transistors of
implementation pulls
a NORthe output
gate issignal
shown down. At the
in figure 3.8.same
The time
NORboth gateofcan
thebe
PMOS transistors
described are in equation:
by the following the off state, so that the output signal gets low.

Y'=A+B
9.1.4 Definitions and Practical Hints (3.3)

The output signals

Designing logic get low if one of the input signals gets high. The circuit in figure
circuits
5.8 can be described as follows. If A or B or both signals gets high one or two of the
In logic
PMOS circuits, pulls
transistors a logicthegate drives
output another
signal down.gate. In order
At the sametotime
ensure
onethat the logic
or both of the
output level of a gate is high enough to drive another logic
NMOS transistors are in the off state, so that the output signal gets low. gate a certain safety
margin is needed. In the case of an output high the safety margin is defined by
The NAND gate in figure 3.9 can be described by
the difference N MH = VOH − VIH , where VOH , is the minimum allowed level of the
output signal of a gate and VIH minimum required input level of the next gate.
Y'=AB (3.4)The
complementary situation applies for the minimum required safety margin of logic
The output
low. Heresignals get low ifis both
the difference of the input
represented by Nsignals
ML = Vget IL −
high.
VOLIn terms VofOLthe
, where , is circuit
the
in figure
maximum5.9 itallowed
can belevel
described
of the as follows.
output If A
signal of and B signals
a gate and VILgets high both
minimum PMOS
required
transistors pulls the output
input level of the next gate. signal down. At the same time both of the NMOS
transistors are in the off state, so that the output signal gets low.
92
11
 A

A B Out
B
0 0 1 VDD
0 1 0 Out
1 0 0
1 1 0

Figure 9.8: Implementation of an NOR logical gate with two inputs

A B Out
0 0 1 VDD
0 1 1 Out
1 0 1
A
1 1 0
B

Figure 9.9: Implementation of an NAND logical gate with two inputs

9.1.5 References
1. A.S. Sedra, K.C. Smith, Microelectronic Circuits, Oxford University Press
(1998)

2. J. Keown, ORCAD PSpice and Circuit Analysis, Prentice Hall Press (2001)

3. P. Horowitz, W. Hill, The Art of Electronics, Cambridge University Press

(1989).

93
9.2 Prelab CMOS Inverters and Logic Gates
9.2.1 Problem 1 : Voltage Transfer Characteristic of a CMOS
inverter
Simulate the voltage transfer characteristic of a CMOS inverter.

V_DD
Vin Vout
5V

Note: Use the ’MbreakN’ device model for the NMOS transistor and the ’MbreakP’
device model for the PMOS transistor from the supplied library. These are the device
models for the MOSFETs in the CD4007.
1. Use 5V for the power supply VDD . Simulate the voltage transfer curve (VTC)
of the CMOS inverter and extract the values of VOH , VOL , VIH , VIL , N ML ,
N MH , and Vth .
Hint: Use the d() function of LTSpice to determine VIH , VIL !!

2. Simulate the current flowing through the inverter as a function of the input
voltage.

3. For what input level the current reaches its maximum. Provide an explanation.

9.2.2 Problem 2 : CMOS Inverter with Capacitive Load

The propagation delay per logical gate is important to realize fast digital circuits. In
this problem the propagation delay of a single inverter stage should be determined.
However, the propagation delay can only be determined if the output of inverter
is used as an input signal for a subsequent logical gate. Therefore, the subsequent
logical gate acts as load for the inverter. The load of the subsequent logical gate is
determined by the gate capacitance of the input transistors of the subsequent logical
gate. We will approximate the load by a simple load capacitor.

V_DD
Vin Vout
5V

C_L

1. The capacitive load should be varied from 25 pF to 100 pF in 25 pF steps.

Determine the propagation delay (tP LH = tP HL ) if the input signal is given

94
 by a 1 KHz square wave with a 20 ns rise and fall time. Use 5 V for the power
supply VDD .

2. Obtain the dynamic power dissipation of the CMOS inverter for the different
load capacitors.

9.2.3 Problem 3 : Propagation Delay of an Inverter Stage

Implement the following 3-stage ring oscillator in the simulator.

Initial Condition V_DD

1 5V

1. Determine the oscillation frequency of the ring oscillator and the propagation
delay per inverter stage for supply voltages of 3 V, 5 V, 7 V and 10 V, respec-
tively.
Note: It might be necessary to apply a single pulse to the input of the ring os-
cillator to start it! Instead of a pulse you also can use the ’.ic [V(<node>)=<voltage>]’
command from LTSpice. See the help!

2. Calculate the dynamic power dissipation per inverter stage for the different
supply voltages.

3. Add a 50pF load capacitor to each inverter of the 3-stage ring oscillator and
measure the oscillation frequency and determine the propagation delay per
inverter for a power supply of VDD = 5.0 V

4. What is the effect of the capacitive load on the propagation delay and the
oscillation frequency?

5. What is the effect of the capacitive load and the power supply on the power
dissipation?

95
9.3 Execution CMOS Inverters and Logic Gates
9.3.1 Problem 1 : Voltage transfer characteristic of an In-
verter
The voltage transfer curve (VTC) vO = f (vI ) of a CMOS inverter should be mea-
sured and displayed. Use a part of the CD4007 MOSFETs array to implement the
CMOS inverter circuit shown below.

V_DD
Vin Vout
5V

To display the VTC we need two steps. In the lab first we measure Vin and Vout for
one switch-on event. In the second step in the evaluation MatLab is used to display
and measure the VTC parameters.
• Generate a ramp signal with 0 to 5V and f = 1 KHz. Check that the waveform
is correct before applying it to the inverter.
• Connect the input of the inverter to Channel 1 and the output to Channel 2.
Show one Vin ramp together with Vout on the screen! Use the measure function
to determine the properties of the signals.
• Take a hardcopy. Take care that you not only got the picture, but also the
complete data set for Ch1 and Ch2 (the *.CSV files)!
Note: The CD4007 chip can be easily damaged. In general, the following precau-
tions have to be considered.
• Do not touch pins. Discharge the static charge on your body, before touching
the chip, by touching a metal part of the workbench.
• Implement the circuit while having the power supply switched off. Check
polarity of the supply voltage at the circuit carefully before switching on !

96
9.3.2 Problem 2 : Propagation Delay of an Inverter
An important characteristic of a CMOS inverter is its propagation delay. The 3-
stage ring oscillator in figure below will be used to determine the propagation delay
time of an inverter stage. Use the CD4007 MOSFETs array to implement the ring
oscillator. Use 3V for the power supply VDD and connect VSS to ground.

V_DD
5V

Note: The initial condition used in the PSpice simulations is not required.
Connect the oscilloscope to the input and the corresponding output of the first
inverter.
Note: The propagation delay determined by this method is not very accurate, as
the probe capacitance has an influence on the measurement. To minimize the effect,
the 10x high impedance probe should be used in the measurement.

1. Measure the oscillation frequency and propagation delay tP LH and tP HL of

the first inverter at 3V, 5V, 7V, and 10V. Take hard copies for the different
measurements!

2. Add load capacitors to each of the three output nodes of the 3-stage ring
oscillator. The load capacitors should have a capacitance value of 1.5nF .

3. Measure the oscillation frequency and the propagation delay tP LH , tP HL for

the first inverter at VDD = 5V .

97
9.4 Evaluation
9.4.1 Problem 1 : Voltage transfer characteristic of an In-
verter
1. Show the implemented circuit with all pin numbers!

2. Use the taken values for Vin and Vout from the oscilloscope and draw the VTC
using MatLab.

3. Extract the parameters VOH , VOL , VIH , VIL , N ML , N MH and VM (see 9.4
from handout) from the MatLab plot using the cursors from the plot window.
Compare the real values to the values from the simulation.

4. Correlate the five regions of operation of the inverter with the regions of oper-
ation of the transistor (cutoff, linear or saturation). The modes of operation
should be stated for the NMOS and PMOS transistor for each of the five
inverter modes of operation.

9.4.2 Problem 2 : Propagation Delay of an Inverter

1. Show the implemented circuit with all pin numbers!

2. Calculate the propagation delay per inverter for each of the supply voltages.

3. Determine the dynamic power consumption per inverter stage for the different
supply voltages.

4. Determine the propagation delay, and the power consumption per inverter
stage after adding the additional load capacitors.

5. Is it possible to use even number of inverters to implement a ring oscillator?

Explain.

98
 Part III

Additional Information

99
A. Appendix
A.1 Hardcopy from oscilloscope screen
For the documentation and evaluation of an experiment it is useful to save the data
from the oscilloscope screen. This is possible with the help of a printer, a computer
or an USB stick.
The TBS series oscilloscope in the laboratory has a USB interface. Insert a USB
stick into the socket on the front panel. To get a hardcopy and the data press the
button with the floppy disk symbol. Do not forget to save the recorded data from
the stick to your computer at the end of the course.

A.2 Books and other Tools

A.2.1 Book
ˆ Sarma

ˆ Floyd

A.2.2 Programs
LTSpice
LTSpice is a powerful and unrestricted circuit simulator for analog circuits. It con-
tains a graphical user interface for entering circuit diagrams and a waveform viewer
for displaying the results. It is freely available for Windows, Mac and with an
emulator also for Linux. Download link is ’from Analog Devices’.

Octave
GNU Octave is a high-level programming language intended for numerical com-
putations. It is typically used for such problems as solving linear and nonlinear
equations, numerical linear algebra, statistical analysis, and for performing other
numerical experiments. It may also be used as a batch-oriented language for auto-
mated data processing. It is freely available for Windows, Mac, and Linux. Octave
has been built with MATLAB compatibility in mind, and shares many features with
MATLAB. Octave is available from ’https://octave.org/’.

KiCad
KiCad is an open-source software suite for creating electronic circuit schematics,
printed circuit boards (PCBs), and associated part descriptions. KiCad supports
an integrated design workflow in which a schematic and corresponding PCB are
designed together, as well as standalone workflows for special uses. KiCad also

100
includes several utilities to help with circuit and PCB design, including a PCB
calculator for determining electrical properties of circuit structures, a Gerber viewer
for inspecting manufacturing files, a 3D viewer for visualizing the finished PCB, and
an integrated SPICE simulator for inspecting circuit behavior. It is freely available
for Windows, Mac, and Linux from ’https://www.kicad.org’.

MatLab
MATLAB (an abbreviation of ”MATrix LABoratory”) is a proprietary multi-paradigm
programming language and numeric computing environment developed by Math-
Works. MATLAB allows matrix manipulations, plotting of functions and data,
implementation of algorithms, creation of user interfaces, and interfacing with pro-
grams written in other languages. It is available for Windows, Mac, and Linux. As
registered student you may download it and use the university based license.

101