Tessent® Scan and ATPG

Lab
Troubleshooting Low Coverage

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 Table of Contents
Before you Begin ......................................................................................................4

Lab Troubleshooting Low Coverage......................................................................6

Introduction ............................................................................................................6
Objectives...............................................................................................................6
Exercise 1: Troubleshooting Low Test Coverage .................................................7

Appendix: Answers to Questions ..........................................................................24

Exercise 1 .............................................................................................................24
 Before you Begin

If this is the first time you are launching this VM (Virtual Machine), you must
download and extract the lab data as described in the "Obtaining Lab Data
Caution
section below.

Whenever you are using the VM for lab exercises and are finished with your
session, please use the "Disconnect" feature of the Desktop Viewer before the
VM times out to preserve the data from one session to the next. Failure to do
so will remove the VM, and its contents.

If the VM was removed, you will be presented with a new VM requiring you
to follow the download and extract process. This allows you to "refresh" the
lab data so you can go through the labs again with a new database.

Setting Environment Variables

The environment uses bash and is ready to use for the labs with all needed
environment variables already setup.

Obtaining Lab Data

If the atpg_data directory, with lab subdirectories, is located in the home

directory (e.g. cd ~), please proceed to the lab exercises as you have already set
up the lab database on this VM.

If this is the first time you are starting a session for this VM, the atpg_data
directory will not be in the home directory and you will need to download and
extract it using the following instructions.

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 1. Double click on the Desktop icon Download_lab_data, . This launches a
web browser.

2. On the resulting web page, select the file named

tessent_atpg_data_v2020.1_20200611.tgz,

3. In the resultant window, select the Download button, enable the Save File
button, then select the OK button to download the file.

Move the file in the Downloads directory to the home directory. If you are using
the terminal (Applications>Favorites>Terminal) you can use the following
command:

mv ./Downloads/tessent_atpg_data_v2020.1_20200611.tgz .

4. In a terminal window, extract the files from the compressed tar file using the
command:

tar xzvf ./tessent_atpg_data_v2020.1_20200611.tgz

You should now have a directory named atpg_data in your $HOME directory.
That directory contains all the files you need to perform the exercises, in this
learning path.

You are now ready to proceed with lab exercises.

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 Lab
Troubleshooting Low Coverage

Introduction
In this lab you learn how to troubleshoot areas of low test coverage.

In exercise 1 you troubleshoot areas of low test coverage by determining why

some faults are identified as ATPG untestable, as well as other faults that cause
coverage problems. Some of the problems are caused by DRCs.

Objectives
Upon completing this lab, you should be able to:
 Identify blocks of low test coverage
 Determine untestable fault classifications
 Determine the cause of ATPG Untestable (AU) faults
 Use Tessent Visualizer to debug faults
 Use report_test_stimulus to display the test set stimulus

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 Troubleshooting Low Coverage

Exercise 1: Troubleshooting Low Test Coverage

Setup Instructions
1. Log in to your workstation if you are not already logged in.
2. Change to the $ATPG_LABS/Lab10/Exercise1 directory.
shell> cd $ATPG_LABS/Lab10/Exercise1

Identify and Black Box Undefined Modules

1. Use the following command to invoke Tessent Shell using the run script
provided:
shell> generate_patterns_step1

Notice that the script starts Tessent Shell. All chains and clocks are defined
and the tool remains in SETUP mode.

The following files are used by the script:

Design: design/gate_scan_8.v

Libraries: ../../libs/adk.atpg, ../../libs/picdram/picdram.tcelllib

Dofile: setup_tessent_shell_broken.do

Log file: logs/ex_1.log

Based on the warning messages, which module(s) should be defined as black

boxes? _______________________________________________________

2. Black box the undefined modules.

SETUP> add_black_boxes -auto

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 Troubleshooting Low Coverage

Examine ATPG Untestable (AU) Faults

1. Run design rules.
SETUP> check_design_rules

2. Report faults in the design.

ANALYSIS> add_faults -all
ANALYSIS> report_statistics (Note the total number of faults.)
ANALYSIS> delete_faults –all

3. Load a subset of the faults from the fs_sample_faults.flt file.

ANALYSIS> read_faults design/fs_sample_faults.flt –retain

4. After the faults are loaded, report statistics before you create patterns.
ANALYSIS> report_statistics

Note that out of 10387 faults, 9845 are classified as UC (uncontrolled).

While several other faults are classified (DI, TI, and BL) most of the faults
at this point are classified as UC.

5. Generate test patterns using the current settings.

ANALYSIS> create_patterns

6. Review the pattern generation statistics.

The total number of AU faults, broken down into black boxes and
unclassified is: BB___________ SEQ _______ Unclassified __________

The total number of UC + UO faults are ____________________________

The total test coverage for the design is _____________________________

The total fault coverage for the design is ____________________________

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 Troubleshooting Low Coverage

7. Open the Tessent Visualizer (open_visualizer) and open the Instance

Browser. Add the Test Coverage information to the Instance tab if it is
not shown already.

From the Columns and Filter Editors button , expand the Fault
Statistics, select “Test Coverage”, “Fault Coverage” and any specific
fault that you need to add, like the DS and UO faults – Click OK

Double click on “bigchip” and then find and double click “p1”. Notice
that the module “fpu1” has a test coverage less than 82%. This is a good
place to start the investigation.

8. Report statistics for the fpu1 instance.

ANALYSIS> report_statistics -Instance /p1/fpu1

You have identified that /p1/fpu1 is reporting low test coverage. The
following steps show you one way of determining a solution to low test
coverage.

9. Create the AU fault list for instance /p1/fpu1.

ANALYSIS> report_faults -class au /p1/fpu1 > results/fpu1_au

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 Troubleshooting Low Coverage

A file that contains the AU classified faults in /p1/fpu1 is now on disk.

Review this list.

10. Investigate a fault from the list.

a. For this exercise, you will investigate /p1/fpu1/U2694/A1. Use the

analyze_fault command to investigate the fault.

The analyze_fault command identifies why a fault is not detected.

From the Tessent Shell Reference Manual, the following usage is one
way to investigate a stuck-at fault:

analyze_fault <pathname_to_fault> -stuck_at 1

(or -stuck_at 0)

Refer to the Tessent Shell Reference Manual for other analyze_fault

command usages.

ANALYSIS> analyze_fault /p1/fpu1/U2694/A1 -stuck_at 1

Look at the transcript window and answer the following questions:

Is the fault controllable? _____________

Is the fault observable? ______________

What parallel pattern number successfully controls the fault site? ______

What is the pattern type for the controlling pattern? _________________

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 Troubleshooting Low Coverage

What are some of the testing issues that can make a fault
Atpg_Untestable?____________________________________________

This fault is controllable but not observable, or the observation is very

difficult to determine. Further analysis is needed.

Graphically Analyze AU Faults

1. Analyze the fault again, and add the instance to the Flat Schematic
window.
ANALYSIS> analyze_fault /p1/fpu1/U2694/A1 -stuck_at 1 \
-display

When debugging coverage and DRC issues, it is usually best to view the
Flat Schematic which shows the ATPG primitives in the schematic.

2. Now, add the fault classifications to the schematic.

From Settings > Gate Report, select “Fault Status”, click OK

Figure 10-1. Graphically Displaying the Fault in the Debug Window

Notice that most of the pins have F-F on their inputs and outputs, except for
F-AU on the A1 pin. The F classification denotes that it could be a fault site,

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 Troubleshooting Low Coverage

but it is not in the current fault list. In other words, the fault site has not been
added for testing.

3. Remember that when <value>-<value> is displayed, this is showing SA0-

SA1.

4. Recall from fault analysis that the fault was controllable by setting the
fault site to 0 using parallel_pattern 0. Set the gate report to display results
of parallel pattern 0.

a. Select Settings > Gate Report, This action loads the Gate Report
Settings dialog box.

b. Check the Parallel Pattern option and enter 0 (zero) and click OK.

Figure 10-2. Output for Parallel Pattern 0

The ATPG tool uses a zero delay simulator, so as soon as the clock pulses,
all outputs update. Notice that the value on the A1 input is 0XX. These three
values represent the state before the leading edge, the state after the leading
edge, and the state after the trailing edge of the clock. Parallel pattern 0 sets

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 Troubleshooting Low Coverage

the fault site to the controlling value (0) before the leading edge of the clock.
Since that was successful, you are not concerned with the other two clock
frames, and they are reported as Xs (or don’t cares).

5. Trace back to the sequential gate that is driving A1 by clicking on A1 with

the RMB and select “Trace Backward”.

Figure 10-3. DFF and NAND Gate in Flat Schematic

6. Click the Zoom All button to zoom out.

7. Determine if the DFF is part of the primitive model for a Scan Flip Flop.
Select the DFF and <cntl>R. This issues the command report_gates
for the DFF.
Is this a part of a scan cell? _______________________
What is it’s cell ID and which chain is it connected to?
________________
We now know that A1 is controllable, since it is directly connected to a
scan cell.

8. Now trace back on A0 of NAND gate U2694. Notice that it is also

connected to a DFF for a scan cell. If you use the analyze_fault
command for NAND gate pin /p1/fpu1/U2694/A0 for stuck-at 0 or 1, you

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 Troubleshooting Low Coverage

find that this fault site can be controlled and observed separately, but
cannot be detected when combining both conditions.

Figure 10-4. Connections to A0

Controllin a Pin to a Set Value

Using the report_test_stimulus -Set <gate_id> {0|1|Z} -store

command provides a way to determine if ATPG can set specific pins to specific
values. In this case, this allows you to determine if ATPG can control both
instances driving the inputs of the NAND gate.

1. Delete the current pattern set from memory and clear the parallel pattern
buffer.
ANALYSIS> reset_state

2. Using the IDs of the gates driving the NAND gate, set A1 to 0 and A0 to
1. A1 needs to be 0 to test for stuck-at-1 fault. A0 needs to be 1 to
propagate the fault to an observation point.

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 Troubleshooting Low Coverage

ANALYSIS> report_test_stimulus -set <gate ID of gate \

driving A0> 1 -set <gate ID of gate driving A1> 0 -store

What do you observe in the transcript window? ______________________

_____________________________________________________________

This indicates that the issue of propagation (Observation) is based on not

being able to set A1=0 and A0=1 in the same pattern. Let’s test that
assumption before we change the design.

Debugging Observation Issues

Using add_primary_inputs, input constraints, and creating a fault list of just A1

stuck_at 1, we will continue the investigation.

1. Create a fault list for just U2694/A1 stuck at one. Select the A1 Pin and
RMB. Notice that the last line of the menu has the “Copy hierarchical name”.
Click on that line so the path is in your paste buffer.

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 Troubleshooting Low Coverage

2. Create a file that contains the fault list for just A1. Remember, you can
“paste” the pathname.
ANALYSIS> write_faults debugA1_stuck.flist \
/p1/fpu1/U2694/A1 -stuck 1 –replace

3. Now, define A0 as an internal primary input that you want to control

during test pattern generation.

a. First go to setup mode.

ANALYSIS> set_system_mode setup

b. As you did in the previous step, copy the pathname to A0.

c. Using the add_primary_inputs command, define A0 as an internal

primary input, and assign it a pseudo port name that you can use for
constraining.
SETUP> add_primary_inputs /p1/fpu1/U2694/A0 \

-internal -pseudo_port_name debugA1

d. Now constrain debugA1 to a 1, so we can test propagation.

SETUP> add_input_constraints debugA1 -c1

4. Now run design rules checks and read the fault list debugA1.flist
a. Check design rules
SETUP> check_design_rules

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 Troubleshooting Low Coverage

b. Read the fault list. Note, that when we wrote the fault list, A1 was
classified as an AU fault. When we read the fault list, it will be
reclassified as a UC. For this case, this is desired. If you wish to
keep the existing classifications (For example, your fault list as DS
classifications) you can use the -retain switch.

ANALYSIS> read_faults debugA1_stuck.flist

5. Create Patterns, and as expected the A1 fault has been classified as an AU

fault.

6. As you did earlier in the lab, analyze the fault using the -display switch.
Note: You can have the system report the pin pathname by using
report_faults.

7. Add the parallel pattern to the display if it is not already there. (Note: use
the history command to show the previously executed commands.)

8. Using the -observe switch for analyze_faults, you can determine

where the fault is propagating. Use the GateID of the instance where you
wish to verify observation. Verify that the fault is propagating through the
NAND gate.

ANALYSIS> analyze_fault /p1/fpu1/U2694/A1 -stuck_at 1 \

-observe 8827

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 Troubleshooting Low Coverage

Note: Gate ID value may vary!

Review the transcript. Was the fault able to be observed at the Y pin of the
NAND gate? ___________

9. Now, trace forward from U2694/Y to an endpoint. This will expose the
combinational instances up to a sequential element.

10. Determine if the fault can be propagated to the input of the TLA by
observing the output of U843 (GateID=12531).

ANALYSIS> analyze_fault /p1/fpu1/U2694/A1 -stuck_at 1 \

-observe 12531

Was this successful?______

11. Now, is the fault observable at the output of the TLA? Use the same
analysis using the GATEID for the TLA.

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 Troubleshooting Low Coverage

Was the fault observable? _________

What is the TLA name? ____________________________________

What is the enable (CLK) value? _____________________________

Do you think the fault can propagate through this latch? ___________

Why? ___________________________________________________

Does this agree with the previous fault analysis?

_________________________________________________

The tool “learns” that the gate is a TLA (transparent latch) during DRC.
Values can propagate through a TLA only when the enable is active – in this
Note case, when CLK = 1.

12. Now, trace the CLK pin of the TLA backwards to an endpoint. Also, go
back to U2694/A1 and trace it backward to an endpoint. Notice that the
same scan cell that drives U2694/A1 is also in the path of the TLA clock.
So if U2694/A1 = 0 the TLA Clock will also =0. The only way to detect
this fault is to change the design

13. Leave Tessent Visualizer open.

Examine Additional DRC Rule Violations

Many times, low test coverage can be caused by DRC violations, so next you
examine the DRC violations.

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 Troubleshooting Low Coverage

1. Open the DRC Browser tab in Tessent Visualizer.

What DRC violations are reported?

Fill in the first two columns in Table 10-1.

Table 10-1. DRC Violation Comparison

DRC violation # fails (run 1) # fails (run 2)

2. Examine D5 rule violations by double clicking on the D5 list. The same

list can be generated in the transcript using the following command.
ANALYSIS> report_drc_rules d5

Is the TLA fract_denorm_reg[9], you identified as an issue earlier, in the

report?

____________________________________________________

How is the latch described in the report? ____________________________

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 Troubleshooting Low Coverage

_____________________________________________________________

Do you also see the gate driving A0 of the NAND gate?

_____________________________________________________

Debugging the Design Netlist

The next step is to debug the design by reviewing the netlist.

1. In a new terminal window, open the design file design/gate_scan_8.v

netlist in a text editor.

2. Look for the problem with the module that needs to be defined as a black
box (Search for instance CLA_0).

What might you do to fix the problem? _____________________________

_____________________________________________________________

Do not edit the netlist. A corrected netlist, design/gate_scan_8_fixed.v, is

provided in the lab data directory.

The corrected netlist includes the following changes:

o Removes comments around CLA_0 so that it no longer is a black box.
o Updates the netlist to eliminate redundancy that was identified earlier in
the lab.
o Updates the netlist to add “other DFFs” to scan chain.
3. Exit Tessent Shell.

Rerun ATPG and Compare Results

1. Use the following command to invoke Tessent Shell using the run script
provided:
shell> generate_patterns_fixed

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 Troubleshooting Low Coverage

Notice that the script starts Tessent Shell. All chains and clocks are defined
and the tool remains in SETUP mode.

The following files are used by the script:

Design: design/gate_scan_8_fixed.v

Libraries: ../../libs/adk.atpg, ../../libs/picdram/picdram.tcelllib

Dofile: solutions/setup_tessent_shell_fixed.do

Log file: logs/ex_1_fixed.log

2. Identify any undefined modules.

Do you need to define a black box? ______________________________

3. Run design rules checks. Ignore DRC warnings.

4. Read faults from the file design/fs_sample_faults.flt, retaining each

fault's classification.

5. Generate test patterns.

ANALYSIS> create_patterns

6. After pattern generation is finished, refer to the statistics report in the

application window. How does this coverage compare to the coverage
generated from the initial netlist?

7. Display statistics for the /p1/fpu1 instance either in the transcript or in the
Instance Browser view of the Tessent Visualizer.

The total test coverage for the fpu1 instance is

________________________

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 Troubleshooting Low Coverage

How do the new results compare to those from the first run?
____________________________________________________________

8. Analyze the fault /p1/fpu1/U2694/A1 stuck-at-1 for controllability and

observability using the report.

What did you find? __________________

9. Investigate DRC violations and fill in the last column in Table 10-1.

10. Exit Tessent Shell.

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Tessent Scan and ATPG – Lab Answers

Appendix: Answers to Questions

These labs were qualified using Tessent 2020.1 and ModelSim 2020.2, if
other Tessent versions were used, results contained in tables in these labs
Note may differ slightly from those shown in this Lab Answers section.

Exercise 1

Identify and Black Box Undefined Modules

Step 1
 Based on the warning messages, which module(s) should be defined as black
boxes? CLA_0

Examine ATPG Untestable (AU) Faults

Step 6
The total number of AU faults, broken down into black boxes and
unclassified is: BB: 65; SEQ: 4; Unclassified: 87;
The total number of UC + UO faults are 997
The total test coverage for the design is 87.25%
 The total fault coverage for the design is 80.31%

Step 10
 Is the fault controllable? Yes
 Is the fault observable? No
 What parallel pattern number successfully controls the fault site? 0
 What is the pattern type for the controlling pattern? clock_sequential

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Tessent Scan and ATPG – Lab Answers

 What are some of the testing issues that can make a fault Atpg_Untestable?
Fault site cannot be propagated to any observation point (path detection
problems) or due to constraints or limitations placed on ATPG tool.

Graphically Analyze AU Faults

Step 7
 Is this a part of a scan cell? Yes

 What is it’s cell ID and which chain is it connected to? 162 and chain 6

Controlling a Pin to a Set Value

Step 2
 What do you observe in the transcript window? Controllability
justification was not successful - fault status = atpg_untestable

Debugging Observation Issues

Step 8
 Was the fault able to be observed at the Y pin of the NAND gate? Yes

Step 10
 Was this successful? Yes

Step 11
 Was the fault observable? No
What is the TLA name? Transparent Latch (fract_denorm_reg)
What is the enable (CLK) value? (0XX)
Do you think the fault can propagate through this latch? No

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Tessent Scan and ATPG – Lab Answers

Why? For values to propagate through TLA, CLK has to be 1 which in

this case is 0
 Does this agree with the previous fault analysis? No

Examine Additional DRC Rule Violations

Step 1
 Table: DRC Violation Comparison [Left for student]

Step 2
 Is the TLA fract_denorm_reg[9], you identified as an issue earlier, in the
report? Yes

 How is the latch described in the report? /p1/fpu1/\fract_denorm_reg[0]

(46229) is a non-scan latch identified as TLA

 Do you also see the gate driving A0 of the NAND gate? No

Debugging the Design Netlist

Step 2
 What might you do to fix the problem? Since CLA is commented to be
defined as a black box, defining it would be a possible fix to the problem.

Rerun ATPG and Compare Results

Step 2
 Do you need to define a black box? No

Step 7
The total test coverage for the fpu1 instance is 98.44%

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Tessent Scan and ATPG – Lab Answers

 How do the new results compare to those from the first run? Approximately
12% increment in the new results

Step 8
 What did you find? Analyzing /p1/fpu1/U2694/A1 stuck-at 1 finds:
Detected by simulation (DS) no longer AU

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