Tessent® Scan and ATPG

Lab
Understanding Test Pattern Generation

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 Table of Contents
Before you Begin ......................................................................................................4
Lab Understanding Test Pattern Generation .......................................................6
Introduction ............................................................................................................6
Objectives...............................................................................................................6
Exercise 1: Creating/Saving Test Patterns .............................................................7
Exercise 2: Verifying Test Patterns .....................................................................20
Exercise 3: Changing Test Pattern Timing (Optional) ........................................25

Appendix: Answers to Questions ..........................................................................30

Exercise 1 .............................................................................................................30
Exercise 2 .............................................................................................................32
Exercise 3 (Optional) ...........................................................................................33
 Before you Begin

If this is the first time you are launching this VM (Virtual Machine), you must
download and extract the lab data as described in the "Obtaining Lab Data
Caution
section below.

Whenever you are using the VM for lab exercises and are finished with your
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Setting Environment Variables

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Obtaining Lab Data

If the atpg_data directory, with lab subdirectories, is located in the home

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If this is the first time you are starting a session for this VM, the atpg_data
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 2. On the resulting web page, select the file named
tessent_atpg_data_v2020.1_20200611.tgz,

3. In the resultant window, select the Download button, enable the Save File
button, then select the OK button to download the file.

Move the file in the Downloads directory to the home directory. If you are using
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mv ./Downloads/tessent_atpg_data_v2020.1_20200611.tgz .

4. In a terminal window, extract the files from the compressed tar file using the
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tar xzvf ./tessent_atpg_data_v2020.1_20200611.tgz

You should now have a directory named atpg_data in your $HOME directory.
That directory contains all the files you need to perform the exercises, in this
learning path.

You are now ready to proceed with lab exercises.

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 Lab
Understanding Test Pattern Generation

Introduction
In this lab you use the create_patterns command to generate the appropriate
pattern types for your design. Next, you use Tessent Visualizer to investigate
fault groupings and coverage. Next, you save test patterns in the following
formats: ASCII and Verilog (parallel, serial, and chain test), and in WGL.
ModelSim will be used to simulate and verify test patterns in a timed simulation
environment. Finally, you will change the timing for simulations and ATE
patterns by editing the timeplate in a test procedure file and writing patterns using
the new timeplate.

Objectives
Upon completing this lab, you should be able to:

 Use one command to create test pattern types for any circuit

 Save test patterns in the following formats: ASCII and Verilog

o Save parallel patterns
o Save serial sample patterns
o Save chain test patterns
 Save test patterns in the WGL format
 Use ModelSim to simulate and verify the following testbenches:
o Parallel patterns
o Serial sample patterns
o Chain test patterns
 Create a new timeplate to change the timing for write_patterns

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 Understanding Test Pattern Generation

Exercise 1: Creating/Saving Test Patterns

In this exercise, you invoke Tessent Shell on a design and generate the correct
pattern type for it using create_patterns. You then invoke Tessent Visualizer
in order to investigate fault groupings and coverage within the three Browser
tabs.

Finally, you save test patterns in the following formats:

 ASCII
 Verilog (Parallel, Serial, Chain test)
 WGL
 Flattened design

Setup Instructions
1. Change to the $ATPG_LABS/Lab7/Exercise1 directory.
shell> cd $ATPG_LABS/Lab7/Exercise1

Invoke Tessent Shell and Generate Test Patterns

2. Invoke Tessent Shell with a logfile specified. Review the dofile
solutions/setup_tessent_shell.do and notice that it does the following:
o Sets the Tessent Shell context (patterns -scan)
o Reads the design: design/gate_2001_scan.v
o Reads the ATPG cell libraries: ../../libs/adk.atpg,
../../libs/picdram/picdram.tcelllib
Note: picdram.tcelllib is an ATPG model for the RAM so multi-load
patterns can be generated.
o Elaborates the design (set_current_design)
o Defines scan groups and scan chains
o Adds clock and control signals
shell> tessent -shell -dofile \
solutions/setup_tessent_shell.do -logfile logs/ex1.log \

-replace

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 Understanding Test Pattern Generation

3. Review the session transcript window to see what commands were

executed by the dofile.

Notice that this circuit design contains the following:

o Non-scan elements
o Scan chains
o RAMs

By default, Tessent Shell generates patterns that produce high test

coverage by using multiple pattern types. More complex designs require
the application of additional pattern types to achieve the highest test
coverage overall. This is achieved by using the create_patterns
command which automatically determines the appropriate pattern types to
create.
4. Run design rule checks.

What are some of the warning messages displayed in the session transcript
area? ________________________________________________________
_____________________________________________________________

Which DRC issues were identified? ______________

Note: Use report_drc_rules to get a synopsis of the DRC violations.

What types of DRCs were reported as warnings? _____________________

_____________________________________________________________

Clocks are very important for testing purposes, and identifying them
properly is important. What warning message is in the transcript about
ramclk? ______________________________________________________
_____________________________________________________________

5. There are two clock DRC violations you will analyze.

report_drc_rules will provide a synopsis of all DRC violations, and it

will also provide more details about specific violations. Start by
investigating the C8 DRC violation.

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 Understanding Test Pattern Generation

ANALYSIS> report_drc_rules C8

The following message reports that there is one occurrence of the C8

violation, and the PO (primary output) where it occurs:

// Warning: Primary output /DI5 is connected to clock /clk1.(C8-1)

If there is more than one occurrence of a DRC violation reported, further

investigation into each occurrence can be made by entering the
Note report_drc_rules <ID_occurence> command with its respective
number, such as C8-1,C8-2,C8-3…C8-N.

If further investigation is wanted, you also can view the DRC violation in
Tessent Visualizer by entering the following command at the ANALYSIS
prompt:
ANALYSIS> analyze_drc_violation C8-1

This automatically loads the violation into the Flat Schematic window in
Tessent Visualizer for further examination.

Open the Tessent Shell Reference Manual in order to find more information
about the C8 and C9 clock rule violations. What impact, if any, do these
violations have on coverage? _____________________________________

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 Understanding Test Pattern Generation

Continue reading as time allows in order to learn how you might resolve a
C8 or C9 DRC violation.

Since the C8 violations do not affect pattern generation or coverage, you will
move forward to create patterns.

6. Notice that “DRC Browser” tab in Tessent Visualizer lists “DRC

Violations”. This is another place where a listing of the DRC violations can
be found. If this tab is not showing, use the Open menu option at the top
and then select “DRC Browser”.

Figure 7-1. Tessent Visualizer –DRC Browser Window

Click on C9 violation, in the left pane, you will see that the C9-1 violation is
the only violation appearing in the right pane for type C9, double click on it,
this will open the flat schematic window analyzing that violation.

7. Leave Tessent Visualizer open.

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 Understanding Test Pattern Generation

8. Generate patterns. Note that since you have not defined a fault list,
create_patterns adds all faults. You can enter commands in the
Transcript window in Tessent Visualizer or in the shell window.
ANALYSIS> create_patterns

9. Fill in the following statistics

Coverage/Effectiveness # Faults

test_coverage

fault_coverage

# test_patterns

# basic patterns

# clock_seq_patterns

# mult_load_patterns

# simulated_patterns

CPU_time (secs)

Table 7-1. Test Coverage Effectiveness Statistics

How many faults were untestable? ____________________

How many faults were not detected? __________________

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 Understanding Test Pattern Generation

At the end of pattern generation, the statistics report is generated, Once you
are in system mode ANALYSIS, you can issue the report_statistics
command.

View Coverage Results in Tessent Visualizer Browser Window

In this next step, you view results in the Tessent Visualizer.

1. Open the Instance Browser tab. This will display the listing of instances
and modules in the design.

In the instance browser, click on the cpu_top module.

To view instances below this top module, click on it with your RMB, from
the popup menu select “Show as Parent in Instance Browser”, this will
show all instances below this top module

2. From the Settings menu, select the Gate Report option, check the Fault
Status option and click OK – this will an extra column with total faults
added to the instance window

3. Now you can add the fault classifications to the display. You can add
either specific classifications, or all classifications.

From the Columns and Filter Editors button on the top left corner
of the Instance Browser, expand Fault Statistics:

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 Understanding Test Pattern Generation

You can select the specific fault specification that you need to add, like the
DS and UO faults, make sure that all items checked below are checked on
your Columns and Filters Editor, Click OK:

Figure 7-2. Tessent Visualizer – Column and Filter Editor

a. Scroll to the right to examine the faults. Note that you can expand an
instance and get more information.

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 Understanding Test Pattern Generation

Figure 7-3. Tessent Visualizer – Instance Browser Window

4. Reordering the columns. While analyzing the design, it is often helpful to

have the columns ordered so all the undetected faults are easily viewable.
These would be the fault locations you may have to debug in order to
increase your coverage.

a. Select the heading “AU” and while holding down the left mouse
button, drag the header so it is positioned to the right of the UO
column. You may have to “drop” this column and scroll to the left
in order to be able to place it where you want.

5. Analyze faults and test coverage in the Cell Library Browser.

a. From the Open menu, Select Cell Library Browser.

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 Understanding Test Pattern Generation

b. The coverage information will need to be added to this view as you

did in the Instance window, using the Columns and Filters Editor
button on the top left corner.

Notice that fault coverage and test coverage numbers are reported both as
maximums and averages, make your selections as shown below in the
following figure, then click OK:

Figure 7-4. Tessent Visualizer – Column and Filter Editor

i. Look at the column heading called Fault Coverage. Which

components have less than 90% coverage (Check both columns)?
_________, _________, __________, __________, _________,
_________.

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 Understanding Test Pattern Generation

ii. Next look at the column heading called Test Coverage. Scroll
down the window. Which model or models has less than 75%
coverage (Check both columns)? ___________, ____________.

c. Continue to experiment with the Browser windows if you want.

When you are finished, close Tessent Visualizer but leave Tessent
Shell running.

Save Test Patterns in Various Formats

The following steps illustrate how to save the flat model and the test patterns
generated in the first part of this exercise. You will save in three formats: ASCII
for reuse and debug, Verilog for validation simulations, and WGL, a common
ATE format. Start with the parallel patterns first, then save the serial patterns.

1. Save the flat model

ANALYSIS> write_flat_model results/cpu_top.flt -replace

2. Save the patterns as an ASCII file with the following characteristics:

File name: results/cpu_top_patterns.ascii

Pattern format: ASCII

Save Scan Cell Data in: parallel (Default)

Overwrite any existing files of the same name.

ANALYSIS> write_patterns results/cpu_top.ascii -ascii \
-replace

ASCII test patterns are useful for reuse, debugging, and diagnostics. By
default, the write_patterns command saves test patterns in ASCII. This
format contains test pattern data in a text-based commented format that also
includes information such as settings and test procedure information.

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 Understanding Test Pattern Generation

3. Save the patterns in parallel Verilog format with the following

characteristics:

File name: results/cpu_top_parallel.v

Pattern format: Verilog

Save Scan Cell Data in: parallel

Overwrite any existing files of the same name.

ANALYSIS> write_patterns results/cpu_top_parallel.v \
-verilog -parallel -replace

The Verilog testbench files contain procedures to apply test patterns,

compare expected output with simulated output, and print out a report
containing information about failing comparisons. Tessent Shell writes all
patterns and comparison functions into the specified filename.v file, while
writing the primary output names in another file (filename.po.name).
Choosing parallel loading of scan chains enables Tessent Shell to write the
names of the scan output pins in each scan subchain into separate files (for
example, filename.chain1.name). This allows Verilog simulators to report
output pins with discrepancies between expected and simulated outputs.

Also note that the default pattern format is parallel, so using the -parallel
argument is not necessary, but useful to document in the logfile if you need
to debug any issues.
4. Next, save the patterns to parallel WGL format with the following
characteristics:

File name: results/cpu_top_parallel.wgl

Pattern format: WGL

Save Scan Cell Data in: parallel

Overwrite any existing files of the same name.

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 Understanding Test Pattern Generation

ANALYSIS> write_patterns results/cpu_top_parallel.wgl \

-parallel -wgl -replace

5. Save the patterns for a chain test only, in serial Verilog format with the
following characteristics:

File name: results/chaintest_ser.v

Pattern format: Verilog

Save Scan Cell Data in: serial

Overwrite any existing files of the same name.

ANALYSIS> write_patterns \
results/cpu_top_chaintest_serial.v –replace \
-verilog -serial -pattern_set chain

Chain test patterns check scan chain integrity. This test loads a repeating
pattern of 0011 into the chains, performs a non-clocked capture cycle, and
then unloads the scan chains. You may have noticed by default the chain test
is written when you write patterns.

6. This time, save the patterns in serial Verilog format with the following
characteristics:

File name: results/testpat_ser.v

Pattern format: Verilog

Save Scan Cell Data in: serial

Number of Patterns to Sample Per Pattern Type: 5

ANALYSIS> set_pattern_filtering -sample 5
ANALYSIS> write_patterns results/cpu_top_serial.v \
-verilog –serial -replace

Setting the number of patterns to sample per pattern type to five, reduces the
run time for the simulation.

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 Understanding Test Pattern Generation

How many patterns were written? ______________________

7. This is the end of this exercise. Exit Tessent Shell.

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 Understanding Test Pattern Generation

Exercise 2: Verifying Test Patterns

In this exercise, you will compile the Verilog testbench and the Verilog netlist
and run simulations in ModelSim. You created three Verilog testbenches in the
last exercise:
 Chain test patterns
 Parallel test patterns
 Serial sample test patterns

Setup Instructions
1. Move into the results directory where you just wrote the Verilog test
benches and other pattern sets.
$ cd results

You should be in $ATPG_LABS/Lab7/Exercise1/results directory.

Simulate/Verify the Chain Test Patterns

1. Compile the following files: <testbench> <netlist> <verilog library>
shell> vlib work
shell> vlog *.v ../design/gate_2001_scan.v \
../../../libs/adk.v \
../../../libs/picdram/picdram.v

2. Open ModelSim.
shell> vsim

A Welcome to ModelSim window opens. Close it and proceed directly to

ModelSim.

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 Understanding Test Pattern Generation

3. In the Library tab, expand the work directory and double-click on the
cpu_top_cpu_top_chaintest_serial_v_ctl testbench as shown to load it
into the simulator:

Figure 7-5. ModelSim – Library Window

Double-clicking on the block loads it into the simulator.

The testbench generated by Tessent Shell contains all the information

needed to run the simulation. Use the pull-down menu Simulate> Run>
Run -All, the Run All button, or type run -all at the VSIM> command
line prompt to run the simulation from start to finish. ModelSim is checking

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 Understanding Test Pattern Generation

for errors between the simulated and expected pattern values. This may take
a while to run.

Click No when you are asked ‘Are you sure you want to finish?’ in the
Finish Vsim dialog box until you have a chance to answer the following
questions.

Look at the transcript window in ModelSim to determine the outcome of

simulation.

How many nanoseconds does the simulation run for? ___________

Are there errors? _____ ________

4. After checking all the messages in the ModelSim transcript, leave the
simulator open so you can test the parallel Verilog patterns.

ModelSim simulated and verified that your serial chaintest Verilog

patterns do not have any simulation mismatches.

Simulate/Verify the Parallel Test Patterns

Next, simulate and verify the parallel Verilog patterns. Remember that this uses
all the patterns but does not shift them in and out of the scan chain.
1. The parallel testbench is already compiled (remember that the netlist and
library are already compiled from the last run.) Go back to the library tab.

2. In the Library tab, expand the work library and double-click

cpu_top_cpu_top_parallel_v_ctl to load the parallel testbench into the
simulator. This action loads the Load Design dialog window. Click Yes
when you are asked, “This operation will close the current simulation,
continue?”
The testbench generated by Tessent Shell contains all the information
needed to run the simulation. Use the pulldown menu Simulate > Run >
Run -All, the Run All button, or type the command to run the simulation

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 Understanding Test Pattern Generation

from start to finish. ModelSim is checking for errors between the simulated
and expected pattern values. This may take a few minutes, depending upon
the operating system you use.
Do not choose Yes in the Finish Vsim dialog box until you have a chance to
answer the following questions.

Look at the transcript window in ModelSim to determine the outcome of

simulation.

What test is done first? ___________________________________

How many nanoseconds does the simulation run for? ___________

Are there any errors? _____________

How do you know this?

_____________________________________________________________

ModelSim simulated and verified that your parallel Verilog patterns do not
have simulation mismatches.

3. After checking all messages in the ModelSim transcript, leave the

simulator open so you can test the serial Verilog patterns.

Simulate/Verify the Serial Test Patterns

Now you simulate and verify the serial Verilog patterns. Recall that the number
of patterns to sample per pattern was set to five. In a serial simulation you
simulate not only the load_unload/shift functions, but also the timing associated
with the more complex loading and clocking schemes. Simulation and
verification processing time is greatly reduced compared to performing a serial
simulation on the complete pattern set (but it is still pretty high).

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 Understanding Test Pattern Generation

These patterns may take longer to simulate, so if you are running out of time,
you can leave the lab at the previous step. The process is the same as the two
Note previous simulations.

1. Remember that the netlist and library are already compiled from the first
run. Click the Library tab to go back to the Library window.

2. In the Library tab, expand the work library and double-click on

cpu_top_cpu_top_serial_v_ctl to load the serial testbench into the
simulator. This action loads the Load Design dialog window. Click Yes
when you are asked, “This operation will close the current simulation,
continue?”
3. Run the simulation.

ModelSim is checking for errors between the simulated and expected pattern
values.

This may take several minutes to run.

Look at the transcript window in ModelSim to determine the outcome of

simulation.

What test is done first? ___________________________________

How many nanoseconds does the simulation run for? ___________

Are there any errors? _____________

How do you know this? _______________________________

ModelSim simulated and verified that your serial Verilog patterns do not
contain simulation mismatches. After you are finished with examining the
results, you may quit ModelSim.

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 Understanding Test Pattern Generation

Exercise 3: Changing Test Pattern Timing (Optional)

In this exercise you will create a fault list that is 1% of the total available faults.
This helps speed up the lab. You will then write a new test procedure file. You then
modify the timing of the test procedure file by creating and editing a new timeplate.
Finally, you apply the new timing to the created patterns as you save the pattern
sets referencing the new test procedure and timeplate.

Setup Instructions
1. Log in to your workstation if you are not already logged in.
2. Change to the $ATPG_LABS/Lab7/Exercise3 directory.
shell> cd $ATPG_LABS/Lab7/Exercise3

Create a Test Procedure File

1. Invoke Tessent Shell using the script solutions/setup_tessent_shell.do that
does the following:
o Sets the Tessent Shell context (patterns –scan)

o Reads the design: design/gate_2001_scan.v

o Reads the ATPG cell libraries: ../../libs/adk.atpg,
../../libs/picdram/picdram.tcelllib
Note: picdram.tcelllib is an ATPG model for the RAM so multi-load
patterns can be generated.
o Elaborates the design (set_current_design)
o Defines scan groups and scan chains
o Adds clock and control signals

Using the commands that you’ve used previously, start Tessent Shell, create a
logfile and run the dofile.

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Understanding Test Pattern Generation

2. Run the file solutions/one_percent_patterns.do.

SETUP> dofile solutions/one_percent_patterns.do

The commands will specify to create a faultlist of 1% of the total faults.

Design rule checks will be run, and then patterns will be generated.

What commands are run in this dofile?

________________________________________________________
___________________________________________________________
___________________________________________________________

3. Write the existing test procedure to a new file name.

ANALYSIS> write_procfile results/modified_proc.testproc \

-full -replace

Test procedure files define scan operations and the timing that will be applied
when you write patterns.

ATPG simulation is done with zero delay. Verilog/VHDL simulations and

Automatic Test Equipment (ATE) does require events to have timing
information associated to them.

When you setup your Tessent Shell environment for a project, you need to
create your test procedure files for the test environment your product will be
tested in. This includes the tester timing information.

There may be times that you get simulation or tester mismatches due to the
timeplate information being incorrect. To fix this, you do not need to recreate
patterns, you only need to apply a new timeplate as you write the patterns.

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 Understanding Test Pattern Generation

Modify the Timeplate in the Test Procedure File

In this example you will create a new timeplate that will be applied to the clock
sequential procedure. The rest of the procedures in the file will continue to
reference the original timeplate.

1. Using a text editor, open the results/modified_proc.testproc.

2. Copy the existing timeplate and name the new procedure gen_tp2.

3. Modify the timeplate as shown in the graphic below.

Figure 7-6. Modified Test Procedure File

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 Understanding Test Pattern Generation

4. Find the clock_sequential procedure. Notice that it currently references the

timeplate gen_tp1.
5. Edit the clock_sequential procedure so it references the new procedure you
just created (gen_tp2).

Figure 7-7. Edited clock_sequential Procedure

6. Save the edited file.

Save Test Patterns With New Timing Information

The next step in this process is to save the test patterns.

1. Save the flat model using the command you’ve used in earlier labs.

2. Save the ASCII parallel test patterns to a file with the following
characteristics:

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Understanding Test Pattern Generation

File name: results/testpat.v

Save Scan Cell Data in: parallel
Use Test Procedure File: results/modified_proc.testproc
Tests to be Saved: Chain and Scan

Overwrite any existing files of the same name.

ANALYSIS> write_patterns results/testpat.v -parallel \

-verilog -procfile ./results/modified_proc.testproc -replace

3. Look at the transcript window. What DRC messages are you getting?
_____________________ _____________________________________

Look in the Tessent Shell Reference Manual to determine what a W14

violation means. Note that these are warning messages and not errors.

4. Exit Tessent Shell.

This is the end of Lab

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Tessent Scan and ATPG – Lab Answers

Appendix: Answers to Questions

These labs were qualified using Tessent 2020.1 and ModelSim 2020.2, if
other Tessent versions were used, results contained in tables in these labs
Note may differ slightly from those shown in this Lab Answers section.

Exercise 1

Invoke Tessent Shell and Generate Test Patterns

Step 4
What are some of the warning messages displayed in the session transcript
area?
Warning: Rule FN1 violation occurs 5 times
Warning: Rule FN4 violation occurs 1487 times
Warning: 1 PO(s) are connected to a clock line. (C8)
Warning: 1 POs are connected to a clock line gated by scan cell that
uses same clock. (C9)
Warning: 7 read lines not forced off when read controls are off. (A7)

Which DRC issues were identified?

A7: #fails=7 handling=warning (unstable RAM cells when read
controls off)
C8: #fails=1 handling=warning (PO connected to a clock line)
C9: #fails=1 handling=warning (PO connected to a clock line gated by
scan cell that uses same clock)
D5: #fails=53 handling=warning (non-scan memory element)
E5: #fails=57 handling=note (X-state propagation)

 What types of DRCs were reported as warnings? A7, C8, C9, D5

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Tessent Scan and ATPG – Lab Answers

 What warning message is in the transcript about ramclk? Warning about

RAMCLK: Automatically adding non-clock write control 'ramclk' to
clock list since it drives the clock pin of edge-triggered RAM(s).

Step 5
 The C8 and C9 clock rule violations. What impact, if any, do these
violations have on coverage?
C8: does not impact coverage (The rule violation occurs when a primary
output is in the clock cone.)
C9: Failure to satisfy this rule may result in a small loss in test coverage
because it may introduce sequential effects into the generated clock
patterns (Data captured by any clock with a direct path (through
combinational logic only) to a primary output must not affect the direct
path to a primary output of that same clock.)

Step 9
 Table 7-1: Test Coverage Effectiveness Statistics

Coverage/Effectiveness # Faults

test_coverage 99.43%

fault_coverage 94.07%

# test_patterns 316

# basic patterns 77

# clock_seq_patterns 227

# mult_load_patterns 12

# simulated_patterns 322

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Tessent Scan and ATPG – Lab Answers

CPU_time (secs) 17.1 secs

 How many faults were untestable? 6743 (UU+TI+RE)

How many faults were not detected? 66

View Coverage Results in Tessent Visualizer Browser Window

Step 5
 Look at the column heading called Fault Coverage. Which components
have less than 90% coverage (Check both columns)?
and02, ao21, ao221, dff, nor03, picdram

 Next look at the column heading called Test Coverage. Scroll down the
window. Which model or models has less than 75% coverage?
nor03, picdram

Save Test Patterns in Various Formats

Step 6
 How many patterns were written? 15/316

Exercise 2

Simulate/Verify the Chain Test Patterns

Step 3
How many nanoseconds does the simulation run for? 29842 ns
 Are there errors? No

Simulate/Verify the Parallel Test Patterns

Step 2
What test is done first? Chain test

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How many nanoseconds does the simulation run for? 50162 ns

Are there any errors? No
 How do you know this? Transcript says: No error between simulated and
expected patterns

Simulate/Verify the Serial Test Patterns

Step 3
What test is done first? Chain test
How many nanoseconds does the simulation run for? 343562 ns
Are there any errors? No
 How do you know this? Transcript says: No error between simulated and
expected patterns

Exercise 3 (Optional)

Create a Test Procedure File

Step 2
 What commands are run in this dofile?
set_fault_sampling 1
check_design_rules
create_patterns

Save Test Patterns with New Timing Information

Step 3
 Look at the transcript window. What DRC messages are you getting?
W14 warnings - # 4, Procedures being replaced/ updates timing

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