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DDCO Lab - Solution 6&7

The document outlines the design and implementation of a 4:1 multiplexer and a 1:4 de-multiplexer using Verilog code. It includes the behavioral modeling for both components along with their respective testbenches to validate functionality. The testbench for the multiplexer tests various input combinations, while the de-multiplexer testbench demonstrates the selection of outputs based on the input signal and select lines.

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Kiran G
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13 views3 pages

DDCO Lab - Solution 6&7

The document outlines the design and implementation of a 4:1 multiplexer and a 1:4 de-multiplexer using Verilog code. It includes the behavioral modeling for both components along with their respective testbenches to validate functionality. The testbench for the multiplexer tests various input combinations, while the de-multiplexer testbench demonstrates the selection of outputs based on the input signal and select lines.

Uploaded by

Kiran G
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Experiment 6 & 7 DD&CO Lab 3rd semester

Course Instructor: Kiran G

4:1 multiplexer:

Fig. 4:1 Multiplexer (TT and expr’n) Fig. 4:1 Multiplexer (logical)

Verilog code for 4:1 mux using behavioural modelling:

Module 4_1_mux (i,s,y);


input [3:0]i;
input [1:0]s;
output reg y;
always @ (*)
begin
case (s)
2’b00: begin y=i[0]; end
2’b01: begin y=i[1]; end
2’b10: begin y=i[2]; end
2’b11: begin y=i[3]; end
Default: y=1’b0;
endcase
end
endmodule

Testbench for 4:1 mux:

module mux_tb();

reg [3:0]i;
reg [1:0]s;
wire y;
4_1_mux m1 (.i(i), .s(s), .y(y));
Initial

begin

i[3]=1'b0; i[2]=1'b0; i[1]=1'b0; i[0]=1'b1; s[1]=1'b0; s[0]=1'b0; #10;


i[3]=1'b0; i[2]=1'b0; i[1]=1'b1; i[0]=1'b0; s[1]=1'b0; s[0]=1'b1; #10;
i[3]=1'b0; i[2]=1'b1; i[1]=1'b0; i[0]=1'b0; s[1]=1'b1; s[0]=1'b0; #10;
i[3]=1'b1; i[2]=1'b1; i[1]=1'b0; i[0]=1'b0; s[1]=1'b1; s[0]=1'b1; #10;

end
endmodule

1:4 de-multiplexer:

Fig. 1:4 De-Multiplexer (LD and TT)

module 1_4_demux (y, s, din);


output reg [3:0] y;
input [1:0] s;
input din;

always @(*)
begin
case (s)
2'b00 : begin y[0] = din; end
2'b01 : begin y[1] = din; end
2'b10 : begin y[2] = din; end
2'b11 : begin y[3] = din; end
default: y[3:0]=4’b0000;
endcase
end
endmodule

Testbench for 1:4 demux:

module mux_tb();

reg din;
reg [1:0]s;
wire [3:0]y;

1_4_demux m1 (.din(din), .s(s), .y(y));

Initial
begin
din = 1’b1;
s = 2'b00; #10;
s = 2'b01; #10;
s = 2'b10; #10;
s = 2'b11; #10;
end

endmodule

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