1

Quantum Circuit Designs of Integer Division

Optimizing T-count and T-depth
Himanshu Thapliyal∗ , Edgard Muñoz-Coreas∗, T. S. S. Varun∗, and Travis S. Humble†

Abstract—Quantum circuits for mathematical functions such basic quantum integer arithmetic functions such as division
arXiv:1809.09732v1 [quant-ph] 25 Sep 2018

as division are necessary to use quantum computers for scientific in quantum programming languages such as Quipper and
computing. Quantum circuits based on Clifford+T gates can LIQU i|i and in quantum computing design tools [1] [5].
easily be made fault-tolerant but the T gate is very costly to
implement. The small number of qubits available in existing Quantum computation can be performed on quantum cir-
quantum computers adds another constraint on quantum cir- cuits built from quantum gates. Any constant inputs in the
cuits. As a result, reducing T-count and qubit cost have become quantum circuit are called ancillae. Garbage outputs are any
important optimization goals. The design of quantum circuits outputs which exist in the quantum circuit to preserve one-to-
for integer division has caught the attention of researchers and one mapping but are neither one of the primary inputs nor a
designs have been proposed in the literature. However, these
designs suffer from excessive T gate and qubit costs. Many of useful output. The inputs regenerated at the outputs are not
these designs also produce significant garbage output resulting in considered garbage outputs [6]. Ancillae and garbage outputs
additional qubit and T gate costs to eliminate these outputs. In are circuit overhead that need to be minimized.
this work, we propose two quantum integer division circuits. The fault-tolerant implementation of quantum circuits is
The first proposed quantum integer division circuit is based gaining the attention of researchers because physical quantum
on the restoring division algorithm and the second proposed
design implements the non-restoring division algorithm. Both computers are prone to noise errors [7]. Fault-tolerant imple-
proposed designs are optimized in terms of T-count, T-depth mentations of quantum gates and quantum error correcting
and qubits. Both proposed quantum circuit designs are based codes can be used to overcome the limits imposed by noise
on (i) a quantum subtractor, (ii) a quantum adder-subtractor errors in implementing quantum computing [8] [9]. Recently,
circuit, and (iii) a novel quantum conditional addition circuit. researchers have implemented quantum logic gates such as
Our proposed restoring division circuit achieves average T-count
savings from 79.03% to 91.69% compared to the existing works. the Toffoli gate, Fredkin gate and quantum full adder with
Our proposed non-restoring division circuit achieves average T- fault-tolerant implementations of the Clifford+T gates due to
count savings from 49.75% to 90.37% compared to the existing their demonstrated tolerance to noise errors [8]. However, the
works. Further, both our proposed designs have linear T-depth. increased tolerance to noise errors comes with the increased
implementation overhead associated with the quantum T gate
[10] [8] [9]. Because of the increased cost to realize the T gate,
I. I NTRODUCTION
T-count and T-depth are important performance measures for
Among the emerging computing paradigms, quantum com- fault-tolerant quantum circuit design.
puting appears promising due to its applications in number The design of quantum circuits for integer division is an
theory, encryption, search and scientific computation [1] [2]. active area of research. Designs such as those proposed in [11],
Quantum circuits for integer arithmetic operations such as [12] and [13] present dividers that can be used in quantum
addition, subtraction, multiplication and division are required computation. The design in [11] implements the restoring
in the quantum circuit implementations of many quantum division algorithm and the designs in [12] are based on the
algorithms in these areas. Quantum arithmetic circuits for non-restoring division algorithm. The design presented in the
division can be used in the circuit implementation of quantum recent work in [13] uses a novel division algorithm. The design
algorithms such as those for computing shifted quadratic in [11] has a significant overhead in terms of T gates because it
character problems, principal ideal problems and hidden shift depends on quantum gates that cannot be exactly constructed
problems [2] [3] [4]. Quantum division circuits also reduce the using Clifford+T gates. The Clifford+T gate approximations
resources needed in the circuit implementations of higher level for these gates are costly in terms of T-count [14]. Further,
functions such as calculating the greatest common divisor via the T-count increases as the accuracy of the approximation
the Euclidean algorithm. An efficient quantum circuit for the of these gates is improved [14]. In contrast the dividers in
Euclidean algorithm has use in quantum algorithms such as [12] depend on quantum gates that can be exactly realized
those for solving the shifted multiplicative character problem with Clifford+T gates. At most 7 T gates are required to
[4]. Thus, researchers have included dedicated libraries of implement each logic gate in [12]. Thus, the designs in [12]
∗ Himanshu Thapliyal, Edgard Muñoz-Coreas, T. S. S. Varun are with the require significantly fewer T gates than the design presented in
Department of Electrical and Computer Engineering, University of Kentucky, [11]. However, the designs in [12] produce significant garbage
Lexington, KY, USA. output. Thus, the dividers in [12] will have additional ancillae
Email :[email protected] and T gate overhead from removing these garbage outputs. A
† Travis S. Humble is with the Quantum Computing Institute, Oak Ridge
National Laboratory, TN, USA. recent design presented in [13] also depends on quantum gates
that can be exactly realized with Clifford+T gates. However,
 2

the design methodology presented in [13] generates a quantum have implemented quantum logic gates and circuits with fault-
circuit that suffers from significant T gate and qubit cost tolerant implementations of the Clifford+T gate set due to its
overhead. In addition, the design in [13] produces significant demonstrated tolerance to noise errors [8]. Figure 1 presents
garbage output. Thus, the divider in [13] will have additional the gates that make up the Clifford+T quantum gate family.
ancillae and T gate overhead from removing these garbage Evaluating quantum circuit performance in terms of T-count
outputs. and T-depth is of interest to researchers because the fault-
To address the shortcomings of the existing work this paper tolerant implementation of the T gate is significantly more
presents two designs for quantum circuit integer division based costly than the fault-tolerant implementation costs of the other
on Clifford+T gates. The first proposed quantum circuit is Clifford+T gates [10]. The number of qubits in a quantum
based on the restoring division algorithm and the second circuit is a resource measure of interest because of the limited
proposed quantum circuit is based on the non-restoring di- number of qubits available on existing quantum computers
vision algorithm. Both proposed quantum integer division [17] [18]. We now define the T-count, T-depth and qubit cost
circuits are based on: (i) a quantum subtractor, (ii) a quantum resource measures.
adder-subtractor circuit, and (iii) a novel quantum conditional • T-count: T-count is the total number of T gates used in
addition circuit. The preliminary version of this paper is avail- the quantum circuit.
able in [15], [16]. The proposed quantum restoring division • T-depth: T-depth is the number of T gate layers in the
circuit has quadratic T-count, linear T-depth and requires 3 · n circuit, where a layer consists of quantum operations that
qubits (where n is the size of the inputs). The proposed non- can be performed simultaneously.
restoring division circuit has quadratic T-count, linear T-depth • Qubit cost: Qubit cost is the total number of qubits
and requires 3 ·n− 1 qubits (where n is the size of the inputs). required to design the quantum circuit.
This paper is organized as follows: Section II discusses the
Clifford+T gate set, background on resource cost measures,
B. Design of Quantum Subtractor
the quantum subtractor, quantum adder-subtractor circuit and
the novel quantum conditional addition circuit. The proposed The subtractor circuit takes two n bit inputs a and b. At
quantum restoring integer division circuit is presented in the end of computation, the input a emerges unchanged and
Section III while the comparison with the existing works the input b is transformed to the difference of b from a. The
is presented in Section IV. In Section V, the design of quantum subtractor calculates (b̄ + a) which is equivalent to
the proposed quantum non-restoring integer division circuit b − a [19]. A quantum ripple carry adder is used to realize the
is discussed and Section VI illustrates comparison with the quantum subtractor circuit. We use the quantum ripple carry
existing works. adder proposed in [20] for developing the quantum subtractor
circuit. We chose the ripple carry adder proposed in [20]
II. BACKGROUND because this adder has been shown in the literature to be
efficient in terms of gates and has a T-depth that is constant
A. Quantum Gates and independent of the circuit size n. We determined that this
quantum subtractor will have a T-count of 14 · n − 14 and a
C LIFFORD +T G ATE S ET   T-depth of 10. Thus, the quantum subtraction circuit used in
√1
1 1
Hadamard Gate our proposed dividers will have a T-count of order O(n) and
H 2 1 −1
  a T-depth of order O(1).
1 0
T Gate
0 ei· 4
π
T
  C. Design of Quantum Adder-Subtractor (Add-Sub) Circuit
Hermitian of T 1 0
Gate T† 0 e−i· 4
π The quantum adder-subtractor (Add-Sub) circuit takes two
  n bit inputs a and b and a single one bit input ctrl. Operation
1 0
Phase Gate of the quantum Add-Sub circuit is conditioned on the value of
S 0 i
  ctrl. When ctrl is high, the circuit calculates b − a. When the
Hermitian of 1 0 ctrl input is low, the circuit calculates b + a. The quantum
Phase Gate S† 0 −i Add-Sub calculates (b̄ + a) when ctrl is high. The expression
 
0 1 (b̄ + a) is equivalent to b − a. The quantum Add-Sub circuit
NOT Gate
1 0 is based on the design presented in [19] and uses the ripple
 
1 0 0 0 carry adder in [20]. We determined that this quantum Add-
Feynman  0 1 0 0 Sub circuit will have a T-count of 14 · n − 14 and a T-depth of
•  
(CNOT) Gate  0 0 0 1 10. Thus, the quantum Add-Sub circuit used in our proposed
0 0 1 0 dividers will have a T-count of order O(n) and a T-depth of
order O(1).
Fig. 1: The quantum gate set used in this work.

Fault-tolerant implementation of quantum circuits is gaining D. Design of Quantum Conditional Addition Ctrl-Add Circuit
the attention of researchers because physical quantum com- The quantum Ctrl-Add circuit in this work is a modified
puters are prone to noise errors [7]. Recently, researchers version of the Ctrl-Add circuit proposed in [21]. Operation of
 3

ctrl • • • • ctrl
b0 • • s0 Algorithm 1: Restoring division algorithm
a0 • • • a0 Function Restoring(a, b)
b1 • • s1 Requirements: a and b are positive and 2’s complement.
a1 • • • • • • • a1 //Takes 2 n bit values a and b as input.
b2 • • s2 //Returns the quotient as an n bit number Q and
a2 • • • • • • • a2 //the remainder from the division as an n bit
b3 s3 //number R.
a3 • • • a3
1 R = 0n ; // Where 0n are n zeros.
Fig. 2: Circuit design of quantum Conditional Addition (Ctrl- 2 Q = an−1 an−2 · · · a1 a0
Add) circuit 3 // an−1 is the most significant bit of a.
4
5 For i = 1 to n − 1
the quantum Ctrl-Add circuit is conditioned on the value of 6 Y = Rn−1−i Rn−3−i · · · R1 R0 Qn−1 · · · Qn−i
ctrl. When ctrl is high, the circuit calculates b + a. When ctrl 7 // Where Rn−1−i is the most significant bit of Y .
is low, the circuit performs no computation. An illustrative 8 Y =Y −b
example is shown in Figure 2 for two 4 qubit operands 9 If (Y < 0)
a0 . . . a3 and b0 . . . b3 . We are able to reduce the amount of 10 Y =Y +b
qubits and quantum gates required because we do not need 11 End
the carry out qubit in the proposed integer dividers. 12 Rn−i = Rn−1−i
We determined that our quantum Ctrl-Add circuit will have 13 End
a T-count of 21 · n − 14 and a T-depth of 2 · n. Thus, the 14
quantum Ctrl-Add circuit used in our proposed dividers will 15 Q=Q−b
have a T-count of order O(n) and a T-depth of order O(n). 16 If (Q < 0)
17 Q = Q + b;
18 End
III. P ROPOSED D ESIGN OF R ESTORING Q UANTUM
19 R0 = Qn−1
I NTEGER D IVISION C IRCUIT
20
We now present our proposed restoring quantum integer 21 Return Q, R
division circuit. The proposed design produces no garbage
output and has lower T-count and qubit costs compared to the Fig. 3: The restoring division algorithm.
existing works. The quantum circuits used in our proposed
quantum restoring division circuit are (i) the quantum sub-
division of a by b. At the end of computation, the quantum
tractor and (ii) the quantum Ctrl-Add circuit. Our proposed
register |Qi will have the quotient of the division of a by b.
quantum restoring divider saves T gates by not doing compu- The proposed methodology is generic in nature and can
tation in the QFT domain. We also base our design on the T design a quantum restoring integer division circuit of any
gate efficient quantum subtractor and the novel quantum Ctrl- size. The steps of the proposed methodology are presented
Add circuit presented in Section II. The modules used in our along with an illustrative example of the proposed quantum
quantum circuit do not produce garbage outputs and restore restoring integer division circuit for the division of two 4
inputs to their original values. Thus, we are able to save qubits bit numbers a0 . . . a3 and b0 . . . b3 shown in Figure 4. The
and T gates by placing these quantum circuits such that our proposed methodology is repeated n times. A quantum circuit
proposed quantum restoring division circuit will produce no
is generated for each step of the design.
garbage outputs.
This proposed quantum integer division circuit calculates
A. Steps of the Proposed Design Methodology
division by implementing the restoring division algorithm. The
restoring division algorithm is illustrated in Figure 3. Prior The following steps of the proposed methodology are re-
research has demonstrated the correctness of the restoring peated n times. Starting with the first n − 1 iterations.
division algorithm through functionally correct circuit imple- For i = 1 : 1 : n − 1:
mentations such as those in [11]. • Step 1: This step executes line 6 and line 8 of Algorithm 1
Consider the division of two n bit 2’s complement positive in quantum hardware. Step 1 is shown for a 4 bit restoring
binary numbers a and b. Let |Bi be a n bit quantum register divider in Figure 4a. This step has the following two sub-
that is initialized to the value b, let |Qi be a n bit quantum steps:
register that is initialized with the value a and let |Ri be a n bit – Sub-step 1: Treat the locations |Rn−1−i i through
quantum register initialized to 0. At the end of computation, |R0 i of quantum register |Ri and locations |Qn−1 i
the quantum register |Bi will be restored to the value b through |Qn−i i of quantum register |Qi as one
while the quantum register |Ri will have the remainder of the n qubit combined quantum register |Y i such that
 4

|Q2:0 i |Q2:0 i |Q2:0 i |Q2:0 i computation.

|Q3 i |Q3 i |Q3 i |Q3 i – Sub-step 2: Apply quantum register location |Rn−i i

Subtraction

Subtraction
|R0 i |R0 i |R0 i |R0 i to the quantum Ctrl-Add circuit such that the opera-
|R1 i |R1 i |R1 i |R1 i tion of the Ctrl-Add circuit will be conditioned on the
|R2 i |R2 i |R2 i • |R2 i value at location |Rn−i i. Quantum register location
|R3 i |R3 i |R3 i |R3 i
|Rn−i i is unchanged.
|B3:0 i • |B3:0 i |B3:0 i • |B3:0 i After this step,
(a) after Step 1 (b) after Step 2 • Step 4: This step completes the execution of line 12 of
|Q2:0 i |Q2:0 i
Algorithm 1. Step 4 is shown for a 4 bit restoring divider
in Figure 4d. At quantum register location |Rn−i i apply
|Q3 i |Q3 i
Subtraction

Ctrl-Add a quantum NOT gate. Quantum register location |Rn−i i

|R0 i |R0 i
now has the remainder bit rn−i of the division of a by
|R1 i |R1 i
b.
|R2 i • |R2 i
|R3 i • |R3 i The final iteration has the following steps:
|B3:0 i • • |B3:0 i • Step 1: This step executes line 15 of Algorithm 1 in
quantum hardware. Step 1 is shown for a 4 bit restoring
(c) after Step 3
divider in Figure 4a. Apply quantum register |Bi and
|Q2:0 i |Q2:0 i |Q2:0 i |Q2:0 i
quantum register |Qi to the quantum subtraction circuit
|Q3 i |Q3 i |Q3 i |Q3 i
Subtraction

so that, at the end of computation, |Bi is unchanged and

Iteration 1
Ctrl-Add

|R0 i |R0 i |R0 i |R0 i |Qi has the result of computation.

|R1 i |R1 i = |R1 i |R1 i • Step 2: This step prepares register location |R0 i for use
|R2 i • |R2 i |R2 i |R2 i in subsequent steps and partially completes the execution
|R3 i • |R3 i |R3 i • |R3 i of line 19 of Algorithm 1. Step 2 is shown for a 4
|B3:0 i • • |B3:0 i |B3:0 i • |B3:0 i bit restoring divider in Figure 4b. At quantum register
locations |R0 i and |Qn−1 i, apply a CNOT gate such
(d) after Step 4. Quantum circuit and equivalent graphical represen-
tation are shown. that quantum register location |Qn−1 i is unchanged and
quantum register location |R0 i shall be transformed to
Fig. 4: Circuit generation of the proposed quantum restoring the value |R0 ⊕ Qn−1 i.
division circuit for the case of i = 1 (illustrated with a 4 bit • Step 3: Steps 3 implements lines 16 through 18 of
divider). Algorithm 1 in quantum hardware. Step 3 is shown for
a 4 bit restoring divider in Figure 4c. Step 3 has the
following two sub-steps:
the values at locations |Qn−1 i through |Qn−i i will
occupy locations |Yi−1 i through |Y0 i and locations – Sub-step 1: Apply the quantum registers |Bi and |Qi
|Rn−1−i i through |R0 i will occupy locations |Yn−1 i to a quantum Ctrl-Add circuit with no input carry
through |Yi i. such that the quantum register |Bi will be unchanged
– Sub-step 2: Apply quantum register |Bi and quantum and quantum register |Qi will contain the result of
register |Y i to the quantum subtraction circuit so computation.
that, at the end of computation, |Bi is unchanged – Sub-step 2: Apply quantum register location |R0 i to
and |Y i has the result of computation. the quantum Ctrl-Add circuit such that the operation
of the Ctrl-Add circuit will be conditioned on the
• Step 2: This step prepares register location |Rn−i i for use
value at location |R0 i. Quantum register location
in subsequent steps and partially completes the execution
|R0 i is unchanged.
of line 12 of Algorithm 1 in quantum hardware. Step 2
is shown for a 4 bit restoring divider in Figure 4b. At After this step, quantum register |Qi will have the quo-
quantum register locations |Rn−i i and |Yn−1 i, apply a tient of the division of a and b.
CNOT gate such that quantum register location |Yn−1 i • Step 4: This step completes the execution of line 19 of
is unchanged and quantum register location |Rn−i i is Algorithm 1. Step 4 is shown for a 4 bit restoring divider
transformed to |Rn−i ⊕ Yn−1 i. in Figure 4d. At quantum register location |R0 i apply a
• Step 3: Step 3 implements lines 9 through 11 of Algo- quantum NOT gate. Quantum register location |R0 i now
rithm 1 in quantum hardware. Step 3 is shown for a 4 bit has the remainder bit r0 of the division of a by b. After
restoring divider in Figure 4c. This step has the following this step, quantum register |Ri now has the remainder of
two sub-steps: the division of a and b.
– Sub-step 1: Apply the quantum registers |Bi and |Y i
to a quantum Ctrl-Add circuit with no input carry Figure 5 shows the complete proposed quantum restoring
such that the quantum register |Bi will be unchanged division circuit for the division of two 4 bit numbers a0 . . . a3
and quantum register |Y i will contain the result of and b0 . . . b3 .
 5

circuits have T-depth of order O(1). We determined as well

|Q0 i |Q0 i that Ctrl-Add circuits in the literature such as the design in

Iteration 4
[21] scale as a function of circuit size n. Thus, these Ctrl-Add
|Q1 i |Q1 i
circuits have a T-depth of order O(n).

Iteration 3
|Q2 i |Q2 i The T-depth of the proposed quantum integer division
circuit is illustrated shortly for each step of the proposed

Iteration 2
|Q3 i Iteration 1 |Q3 i design methodology. The steps are iterated n times.
|R0 i • |R0 i • Step 1 has a constant T-depth of 10. This T-depth is seen
by locations |B1 i through |Bn−2 i of quantum register
|R1 i • |R1 i |Bi. We use a quantum subtraction circuit of constant
|R2 i • |R2 i T-depth 10 in this step (where T-depth is independent of
circuit size n).
|R3 i • |R3 i • Step 2 does not require T gates.
• Step 3 has a T-depth of 2 · n. This T-depth is seen by
|B3:0 i • • • • |B3:0 i
location |Rn−1−i i of quantum register |Ri (where 0 ≤
Fig. 5: Complete proposed quantum restoring integer divider i ≤ n− 1). We use a quantum Ctrl-Add circuit of T-depth
circuit (after all 4 iterations) 2 · n in this Step.
• Step 4 does not require T gates.
We now illustrate the steps we use to determine the total
IV. C OST A NALYSIS OF THE P ROPOSED R ESTORING T-depth for the proposed quantum restoring integer division
D IVISION C IRCUIT circuit.
A. T-Count Analysis • Step 1: Calculate the total T-depth for quantum register

The T-count of the proposed quantum integer division |Bi. We determine the T-depth for quantum register |Bi
circuit is illustrated shortly for each step of the proposed for each step of the proposed methodology.
design methodology. The steps are iterated n times. – Step 1: Locations |B1 i through |Bn−2 i of quantum
• The T-count for Step 1 is 14 · n − 14. We use a quantum
register |Bi see 10 T gate layers.
subtraction circuit of T-count 14 · n − 14 in this step. – Step 2 does not require T gates
• Steps 2 does not require T gates.
– Step 3: Locations |B1 i through |Bn−2 i of quantum
• The T-count for Step 3 is 21 · n − 14. We use a quantum
register |Bi see 13 T gate layers.
Ctrl-Add circuit of T-count 21 · n − 14 in this step. – Step 4 does not require T gates.
• Steps 4 does not require T gates. Thus, quantum register |Bi has a T-depth of 23 · n.
• Step 2: Calculate the total T-depth for quantum register
We determine the T-count for a single iteration of the
|Ri. We first consider iterations 1 through n − 1. For
proposed design by summing the T-count for each step in the
methodology as shown below: iteration i (where 1 ≤ i ≤ n − 1), we determine the
T-depth for quantum register |Ri for each step of the
proposed methodology.
14 · n − 14 + 21 · n − 14 (1)
– Step 1: Locations |Rn−2−i i through |R0 i of quantum
This expression can be simplified to the following: register |Ri see 4 T gate layers. After iteration n−2,
only location |R0 i of quantum register |Ri will see
35 · n − 28 (2) T gate layers. In iteration n − 1, |Ri will not see any
T gate layers.
The steps in the proposed methodology are iterated n times.
– Step 2 does not require T gates
Thus the T-count for the proposed restoring division circuit is
– Step 3: Locations |Rn−i i sees 2 · n T gate layers
n · (35 · n − 18) which simplifies to the expression shown
while |Rn−2−i i through |R0 i of quantum register
below:
|Ri see 6 T gate layers. After iteration n − 2, only
locations |R2 i and |R0 i of quantum register |Ri will
35 · n2 − 28 · n (3) see T gate layers. In iteration n − 1, only location
|R1 i will see any T gate layers.
B. T-Depth Analysis – Step 4 does not require T gates.
The T-depth of the proposed quantum integer division Thus, a single iteration of the proposed design see a T-
circuit is illustrated shortly for each step of the proposed depth of 2 · n on quantum register location |Rn−i i. We
design methodology. Our proposed design is based on T-depth now consider the final iteration pf the proposed design:
efficient designs of quantum subtraction circuits and quantum – Step 1: No locations of quantum register |Ri see T
Ctrl-Add circuits. We determined that garbageless and T gate gate layers.
optimized quantum subtraction circuits in the literature such – Step 2 does not require T gates
as the design in [19] have a T-depth that is constant and – Step 3: Location |R0 i sees 2 · n T gate layers.
independent of the circuit size n. Thus, these subtraction – Step 4 does not require T gates.
 6

Thus, the final iteration of the proposed design see a TABLE I: Comparison of Resource Count Between Proposed
T-depth of 2 · n on quantum register location |R0 i. and Existing Work
We calculate the total T-depth seen by each location in
register |Ri and determined that location |R0 i sees the 1 2 Proposed
most T gate layers, a total of 12 · n − 18 T gate layers.
T-count ≈ 400 · n2 ≈9· n3 35 · n2 − 28 · n
• Step 3: Calculate the total T-depth for quantum register T-depth 130 · n NA 23 · n
|Qi. We first consider iterations 1 through n − 1. For qubits 4·n ≈ 12 n3 + 4 · n 3·n
iteration i (where 1 ≤ i ≤ n − 1), we determine the 1 is the design by Khosropour et al. [11]
T-depth for quantum register |Qi for each step of the 2 is the design by Dibbo et al. [13] modified to remove garbage output.
Table entries are marked NA where a closed-form expression is not
proposed methodology. available for the design by Dibbo et al.
– Step 1: Locations |Qn−1 i through |Qn−i i of quan-
tum register |Qi see 4 T gate layers. TABLE II: T-count Comparison of Quantum Integer Division
– Step 2 does not require T gates Circuits
– Step 3: Locations |Qn−1 i through |Qn−i i of quan-
n 1 2 Proposed % Impr. % Impr.
tum register |Qi see 6 T gate layers. w.r.t. 1 w.r.t. 2
– Step 4 does not require T gates. 4 ≈ 6400 ≈ 576 448 ≈ 93.00 ≈ 22.22
8 ≈ 25600 ≈ 4608 2016 ≈ 92.13 ≈ 56.25
Thus, a single iteration of the proposed design see a T- 16 ≈ 102400 ≈ 36864 8512 ≈ 91.69 ≈ 76.91
depth of 10 on quantum register location |Qn−1 i through 32 ≈ 409600 ≈ 294912 34944 ≈ 91.47 ≈ 88.15
64 ≈ 1638400 ≈ 2359296 141568 ≈ 91.36 ≈ 94.00
|Qn−i i. We now consider the final iteration of the pro- 128 ≈ 6553600 ≈ 18874368 569856 ≈ 91.30 ≈ 96.98
posed design: 256 ≈ 26214400 ≈ 150994944 2286592 ≈ 91.28 ≈ 98.49
512 ≈ 104857600 ≈ 1207959552 9160704 ≈ 91.26 ≈ 99.24
– Step 1: Locations |Qn−2 i through |Q0 i of quantum Average: 91.69 79.03
register |Qi see 4 T gate layers. 1 is the design by Khosropour et al. [11]
– Step 2 does not require T gates 2 is the design by Dibbo et al. [13] modified to remove garbage output.
– Step 3: Locations |Qn−2 i through |Q0 i of quantum
register |Qi see 6 T gate layers.
– Step 4 does not require T gates. depends on quantum gates that cannot be accurately realized
Thus, the final iteration of the proposed design see a T- with Clifford+T gates. For these quantum gates, we use the
depth of 10 on quantum register locations |Qn−2 i through Clifford+T approximations presented in [14] to calculate the
|Q0 i. We calculate the total T-depth seen by each location T-count. We select the approximations for these gates with
in register |Qi and determined that location |Qn−1 i sees the poorest accuracy in our calculations since they have the
the most T gate layers. Location |Qn−1 i sees 10 · n − 8 lowest T-count. We also apply the Bennett’s garbage removal
T gate layers. scheme illustrated in [22] to remove the garbage outputs from
• Step 4: Determine which quantum register sees the most the design by Dibbo et. al. We determined the qubit cost for the
T gate layers. In our proposed design the T-depth for each design in Khosropour et al. by summing the qubits required for
quantum register is given as: the quotient, remainder, garbage outputs, and primary inputs.
We estimated the qubit cost for the design by Dibbo et. al.
– Quantum register |Qi has a T-depth of 10 · n − 8. by summing the qubits required for the quotient, remainder,
– Quantum register |Ri has a T-depth of 12 · n − 18. garbage outputs, and primary inputs.
– Quantum register |Bi has a T-depth of 23 · n.
1) Cost Comparison in Terms of T-count: Table I shows
Quantum register |Bi sees the most T gate layers because that our proposed design and the design by Khosropour et
23 · n > 12 · n − 18 and 23 · n > 10 · n − 8. Thus, al. have T-count costs of order O(n2 ) while the T-count for
the T-depth for our proposed quantum restoring integer the design by Dibbo et al. is of order O(n3 ). Table II shows
division circuit is 23 · n. This T-depth is seen by location
|B1 i through |Bn−2 i of quantum register |Bi.
TABLE III: Qubit Cost Comparison of Quantum Integer
Division Circuits
C. Cost Comparison
Comparisons of the proposed design with the current state n 1 2 Proposed % Impr. % Impr.
w.r.t. 1 w.r.t. 2
of the art are presented in Tables I, II and III. We compare
our proposed design to the existing quantum restoring division 4 16 ≈ 48 12 25.00 ≈ 75.00
8 32 ≈ 288 24 25.00 ≈ 91.67
circuit by Khosropour et al. [11]. We also compare against 16 64 ≈ 2112 48 25.00 ≈ 97.73
the novel design methodology presented in Dibbo et. al. 32 128 ≈ 16512 96 25.00 ≈ 99.42
[13]. To perform the comparison of our proposed design to 64 256 ≈ 131328 192 25.00 ≈ 99.85
128 512 ≈ 1049088 384 25.00 ≈ 99.96
the existing quantum division circuits, we implemented each 256 1024 ≈ 8389632 768 25.00 ≈ 99.99
designs with Clifford+T gates. To realize reversible gates such 512 2048 ≈ 67110912 1536 25.00 ≈ 99.99
as the Toffoli gate, we use the Clifford+T implementations Average: 25.00 93.94
presented in [8]. As ahown in [8], the Toffoli gate has a T- 1 is the design by Khosropour et al. [11]
count of 7 and a T-depth of 3. The design by Khosropour et al. 2 is the design by Dibbo et al. [13] modified to remove garbage output.
 7

that our proposed design methodology achieves improvement

ratios ranging from 91.26% to 93.00% and 22.22% to 99.24%
Algorithm 2: Non-restoring division algorithm
compared to the designs by Khosropour et al. and the design
by Dibbo et al. in terms of T-count. Function Non-Restoring(a, b)
2) Cost Comparison in Terms of Qubits: Table I shows that Requirements: a and b are positive and 2’s complement.
our proposed design and the design by Khosropour et al. have //Takes 2 n bit values a and b as input.
qubit costs of order O(n) while the qubit cost for the design //Returns the quotient as an n bit number Q and
by Dibbo et al. is of order O(n3 ). We also compared the //the remainder from the division as an n − 1 bit
qubit cost of our proposed design methodology to the designs //number R.
presented by Khosropour et al. and Dibbo et. al. for values of
n ranging from 4 to 512 in table III. We calculated that our 1 R = 0n−1 ; // Where 0n−1 are n − 1 zeros.
proposed design methodology achieves an improvement ratio 2 Q = 0n−1 an−1 ; // Where 0n−1 are n − 1 zeros.
of 25.00% compared to the design by Khosropour et al. We 3 // Q’s least significant bit has the value an−1
determined that our proposed design achieves improvement 4 // an−1 is the most significant bit of a.
ratios ranging from 75.00% to 99.99% compared to the design 5 Q=Q−b
by Dibbo et. al. 6
3) Cost Comparison in Terms of T-depth: The T-depth cost 7 For i = 1 to n − 1
of the proposed design and designs by Khosropour et al. 8 Qn−i = Qn−i
and the proposed design are O(n). A closed-form T-depth 9 Y = Qn−1−i · · · Q0 Rn−2 · · · Rn−1−i
expression is not available for the design by Dibbo et al. We 10 // Where Qn−1−i is the most
calculated that the design by Khosropour et al. has a T-depth 11 // significant bit of Y .
that is 5.6 times higher than the T-depth of the proposed work. 12 If (Qn−i = 0)
13 Y =Y +b
14 Else
V. P ROPOSED D ESIGN OF N ON -R ESTORING Q UANTUM 15 Y =Y −b
I NTEGER D IVISION C IRCUIT 16 End
We now present our proposed non-restoring quantum integer 17 End
division circuit. The proposed design produces no garbage 18
output and has lower T-count and qubit costs compared to 19 If (R < 0)
the existing work. The quantum circuits required to build our 20 R=R+b
proposed quantum non-restoring division circuit are (i) the 21 End
quantum subtractor, (ii) the quantum Add-Sub circuit and (iii) 22 Q0 = Q0
the quantum Ctrl-Add circuit. Our proposed quantum non- 23 Return Q, R
restoring divider saves T gates by not doing computation in
the QFT domain. We also base our design on the T gate Fig. 6: The non-restoring division algorithm.
efficient quantum subtractor, quantum Add-Sub circuit and the
novel quantum Ctrl-Add circuit presented in Section II. The
modules used in our proposed quantum circuit do not produce are initialized to 0. At the end of computation, the quantum
garbage outputs and restore inputs to their original values. register |Bi will be restored to the value b while the quantum
Thus, we are able to save qubits and T gates by placing these register |Ri will have the remainder of the division of a by
quantum circuits such that our proposed quantum restoring b. At the end of computation, the quantum register |Qi will
division circuit will produce no garbage outputs. We are able have the quotient of the division of a by b.
to save additional qubits and T gates because the remainder The proposed methodology is generic in nature and can
will be at most n − 1 bits wide when we divide two n bit design a quantum non-restoring integer division circuit of any
numbers with our proposed divider. size. The steps of the proposed methodology are presented
This proposed quantum integer division circuit calculates along with an illustrative example of the proposed quantum
division by implementing the non-restoring division algorithm. non-restoring integer division circuit for the division of two
The non-restoring division algorithm is illustrated in Figure 6 bit numbers a0 . . . a5 and b0 . . . b5 shown in Figure 7. The
6. Existing research has demonstrated the correctness of the proposed methodology has three steps. A quantum circuit is
non-restoring division algorithm through functionally correct generated for each step of the design.
circuit implementations such as those in [23] [16].
Consider the division of two n bit 2’s complement positive
A. Steps of the Proposed Design Methodology
binary numbers a and b. Let |Bi be a n bit quantum register
where that is initialized to the value b, let |Ri be a n − 1 • Step 1: This step executes line 5 of Algorithm 2 in
quantum register where each register location is initialized quantum hardware. Step 1 is shown for a 6 bit restoring
with the value ai for 0 ≤ i ≤ n − 2 and let |Qi be a n divider in Figure 7a. Apply the quantum registers |Qi
bit quantum register where register location |Q0 i is initialized and |Bi to a quantum subtraction circuit such that, at
with the value an−1 and the remaining n − 1 locations in |Qi the end of computation, the quantum register |Bi is
 8

locations |Yi−1 i through |Y0 i and the values at

|B5:0 i • |B5:0 i |B5:0 i • • |B5:0 i
|R0 i |R0 i
locations |Qn−1−i i to |Q0 i will occupy locations
|R0 i |R0 i
|R1 i |R1 i |R1 i |R1 i |Yn−1 i through |Yi i.
|R2 i |R2 i |R2 i |R2 i – Sub-step 2: This sub-step executes line 8 of Algo-
|R3 i |R3 i |R3 i |R3 i rithm 2 in quantum hardware and prepares location
|R4 i |R4 i |R4 i |R4 i
|Qn−i i for use in subsequent sub-steps.. At quantum
|Q0 i |Q0 i |Q0 i |Q0 i
register location |Qn−i i apply a quantum NOT gate.

Add-Sub
|Q1 i |Q1 i |Q1 i |Q1 i

Subtraction
Subtraction

|Q2 i |Q2 i |Q2 i |Q2 i Location |Qn−i i now has the quotient bit qn−i of
|Q3 i |Q3 i |Q3 i |Q3 i the division of a by b.
|Q4 i |Q4 i
|Q4 i |Q4 i – Sub-step 3: Apply the quantum registers |Bi and
|Q5 i |Q5 i |Q5 i • |Q5 i
|Y i to a quantum Add-Sub circuit such that |Bi
(a) After Step 1 (b) After iteration 1 is unchanged while |Y i will hold the result of
of Step 2 computation.
– Sub-step 4: Apply the quantum register location
|B5:0 i • • • • • • |B5:0 i
|R0 i |R0 i
|Qn−i i to the quantum Add-Sub circuit such that the
|R1 i |R1 i operation of the circuit is conditioned on the value
Add-Sub

|R2 i |R2 i at location |Qn−i i. Location |Qn−i i is unchanged.

Add-Sub

|R3 i |R3 i If |Qn−i i = 0, this step executes line 13 of Algorithm 2.

Add-Sub

|R4 i |R4 i
If |Qn−i i = 1, this step executes line 15 of Algorithm 2.
Add-Sub

|Q0 i |Q0 i
Add-Sub

|Q1 i • |Q1 i • Step 3: This step executes lines 19 through 22 of Algo-

Subtraction

|Q2 i • |Q2 i rithm 2 in quantum hardware. Step 3 is shown for a 6 bit

|Q3 i • |Q3 i restoring divider in Figure 7d. This step has the following
|Q4 i • |Q4 i
three sub-steps:
|Q5 i • |Q5 i
– Sub-step 1: Apply locations |Bn−2 i through |B0 i of
(c) After final iteration of Step 2 quantum register |Bi and quantum register |Ri to a
quantum Ctrl-Add circuit such that locations |Bn−2 i
|B4:0 i • • • • • • • |B4:0 i
|B5 i • • • • • • |B5 i
through |B0 i are unchanged while quantum register
|R0 i |R0 i |Ri is transformed to the remainder.
|R1 i |R1 i – Sub-step 2: Apply location |Q0 i of register |Qi to the
Ctrl-Add
Add-Sub

|R2 i |R2 i quantum Ctrl-Add circuit such that the operation of

Add-Sub

|R3 i |R3 i
the circuit is conditioned on the value at register loca-
Add-Sub

|R4 i |R4 i
tion |Q0 i. Location |Q0 i is unchanged. If |Q0 i = 1,
Add-Sub

|Q0 i • |Q0 i
Add-Sub

|Q1 i • |Q1 i Step 1 and Step 2 execute line 21. After this Sub-step
Subtraction

|Q2 i • |Q2 i 2, quantum register |Ri will contain the remainder

|Q3 i • |Q3 i
of the division of a by b.
|Q4 i • |Q4 i
|Q5 i • |Q5 i
– Sub-step 3: At quantum register location |Q0 i, apply
a quantum NOT gate. Step 3 executes line 23 of
(d) After Step 3 Algorithm 2. Location |Q0 i now has the quotient bit
q0 of the division of a by b. After this step, quantum
Fig. 7: Circuit generation of proposed quantum non-restoring
register |Qi will contain the quotient of the division
division circuit (illustrated with a 6 bit divider).
of a by b.

VI. C OST A NALYSIS OF THE P ROPOSED N ON -R ESTORING

unchanged while quantum register |Qi now has the result
of computation. D IVISION C IRCUIT
• Step 2: this step is repeated n − 1 times and has the fol- A. T-Count Analysis
lowing four sub-steps. This step executes lines 8 through The T-count of the proposed quantum integer division
16 of Algorithm 2 in quantum hardware. Iteration 1 of circuit is illustrated shortly for each step of the proposed
Step 2 is shown for a 6 bit restoring divider in Figure 7b. design methodology:
The final Iteration of Step 2 is shown for a 6 bit restoring • The T-count for Step 1 is 14 · n − 14. We use a quantum
divider in Figure 7c. We show the steps for iteration i subtraction circuit of T-count 14 · n − 14 in this step.
where 1 ≤ i ≤ n − 1. • Step 2 is repeated n − 1 times. The T-count for each
– Sub-step 1: This sub-step executes line 9 of Algo- iteration of Step 2 is 14 · n − 14. We use a quantum
rithm 2 in quantum hardware. Treat the locations Add-Sub circuit of T-count 14 · n − 14 in this step.
|Rn−2 i through |Rn−1−i i of quantum register |Ri • The T-count for Step 3 is 21 · n − 21. We use a quantum
and locations |Qn−1−i i through |Q0 i of register |Qi Ctrl-Add circuit of size n − 1 in this step. We use a
as a combined quantum register |Y i. The values quantum Ctrl-Add circuit of T-count 21 · n − 14 in this
at locations |Rn−2 i through |Rn−1−i i will occupy step.
 9

TABLE IV: Comparison of Quantum Integer Division Circuits

1 2 3 Proposed
T count 28 ·n2 42 · n2
+ 28 · n ≈9· n3 14 · n2 + 7 · n + 7
T-depth NA NA NA 10 · n + 13
qubits 2 · n2 + 5 · n − 1 3 · n2 + 14 · n ≈ 21 n3 + 4 · n 3·n−1
1 and 2 are the designs by Jamal et al. [23] modified to remove garbage output.
3 is the design by Dibbo et al. [13] modified to remove garbage output.
Table entries are marked NA where a closed-form expression is not available for
the designs by Jamal et al. and Dibbo et al.

TABLE V: T-count Comparison of Quantum Integer Division Circuits

n 1 2 3 Proposed % Impr. % Impr. % Impr.

w.r.t. 1 w.r.t. 2 w.r.t. 3
4 448 784 ≈ 576 217 51.56 72.32 ≈ 62.33
8 1792 2912 ≈ 4608 917 48.83 68.51 ≈ 80.10
16 7168 11200 ≈ 36864 3661 48.93 67.31 ≈ 90.07
32 28672 43904 ≈ 294912 14525 49.34 66.92 ≈ 95.07
64 114688 173824 ≈ 2359296 57757 49.64 66.77 ≈ 97.55
128 458752 691712 ≈ 18874368 230237 49.81 66.71 ≈ 98.78
256 1835008 2759680 ≈ 150994944 919261 49.90 66.69 ≈ 99.39
512 7340032 11024384 ≈ 1207959552 3673565 49.95 66.68 ≈ 99.70
Average: 49.75 67.74 90.37
1 and 2 are the designs by Jamal et al. [23] modified to remove garbage output.
3 is the design by Dibbo et al. [13] modified to remove garbage output.

TABLE VI: Qubit Cost Comparison of Quantum Integer Division Circuits

n 1 2 3 Proposed % Impr. % Impr. % Impr.

w.r.t. 1 w.r.t. 2 w.r.t. 3
4 51 104 ≈ 48 11 78.43 89.42 ≈ 77.08
8 167 304 ≈ 288 23 86.23 92.43 ≈ 92.01
16 591 992 ≈ 2112 47 92.05 95.26 ≈ 97.77
32 2207 3520 ≈ 16512 95 95.70 97.30 ≈ 99.42
64 8511 13184 ≈ 131328 191 97.76 98.55 ≈ 99.85
128 33407 50944 ≈ 1049088 383 98.85 99.25 ≈ 99.96
256 132351 200192 ≈ 8389632 767 99.42 99.62 ≈ 99.99
512 526847 793600 ≈ 67110912 1535 99.71 99.81 ≈ 99.99
Average: 93.52 96.46 95.76
1 and 2 are the two designs from Jamal et al. [23] modified to remove garbage output.
3 is the design by Dibbo et al. [13] modified to remove garbage output.

We determine the total T-count by summing the T-count for such as the design in [21] scale as a function of circuit size n.
each step in the design as shown below: Thus, these Ctrl-Add circuits have a T-depth of order O(n).
• Step 1 has a constant T-depth of 10. This T-depth is seen

14 · n − 14 + (14 · n − 14) · (n − 1) + 21 · n − 21 (4) by locations |B1 i through |Bn−2 i of quantum register

|Bi. We use a quantum subtraction circuit of constant
This expression can be simplified to the following: T-depth 10 in this step (where T-depth is independent of
circuit size n).
14 · n2 + 7 · n − 35 (5) • Step 2 is repeated n − 1 times. The ith iteration of Step
2 (where 1 ≤ i ≤ n − 1) has a constant T-depth of 10.
B. T-depth Cost This T-depth is seen by locations |B1 i through |Bn−2 i of
The T-depth of the proposed quantum integer division quantum register |Bi. We use a quantum Add-Sub circuit
circuit is illustrated shortly for each step of the design method- of constant T-depth 10 in this step (where T-depth is
ology. Our proposed design is based on T-depth efficient independent of circuit size n).
• Step 3 has a T-depth of 2 · n. This T-depth is seen by
designs of quantum subtractors, quantum Add-Sub circuits and
quantum Ctrl-Add circuits. We determined that garbageless location |Q0 i of quantum register |Qi. We use a quantum
and T gate optimized quantum subtractor and quantum Add- Ctrl-Add circuit of T-depth 2 · n in this Step.
Sub circuits in the literature such as the designs in [19] have We now illustrate the steps to determine the total T-depth
a T-depth that is constant and independent of the circuit size for the proposed quantum integer division circuit:
n. Thus, these quantum circuits have T-depth of order O(1). 1) Calculate the T-depth for Step 1. Step 1 has a T-depth
We determined as well that Ctrl-Add circuits in the literature of 10. This T-depth is seen by locations |B1 i through
 10

|Bn−2 i of quantum register |Bi. by summing the qubits required for the quotient, remainder,
2) Calculate the T-depth for all iterations of Step 2. The garbage outputs, and primary inputs. We estimated the qubit
total T-depth for all iteration of Step 2 has a T-depth of cost for each design by summing the qubits required for the
10 · (n − 1) because each iteration of Step 2 requires a quotient, remainder, garbage outputs, and primary inputs.
quantum Add-Sub circuit. The total T-depth 10 · (n − 1) 1) Cost Comparison in Terms of T-count: Table IV illus-
simplifies to 10·n−10. This T-depth is seen by locations trates that the T-count cost of the proposed design and the
|B1 i through |Bn−2 i of quantum register |Bi. designs by Jamal et al. are O(n2 ). The design by Dibbo
3) Calculate the T-depth for Step 3. Step 3 has a T-depth of et. al. has a T-count cost of order O(n3 ). Table V shows
2 · n. This T-depth is seen by location |Q0 i of quantum that our proposed design methodology achieves improvement
register |Qi. ratios ranging from 49.95% to 51.56%, 66.68% to 72.32%
4) Determine which qubits see the most T gate layers. We and 62.33% to 99.70% compared to the designs by Jamal et
find after comparing all the qubits in our proposed de- al. and the design by Dibbo et. al. in terms of T-count.
sign, quantum register location |Q0 i of quantum register 2) Cost Comparison in Terms of Qubits: Table IV shows
|Qi and quantum register locations |B1 i through |Bn−2 i that our proposed design has a qubit cost of order O(n) while
of quantum register |Bi see the most T gate layers. the qubit cost for the designs by Jamal et al. are of order
5) Determine the total number of T gate layers seen by O(n2 ). Table IV also illustrates that the design by Dibbo
quantum register location |Q0 i in the proposed design. et. al. has a qubit cost of order O(n3 ). Table VI shows
Quantum register |Q0 i will see a total of 6 · n − 4 T the comparison of our proposed design methodology to the
gate layers because in Step 1 location |Q0 i sees 4 T designs presented by Jamal et al. and Dibbo et. al. for values of
gate layers, in Step 2 location |Q0 i sees 4 · (n − 2) T n ranging from 4 to 512 in terms of qubit cost. We calculated
gate layers and in Step 2 location |Q0 i sees 2 · n T that our proposed design methodology achieves improvement
gate layers. The total number of T gate layers seen by ratios ranging from 78.43% to 99.71%, 89.42% to 99.81%
location |Q0 i is 4 + 4 · (n − 2) + 2 · n which simplifies and 77.08% to 99.99% compared to the designs by Jamal et
to 6 · n − 4. al. and the design by Dibbo et. al.
6) Determine the total number of T gate layers seen by 3) Cost Comparison in Terms of T-depth: The T-depth cost
quantum register locations |B1 i through |Bn−2 i in of the proposed design is O(n). A closed-form expression is
the proposed design. Quantum register locations |B1 i not available for the designs by Jamal et al. and the design by
through |Bn−2 i will see a total of 10·n+13 T gate layers Dibbo et al. for the T-depth.
because in Step 1 locations |B1 i through |Bn−2 i see 10
T gate layers, in Step 2 locations |B1 i through |Bn−2 i VII. C ONCLUSION
sees 10 · (n − 1) T gate layers and in Step 3 locations In this work, we have proposed two designs for quantum
|B1 i through |Bn−2 i see 13 T gate layers. The total circuit integer division based on Clifford+T gates. The first
number of T gate layers seen by locations |B1 i through quantum integer division circuit proposed is based on the
|Bn−2 i is 10 + 10 · (n − 1) + 13 which simplifies to restoring division algorithm and the second is based on the
10 · n + 13. non-restoring division algorithm. We also show the design of
7) Determine which qubits see the most T gate layers. We components used in our proposed quantum integer division
determined that locations |B1 i through |Bn−2 i see more circuits such as the quantum subtraction circuit, quantum
T gate layers than register location |Q0 i because 10·n+ Add-Sub circuit and quantum Ctrl-Add circuit. The proposed
13 > 6 · n − 4. quantum restoring division circuit is shown to be superior
Thus, our proposed design has a T-depth of 10 · n + 13 to existing designs in terms of T-depth, T-count and qubits.
and this T-depth is seen by locations |B1 i through |Bn−2 i of Likewise, the proposed quantum non-restoring division circuit
quantum register |Bi. is shown to be superior to existing designs in terms of T-
count and qubits. We conclude that the proposed restoring
division circuit or proposed non-restoring division circuit can
C. Cost Comparison be integrated in a larger quantum data path system design
Comparison of the proposed design with the current state where T-count and T-depth are of primary concern.
of the art are presented in Tables IV, V and VI. We compare
our proposed design to the existing quantum non-restoring R EFERENCES
division circuits by Jamal et al. [23] and the alternative design [1] P. Selinger et al., The Quipper System, 2016, available at:
methodology presented in Dibbo et. al. [13]. To perform the http://www.mathstat.dal.ca/ selinger/quipper/doc/.
[2] S. Hallgren, “Polynomial-time quantum algorithms for pell’s
comparison we implemented each design with Clifford+T equation and the principal ideal problem,” J. ACM, vol. 54,
gates. To realize reversible gates such as the Toffoli gate, no. 1, pp. 4:1–4:19, Mar. 2007. [Online]. Available:
we use the Clifford+T implementations presented in [8]. As http://doi.acm.org/10.1145/1206035.1206039
[3] W. van Dam and S. Hallgren, “Efficient Quantum Algorithms for
ahown in [8], the Toffoli gate has a T-count of 7 and a T- Shifted Quadratic Character Problems,” eprint arXiv, Nov. 2000.
depth of 3. We also apply the Bennett’s garbage removal [Online]. Available: https://arxiv.org/abs/quant-ph/0011067
scheme illustrated in [22] to remove the garbage outputs from [4] W. van Dam, S. Hallgren, and L. Ip, “Quantum algorithms
for some hidden shift problems,” SIAM Journal on Computing,
each design presented by Jamal et al. and Dibbo et. al. We vol. 36, no. 3, pp. 763–778, 2006. [Online]. Available:
determined the qubit cost for each design in Jamal et. al. https://doi.org/10.1137/S009753970343141X
 11

[5] D. Wecker et al., Language-Integrated Quantum Operations:

LIQUi|i, 2016, available at: https://www.microsoft.com/en-
us/research/project/language-integrated-quantum-operations-liqui/.
[6] E. Fredkin and T. Toffoli, “Conservative logic,” International Journal
of Theoretical Physics, vol. 21, no. 3, pp. 219–253, 1982. [Online].
Available: http://dx.doi.org/10.1007/BF01857727
[7] X. Zhou, D. W. Leung, and I. L. Chuang, “Methodology for quantum
logic gate construction,” Phys. Rev. A, vol. 62, p. 052316, Oct 2000. [On-
line]. Available: https://link.aps.org/doi/10.1103/PhysRevA.62.052316
[8] M. Amy, D. Maslov, M. Mosca, and M. Roetteler, “A meet-in-the-
middle algorithm for fast synthesis of depth-optimal quantum circuits,”
IEEE Transactions on Computer-Aided Design of Integrated Circuits
and Systems, vol. 32, no. 6, pp. 818–830, June 2013.
[9] A. Paler, I. Polian, K. Nemoto, and S. J. Devitt, “Fault-tolerant, high-
level quantum circuits: form, compilation and description,” Quantum
Science and Technology, vol. 2, no. 2, p. 025003, 2017. [Online].
Available: http://stacks.iop.org/2058-9565/2/i=2/a=025003
[10] D. Gosset, V. Kliuchnikov, M. Mosca, and V. Russo, “An
algorithm for the t-count,” Quantum Information & Computation,
vol. 14, no. 15-16, pp. 1261–1276, 2014. [Online]. Available:
http://www.rintonpress.com/xxqic14/qic-14-1516/1261-1276.pdf
[11] A. Khosropour, H. Aghababa, and B. Forouzandeh, “Quantum division
circuit based on restoring division algorithm,” in Information Technol-
ogy: New Generations (ITNG), 2011 Eighth International Conference
on. IEEE, 2011, pp. 1037–1040.
[12] L. Jamal and H. M. H. Babu, “Efficient approaches to design a reversible
floating point divider,” in 2013 IEEE International Symposium on
Circuits and Systems (ISCAS2013), May 2013, pp. 3004–3007.
[13] S. V. Dibbo, H. M. H. Babu, and L. Jamal, “An efficient design technique
of a quantum divider circuit,” in 2016 IEEE International Symposium
on Circuits and Systems (ISCAS), May 2016, pp. 2102–2105.
[14] V. Kliuchnikov, D. Maslov, and M. Mosca, “Fast and efficient exact
synthesis of single-qubit unitaries generated by clifford and t gates,”
Quantum Info. Comput., vol. 13, no. 7-8, pp. 607–630, Jul. 2013.
[Online]. Available: http://dl.acm.org/citation.cfm?id=2535649.2535653
[15] H. Thapliyal, T. S. S. Varun, and E. Muñoz-Coreas, “Quantum circuit
design of integer division optimizing ancillary qubits and t-count,” in
16th Asian Quantum Information Science Conference, August 2016, pp.
197–199.
[16] H. Thapliyal, T. S. S. Varun, E. Muñoz-Coreas, K. A. Britt, and T. S.
Humble, “Quantum circuit designs of integer division optimizing t-count
and t-depth,” in 2017 IEEE International Symposium on Nanoelectronic
and Information Systems (iNIS), Dec 2017, pp. 123–128.
[17] IBM, Quantum Computing - IBM Q, 2017, available at:
https://www.research.ibm.com/ibm-q/.
[18] C. Song, K. Xu, W. Liu, C.-p. Yang, S.-B. Zheng, H. Deng, Q. Xie,
K. Huang, Q. Guo, L. Zhang, P. Zhang, D. Xu, D. Zheng, X. Zhu,
H. Wang, Y.-A. Chen, C.-Y. Lu, S. Han, and J.-W. Pan, “10-Qubit
Entanglement and Parallel Logic Operations with a Superconducting
Circuit,” Physical Review Letters, vol. 119, no. 18, p. 180511, Nov.
2017.
[19] H. Thapliyal, “Mapping of subtractor and adder-subtractor circuits on
reversible quantum gates,” in Transactions on Computational Science
XXVII. Springer, 2016, pp. 10–34.
[20] H. Thapliyal and N. Ranganathan, “Design of efficient reversible logic-
based binary and bcd adder circuits,” ACM Journal on Emerging
Technologies in Computing Systems (JETC), vol. 9, no. 3, p. 17, 2013.
[21] E. Muñoz-Coreas and H. Thapliyal, “T-count Optimized Design of
Quantum Integer Multiplication,” ArXiv e-prints, Jun. 2017. [Online].
Available: https://arxiv.org/abs/1706.05113
[22] C. H. Bennett, “Logical reversibility of computation,” IBM J. Res.
Dev., vol. 17, no. 6, pp. 525–532, Nov. 1973. [Online]. Available:
http://dx.doi.org/10.1147/rd.176.0525
[23] L. Jamal and H. M. H. Babu, “Efficient approaches to design a reversible
floating point divider,” in 2013 IEEE International Symposium on
Circuits and Systems (ISCAS2013), May 2013, pp. 3004–3007.