CEG 3155: Digital Systems II

(Fall 2024)
Prof. Rami Abielmona
Possible Solutions of Assignment #1: Logical
Function Optimization

October 1, 2024

Question I
This question is about the optimization of logical functions using algebraic ma-
nipulation.

Part a
With the canonical products-of-sums for f, we Obtained:

f = x1 · x2 · x3 + x1 · x2 · x3 + x1 · x2 · x3 + x1 · x2 · x3 + x1 · x2 · x3 + x1 · x2 · x3 + x1 · x2 · x3 (1)

= x1 (x2 ·x3 +x2 ·x3 +x2 ·x3 +x2 ·x3 )+x2 (x1 ·x3 +x1 ·x3 +x1 ·x3 +x1 ·x3 )+x3 (x1 ·x2 +x1 ·x2 +x1 ·x2 +x1 ·x2 )
= x1 (x2 · 1 + x2 · 1) + x2 (x1 · 1 + x1 · 1) + x3 (x1 · 1 + x1 · 1)
= x1 (x2 · x2 ) + x2 (x1 · x1 ) + x3 (x1 · x1 )
= x1 · 1 + x2 · 1 + x3 · 1
= x1 + x2 + x3 (2)

Part b
With the canonical products-of-sums for f, we Obtained:

f = (x1 +x2 +x3 )(x1 +x2 +x3 )(x1 +x2 +x3 )(x1 +x2 +x3 )·(x1 +x2 +x3 )(x1 +x2 +x3 )(x1 +x2 +x3 ) (3)

= ((x1 +x2 +x3 )(x1 +x2 +x3 ))((x1 +x2 +x3 )(x1 +x2 +x3 ))·((x1 +x2 +x3 )(x1 +x2 +x3 ))((x1 +x2 +x3 )(x1 +x2 +x3 ))
= (x1 + x2 + x3 · x3 )(x1 + x2 + x3 · x3 )(x1 + x2 + x3 · x3 )(x1 + x2 · x2 + x3 )
= (x1 + x2 )(x1 + x2 )(x1 + x2 )(x1 + x3 )

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 = (x1 + x2 · x2 )(x1 + x2 · x3 )
= x1 (x1 + x2 · x3 )

= x1 · x1 + x1 · x2 · x3

= x1 · x2 · x3 (4)

Partie c
P
One minimum SOP expression for the function f (x1 , x2 , x3 ) = m(3, 4, 6, 7)
is

f = x1 · x2 + x1 · x3 + x1 · x3 (5)

The corresponding circuit realized through NAND gates is presented

in Figure 1.

Figure 1: Circuit of part c

Part d
P
A minimum cost POS expression for the function f (x1 , x2 , x3 ) = m(3, 4, 6, 7)
is

f = (x1 + x3 )(x1 + x2 + x3 ) (6)

The corresponding circuit realized through NOR gates is presented in

Figure 2.

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 Figure 2: Circuit of part d

Part e
With the two functions:

f (x, y, z) = x · y + y · z + x · z + x · y (7)
g(x, y, z) = x · y + x · y + x · y · z (8)

We can represent them in their canonical form:

f (x, y, z) = x · y · (z + z) + (x + x) · y · z + x · (y + y) · z + x · y · (z + z)

=x·y·z+x·y·z+x·y·z+x·y·z+x·y·z (9)
g(x, y, z) = x · y + x · y + x · y · z = x · y · (z + z) + x · y · (z + z) + x · y · z
=x·y·z+x·y·z+x·y·z+x·y·z+x·y·z (10)
Since the two canonical forms of Equations 9 and 10 are identical,
they represent the same Boolean function.

Question II
This question is about synthesis with multiple outputs and levels.

Part a
P
The simplest realization of the function f (x1 , ..., x4 ) = m(0, 3, 4, 7, 9, 10, 13, 14),
given that logic gates have a maximum fan-in of two, is:

f = x1 · g + x1 · g (11)

où g = x3 · x4 + x3 · x4 .

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Part b
If we set D(0, 20) = 0 and D(15, 26) = 1, the decomposition gives

g = x5 (x1 + x2 )

f = (x3 · x4 + x3 · x4 )g + x3 · x4 · g = x3 · x4 · g + x3 · x4 · g + x3 · x4 · g
The cost of the circuit is 9 + 18 = 27. Hence, the best SOP form is:

f = x3 · x4 · x5 + x1 · x3 · x4 · x5 + x1 · x3 · x4 · x5 + x2 · x3 · x4 · x5 + x2 · x3 · x4 · x5

The cost of the circuit is 7 + 29 = 36, we reduced the cost by 9 by

using functional decomposition.

Part c
Karnaugh map with five variables is divided by two Karnaugh maps of
four variables. The left map in figure 3 contains minterms with a =
0 and the right map contains minterms with a = 1.

Figure 3: Karnaugh Map with five variables

We can group the two maps in one as in figure 4.

Figure 4: Minimized Karnaugh Map

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 We can then reduce the map in two steps: (i) group all terms with
1’s and d’s (figure 5), puis (ii) group all terms with variables with
1’s et d’s adjacent (figure 5).

Figure 5: Two steps of minimization

The first step gives f (a, b, c, d, e) = b · c · d + b · c · d, the second step

gives our final minimized function f (a, b, c, d, e) = a · c · e + a · b · d + b ·
c · d + b · c · d.

Part d
By using Karnaugh maps for each function, we obtain the following boolean
expressions,

f1 = a · c · d + b · c · d + a · d + b · c · d

f2 = a · b + b · c · d + a · c + b · c · d
f3 = a · b · c + a · b · c + a · b · c + a · c
There are 12 terms of product in original expressions. 4 of them
may be shared, thus we can rewrite the functions as:

f1 = W + X + a · d + Z (12)

f2 = a · b + X + Y + Z (13)
f3 = W + a · b · c + Y + a · b · b (14)
où W = a · b · d, X = b · c · d, Y = a · c, et Z = b · c · d.

Question III
This question is about components of combinatorial circuits.

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Partie a
Shannon’s expansion with w2 gives

fw2 = w2 (1 + w1 · w3 + w1 · w3 ) + w2 (w1 · w3 + w1 · w3 )

= w1 · w2 · w3 + w1 · w2 · w3 + w2 + w1 · w2 · w3 + w1 · w2 · w3
Successive Shannon’s expansion with w1 gives

fw1 = w1 (w2 · w3 + w2 · w3 + w2 ) + w1 (w2 · w3 + w2 · w3 + w2 )

= w1 · w2 · w3 + w1 · w2 · w3 + w1 · w2 + w1 · w2 · w3 + w1 · w2 · w3 + w1 · w2
Successive Shannon’s expansion with w3 gives

fw3 = w3 (w1 ·w2 +w1 ·w2 +w1 ·w2 +w1 ·w2 )+w3 (w1 ·w2 +w1 ·w2 +w1 ·w2 +w1 ·w2 )

= w1 · w2 · w3 + w1 · w2 · w3 + w1 · w2 · w3 + w1 · w2 · w3 + w1 · w2 · w3 + w1 · w2 · w3

Partie b
Shannon’s expansion with w1 gives

fw1 = w1 · w2 + w1 · w3 + w1 · w2

Successive Shannon’s expansion with w2 gives

fw2 = w2 (w1 · w3 ) + w2 (w1 + w1 + w1 · w3 )

= w1 · w2 + w1 · w2 · w3 + w1 · w2 · w3 + w1 · w2
Successive Shannon’s expansion with w3 gives

fw3 = w3 (w1 · w2 + w1 · w2 + w1 · w2 + w1 · w2 ) + w3 (w1 · w2 + w1 · w2 )

= w1 · w2 · w3 + w1 · w2 · w3 + w1 · w2 · w3 + w1 · w2 · w3 + w1 · w2 · w3

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Partie c
First, let’s define a set of intermediate variables:

i0 = w7 · w6 · w5 · w4 · w3 · w2 · w1 · w0

i1 = w7 · w6 · w5 · w4 · w3 · w2 · w1
i2 = w7 · w6 · w5 · w4 · w3 · w2
i3 = w7 · w6 · w5 · w4 · w3
i4 = w7 · w6 · w5 · w4
i5 = w7 · w6 · w5
i6 = w7 · w6
i7 = w7
An traditional binary encoder may be used to realize the priority encoder:

y0 = i1 + i3 + i5 + i7

y1 = i2 + i3 + i6 + i7
y2 = i4 + i5 + i6 + i7

Partie d
First, functions must be written in canonical form.

f1 (a, b, c) = a · b · c + a · b · c + a · b · c

f2 (a, b, c) = a · b · c + a · b · c + a · b · c + a · b · c
The input variables a, b, et c are connected to the decoder address
inputs; the decoder outputs corresponding to the terms of the given
functions are connected to the inputs of the two NAND gates. The resulting
circuit is shown in figure 6. Note the following expressions for this
decoder: D0 = a · b · c, D1 = a · b · c, D2 = a · b · c, D3 = a · b · c, D4 =
a · b · c, D5 = a · b · c, D6 = a · b · c, et D7 = a · b · c.

Partie e
The decoder 6to64 is shown in figure 7 below.

Question IV
This question relates to VHDL at the structural level.

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 Figure 6: Realization of f1 et f2

Part a
The entities if2to4 and h3to8 are coded in VHDL as shown below:
LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY if2to4 IS
PORT (w : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
En : IN STD_LOGIC;
y : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END if2to4;

ARCHITECTURE Behavior OF if2to4 IS

BEGIN
PROCESS (En, w)
BEGIN
IF En = ’0’ THEN
y <= "0000";
ELSE
IF w = "00" THEN
y <= "0001";
ELSIF w = "01" THEN
y <= "0010";
ELSIF w = "10" THEN
y <= "0100";
ELSE

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 y <= "1000";
END IF;
END IF;
END PROCESS;
END Behavior;

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY h3to8 IS PORT (

w : IN STD_LOGIC VECTOR(2 DOWNTO 0);
En : IN STD_LOGIC;
y : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END h3to8;

ARCHITECTURE Structure OF h3to8 IS

SIGNAL EnableTop, EnableBot : STD_LOGIC ;
COMPONENT if2to4
PORT (w : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
En : IN STD_LOGIC;
y : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;

BEGIN
EnableTop <= w(2) AND En;
EnableBot <= (NOT w(2)) AND En;

Decoder1: if2to4 PORT MAP (w(1 DOWNTO 0), EnableBot, y(3 DOWNTO 0));
Decoder2: if2to4 PORT MAP (w(1 DOWNTO 0), EnableTop, y(7 DOWNTO 4));
END Structure;

Partie b
The entities h6to64 are coded in VHDL as shown below:

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY h6to64 IS PORT (

w : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
En : IN STD_LOGIC;
y : OUT STD_LOGIC_VECTOR(63 DOWNTO 0));
END h6to64;

ARCHITECTURE Structure OF h6to64 IS

SIGNAL Enables : STD_LOGIC_VECTOR(7 DOWNTO 0);

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 COMPONENT h3to8
PORT (w : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
En : IN STD_LOGIC;
y : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END COMPONENT;

BEGIN
root: h3to8 PORT MAP (w(5 DOWNTO 3), En, Enables);
leaf0: h3to8 PORT MAP (w(2 DOWNTO 0), Enables(0), y(7 DOWNTO 0));
leaf1: h3to8 PORT MAP (w(2 DOWNTO 0), Enables(1), y(15 DOWNTO 8));
leaf2: h3to8 PORT MAP (w(2 DOWNTO 0), Enables(2), y(23 DOWNTO 16));
leaf3: h3to8 PORT MAP (w(2 DOWNTO 0), Enables(3), y(31 DOWNTO 24));
leaf4: h3to8 PORT MAP (w(2 DOWNTO 0), Enables(4), y(39 DOWNTO 32));
leaf5: h3to8 PORT MAP (w(2 DOWNTO 0), Enables(5), y(47 DOWNTO 40));
leaf6: h3to8 PORT MAP (w(2 DOWNTO 0), Enables(6), y(55 DOWNTO 48));
leaf7: h3to8 PORT MAP (w(2 DOWNTO 0), Enables(7), y(63 DOWNTO 56));
END Structure;

Part c
By using an arrangement as in figure 6.56 in your manual, the desired
circuit can be specified in the next truth table:

Lef t Right h y3 y2 y1 y0 k
0 0 0 w3 w2 w1 w0 0
0 1 1 w0 w3 w2 w1 w0
1 0 w3 w2 w1 w0 w3 0

By using multiplexer, the truth table can be realized as in figure

8.

Question V
This question relates to the ASM method. Review Lessons and Lab #1 to get
a deeper idea of this technique of systematically designing digital circuits. A
four-bit counter should be designed to count in the following order: 0000 →
0001 → 0011 → 0010 → 0110 → 0111 → 0101 → 0100 → 1100 → 1101 →
1111 → 1110 → 0000 → etc. The counter starts at the state 0000 and when the
command singal START is ON.

Part a
There are many different pseudo-codes that will solve this problem,
one of which is presented below. This pseudo-code uses the concept

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that an exclusive-or gate can compare two numbers and produce the bit
difference between the two.

1. CGC ← 0000; step ← 0

2. if (START)
• if (step = 3)
– CGC ← CGC XOR 0100;
• else if (step = 7)
– CGC ← CGC XOR 1000;
• else if (step = 11)
– Return to step #1;
• else if (step = 1) or (step = 5) or (step = 9)
– CGC ← CGC XOR 0010;
• else
– CGC ← CGC XOR 0001;
else

• Return to step #1;

3. step++; Return to step #2;

Part b
Check figure 9 for the ASM diagram, figure 10 for the datapath, figure
11 for the detailed ASM diagram, and finally figure 12 for the controlpath.
Note that we could solve this problem using a finite state machine
(as we will see in the following discussion), and that we could use
the state flip-flops as the output of our module, CGC, but we took
the output of the Gray Code Counter (CGC) as the output of a set of
1-bit registers.

Bonus Question
An overflow occurs when two numbers of the 2’s complement are added,
if the input carry-in of the sign bit is different from the output
carry-out of the sign bit. The sign bit, in this case, is the most
significant bit (MSB). Therefore, the exclusive-or of the carry-in
and the carry-out of the most significant bit (MSB), produces the overflow
bit. Refer to Table 1 for a clearer explanation.

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 Sign Sign Carry Carry Sign Sign Overflow ? Carry in Notes
A B in out of the result of the correct result XOR
result Carry out
0 0 0 0 0 0 No 0
0 0 1 0 1 0 Yes 1 Different Carry
0 1 0 0 1 1 No 0 |A| < |B|
0 1 1 1 0 0 No 0 |A| > |B|
1 0 0 0 1 1 No 0 |A| > |B|
1 0 1 1 0 0 No 0 |A| < |B|
1 1 0 1 0 1 Yes 1 Different Carry
1 1 1 1 1 1 No 0

Table 1: Table Explaining Detection of Overflow

Thanks
Answers and figures for questions in the manual are taken from the Companion
Guide Fundamentals of Digital Logic with VHDL Design by Stephen Brown and
Zvonko Vranesic.

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Figure 7: Decoder 6-to-64
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Figure 8: Réalisation d’un circuit de décalage

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Figure 9: ASM Diagrma

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Figure 10: ASM Datapath

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Figure 11: Detailed ASM Diagram

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Figure 12: ASM Controlpath

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