CEG 3155: Digital Systems II

(Fall 2024)
Prof. Rami Abielmona
Possible Solutions for Assignment #2:
Arithmetic Circuits

October 03, 2024

Question I
This question is concerned with the construction of a half and full ternary adder.
Parts a and b are questions 3.25 and 3.26 of your textbook.

Part a
The half ternary adder can be defined using binary encoded signals
as following:

A B Carry out Sum

a1 a0 b1 b0 cout s1 s0
0 0 0 0 0 0 0
0 0 0 1 0 0 1
0 0 1 0 0 1 0
0 1 0 0 0 0 1
0 1 0 1 0 1 0
0 1 1 0 1 0 0
1 0 0 0 0 1 0
1 0 0 1 1 0 0
1 0 1 0 1 0 1

The remaining 7 combinations (out of 16) where a1 = a0 = 1, or

b1 = b0 = 1, can be treated as don’t care conditions. So the expressions
for the minimum cost are:

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 cout = a0 · b0 + a1 · b1 + a1 · b0 (1)

s1 = a0 · b0 + a1 · a0 · b1 + a1 · b1 · b0 (2)
s0 = a1 · b1 + a1 · a0 · b0 + a0 · b1 · b0 (3)

Part b
The full-ternary adder can be defined in the truth table in table 1.

cin A B cout Sum

0 0 0 0 0
0 0 1 0 1
0 0 2 0 2
0 1 0 0 1
0 1 1 0 2
0 1 2 1 0
0 2 0 0 2
0 2 1 1 0
0 2 2 1 1
1 0 0 0 1
1 0 1 0 2
1 0 2 1 0
1 1 0 0 2
1 1 1 1 0
1 1 2 1 1
1 2 0 1 0
1 2 1 1 1
1 2 2 1 2

Table 1: Truth Table for Question 1b

Using binary encoded signals, we get the truth table shown in table
2.
The remaining 14 combinations (out of 32) where ‘u a1 = a0 = 1, ou
b1 = b0 = 1, can be treated as don’t care conditions. So the expressions
for the minimum cost are:

cout = a0 · b1 + a1 · b0 + a1 · b1 + a1 · cin + b1 · cin + a0 · b0 · cin (4)

s1 = a0 ·b0 ·cin +a1 ·a0 ·b1 ·cin +a1 ·b1 ·b0 ·cin +a1 ·b1 ·cin +a1 ·a0 ·b0 ·cin +a0 ·b1 ·b0 ·cin (5)
s0 = a1 ·b1 ·cin +a1 ·a0 ·b1 ·cin +a0 ·b1 ·b0 ·cin +a1 ·b0 ·cin +a0 ·b1 ·cin +a1·a0 ·b1 ·b0 ·cin (6)

2
 A B Carry out Sum
cin a1 a0 b1 b0 cout s1 s0
0 0 0 0 0 0 0 0
0 0 0 0 1 0 0 1
0 0 0 1 0 0 1 0
0 0 1 0 0 0 0 1
0 0 1 0 1 0 1 0
0 0 1 1 0 1 0 0
0 1 0 0 0 0 1 0
0 1 0 0 1 1 0 0
0 1 0 1 0 1 0 1
1 0 0 0 0 0 0 1
1 0 0 0 1 0 1 0
1 0 0 1 0 1 0 0
1 0 1 0 0 0 1 0
1 0 1 0 1 1 0 0
1 0 1 1 0 1 0 1
1 1 0 0 0 1 0 0
1 1 0 0 1 1 0 1
1 1 0 1 0 1 1 0

Table 2: Truth Table of Question 1b

Table 3: Table 1

Question II
This question is concerned with the row multiplier circuit. Part a is question
3.15 of your textbook.

Part a
The longest path, which causes the critical delay, is entries m0 and
m1 at the output p7 , indicated by the dashed path in the figure 1.
Propagation through block A involves a delay of one gate in the AND
logic gate shown in Figure 5.32b and two delays to produce the full-adder
output carry-out. Then in each of blocks B, C, D, E, F, G, and H,
two more delays are needed to produce the output signals carry-out
in the circuits shown by figure 5.32c. Therefore, the total delay
along the critical path is 17 logic gate delays.

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 Figure 1: Row Multiplier

Part b
The greatest value of an n-digit number, if unsigned in the base B,
is B n −1. This square value gives us the greatest possible result
of B 2n − 2B n + 1. This value is smaller than B 2n − 1, and therefore
can be represented using 2n digits.
So, multiplying two n-digit numbers will always yield a product which
can be represented in 2n digits.

Question III
This question relates to the state transition tables. Parts a, b and c are questions
6.9, 6.10 and 6.23 in your textbook.

Part a
To compare two individual bits, we let k = w1 ⊕w2 . So, appropriate
state and transition tables can be as shown in the table .
Finally, the design equations are:

Y2 = k · y1 + k · y2

Y1 = k · y1 + k · y2
z = k · y1 · y2

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 Present Next State Yield
Present Next State Yield
état k=0 k=1
état k=0 k=1 k= 0 k=1
y2 y1 Y2 Y1 Y2 Y1 k=0 k=1
A B A 0 0
A→ 00 01 00 0 0
B C A 0 0
B→ 01 10 00 0 0
C D A 0 0
C→ 10 11 00 0 0
D D A 1 0
D→ 11 11 00 1 0

Table 4: State and Transition Tables of Question IIIa

Part b
The Question IIIb entity is encoded in VHDL as below:

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY questionIIIb IS
PORT (i_clock : IN STD_LOGIC;
i_resetb : IN STD_LOGIC;
i_w1, i_w2 : IN STD_LOGIC;
o_z : OUT STD_LOGIC);
END questionIIIb;

ARCHITECTURE Behavior OF questionIIIb IS

TYPE stateType IS (A, B, C, D);
SIGNAL int_state: stateType;
SIGNAL int_k: STD_LOGIC;
BEGIN
int_k <= i_w1 XOR i_w2;
PROCESS (i_resetb, i_clock)
BEGIN
IF (i_resetb = ’0’) THEN
int_state <= A;
ELSIF (i_clock’EVENT AND i_clock = ’1’) THEN
CASE int_state IS
WHEN A =>
IF int_k = ’0’ THEN
y <= B;
ELSE y <= A;
END IF;
WHEN B =>
IF int_k = ’0’ THEN

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 Present Next State Yield
Present Next State Yield
état w=0 w=1
état w=0 w=1 z2 z1 z0
y2 y1 y0 Y2 Y1 Y0 Y2 Y1 Y0 z2 z1 z0
A A B 0 0 0
A→ 000 000 001 0 0 0
B B C 0 0 1
B→ 001 001 010 0 0 1
C C D 0 1 0
C→ 010 010 011 0 1 0
D D E 0 1 1
D→ 011 011 100 0 1 1
E E F 1 0 0
E→ 100 100 101 1 0 0
F F A 1 0 1
F→ 101 101 000 1 0 1

Table 5: State and Transition Tables of Question IIIc

y <= C;
ELSE y <= A;
END IF;
WHEN C =>
IF int_k = ’0’ THEN
y <= D;
ELSE y <= A;
END IF;
WHEN D =>
IF int_k = ’0’ THEN
y <= D;
ELSE y <= A;
END IF;
END CASE;
END IF;
END PROCESS;

z <= ’1’ WHEN int_state = D and int_k = ’0’ ELSE

’0’;
END Behavior;

Part c
Appropriate state and transition tables can be as shown in the table
5.
Finaly, the design equations are:

Y2 = y0 · y2 + w · y2 + w · y0 · y1

Y1 = y0 · y1 + w · y1 + w · y0 · y1 · y2
Y0 = w · y0 + w · y0
z2 = y2

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 z1 = y1
z0 = y0

Question IV
This question relates to Mealy and Moore type FSMs. The diagrams used are
figures 6.43 and 6.47 in your manual.

The synchronization diagram of the FSMs is shown in figure 2. We can

see that the sum of a Mealy machine changes with inputs, a and b, while
the sum of a Moore machine changes a clock period after the change
in the output of the Mealy Machine. This is caused by the state flip-flop
used in figure 8.47 in your manual to produce the present state variable
y1 and the output s.

Figure 2: Synchronization Diagram

Bonus Question
Demonstrate, using a synchronization diagram, the correct operation of a D
flip-flop, shown in figure 3 and presented in class.
The synchronization diagram which correctly demonstrates the operation
of a type D flip-flop is shown in figure 4. Note that the labels indicate
the following states:

• When the clock is high, the master latch maintains its output
values , (int D and int DBar ), while the slave latch saves its
data when it exits (Q and QBar );

• When the clock is low, the master latch records its data at its
outputs, while the slave latch maintains its output values.

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 Figure 3: D Flip-Flop in Master-Slave Configuration

Figure 4: Synchronization Diagram of a D flip-flop

So when the clock is high the input changes (D ) are ignored until
the next edge of the clock, while when the clock is low, changes to
slave latch inputs are ignored until the next edge of the clock. The
result is that the changes of the input D are only observed at the
output Q at the transition from low to high of the clock (assuming
flip-flops are triggered by positive pulse front).

Thanks
The answers and figures related to the questions in the textbook are taken
from the manual Coaching Guide for Fundamentals of Digital Logic with VHDL
Design by Stephen Brown and Zvonko Vranesic.