Shri VaishnavSM Institute of Technology & Science, Indore

Discipline Department of Electrical & Electronics Engineering Pages: 1/5

Subject Name: Digital Logic and Circuit Design Sub. Code: BTEC104 Experiment No.: 04

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EXPERIMENT NO. – 04

1.0 Aim: -
To compare and verify Standard SOP/POS expression with minimized Boolean form using
K-map.

2.0 Objectives: -
2.1 Usage of K-map to simplify Boolean function
2.2 To design combinational circuits that do a predefined task

3.0 Pre – Requisites: -

3.1 Knowledge of Binary Number System.
3.2 Knowledge of pin diagrams of all logic gates.
3.3 Knowledge of truth table of all logic gates

4.0 Apparatus Requirements: -

4.1 DC Power Supply (5 Volt)
4.2 IC’s of logic gates (AND, OR, X-OR, and NOT)
4.3 Breadboard
4.4 SPDT Switches
4.5 LED’s
4.6 Resistors
4.7 Connecting Wires

5.0 Theory: -
In previous chapters, we have simplified the Boolean functions using Boolean postulates and
theorems. It is a time consuming process and we have to re-write the simplified expressions after
each step.
5.1 Karnaugh map method or K-map method
To overcome this difficulty, Karnaugh introduced a method for simplification of Boolean
functions in an easy way. This method is known as Karnaugh map method or K-map method. It
is a graphical method, which consists of 2n cells for ‘n’ variables. The adjacent cells are differed
only in single bit position.

K-Maps for 2 to 5 Variables

K-Map method is most suitable for minimizing Boolean functions of 2 variables to 5 variables.
Now, let us discuss about the K-Maps for 2 to 5 variables one by one.
Study Group. Digital Electronics Modified by: Nitin Saravagi
Created by: Nitin Saravagi Date of Creation: 10/11/2022 Date of Modification:
Rev. No. EC/DE/01/2022 Approved by: HOD
 Shri VaishnavSM Institute of Technology & Science, Indore
Discipline Department of Electrical & Electronics Engineering Pages: 2/5
Subject Name: Digital Logic and Circuit Design Sub. Code: BTEC104 Experiment No.: 04

2 Variable K-Map
The number of cells in 2 variable K-map is four, since the number of variables is two. The
following figure shows 2 variable K-Map.

There is only one possibility of grouping 4 adjacent min terms.

The possible combinations of grouping 2 adjacent min terms are {(m0, m1), (m2, m3), (m0, m2)
and (m1, m3)}.

3 Variable K-Map
The number of cells in 3 variable K-map is eight, since the number of variables is three. The
following figure shows 3 variable K-Map.

There is only one possibility of grouping 8 adjacent min terms.

The possible combinations of grouping 4 adjacent min terms are {(m0, m1, m3, m2), (m4, m5,
m7, m6), (m0, m1, m4, m5), (m1, m3, m5, m7), (m3, m2, m7, m6) and (m2, m0, m6, m4)}.
The possible combinations of grouping 2 adjacent min terms are {(m0, m1), (m1, m3), (m3, m2),
(m2, m0), (m4, m5), (m5, m7), (m7, m6), (m6, m4), (m0, m4), (m1, m5), (m3, m7) and (m2,
m6)}.
If x=0, then 3 variable K-map becomes 2 variable K-map.

4 Variable K-Map
The number of cells in 4 variable K-map is sixteen, since the number of variables is four. The
following figure shows 4 variable K-Map.

Study Group. Digital Electronics Modified by: Nitin Saravagi

Created by: Nitin Saravagi Date of Creation: 10/11/2022 Date of Modification:
Rev. No. EC/DE/01/2022 Approved by: HOD
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Subject Name: Digital Logic and Circuit Design Sub. Code: BTEC104 Experiment No.: 04

There is only one possibility of grouping 16 adjacent min terms.

Let R1, R2, R3 and R4 represents the min terms of first row, second row, third row and fourth
row respectively. Similarly, C1, C2, C3 and C4 represents the min terms of first column, second
column, third column and fourth column respectively. The possible combinations of grouping 8
adjacent min terms are {(R1, R2), (R2, R3), (R3, R4), (R4, R1), (C1, C2), (C2, C3), (C3, C4),
(C4, C1)}.
If w=0, then 4 variable K-map becomes 3 variable K-map.

5 Variable K-Map
The number of cells in 5 variable K-map is thirty-two, since the number of variables is 5. The
following figure shows 5 variable K-Map.

There is only one possibility of grouping 32 adjacent min terms.

There are two possibilities of grouping 16 adjacent min terms. i.e., grouping of min terms from
m0 to m15 and m16 to m31.
If v=0, then 5 variable K-map becomes 4 variable K-map.
In the above all K-maps, we used exclusively the min terms notation. Similarly, you can use
exclusively the Max terms notation.
Minimization of Boolean Functions using K-Maps
If we consider the combination of inputs for which the Boolean function is ‘1’, then we will get
the Boolean function, which is in standard sum of products form after simplifying the K-map.
Similarly, if we consider the combination of inputs for which the Boolean function is ‘0’, then we
will get the Boolean function, which is in standard product of sums form after simplifying the K-
map.

Study Group. Digital Electronics Modified by: Nitin Saravagi

Created by: Nitin Saravagi Date of Creation: 10/11/2022 Date of Modification:
Rev. No. EC/DE/01/2022 Approved by: HOD
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Subject Name: Digital Logic and Circuit Design Sub. Code: BTEC104 Experiment No.: 04

Follow these rules for simplifying K-maps in order to get standard sum of products form.
Select the respective K-map based on the number of variables present in the Boolean function.
If the Boolean function is given as sum of min terms form, then place the ones at respective min
term cells in the K-map. If the Boolean function is given as sum of products form, then place the
ones in all possible cells of K-map for which the given product terms are valid.
Check for the possibilities of grouping maximum number of adjacent ones. It should be powers
of two. Start from highest power of two and upto least power of two. Highest power is equal to
the number of variables considered in K-map and least power is zero.
Each grouping will give either a literal or one product term. It is known as prime implicant. The
prime implicant is said to be essential prime implicant, if atleast single ‘1’ is not covered with any
other groupings but only that grouping covers.
Note down all the prime implicants and essential prime implicants. The simplified Boolean
function contains all essential prime implicants and only the required prime implicants.

Note 1 − If outputs are not defined for some combination of inputs, then those output values will
be represented with don’t care symbol ‘x’. That means, we can consider them as either ‘0’ or ‘1’.

Note 2 − If don’t care terms also present, then place don’t cares ‘x’ in the respective cells of K-
map. Consider only the don’t cares ‘x’ that are helpful for grouping maximum number of
adjacent ones. In those cases, treat the don’t care value as ‘1’.

Difference between SOP and POS in Digital Logic

S.No. SOP POS
1 SOP stands for Sum of Products. POS stands for Product of Sums.
2 It is a technique of defining the It is a technique of defining
boolean terms as the sum of boolean terms as a product of sum
product terms. terms.
3 It prefers minterms. It prefers maxterms.
4 In the case of SOP, the minterms In the case of POS, the Maxterms
are defined as ‘m’. are defined as ‘M’
5 It gives HIGH (1) output. It gives LOW (0) output.
6 In SOP, we can get the final term In POS, we can get the final term
by adding the product terms. by multiplying the sum terms.

Examples:
Ex1: Design a combinational circuit with 3 inputs and 1 output. The output is 1 when the binary
value is less than 3.

Study Group. Digital Electronics Modified by: Nitin Saravagi

Created by: Nitin Saravagi Date of Creation: 10/11/2022 Date of Modification:
Rev. No. EC/DE/01/2022 Approved by: HOD
 Shri VaishnavSM Institute of Technology & Science, Indore
Discipline Department of Electrical & Electronics Engineering Pages: 5/5
Subject Name: Digital Logic and Circuit Design Sub. Code: BTEC104 Experiment No.: 04

6.0 Questions to Be Answered: -

6.1 Minimize the following boolean function- F(A, B, C, D) = Σm(0, 1, 2, 5, 7, 8, 9, 10, 13, 15)
6.2 Minimize the following boolean function- F(A, B, C) = Σm(1, 2, 5, 7) + Σd(0, 4, 6)
6.3 What are difference between canonical and standard form.

7.0 Investigations Expected:

7.1. Answers to the questions asked.
7.2. Exploring inferences and conclusion.

8.0 Students should submit in their own handwriting: -

8.1. Truth table.
8.2. Answer of the given questions.

References: -
 M. Morris Mano; "Digital Logic & Computer Design"; PHI.

Study Group. Digital Electronics Modified by: Nitin Saravagi

Created by: Nitin Saravagi Date of Creation: 10/11/2022 Date of Modification:
Rev. No. EC/DE/01/2022 Approved by: HOD