Computer Achitecture
Computer Achitecture
in
NUMBER SYSTEMS
There are several number systems which we normally use, such as decimal, binary, octal, hexadecimal, etc.
The Decimal Number System: The Decimal number system is a number system of base or radix equal to 10,
called Arabic numerals. The symbols used to represent number : 0, 1, 2, 3,4,5,6,7,8, 9 which are used for
counting.
This is expressed mathematically of the first five positions as 10 4 103 102 101 100
For example the value of the combination of symbols 435 is determined by adding the weight of each position
as 4 * 102 + 3 * 101 + 5 * 10owhich can be written as
4 * 100 + 3 * 10 + 5 * 1 or 400 + 30 + 5 = 435
Octal System
Octal to decimal Decimal to Octal
Octal to Binary Binary to Octal
Hexa-Decimal System
Hexa-Decimal to Decimal
Decimal to Hexa-Decimal
Hexa-Decimal toBinary
Binary to Hexa-Decimal
………………………………………………………………………………………………………………….
Binary to Decimal
Weight 210 29 28 27 26 25 24 23 22 21 20
1. 11011012= 10910
2. Convert binary number 1110.0112 to decimal. 2. 0.0112= 0.37510
1110.0012 3. 1111.10112= 15.687510
= 1×23+1×22+1×21+0×20+0×2-1 +1×2-2 +1×2-3 = (15.375)10
Decimal to Binary
Example Problems
1. 4110= 1010012
2. 0.610= 0.100112
3. 4096.312510 =
1000000000000.01012
1. 630.48= 408.510
2. 54738= 287510
3. 763.3758= 499.4939510
Octal to Binary
Binary to Octal
COMBINATIONAL CIRCUITS
…..………………………………………………………………………………………………………………….
HALF ADDER
A half adder takes two single bit binary numbers and produces a sum and a carry–out, called “carry”.
Logical Expression
Logic Diagram
The sum can be given in two equivalent expressions.
The simplest expression uses the exclusive OR
function
Sum = AB
Half adder is a combinational logic circuit with two inputs and two outputs. The half adder circuit is designed to
add two single bit binary numbers A and B. It is the basic building block for addition of two single bit numbers.
This circuit has two outputs carry and sum.
FULL ADDER
Full adder is developed to overcome the drawback of Half Adder circuit. The full adder is a three input and two
output combinational circuit. The first two inputs are A and B and the third input is an input carry as C-in and
produces a sum ‘S’ and a carry–out.
Logic SymbolTruth Table
A B Cin S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
Logical Diagram 1 1 0 0 1
1 1 1 1 1
Logical Expression
The circuit implements the following two
expressions, where C is
the carry–in to the full adder.
Sum= · ·C + ·B· + A· · + A·B·C
Carry = A·B + A·C + B·C
Suppose we let the carry–in C = 0. Then =
1.
What we have then is as follows.
Sum = · ·0 + ·B·1 + A· ·1 + A·B·0
= ·B + A·
Carry = A·B + A·0 + B·0
= A·B
As expected, a full adder with carry–in set to
zero acts likes a half adder.
A full adder can be constructed from two half adders by connecting A and B to the input of one half adder,
connecting the sum from that to an input to the s econd adder, connecting the carry in, Cin, to the other input and
ORing the two half adder carry outputs to give the final carry output, C out.
HALF SUBTRACTOR
A Half Subtractor is a logic circuit that performs Binary subtraction. It accepts two input variables and produces
two output variables called the difference bit and borrow bit.
The binary subtraction is also performed by the Ex -OR gate with additional circuitry to perform the borrow
operation. Thus, a half subtractor is designed by an Ex -OR gate including AND gate with A input
complemented before fed to the gate.
Logical Expression
DIFFERENCE bit:
D =AB
BORROW bit
B = X.Y
…..………………………………………………………………………………………………………………….
FULL SUBTRACTOR
The Half Subtractor does not handle Borrow from the previous stage. The Full Subtractor accepts Borrow from
the previous stage, so it has three inputs Bin, A and B. It has two outputs D (Difference) and Bo (Borrow
Output).
…..………………………………………………………………………………………………………………….
The mode input control line M is connected with carry input of the least significant bit of the full adder.
This control line decides the type of operation, whether addition or subtract
When M= 1, the circuit is a subtractor and when M=0, the circuit becomes adder.
The Ex-OR gate consists of two inputs to which one is connected to the B and other to input M.
When M = 0, B Ex-OR of 0 produce B. Then full adders add the B with A with carry input zero and hence an
addition operation is performed.
When M = 1, B Ex-OR of 0 produce B complement and also carry input is 1. Hence the complemented B inputs
are added to A and 1 is added through the input carry, nothing but a 2’s complement operation. Therefore, the
subtraction operation is performed.
Arithmetic logic unit - This is the part of the CPU performs arithmetic and logic operations. The ALU has 3
sections, the Register, the ALU circuitry and the pathways in between.
Register is basically a storage cell which holds information such as the address of the instructions and results of
the calculations.
ALU circuitryIt actually performs calculations and is designed from AND, OR and NOT gates just as a chip.
Pathways in between are for electric current within ALU.
Main Memory (RAM)–Main memory is volatile which means the information will be lost without constant
flow of electricity; hence it is called a temporary storage device. Main memory can be seen as a sequence of
cells. Each cell has its own unique address so that the data can be fetched.
Input/ Output -Computers can only interact with the world using input and output devices. Inputs receive data
for the computer and outputs send information from the computer.
Control Unit - The control unit is in charge of ‘fetching’ each instruction that needs to be executed in a
program by issuing control signals to the hardware. It then decodes the instruction and finally issues more
control signals to the hardware to actually execute it.
Harvard Architecture
Harvard architecture is computer architecture with physically separate storage and signal pathways for
instructions and data. The term originated from the Harvard Mark I relay-based computer, which stored
instructions on punched tape (24 bits wide) and data in electro-mechanical counters (23 digits wide). These
early machines had limited data storage, entirely contained within the CPU, and provided no access to the
instruction storage as data, making loading and modifying programs tedious.
LOGIC GATES
2. Derive basic/simple logic gates with its definition, logic symbol, truth table and expression?
The three basic logic operations are NOT, ANDandOR
NOT Gate (Inverter)
Definition: NOT gate is a logic gate that changes a 0 input to 1 and a 1 input to 0. NOT gate also called the
Inverter performs the operation called Inversion or Complement or Negation.
Truth Table
Logic Symbol:
̅
Y A Expression: Y= ̅A
0 1
Application:
NOT gate can be used to find 1’s complement of an 1 0
8-bit binary number (byte of data)
0 0 0
0 1 0
Application: AND gate is commonly used to enable
Passage of signal (pulse waveform) from one point 1 0 0
toanother.
1 1 1
OR Gate (Addition)
Definition: OR gate is a logic gate which performs logical addition. The output is HIGH (1) if any one of its
inputs is HIGH (1). The output will be low only if both the inputs are low.
A B Y=A+B
Expression: Y= A+B
0 0 0
0 1 1
Application: OR gate is used in intrusion detection
and alarm system. 1 0 1
1 1 1
3. Derive compound logic gates with its definition, logic symbol, truth table and expression?
NAND and NOR are compound logic gates.
NAND Gate
Definition: NAND is a combination of both AND and NOT gate. It operates the same as an AND gate but the
output will be opposite. The output is HIGH (1) only if both inputs are LOW (0).
A B Y=A.B
0 0 1
Expression: Y= A.B
0 1 1
1 0 1
1 1 0
NOR Gate
Definition: NOR is a combination of both OR and NOT gate. It operates the same as an OR gate but the output
will be opposite. The output is HIGH (1) if all its inputs are LOW (0), the output is LOW (0) if either of the
inputs or all its inputs are HIGH (1).
A B Y=A+B
Expression: Y= A+B
0 0 1
0 1 0
1 0 0
1 1 0
4. Explain XOR and XNOR logic gates with its definition, logic symbol, truth table and expression?
XOR Gate
Definition: The exclusive OR gate is a modified OR gate. The XOR gate produces a high outputwhen both its
inputs are different. If the inputs are the same, the output is a low.
A B Y=A B
Expression:
0 0 0
0 1 1 Y= A . B + A . B
1 0 1
1 1 0
NAND as OR Gate
The OR gate is replaced by a NAND gate with all its inputs com plemented by NAND gate inverter
NOR as OR Gate
The OR is replaced by a NOR gate with its output complemented by a NOR gate inverter