VHDL

Data Types
SISTEMES ELECTRÒNICS DIGITALS

Sebastià Bota

Data Types
 A Data Type defines a set of values and related
operations.
 VHDL is a strongly-typed Language. Types cannot be
mixed in Expressions or in assignements
DATA TYPES
ENUMERATED COMPOSITES
• BIT • Arrays
• STD_LOGIC • Records

SCALARS File Type &

• Numeric Access Type
(Integer, Real)
• Not Used for
•Physical H/W Modeling

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Data Types
 Data types and related operators are defined in Packages.
Packages are organised in libraries (A library is a directory and
each package is a file in that directory).

A package in VHDL is a database containing a

collection of functions, procedures, shared
variables, constants, files, aliases, types,
subtypes, attributes, and components which can
be shared among several designs.

 The Standard Package is available by default (predefined in the

compiler) placed in library STD
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Packages in Library STD

Package STD.STANDARD Package STD.TEXTIO
Types defined Types defined
BOOLEAN LINE
BIT, BIT_VECTOR TEXT
INTEGER, NATURAL, POSITIVE SIDE
REAL WIDTH
TIME, DELAY_LENGTH
STRING
CHARACTER
Functions defined
READ, READLINE
WRITE, WRITELINE, ENDLINE

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Standard Packages
Package STD.STANDARD

Types defined

BOOLEAN
BIT, BIT_VECTOR
INTEGER, NATURAL, POSITIVE
REAL
TIME, DELAY_LENGTH
STRING
CHARACTER

 type BOOLEAN is (FALSE, TRUE);

 type BIT is (‘0’, ‘1’);
 Type INTEGER is range -2,147,483,647 to +2,147,483,647).
 subtype NATURAL is INTEGER range 0 to INTEGER'HIGH;
 subtype POSITIVE is INTEGER range 1 to INTEGER'HIGH;
 REAL: Real numbers ranging from -1.0E38 to +1.0E38. Not synthesizable.
 subtype DELAY_LENGTH is TIME range 0 fs to TIME'HIGH;

Standard Package
• boolean has two possible values FALSE and TRUE

– Not intended for electrical signals!

– Typically used when checking some conditions, like

if a = b then -- equal
if a /= b then -- not equal
if a > b then -- larger
if a < b then -- smaller
if a <= b then -- smaller or equal
if a >= b then -- larger or equal

the result of the comparison is a boolean

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Packages in library IEEE
The packages that you need, except for
"standard", must be specifically accessed by
• std_logic_1164.all; each of your source files with statements such
as:
• std_logic_textio.all;
• std_logic_arith.all; library IEEE;
use IEEE.std_logic_1164.all;
• numeric_bit.all; use IEEE.std_logic_textio.all;
use IEEE.std_logic_arith.all;
• numeric_std.all; use IEEE.numeric_bit.all;
use IEEE.numeric_std.all;
• std_logic_signed.all; use IEEE.std_logic_signed.all;
use IEEE.std_logic_unsigned.all;
• std_logic_unsigned.all; use IEEE.math_real.all;
• math_real.all; use IEEE.math_complex.all;

• math_complex.all; library STD;

use STD.textio;

https://redirect.cs.umbc.edu/portal/help/VHDL/stdpkg.html

Most used Packages

Package STD.STANDARD Package IEEEE.STD_LOGIC_1164

Types Types

BOOLEAN STD_LOGIC
BIT STD_ULOGIC
BIT_VECTOR STD_LOGIC_VECTOR
INTEGER STD_ULOGIC_VECTOR
REAL
TIME
STRING
CHARACTER

and =
nand /=
or Implicit >
Operators
nor operators >=
xor <
not <=

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 STD_LOGIC_1164 Types
 Std_ulogic and std_logic Defined in IEEE package
STD_LOGIC_1164

 Values for Simulation & Synthesis

 ‘0’ -- Forcing ‘0’
 ‘1’ -- Forcing ‘1’
 ‘Z’ -- High Impedance
 ‘L’ -- Weak ‘0’
 ‘H’ -- Weak ‘1’
 ‘-’ -- Don’t care

 Values for Simulation only:

 ‘U’ -- Uninitialized
 ‘X’ -- Forcing Unknown
 ‘W’ -- Weak Unknown

Resolution table for std_logic

resolved function

uninitialized

unknown

forcing low

forcing high

high impedance

weak unknown

weak low

weak high

Don’t Care

Resolution Function Defined for STD_LOGIC. Not for STD_ULOGIC

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STD_LOGIC versus STD_ULOGIC

std_logic and std_logic_vector are the

industry standard logic type for digital design

A disadvantage of using std_logic instead of std_ulogic is that

signals that are unintententionally multiply driven will not be
detected as an error during compilation.

However, Standard IEEE Std 1164 recomends that std_logic be

used instead of std_ulogic, even if all signals has only a single
source.

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STD_LOGIC
ENTITY nand_gate IS
PORT(
a : IN BIT;
b : IN BIT;
z : OUT BIT);
END nand_gate;

ARCHITECTURE model OF nand_gate IS

BEGIN
z<= a NAND b;
END model;
CORRECT CODE, ALTHOUGH
NOT RECOMMENDED

Add the IEEE library to the top of your VHDL file : LIBRARY ieee;
and then reference the needed package.

Library ieee; --the compile would know that the word ieee is a library name
use ieee.std_logic_1164.all;
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STD_LOGIC
BEWARE WITH FILES WITH
MULTIPLE ENTITIES

The second design unit (entity

F2_POS) does not know about the use
clauses, and so you see an error here

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STD_LOGIC
BEWARE WITH FILES WITH
MULTIPLE ENTITIES

No compilation errors now

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More on STD_LOGIC Meanings
type std_logic is ('U' , 'X' , '0' , '1' , 'Z' , 'W' , 'L' , 'H' , '-‘);

‘U’ -- Uninitialized
Signal has not been assigned a value yet

STD_LOGIC initializes to uninitialized

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More on STD_LOGIC Meanings

Model this circuit is allowed only when using std_logic
but not bit!

A
B
Y <= not C;
Y Y <= A or B;
C

When not C = ‘1’ and A or B = ‘0’

Or when not C = ‘0’ and A or B = ‘1’

According to te resolution table, the simulator will assign the value ‘X’
(forcing unknown) to signal Y

‘W’ is the weak versión of ‘X’ 'X' , -- forcing unknown

'W', -- weak unknown
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Three state buffers

A three-state buffer (or tri-state) has a data input and an enable input.
Its enable input controls whether the three-state buffer is OFF and its
output is high impedance ('Z'), or whether it is ON and its output is driven by
its data input.
Thus, the output of a three-state buffer can be either '0', '1', or 'Z'.

‘Z' , -- High Impedance

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Three state buffers

Non inverting three-state buffer inverting three-state buffer

enable Low enable Low

Non inverting three-state buffer inverting three-state buffer

enable high enable High

A three-state buffer is represented by a triangle symbol.

Some three-state buffers are enabled when their enable input
is '0‘ and others when it is '1'.

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 Busses
 Busses, on the other hand, can
be driven by one or more
sources ENB

 In both cases, wires and

busses, there can be more ENB

than one destination for the

signal
 With busses, only the device
acting as source will actually ENB

drive a value. All others will

have their output set at high
impedance (‘Z’).
 If none of the buffers is
enabled, the bus node is at ‘Z’.
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Information on a Bus
 Possible state for a BUS
 Driven high (driven to a 1) ENB

 Driven low (driven to a 0)

 No driving value (Z or high ENB

impedance)
 Capacitive high (H)
 Capacitive low (L)
 Conflict (one driver driving it ENB

to a 1, another a 0) (X)
 Conflict of capacitive values
(W)

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More on STD_LOGIC Meanings

• Do not care. ‘-’

• Can be assigned to outputs for the case of invalid
inputs (may produce significant improvement in
resource utilization after synthesis).
• Use with caution ‘1’ = ‘-’ give FALSE

‘-' , -- don’t care

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Single Wire versus Bus

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Single Wire versus Bus
SIGNAL a : STD_LOGIC;

1 wire

SIGNAL b : STD_LOGIC_VECTOR (7 downto 0);

8 bus

STD_LOGIC_VECTOR is the equivalent to BIT_VECTOR

Example Entity Description with array types

A B

N
op Z

MSB LSB

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 y downto x vs x to y
....
y downto x SIGNAL z_bus: BIT_VECTOR (3 DOWNTO 0);
meaning y is the MSB, SIGNAL a_bus: BIT_VECTOR (1 TO 4);
....
x to y
meaning x is the MSB. z_bus <= a_bus;

-- is the same as:

z_bus(3) <= a_bus(1);

z_bus(2) <= a_bus(2);
z_bus(1) <= a_bus(3);
z_bus(0) <= a_bus(4);

it is reasonable to use the notation x downto 0 for a non-negative

integer, because bit positions correspond to the power of 2 multiplied
by the digit to add up to the number value. This seems to have been
extended also in most other practice involving integers.

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Operators: Assignment

 Assignment Operators

- Assignment operator is “<=“ which reads “gets”

- The Results is always on the Left, Operands on the Right

- Types need to all be of the same type

- need to watch the length of arrays!

EXAMPLES
 data_bit <= ‘1’;
 data_bus <=“110011”;

Individual bits are enclosed in single quotes (‘)

Bit strings are enclosed in double quotes (“)

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 Standard Logic Vectors

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Operators: Concatenation
& is the concatenation operator. combines objects of same
type into an array, the order is preserved

Concatenation: “&” is not the same as “AND” 32

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Logical Operators
Logical operators Defined on types

and BOOLEAN
nand BIT
or BIT_VECTOR
nor STD_LOGIC
xor STD_LOGIC_VECTOR
not

xnor

VHDL 93

Logic operators rules

--ILLEGAL!, can't mix logical operators

result <= a and b or c; --!

--should be...
result <= (a and b) or c;

--ILLEGAL!, can't chain nand or nor

--(nand and nor are not associative)
result <= a nand b nand c; --!
result <= a nor b nor c; --!

--maybe
result <= (a nand b) nand c;

--or
result <= a nand (b nand c);

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Precedence in Operators
 Logic and relational operators precedence
Highest not
= /= < <= > >=
Lowest and or nand nor xor xnor

compare a = bc

Incorrect … when a = b and c else …

is equivalent to … when (a = b) and c else …

Correct … when a = (b and c) else …

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Implicit Relational Operators

 Beware: for type STD_LOGIC

'U' < 'X' < '0' < '1' < 'Z' < 'W' < 'L' < 'H' < '-'

 Beware: for type STD_LOGIC_VECTOR

"0" < "00" < "000" < "001" < "100" < "111" < "1111"

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