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MAX17572 4.5V–60V, 1A, High-Efficiency, Synchronous

Step-Down DC-DC Converter
with Internal Compensation

General Description Benefits and Features

The MAX17572 high-efficiency, high-voltage, synchronous ●● Reduces External Components and Total Cost
step-down DC-DC converter with integrated MOSFETs • No Schottky-Synchronous Operation
operates over a 4.5V to 60V input. The converter can • Internal Compensation for Any Output Voltage
deliver up to 1A and generates output voltages from 0.9V • All-Ceramic Capacitors, Compact Layout
up to 0.9 x VIN. The feedback (FB) voltage is accurate to ●● Reduces Number of DC-DC Regulators to Stock
within ±1.2% over -40°C to +125°C. The MAX17572 uses • Wide 4.5V to 60V Input
peak current-mode control. • Adjustable 0.9V to 0.9 x VIN Output
The device is available in a 12-pin (3mm x 3mm) TDFN • Continuous 1A Current Over Temperature
package. Simulation models are available. • 400kHz to 2.2MHz Adjustable Switching Frequency
with External Synchronization
Applications ●● Reduces Power Dissipation
●● Industrial Control Power Supplies • Peak Efficiency > 92%
●● General-Purpose Point-of-Load • Auxiliary Bootstrap LDO for Improved Efficiency
●● Distributed Supply Regulation • 4.65µA Shutdown Current
●● Base Station Power Supplies
●● Operates Reliably in Adverse Industrial Environments
●● Wall Transformer Regulation
• Hiccup Mode Overload Protection
●● High-Voltage, Single-Board Systems
• Adjustable Soft-Start
• Built-In Output-Voltage Monitoring with RESET
• Programmable EN/UVLO Threshold
• Monotonic Startup into Prebiased Load
• Overtemperature Protection
• High Industrial -40°C to +125°C Ambient Operating
Temperature Range/-40°C to +150°C Junction
Temperature Range

Ordering Information appears at end of data sheet.

19-8640; Rev 3; 5/18

MAX17572 4.5V–60V, 1A, High-Efficiency, Synchronous
Step-Down DC-DC Converter
with Internal Compensaton
Absolute Maximum Ratings
VIN to PGND..........................................................-0.3V to +65V VCC to GND..........................................................-0.3V to +6.5V
EN/UVLO to GND......................................... -0.3V to VIN + 0.3V LX Total RMS Current.........................................................±1.6A
EXTVCC to GND....................................................-0.3V to +26V Continuous Power Dissipation (TA = +70°C)
BST to PGND.........................................................-0.3V to +70V (derate 24.4mW/°C above +70°C) (Multilayer board)...1951mW
LX to PGND................................................-0.3V to (VIN + 0.3)V Output Short-Circuit Duration.....................................Continuous
BST to LX..............................................................-0.3V to +6.5V Junction Temperature.......................................................+150°C
BST to VCC............................................................-0.3V to +65V Storage Temperature Range............................. -65°C to +160°C
RESET, SS, RT/SYNC to GND.............................-0.3V to +6.5V Lead Temperature (soldering, 10s).................................. +300°C
PGND to GND.......................................................-0.3V to +0.3V Soldering Temperature (reflow)........................................+260°C
FB to GND.............................................................-0.3V to +1.5V

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability. Junction temperature greater than +125°C degrades operating lifetimes.

Package Information
PACKAGE TYPE: 12 TDFN
Package Code TD1233+1C
Outline Number 21-0664
Land Pattern Number 90-0397
THERMAL RESISTANCE, FOUR-LAYER BOARD
Junction to Ambient (θJA) 41°C/W
Junction to Case (θJC) 8.5°C/W

For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.

Electrical Characteristics
(VIN = VEN/UVLO = 24V, RRT = 40.2k, CVCC = 2.2µF, VPGND = VGND = EXTVCC = 0, LX = SS = RESET = OPEN, VBST to VLX = 5V,
VFB = 1V, TA = -40°C to 125°C, unless otherwise noted. Typical values are at TA = +25°C. All voltages are referenced to GND, unless
otherwise noted.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

INPUT SUPPLY (VIN)
Input Voltage Range V­IN_ 4.5 60 V
Input Shutdown Current IIN-SH VEN/UVLO = 0V (shutdown mode) 4.65 7.25 µA
Normal switching mode, fSW = 500kHz,
Input Quiescent Current IQ_PWM 5.2 mA
VFB = 0.8V, EXTVCC = GND
ENABLE/UVLO (EN)
VENR VEN/UVLO rising 1.19 1.215 1.26 V
EN/UVLO Threshold
VENF VEN/UVLO falling 1.068 1.09 1.131 V
EN/UVLO Input Leakage
IENLKG VEN/UVLO = 1.25V, TA = 25°C -50 +50 nA
Current

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MAX17572 4.5V–60V, 1A, High-Efficiency, Synchronous
Step-Down DC-DC Converter
with Internal Compensaton
Electrical Characteristics (continued)
(VIN = VEN/UVLO = 24V, RRT = 40.2k, CVCC = 2.2µF, VPGND = VGND = EXTVCC = 0, LX = SS = RESET = OPEN, VBST to VLX = 5V,
VFB = 1V, TA = -40°C to 125°C, unless otherwise noted. Typical values are at TA = +25°C. All voltages are referenced to GND, unless
otherwise noted.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

VCC LDO
1mA ≤ IVCC ≤ 15mA 4.75 5 5.25 V
VCC Output Voltage Range VCC
6V ≤ VIN ≤ 60V; IVCC = 1mA 4.75 5 5.25 V
VCC Current Limit IVCC-MAX VCC = 4.3V, VIN = 6.5V 25 54 100 mA
VCC Dropout VCC-DO VIN = 4.5V , IVCC = 15mA 4.15 V
VCC-UVR Rising 4.05 4.2 4.3 V
VCC UVLO
VCC-UVF Falling 3.65 3.8 3.9 V
EXT LDO
EXTVCC rising 4.56 4.7 4.84 V
EXTVCC Switchover Voltage
EXTVCC falling 4.3 4.45 4.6 V
EXTVCC Dropout EXTVCC-DO EXTVCC = 4.75V , IEXTVCC = 15mA 0.3 V
EXTVCC Current Limit EXT VCCILIM VCC = 4.5V, EXTVCC = 7V 26.5 60 100 mA
HIGH-SIDE MOSFET AND LOW-SIDE MOSFET DRIVER
High-Side nMOS On-Resistance RDS-ONH ILX = 0.3A 330 620 mΩ
Low-Side nMOS On-Resistance RDS-ONL ILX = 0.3A 170 320 mΩ
LX Leakage Current VLX = VIN-1V; VLX = VPGND +1V;
ILXLKG -2 +2 µA
(LX to PGND_) TA = 25°C
SOFT-START
Soft-Start Current ISS VSS = 0.5 V 4.7 5 5.3 µA
FEEDBACK (FB)
FB Regulation Voltage VFB_REG 0.889 0.9 0.911 V
FB Input Bias Current IFB 0 ≤ VFB ≤ 1V, TA = 25°C -50 +50 nA
CURRENT LIMIT
Peak Current-Limit Threshold IPEAK-LIMIT 1.5 1.75 2.00 A
Runaway Current-Limit IRUNAWAY-
1.75 2 2.25 A
Threshold LIMIT
Negative Current-Limit Threshold 0.65 A
RT/SYNC AND TIMINGS
RRT = OPEN 430 490 550 kHz
RRT = 51.1kΩ 370 400 430 kHz
Switching Frequency fSW
RRT = 40.2kΩ 475 500 525 kHz
RRT = 8.06kΩ 1950 2200 2450 kHz
VFB Undervoltage Trip Level to
VFB-HICF 0.56 0.58 0.65 V
Cause HICCUP

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MAX17572 4.5V–60V, 1A, High-Efficiency, Synchronous
Step-Down DC-DC Converter
with Internal Compensaton
Electrical Characteristics (continued)
(VIN = VEN/UVLO = 24V, RRT = 40.2k, CVCC = 2.2µF, VPGND = VGND = EXTVCC = 0, LX = SS = RESET = OPEN, VBST to VLX = 5V,
VFB = 1V, TA = -40°C to 125°C, unless otherwise noted. Typical values are at TA = +25°C. All voltages are referenced to GND, unless
otherwise noted.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

HICCUP Timeout 32768 Cycles
Minimum On-Time tON_MIN 60 80 ns
Minimum Off-Time tOFF_MIN 140 150 160 ns
LX Dead Time 5 ns
SYNC Frequency Capture 1.1 × 1.4 ×
fSW set by RRT
Range fSW fSW
SYNC Pulse Width 50 ns
VIH 2.1 V
SYNC Threshold
VIL 0.8 V
RESET
RESET Output Level Low IRESET = 10mA 400 mV
RESET Output Leakage Current TA = TJ = 25°C, VRESET = 5.5V -100 +100 nA
VOUT Threshold for RESET
VOUT-OKF VFB falling 90.5 92 94.6 %
Assertion
VOUT Threshold for RESET
VOUT-OKR VFB rising 93.8 95 97.8 %
De-Assertion
RESET Delay After FB Reaches
1024 Cycles
95% Regulation
THERMAL SHUTDOWN
Thermal-Shutdown Threshold TSHDNR Temp rising 165 °C
Thermal-Shutdown Hysteresis TSHDNHY 10 °C
Note 1: All limits are 100% tested at TA = +25°C. Limits over the operating temperature range and relevant supply voltage range
are guaranteed by design and characterization

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MAX17572 4.5V–60V, 1A, High-Efficiency, Synchronous
Step-Down DC-DC Converter
with Internal Compensaton
Typical Operating Characteristics
(VIN = VEN/UVLO = 24V, VGND = VPGND = 0V, CVIN = 2.2μF, CVCC = 2.2μF, CBST = 0.1μF, CSS = 5600pF, TA = -40°C to +125°C,
unless otherwise noted. Typical values are at TA = +25°C. All voltages are referenced to GND, unless otherwise noted.)

EFFICIENCY vs. LOAD CURRENT EFFICIENCY vs. LOAD CURRENT

(5V OUTPUT) (3.3V OUTPUT)
FIGURE 4 CIRCUIT FIGURE 5 CIRCUIT
toc01 toc02
100 100

90 90

80
80
EFFICIENCY (%)

EFFICIENCY (%)
VIN = 48V 70
VIN = 36V
70 VIN = 24V VIN = 36V
60 VIN = 48V
VIN = 24V
60
VIN = 12V 50
VIN = 12V
50
40

40 30

30 20
0 200 400 600 800 1000 0.0 0.2 0.4 0.6 0.8 1.0
LOAD CURRENT (mA) LOAD CURRENT (A)

LOAD AND LINE REGULATION LOAD AND LINE REGULATION

(5V OUTPUT) (3.3V OUTPUT)
FIGURE 4 CIRCUIT FIGURE 5 CIRCUIT
toc03 toc04
5.04 3.50

3.45
5.03
OUTPUT VOLTAGE (V)

VIN = 24V VIN = 48V

VIN = 24V VIN = 48V
OUTPUT VOLTAGE (V)

3.40
5.02
3.35
5.01
3.30 VIN = 12V VIN = 36V
VIN = 12V VIN = 36V
5.00
3.25

4.99 3.20
0 200 400 600 800 1000 0.00 0.20 0.40 0.60 0.80 1.00
LOAD CURRENT (mA) LOAD CURRENT (A)

SOFT-START/SHUTDOWN FROM EN/UVLO, SOFT-START/SHUTDOWN FROM EN/UVLO

(5V OUTPUT, 1A LOAD CURRENT) (3.3V OUTPUT, 1A LOAD CURRENT)
FIGURE 4 CIRCUIT toc05
FIGURE 5 CIRCUIT toc06

VEN/UVLO 5V/div
VEN/UVLO 5V/div

VOUT 2V/div

VOUT 2V/div
IOUT 0.5A/div
IOUT 0.5A/div

VRESET 5V/div
VRESET 5V/div

1ms/div 1mS/div
CONDITION: RESET IS PULLED UP TO VCC WITH A 10kΩ RESISTOR CONDITION: RESET IS PULLED UP TO VCC WITH A 10kΩ RESISTOR

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MAX17572 4.5V–60V, 1A, High-Efficiency, Synchronous
Step-Down DC-DC Converter
with Internal Compensaton
Typical Operating Characteristics (continued)
(VIN = VEN/UVLO = 24V, VGND = VPGND = 0V, CVIN = 2.2μF, CVCC = 2.2μF, CBST = 0.1μF, CSS = 5600pF, TA = -40°C to +125°C,
unless otherwise noted. Typical values are at TA = +25°C. All voltages are referenced to GND, unless otherwise noted.)

SOFT-START WITH 2.5V PREBIAS SOFT-START WITH 2.5V PREBIAS

(5V OUTPUT) (3.3V OUTPUT)
FIGURE 4 CIRCUIT toc07
FIGURE 5 CIRCUIT toc08

5V/div 5V/div
VEN/UVLO 1V/div VEN/UVLO

1V/div

VOUT
5V/div

VOUT 5V/div VRESET

VRESET
1mS/div 1mS/div
CONDITION: RESET IS PULLED UP TO VCC WITH A 10kΩ RESISTOR CONDITION: RESET IS PULLED UP TO VCC WITH A 10kΩ RESISTOR

STEADY-STATE SWITCHING WAVEFORMS STEADY-STATE SWITCHING WAVEFORMS

(5V OUTPUT, 1A LOAD CURRENT) (5V OUTPUT, NO LOAD CURRENT)
FIGURE 4 CIRCUIT FIGURE 4 CIRCUIT
toc09 toc10

VOUT VOUT
(AC) 50mV/div 50mV/div
(AC)

VLX 10V/div VLX 10V/div

ILX 1A/div ILX 500mA/div

2µS/div 2µs/div

LOAD CURRENT STEPPED FROM 0.5A TO 1A LOAD CURRENT STEPPED FROM 0.5A TO 1A
(5V OUTPUT) (3.3V OUTPUT)
FIGURE 4 CIRCUIT FIGURE 5 CIRCUIT
toc11 toc12

VOUT
(AC) 100mV/div VOUT 50mV/div
(AC)

ILOAD 500mA/div ILOAD 500mA/div

100μS/div 100μS/div

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MAX17572 4.5V–60V, 1A, High-Efficiency, Synchronous
Step-Down DC-DC Converter
with Internal Compensaton
Typical Operating Characteristics (continued)
(VIN = VEN/UVLO = 24V, VGND = VPGND = 0V, CVIN = 2.2μF, CVCC = 2.2μF, CBST = 0.1μF, CSS = 5600pF, TA = -40°C to +125°C,
unless otherwise noted. Typical values are at TA = +25°C. All voltages are referenced to GND, unless otherwise noted.)

LOAD CURRENT STEPPED FROM NO LOAD TO 0.5A LOAD CURRENT STEPPED FROM NO LOAD TO 0.5A
(5V OUTPUT) (3.3V OUTPUT)
FIGURE 4 CIRCUIT FIGURE 5 CIRCUIT
toc13 toc14

VOUT VOUT
(AC) 100mV/div (AC) 50mV/div

ILOAD 500mA/div ILOAD 500mA/div

100μS/div 100μS/div

OVERLOAD PROTECTION APPLICATION OF EXTERNAL CLOCK AT 600kHz

(5V OUTPUT) FIGURE 4 CIRCUIT (5V OUTPUT) FIGURE 1 CIRCUIT
toc15 toc16

VOUT 20mV/div

VLX 10V/div

ILX 0.5A/div VSYNC 2V/div

20ms/div 4μs/div

BODE PLOT BODE PLOT

(5V OUTPUT, 1A LOAD CURRENT) (3.3V OUTPUT, 1A LOAD CURRENT)
FIGURE 4 CIRCUIT toc17
FIGURE 5 CIRCUIT toc18
50 40
100 80
40 30
PHASE 80
30 20 PHASE 60

60
GAIN (dB)

20
GAIN (dB)

10 GAIN 40
GAIN
10 40 0
20
0 20 -10
0
-10 -20
CROSSOVER 0 CROSSOVER
FREQUENCY = 47.9kHz, FREQUENCY = 42.9kHz,
-20 PHASE MARGIN = 70.5° -30 PHASE MARGIN = 64.5° -20
103 104 105 3 104 105
10
FREQUENCY (Hz) FREQUENCY (Hz)

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MAX17572 4.5V–60V, 1A, High-Efficiency, Synchronous
Step-Down DC-DC Converter
with Internal Compensaton
Pin Configuration

TOP VIEW

MAX17572
VIN 1 12 PGND

+
EN/UVLO 2 11 LX

RESET 3 10 BST

SS 4 9 EXTV CC

VCC 5 8 GND

RT/SYNC 6 EP* 7 FB

TDFN
(3mm x 3mm)
*EP = EXPOSED PAD , CONNECTED TO GND

Pin Description
PIN NAME FUNCTION
VIN 1 Power-Supply Input. The input supply range is from 4.5V to 60V.
Enable/Undervoltage Lockout Input. Drive EN/UVLO high to enable the output voltage. Connect to the
EN/UVLO 2 centre of the resistive divider between VIN and GND to set the input voltage (undervoltage threshold) at
which the device turns on. Pull up to VIN for always on.
Open-Drain RESET Output. The RESET output is driven low if FB drops below 92% of its set value. RESET
RESET 3 goes high 1024 clock cycles after FB rises above 95% of its set value. RESET is valid when the device is
enabled and VIN is above 4.5V.
SS 4 Soft-Start Input. Connect a capacitor from SS to GND to set the soft-start time.
5V LDO Output. Bypass VCC with 2.2μF/10V/X7R/0603(MURATA GRM188R71A225KE15) or 4.7μF/10V/
VCC 5
X7R/0805(TDK C2012X7R1A475K085AC) ceramic capacitor to GND.
Oscillator Timing Resistor Input. Connect a resistor from RT/SYNC to GND to program the switching
frequency from 400kHz to 2.2MHz. An external pulse can be applied to RT/SYNC through a coupling
RT/SYNC 6
capacitor to synchronize the internal clock to the external pulse frequency. See the Switching Frequency
Selection and External Frequency Synchronization section for details.
FB 7 Feedback Input. Connect FB to the center of the resistive divider between output voltage and GND.
GND 8 Analog Ground.
External Power-Supply Input for the Internal LDO. Applying a voltage between 4.84V and 24V at the
EXTVCC 9
EXTVCC pin will bypass the internal LDO and improve efficiency.

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MAX17572 4.5V–60V, 1A, High-Efficiency, Synchronous
Step-Down DC-DC Converter
with Internal Compensaton
Pin Description (continued)
PIN NAME FUNCTION
BST 10 Boost Flying Capacitor. Connect a 0.1μF ceramic capacitor between BST and LX.
Switching Node. Connect LX to the switching side of the inductor. LX is high impedance when the device is
LX 11
in shutdown mode.
Power Ground. Connect PGND externally to the power ground plane. Connect GND and PGND pins
PGND 12
together at the ground return path of the VCC bypass capacitor.
Exposed Pad. Always connect EP to the GND pin of the IC. Also, connect EP to a large GND plane
EP — with several thermal vias for best thermal performance. Refer to the MAX17572 EV kit data sheet for an
example of the correct method for EP connection and thermal vias.

Functional (or Block) Diagram

VIN

MAX17572

EXTVCC INTERNAL LDO VCC

REGULATOR

POK
BST
VCC_INT

EN/UVLO
PEAK-LIMIT
CHIPEN CS CURRENT
SENSE
1.215V CURRENT
AMPLIFIER
SENSE LOGIC

HIGH SIDE
THERMAL DRIVER
SHUTDOWN DH

PWM LX
CONTROL LOGIC LOW SIDE
DRIVER
CLK DL
RT/SYNC
OSCILLATOR

PGND

SLOPE

CS
FB
PWM SINK LIMIT ZX/ILIMIN
ERROR NEGATIVE
COMP
EXTERNAL AMPLIFIER CURRENT RESET
SS
SOFT START REF
CONTROL

0.76V
2ms
DELAY
CLK FB GND

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MAX17572 4.5V–60V, 1A, High-Efficiency, Synchronous
Step-Down DC-DC Converter
with Internal Compensaton
Detailed Description Switching Frequency Selection and External
The MAX17572 high-efficiency, high-voltage, synchronous Frequency synchronization
step-down DC-DC converter with integrated MOSFETs The switching frequency of the MAX17572 can be
operates over a 4.5V to 60V input. The converter can programmed from 400kHz to 2.2MHz by using a resistor
deliver up to 1A and generates output voltages from 0.9V connected from the RT/SYNC pin to GND. When no
up to 0.9 x VIN. The feedback (FB) voltage is accurate to resistor is used, the frequency is programmed to 490kHz.
within ±1.2% over -40°C to +125°C. The switching frequency (fSW) is related to the resistor
The device features a peak-current-mode control architecture. connected at the RT pin (RRT) by the following equation:
An internal transconductance error amplifier produces an
21× 10 3
integrated error voltage at an internal node that sets the R RT
= − 1.7
duty cycle using a PWM comparator, a high-side current- FSW
sense amplifier, and a slope-compensation generator. where RRT is in kΩ and fSW is in kHz. See Table 1 for RT
At each rising edge of the clock, the high-side MOSFET resistor values for a few common switching frequencies.
turns on and remains on until either the appropriate or
The RT/SYNC pin can be used to synchronize the
maximum duty cycle is reached, or the peak current limit
device’s internal oscillator to an external system clock.
is detected. During the high-side MOSFET’s on-time, the
A resistor must be connected from the RT/SYNC pin
inductor current ramps up. During the second-half of the
to GND to be able to synchronize the MAX17572 to an
switching cycle, the high-side MOSFET turns off and the
external clock. The external clock should be coupled to
low-side MOSFET turns on. The inductor releases the
the RT/SYNC pin through a network, as shown in Figure
stored energy as its current ramps down and provides
1. When an external clock is applied to MODE/SYNC pin,
current to the output.
the internal oscillator frequency changes to external clock
The device features a RT/SYNC pin to program the frequency (from original frequency based on RT setting)
switching frequency and to synchronize to an external after detecting 16 external clock edges. The external clock
clock. The device also features adjustable-input, undervolt- logic-high level should be higher than 2.1V, logic-low level
age-lockout, adjustable soft-start, open-drain RESET and lower than 0.8V and the pulse width of the external clock
auxiliary bootstrap LDO. should be more than 50ns. The RT resistor should be
Linear Regulator (VCC) selected to set the switching frequency at 10% lower than
The device has two internal (low-dropout) regulators the external clock frequency.
(LDOs) which powers VCC. One LDO is powered from
VIN and the other LDO is powered from EXTVCC
Table 1. Switching Frequency vs. RT
(EXTVCC LDO). Only one of the two LDOs is in operation Resistor
at a time, depending on the voltage levels present at SWITCHING FREQUENCY (kHz) RT RESISTOR (kΩ)
EXTVCC. If EXTVCC voltage is greater than 4.7V (typ),
400 51.1
VCC is powered from EXTVCC. If EXTVCC is lower than
4.7V (typ), VCC is powered from VIN. Powering VCC from 500 OPEN
EXTVCC increases efficiency at higher input voltages. 1000 19.1
EXTVCC voltage should not exceed 24V. 2200 8.06
Typical VCC output voltage is 5V. Bypass VCC to
GND with either 2.2μF/10V/X7R/0603(MURATA
GRM188R71A225KE15) or 4.7μF/10V/X7R/0805(TDK MAX17572
C2012X7R1A475K085AC) ceramic capacitor. VCC pow- C1 C8
ers the internal blocks and the low-side MOSFET driver RT/SYNC
47pF
and recharges the external bootstrap capacitor. Both LDO 100pF R8 R7
1K 40.2K
can source up to 60mA (typ). The MAX17572 employs an CLOCK
SOURCE
undervoltage-lockout circuit that forces the converter off
when VCC falls below 3.8V (typ). The converter is enabled
again when VCC is higher than 4.2V. The 400mV UVLO VLOGIC-HIGH

hysteresis prevents chattering on power-up/power-down. VLOGIC-LOW

In applications where the buck converter output is connected DUTY

to the EXTVCC pin, if the output is shorted to ground, then
transfer from EXTVCC LDO to the internal LDO happens
Figure 1. External Clock Synchronization
seamlessly without any impact on the normal functionality.

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MAX17572 4.5V–60V, 1A, High-Efficiency, Synchronous
Step-Down DC-DC Converter
with Internal Compensaton
Operating Input Voltage Range voltage drops to below 92% of the set nominal output volt-
The minimum and maximum operating input voltages for age. RESET also goes low during thermal shutdown.
a given output voltage should be calculated as follows: Prebiased Output

VIN(MIN) =
( (
VOUT + I OUT(MAX) × R DCR(MAX) +R DS_ONL(MAX) )) When the device starts into a prebiased output, both the
high-side and low-side switches are turned off so that the
(
1 − f SW(MAX) × t OFF_MIN(MAX) ) converter does not sink current from the output. High-
side and low-side switches do not start switching until the
( (
+ I OUT(MAX) × R DS_ONH(MAX) − R DS_ONL(MAX) )) PWM comparator commands the first PWM pulse. The
VOUT output voltage is then smoothly ramped up to the target
VIN(MAX) =
f SW(MAX) × t ON_MIN(MAX) value in alignment with the internal reference.

where:
Thermal Shutdown Protection
VOUT = Steady-state output voltage Thermal shutdown protection limits total power dissipation in
IOUT(MAX) = Maximum load current the device. When the junction temperature of the device
RDCR(MAX) = Worst-case DC resistance of the inductor exceeds +165°C, an on-chip thermal sensor shuts down
the device, allowing the device to cool. The thermal
fSW(MAX) = Maximum switching frequency
sensor turns the device on again after the junction
tOFF_MIN(MAX) = Worst-case minimum switch off-time
temperature cools by 10°C. Soft-start is deasserted dur-
(160ns)
ing thermal shutdown and initiates the start-up opera-
tON_MIN(MAX) = Worst-case minimum switch on-time (80ns) tion when the device recovers from thermal shutdown.
RDS_ONH(MAX) = Worst-case on-state resistances and high- Carefully evaluate the total power dissipation (see the
side internal MOSFET Power Dissipation section) to avoid unwanted triggering
RDS_ONL(MAX) = Worst-case on-state resistances and low- of the thermal shutdown protection in normal operation.
side external MOSFET
Overcurrent Protection Applications Information
The device is provided with a robust overcurrent protection Input Capacitor Selection
scheme that protects the device under overload and output The input filter capacitor reduces peak currents drawn
short-circuit conditions. A cycle-by-cycle peak current limit from the power source and reduces noise and voltage
turns off the high-side MOSFET whenever the high-side ripple on the input caused by the circuit’s switching. The
switch current exceeds an internal limit of 1.75A (typ). input capacitor RMS current (IRMS) is defined by the
A runaway current limit on the high-side switch current following equation:
at 2A (typ) protects the device under high input voltage,
short-circuit conditions when there is insufficient output VOUT × (VIN − VOUT )
voltage available to restore the inductor current that was IRMS I OUT(MAX) ×
=
built up during the on period of the step-down converter. VIN
One occurrence of runaway current limit triggers a hiccup
where, IOUT(MAX) is the maximum load current.
mode. In addition, if, due to a fault condition, feedback
IRMS has a maximum value when the input voltage
voltage drops to 0.58V (typ) any time after soft-start is
equals twice the output voltage (VIN = 2 x VOUT), so
complete, hiccup mode is triggered. In hiccup mode, the
IRMS(MAX) = IOUT(MAX)/2.
converter is protected by suspending switching for a hiccup
timeout period of 32,768 clock cycles. Once the hiccup Choose an input capacitor that exhibits less than +10°C
timeout period expires, soft-start is attempted again. temperature rise at the RMS input current for optimal
Note that when soft-start is attempted under an overload long-term reliability. Use low-ESR ceramic capacitors
condition, if the feedback voltage does not exceed 0.58V, with high-ripple-current capability at the input. X7R capacitors
the device switches at half the programmed switching are recommended in industrial applications for their
frequency. Hiccup mode of operation ensures low power temperature stability. Calculate the input capacitance
dissipation under output short-circuit conditions. using the following equation:

RESET Output I OUT(MAX) × D × (1 − D)

C IN =
The device includes a RESET comparator to monitor the η × f SW × ∆VIN
status of the output voltage. The open-drain RESET output
requires an external pullup resistor. RESET goes high where D = VOUT/VIN is the duty ratio of the converter,
(high impedance) 1024 switching cycles after the regulator fSW is the switching frequency, ∆VIN is the allowable input
output increases above 95% of the designed nominal regu- voltage ripple, and η is the efficiency.
lated voltage. RESET goes low when the regulator output
www.maximintegrated.com Maxim Integrated │ 11
MAX17572 4.5V–60V, 1A, High-Efficiency, Synchronous
Step-Down DC-DC Converter
with Internal Compensaton
In applications where the source is located distant from The soft-start time (tSS) is related to the capacitor connected
the device input, an electrolytic capacitor should be added at SS (CSS) by the following equation:
in parallel to the ceramic capacitor to provide necessary
damping for potential oscillations caused by the inductance C SS
t SS =
of the longer input power path and input ceramic capacitor. 5.55 × 10 −6
Inductor Selection
For example, to program a 2ms soft-start time, a 12nF
Three key inductor parameters must be specified for
capacitor should be connected from the SS pin to GND.
operation with the device: inductance value (L), inductor
saturation current (ISAT) and DC resistance (RDCR). The Adjusting Output Voltage
switching frequency and output voltage determine the Set the output voltage with a resistive voltage-divider connected
inductor value as follows: from the positive terminal of the output capacitor (VOUT)
2 × VOUT to SGND (see Figure 2). Connect the center node of
L= the divider to the FB pin. Use the following procedure to
f SW
choose the resistive voltage-divider values:
Where VOUT and fSW are nominal values and fSW is in Calculate resistor R4 from the output to the FB pin as
Hz. Select an inductor whose value is nearest to the value follows:
calculated by the previous formula.
Select a low-loss inductor closest to the calculated value 1850
R4 =
with acceptable dimensions and having the lowest possible C OUT_SEL
DC resistance. The saturation current rating (ISAT) of the
inductor must be high enough to ensure that saturation Where COUT_SEL (in µF) is the actual derated value of
can occur only above the peak current-limit value. the output capacitance used and R4 is in kΩ. The minimum
allowable value of R4 is (5.6 x VOUT), where R4 is in kΩ.
Output Capacitor Selection If the value of R4 calculated using the above equation
X7R ceramic output capacitors are preferred due to their is less than (5.6 x VOUT), increase the value of R4 to at
stability over temperature in industrial applications. The least (5.6 x VOUT).
output capacitors are usually sized to support a step load
of 50% of the maximum output current in the application, R4 × 0.9
so the output voltage deviation is contained to 3% of the R5 =
(VOUT − 0.9)
output voltage change. The minimum required output
capacitance can be calculated as follows: R5 is in kΩ.
60
C OUT =
VOUT
VOUT
Where COUT is in µF. Derating of ceramic capacitors with
DC-voltage must be considered while selecting the output R4
capacitor. Derating curves are available from all major
ceramic capacitor vendors. FB

Soft-Start Capacitor Selection R5

The device implements adjustable soft-start operation to
reduce inrush current. A capacitor connected from the SS
SGND
pin to GND programs the soft-start time. The selected
output capacitance (CSEL) and the output voltage (VOUT)
determine the minimum required soft-start capacitor as Figure 2. Adjusting Output Voltage
follows:

C SS ≥ 56 × 10 −6 × C SEL × VOUT

www.maximintegrated.com Maxim Integrated │ 12

MAX17572 4.5V–60V, 1A, High-Efficiency, Synchronous
Step-Down DC-DC Converter
with Internal Compensaton
Setting the Undervoltage Lockout Level
The device offers an adjustable input undervoltage-lockout VIN
level. Set the voltage at which the device turns on with
a resistive voltage-divider connected from VIN to SGND R1
(see Figure 3). Connect the center node of the divider to
EN/UVLO. Choose R1 to be 3.3MΩ and then calculate EN/UVLO
R2 as follows:
R2
1.215 × R1
R2 =
(VINU − 1.215) SGND

where VINU is the voltage at which the device is required

to turn on. Ensure that VINU is higher than 0.8 x VOUT. Figure 3. Setting the Input Undervoltage Lockout

If the EN/UVLO pin is driven from an external signal source,

a series resistance of minimum 1kΩ is recommended to be PCB Layout Guidelines
placed between the signal source output and the EN/UVLO All connections carrying pulsed currents must be very
pin, to reduce voltage ringing on the line. short and as wide as possible. The inductance of these
Power Dissipation connections must be kept to an absolute minimum due
to the high di/dt of the currents. Since inductance of a current
At a particular operating condition, the power losses that
carrying loop is proportional to the area enclosed by the
lead to temperature rise of the part are estimated as follows:
loop, if the loop area is made very small, inductance is
reduced. Additionally, small-current loop areas reduce
1
(
= (POUT × ( − 1)) − I OUT 2 × R DCR
PLOSS
η
) radiated EMI.
A ceramic input filter capacitor should be placed close
P=
OUT VOUT × I OUT to the VIN pins of the IC. This eliminates as much trace
inductance effects as possible and gives the IC a cleaner
Where POUT is the output power, η is the efficiency of the
voltage supply. A bypass capacitor for the VCC pin also
converter and RDCR is the DC resistance of the inductor
should be placed close to the pin to reduce effects of trace
(see the Typical Operating Characteristics for more information
impedance.
on efficiency at typical operating conditions).
When routing the circuitry around the IC, the analog small-
For a typical multilayer board, the thermal performance
signal ground and the power ground for switching currents
metrics for the package are given below:
must be kept separate. They should be connected together
θ JA = 41°C / W at a point where switching activity is at a minimum, typically
the return terminal of the VCC bypass capacitor. This helps
θ JC = 8.5°C / W
keep the analog ground quiet. The ground plane should
The junction temperature of the device can be estimated be kept continuous/unbroken as far as possible. No trace
at any given maximum ambient temperature (TA_MAX) carrying high switching current should be placed directly
from the following equation: over any ground plane discontinuity.
PCB layout also affects the thermal performance of the
= T A _MAX + (θ JA × PLOSS )
TJ_MAX design. A number of thermal vias that connect to a large
ground plane should be provided under the exposed pad
If the application has a thermal-management system that of the part, for efficient heat dissipation.
ensures that the exposed pad of the device is maintained
at a given temperature (TEP_MAX) by using proper heat For a sample layout that ensures first pass success,
sinks, the junction temperature of the device can be refer to the MAX17572 evaluation kit layout available at
estimated at any given maximum ambient temperature as: www.maximintegrated.com.

J_MAX TEP_MAX + (θ JC × PLOSS )

T=

Junction temperatures greater than +125°C degrades

operating lifetimes.

www.maximintegrated.com Maxim Integrated │ 13

MAX17572 4.5V–60V, 1A, High-Efficiency, Synchronous
Step-Down DC-DC Converter
with Internal Compensaton
Typical Application Circuit

VIN VIN BST

C1 C5
0.1µF L1
2.2µF
15µH
PGND EN/UVLO LX VOUT
C2 5V/1A
PGND R3 10µF
MAX17572 4.7Ω
R1
EXTVCC
178kΩ
C6
VCC
0.1µF
C3

FB
RT/SYNC
R2
GND 39kΩ
R4
40.2KΩ

RESET
SS fSW = 500kHz
C4 EP
L1 = 15µH COILCRAFT XAL4040-153 (4mm × 4mm)
5600pF C2 = 10µF/10V/X7R/1210 MURATA GRM32DR71A106KA01
C3 = 4.7µF/10V/X7R/0805 TDK 2012X7R1A475K085AC (or)
2.2µF/10V/X7R/0603 MURATA GRM188R71A225KE15

Figure 4. Typical Application Circuit for 5V Output

VIN VIN BST

C1 C5
0.1µF L1
2.2µF
15µH
PGND EN/UVLO LX VOUT
C2 3.3V/1A
PGND 22µF
MAX17572 R1
EXTVCC
86.6kΩ
VCC
C3

FB
RT/SYNC
R2
GND 32.4kΩ
R4
40.2KΩ

RESET
SS fSW = 500kHz
C4 EP
L1 = 15µH COILCRAFT XAL4040-153 (4mm × 4mm)
5600pF C2 = 22µF/10V/X7R/1210 MURATA GRM32ER71A226K
C3 = 4.7µF/10V/X7R/0805 TDK 2012X7R1A475K085AC (or)
2.2µF/10V/X7R/0603 MURATA GRM188R71A225KE15

Figure 5. Typical Application Circuit for 3.3V Output

www.maximintegrated.com Maxim Integrated │ 14

MAX17572 4.5V–60V, 1A, High-Efficiency, Synchronous
Step-Down DC-DC Converter
with Internal Compensaton
Ordering Information Chip Information
PART PIN-PACKAGE PACKAGE-SIZE PROCESS: BiCMOS
MAX17572ATC+ 12 TDFN 3mm × 3mm
+Denotes a lead(Pb)-free/RoHS-compliant package.

www.maximintegrated.com Maxim Integrated │ 15

MAX17572 4.5V–60V, 1A, High-Efficiency, Synchronous
Step-Down DC-DC Converter
with Internal Compensaton
Revision History
REVISION REVISION PAGES
DESCRIPTION
NUMBER DATE CHANGED
0 9/16 Initial release —
1 3/17 Updated Absolute Maximum Ratings and Typical Operating Characteristics sections 2, 5–7
Updated VCC capacitor to 4.7μF 0805. Updated global characteristics for Electrical
Characteristics table and Typical Operatings Characteristics. Updated Function
2–8, 10–11,
2 6/17 for VCC in Pin Description table. Updated Detailed Description, Equation 1, added
13–14
a reference to Figure 3 in the Setting the Undervoltage Lockout Level section.
Updated Typical Application Circuits.

Updated the Absolute Maximum Ratings, Detailed Description, Linear Regulator,

Operating Input-Voltage Range, RESET Output, Thermal Shutdown Protection,
3 5/18 Application Information, and Power Dissipation sections. Updated the Electrical 2–11, 13–14
Characteristics and Typical Operating Characteristics global characteristics,
TOC05–TOC08, and the Pin Description table.
3.1 Corrected references in the Pin Description table. 8

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. © 2018 Maxim Integrated Products, Inc. │ 16