OMKAR SHIRASGAONKAR Workshop Day 1: 12-08-2024 240938016

ANALOG AND DIGITAL IC DESIGN FLOW USING CADENCE EDA

Digital Design : UART

The design flow Digital ICs in Cadence is as follows:

1. Specification Definition
 Objective: Define the functionality, timing, power, and area requirements of the
digital IC.
 Key Outputs: Specifications for speed, power, process technology, logic gates, clock
frequency, input/output constraints, and verification metrics.
2. RTL Design (Register Transfer Level)
 Tool: Cadence NC-Verilog or Xcelium (for simulation).
 Objective: Write the behavioral design of the digital circuit using a hardware
description language (HDL) like Verilog or VHDL.
 Steps:
o Write RTL code that defines the logical functionality of the circuit.
o Run simulations to verify functionality and ensure that it meets the design
specifications.
 Key Outputs: Synthesizable RTL code and functional simulation results.
3. Functional Verification
 Tool: Cadence Xcelium for simulation or JasperGold for formal verification.
 Objective: Verify that the RTL design behaves correctly under all input conditions.
 Steps:
o Create testbenches to simulate various inputs and conditions.
o Run simulations and formal verification to ensure the design is functionally
correct.
 Key Outputs: Verified RTL design and testbench results.
4. Synthesis
 Tool: Cadence Genus Synthesis Solution.
 Objective: Convert the RTL code into a gate-level netlist composed of standard cells
from the chosen technology library.
 Steps:
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o Set design constraints (timing, power, and area).

o Run synthesis to map the RTL to actual logic gates.
o Optimize the design to meet performance and area targets.
 Key Outputs: Gate-level netlist and synthesized design reports.
5. Pre-Layout Static Timing Analysis (STA)
 Tool: Cadence Tempus.
 Objective: Analyze timing of the synthesized design to ensure it meets timing
requirements without violating setup and hold times.
 Steps:
o Run static timing analysis (STA) on the gate-level netlist.
o Identify and fix timing violations (e.g., critical paths, hold violations).
 Key Outputs: Timing reports, including worst-case slack and critical paths.
6. Floorplanning
 Tool: Cadence Innovus Implementation System.
 Objective: Define the chip’s physical structure, including the placement of key blocks
and IO pins, as well as the allocation of space for power and signal routing.
 Steps:
o Create a floorplan that includes block locations, power grid layout, and IO pad
placement.
o Determine chip dimensions and aspect ratio.
 Key Outputs: Floorplan diagram with block and pin placements.
7. Placement
 Tool: Cadence Innovus Implementation System.
 Objective: Place the standard cells onto the layout according to the floorplan, ensuring
efficient use of space and proper timing.
 Steps:
o Place the synthesized gates onto the layout within the defined floorplan.
o Ensure that critical paths are optimized for timing.
 Key Outputs: Placed netlist and design layout.
8. Clock Tree Synthesis (CTS)
 Tool: Cadence Innovus Implementation System.
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 Objective: Build a balanced clock tree to distribute the clock signal evenly throughout
the design, minimizing clock skew and ensuring timing integrity.
 Steps:
o Design and insert the clock tree, ensuring balanced delays from the clock
source to all clock sinks.
o Run timing analysis to check clock skew and propagation delays.
 Key Outputs: Clock tree network and clock timing reports.
9. Routing
 Tool: Cadence Innovus Implementation System.
 Objective: Route the interconnections between placed standard cells, ensuring that
signals can travel without congestion or delay.
 Steps:
o Perform global and detailed routing of all signal and power nets.
o Ensure DRC compliance and optimize signal integrity.
 Key Outputs: Fully routed design ready for post-layout verification.
10. Post-Layout Static Timing Analysis (STA)
 Tool: Cadence Tempus.
 Objective: Perform post-layout STA to check for timing violations caused by
parasitics introduced during placement and routing.
 Steps:
o Extract parasitics from the layout.
o Run STA to verify that timing constraints (setup, hold, skew) are met.
o Fix any remaining violations by adjusting the layout or gate sizes.
 Key Outputs: Timing reports with post-layout analysis.
11. Power Analysis
 Tool: Cadence Voltus.
 Objective: Analyze power consumption and ensure the power delivery network can
supply sufficient current without excessive voltage drops.
 Steps:
o Run dynamic and static power analysis.
o Optimize power distribution to meet power integrity constraints.
 Key Outputs: Power reports and a verified power distribution network.
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12. Design Rule Checking (DRC)

 Tool: Cadence Pegasus DRC or Assura DRC.
 Objective: Ensure that the design meets all process technology rules provided by the
foundry.
 Steps:
o Run DRC to check for violations in layout geometry, spacing, and layer
thickness.
o Fix any errors flagged by the tool.
 Key Outputs: DRC-clean layout.
13. Layout vs. Schematic (LVS)
 Tool: Cadence Pegasus LVS or Assura LVS.
 Objective: Ensure that the physical layout matches the original schematic in terms of
connectivity and logic function.
 Steps:
o Compare the netlist extracted from the layout with the schematic netlist.
o Fix any mismatches identified by the tool.
 Key Outputs: LVS-clean layout.
14. Final Verification (Sign-Off)
 Objective: Perform final checks, such as signal integrity analysis, electromigration
checks, and voltage drop analysis, to ensure design robustness.
 Steps:
o Run final checks on signal integrity (SI), electromigration (EM), and IR drop.
o Verify that the design is ready for fabrication with all design goals met.
 Key Outputs: Fully verified design ready for tape-out.
15. Tape-Out
 Objective: Prepare the final design for manufacturing and submit it to the foundry.
 Steps:
o Generate GDSII files containing the final layout.
o Submit the design for fabrication.
 Key Outputs: GDSII file and sign-off documentation ready for foundry tape-out.
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Aim:
Write a Verilog code for UART and carry out the following:
• To Verify the Functionality using test Bench
• Synthesize Design using constraints
• Tabulate Reports using various Constraints
Tool Required:
• Functional Simulation: Incisive Simulator (ncvlog, ncelab, ncsim)
• Synthesis: Genus

Design Information :
UART (Universal Asynchronous Receiver/Transmitter) is an integrated circuit in
microcontrollers designed for serial data communication, distinct from protocols such as I2C
or SPI. It facilitates both serial and parallel data transmission. The transmitter side includes a
transmit hold register, a shift register, and control logic, while the receiver side mirrors this
setup with its own registers and control logic. Both sections use a baud-rate generator to
synchronize the speed of data transmission and reception.
UART communication is straightforward, requiring only two wires: TX (transmit) and RX
(receive). This simplicity makes it popular in microcontrollers. For flow control, additional
RTS (Request to Send) and CTS (Clear to Send) lines can be used. UART data frames
typically contain start, stop, and optional parity bits to ensure data integrity. Despite its ease
of use, UART is not ideal for high-speed communication over long distances when compared
to more advanced protocols like SPI or I2C.
Creating a Workspace:
1. Make sure the Licensing Server is switched ON and the client is connected to the
server.
2. General Note: Before starting to work on a design, create a Workspace (Folder) for the
project individually.
3. Open a terminal from the Sub-Directory. In a terminal window, type csh in the
command prompt to invoke the C shell. #csh
4. To verify that the path to the software is properly set in the cshrc file. #source
/home/install/cshrc
5. A welcome string “Welcome to Cadence Tool Suite” appears indicating a terminal
ready to invoke Cadence Tools available for you.
6. Create <sourcecode>.tb and <testbench>.tb using gedit command and run using irun
and waveform is obtained.
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Waveform:

Synthesis and Report/Output Analysis

1. Getting Started
o Make sure you close out all the Incisive tool windows first
o Synthesis requires three files as follows,
Liberty Files (.lib)
Verilog/VHDL Files (.v or .vhdl or .vhd)
SDC (Synopsis Design Constraint) File (.sdc)
2. Creating an SDC File
3. Performing Synthesis
The Liberty files are present in the below path,
/home/install/FOUNDRY/digital/<Technology_Node_number>nm/dig/lib/
The Available technology nodes are 180nm ,90nm and 45nm.
In the terminal, initialise the tools with the following commands if a new terminal is
being used.
csh
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source /home/install/cshrc
The tool used for Synthesis is “Genus”. Hence, type “genus -gui” to open the tool.
The Following are commands to proceed,

1. read_libs /home/install/FOUNDRY/digital/90nm/dig/lib/slow.lib
2. read_hdl {uart.v} //Choose any one
3. elaborate
4. read_sdc constraints_top.sdc //Reading Top Level SDC
5. set_db syn_generic_effort medium //Setting effort medium
6. set_db syn_map_effort medium
7. set_db syn_opt_effort medium
8. syn_generic
9. syn_map
10. syn_opt //Performing Synthesis Mapping and Optimisation
11. report_timing > uart_timing.rep
//Generates Timing report for worst datapath and dumps into file
12. report_area > uart_area.rep
//Generates Synthesis Area report and dumps into a file
13. report_power > uart_power.rep
//Generates Power Report [Pre-Layout]
14. report_qor > uart_qor.rep
15. write_hdl > uart_netlist.v
//Creates readable Netlist File
16. write_sdc > uart_sdc.sdc
//Creates Block Level SDC
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Logic Equivalence Checking

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Physical Design
Tool Required:
• Functional Simulation: Incisive Simulator (ncvlog, ncelab, ncsim)
• Synthesis: Genus
• Physical Design: Innovus
Mandatory Inputs for PD:

 Gate Level Netlist [Output of Synthesis]

 Block Level SDC [Output of Synthesis]
 Liberty Files (.lib)
 LEF Files (Layer Exchange Format)
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Expected Outputs from PD:

 GDS II File (Graphical Data Stream for Information Interchange – Feed In for
Fabrication Unit).
 SPEF, SDF

Physical Design involves 5 stages as following :

After Importing Design,

 Floor Planning
 Power Planning
 Placement
 CTS (Clock Tree Synthesis)
 RoutingModule

Importing Design
To Import Design, all the Mandatory Inputs are to be loaded and this can be done either using
script files named with .globals and .view/.tcl or through GUI
Else, if you would like to import your design using GUI, open the Innovus tool and from the
GUI, go to File → Import Design.
• A new pop-up window appears.
• First load the netlist. You can browse for the file and select “Top cell : Auto Assign”.
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 Similarly select your lef files from /home/install/FOUNDRY/digital/90nm/dig/lef/

 Once LEF Files are loaded, your import design window is as follows.
 Next step is to create the power supply pins both VDD and VSS
 In order to load the Liberty File and SDC, create delay corners and analysis view,
select the “Create Analysis Configuration” option at the bottom.

 An MMMC browser Pops Up.

The order of adding the MMMC Objects is as follows.

1. Library Sets
2. RC Corners
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3. Delay Corners
4. Constraints (SDC)
Once all of them are added, Analysis Views are created and assigned to Setup and Hold.
In order to add any of the objects, make a right click on the corresponding label → Select
New.
 Adding Liberty Files under “Library Sets”

Similarly, add fast.lib with a label Fast or any identifier of your own.

 Adding RC Corners can also be done in a similar process. The temperature value can
be found under the corresponding liberty file. Also, cap table and RC Tech files can be
added from Foundry where available.
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 Delay Corners are formed by combining Library Sets with RC Corners.

 Similarly, SDC can be read in under the MMMC Object of “Constraints”.

 Analysis Views are formed from combinations of SDC and Delay Corner.
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 Once “Best” and “Worst” Analysis views are created, assign them to Setup and Hold.

 Once all the process is done, Click on “Save&Close” and save the script generated
with any name of your choice.
Make sure the file extension remains .view or .tcl
After saving the script, go back to Import Design window and Click “OK” to load
your design.

• To load the complete netlist and the analysis configuration to the Innovus tool.
• A rectangular or square box appears in your GUI if and only if all the inputs are read
properly.
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Floorplan
Steps under Floorplan :
1. Aspect Ratio [Ratio of Vertical Height to Horizontal Width of Core]
2. Core Utilisation [The total Core Area % to be used for Floor Planning]
3. Channel Spacing between Core Boundary to IO Boundary

• Select Floorplan → Specify Floorplan to modify/add concerned values to the above

Factors. On adding/modifying the concerned values, the core area is also modified.

Power Planning
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Steps under Power Planning :

1. Connect Global Net Connects
2. Adding Power Rings
3. Adding Power Strings
4. Special Route
Under Connect Global Net Connects, we create two pins, one for VDD and one for VSS
connecting them to corresponding Global Nets as mentioned in Globals file / Power and
GroundNets.
1. Select Power → Connect Global Nets.. to create “Pin” and “Connect to Global
Net” as shown and use “Add to list”.
2. Click on “Apply” to direct the tool in enforcing the Pins and Net connects to
Design and then Close the window.

In order to Tap in Power from a distant Power supply, Wider Nets and Parallel connections
improve efficiency. Moreover, the cells that would be placed inside the core area are expected
to have shorter Nets for lower resistance.
Hence Power Rings [Around Core Boundary] and Power Stripes [Across Core Boundary] are
added which satisfies the above conditions.
Select Power → Power Planning → Add Rings to add Power rings ‘around Core Boundary’.
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Select the Nets from Browse option OR Directly type in the Global Net Names separated by a
space being Case and Spelling Sensitive.
Select the Highest Metals marked ‘H’ [Horizontal] for Top and Bottom and Metals marked
‘V’ [Vertical] for Right and Bottom. This is because Highest metals have Highest Widths and
thus Lowest Resistance.
• Click on Update after the selection and “Set Offset : Centre in Channel” in order to
get the Minimum Width and Minimum Spacing of the corresponding Metals and then
Click “OK”.
• Similarly, Power Stripes are added using similar content to that of Power Rings.

• On adding Power Stripes, The Power mesh setup is complete as shown. However,
There are no Vias that could connect Metal 9 or Metal 8 directly with Metal 1
[VDD or VSS of Standard Cells are generally made up of Metal 1].
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• The connection between the Highest and Lowest Metals is done through Stacking
of Vias done using “Special Route”.
• To perform Special Route, Select Route → Special Route → Add Nets → OK.
• After the Special Route is complete, all the Standard Cell Rows turn to the Color
coded

Placement
• The Placement stage deals with Placing of Standard Cells as well as Pins.
• Select Place → Place Standard Cell → Run Full Placement → Mode → Enable
‘Place I/O Pins’ → OK → OK .

•
•
•
•
•
•
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Clock Tree Synthesis

The CTS Stage is meant to build a Clock Distribution Network such that every Register(Flip
Flop) acquires Clock at the same time (Atleast Approximately) to keep them in proper
communication
.
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Source the Script as shown in the above snapshot through the Terminal and then Select Clock
→ CCOpt Clock Tree Debugger → OK to build and view clock tree.

Report Generation and Design Optimization :

CTS Stage adds real clock into the Design and hence “Hold” Analysis also becomes
prominent. Hence, Optimizations can be done for both Setup & Hold, Timing Reports are to
be Generated for Setup and Hold Individually.
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Routing :
• All the net connections shown in the GUI till CTS are only based on the Logical
connectivity.
• These connections are to be replaced with real Metals avoiding Opens, Shorts,
Signal Integrity [Cross Talks], Antenna Violations etc.
• To run Routing, Select Route → Nano Route → Route and enable Timing Driven
and SI Driven for Design Physical Efficiency and Reliability.
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Display and Generating Timing Report :

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Output File Generation (.spef, .sdf, .v& .gds)

Extracting RC Data:
The capacitance and resistance values for all the nets in the design are extracted by the
Extract RC form.
Extraction is run in pre-route mode prior to signal routing and in post-route mode after the
signals are routed with NanoRoute. In post-route mode there are four effort levels to choose
from (low, medium, high and signoff) which increase with accuracy at the expense of longer
run-times.
The RC extraction mode can be changed by the Tools →Set Mode Specify RC Extraction
Mode form.
Select Timing - Extract RC
Write the SDF: Select Timing → Write SDF

GDSII:
The GDS File is a Binary Format File which is not human readable and is fed to the
Fabrication unit with data of various layers used depicted in terms of Geometrical Shapes.

Saving GDS => File Save GDS/OASIS→ <FileName>.gds→ OK

OMKAR SHIRASGAONKAR Workshop Day 2: 12-08-2024 240938016

ANALOG AND DIGITAL IC DESIGN FLOW USING CADENCE EDA

Analog Design : Differential Amplifier

Objective:
• To set up and run simulations on the Differential Amplifier Test design.
• To run the simulation for Differential Amplifier and plot the Transient, DC and AC
characteristics.
• Layout and Physical Verification of Differential Amplifier.
Theory:
The differential amplifier is one of the most commonly used circuit components in analog
integrated circuits, particularly in operational amplifiers (Op Amps). This amplifier can be
constructed using either BJTs or MOSFETs.
Its primary function is to amplify the voltage difference between two inputs (Vin+ - Vin-) by
a constant factor called the differential gain (Ad). The amplifier can have either a single
output or two outputs, where the key signal is the voltage difference between the two outputs.
Additionally, a differential amplifier is designed to reject the portion of the input signals that
are the same for both inputs (Vin+ + Vin-)/2, known as the common mode signal.
Getting Started:
1. Select “Open in Terminal”.
2. In a terminal window, type csh in the command prompt to invoke the C shell. #csh
3. To verify that the path to the software is properly set in the cshrc file. #source
/home/install/cshrc

4. “Welcome to Cadence Tool Suite” appears indicating a terminal ready to invoke

Cadence Tools available for you.
5. In the same terminal window, Type: virtuoso.
6. The virtuoso or Command Interpreter Window (CIW) appears at the bottom of the
screen.
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Schematic Capture of Differential Amplifier :

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Schematic Entry:
Objective: To create a library and build a schematic of a Differential Amplifier.
Execute Tools – Library Manager in the CIW or Virtuoso window to open Library Manager.

Creating a New Library:

1. In the Library Manager, execute File - New – Library. The new library form appears.
2. In the next “Technology File for New library” form, select option Attach to an
existing techfile and click OK.
3. In the “Attach Design Library to Technology File” form, select gpdk180 from the
cyclic field and click OK.
4. After creating a new library, you can verify it from the library manager.
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Creating a Schematic Cellview:

1. In the CIW or Library manager, execute File – New – Cellview.
2. Set up the New file form as follows:
3. Click OK when done in the above settings. A blank schematic window for the design
appears.

Adding Components to schematic:

1. Click the Instance fixed menu icon to display the Add Instance form.
2. Click on the Browse button. This opens a Library browser from which you can select
components and the symbol view.
3. After you complete the Add Instance form, move your cursor to the schematic
window and use LMB (left mouse button) to place a component.
gpdk180 nmos Model name = nmos1 (NM0, NM1) W= 3u; L=1u
gpdk180 nmos Model name = nmos1 (NM2) W= 4.5u; L=1u
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gpdk180 pmos Model name = pmos1 (PM0, PM1) W= 15u; L=1u

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4. After entering components, click Cancel in the Add Instance form or press Esc with
your cursor in the schematic window.

Adding pins to Schematic:

Use Create – Pin or the menu icon to place the pins on the schematic window.
1. Click the Pin fixed menu icon in the schematic window.
2. You can also execute Create – Pin or press p. The Add pin form appears.
3. Type the following in the Add pin form in the exact order leaving space between the
pin names.
vin1, vin2, vbias, vdd, vss input
vout output
4. Select Cancel from the Add pin form after placing the pins. In the schematic window,
execute View— Fit or press the f bindkey.

Adding Wires to a Schematic:

Add wires to connect components and pins in the design.
1. Click the Wire (narrow) icon in the schematic window. You can also press the w key,
or execute Create - Wire (narrow).
2. Complete the wiring as shown in figure and when done wiring press ESC key in the
schematic window to cancel wiring.
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Saving the Design:

1. Click the Check and Save icon in the schematic editor window.
2. Observe the CIW output area for any errors.
Symbol Creation:
Objective: To create a symbol for the Differential Amplifier
1. In the Differential Amplifier schematic window, execute Create — Cellview— From
Cellview.
2. The Cellview from Cellview form appears. With the Edit Options function active, you
can control the appearance of the symbol to generate.
3. Verify that the From View Name field is set to schematic, and the To View Name field
is set to symbol, with the Tool/Data Type set as SchematicSymbol.
4. Click OK in the Cellview from Cellview form. The Symbol Generation Form appears.
5. Modify the Pin Specifications as in the below symbol.
6. Click OK in the Symbol Generation Options form.
7. A new window displays an automatically created Differential Amplifier symbol.
8. Execute Create— Selection Box. In the Add Selection Box form, click Automatic. A
new red selection box is automatically added.
9. After creating symbol, click on the save icon in the symbol editor window to save the
symbol. In the symbol editor, execute File— Close to close the symbol view window.
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Building the diff_amplifier_tb Design

Objective: To build Differential Amplifier Test circuit using your Differential Amplifier

Creating the Differential Amplifier Test Cellview:

1. In the CIW or Library Manager, execute File— New— Cellview.
2. Click OK when done. A blank schematic window for the diff_ amplifier_tb design
appears.

Building the Diff_amplifier_test Circuit:

1. analogLib vsin AC Magnitude= 1v; Amplitude= 10u; Frequency= 10K
analogLib vdd, vss, gnd vdc=3.3v; vbias_NMOS=662m
2. Click the Wire (narrow) icon and wire your schematic.
3. Click on the Check and save icon to save the design.
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Schematic Capture of Diff_amplifier_test Circuit:

Analog Simulation with Spectre:
Objective:
• To set up and run simulations on the Differential Amplifier Test design.
• In this section, we will run the simulation for Differential Amplifier and plot the
transient, DC and AC characteristics.
Starting the Simulation Environment:
1. In the Diff_amplifier_test schematic window, execute Launch – ADE L. The Analog
Design Environment simulation window appears.
2. Choosing a Simulator:
• In the simulation window or ADE, execute Setup— Simulator/Directory/Host.
• In the Choosing Simulator form, set the Simulator field to spectre (Not spectreS) and
click OK.
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Setting the Model Libraries:

1. Click Setup - Model Libraries.
2. In the Model Library Setup form, click Browse and find the gpdk180.scs file in the
./models/spectre directory. Select NN in Section field, click Add and click OK.
3. Choosing Analyses: In the Simulation window, click the Choose - Analyses icon.
You can also execute Analyses - Choose.
4. The Choosing Analysis form appears. This is a dynamic form, the bottom of the form
changes based on the selection above.
5. To setup for transient analysis
a. In the Analysis section select tran
b. Set the stop time as 10m
c. Click at the moderate or Enabled button at the bottom, and then click Apply.
6. To set up for DC Analyses:
a. In the Analyses section, select dc.
b. In the DC Analyses section, turn on Save DC Operating Point.
c. Turn on the Component Parameter
d. Double click the Select Component, Which takes you to the schematic
window.
e. Select input signal Vsin for dc analysis.
f. In the analysis form, select start and stop voltages as -5 to 5 respectively.
g. Check the enable button and then click Apply.
7. To set up for AC Analyses form is shown in the previous page.
a. In the Analyses section, select ac.
b. In the AC Analyses section, turn on Frequency.
c. In the Sweep Range section select start and stop frequencies as 150 to 100M
d. Sweep type Automatic.
e. Check the enable button and then click Apply.
8. Click OK in the Choosing Analyses Form.
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Selecting Outputs for Plotting:

1. Select the nodes to plot when simulation is finished.
2. Execute Outputs – To be plotted – Select on Schematic in the simulation window.
3. Follow the prompt at the bottom of the schematic window, Click on output net Vo,
input net Vin of the Diff_amplifier. Press ESC with the cursor in the schematic after
selecting node.
Settings in ADE L window:
Running Simulation:
1. Execute Simulation – Netlist and Run in the simulation window to start the
simulation, this will create the netlist as well as run the simulation.
2. When simulation finishes, the Transient, DC and AC plots automatically will be
popped up along with netlist.
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LAYOUT FOR DIFFERENTIAL AMPLIFIER:

1. From the Virtuoso Schematic Editor , select “Launch →Layout XL”
2. The “Startup Option”. Select “Layout→ Create New” and “Configuration →
Automatic” and click on “OK”.
3. The “New File” window pops up. Verify the Library Name and Cell Name. “View”
and “Type” should be “layout”. Click on “OK”.
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4. The “Virtuoso Layout Suite XL Editing” window pops up. Click on “F” to fit the
cross wire to the center of the Virtuoso Layout Editor.
Note: We have created a Template for gpdk180.
5. To instantiate all the devices from the Virtuoso Schematic Editor, select
“Connectivity → Generate → All From Source”
6. The “Generate Layout” window pops up. Click on “OK” .

7. To edit the device properties, use a Right Mouse Click and select “Properties” .
8. The “Edit Instance Properties” window.
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Click on “File → Save” to Save the layout.

Physical Verification with ASSURA:
Physical Verification involves DRC (Design Rule Check) and LVS (Layout versus
Schematic) checks on the layout. These checks are performed using Assura.
To map the library file, select “Assura → Technology...”
DRC (DESIGN RULE CHECK):
• To run DRC check using Assura, select “Assura → Run DRC” .
• Check for the “Layout Design Source”, mention a “Run Name” (it can be any name)
and select “Technology → gpdk180” from the drop down and click on “OK” .
• The “Progress” window pops up.
• Click on “Yes” to get the results of DRC.
• In case of errors, the error information will be shown. If the error is selected, it points
out the issue which has to be reworked on the layout. Once done, Save the layout and
re-run the DRC check to make sure that the layout is DRC clean.
OMKAR SHIRASGAONKAR Workshop Day 2: 12-08-2024 240938016

LVS (LAYOUT VERSUS SCHEMATIC):

• To run the LVS check using Assura, select “Assura → Run LVS”.
• Check for the correctness of the Schematic and Layout to be compared in the
“Schematic Design Source” and the “Layout Design Source”, mention a “Run Name”
(it can be any name but avoid space) and select the Technology.
• After the LVS check gets completed, the “Run: “1_lvs”” window pops up.
• Click on “Yes” to see the result in the “LVS Debug”.
• Since the design is LVS clean, the message “Schematic and Layout Match” can be
seen. In case of violations, the respective messages are listed out.

QRC (RC / PARASITIC EXTRACTION):

• The tool used for Parasitic Extraction process is “Quantus”. Select “Assura → Run
Quantus” to invoke the tool and enter the “Quantus (Assura) Parasitic Extraction Run
Form”.
• Click on the “Setup” tab, check for “Technology → gpdk180” and select “Output→
Extracted View” as shown in Figure – 1.131. Click on “Extraction” tab.
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• Select “Extraction Type → RC” and the other options like “R only”, “C only” and
others can be checked as per the requirements. Select the “Ref Node → VSS”,
Disable HRCX and click on “OK.
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The impact of these parasitic devices can be checked out through the Backannotation(Post
Layout Simulation) process.

BACKANNOTATION (POST LAYOUT SIMULATION):

• To run the Post Layout Simulation, the extracted Parasitics have to be imported into
the Test Schematic. So, a New Configuration has to be created.
• To create a “New Configuration” select the Cell which has the Test Schematic and
select its “Schematic” view .

• The “New File” window pops up. Select the “Type → config” from the drop down.
Soon as the “Type → config” is selected, “View →config” and in “Application”,
“Open with → Hierarchy Editor” gets updated. Click on “OK”.
• Click on the drop down and select “Name → Spectre”, the name of the Simulator and
click on “OK”.
The updated “New Configuration” window pops up.
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• The “Top Cell → View → Schematic” has to be selected using the drop down. The
“New Configuration” window gets updated.
• Top Cell → View → Schematic.
• Click on “OK” and the “Virtuoso Hierarchy Editor: New Configuration” window
• pops up .
• Two types of views, “Table View” and “Tree View” can be seen. Select “Tree View”,
the instance “I0” which is the Instance number of the Symbol with which we had
created the Test Schematic can be seen.
• Select the Instance “I0”, make a Right Click, select “Set Instance View →
av_extracted”.
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• Click on “Launch → ADE L” and select “Session → Load State” to open the Saved
State.
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• Re-run the Simulation and check for the waveforms of Transient Analysis and DC
Analysis.

Stream Out Translation and Log File:

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