Marks Distribution

Topic : Number System

 13 H

0 0 0 1 0 0 1 1

8 bits= 1 Byte
Symbols and Abbreviations
Symbol/Abbreviations Meaning
Addr 16-bit address of the memory location.
Data 8-bit data
data 16 16-bit data
r, r1, r2 One of the registers A, B, C, D, E, H or L
A, B, C, D, H, L 8-bit register
A Accumulator
H-L Register pair H-L
B-C Register pair B-C
D-E Register pair D-E
PSW Program Status Word
Memory whose address is in H-L pair
M
[C000H] = 04 H [H-L] = C000 H,
Symbol/Abbreviations MEANING
Appearing at the end of the group of digits specifies
H​
hexadecimal, e.g. 2500H​
Rp One of the register pairs.​ Eg. H-L, B-C, D-E
Rh The high order register of a register pair eg. H-L => Rh=H
Rl The low order register of a register pair eg. H-L =>Rl=L
16 bit program counter, PCH is high order 8 bits and PCL low
PC
order 8 bits of register PC.​
CS​ Carry Status
The contents of the register identified within bracket​
[]​
eg. [2500H ] = 04 H
The content of the memory location whose address is in the
[ [] ] register pair identified within brackets​.
Eg. [H-L] = C000 H, [C000H] = 04 H => [[H-L]] = 04 H
Symbol/Abbreviations Meaning
^​ AND operation eg. [A] ← [A] ^ data
∨ OR operation eg. [A] ← [A] ∨ data
⊕ or ∀ Exclusive OR​​ eg. [A] ← [A] ∀ data
← Move data in the direction of arrow eg. [rd] ← [rs].
⇔ Exchange contents
M Memory whose address is in H-L pair
What's M ? [H-L]
C000 H 04 H M

[C000 H] = 04 H C001 H
[HL] = C000 H C002 H

C003 H
Memory
 Topic : Instruction Size

● MOV A, B - 1 Byte instruction size

MOV –> 1 Byte

● MVI A, 23 H - 2 Byte instruction size

MVI - > 1 Byte

+23 H - > 1 Byte
-
Total => 2Byte

● LXI H, C002 H - 3 Byte instruction size

LXI - > 1 Byte
+C002 H - > 2 Byte
-
Total => 3 Byte
Topic : Byte Places

LXI H, C002 H - 3 Byteinstruction size

LXI - > 1st Byte

02 - > 2nd Byte
C0. -> 3rd Byte
Topic : PROGRAMMING MODEL
OF 8085
Programming model of 8085 is a diagram of programmable registers.

Flags (8) Accumulator A (8)

B (8) C (8)
D (8) E (8)
H (8) L (8)
(Stock pointer ) SP(16)
(Program counter ) PC(16)
 PROGRAMMING MODELOF8085

• The 8085 microprocessor uses both 8-bit and 16-bit registers.

• The 8085 has eight addressable 8- bit registers.
• Six of these can be used as 8 - bit registers or 16 - bit register pairs.
• In addition, the 8085 contains two more 16-bit registers.

Flags (8) Accumulator A (8)

B (8) C (8)

D (8) E (8)

H (8) L (8)

(Stock pointer ) SP(16)

(Program counter ) PC(16)

 PROGRAMMING MODELOF8085
• The result of operation (Arithmetic and Logical) is stored in the accumulator.
• The registers BC, DE and HL are general purpose registers.
• They can be used as six 8-bit registers or three 16-bit registers.
• BC and DE are normally used as data registers while HL register pairs can
be used for addresspointing.

Flags (8) Accumulator A (8)

B (8) C (8)

D (8) E (8)

H (8) L (8)

(Stock pointer ) SP(16)

(Program counter ) PC(16)

 PROGRAMMING MODELOF8085
Flags (8) Accumulator A (8)
• Program counter is 16 bit register.
B (8) C (8)
• It contains the address of the next instruction to be
D (8) E (8)
executed.
H (8) L (8)

(Stock pointer) SP(16)

(Program counter ) PC(16)

C001 H C000 H Instruction 1

C001 H Instruction 2
Program Counter
C002 H Instruction 3
 PROGRAMMING MODELOF8085
Flags (8) Accumulator A (8)
• Stack pointer is also a 16 bit register.
B (8) C (8)
• It consist of top address of memory location called
D (8) E (8)
stack.
H (8) L (8)

(Stock pointer) SP(16)

(Program counter ) PC(16)

Push Pop

C001 H C000 H
Stack Pointer
C001 H

C002 H

Stack
 PROGRAMMING MODELOF8085
Flags (8) Accumulator A (8)
• 8085 has Five flags.
B (8) C (8)
• They are Zero (Z), Carry ( Cy ), Sign ( S ), Parity (P)
and Auxiliary Carry (Ac ) flag. D (8) E (8)
• The microprocessor uses these flags to test data
conditions. H (8) L (8)

(Stock pointer) SP(16)

(Program counter ) PC(16)

B7 B6 B5 B4 B3 B2 B1 B0
S Z - AC - P - CY
 Topic : Addressing Modes of 8085

• Each instruction requires some data on which it has to operate.

• There are different techniques to specify data forinstructions.
• These techniques are called addressingmodes.
 Topic : Types of Addressing Modes

Intel 8085 microprocessor has five addressing modes:

1. Register Addressing Mode

2. Direct Addressing Mode
3. Register Indirect Addressing Mode
4. Immediate Addressing Mode
5. Implicit Addressing Mode (Implied)
 1. Register Addressing Mode
• In this mode, the operand is in general purpose register.
• A, B, C, D, E, H and L are general purpose registers.
• In instruction, both source and destination are registers.
• Instructions using register addressing are very efficient.
• These instructions only use 1 byte of programming memory space.
• They are also executed quickly because they do not have to fetch
operands from memory.

Eg. MOV A, B
Let A = 03 H , B = 04 H
After MOV A, B
A = 04 H B = 04 H
 2. Direct Addressing Mode
• In this mode, the memory address of the operand is given in the
instruction itself.
• Either memory address of source or destination is given in the
instruction directly.
• Instructions using direct addressing are 3 byte instruction.

•Eg. LDA C000 H

Let A = 05 H and [C000 H]=04H
After LDA C000 H
A = 04H
 3. Register Indirect Addressing Mode
• In this mode, the memory address of the operand is specified by (given
in) register pair.
• Either memory address of source or destination is given in register pair.
HL, BC, DE are register pair.
• Instructions using register indirect addressing are 1 byte

•Eg. MOV A, M
Let A = 05 H , [HL]=C000F, [C000F]=04
After MOV A, M
A = 04 H and [C000F]=04
 4. Immediate Addressing Mode
• In this mode, the operand is specified (given) within the instruction itself.
• Either 8 bit data or 16 bit data given in the instruction.
• Instructions using immediate addressing are 2 byte or 3 byte Instruction.

•Eg. 1. MVI A, 23 H
Let A = 05 H ,
A = 23 H
Eg. 2. LXI H, C002 H
Let [HL] = C000H
After LXI H, C002 H
[HL] = C002 H
 5. Implicit / Implied Addressing Mode
• In this mode, address of source of data as well as address of destination of
result is fixed there is no need to give any operand along with
the instruction.

• Instructions using implicit addressing are 1 byte instructions.

•Eg. CMA
Let A = 04 H
After CMA
A=FB H
 Topic : Instruction Set

1. Data transfer group

2. Arithmetic group
3. Logical group
4. Branching group
5. Machine control group.
 1. Data Transfer Group :

1. MOV rd, rs: [MOVE REGISTER]

Format: [rd] ← [rs].
Addressing: Register addressing
Group: Data transfer group
Bytes: 1byte
Flag: None
Comment:
• This instruction will copy destination register with the content of source register.
• The contents of source register are not altered i.e. they remain unchanged.
• rd and rs can be of one of the registers A, B, C, D, E, H, L.

Example: Let [A]=05H and [B]=55H

Instruction: MOV A, B
After execution: [A] = 55H and B] = 55H
2. MOV r, M: [MOVE FROM MEMORY]
Format: [r] ← [[H-L]]
Addressing: Register Indirect addressing
Group: Data transfer group
Bytes: 1byte
Flag: None

Comment:
• This instruction will load destination register with content of memory location, whose
address is stored in H-L register pair.
• The contents of memory location are not altered.
• r can be any one of the registers A, B, C, D, E, H, L.

Example: Let, [H-L] = CFFF H, [CFFF]=35H and [B] =82H

Instruction: MOV B, M
After execution: [B]=35H
3. MOV M, r :[MOVE TO MEMORY]
Format: [[H-L] ← [r] ]
Addressing: Register Indirect
Group: Data transfer group
Bytes: 1byte
Flag: None

Comment:
• This instruction will copy the content of register r to the memory location, whose address
is placed in H-L register pair.
• r can be any one of the A, B, C, D, E, H, L.

Example: Let [HL] = F000 H and [F000] = 40 H and [C]= FA H then

Instruction: MOV M, C
After execution: [C]= FA H, [F000]= FA H
4. MVI r, data : [MOVE IMMEDIATE 8-BIT]
Format: [r] ← data (second byte)
Addressing: Immediate addressing
Group: Data transfer group
Bytes: 2 bytes
Flag: None

Comment:
• This instruction will load the register r with 8-bit immediate data specified in second byte
of instruction.

Example: Let [A] =04 H

Instruction: MVI A, 35 H
After execution: [A]= 35 H
5. MVI M, data, : [MOVE IMMEDIATE 8-BIT]
Format: [[H-L]] ← data (second byte)
Addressing: Immediate/Register indirect address
Group: Data transfer group
Bytes: 2 bytes
Flag: None

Comment:
• This instruction will load the memory location, whose address is stored in
• H-L pair with 8-bit immediate data specified in the second byte of instruction.

Example: Let [H] [L] = D000 H, [D000 H] = 04 H

Instruction: : MVI M, 35 H
After execution: [D000 H]= 35 H
6. LXI rp, 16-bit data : [LOADREGISTER PAIR IMMEDIATE]
Format: [rp] ← 16-bit data ==> [rh] ← byte 3, [rl] ← byte 2
Addressing: Immediate
Group: Data transfer group
Bytes: 3 bytes
Flag: None

Comment:
• The byte 3 of instruction is moved into high order register (rh) of register pair rp and byte
2 is moved into low order register (rl) of register pair.
• The register pairs can be BC, DE, HL or SP.
• SP (Stack pointer) is not a valid register pair, but it can be used in LXI instruction

Example: [H-L]=4500 H ==> [H] (byte 3) = 45 H and [L] (byte 2) = 00H

Instruction: : LXI H, 3500 H
After execution: [H-L]=3500 H ==> [H]= 35H, [L]=00 H
7. LDA addr : [LOAD ACCUMULATOR DIRECT]
Format: [A] ← [[byte 3] [byte 2]]
Addressing: Direct addressing mode
Group: Data transfer group
Bytes: 3 bytes
Flag: None

Comment:
• This instruction will load accumulator with content of memory location, whose address is
given in the instruction itself.
• The contents of memory location are not altered.

Example: Let [C500] = 26 H, [A]=04 H

Instruction: LDA C500 H
After execution: [A] =26 H and [C500]= 26 H
8. STA addr : [STORE ACCUMULATOR DIRECT]
Format: [[byte 3] [byte 2]] ← [A]
Addressing: Direct addressing
Group: Data transfer group
Bytes: 3 bytes
Flag: None

Comment:
• This instruction will load the content of accumulator into the memory location, whose
address is specified in the instruction.
• The contents of accumulator are not altered.

Example: Let [A] =35H, [C500] =04 H

Instruction: STA C500 H
After execution: [A]= 35 H and [C500] = 35 H
9. LHLD addr : [LOAD H AND L REGISTER DIRECT]
Format: [L] ← [[byte 3] [byte 2]]
[H] ← [[byte 3] [byte 2] + 1]
Addressing: Direct addressing
Group: Data transfer group
Bytes: 3 bytes
Flag: None

Comment:
• I this instruction, the 1st byte gives the opcode and 2nd and 3rd byte give 16-bit address
of memory location in usual convention.
• The contents of memory location whose address is specified in the instruction are loaded
into register L and the content of next memory location loaded in register H.

Example: Let [2100 H]=31 H and [2101 H] = 52 H

Instruction: LHLD 2100 H
After execution: [H]= 52 H and [L]=31 H
For example:
10. SHLD addr : [STORE H AND L REGISTERSDIRECT]
Format: [byte 3] [byte 2]] ← [L]
[[byte3][byte2] +1] ← [H]
Addressing: Direct addressing
Group: Data transfer group
Bytes: 3 bytes
Flag: None

Comment:
• The contents of register L are transferred to the memory location whose address is
specified by byte 2 and byte 3 of the instruction.
• The contents of register H are moved to succeeding memory location.
Example: Let [H]= 32 H and [L]= 35 H
Instruction: SHLD 2100 H
After execution: [2100] = 35 H
[21011 = 32 H
11. LDAX rp : [LOAD ACCUMULATOR INDIRECT]
Format: [A] ← [[rp]]
Addressing: Register indirect
Group: Data transfer group
Bytes: 1 byte
Flag: None

Comment:
• The contents of memory location, whose address is stored in register pair rp are loaded
into accumulator.
• The content of memory location remain unchanged. rp can be B(i.e. B and C) or D(i.e. D
and E)

Example: Let [B]= 25 H, [C] =25 H => [B-C]= 2525 H and [2525]= 33 H
Instruction: LDAX B
After execution: [A] =33 H
12. STAX гр : [STORE ACCUMULATOR INDIRECT]
Format: [[rp]] ← [A]
Addressing: Register Indirect addressing
Group: Data transfer group
Bytes: 1 byte
Flag: None

Comment:
• The contents of accumulator are transferred to the memory location whose address is
stored in register pair rp.
• The valid register pairs are B(i.e. B&C) and D e.il D& E)

Example: Let [D][E] =2525 H and [2525]=04 H and [A] =55 H

Instruction: STAX D
After execution: [2525] = 55 H and [A] =55 H
13. XCHG : [EXCHANGE H.AND L WITH D AND E]
Format: [H] ← [D]
[L] ← [E]

Addressing: Register
Group: Data transfer group
Bytes: 1 byte
Flag: None

Comment:
• The contents of register H are exchanged with that of register D and the contents of
register L are exchanged with that of register E.

Example: Let [ H ] = 23H, [L] = 32H, [D] = 53H and [E] = 55H
Instruction: XCHG
After execution: [H]=53 H and [L]=55H, [D]= 23 H and [E]= 32 H
 2. ArithmeticGroup :

1. ADD r : [ADD REGISTER]

Format: [A] ← [A] + [r]

Addressing: Register addressing

Group: Arithmetic group
Bytes: 1 byte
Flag: All

Comment:
• The contents of register r are added to the content of accumulator.
• The result is stored in accumulator.
• All the flags may be affected.

Example: Let, [D] = 35 H and [A] =05 H

Instruction: ADD D
Addition: 35H = 0 0 1 1 0 1 0 1
+05H = 0 0 0 0 0 1 0 1
-
ЗА Н = 0 0 1 1 1 0 1 0

S=0, Z=0, AC=0 P=1, Cy=0

After execution: [A]= ЗА Н

Flag Register = 0 0 - 0 - 1 - 0

[D] = 35 H
2. ADD M : [ADD MEMORY CONTENT OT ACCUMULATOR]

Format: [A] ← [A]+[[H] [L]]

Addressing: Register Indirect addressing

Group: Arithmetic group
Bytes: 1 byte
Flag: All

Comment:
• The contents of accumulator are added to the content of memory location, whose
address is stored in H-L pair.
• The result is placed in accumulator.
• All flags may beaffected.

Example: Let [H-L] = D000 H, [D000] = 35 H and [A] = 05 H

Instruction: ADD M
After execution: [A] = 3A H and [D0001]= 35 H
3. ADI data : [ADD IMMEDIATE TO ACCUMULATOR]

Format: [A] ← [A]+ data (byte 2)

Addressing: Immediate addressing

Group: Arithmetic group
Bytes: 2 bytes
Flag: All

Comment:
• This instructions adds the 8-bit immediate data specified in second byte of instruction to
the content of accumulator.
• All flags may beaffected.

Example: Let [A] = EA H

Instruction: ADI 15 H
After execution: [A]= FFH
4. ADC r : [ADD REGISTER TO ACCUMULATOR WTIH CARRY]

Format: [A] ← [A]+[r] +[Cy]

Addressing: Register addressing
Group: Arithmetic group
Bytes: 1 byte
Flag: All

Comment:
• This instructions adds the content of accumulator to the content of register and the
content of the carry flag.
• The result is placed in accumulator.
• All flags may beaffected.

Example: Let[A]=5FH, [D]=33H and [Cy]=01H

Instruction: ADC D
After execution: [A]= 93H
5. ADC M : [ADD MEMORY CONTENT TO ACCUMULATOR WITH CARRY]

Format: [A] ← [A] + [H-LI + [Cy]

Addressing: Register Indirect
Group: Arithmetic
Bytes: 1 byte
Flag: All

Comment:
• The contents of memory location whose address place in H-L register pair and content of
Cy flag are added to the content of accumulator.
• The result is placed in accumulator.

Example: Let [HL] = F000H , [F000H] = 05 H, [A] = 35 H,[Cy] =00H

Instruction: ADC M
After execution: [A] =3AH
6. ACI data : [ADD IMMEDIATE TO ACCUMULATOR WITH CARRY]

Format: [A] ← [A] + data + [Cy]

Addressing: Immediate addressing
Group: Arithmetic group
Bytes: 2 bytes
Flag: All

Comment:
• This instruction adds the content of accumulator to the 8-bit immediate data specified in
second byte of instruction along with the content of carry flag.
• The result is placed in accumulator.
• All flags may beaffected.

Example: Let : [Cy] = 1H & [A] =05 H

Instruction: ACI 55 H
After execution: [A] = 5B H
7. SUB r : [SUBTRACT REGISTER FROM ACCUMULATOR]

Format: [A] ← [A] - [r]

Addressing: Register addressing
Group: Arithmetic instructions group
Bytes: 1 byte
Flag: All

Comment:
• The contents of register r are subtracted from the content of accumulator.
• The result is placed in accumulator. Al the flags may be affected.

Example: [A]=37H
[C] = 40 H
Instruction : SUB C
11110111
[C]:40H = 0 1 0 0 0 0 0 0. 1'scomplement = 0 0 0 0 1 0 0 0
1'scomplement = 1 0 1 1 1 1 1 1 +1
+1 ----------------------------
---------------------------- 0 0 0 0 1 0 01
2'scomplement = 1 1 0 0 0 0 0 0
+[A]:37H = 0 0 1 1 0 1 1 1
-------------------- Result: [A] = 09 H
11110 11 1
0
Complement carry:
←

11110111
1
The result, as a negative number, will be in 2's
complement and thus the carry (Borrow) flag is
Flags: S = 1 , Z = 0 , Ac = 0 set.
P =0, Cy=1
8. SUB M : [SUBTRACTMEMORY FROM ACCUMULATOR]

Format: [A] ← [A] -[[H-L]]

Addressing: Register Indirect
Group: Register Indirect
Bytes: 1
Flag: All

Comment:
The content of memory of memory location, whose address stored in H-L register pair is subtracted from
the content of accumulator. The result is placed in the accumulator.

Example: [HL] = 2500H

[2500] = 05 H
[A] = 07 H
Instruction: SUB M
After execution: [A]=02H
9. SUI data: [SUBTRACT IMMEDIATE FROM ACCUMULATOR]

Format: [A] ← [A] - data

Addressing: Immediate addressing
Group: Data transfer group
Bytes: 2 bytes
Flag: All

Comment:
• The 8-bit immediate data specified in the second byte of the instruction si subtracted from the content
of accumulator.
• Result is placedin accumulator.
• All the flags may be affected.

Example: Let, [A]= 1F H

Instruction: SUI 1FH
After execution: [A] = 00H
10. SBB r : [SUBTRACT REGISTER AND BORROW FROM ACCUMULATOR]

Format: [A] ← [A] - [r] - [Cy]

Addressing: Register addressing
Group: Arithmetic group
Bytes: 1 byte
Flag: All

Comment:
• The contents of register r and carry bit are subtracted from the contents of accumulator.
• The result is placedin accumulator.
• All the flags may be affected.

Example: [A] = 37H

[B] = 3FH
[Cy]=01 H
Instruction : SBB B
After execution : [A] = F7H
11. SBB M : [SUBTRACT MEMORY CONTENT AND BORROW FROM CCUMULATOR]

Format: [A] ← [A] - [[H][L]]- [Cy]

Addressing: Register Indirect addressing
Group: Arithmetic group
Bytes: 1 byte
Flag: All

Comment:
• The contents of memory location whose address is stored in H-L pair along with carry bit are
subtracted from the contents of accumulator.
• Result is placedin accumulator.
• All the flags may be affected.

Example: Let [H-L] = 2500 H, [2500] = 05 H,

[ A ] = 0 7 H and [Cy] =0
Instruction : SBB M
After execution : [A] = 02 H
12. SBI data : [SUBTRACT IMMEDIATE WITH BORROW]

Format: [A] ← [A] - data - [Cy]

Addressing: Immediate addressing
Group: Arithmetic group
Bytes: 2 bytes
Flag: All

Comment:
• The 8-bit immediate data, specified in the second byte of instruction is subtracted along with the carry
bit from the content of accumulator.
• The result is placedin accumulator.
• Al the flags may beaffected.

Example: Let [A] =32 H, [Cy] =1H

Instruction: SBI 31 H
After execution: [A] =0
13. INR r : [INCREMENT REGISTER CONTENT BY 1]

Format: [r] ← [r] + 1

Addressing: Register addressing
Group: Arithmetic group
Bytes: 1 byte
Flag: S, Z, P, Ac

Comment:
• The contents of register r incremented by one and the results are stored in the same place.
• Al the flags except carry flag may be affected.
• The register r can be A, B, C, D, E, Hand L.

Example: Let [B] =01H

Instruction: INR B
After execution: [B] = 02H
14. INR M : [INCREMENTMEMORY CONTENT BY1 ] 14)

Format: [[H][L] ← [H] [L]] + 1

Addressing: Register indirect
Group: Arithmetic instruction
Bytes: 1 byte
Flag: S, Z, P, Ac except Cy

Comment:
The content of memory location whose address is stored in H-L register pair is incremented by one and
result again i.e stored on the same place.

Example: [H-L] = 2500 H

[25001 = 04 H
Instruction: INR M
After execution: [25001 = 05 H
14. INR M : [INCREMENTMEMORY CONTENT BY1 ]

Format: [[H][L] ← [H] [L]] + 1

Addressing: Register indirect
Group: Arithmetic instruction
Bytes: 1 byte
Flag: S, Z, P, Ac except Cy

Comment:
The content of memory location whose address is stored in H-L register pair is incremented by one and
result again i.e stored on the same place.

Example: [H-L] = 2500 H

[25001 = 04 H
Instruction: INR M
After execution: [25001 = 05 H
15. INX rp : [INCREMENT REGISTER PAIR BY 1]

Format: [rp] ← [rp] + 1

Addressing: Register addressing
Group: Arithmetic group
Bytes: 1 byte
Flag: None

Comment:
• This instruction increments the content of register pair rp by .
• 1 No flags are affected. The instruction views the contents of the two registers as a 16-bit number.

Example: Let [HL] = D000 H

Instruction: INX H
After execution: [HLI =D001 H
16. DCR r : [DECREMENTREGISTER BY 1]

Format: [r] ← [r]-1

Addressing: Register
Group: Arithmetic
Bytes: 1 byte
Flag: S, Z, P, Ac except Cy

Comment:
• The content of register is decremented by 1 and the results are stored in the same place.

Example: [D] = 01H

Instruction: DCR D
[DI: 00H
17. DCR M : [DECREMENT MEMORY CONTENT BY 1]

Format: [H]L]] ← [H][L]] - 1

Addressing: Register indirect addressing
Group: Arithmetic group
Bytes: 1 byte
Flag: S, Z, Ac, P except Cy

Comment:
• This instruction decrements the content of memory location, whose address is stored in H-L pair by
1and the result is placed at sameplace.
• All flags except carry flags are affected.

Example: Let [H-L] = D000H and [D000] =2A H

Instruction: DCR M
After execution: [D000]= 29 H
18. DCX p : [DECREMENT REGISTER PAIR BY 1]

Format: [rp] ← [rp] - 1

Addressing: Register addressing
Group: Arithmetic group
Bytes: 1 byte
Flag: None

Comment:
• This instruction decrements the content of register pair rp by 1.
• No flags are affected.
• This instruction views the contents of the two registers as a 16-bit number.

Example: Let [DE] = D000 H

Instruction: DCX D
Afterexecution: [DE] = CFFF H
19. DAD rp : [ADD REGISTER PAIR TO H AND L REGISTER]

Format: [HIL] ← [H] [L] + [rh] [rl]

Addressing: Register addressing
Group: Arithmetic group
Bytes: 1 byte
Flag: Cy

Comment:
• The contents of register pair rp are added to the contents of H-L pair.
• Result is placed in register H and L.
• Only carry flag is affected.

Example: Let, [H] = 03 H, [L] = 05, [D] = 15 H and [E] = 12 H.

Instruction: DAD D
After execution: [L] = 05 + 12= 17 H
[H] = 03 + 15 = 18 H
[H-L] = 1817 H
20. DAA : [DECIMAL ADJUST ACCUMULATOR]

Addressing: Implied addressing

Group: Arithmetic group
Bytes: 1 byte
Flag: All

Comment:
The eight bit number in the accumulator is adjusted to form two four-bit Binary coded Decimal digits by this
instruction. It can be done by following process:

LSB=Least Significant Bits. MSB= Most Significant Bits

1) If the value of the LSB of the A (A3 - A0) is > 9 or if the AC flag is set =1, 6 (06) is added to LSB of A
2) If the value of MSB of the A (A7 - A4) is > 9 or if the Cy =1, 6 (60) is added to the MSB of A
3) If both 4 LSBs and 4 MSBs of A are > 9 or flags Ac=1 and Cy=1 are set respectively then 66 add to
the accumulator content.
1. LSB > 9 or AC =1 then 6 are added to LSB
2. MSB > 9 or Cy =1 then 6 are added to MSB
3. LSB > 9 and MSB >9 and AC=1 and Cy=1 then 66 to A
[ Note : This instruction must always follow an addition instruction for two BCD numbers. It
can not be used to adjust results after subtraction.]

Example:

Add 12BCD to 39BCD

39 BCD = 0 0 1 1 1 0 0 1
+12CD = 0 0 0 1 0 0 1 0

51BCD = 0 0 0 1 0 0 1 0 = 4BH

The binary sum is 4B H.

But BCD sum is 51 To adjust result add 6 to lower nibble
 4B = 0 1 0 0 1 0 1 1
+06 = 0 0 0 0 0 1 1 0

51 = 0 1 0 1 0 0 0 1

Thus [A] = 51 i.e. contents are adjusted to BCD values.

 3. Logical Group

A B A^B AvB A⊕B

0 0 0 0 0
0 1 0 1 1
1 0 0 1 1
1 1 1 1 0
1. ANA r : [LOGICAL AND WITH ACCUMULATOR]

Format: [A] ← [A] ^ [r]

Addressing: Register addressing
Group: Logical group
Bytes: 1 byte
Flag: S, Z, P are modified Cy =0, Ac = 1

Comment:
• The contents of accumulator are logically ANDed with the content of register r.
• Result is placedin accumulator.
• S, Z, and P flags aremodified.
• The Cy flag is reset and Ac flag is set.

Example : Let , [A] = 25 H and [B] = 31 H

Instruction: ANA B
 25H = 0 0 1 0 0 1 0 1
31 H = ^ 0 0 1 1 0 0 0 1

21 H = 0 0 1 0 0 0 0 1

After execution : [A] = 21 H

Flags: S = 0, Z = 0, P = 1, Ac =1,Cy=0
2. ANA M : [LOGICAL AND WITH MEMORY]

Format: [A] ← [A] ^ [H][L]]

Addressing: Register indirect addressing
Group: Logical group
Bytes: 1 byte
Flag: S, Z, P modified Cy = 0, Ac = 1

Comment:
• The contents of accumulator are logically ANDed with the content of memory location, whose address
is stored in H-L pair.
• The result is placed in accumulator. The S, Z and P flags are modified.
• The Cy flag is reset and the Ac flag is set.

Example : Let [A] = 3B H, [H-L] = D000 H and [D000] = 29 H

Instruction: ANA M
[A] : 3BH = 0 0 1 1 1 0 1 1
AND 29H = 0 0 1 0 1 0 0 1

0 0 1 0 1 0 0 1 = 29H

After execution: [A] = 29 H

Flags : S = 0, Z = 0, P = 0, Ac = 1, Cy =0
3. ANI data : [AND IMMEDIATE WITHACCUMULATOR]

Format: [A] ← [A] ^ data

Addressing: Immediate addressing
Group: Logical group
Bytes: 2 bytes
Flag: S, Z, P are modified Cy = 0, Ac =1

Comment:
• The contents of accumulator are logically ANDed with the 8-bit immediate data specified in the second
byte of the instruction.
• The result is placed inthe accumulator.
• The S, Z, and P flags are modified. Cy flag is cleared and Ac flag is set.

Example : Let [A] = 1 H

Instruction: ANI 1 H
After execution: [A]= 11 H
4. ORA r : [LOGICALLY OR WITH ACCUMULATOR]

Format: [A] ← [A] v [r]

Addressing: Register addressing
Group: Logical group
Bytes: 1 byte
Flag: Z, S, P are modified.Ac and Cy are reset

Comment:
• The contents of accumulator are logically Inclusive ORed with the contents of register r.
• The result is placedin accumulator.
• r may be any one of A, B, C, D, E, H and L registers.
• Ac and Cy flags are reset.

Example : Let [A] = 29 H and [B] = 35 H

Instruction: ORA B

[A]: 29H = 0 0 1 0 1 0 0 1
OR [B]:35H = 0 0 1 1 0 1 0 1

0 0 1 1 1 1 0 1 = 3D H

After execution : [A] = 3D H

Flags: S = 0, Z = 0, P = 0, Ac = 0, Cy = 0
5. ORA M : [LOGICALLY OR WITH MEMORY]

Format: [A] ← [A] v [H] [L]]

Addressing: Register Indirect
Group: Logical
Bytes: 1 byte
Flag: Z, S, P are modified,Ac and Cy are reset

Comment:
• The contents of accumulator are logically ORed with the contents of memory location, whose address
is placed in H-L registerpair.
• The result is placedin accumulator.
• Ac and Cy flags are reset.

Example : [A] = 03 H
[H-L] = D000H
[D000] = 81 H

Instruction: ORA M
 03H = 0 0 0 0 0 0 1 1
OR 81H = 1 0 0 0 0 0 0 1

83H = 1 0 0 0 0 0 1 1

After execution: A = 83 H

Flags : S = 1, Z = 0 , P = 0 , Cy = 0 , Ac = 0
6. ORI data : [LOGICALLY OR IMMEDIATE]

Format: [A] ← [A] v data

Addressing: Immediate addressing
Group: Logical group
Bytes: 2 bytes
Flag: S, Z, P are modified, Cy and Ac are reset.

Comment:
• The contents of accumulator are logically ORed with the 8-bit immediate data specified in the second
byte of the instruction.
• The result is placedin accumulator.
• The S, Z and P flags areaffected.
• The Cy and Ac flags arereset.

Example : Let, [A] = 35 H

Instruction: ORI 99H

[A] = 35H = 0 0 1 1 0 1 0 1
OR 99H = 1 0 0 1 1 0 0 1

1 0 1 1 1 1 0 1 = BDH

After execution: [A]= BDH

Flags : S = 1, Z=0 , P = 1, Ac = 0, Cy = 0
7. XRA r : [EXCLUSIVE OR WITH ACCUMULATOR]

Format: [A] ← [A] ⊕ [r]

Addressing: Register addressing
Group: Logical group
Bytes: 1 byte
Flag: S, Z, P are modified , Cy = 0 , Ac = 0

Comment:
• The contents of accumulator are logically exclusive-ORed with the contents of register r.
• The result is placedin accumulator.
• The r may be any one of the A, B, C, D, E, H and L register.
• The Cy and Ac flags arereset.

Example : Let [A] = 25H and [B] = 39H

Instruction: XRA B

[A] : 25H = 0 0 1 0 0 1 0 1
XOR [B] : 39H = 0 0 1 1 1 0 0 1

0 0 0 1 1 1 0 0 = 1CH
After execution: [A]= 1CH

Flags : S= 0, Z = 0, P = 0, Ac = 0, Cy = 0
8. XRA M : [EXCLUSIVE OR WITH MEMORY]

Format: [A] ← [A] ⊕ [H-L]]

Addressing: Register Indirect
Group: Logical group
Bytes: 1 byte
Flag: S, P, Z are modified Cy and Ac are reset.

Comment:
• The content of the accumulator are logically exclusive OR-ed with the Content of the memory location
whose address placed in H-L register pair.
• The results placed in theaccumulator.
• The Cy and Ac flags arereset.

Example : Let [A] = 77 H

[H-L] = D000H
[D000] = 56 H
Instruction: XRA M

[A] : 77H = 0 1 1 1 0 1 1 1
XOR [D000]:56H = 0 1 0 1 0 1 1 0

00100001
After execution: [A] = 21 H

Flags : S= 0, Z= 0, P = 1, Cy = 0, Ac = 0
9. XRI data : [EXCLUSIVE OR IMMEDIATE WITH ACCUMULATOR]

Format: [A] ← [A] ⊕ data

Addressing: Immediate addressing
Group: Logical group
Bytes: 2 byte
Flag: S, Z, P are modified Ac =0, Cy =0

Comment:
• The content of accumulator are logically exclusive- OR'ed with the 8-bit immediate data specified in
second byte of instruction.
• The result is placedin accumulator.
• The S, Z, and P flags are affected. The Cy and Ac flags are reset.

Example : Let [A] = 5B H

Instruction: XRI 35 H

[A] : 5B H = 0 1 0 1 1 0 1 1
Data 35H = 0 0 1 1 0 1 0 1

0 1 1 0 1 1 1 0 = 6E H
After execution: [A] = 6E H

Flags : S=0, Z=0 , P=0 , Cy=0 ,Ac=0

10. CMP r : [COMPARE WITH ACCUMULATOR]

Format: [A] - [r]

Addressing: Register addressing
Group: Logical group
Bytes: 1 byte
Flag: All

Comment:
• This instruction compares the content of the register with content of accumulator.
• Comparison is done using subtraction of content of register from the content of accumulator.
• The content of accumulator remains unchanged.
• The result of comparison is shown by setting the flags as :

a) If [A] < [r] then Cy flag is set to 1

b) If [A] = [r] then Z flag is set to 1
c) If[A] > [r] then Z and Cy flags are reset
The 'r' may be any one of the A, B, C, D, E, H and L register.

Example: Let [A]= 15 Hand [H]= 57 H

Instruction: CMP H
After execution: Cy = 1, Z = 0
11. CMP M : [COMPARE MEMORY WITH ACCUMULATOR]

Format: [A] - [[H-L]]

Addressing: Register indirect addressing
Group: Logical group
Bytes: 1 byte
Flag: All

Comment:
• This instruction compares the content of memory location whose address is stored in H-L pair with the
content of accumulator by subtracting the content of memory location from the content of accumulator.
The content of accumulator remains unchanged.
• The result of comparison is shown by setting the flags as below:

a) [A] < [[H][L]] then Cy flag is set to1

b) [A] = [[H][L]] then zero flag is set to 1
c) [A] > [[H][L]] then both Cy and Z flags are reset
12. CPI data : [COMPARE IMMEDIATE WITH ACCUMULATOR]

Format: [A] - data

Addressing: Immediate addressing
Group: Logical group
Bytes: 2 byte
Flag: All

Comment:
• This instruction compares the 8-bit immediate data, specified in the second byte of instruction, by
subtracting it from the contents of accumulator.
• The content of accumulator remains unchanged.
• The result of comparison is shown by setting flags as :

a) [A] < 8-bit data then Cy flag is set to1

b) [A] = 8-bit data then zero flag is set to 1
c) [A] > 8-bit data then both Cy and Z flags are reset
13. RLC : [ROTATE ACCUMULATOR LEFT]

Format: [An+1] ← [An], [Ao] ← [A7], [Cy] ← [A7]

Addressing: Immediate addressing
Group: Logical group
Bytes: 1 byte
Flag: Only Cy

Comment:
• The contents of accumulator are rotated to left by one bit position.
• The bit A7 is stored in bit A0 as well as in carry flag.
• It is shown in following figure :
Example: Let [A] =93 Hand [Cy] =0
Instruction: RLC

A7 A0
Before instruction: 1 0 0 1 0 0 1 1
0
Cy Accumulator

After execution: RLC A7 A0

Cy 1 0 0 1 0 0 1 1 1
Accumulator
14. RRC : [ROTATE ACCUMULATOR RIGHT]

Format: [An] ← [An+1], [A7] ←[A0], [Cy] ← [A0]

Addressing: Implied addressing
Group: Logical group
Bytes: 1 byte
Flag: Cy

Comment:
• The contents of accumulator are rotated right by one bit position.
• The bit A0 of accumulator is stored in the bit A7 as well as in carry flag.
• Only the Cy flag is affected.
• The function of RRC is shown in the following figure.
Example: [A] = 83 H [Cy] = 0

A7 A0

0 1 0 0 0 0 0 1 1
Cy Accumulator

Instruction: RRC

A7 A0
After execution:
1 1 1 0 0 0 0 0 1
Cy Accumulator

Thus [A] = C1H, [Cy] =1

15. RAL : [ROTATE ACCUMULATOR LEFT THROUGH CARRY]

Format: [An+1] ← [An], [A0] ← [Cy], [Cy] ← [A7]

Addressing: Implied addressing
Group: Logical group
Bytes: 1 byte
Flag: Cy

Comment:
• This instruction rotates the content of accumulator one position left through carryflag.
• The carry flag status is stored in bit A0 of accumulator and the bit A7 of accumulator is
stored in carry flag.
• The function of RAL is shown in following figure:
 Example: Let [A] = 29 H,
[Cy]= 1H

A7 A0
1 0 0 1 0 1 0 0 1
Cy Accumulator

Instruction: RAL
A7 A0

0 0 1 0 1 0 0 1 1
Cy Accumulator

Thus [Al=53H
[Cy] = 0
16. RAR : [ROTATE ACCUMULATOR RIGHT THROUGH CARRY]

Format: [An] ← [An+1], [A7] ← [Cy], [Cy] ← [A0]

Addressing: Implied addressing
Group: Logical group
Bytes: 1 byte
Flag: Cy

Comment:
• The contents of the accumulator are rotated to right by one bit position through carry flag.
• The carry flag status is stored in bit A7 of accumulator and the bit A0 of accumulator is
stored in carry flag.
• Only the carry flag is affected.
• The function of RAR is shown in the following figure.
 Example: Let [AJ =3B H,
[Cy] =OH

0 0 0 1 1 1 0 1 1
Cy Accumulator

Instruction: RAR

1 0 0 0 1 1 1 0 1
Cy
Accumulator
Thus [A]= 1DH
[Cy] =1
17. CMA : [COMPLEMENT THE ACCUMULATOR]

Format: [A] ← [A]

Addressing: Implied addressing
Group: Logicalgroup
Bytes: 1 byte
Flag: None

Comment:
• This instruction complements the content of accumulator.
• Result is placed in the accumulator.

Example: Let, [A]= 3BH =00111011

Instruction: CMA
After execution: [A] =11000100
i.e. [A] = CAH
18. CMC : [COMPLEMENT CARRY]

Format: [Cy] ← [Cy]

Addressing: Implied addressing
Group: Logical group
Bytes: 1 byte
Flag: Cy

Comment:
• The carry flag is complemented.
• No other flags are affected.

Example: Let [Cy] =1H

Instruction: CMC
After execution: [Cy]= 0 H
19. STC : [SET CARRY]

Format: [Cy] ← 1
Addressing: Implied addressing
Group: Logicalgroup
Bytes: 1 byte
Flag: Cy

Comment:
• This instruction sets carry flag to 1.
• No other flags are affected.

Example: Let [Cy] =0H

Instruction: STC
After execution: [Cy]= 1 H
 4. Branching Group:
1. JMP addr : [JUMP UNCONDITIONALLY]]

Format: [PC] ← addr

Addressing: Immediate addressing
Group: Branching group
Bytes: 3 bytes

Comment:
• The control is transferred unconditionally to the memory location, whose address is
specified in the instruction.
1. JMP addr :

C000H C001 H MVI A, 02H. A=02 H

C002 H DCR A A=01 H
C003 H JMP C005 H
C004 H MOV B,A B=01 H
C005 H HLT
2. jcondition addr : [Conditional JUMP]

Format: [PC] ← addr

Addressing: Immediate addressing
Group: Branching group
Bytes: 3 bytes

Comment:
• In conditional jump instructions, the jump is taken only if the condition is true.
 • The conditional jump instructions and conditions are as givenbelow.

Opcode Description Flag Status

JNZ Jump on not zero Z=0
JZ Jump on zero Z=1
JNC Jump on zero CY=0
JC Jump on Carry CY=1
JPO Jump on odd parity P=0
JPE Jump on even parity P=1
JP Jump on plus S=0
JM Jump on minus S=1

If the condition is satisfied, then only the address of the memory location specified
in the instruction is loaded in the program counter.
2. jcondition addr :

C000H C001 H MVI A, 01H A=01 H

C002 H DCR A. A=00 H
C003 H JZ C005H. Z=1
C004 H MOV B,A. b
C005 H HLT
3. CALL addr : [UNCONDITIONAL SUBROUTINE CALL]

Format: [[SP] - 1]← [PC H]

[[SP] - 2] ← [PC L]
[SP] ← [SP]- 2
[PC]← addr

Addressing: Immediate addressing

Group: Branching group
Bytes: 3 bytes

Comment:
• CALL instruction is used to call subroutine unconditionally.
• Before the control is transferred to the subroutine, the address of next instruction to be
executed the main program is stored in the stack.
• The contents of SP are decremented by 2.
• Then, the program jumps to the subroutine whose starting address is specified in the
instructions.
 3. CALL addr :

Main Program :
C000H C001 H MVI A, 01H A=01 H
C002 H JMP D000 H In JMP backup is notcreated
C003 H MOV B,A
C004 H HLT

Subroutine Program

D000 H DCR A. A=00 H

D001 H RET
3. CALL addr : [PC H]=C0, [PC L]=03 => [PC] =C003 H
[SP]=E011 H
Main Program :
C000H C001 H MVI A, 01H A=01 H [[SP] - 1]← [PC H] => [E010 H]= C0 H
C002 H CALL D000 H
C003 H MOV B,A [[SP] - 2] ← [PC L] => [E009 H] =03 H
C004 H HLT
[SP] ← [SP] - 2 =>E011 H – 2 => [SP] = E009 H

[PC]← addr => [PC]=D000 H

Subroutine Program E009 H

D000 H DCR A. A=00 H E010 H

D001 H RET E011 H 3A
Stack Pointer 4F
Stack
(SP)=E011 H E012 H

[PCL]←[[SP]] => [PC L]=03 Stack Memory

[PCH] ← [[SP]+1] => [PC H]=C0
[SP] ← [SP] + 2 => E011 H
4. Condition addr : [Conditional CALL]

Format: [[SP]- 1]← [PCH]

[[SP] -2] ← [PC L]
[SP] ← [SP] -2
[PC]← addr
Addressing: Immediate addressing
Group: Branching group
Bytes: 3 bytes

Comment:
• CALL instruction is used to call subroutine unconditionally.
• Before the control is transferred to the subroutine, the address of next instruction to be
executed the main program is stored in the stack.
• The contents of SP are decremented by2.
• Then, the program jumps to the subroutine whose starting address is specified in the
instructions.
Opcode Description Flag Status
CNZ addr Call if not zero Z=0
CZ addr Call if zero Z=1
CC addr Call if carry Cy = 1
CNC addr Call if not carry CY=0
СРО addr Call if odd parity P=0
CPE addr Call if even parity P=1
CP addr Call if plus S=0
см addr Call if minus S=1
4. Condition addr :

Main Program :
C000H C001 H MVI A, 01H A=01 H
C002 H CNZ D000 H
C003 H MOV B,A
C004 H HLT

Subroutine Program

D000 H DCR A. A=00 H

D001 H RET
5. RET : [RETURN FROM SUBROUTINE]

Format: [PCL]← [[SP]]

[PCH] ← [[SP]+1]
[SP] ←[SP] + 2
Addressing: Register indirect
Group: Branching group
Bytes: 1 byte

Comment:
• The contents of the memory location, whose address is specified in stack pointer are
moved to the lower-order byte of the program counter.
• The content of the memory location whose address is one more than the content of SP,
moved to the higher order byte of program counter.
• The contents of the stack pointer are incremented by 2.
6. Recondition: [Conditional RETURN]

Format: [PCL]← [[SP]]

[PCH] ← [[SP]+1]
[SP] ←[SP] + 2

Addressing: Register indirect

Group: Branching group
Bytes: 1 byte
Flag: None

Comment:
• If the specified condition is true, the actions specified in RET are performed Otherwise
the control continues sequentially.
Opcode Description Flag Status
RNZ Return on not zero Z=0
RZ Return on zero Z=1
RC Return on carry Cy = 1
RNC Return on carry CY=0
RРО Return on odd parity P=0
RPE Return on odd parity P=1
RP Return on positive S=0
RM Return on minus S=1
6. Recondition:

Main Program :
C000H C001 H MVI A, 01H A=01 H
C002 H CNZ D000 H
C003 H MOV B,A
C004 H HLT

Subroutine Program

D000 H DCR A. A=00 H

D001 H RZ
7. RST n: [RESTART]

Format: [[SP]- 1]← [PCH]

[[SP] -2] ← [PC L]
[SP] ← [SP]- 2
[PC]← 8*(n)

Addressing: Register indirect

Group: Branching group
Bytes: 1 byte
Flag: None

Comment:
• Control is transferred to the instruction whose address is 8 times the content of n.
• These instructions are used with interrupts

• Example : RST 2
n=2 => n*8 => 2*8 => 16 => 0010 H
Opcode Operand Restart addr.

RST 0 0*8=0 =>0000 H

RST 1 1*8=8 =>0008 H
RST 2 2*8=16 =>0010 H
RST 3 3*8=24 =>0018 H
RST 4 4*8=48 =>0020 H
RST 5 5*8=40 =>0028 H
RST 6 6*8=48 =>0030 H
RST 7 7*8=56 =>0038 H
8. PCHL: [LOAD PROGRAM COUNTER WITH HL]
Format: [PCH] ← [H]
[PCL] ← [L]
Addressing: Register indirect
Group: Branching group
Bytes: 1 byte
Flag: None

Comment:
• This instruction moves the content of register H to higher order byte of program counter and
the content of register L to the lower order byte of program counter.
• This instruction is equivalent to a one-byte unconditional jump instruction, whit jump
address. stored in the H-L pair.

Example : Let, [H]= 25 H and [L] = 39 H

Instruction: PCHL
After execution: [PC] = 2539 H
After execution of PCHL instruction, the control will be transferred to memory location 2539 H.
 5. MachineControl Group:
A) Stack operation:

1. PUSH rp: [PUSH REGISTER PAIR ON STACK]

Format: [[SPl-1]] ← [rh]

[[SP] - 2] ← [rl]
[SP] ← [SP] -2
Addressing: Registerindirect addressing
Group: Machine Control Group:
Bytes: 1 byte
Flag: None

Comment:
a) The contents of the higher order register of register pair rp are moved to memory
location, whose address is one less than the content of stack pointer.
b) The contents of the low order register of register pair r p are moved to the location whose
address is two less than the content of stack pointer.
c) The stack pointer is decremented by two. rp may be any one of the B(B &C), DD(&E), H
(H & L).
Example : Let [SP]=D015 H ,[B]=25 H and [C]=55 H
Instruction: PUSH B
After execution: [D014]= 25 H
[D013] = 55 H
and [SP] =D013 H

stack stack
D013 SP D013 55
D014 D014 25
SP D015 02 D015 02
10 D016
10
D016
2. PUSH PSW: [PUSH ACCUMULATOR AND FLAG REGISTER ON STACK]

Format: [[SP] - 1]] ← [A]

[[SP] - 2]0 ← [Cy], [[SP] - 2]1 ← x,
[[SP] - 2]2 ← [P], [[SP] - 2]3 ← x,
[[SP] - 2]4 ← [Ac], [[SP] - 2]5 ← x,
[[SP] - 2]6 ← [Z], [[SP] - 2]7 ←[S],
[SP] ← [SP] - 2 (x – undefined)
Addressing: Register indirect addressing
Bytes: 1 byte
Flag: None

Comment:
a) The contents of accumulator are moved to the memory location, whose address is one
less than the content of stack pointer.
b) The contents of processor status word (flag register) are moved to the memory location,
whose address is two less than the content of stack pointer.
c) The stack pointer is decremented by 2.
 5. Machine Control Group:
Example: Let [A] = 03 H and Flag Register , [SP]= D015 H
Instruction: PUSH PSW
After execution: [D014] = 3 H, [D013] = 25 H
[SPI = D013 H
B7 B6 B5 B4 B3 B2 B1 B0
Flag Register 1 0 x 1 x 0 x 1
S Z AC P CY
SP-2=D015-2
=> D013 1 0 x 1 x 0 x 1
7 6 5 4 3 2 1 0

stack
stack
D013 SP D013 Flag registervalue
D014
D014 03
D015
SP D015 02 02
D016
10 10
D016
3. POP rp : [POP OFF STACK TO REGISTERPAIR]

Format: [rl] ← [[SP]]

[rh] ← [[SP] + 1 ]
[SP] ← [[SP] + 2 ]

Addressing: Register indirect

Bytes: 1 byte
Flag: None

Comment:
a) The contents of the memory location, whose address is specified by the stack pointer are
moved to low order register of register pair rp.
b) The contents of the memory location, whose address is one more than the content of
stack pointer are moved to high order register of register pair rp.
c) The stack pointer is incremented by 2.rp may beany one of the pairs B(B &C), D(D &E)
and H(H &L)
Example: Let [SP] = D013 H
Instruction : POP B
After execution: [B]= 25 H
[C] = 55 H
and [SP] =D015 H

stack stack
SP D013 D013
55
D014 25 D014

D015 02 SP D015 02
10 D016
10
D016
4. POP PSW : [POP OFF STACK TO ACCUMULATOR AND FLAG REGISTER]

Format: [Cy] ← [[SP]] 0

[p] ← [[SP]2, [AC] ← [SP]]4
[Z] ← [[SP]6 , [S] ← [SP]]7
[A] ← [[SP] + 1]
[SP]← [SP] + 2
Addressing: Register indirect
Bytes: 1 byte
Flag: None

Comment:
a) The contents of the memory location, whose address is specified by the content
of register stack pointer are used to restore the condition flags.
b) The contents of memory location, whose address is one more than stack pointer
are moved to accumulator.
c) The contents of stack pointer are incremented by 2.
5. XTH : [EXCHANGE H AND L WITH TOP OF STACK]

Format: [L] ← [SP]

[H] ← [[SP] + 1]

Addressing: Register indirect

Bytes: 1 byte
Flag: None

Comment:
a) The contents of the L register are exchanged with the content of the memory
location, whose address is stored in stack pointer.
b) The contents of the H register are exchanged with the contents of the memory location,
whose address is one more than the contents of the stack pointer.
c) Content of SP are not altered.
Example: Let [H] = 20 H, [L] = FFH, Stack :

AB ← SP

CD

Instruction: XTHL
[H]= CD H and [L]= AB H
FE ← SP

20
6. SPHL: [MOVE HL TO SP]

Format: [ SPL ] ← [L]

[SPH] ← [H]

Addressing: Register
Group: Machine control group [stackoperation]
Bytes: 1 byte
Flag: None

Comment:
a) This instruction copies the content of register L into lower order byte of stack pointer and
the content of register H into higher order byte stack pointer.
b) The contents of register H and L are not affected.
c) This instruction is used for initializing the stack pointer.
Example : Let, [H] = 25 H and [L] = 59 H
Instruction: SPHL
After execution: [SP] = 2559 H
B) Other Instructions: (I/O)

1.IN port: [INPUT 8-BIT DATA FROM AN INPUT PORT TO ACCUMULATOR]

Format: [A] ← data

Addressing: Direct addressing
Group: Machine (I/O) control group
Bytes: 2 bytes.
Flag: No flags are affected.

Comment:
• When this instruction is executed, microprocessor sends 8-bit port address on lower
order address bus ie. A0 to A7.
• Then, the 8-bit data placed on the 8-bit bidirectional data bus by the specified port is
moved to accumulator.
• e.g. IN 10 H. [10 H] = 40 H

• [A] = 40 H
 5. Machine Control Group:
2. OUT port : [OUTPUT 8-BIT DATA FROM ACCUMULATOR TO AN OUTPUT PORT]

Format: [data] ← [A]

Addressing: Direct addressing
Group: Machine (I/O) control group
Bytes: 2 bytes.
Flag: No flags are affected.

Comment:
• When this instruction is executed, microprocessor sends 8-bit port address on the lower
order address bus AD, to AD.
• 8-bit data is then transferred from accumulator to selected port.

Example: Let A= 40 H
OUT 10 H

[10 H] = 40 H

When this instruction is executed, microprocessor sends8-bit data from accumulator to

 5. Machine Control Group:
3. EI : [ENABLE INTERRUPT]

Group: Machine control group

Bytes: 1 bytes.
Flag: None.

Comment:
• EI means Interrupt Enable.
• The interrupt system is enabled following the execution of the instruction next to El and all
interrupts are enabled.
 5. Machine Control Group:
4. DI : [DISABLE INTERRUPT]

Group: Machine control group

Bytes: 1 bytes.
Flag: None.

Comment:
• DI means disable interrupts.
• As soon as DI instruction is executed, the interrupt, system is disabled.
• Interrupts are not recognized during the DI instruction.
 5. Machine Control Group:
5. HLT : [HALT AND ENTER WAIT STATE]

Group: Machine control group

Bytes: 1 bytes.
Flag: None.

Comment:
• When HLT instruction is executed, the processor is stopped.
• The register and flags are unaffected.
• This instruction is used to stop MPU.
• It is waiting for a peripheral device to finish its task and interrupt the processor. This is
generally the last instruction of our assembly language program.
• An interrupt or reset is necessary to exit from Halt state.
 5. Machine Control Group:
6. NOP : [HALT AND ENTER WAIT STATE]

Group: Machine control group

Bytes: 1 bytes.
Flag: None.

Comment:
• When this instruction is executed, no operation is performed, only this instruction is
fetched and decoded.
• This instruction do not affect flags or content of registers.
• This instruction is useful to produce a time delay in a timing loop.
 5. Machine Control Group:
7. RIM : [READ INTERRUPT MASKI]

Group: Machine control group

Bytes: 1 bytes.
Flag: None.

Comment:
• This is a multipurpose instruction used to read the status of interrupts 7.5, 6.5, 5.5 and
read serial data input bit.
• The instruction loads eight bits in the accumulator with the following interpretations:
 5. Machine Control Group:
7. RIM : [READ INTERRUPT MASKI]

Group: Machine control group

Bytes: 1 bytes.
Flag: None.

Comment:
• This is a multipurpose instruction used to read the status of interrupts 7.5, 6.5, 5.5 and
read serial data input bit.
• The instruction loads eight bits in the accumulator with the following interpretations:
 5. Machine Control Group:
7. RIM : [READ INTERRUPT MASKI]
 5. Machine Control Group:

Example: After the execution of instruction RIM, the accumulator contained 49H. Explain
the accumulator contents.
 5. Machine Control Group:
8. SIM : [SETINTERRUPT MASK]

Group: Machine control group

Bytes: 1 bytes.
Flag: None.

Comment:
• This is a multipurpose instruction and used to implement the 8085 interrupts (RST 7.5,
6.5 and 5.5) and serial data output.
• The instruction interrupts the accumulator contents as follows :
 5. Machine Control Group:
8. SIM : [SETINTERRUPT MASK]
 5. Machine Control Group:

• SOD : Serial Output Data: Bit Dr of the accumulator is latched into the SOD output line
and made available to a serial peripheral if bit D6 = 1.

• SOE : SOD Enable : If this bit = 1, it enables the serial output. To implement serial
output, this bit needs to be enabled.

• XXX : Don't Care

• R7.5 : Reset RST 7.5: If this bit =1, RST 7.5 flip-flop is reset. This is an additional control
to reset RST 7.5.

• MSE : Mask Set Enable: If this bit is high, it enables the functions of bits D2 , D1, D0. This
is a master control over all the interrupt masking bits. If this bit is low, bits D2, D1 and D0
do not have any effect on the masks.
 5. Machine Control Group:

• M7.5 : D2 = 0, RST 7.5 is enabled.

= 1, RST 7.5 is masked or disabled.

• M6.5 : D1 = 0, RST 6.5 is enabled.

= 1, RST 6.5 is masked or disabled.

• M5.5 : D0 = 0, RST 5.5 is enabled.

• = 1, RST 5.5 is masked or disabled.