International Journal of Power Electronics and Drive Systems (IJPEDS)

Vol. 15, No. 3, September 2024, pp. 1609~1616

ISSN: 2088-8694, DOI: 10.11591/ijpeds.v15.i3.pp1609-1616  1609

THD analysis of 15-level multilevel inverter using lesser number

of switches with nearest level control technique

Nunsavath Susheela1, Vilasagaram Revanth Chandra2

Department of Electrical Engineering, University College of Engineering, Osmania University, Hyderabad, India

Article Info ABSTRACT

Article history: The multilevel inverters are considered as the efficient power converters.
Because of the predominant properties of multilevel inverters over the two-
Received Nov 16, 2023 level inverters, these are acquiring more popularity. The aim of research is to
Revised Mar 19, 2024 minimize the number of switches as well as sources. In this paper, total
Accepted Mar 28, 2024 harmonic distortion (THD) analysis for different modulation indices is carried
out for a 15-level inverter with fewer switches. This 15-level inverter uses
three asymmetrical sources with nine switching devices. Nearest level control
Keywords: modulation technique provides the pulses for the switching devices at
fundamental switching frequency. Evaluation of THD has been carried out in
Fast fourier transform MATLAB/Simulink.
Modulation index
Multilevel inverter
Nearest level control
Total harmonic distortion This is an open access article under the CC BY-SA license.
Total standing voltage

Corresponding Author:
Nunsavath Susheela
Department of Electrical Engineering, University College of Engineering, Osmania University
Hyderabad-500007, Telangana, India
Email: [email protected]

1. INTRODUCTION
Due to the predominant power quality of the multilevel inverters (MLI) over the conventional two-
level inverter, the multilevel inverter topologies have acquired popularity. The output has only two levels in a
conventional inverter, which has a heavy distortion from the sine wave. Multilevel inverters are used to produce
various levels resulting in the lesser distortion in output that approaches near to sine wave. The applications of
the multilevel inverter can be found where there is a need of medium and high power in the electrical
engineering fields.
There are some complications in the traditional multilevel inverters like balancing the voltage across
the capacitor in flying capacitor type topology, semiconductor switching devices are more in case of neutral
point clamped inverter, more number of sources in cascaded H-bridge (CHB) topology [1], [2]. Researches are
trying to solve the problems related to the multilevel inverters and are publishing huge number of papers in the
past few years. In order to reimburse the downsides of the conventional MLI, new topologies are being
introduced. The main focus of the researches is being on reducing the number of switching components, source
requirement along with the increase in the number of levels in the output. The designing of the multilevel
inverter relays on the number of levels required in the output, number of sources, number of switch
requirement. Different topologies were put forward to prevail over the issues of the conventional multilevel
inverters [3]-[8].
One such topology suggested is 15-level MLI [4]. This suggested topology uses asymmetrical
configuration of the dc voltage sources and it includes features like, using three dc sources, reduction in the
number of switches used, study of the total standing voltage, comparison with the other topologies. The
topologies from previous studies [9], [10] describe the disadvantages of the conventional CHB. The proposed

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1610  ISSN: 2088-8694

topology in study by Samadaei et al. [10] produces 17 levels in the output without H-bridge configuration. It
uses two T-type arrangements connected back to back. In study by Alishah et al. [11] , another topology which
is modified H-bridge has been developed using diodes, capacitors, dc voltage sources. The capacitor gets
charged to the double of the dc voltage supply and thus various multi levels are obtained at the output.
For high power applications, the multilevel inverter modulation techniques used are many modulation
techniques in the literature such as space-vector modulation (SVM), nearest-level control (NLC), sinusoidal
pulse width modulation (SPWM) and selective harmonic elimination-pulse width modulation (SHE-PWM)
[12]-[17]. The modulation technique called nearest level control comes under the fundamental switching
frequency techniques. Nearest level control is also termed as round control method, due to the levels in the
output that are selected based on the rounded control method [18], [19]. For high level inverters the modulation
technique preferred is the nearest level control but it is not suitable for low level inverters. In nearest level
control a stepped waveform is obtained by rounding off a reference sine wave. MLI output is similar to that of
rounded off stepped wave. Gate pulses to the switches are obtained in such a way that the output the inverter
is same as that of the stepped waveform obtained from rounding off.
In this paper, the analysis of the total harmonic distortion (THD) in the output voltage has been carried
out for the topology that has been proposed in previous research [4] with a resistive load of R=100 Ω for
different modulation indices and is discussed in the section 4. Section 2 narrates the topology that has been
used as a multilevel inverter while the section 3 expresses about the modulation technique that has been used.
Section 4 confers about the various results that have been obtained through simulation and section 5
encapsulates the paper.

2. 15-LEVEL INVERTER TOPOLOGY

Three asymmetrical sources and nine switches are used in this topology as seen in Figure 1. The
topology [20] uses 12 switches to produce 15-level output whereas ten switches are used in [21] for
synthesizing the same output. The 11 switches are used in a novel inverter [22]. This topology uses only nine
switches for obtaining 15-levels and hence switches are reduced. One voltage source having a magnitude of
Vx whereas Vy is the magnitude of remaining sources. Out of the nine switches, eight switches are
unidirectional (T1-T8) and one switch is bidirectional (T9).

Figure 1. Fifteen-level multilevel topology

Vy sources including switches T3, T4, T5, T6, and T9 constitutes the inner part of the topology whereas
the outer part comprises of Vx and remaining switches viz. T1, T2, T7 and T8. The complementary switches are
(T1-T2), (T5-T6), and (T7-T8). The magnitudes of the dc voltage sources chosen such that Vx = Vs and Vy = 3Vs,
making the topology an asymmetrical configuration. For the topology that has been taken, it generates 15 levels
in the output voltage. 15-level MLI switching is given in Table 1. The peak output voltage (maximum level)
of the inverter is in (1).

𝑉𝑥 + 2𝑉𝑦 = 7𝑉𝑠 (1)

Total standing voltage in multilevel inverters refers to the cumulative of maximum blocking voltage
across switches. By controlling and managing the levels of standing voltage, engineers can optimize the

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Int J Pow Elec & Dri Syst ISSN: 2088-8694  1611

performance and efficiency of these systems and reduce harmonics in the output. The switches voltage stress
is in (2)-(4).

𝑉𝑇1 , 𝑉𝑇2 , 𝑉𝑇7 , 𝑉𝑇8 = 𝑉𝑥 = 𝑉𝑠 (2)

𝑉𝑇3 , 𝑉𝑇4 , 𝑉𝑇5 , 𝑉𝑇6 , 𝑉𝑇9 = 2𝑉𝑦 = 6𝑉𝑠 (3)

𝑇𝑜𝑡𝑎𝑙 𝑆𝑡𝑎𝑛𝑑𝑖𝑛𝑔 𝑉𝑜𝑙𝑡𝑎𝑔𝑒 (𝑇𝑆𝑉) = 34𝑉𝑠 (4)

Table 1. States for 15-level multilevel inverter

Voltage T1 T2 T3 T4 T5 T6 T7 T8 T9
+7Vs 1 0 0 1 1 0 0 1 0
+6Vs 0 1 0 1 1 0 0 1 0
+5Vs 0 1 0 1 1 0 1 0 0
+4Vs 1 0 0 0 1 0 0 1 1
+3Vs 0 1 0 0 1 0 0 1 1
+2Vs 0 1 0 0 1 0 1 0 1
+1Vs 1 0 1 0 1 0 0 1 0
0 1 0 1 0 1 0 1 0 0
-1Vs 0 1 0 1 0 1 1 0 0
-2Vs 1 0 0 0 0 1 0 1 1
-3Vs 1 0 0 0 0 1 1 0 1
-4Vs 0 1 0 0 0 1 1 0 1
-5Vs 1 0 1 0 0 1 0 1 0
-6Vs 1 0 1 0 0 1 1 0 0
-7Vs 0 1 1 0 0 1 1 0 0

3. MODULATION TECHNIQUE
The modulation methods with high switching frequency and fundamental switching frequency are
discussed in literature [23]-[28]. For attaining high power conversion with lesser system cost, fundamental
switching frequency would rather be used than high switching frequency. NLC is usually employed in MLI
due to easy execution and control. The detailed THD analysis of voltage for a 15-level MLI is carried out at
modulation indices of 0.4, 0.6, 0.7, 0.8, 0.9 and 1.0.
NLC modulation aims to select the nearest to the desired output levels at each instant as shown in
Figure 2. This technique minimizes the switching losses and harmonic content in the output waveform, leading
to improved efficiency and reduced distortion. To achieve the nearest voltage level, control algorithm then
decides the switches of the inverter that needs to be turned on or off. Based on the switching decision, the
control system generates the appropriate switching signals to control the inverter switches. It is commonly used
in various multilevel inverter topologies, to improve their performance and efficiency.

Figure 2. NLC strategy

THD analysis of 15-level multilevel inverter using lesser number of switches … (Nunsavath Susheela)
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4. SIMULATION RESULTS
15-level inverter Simulink model is shown in Figure 3, where Vx = 100 V and Vy = 300 V with R-
load of 100 Ω. Peak value of output voltage is 700 V. By varying the modulation index, the corresponding
outputs are obtained. The 5-levels are attained for a modulation index (ma) of 0.4 as depicted in Figure 4(a)
(see in Appendix). There is an increment of two levels in the output voltage as presented in Figure 4(b) (see in
Appendix). The results for ma of 0.7, 0.8, 0.9 and 1.0 can be seen in Figures 4(c) to 4(f) (see in Appendix).
For the ma = 0.9, output has 13-levels with THD of 6.15% as shown in Figure 5(a). The THD for 15
level output voltage at ma = 1.0 is 5.49 % as depicted in Figure 5(b). 0.66 % THD is decreased for m a = 1.0
when compared to ma = 0.9. Table 2 summerizes the output THD for different ma. The comparison of various
15-level inverters is listed in Table 3 [29], [30].

Figure 3. Simulink model of the 15-level topology

(a) (b)

Figure 5. FFT analysis for output voltage at (a) m a = 0.9 and (b) ma = 1.0

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Int J Pow Elec & Dri Syst ISSN: 2088-8694  1613

Table 2. Output voltage THD for different modulation indices

Modulation index Number of levels in output THD (%)
0.4 5 16.83
0.6 7 12.08
0.7 9 8.89
0.8 11 7.94
0.9 13 6.15
1.0 15 5.49

Table 3. Comparative analysis for different 15-Level inverter topologies

15-level inverters Switch count
Conventional cascaded H-bridge 28
Conventional diode clamped asymmetrical inverter 24
Inverter with reduce switch count [29] 11
Hybrid multilevel inverter [30] 10
Inverter with nearest level control 09

This paper evaluates the effectiveness of the nearest level control strategy by comparing it to
sinusoidal pulse width modulation techniques from existing literature. The analysis reveals that THD of the
output voltage is lower with the nearest level control technique. Table 4 summarizes the comparison of THD
for various modulation techniques.

Table 4. THD in output voltage for 15-level inverter with various modulation methods
THD (%) of output voltage for 15-level inverter
SPWM [31]
PD PWM APOD PWM POD PWM Hybrid PWM Phase shifted PWM Nearest level control technique
8.98 9.03 9.42 9.15 9.14 5.49
Note: Phase disposition (PD), alternative phase opposition disposition (APOD), and phase opposition disposition (POD)

5. CONCLUSION
The THD analysis of a 15-level inverter is carried out for various modulation indices with lesser
switches. It is found that THD in the voltage for 15-levels in the output is around 5.49% at 50Hz frequency. In
case of motor drives, electric vehicles and PV applications, this multilevel inverter has a great significance and
better future scope.

APPENDIX

(a)

Figure 4. Output voltage for 15-level inverter at (a) ma = 0.4

THD analysis of 15-level multilevel inverter using lesser number of switches … (Nunsavath Susheela)
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(b)

(c)

(d)

(e)

Figure 4. Output voltage for 15-level inverter at (b) ma = 0.6, (c) ma = 0.7 (d) ma = 0.8,
(e) ma = 0.9, and (f) ma = 1.0 (continued)

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(f)

Figure 4. Output voltage for 15-level inverter at (f) ma = 1.0 (continued)

REFERENCES
[1] J. Rodriguez, Jih-Sheng Lai, and Fang Zheng Peng, “Multilevel inverters: a survey of topologies, controls, and applications,” IEEE
Transactions on Industrial Electronics, vol. 49, no. 4, pp. 724–738, Aug. 2002, doi: 10.1109/TIE.2002.801052.
[2] N. Prabaharan and K. Palanisamy, “A comprehensive review on reduced switch multilevel inverter topologies, modulation
techniques and applications,” Renewable and Sustainable Energy Reviews, vol. 76, pp. 1248–1282, Sep. 2017, doi:
10.1016/j.rser.2017.03.121.
[3] K. K. Gupta, A. Ranjan, P. Bhatnagar, L. K. Sahu, and S. Jain, “Multilevel Inverter Topologies With Reduced Device Count: A
Review,” IEEE Trans Power Electron, vol. 31, no. 1, pp. 135–151, Jan. 2016, doi: 10.1109/TPEL.2015.2405012.
[4] M. D. Siddique, S. Mekhilef, N. M. Shah, A. Sarwar, A. Iqbal, and M. A. Memon, “A New Multilevel Inverter Topology With
Reduce Switch Count,” IEEE Access, vol. 7, pp. 58584–58594, 2019, doi: 10.1109/ACCESS.2019.2914430.
[5] E. Babaei, “A Cascade Multilevel Converter Topology With Reduced Number of Switches,” IEEE Trans Power Electron, vol. 23,
no. 6, pp. 2657–2664, Nov. 2008, doi: 10.1109/TPEL.2008.2005192.
[6] N. Susheela, “Comparative Analysis of Carrier based techniques for Single phase Diode Clamped MLI and Hybrid inverter with
reduced components,” Indonesian Journal of Electrical Engineering and Computer Science, vol. 7, no. 3, p. 687, Sep. 2017, doi:
10.11591/ijeecs.v7.i3.pp687-697.
[7] R. S. Alishah, S. H. Hosseini, E. Babaei, and M. Sabahi, “A New General Multilevel Converter Topology Based on Cascaded
Connection of Submultilevel Units With Reduced Switching Components, DC Sources, and Blocked Voltage by Switches,” IEEE
Transactions on Industrial Electronics, vol. 63, no. 11, pp. 7157–7164, Nov. 2016, doi: 10.1109/TIE.2016.2592460.
[8] N. Susheela and P. S. Kumar, “Performance Evaluation of Multicarrier Based Techniques for Single Phase Hybrid Multilevel
Inverter using Reduced Switches,” Indonesian Journal of Electrical Engineering and Computer Science, vol. 7, no. 3, p. 676, Sep.
2017, doi: 10.11591/ijeecs.v7.i3.pp676-686.
[9] E. Samadaei, S. A. Gholamian, A. Sheikholeslami, and J. Adabi, “An Envelope Type (E-Type) Module: Asymmetric Multilevel
Inverters With Reduced Components,” IEEE Transactions on Industrial Electronics, vol. 63, no. 11, pp. 7148–7156, Nov. 2016,
doi: 10.1109/TIE.2016.2520913.
[10] E. Samadaei, A. Sheikholeslami, S. A. Gholamian, and J. Adabi, “A Square T-Type (ST-Type) Module for Asymmetrical Multilevel
Inverters,” IEEE Trans Power Electron, vol. 33, no. 2, pp. 987–996, Feb. 2018, doi: 10.1109/TPEL.2017.2675381.
[11] R. Shalchi Alishah, S. H. Hosseini, E. Babaei, M. Sabahi, and A. Zare, “Extended high step‐up structure for multilevel converter,”
IET Power Electronics, vol. 9, no. 9, pp. 1894–1902, Jul. 2016, doi: 10.1049/iet-pel.2015.0893.
[12] N Susheela and P Satish Kumar, “Performance analysis of FPGA based diode clamped multilevel inverter fed induction motor using
phase opposition disposition multicarrier based modulation strategy,” International Journal on Power Electronics and Drive
Systems, vol. 8, no. 4, pp. 1512–1523, Dec. 2017.
[13] R. José, L. Jih-Sheng, and P. Fangzheng, “Multilevel inverters: A survey of topologies, controls, and applications,” IEEE
Transactions on Industrial Electronics, vol. 49, no. 2, pp. 724–738, 2002.
[14] P. Hu and D. Jiang, “A Level-Increased Nearest Level Modulation Method for Modular Multilevel Converters,” IEEE Trans. Power
Electron, vol. 30, no. 4, pp. 1836–1842, Apr. 2015.
[15] Y. Deng and R. G. Harley, “Space-Vector Versus Nearest-Level Pulse Width Modulation for Multilevel Converters,” IEEE Trans
Power Electron, vol. 30, no. 6, pp. 2962–2974, Jun. 2015, doi: 10.1109/TPEL.2014.2331687.
[16] H. Jafari, M. Hassanifar, D. Nazarpour, and S. Golshannavaz, “Design and Analysis of a New Multilevel Inverter with Reduced
Number of Switching Devices,” in 2021 12th Power Electronics, Drive Systems, and Technologies Conference (PEDSTC), IEEE,
Feb. 2021, pp. 1–5. doi: 10.1109/PEDSTC52094.2021.9405914.
[17] Rajkumar Sakile, A Bhanuchandar, and Kasoju Bhash kumar, “A nearest level for reduced switch count cascaded half-bridge based
MLI DC link inverter topology,” in IEEE-SPIN, Int. Conf., 2021.
[18] M. Perez, J. Rodriguez, J. Pontt, and S. Kouro, “Power Distribution in Hybrid Multi-cell Converter with Nearest Level Modulation,”
in 2007 IEEE International Symposium on Industrial Electronics, IEEE, Jun. 2007, pp. 736–741. doi: 10.1109/ISIE.2007.4374688.
[19] I. Colak, E. Kabalci, and R. Bayindir, “Review of multilevel voltage source inverter topologies and control schemes,” Energy
Convers Manag, vol. 52, no. 2, pp. 1114–1128, Feb. 2011, doi: 10.1016/j.enconman.2010.09.006.
[20] S. Thomas and A. Xavier, “Cascaded H-bridge fifteen level inverter,” International Journal of Engineering Research & Technology,
vol. 4, no. 9, 2015.
[21] Y. S. Bhargav, C. Abinay, G. Srinu, and G. Pawan, “15 Level diode clamped multilevel inverter with reduced number of switches,”
International Journal of Research and Analytical Reviews, vol. 6, no. 1, pp. 183–189, 2019.

THD analysis of 15-level multilevel inverter using lesser number of switches … (Nunsavath Susheela)
1616  ISSN: 2088-8694

[22] J. F. Ardashir, B. Rozmeh, M. Gasemi, A. M. Shotorbani, and A. A. Ghavifekr, “A Novel Boost Fifteen-Level Asymmetrical Flying-
Capacitor Inverter with Natural Balancing of Capacitor Voltages,” in 2021 12th Power Electronics, Drive Systems, and
Technologies Conference (PEDSTC), IEEE, Feb. 2021, pp. 1–5. doi: 10.1109/PEDSTC52094.2021.9405887.
[23] S. R. Kunduru, N. K. Reddy Chegireddy, and S. B. Choppavarapu, “Implementation of Nearest Vector Control and Nearest Level
Control for Three Phase, Five Level CHB MLI with WAVECT Controller,” in 2022 International Conference on Recent Trends in
Microelectronics, Automation, Computing and Communications Systems (ICMACC), IEEE, Dec. 2022, pp. 194–199. doi:
10.1109/ICMACC54824.2022.10093596.
[24] K. Sneha and B. M. Das, “A low switching frequency based 17 level multilevel inverter with nearest level control,” in IEEE-PEDES
Int.Conf., 2020.
[25] M. H. Nguyen and S. Kwak, “Nearest-Level Control Method With Improved Output Quality for Modular Multilevel Converters,”
IEEE Access, vol. 8, pp. 110237–110250, 2020, doi: 10.1109/ACCESS.2020.3001587.
[26] N. Susheela and P. S. Kumar, “Performance evaluation and comparison of diode clamped multilevel inverter and hybrid inverter
based on PD and APOD modulation techniques,” International Journal of Advances in Applied Sciences, vol. 8, no. 2, p. 143, Jun.
2019, doi: 10.11591/ijaas.v8.i2.pp143-153.
[27] Z. Sarwer et al., “Implementation of a Novel Variable Structure Nearest Level Modulation on Cascaded H-Bridge Multilevel
Inverter,” IEEE Access, vol. 9, pp. 133974–133988, 2021, doi: 10.1109/ACCESS.2021.3113704.
[28] N. Susheela and P. S. Kumar, “Evaluation of POD and APOD multicarrier SPWM techniques for three-phase seven-level diode
clamped multilevel inverter fed induction motor drive using FPGA,” International Journal of Power Electronics, vol. 12, no. 3, p.
282, 2020, doi: 10.1504/IJPELEC.2020.110063.
[29] M. Fahad, M. D. Siddique, A. Iqbal, A. Sarwar, and S. Mekhilef, “Implementation and Analysis of a 15-Level Inverter Topology
With Reduced Switch Count,” IEEE Access, vol. 9, pp. 40623–40634, 2021, doi: 10.1109/ACCESS.2021.3064982.
[30] A. Azad and J. Kumar, “THD Minimisation in 15- Level Hybrid Multilevel Inverter using Harmonic Minimization Technique,” in
2018 2nd IEEE International Conference on Power Electronics, Intelligent Control and Energy Systems (ICPEICES), IEEE, Oct.
2018, pp. 398–402. doi: 10.1109/ICPEICES.2018.8897311.
[31] M. Q. Abbas, A. Majid, J. Saleem, and M. Arif, “Design and Analysis of 15-level Asymmetric Multilevel Inverter with Reduced
Switch Count using Different PWM Techniques,” in 2017 International Conference on Frontiers of Information Technology (FIT),
IEEE, Dec. 2017, pp. 333–338. doi: 10.1109/FIT.2017.00066.

BIOGRAPHIES OF AUTHORS

Nunsavath Susheela has obtained her B.Tech degree in Electrical and Electronics
Engineering in 2003 from SSJ Engineering College, JNTU and M.E. degree in 2009 in
Electrical Engineering with specialization of Industrial Drives and Control from Osmania
University, Hyderabad. She has obtained her Ph.D. degree in 2018 from Department of
Electrical Engineering, University College of Engineering, Osmania University, Hyderabad in
the area of Multilevel Inverters. She has presented papers in various journals and conferences.
She is working as Associate Professor in Department of Electrical Engineering, University
College of Engineering (Autonomous), Osmania University, Hyderabad, Telangana, India.
She has 16 years of teaching experience. Her research interests include multilevel inverters,
special electrical machines, and power electronics. She can be contacted at email:
[email protected].

Vilasagaram Revanth Chandra has obtained his B.Tech. degree in Electrical

Engineering in 2022 from Rajiv Gandhi University of Knowledge Technologies, Basar,
Telangana, India. He is currently pursuing his PG (M.E) in Industrial Drives and Control
specialization in Department of Electrical Engineering, University College of Engineering
(Autonomous), Osmania University, Hyderabad, India. His areas of interests include
multilevel inverters, power electronics, and renewable energy sources. He can be contacted
at email: [email protected].

Int J Pow Elec & Dri Syst, Vol. 15, No. 3, September 2024: 1609-1616