Chinese Journal of Electronics

Vol.19, No.4, Oct. 2010

Efficient Scheme for Path Recognition from

Integrated Circuit Layout∗
YUAN Zhaohui, SUN Shilei and WANG Gaofeng
(Institute of Microelectronics and Information Technology, Wuhan University, Wuhan 430072, China)

Abstract — An efficient scheme for the centerline-based end up with an X-like shape, to which the partitioning strat-
path recognition from an IC mask layout is presented. Un- egy in Ref.[4] could generate unwanted centerline and width.
like the division-based methods, a tree-traverse-based ap- In this work, a simple yet efficient method for the path
proach is proposed. This new scheme can be realized as a
recognition based on the tree traverse is introduced. Starting
reverse procedure of the layout generation from wire rout-
ing trees. Moreover, this scheme can handle complex all- from the minimal branch of a complex polygon, one will first
angle wires. Experimental results show that this scheme find the centerline and width of this minimal branch within its
has nearly linear computational complexity yet generates area bounded by the polygon border, and then this minimal
precise results. branch is discarded from the polygon and the same procedure
Key words — VLSI, Mask layout, Path recognition, is repeated on the remaining smaller polygon. Contact cuts
or vias (Vertical interconnect access) are utilized to connect
Interconnect extraction.
wires in different layer. Each net composed with poly-silicon
or metal parts and contacts or vias with a polygon-based repre-
I. Introduction sentation is recorded as an element with centerline and width
data. This new path recognition algorithm can successfully
Originally, the path recognition in layout extraction from identify non-Manhattan paths; it is implemented in C++ as
an original mask layout is to find just the connectivity among an integrated component of an IC parasitic extraction pro-
the devices. In recent years, as the operating speed of logic cir- gram, called QXT[5] , for IC parasitic inductance extraction.
cuits increasingly becomes faster, the inductance effect plays
an even more important role in mask layout verification and
must be included in delay estimation, during VLSI verification. II. Theory
To extract the IC parasitic inductances, a full set of geomet- 1. Preliminaries
rical parameters such as centerlines, widths, and heights of IC IC layout is generally described by a GDSII design file,
interconnects must be known before the inductance calcula- in which all geometries are represented by rectangles or poly-
tions can be performed[1,2,5,12] . Accordingly, the goal of the gons. Device recognition algorithms can be applied to extract
path recognition in layout extraction is becoming not only to the devices and the design netlists from the IC layout[6−8] . In
identify the connections of devices, but also to locate the cen- the device recognition, various device models are used. Each
terline and evaluate the width of each wire segment (Note that device model describes one type of device in terms of geomet-
the height of the wire segment can be found from the layer def- ric shapes and their topological relationships. In the present
initions in the technology files). work, the algorithm proposed in Ref.[8] will be utilized to pre-
The path recognition with a capability of identifying cen- process the layout for device and netlist extraction.
terlines and widths is a much more difficult task due to arbi-
trary shapes of the mask layout polygons. Similar works were
resorted to division-based methods[3,4] . Choi et al. used a vi-
sual grid to divide a polygon into rectangles and then extract
wire segments in terms of directions of the rectangles[3] . How-
ever, this method cannot treat non-Manhattan paths since it
used the horizontal and vertical grid lines to divide a polygon,
moreover, it cannot identify the actual location of centerlines.
In Ref.[4], Lakos constructed a non-Manhattan path recogni-
Fig. 1. Polygon, centerline and width
tion algorithm, in which a partitioning strategy is utilized to
decompose a polygon (an intersecting wire) into sub-polygons After all the devices are recognized, the corresponding lay-
(single paths) and then recognize the centerline and width for ers are deleted for the wire extraction in the next step. The
each single path. However, some complex polygons cannot be remaining layout geometries are interconnection materials, in-
decomposed, for instance, the overlap rule for contact cuts may cluding poly-silicon, metals, and contact cuts or vias, all of

∗ Manuscript Received Aug. 2009; Accepted Mar. 2010. This work is supported by the National Natural Science Foundation of China

(No.90307017).
628 Chinese Journal of Electronics 2010

which are represented by coordinates of the intersection points pick up the next minimum length edge in the sorted set, and
of abutting segments on their boundaries, as shown in Fig.1(a). repeat the above processes until a branch is found. The algo-
The goal for the path recognition is to represent each inter- rithm is described in pseudo codes as Subroutine 1 (see Table
connection polygon with a centerline and a width, as shown in 1).
Fig.1(b), which can be used in inductance extraction, or other
efforts in VLSI verification[9−12] . Table 1
2. New path recognition scheme Subroutine 1 Find branch (B, p, i, j)
The polygon-based mask layout, which has been operated Sort each edge in B in terms of the edge length in an increasing
order;
with overlapping and abutting merging, was originally gen-
for each edge si in B do
erated from routing trees. It can be readily shown that the p ← si ;
operation of path recognition with centerline and width from i ← p − 1; j ← p + 1;
the polygon-based layout is, in fact, a reverse process of the Calculate direction di and dj of edge i and j;
mask layout generation from the routing tree. For this rea- if di ≈ dj then
son, instead of adopting a conventional division scheme based break;
on the scan-line algorithms to decompose the polygon into a end if
set of rectangles or single paths, a tree-transverse method is
proposed in this work to carry out the path recognition.
In general, every net from the netlist consists of several
parts such as poly-silicon, metals over various layers, and
contact cuts or vias, each of which is represented as a poly-
gon without overlapping and abutting. In the proposed tree-
transverse scheme, the path recognition is first performed for
each part on a single layer. Then, the path segments over var-
ious layers are connected by checking contact cuts and vias.
Finally, the entire net represented by the centerline and width
Fig. 3. L-shape branch (a) L-shape branch: The lengths of
are recorded into a data structure. edges i and j are not equal; Edges i − 1 and j + 1 run
The proposed path recognition algorithm consists of two in the same direction approximately; (b) This rectan-
phases: Wire recognition phase: Invoke the tree-transverse gle is cut off from the original polygon by inserting a
path recognition algorithm to find a path from each part in a new point on edge j
single layer that is represented by a polygon. Connection
phase: These paths recognized in the first phase are connected
by checking contact cuts or vias. The fake centerlines or widths
generated by the design rules are also identified and deleted in
this phase.
(1) Wire recognition
All polygons are represented by the coordinates of the seg-
Fig. 4. T-shape branch (a) T-shape branch: The lengths of
ment vertices on the boundary, which are sorted in a counter-
edges i and j are approximately equal; Edges i − 1
clockwise or clockwise direction (Fig.1(a)). The identified cen- and j + 1 run in different directions; (b) This rectangle
terline and width are recorded into a data structure. is cut off from the polygon and a new point on the
Given a polygon on a intersection of the extended line of i − 1 and j + 1 and
layer, the first step in the the centerline recognized
wire recognition phase is to Once a branch is found, the midpoint of the start segment
find a branch. Start with p is stored as one of the end points of the centerline. The
sorting the boundary edges length of the start segment p is recorded as the width of the
in terms of the edge lengths. branch. Both the centerline and width are stored into a struc-
After completion of the edge ture (undirected graph), in which the centerline is represented
sorting, pick up the minimal by an edge with vertices being the end points and the width is
Fig. 2. Find a branch from a
length edge p, as shown in polygon denoted as a weight assigned to the edge. Since the number of
Fig.2. the centerlines is not predictable during the recognizing pro-
Consider the two line edges that have a common end point cess, a dynamic list is adopted to manage the vertices in the
with p. Name the edge that has a common end point with graph.
the left end point of p as the left side edge, by convention, ex- There are two adjacent segments that join the end points
pressed as edge i, and the edge that has a common end point of segment edge i and segment edge j: one is expressed as
with the right end point of p as the right side edge, expressed edge i − 1 and another edge j + 1, as shown in Fig.2. The
as edge j. Calculate the slopes (or directions) di and dj of relationship between edge i − 1 and edge j + 1 determines the
edge i and edge j, respectively. If directions di and dj are second end point of the centerline as well as the shape of the
approximately the same (here, “approximately the same” is branch. Although there are essentially infinite types of branch
used because one cannot rely on the corresponding edges of a shapes, it is still able to classify them into two subsets of useful
segment to be exactly parallel or vertical), the starting edge branches using two disjoint criteria: L-shape and T-shape, as
p and edges i, j form a branch of the routing tree. Otherwise, shown in Fig.3 and Fig.4 respectively.
 Efficient Scheme for Path Recognition from Integrated Circuit Layout 629

Table 2 (2) Wire connection

Algorithm 1 Wire recognition (B, C, p)
After all the single-layer polygons that belong to a single
Input B /* the circular linked list, in which nodes are vertices
on the boundary of polygon */ net are recognized over all the layers and represented as a set
C /* the centerline graph */ of wire path segments, the contact cuts and vias will be ex-
1. Find Branch (B, p, i, j); tracted to connect all the wire path segments into a complete
2. if B consists of only 4 vertices then wire path for the net. In the wire connection phase, we need
c1 ← middle(p); c2 ← middle(i − 1); to accomplish two procedures.
C ← C ∪ {c1 , c2 };
Delete B;
One procedure is the vertex correction for the vertices with
Return; the type property “inexact”. During the vertex correction, for
3. if li < lj then /* L-shape */ each “inexact” vertex, the algorithm searches an “exact” ver-
Insert a new point n as the truncated point on edge j tex that has a minimal distance to the “inexact” vertex, and
such that replaces the “inexact” vertex with this “exact” vertex.
j = j  + j  , li = lj 
Another procedure is checking for removing the design rule
B ← B − {p, i, j} + {j  };
4. else if li > lj then /* L-shape */ effect. As shown in Fig.5, for instance, the overlap design
Insert a new point n as the truncated point on edges i rule for the contact cut results in a change in the polygon
such that shape in the metal layer, which is a “geometrical disturbance”
i = i + i , ii = ij  to the original design. This “disturbing” change may gen-
B ← B − {p, i, j} + {i }; erate unwanted centerline segments. Hence, the disturbing
Calculate the centerline {c1 , c2 } from p, i, j; regress checking for undesirable centerline segments has to be
C ← C ∪ {c1 , c2 };
performed in order to rectify some “incorrect” vertices. This
5. if li = lj then /* T-shape */
Calculate the middle point n of two end points of edges i rectification is accomplished by scanning the entire centerline
and j; graph. During the scanning process, all the vertices locating
c1 ← middle(p); C ← C ∪ {c1 , c2 }; in the areas of contact cuts or vias are deleted, and the center-
B ← B − {p, i, j}; lines touching the areas of contact cuts or vias are connected
6. Wire Recognition (B, C, p); with the center points of the respective contact cuts or vias,
End as shown in Fig.5.

By far the most common, the L-shape branch identifies

wires that form L-shape connections although not necessarily
at 90 degrees. If two next boundary edges, i − 1 and j + 1,
have approximately the same direction, and the lengths of the
current edges, edge i and edge j, are not approximately equal,
then the longer edge (i.e., edge j in Fig.3(a)) is truncated into
two shorter edges by inserting a new point n on it. The rule Fig. 5. Rectify the incorrect line. (a) Overlap design rule in-
for this new point n is to make the length of the first sub-edge volved polygon; (b) Centerline found after recognin-
ion phase; (c) After connection phase with incorrect
and the length of the shorter edge is equal. After inserting
checking
such a new point on the longer edge, the midpoint between
the new point and the end point of the shorter edge will be In the wire recognition phase, the computational complex-
calculated and stored as a vertex with a type property “inex- ity of the sorting step is O(k log k), where k is the number
act”. The vertices with the type property “inexact” will be of edges in a polygon. In the connection phase, the compu-
further calibrated in the connection phase. The branch that tational complexity of the graph traverse is also O(k log k).
has been recognized will be removed from the original poly- Hence, the total computational complexity of the proposed
gon after inserting the new point on the longer edge, and a path recognition algorithm is O(nm log m), where n is the
new branch finding and recognition process on the remaining number of the nets, and m is the average number of edges
smaller polygon will be recursively repeated until the entire in a net.
polygon is completely recognized.
The T-shape branch is used when the lengths of the cur- III. Experiment Results
rent edges i and j are approximately equal, as shown in Fig.4.
If there is just one quadrangle remained, the centerline from The wire path recognition scheme is implemented in C++
the start segment is then recognized, wire recognition phase is as a component of a parasitic extraction tool QXT3.0, which is
terminated. Otherwise, the midpoint of the start segment p is developed at Wuhan University. The VLSI inductance extrac-
stored as the first end point of the centerline of this branch, tion is one of the major components of the parasitic extraction
and the midpoint n between two end points of edges i and j is tool QXT3.0. The proposed algorithms have been applied on
recorded as the other end point of the centerline with a type real business applications for a period of days. In all cases, the
property “inexact”. After that, the point n is inserted as a wire paths are correctly recognized.
boundary vertex of the polygon and the current branch is re- Fig.6 depicts an original layout of a circuit, which con-
moved from the polygon. Another branch finding cycle starts sists of 15 nets. After applying the proposed path recognition
on the remaining smaller polygon. scheme to this layout, the total number of edges is found to be
In summary, the wire recognition algorithm can be de- 122. Fig.7 shows the centerlines and the corresponding widths
scribed in pseudo codes as Algorithm 1 (see Table 2). that have been recognized by the proposed path recognition
630 Chinese Journal of Electronics 2010

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files. Fig.8 depicts the ge-
Vol.89, No.4, pp.529–555, 2001.
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proposed path recognition dent inductance and resistance extraction for on-chip intercon-
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YUAN Zhaohui received the B.S.
in the preceding section, the total computational time is found degree in computer science in 2004 from
to be nearly linear to the number of nets due to very small Huazhong Normal University, and the
number of edges in each net, which has been substantiated by Ph.D. degree in computer science in 2009
the experiments. from Wuhan University. Currently he is a
research member at the Next Generation
Networks Research Center, City Univer-
IV. Conclusions sity of Hong Kong. His research interests
A centerline-based path recognition scheme has been in- include VLSI design automation, wireless
sensor networks, real-time and embedded
troduced for path extractions from IC mask layouts. This systems and mobile computing. (Email: [email protected])
proposed path recognition scheme can readily handle all kinds
SUN Shilei received the Ph.D. de-
of complex all-angle polygons from a GDSII file and efficiently gree in computer science from Wuhan Uni-
recognize the current-flow lines from IC mask layouts by virtue versity, Wuhan, China, in 2008. He is
of tree traverses. In the experiments, this new path recogni- currently working with the Institute of
tion scheme achieved 100% correctness and the computational Microelectronics and Information Technol-
complexity is nearly linear to the number of nets. This new ogy, Wuhan University. His research in-
terests include electric design automation
path recognition algorithm provides an effective way to ex-
algorithm and embedded system. (Email:
tract the current-flow paths with both centerlines and widths, [email protected])
which are mandatory geometrical parameters in IC parasitic
inductance calculations. WANG Gaofeng received the
Ph.D. degree in electrical engineering from
the University of Wisconsin, Milwaukee,
References
and the Ph.D. degree in scientific com-
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Krauter, D. Edelstein and P. Restle, “On-chip wiring design CA, in 1993 and 2001, respectively. From
challenges for gigahertz operation”, Proceedings of the IEEE, 2001 to 2003, he was the Chief technology
Vol.89, No.4, pp.529–555, 2001. officer (CTO) with Intpax, Inc., San Jose,
[2] H. Mahawar and V. Sarin, “Parallel algorithms for inductance CA. Since 2004, he has been the CTO with
extraction of VLSI circuits”, Proc. of 20th IEEE International Siargo Ltd., Santa Clara, CA. He is also
Parallel and Distributed Processing Symposium, Rhodes Island, currently a Professor and the Head of CJ Huang Info Tech Re-
Greece, pp.25–29, 2006. search Institute, Wuhan University. He has over 180 publications
[3] Y. Choi, I. Chun and B. Kim, “Rectangle-based hierarchical and is the holder of 11 patents. His research and development inter-
layout extraction algorithm”, Journal of the Korean Physical ests include IC and MEMS design and simulation, computational
Society, Vol.41, No.6, pp.988–992, 2002. electromagnetics, electronic design automation, and wavelet appli-
[4] J. Lakos, “Technology retargeting for IC layout”, Proc. of cations in engineering. He is a senior member of IEEE. (Email:
the 34th Design Automation Conference, Anaheim, California, [email protected])