Shift-add Multiplier Version 3 Shift-add Multiplier Version 3

Start
Start

Product0 = 1 1. Test Product0 = 0

Product0 = 1 1. Test Product0 = 0
Product0 Example: 0010 * 0011:
Product0

Itera Step Multiplicand Product

Multiplicand
-tion
1a. Add multiplicand to the left half of 0 init 0010 0000 0011
32 bits 1a. Add multiplicand to the left half of the product and place the result in
the product and place the result in the left half of the Product register values
the left half of the Product register
1 1a 0010 0010 0011
32-bit ALU 2 0010 0001 0001
2 …
2. Shift the Product register right 1 bit
Shift right Control 2. Shift the Product register right 1 bit
Product
Write test
64 bits
No: < 32 repetitions
32nd repetition?
No: < 32 repetitions
32nd repetition?
Product register is initialized with multiplier on right
Yes: 32 repetitions
Yes: 32 repetitions
No separate multiplier register; multiplier
Done
placed on right side of 64-bit product register
Done Algorithm
Algorithm

Observations on Multiply Motivating Booth’s algorithm

Version 3 • Example 0010 * 0110. Traditional:
0010
x 0110
0000 shift (0 in multiplier)
• 2 steps per bit because multiplier & product combined 0010 add (1 in multiplier)
• What about signed multiplication? 0010 add (1 in multiplier)
– easiest solution is to make both positive and remember whether to 0000 shift (0 in multiplier)
negate product when done, i.e., leave out the sign bit, run for 31 steps, 00001100
then negate if multiplier and multiplicand have opposite signs • Same example. But observe there are two successive 1’s in multiplier
0110 = 22 + 21 = 23 – 21, so can replace successive 1’s by subtract and
• Booth’s Algorithm is an elegant way to multiply signed numbers using then add:
same hardware – it also often quicker… 0010
0110
0000 shift (0 in multiplier)
-0010 sub (first 1 in multiplier)
0000 shift (middle of string of 1’s)
0010 add (previous step had last 1)
00001100
 Booth from Multiply Version 3
Motivating Booth’s Algorithm • Modify Step 1 of the algorithm Multiply Version 3 to consider 2 bits of
the multiplier: the current bit and the bit to the right (i.e., the current bit of
Run direction
the previous step). Instead of two outcomes, now there are four:
middle of run
end of run beginning of run Case Current Bit Bit to the Right Explanation Op
0 1 1 1 1 0 1a 0 0 Middle of run of 0s none
1b 0 1 End of run of 1s add
bit = 2n bit = 2m
1c 1 0 Begins run of 1s sub
• Math idea: string of 1’s …011…10… has
1d 1 1 Middle of run of 1s none
successive 1’s

value the sum 2n + 2n-1 + … + 2m = 2n+1 – 2m • Modify Step 2 of Multiply Version 3 to sign extend when the product is
shifted right (arithmetic right shift, rather than logical right shift) because
• Replace a string of 1s in multiplier with an initial subtract when we first the product is a signed number
see a one and then later add after the last one • Multiply Version 3 and Booth share the same hardware, except Booth
– What if the string of 1’s started from the left of the (2’s complement) number, requires one extra flipflop to remember the bit to the right of the current
e.g., 11110001 – would the formula above have to be modified?! bit in the product register – which is the bit pushed out by the preceding
right shift

Booth Algorithm (2 x 7) Booth Algorithm (2 * -3)

Operation Multiplicand Product next? Operation Multiplicand Product next?

0. initial value 0010 0000 0111 0 10 -> sub P = P - M 0.initial value 0010 0000 1101 0 10 -> sub P = P - M

1c. 0010 1110 0111 0 shift P (sign ext) 1c. 0010 1110 1101 0 shift P (sign ext)

2. 0010 1111 0011 1 11 -> nop 2. 0010 1111 0110 1 01 -> add P = P + M

1d. 0010 1111 0011 1 shift P (sign ext) 1b. 0010 0001 0110 1 shift P (sign ext)

2. 0010 1111 1001 1 11 -> nop 2. 0010 0000 1011 0 10 -> sub P = P - M

1d. 0010 1111 1001 1 shift P (sign ext) 1c. 0010 1110 1011 0 shift P

2. 0010 1111 1100 1 01 -> add P = P + M 2. 0010 1111 0101 1 11 -> nop

1b. 0010 0001 1100 1 shift P (sign ext) 1d. 0010 1111 0101 1 shift P

2. 0010 0000 1110 0 done 2. 0010 1111 1010 1 done

 MIPS Notes
Divide
• MIPS provides two 32-bit registers Hi and Lo to hold a 1001 Quotient
64-bit product Divisor 1000 1001010 Dividend
• mult, multu (unsigned) put the product of two 32-bit –1000
10
register operands into Hi and Lo: overflow is ignored by 101
MIPS but can be detected by programmer by examining 1010
contents of Hi –1000
10 Remainder
• mflo, mfhi moves content of Hi or Lo to a general-
purpose register • Junior school method: see how big a multiple of the divisor can be
• Pseudo-instructions mul (without overflow), mulo (with subtracted, creating quotient digit at each step
• Binary makes it easy ⇒ first, try 1 * divisor; if too big, 0 * divisor
overflow), mulou (unsigned with overflow) take three 32-
• Dividend = (Quotient * Divisor) + Remainder
bit register operands, putting the product of two registers • :
into the third

Divide Version Divide Version

Start

Start

1. Subtract the Divisor register from the

Example: 0111 / 0010:
Remainder register and place the
result in the Remainder register 1. Subtract the Divisor register from the
Remainder register and place the Itera- Step Quotient Divisor Remainder
result in the Remainder register
32-bit divisor starts at left half of divisor register tion
Remainder –> 0 Remainder < 0
0 init 0000 0010 0000 0000 0111
Test Remainder
Divisor Quotient register is Remainder –> 0 Remainder < 0 1 1 0000 0010 0000 1110 0111
Shift right Test Remainder
initialized to be 0 2b 0000 0010 0000 0000 0111
64 bits
3 0000 0001 0000 0000 0111
Quotient
2a. Shift the Quotient register to the left,
setting the new rightmost bit to 1
2b. Restore the original value by adding
the Divisor register to the Remainder
2 1 0000 0001 0000 1111 0111
2a. Shift the Quotient register to the left, 2b. Restore the original value by adding
64-bit ALU Shift left register and place the sum in the setting the new rightmost bit to 1 the Divisor register to the Remainder 2b 0000 0001 0000 0000 0111
32 bits Remainder register. Also shift the register and place the sum in the
Quotient register to the left, setting the Remainder register. Also shift the 3 0000 0000 1000 0000 0111
new least significant bit to 0 Quotient register to the left, setting the
Remainder Control
Write test
new least significant bit to 0 3 1 0000 0000 1000 1111 1111
64 bits 2b 0000 0000 1000 0000 0111
3 0000 0000 0100 0000 0111
3. Shift the Divisor register right 1 bit
Remainder register is initialized with the dividend at right 3. Shift the Divisor register right 1 bit 4 1 0000 0000 0100 0000 0011
2a 0001 0000 0100 0000 0011
Divisor register, remainder register, ALU are No: < 33 repetitions
3 0001 0000 0010 0000 0011
No: < 33 repetitions
33rd repetition? 33rd repetition?
64-bit wide; quotient register is 32-bit wide 5 1 0001 0000 0010 0000 0001
Yes: 33 repetitions Yes: 33 repetitions
2a 0011 0000 0010 0000 0001
3 0011 0000 0001 0000 0001
Done Algorithm Done

Algorithm
 MIPS Notes
Observations
• div (signed), divu (unsigned), with two 32-bit register operands,
divide the contents of the operands and put remainder in Hi register
• Half the bits in divisor always 0
and quotient in Lo; overflow is ignored in both cases
– ⇒ 1/2 of 64-bit adder is wasted
– ⇒ 1/2 of divisor register is wasted
• Intuition: instead of shifting divisor to right, shift remainder to left…

• Step 1 cannot produce a 1 in quotient bit – as all bits corresponding to

the divisor in the remainder register are 0 (remember all operands are
32-bit)
• Intuition: switch order to shift first and then subtract – can save 1
iteration…

IEEE 754 Floating-point Standard

Floating Point
• IEEE 754 floating point standard:
• We need a way to represent
– single precision: one word
– numbers with fractions, e.g., 3.1416
– very small numbers (in absolute value), e.g., .00000000023
31 bits 30 to 23 bits 22 to 0
– very large numbers (in absolute value) , e.g., –3.15576 * 1046
sign 8-bit exponent 23-bit significand
• Representation:
binary point – double precision: two words
– scientific: sign, exponent, significand form:
• (–1)sign * significand * 2exponent . E.g., –101.001101 * 2111001
31 bits 30 to 20 bits 19 to 0
– more bits for significand gives more accuracy
sign 11-bit exponent upper 20 bits of 52-bit significand
– more bits for exponent increases range
bits 31 to 0
– if 1 ≤ significand < 10two(=2ten) then number is normalized, except for
lower 32 bits of 52-bit significand
number 0 which is normalized to significand 0
• E.g., –101.001101 * 2111001 = –1.01001101 * 2111011 (normalized)
 IEEE 754 Floating-point Standard IEEE 754 Floating-point Standard

• Sign bit is 0 for positive numbers, 1 for negative numbers Example : Represent –0.75ten in IEEE 754 single precision
– decimal: –0.75 = –3/4 = –3/22
• Number is assumed normalized and leading 1 bit of significand left of
binary point (for non-zero numbers) is assumed and not shown – binary: –11/100 = –.11 = –1.1 x 2-1
– e.g., significand 1.1001… is represented as 1001…, – IEEE single precision floating point exponent = bias + exponent
– exception is number 0 which is represented as all 0s (see next slide) value
– for other numbers: = 127 + (-1) = 126ten = 01111110two
value = (–1)sign * (1 + significand) * 2exponent value
– IEEE single precision: 10111111010000000000000000000000
exponent significand
• Exponent is biased to make sorting easier sign
– all 0s is smallest exponent, all 1s is largest
– bias of 127 for single precision and 1023 for double precision
equals exponent value
– therefore, for non-0 numbers:
value = (–1) * (1 + significand) * 2(exponent – bias)
sign

Start

Floating Point Addition

Floating Point Addition 1. Compare the exponents of the two numbers.
Shift the smaller number to the right until its
exponent would match the larger exponent Sign Exponent Significand Sign Exponent Significand

• Algorithm: 2. Add the significands

• Hardware: Compare
Small ALU exponents

3. Normalize the sum, either shifting right and

incrementing the exponent or shifting left Exponent
and decrementing the exponent difference

0 1 0 1 0 1

Shift smaller
Overflow or Yes Control Shift right
number right
underflow?

No
Exception Add
Big ALU
4. Round the significand to the appropriate
number of bits
0 1 0 1

Increment or
decrement Shift left or right Normalize
No
Still normalized?

Rounding hardware Round

Yes

Done Sign Exponent Significand

 Start

Floating Point Multiplication

1. Add the biased exponents of the two
numbers, subtracting the bias from the sum
to get the new biased exponent
MIPS Floating Point
• Algorithm: 2. Multiply the significands
• MIPS has a floating point coprocessor (numbered 1, SPIM) with
thirty-two 32-bit registers $f0 - $f31. Two of these are required to
3. Normalize the product if necessary, shifting hold doubles. Floating point instructions must use only even-
it right and incrementing the exponent
numbered registers (including those operating on single floats).
SPIM simulates MIPS floating point.
Overflow or Yes
underflow?
• Floating point arithmetic: add.s (single addition), add.d (double
No
Exception
addition), sub.s, sub.d, mul.s, mul.d, div.s, div.d
4. Round the significand to the appropriate
number of bits
• Floating point comparison: c.x.s (single), c.x.d (double), where x
may be eq, neq, lt, le, gt, ge
No
Still normalized?
• Other instructions…
Yes

5. Set the sign of the product to positive if the

signs of the original operands are the same;
if they differ make the sign negative

Done

Summary
• Computer arithmetic is constrained by limited precision
• Bit patterns have no inherent meaning but standards do exist:
– two’s complement
– IEEE 754 floating point
• Computer instructions determine meaning of the bit patterns.
• Performance and accuracy are important so there are many
complexities in real machines (i.e., algorithms and implementation)

• Read Computer Arithmetic Algorithms by I. Koren

– it is easy-to-read and shows new algorithms for arithmetic
– there will be assignment and projects based on Koren’s material