1.

Software Pipelining
Q: Explain software pipelining and its advantages. How does it compare to loop
unrolling?
Software pipelining is a compiler optimization technique that interleaves instructions from
di8erent iterations of a loop to utilize pipeline stages more e8ectively. By reorganizing loop
instructions, it reduces stalls caused by dependencies or resource unavailability.
Mechanism:
• Fills pipeline slots with instructions from subsequent iterations.
• Handles data hazards dynamically using techniques like forwarding or
introducing delays (bubbles).
Advantages:
1. Reduces pipeline stalls and improves throughput.
2. Consumes less code space compared to loop unrolling.
3. Avoids repeated pipeline start-up and shutdown, ensuring steady
performance.
Comparison with Loop Unrolling:
• Loop unrolling reduces loop overhead but increases code size and register
pressure.
• Software pipelining is more e8icient for embedded systems where memory
and register resources are constrained.
2. Speculative Execution
Q: What is speculative execution, and how does it improve performance?
Speculative execution allows the processor to predict the outcome of a branch and
execute subsequent instructions before the branch’s decision is resolved. If the prediction
is correct, execution continues seamlessly; otherwise, incorrect instructions are
discarded.
Mechanism:
1. Branch Prediction: Guesses whether the branch will be taken or not.
2. Reorder BuIer (ROB): Tracks speculative instructions to ensure they do not
commit until the prediction is verified.
3. If a prediction is incorrect, the ROB flushes invalid instructions, and
execution restarts at the correct branch target.
Advantages:
 1. Increases pipeline e8iciency by reducing control hazards.
2. Keeps functional units busy, even when a branch decision is pending.
3. Ensures precise exceptions, maintaining program correctness.
Key Features:
• Uses functional units that might otherwise be idle.
• Can handle incorrect predictions with minimal performance impact.
3. Dynamic Scheduling
Q: Define dynamic scheduling and explain its advantages.
Dynamic scheduling is a hardware mechanism that decides the order of instruction
execution at runtime based on resource availability and data dependencies. It enables out-
of-order execution to maximize instruction throughput.
Mechanism:
1. Reservation Stations: Temporarily store instructions until operands are
ready.
2. Out-of-Order Execution: Executes instructions as soon as resources and
data are available.
3. Hazard Detection: Identifies and resolves data hazards dynamically.
Advantages:
1. Resolves dependencies without requiring software changes.
2. Reduces stalls caused by data and control hazards.
3. Maximizes processor utilization and performance.
4. Allows code compiled for one pipeline architecture to run e8iciently on
another.
4. Vector Processors
Q: What are vector processors, and why are they eIicient?
Vector processors handle data-level parallelism by executing the same operation on
multiple data elements (vectors) simultaneously. They are well-suited for scientific
computing, simulations, and graphics processing.
Features:
1. Parallel Execution: Processes entire vectors in a single instruction.
 2. Optimized Memory Access: Reduces latency with vector-specific caches
and prefetching.
3. Functional Units: Multiple units operate in parallel to accelerate vector
calculations.
Advantages:
1. High throughput for repetitive operations like matrix multiplication.
2. E8icient use of hardware resources.
3. Compiler optimizations, like loop unrolling and software pipelining, enhance
performance.
5. TRAP Instruction
Q: Explain the TRAP instruction and its purpose.
The TRAP instruction is a machine-level command used to generate a software interrupt,
enabling control transfer to a predefined routine, such as error handling or system calls.
• Mechanism:
1. Saves the current program state, including the Program Counter (PC).
2. Transfers control to a predefined memory location.
3. Executes the interrupt routine and returns control to the program.
• Applications:
• Handling system calls (e.g., file I/O).
• Error and exception management.
• Debugging.
6. MIPS LOAD Opcode
Q: How does the MIPS LOAD opcode improve pipeline performance?
The MIPS LOAD opcode splits the immediate value into upper and lower parts, enabling
parallel decoding and e8icient memory access.
Benefits:
1. Reduced Pipeline Delays: Parallel processing of immediate values reduces
stalls.
2. Flexible Addressing Modes: Supports base + o8set addressing, improving
array access.
3. EIicient Execution: Ensures faster decoding and memory operations.
7. Cache Block Size
Q: What is the eIect of increasing cache block size?
Increasing the cache block size impacts performance by balancing compulsory and
conflict misses.
EIects:
1. Reduces Compulsory Misses: Larger blocks fetch more data, leveraging
spatial locality.
2. Increases Conflict Misses: More addresses map to the same cache set,
increasing contention.
3. Trade-oIs: Larger blocks benefit programs with high spatial locality but
reduce cache flexibility.
8. Multiprocessor Cache
Q: How is cache coherency maintained in multiprocessor systems?
Cache coherency ensures consistent data across multiple processor caches.
Techniques:
1. Write Update Protocol: Updates all copies of data when one processor
writes to it.
2. Write Invalidate Protocol: Invalidates other caches, forcing them to fetch
updated data.
3. Directory-Based Protocol: A central directory tracks and coordinates data
sharing among caches.
Optimizations:
• Direct data sharing between processors reduces delays.
• Maintains system consistency even with multiple processors.
9. Branch Prediction
Q: What is branch prediction, and how does it enhance performance?
Branch prediction guesses the outcome of a branch (e.g., if statements) and fetches
instructions from the predicted path.
Techniques:
1. 1-Bit Predictor: Changes state after one misprediction.
 2. 2-Bit Predictor: Requires two mispredictions to change state, improving
accuracy.
Branch Target BuIers (BTB):
• Store predicted addresses of branches.
• Enable immediate fetching of instructions, reducing pipeline stalls.
10. Butterfly Network
Q: Explain the Butterfly Network and its advantages.
A:
The Butterfly Network is a network topology used in parallel computing for e8icient data
routing. It connects nodes in a structured, layered manner resembling a butterfly.
Advantages:
1. Scalability: Easily supports additional processors.
2. Fault tolerance: Alternate paths ensure data routing even with node failures.
3. Low Latency: Reduces hops, enabling faster communication.