ECEN 687

VLSI Design Automation

Lecture 13 Partitioning

ECEN 687 Lecture 13 1

 Introduction

© KLMH
System Specification

Partitioning
Architectural Design
ENTITY test is
port a: in bit;
end ENTITY test;
Functional Design Chip Planning
and Logic Design

Circuit Design Placement

Physical Design
Clock Tree Synthesis

Physical Verification
DRC and Signoff
LVS Signal Routing
ERC
Fabrication

Timing Closure

Packaging and Testing

Chip

VLSI Physical Design: From Graph Partitioning to Timing Closure Courtesy of I. Markov Chapter 2: Netlist and System Partitioning 2

Lienig
 Introduction

© KLMH
Circuit: 1 Cut cb
3
2
7 8
4
6
5
Cut ca

Block A Block B Block A Block B

8 3 4 1 8 5 4 1

7 6 5 2 7 6 3 2

Cut ca: four external connections Cut cb: two external connections

VLSI Physical Design: From Graph Partitioning to Timing Closure Courtesy of I. Markov Chapter 2: Netlist and System Partitioning 3

Lienig
 Terminology

© KLMH
Block (Partition) Graph G1: Nodes 3, 4, 5.

4 4
1 1
5 6 3 5 6
3
2 2

Cells
Graph G2: Nodes 1, 2, 6.

Collection of cut edges

Cut set: (1,3), (2,3), (5,6),

VLSI Physical Design: From Graph Partitioning to Timing Closure Courtesy of I. Markov Chapter 2: Netlist and System Partitioning 4

Lienig
 Optimization Goals

© KLMH
• Given a graph G(V,E) with |V| nodes and |E| edges where each node v Î V
and each edge e Î E.

• Each node has area s(v) and each edge has cost or weight w(e).

• The objective is to divide the graph G into k disjoint subgraphs such that all
optimization goals are achieved and all original edge relations are respected.

VLSI Physical Design: From Graph Partitioning to Timing Closure Courtesy of I. Markov Chapter 2: Netlist and System Partitioning 5

Lienig
 Kernighan-Lin (KL) Algorithm

© KLMH
Given: A graph with 2n nodes where each node has the same weight.
Goal: A partition (division) of the graph into two disjoint subsets A and B with
minimum cut cost and |A| = |B| = n.

Example: n = 4 1 5

2 6
Block A Block B
3 7

4 8

VLSI Physical Design: From Graph Partitioning to Timing Closure Courtesy of I. Markov Chapter 2: Netlist and System Partitioning 6

Lienig
 Kernighan-Lin (KL) Algorithm – Terminology

© KLMH
Cost D(v) of moving a node v 1 5

D(v) = |Ec(v)| – |Enc(v)| , 2 6

where 3 7
Ec(v) is the set of v’s incident edges that are cut by the Node 3:
cut line, and D(3) = 3-1=2 4 8
Enc(v) is the set of v’s incident edges that are not cut by
the cut line.

Node 7:
High costs (D > 0) indicate that the node
should move, while low costs (D < 0) indicate D(7) = 2-1=1
that the node should stay within the same
partition.

VLSI Physical Design: From Graph Partitioning to Timing Closure Courtesy of I. Markov Chapter 2: Netlist and System Partitioning 7

Lienig
 Kernighan-Lin (KL) Algorithm – Terminology

© KLMH
Gain of swapping a pair of nodes a und b 1 5

Dg = D(a) + D(b) - 2* c(a,b), 2 6

where 3 7
• D(a), D(b) are the respective costs of nodes a, b
• c(a,b) is the connection weight between a and b: 4 8
If an edge exists between a and b,
then c(a,b) = edge weight (here 1),
otherwise, c(a,b) = 0.

The gain Dg indicates how useful the swap between two

nodes will be

The larger Dg, the more the total cut cost will be reduced

VLSI Physical Design: From Graph Partitioning to Timing Closure Courtesy of I. Markov Chapter 2: Netlist and System Partitioning 8

Lienig
 Kernighan-Lin (KL) Algorithm – Terminology

© KLMH
Node 7:
Gain of swapping a pair of nodes a und b D(7) = 2-1=1 1 5

Dg = D(a) + D(b) - 2* c(a,b), 2 6

where 3 7
• D(a), D(b) are the respective costs of nodes a, b Node 3:
• c(a,b) is the connection weight between a and b: D(3) = 3-1=2 4 8
If an edge exists between a and b,
then c(a,b) = edge weight (here 1),
otherwise, c(a,b) = 0.
1 5

Dg (3,7) = D(3) + D(7) - 2* c(a,b) = 2 + 1 – 2 = 1

2 6

=> Swapping nodes 3 and 7 would reduce the cut size by 1

3 7

4 8

VLSI Physical Design: From Graph Partitioning to Timing Closure Courtesy of I. Markov Chapter 2: Netlist and System Partitioning 9

Lienig
 Kernighan-Lin (KL) Algorithm – Terminology

© KLMH
Node 5:
Gain of swapping a pair of nodes a und b D(5) = 2-1=1 1 5

Dg = D(a) + D(b) - 2* c(a,b), 2 6

where 3 7
• D(a), D(b) are the respective costs of nodes a, b Node 3:
• c(a,b) is the connection weight between a and b: D(3) = 3-1=2 4 8
If an edge exists between a and b,
then c(a,b) = edge weight (here 1),
otherwise, c(a,b) = 0.
1 5

Dg (3,5) = D(3) + D(5) - 2* c(a,b) = 2 + 1 – 0 = 3

2 6

=> Swapping nodes 3 and 5 would reduce the cut size by 3

3 7

4 8

VLSI Physical Design: From Graph Partitioning to Timing Closure Courtesy of I. Markov Chapter 2: Netlist and System Partitioning 10

Lienig
 Kernighan-Lin (KL) Algorithm – Terminology

© KLMH
Gain of swapping a pair of nodes a und b

The goal is to find a pair of nodes a and b to exchange such that Dg is

maximized and swap them.

VLSI Physical Design: From Graph Partitioning to Timing Closure Courtesy of I. Markov Chapter 2: Netlist and System Partitioning 11

Lienig
 Kernighan-Lin (KL) Algorithm – Terminology

© KLMH
Maximum positive gain Gm of a pass

The maximum positive gain Gm corresponds to the best prefix of m swaps

within the swap sequence of a given pass.

These m swaps lead to the partition with the minimum cut cost
encountered during the pass.

Gm is computed as the sum of Δg values over the first m swaps of the

pass, with m chosen such that Gm is maximized.

m
Gm = å Dg
i =1
i

VLSI Physical Design: From Graph Partitioning to Timing Closure Courtesy of I. Markov Chapter 2: Netlist and System Partitioning 12

Lienig
 Kernighan-Lin (KL) Algorithm

Kernighan-Lin Algorithm

© KLMH
Step 0:
– V = 2n nodes
– {A, B} is an initial arbitrary partitioning
Step 1:
– i=1
– Compute D(v) for all nodes vÎV
Step 2:
– Choose ai and bi such that Dgi = D(ai) + D(bi) – 2 * c(aibi) is maximized
– Swap and fix ai and bi
Step 3:
– If all nodes are fixed, go to Step 4. Otherwise
– Compute and update D values for all nodes that are connected to ai and bi and are not fixed.
– i=i+1
– Go to Step 2
Step 4:

å
m
– Find the move sequence 1...m (1 £ m £ i), such that Gm =
i =1
Δg i is maximized
– If Gm > 0, go to Step 5. Otherwise, END
Step 5:
– Execute m swaps, reset remaining nodes,
– Go to Step 1

VLSI Physical Design: From Graph Partitioning to Timing Closure Courtesy of I. Markov Chapter 2: Netlist and System Partitioning 13

Lienig
 Kernighan-Lin (KL) Algorithm – Example

© KLMH
1 5

2 6

3 7

4 8

Cut cost: 9
Not fixed:
1,2,3,4,5,6,7,8

VLSI Physical Design: From Graph Partitioning to Timing Closure Courtesy of I. Markov Chapter 2: Netlist and System Partitioning 14

Lienig
 Kernighan-Lin (KL) Algorithm – Example

© KLMH
1 5

2 6

3 7

4 8

Cut cost: 9
Not fixed:
1,2,3,4,5,6,7,8

Costs D(v) of each node:

D(1) = 1 D(5) = 1
D(2) = 1 D(6) = 2 Nodes that lead to
D(3) = 2 D(7) = 1 maximum gain
D(4) = 1 D(8) = 1

VLSI Physical Design: From Graph Partitioning to Timing Closure Courtesy of I. Markov Chapter 2: Netlist and System Partitioning 15

Lienig
 Kernighan-Lin (KL) Algorithm – Example

© KLMH
1 5

2 6

3 7

4 8

Cut cost: 9
Not fixed:
1,2,3,4,5,6,7,8

Costs D(v) of each node:

D(1) = 1 D(5) = 1
D(2) = 1 D(6) = 2 Nodes that lead to
D(3) = 2 D(7) = 1 maximum gain
D(4) = 1 D(8) = 1

Dg1 = 2+1-0 = 3 Gain after node swapping

Swap (3,5)
G1 = Dg1 =3 Gain in the current pass

VLSI Physical Design: From Graph Partitioning to Timing Closure Courtesy of I. Markov Chapter 2: Netlist and System Partitioning 16

Lienig
 Kernighan-Lin (KL) Algorithm – Example

© KLMH
1 5 1 5

2 6 2 6

3 7 3 7

4 8 4 8

Cut cost: 9
Not fixed:
1,2,3,4,5,6,7,8

D(1) = 1 D(5) = 1
D(2) = 1 D(6) = 2 Nodes that lead to
D(3) = 2 D(7) = 1 maximum gain
D(4) = 1 D(8) = 1

Dg1 = 2+1-0 = 3 Gain after node swapping

Swap (3,5)
G1 = Dg1 =3 Gain in the current pass

VLSI Physical Design: From Graph Partitioning to Timing Closure Courtesy of I. Markov Chapter 2: Netlist and System Partitioning 17

Lienig
 Kernighan-Lin (KL) Algorithm – Example

© KLMH
1 5 1 5

2 6 2 6

3 7 3 7

4 8 4 8

Cut cost: 9 Cut cost: 6

Not fixed: Not fixed:
1,2,3,4,5,6,7,8 1,2,4,6,7,8

D(1) = 1 D(5) = 1
D(2) = 1 D(6) = 2
D(3) = 2 D(7) = 1
D(4) = 1 D(8) = 1

Dg1 = 2+1-0 = 3
Swap (3,5)
G1 = Dg1 =3

VLSI Physical Design: From Graph Partitioning to Timing Closure Courtesy of I. Markov Chapter 2: Netlist and System Partitioning 18

Lienig
 Kernighan-Lin (KL) Algorithm – Example

© KLMH
1 5 1 5

2 6 2 6

3 7 3 7

4 8 4 8

Cut cost: 9 Cut cost: 6

Not fixed: Not fixed:
1,2,3,4,5,6,7,8 1,2,4,6,7,8

D(1) = 1 D(5) = 1 D(1) = -1 D(6) = 2

D(2) = 1 D(6) = 2 D(2) = -1 D(7)=-1
D(3) = 2 D(7) = 1 D(4) = 3 D(8)=-1
D(4) = 1 D(8) = 1

Dg1 = 2+1-0 = 3
Swap (3,5)
G1 = Dg1 =3

VLSI Physical Design: From Graph Partitioning to Timing Closure Courtesy of I. Markov Chapter 2: Netlist and System Partitioning 19

Lienig
 Kernighan-Lin (KL) Algorithm – Example

© KLMH
1 5 1 5 1 5

2 6 2 6 2 6

3 7 3 7 3 7

4 8 4 8 4 8

Cut cost: 9 Cut cost: 6

Not fixed: Not fixed:
1,2,3,4,5,6,7,8 1,2,4,6,7,8

D(1) = 1 D(5) = 1 D(1) = -1 D(6) = 2

D(2) = 1 D(6) = 2 D(2) = -1 D(7)=-1 Nodes that lead to
D(3) = 2 D(7) = 1 D(4) = 3 D(8)=-1 maximum gain
D(4) = 1 D(8) = 1

Dg1 = 2+1-0 = 3 Dg2 = 3+2-0 = 5 Gain after node swapping

Swap (3,5) Swap (4,6)
G1 = Dg1 =3 G2 = G1+Dg2 =8 Gain in the current pass

VLSI Physical Design: From Graph Partitioning to Timing Closure Courtesy of I. Markov Chapter 2: Netlist and System Partitioning 20

Lienig
 Kernighan-Lin (KL) Algorithm – Example

© KLMH
1 5 1 5 1 5 1 5

2 6 2 6 2 6 2 6

3 7 3 7 3 7 3 7

4 8 4 8 4 8 4 8

Cut cost: 9 Cut cost: 6 Cut cost: 1 Cut cost: 7

Not fixed: Not fixed: Not fixed: Not fixed:
1,2,3,4,5,6,7,8 1,2,4,6,7,8 1,2,7,8 2,8

D(1) = 1 D(5) = 1 D(1) = -1 D(6) = 2 D(1) = -3 D(7)=-3

D(2) = 1 D(6) = 2 D(2) = -1 D(7)=-1 D(2) = -3 D(8)=-3 Nodes that lead to
D(3) = 2 D(7) = 1 D(4) = 3 D(8)=-1 maximum gain
D(4) = 1 D(8) = 1

Dg1 = 2+1-0 = 3 Dg2 = 3+2-0 = 5 Dg3 = -3-3-0 = -6 Gain after node swapping
Swap (3,5) Swap (4,6) Swap (1,7)
G1 = Dg1 =3 G2 = G1+Dg2 =8 G3= G2 +Dg3 = 2 Gain in the current pass

VLSI Physical Design: From Graph Partitioning to Timing Closure Courtesy of I. Markov Chapter 2: Netlist and System Partitioning 21

Lienig
 Kernighan-Lin (KL) Algorithm – Example

© KLMH
1 5 1 5 1 5 1 5 1 5

2 6 2 6 2 6 2 6 2 6

3 7 3 7 3 7 3 7 3 7

4 8 4 8 4 8 4 8 4 8

Cut cost: 9 Cut cost: 6 Cut cost: 1 Cut cost: 7 Cut cost: 9
Not fixed: Not fixed: Not fixed: Not fixed: Not fixed:
1,2,3,4,5,6,7,8 1,2,4,6,7,8 1,2,7,8 2,8 –

D(1) = 1 D(5) = 1 D(1) = -1 D(6) = 2 D(1) = -3 D(7)=-3 D(2) = -1 D(8)=-1

D(2) = 1 D(6) = 2 D(2) = -1 D(7)=-1 D(2) = -3 D(8)=-3
D(3) = 2 D(7) = 1 D(4) = 3 D(8)=-1
D(4) = 1 D(8) = 1

Dg1 = 2+1-0 = 3 Dg2 = 3+2-0 = 5 Dg3 = -3-3-0 = -6 Dg4 = -1-1-0 = -2

Swap (3,5) Swap (4,6) Swap (1,7) Swap (2,8)
G1 = Dg1 =3 G2 = G1+Dg2 =8 G3= G2 +Dg3 = 2 G4 = G3 +Dg4 = 0

VLSI Physical Design: From Graph Partitioning to Timing Closure Courtesy of I. Markov Chapter 2: Netlist and System Partitioning 22

Lienig
 Kernighan-Lin (KL) Algorithm – Example

© KLMH
D(1) = 1 D(5) = 1 D(1) = -1 D(6) = 2 D(1) = -3 D(7)=-3 D(2) = -1 D(8)=-1
D(2) = 1 D(6) = 2 D(2) = -1 D(7)=-1 D(2) = -3 D(8)=-3
D(3) = 2 D(7) = 1 D(4) = 3 D(8)=-1
D(4) = 1 D(8) = 1

Dg1 = 2+1-0 = 3 Dg2 = 3+2-0 = 5 Dg3 = -3-3-0 = -6 Dg4 = -1-1-0 = -2

Swap (3,5) Swap (4,6) Swap (1,7) Swap (2,8)
G1 = Dg1 =3 G2 = G1+Dg2 =8 G3= G2 +Dg3 = 2 G4 = G3 +Dg4 = 0

Maximum positive gain Gm = 8 with m = 2.

VLSI Physical Design: From Graph Partitioning to Timing Closure Courtesy of I. Markov Chapter 2: Netlist and System Partitioning 23

Lienig
 Kernighan-Lin (KL) Algorithm – Example

© KLMH
D(1) = 1 D(5) = 1 D(1) = -1 D(6) = 2 D(1) = -3 D(7)=-3 D(2) = -1 D(8)=-1
D(2) = 1 D(6) = 2 D(2) = -1 D(7)=-1 D(2) = -3 D(8)=-3
D(3) = 2 D(7) = 1 D(4) = 3 D(8)=-1
D(4) = 1 D(8) = 1

Dg1 = 2+1-0 = 3 Dg2 = 3+2-0 = 5 Dg3 = -3-3-0 = -6 Dg4 = -1-1-0 = -2

Swap (3,5) Swap (4,6) Swap (1,7) Swap (2,8)
G1 = Dg1 =3 G2 = G1+Dg2 =8 G3= G2 +Dg3 = 2 G4 = G3 +Dg4 = 0

Maximum positive gain Gm = 8 with m = 2.

1 5
Since Gm > 0, the first m = 2 swaps
(3,5) and (4,6) are executed.
2 6

3 7
Since Gm > 0, more passes are needed until
Gm £ 0.
4 8

VLSI Physical Design: From Graph Partitioning to Timing Closure Courtesy of I. Markov Chapter 2: Netlist and System Partitioning 24

Lienig
 Clustering

© KLMH
a d d a d

a,b,c

b c e b c,e
e

Initital graph Possible clustering hierarchies of the graph

© 2011 Springer
VLSI Physical Design: From Graph Partitioning to Timing Closure Courtesy of I. Markov Chapter 2: Netlist and System Partitioning 25

Lienig
 Multilevel Partitioning

© KLMH
© 2011 Springer Verlag
VLSI Physical Design: From Graph Partitioning to Timing Closure Courtesy of I. Markov Chapter 2: Netlist and System Partitioning 26

Lienig