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Tanish Pathak - Assignment 02

The document contains VHDL code for various digital circuits, including a bit counter, D flip-flop, ring counter, and Johnson counter. Each section defines the entity and architecture for the respective components, detailing their input and output ports along with the logic for state changes. The code demonstrates the use of libraries and standard logic types to implement sequential logic circuits.

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Tanishpathak
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10 views6 pages

Tanish Pathak - Assignment 02

The document contains VHDL code for various digital circuits, including a bit counter, D flip-flop, ring counter, and Johnson counter. Each section defines the entity and architecture for the respective components, detailing their input and output ports along with the logic for state changes. The code demonstrates the use of libraries and standard logic types to implement sequential logic circuits.

Uploaded by

Tanishpathak
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Name : Tanish Pathak

Batch : P6

Enrollment No:21115147
Assignment -2
1.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bit_counter is
port(C, CLR : in std_logic;
Q : out std_logic_vector(3 downto 0));
end bit_counter;
architecture ans of bit_counter is
signal tmp: std_logic_vector(3 downto 0);
begin
process (C, CLR)
begin
if (CLR='1') then
tmp <= "0000";
elsif (C'event and C='1') then
tmp <= tmp + 1;
end if;
end process;
Q <= tmp;
end ans;
2.
a.)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bit_counter is
port(C, CLR : in std_logic;
Q : out std_logic_vector(3 downto 0));
end bit_counter;
architecture anss of bit_counter is
signal tmp: std_logic_vector(3 downto 0);
begin
process (C, CLR)
begin
if (CLR='1') then
tmp <= "0000";
elsif (C'event and C='1') then
tmp <= tmp + 1;
end if;
end process;
Q <= tmp;
end ans;

b.)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bit_counter is
port(C, CLR : in std_logic;
Q : out std_logic_vector(3 downto 0));
end bit_counter;
architecture sss of bit_counter is
signal tmp: std_logic_vector(3 downto 0);
begin
process (C, CLR)
begin
if (CLR='1') then
tmp <= "0000";
elsif (C'event and C='1') then
tmp <= tmp + 1;
end if;
end process;
Q <= tmp;
end sss;
c.)
library ieee;
use ieee.std_logic_1164.all;
entity d_flipflop is
port(d,clk,reset:in std_logic;q:out std_logic);
end d_flipflop;
architecture sss of d_flipflop is
begin
process(clk,reset)
begin
if(reset='1') then
q<='0';
elsif(clk'event and clk='1') then
q<=d;
end if;
end process;
end sss;
3.
a.
library ieee;
use ieee.std_logic_1164.all;
entity Ring_counter is
Port ( CLOCK : in STD_LOGIC;
RESET : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (3 downto 0));
end Ring_counter;

architecture Behavioral of Ring_counter is


signal q_tmp: std_logic_vector(3 downto 0):= “0000”;
begin
process(CLOCK,RESET)
begin
if RESET = ‘1’ then
q_tmp <= “0001”;
elsif Rising_edge(CLOCK) then
q_tmp(1) <= q_tmp(0);
q_tmp(2) <= q_tmp(1);
q_tmp(3) <= q_tmp(2);
q_tmp(0) <= q_tmp(3);
end if;
end process;
Q <= q_tmp;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Johnson_counter is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (3 downto 0));
end Johnson_counter;

architecture Behavioral of Johnson_counter is


signal temp: std_logic_vector(3 downto 0):= “0000”;
begin
process(clk,rst)
begin
if rst = ‘1’ then
temp <= “0000”;
elsif Rising_edge(clk) then
temp(1) <= temp(0);
temp(2) <= temp(1);
temp(3) <= temp(2);
temp(0) <= not temp(3);
end if;
end process;
Q <= temp;
end Behavioral;

3.b
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Johnson_counter is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (3 downto 0));
end Johnson_counter;

architecture Behavioral of Johnson_counter is


signal temp: std_logic_vector(3 downto 0):= "0000";
begin
process(clk,rst)
begin
if rst = '1' then
temp <= "0000";
elsif Rising_edge(clk) then
temp(1) <= temp(0);
temp(2) <= temp(1);
temp(3) <= temp(2);
temp(0) <= not temp(3);
end if;
end process;
Q <= temp;
end Behavioral;
4.

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