1

GENERAL PURPOSE HARDWARE

From special-purpose FSMD to general-purpose microcontroller:

• RT-level design and FSMD provide a general

methodology to convert a sequential
algorithm to customized hardware
• In an FSMD, all components, including the
number of registers, the routing of registers’
input and output, the number and types of
functional units, and the control FSM, are
tailored to the target application
2
 GENERAL PURPOSE HARDWARE
Alternative: To keep same hardware but use customized software for different applications
Transformation:
•Replace the customized data path with a fixed
configuration
• The data registers and customized routing networks
are replaced by a register file (a fixed number of
registers with two read ports and one write port)
• The customized function units are replaced with an
ALU which can only perform a set of predefined
functions
Format of RT operation performed by data path
rd ← rl op r2
rl, r2, and rd : addresses of two source registers and
one destination register
3
op: one of the available ALU functions

GENERAL PURPOSE HARDWARE

Replace the customized FSM with a programmable state machine (PSM)
Recall: FSM
The state register keeps track of the current state
The output logic activates certain output signals according to current state
The next-state logic determines the new state
• Replace the state register with the program counter: The content of the program
counter represents the current state of the control path
• FSM- each state activates certain output signals to control operation of data
path. PSM encodes output patterns into instructions and stores them in a
memory module, known as instruction memory
• A memory address corresponds to a state (a value) of the program counter
• During execution, the instruction pointed by the program counter is retrieved
from the memory and decoded to generate the control signals
• The instruction memory and decoding logic function as an output logic circuit4
 GENERAL PURPOSE HARDWARE

• In an FSM- no limitation on where to

go next. In PSM, the next state is
usually the value of the current state
plus 1 (PC is incremented by l:
Sequential Execution)
• The sequential execution may be
altered only by several special
instructions in which the PC is loaded
with a different value.
• The incrementor and the associated
multiplexing logic function as a simple
next-state logic circuit 5

GENERAL PURPOSE HARDWARE

• After the replacement, customizing the system corresponds to developing a new

sequence of instructions (develop a software program) and loads the
instructions to the instruction memory
• The organization of the FSMD is now the same for different applications and
becomes a general-purpose hardware platform.
• The platform constitutes the basic skeleton of the PicoBlaze microcontroller
• In a customized FSMD, the data path may contain multiple customized
functional units and parallel routing paths, and can complete complex
computation in a single state (one clock cycle). Whereas, the PicoBlaze can
only perform one predefined RT operation (an instruction) at a time.
• Microcontroller may need many instructions to perform the same task and thus
require much more time 6
 MICROCONTROLLER: PicoBlaze
Application of microcontroller
• Many tasks can be done by either a customized FSMD or a microcontroller.
• The tradeoff is between the hardware complexity, performance and ease of
development.
• Because developing software is usually easier than creating customized hardware,
the microcontroller option is preferable for nontime- critical applications
• PicoBlaze requires two clock cycles to complete an instruction. If the system
clock is 50 MHz, 25 million instructions can be perform in one second
• For a task, examine how frequent a request is issued and how fast the task must
be completed, and then estimate the number of available instructions

MICROCONTROLLER: PicoBlaze

• PicoBlaze processor is a compact 8-bit microcontroller core for Xilinx FPGA

devices
• It is provided as a HDL description (soft core) and can be synthesized along
with other logic
• PicoBlaze is optimized for efficiency and occupies only about 200 logic cells,
which amount to less than 5% resource of a 3S200 device
• it is compact and flexible and can be used for simple data processing and
control, particularly for non-time-critical and I/O operations
• The PicoBlaze processor can be easily integrated into a larger system and adds
another dimension of flexibility in an FPGA-based design

8
 PicoBlaze
Basic Features:
• 8-bit data width
• 8-bit ALU with the carry and zero flags
• 16 8-bit general-purpose registers
• 64-byte data memory
• 18-bit instruction width
• 10-bit instruction address (supports a program up to 1024 instructions)
• 31-word call/return stack
• 256 input ports and 256 output ports
• 2 clock cycles per instruction
• 5 clock cycles for interrupt handling
9

PicoBlaze

Block diagram of PicoBlaze

10
 PicoBlaze
Top-level HDL modules
During synthesis, a PicoBlaze system is organized as two top-level HDL modules.
1. PicoBlaze processor : KCPSM3, constant ( K ) Coded Programmable State Machine
Input and output signals:
• clk (input, 1 bit): system clock signal
• reset (input, 1 bit): reset signal
• address (output, 10 bits): location of instruction to be retrieved
• instruction (input, 18 bits): fetched instruction
• port-id (output, 8 bits): address of the input or output port
• in-port (input, 8 bits): input data from I/O peripherals
• read-storbe (output, 1 bit): strobe associated with the input operation
• out-port (output, 8 bits): output data to I/O peripherals
• write-storbe (output, 1 bit): strobe associated with the output operation
• interrupt (input, 1 bit): interrupt request from I/O peripherals
11
• interrupt-ack (output, 1 bit): interrupt acknowledgement to I/O peripherals

PicoBlaze
2. Instruction ROM : To store the compiled assembly code to memory in
advance and configure it as a ROM in HDL code

Top-level diagram of PicoBlaze

 PicoBlaze
DEVELOPMENT FLOW
• With conventional microcontroller- examine the required functionalities and
select a processor with the proper computation capability and adequate I/O
interface; additional chips are frequently needed to perform special functions
• With soft-core microcontroller- customized circuit and a microcontroller
developed and implemented in the same FPGA device
• With FPGA platform - implement the time-critical tasks in a customized
circuit (“hardware”) for performance and realize the remaining low-speed I/O
functions in a microcontroller (“software”)

PicoBlaze
The basic PicoBlaze-based development flow in steps:
1. Determine the software-hardware partition
2. Develop the assembly program for the software portion
3. Compile the assembly program to generate an instruction ROM (HDL file)
4. Perform instruction-set-level simulation
5. Derive HDL code for the hardware portion (customized circuits for time-
critical functions and to interface with PicoBlaze)
6. Create the top-level HDL code that combines the codes for the PicoBlaze
core, the instruction ROM, and customized hardware
7. Develop a testbench and perform HDL simulation for the entire system.
8. Synthesize and implement the HDL code and program the FPGA chip on
the proto typing board
PicoBlaze
Functional Blocks/Programming model

PicoBlaze

INSTRUCTION SET
PicoBlaze has 57 instructions. According to the nature of operations these
are divided into following categories:
• Logical instructions
• Arithmetic instructions
• Compare and test instructions
• Shift and rotate instructions
• Data movement instructions
• Program flow control instructions
• Interrupt related instructions
 PicoBlaze

Notations for memory components and some constant definitions:

• sX, sY: each representing one of the 16 general-purpose registers, ( X and Y
take on hexadecimal values from 0 to f)
• pc: program counter
• tos: top-of-stack pointer of the call/return stack
• c, z , i: carry, zero, and interrupt flags
• KK: 8-bit constant value or port id, (expressed as two hexadecimal digits)
• SS: 6-bit constant data memory address, (expressed as two hexadecimal digits)
• AAA: 10-bit constant instruction memory address, (expressed as three
hexadecimal digits)

PicoBlaze
Instruction format
PicoBalze’s instructions have five formats:
op sX, sY: register-register format.
SX ←SX op SY
op sX, KK: register-constant format.
SX ← SX op KK
op sX: single-register format.
SX ← op SX
op AAA: single-address format. used in jump and call instructions.
AAA - an address of the instruction memory. If the specified condition
is met, AAA is loaded into the PC
op: zero-operand format. used in some instructions that don’t involve any operand
Two assembler programs for PicoBlaze: KCPSM3 from Xilinx
PBlazeIDE from Mediatronix ( )
 PicoBlaze
Logical instructions
• Six logical instructions, which support the and, or, and xor operations
• Performs bitwise logical operation between two registers or one register and a
constant
• Carry flag c is always cleared; zero flag reflect the result of the operation
and sX, SY or sX, KK
Macro RTL SX ← sX and sY Macro RTL sX ← sX or KK
c←0 c ←0
and sX, KK xor sX, SY
Macro RTL SX ← sX and KK Macro RTL sX ←sX xor sY
c←0 c ←0
or sX, SY xor sX, KK
Macro RTL SX ← sX or sY Macro RTL SX ←sX xor KK
c←0 c ←0

PicoBlaze
Arithmetic instructions
• Eight arithmetic instructions; support addition and subtraction with or without
the carry
• carry flag and the zero flag reflect the result of operation

add sX, SY - add without the carry flag

sX ← sX + sY;
add sX , KK - add without the carry flag
sX ← sX + KK;
addcy s X , SY (addc sX , sY ) - add with carry
sX ← sX + SY + c ;
addcy s X , KK (addc sX , KK)- add with carry
sX ← sX + KK + c;
 PicoBlaze
sub sX, sY -subtract without the carry flag
sX ← sx - sY

sub sX, KK -subtract without the carry flag

sX ← sX - KK

subcy sX, sY (subc sX, sY) - subtract with the carry flag (as a borrow bit)
sX ←sX - sY - c

subcy sX, KK (subc sX, KK) - subtract with the carry flag (as a borrow bit)
sX ← sX - KK - c

PicoBlaze
Compare and test instructions
• Examine two registers or one register and constant, and set the carry and zero
flags accordingly; the contents of the registers remain intact
• The instructions are usually used in conjunction with a conditional jump or call
instruction
compare sX, sY (comp sX, sY)- compare two registers and set the flags
if sX = sY then z ← 1 else z ← 0
if sY > sX then c ← 1 else c ← 0
compare sX, KK (comp sX, KK) - compare a register and a constant and set flags
if sX = KK then z ← 1 else z ← 0
if KK > sX then c ← 1 else c ← 0
A test instruction performs an and operation. If the result is 0, zero flag is set to 1.
The result is also checked for the odd parity. Carry flag is set for odd parity. 22
 PicoBlaze
test sX, sY - test two registers and set the flags
t ← sX and sY
if t =0 then z ← 1 else z ← 0
c ← t(7) xor t(6) xor . . . xor t(0)
test sX, KK - test a register and a constant and set the flags
t ← sX and KK
if t = 0 then z ← 1 else z ← 0
c ← t(7) xor t(6) xor . . . xor t(0)

Shift and rotate instructions

•Four shift-left, four shift-right, and two rotate instructions
•Use the single-register format and have only one operand
23

PicoBlaze
sl0 sX - shift a register left 1 bit and shift 0 into the LSB
sX ← sX (6 . . 0) & 0
c ← sX(7)
sl1 sX - shift a register left 1 bit and shift 1 into the LSB
sX ← sX (6 . . 0) & 1
c ← sX(7)
slx sX - shift a register left 1 bit and shift sX(0) into LSB
sX ← sX (6 . . 0) & sX(0)
c←sX(7)
sla sX - shift a register left 1 bit and shift c into the LSB
sX ← sX(6 . . 0) & c
c ← sX(7)
rl sX - rotate a register left 1 bit
sX ← sX(6..0) & sX(7)
24
c← sX(7)
 PicoBlaze
sr0 sX - shift a register right 1 bit and shift 0 into the MSB
sX ← 0 & sX(7..1)
c ← sX(0)
srl sX - shift a register right 1 bit and shift 1 into the MSB
sX ← 1 & sX(7..1)
c ← sX(0)
srx sX - shift a register right 1 bit and shift sX(7) into MSB
sX ← sX(7) & SX(7.. 1)
c ← sX(0)
sra sX - shift a register right 1 bit and shift c into the MSB
sX ← c & sX(7..1);
c ← sX(0)
rr sX - rotate a register right 1 bit
sX ← sX(0) & sX(7..1)
c ← sX(0)

PicoBlaze
Data movement instructions
• The computation is done via the registers and ALU. The data RAM supplies
additional storage and the I/O ports provide paths to peripherals
• Several instructions to move data between registers, data RAM, and I/O ports.
• Between registers: the load instruction
• Between a register and data RAM: the fetch and store instruction
• Between a register and an I/O port: the input and output instruction

load sX, sY - move data between two registers

sX ← sY
load sX, KK - move a constant to a register
sX ← KK

26
 PicoBlaze
fetch sX, (sY) (fetch sX, sY) - move data from the data RAM to a register
sX ← RAM [(sY)]

fetch sX, SS - move data from the data RAM to a register

sX ← RAM [SS]

store sX, (sY) (store sX , sY) - move data from a register to the data RAM
RAM [(sY)] ← sX

store sX, SS - move data from a register to the data RAM

RAM [SS] ← sX

input sX, (sY) (in sX, sY) - move data from the input port to a register
port_ id ← sY
sX ← in_port 27

PicoBlaze
input sX, KK (in sX, KK) - move data from the input port to a register
port_ id ← KK
sX ←in_port

output sX, (sY) (out sx, sY) - move data from a register to the output port
port_ id ← sY
out_port ← sX

output sX, KK (out sX, KK) - move data from a register to the output port
port_id ← KK
out_ port ← sX
• No explicit instruction to move data to or from the instruction memory
• Many instructions include a field for an immediate constant, it can be considered
as data that is implicitly moved from the instruction memory to a register
28
 PicoBlaze
Program flow control instructions
• The PC indicates where to fetch the instruction. By default, execution proceeds
to the next address the PC is implicitly incremented (pc ← pc+1)
• jump, call and return instructions can explicitly load a value to the PC and
modify the program flow
• These instructions can be executed unconditionally or conditionally based on the
values of the carry and zero flags
• A jump instruction loads new value to PC if the corresponding condition is met,
program execution changes the regular flow and branches to the new address

jump AAA - unconditionally jump

pc ← AAA
29

PicoBlaze
jump c, AAA -jump if the carry flag is set
if c = l
then pc ← AAA
else pc ← pc + 1
jump nc, AAA -jump if the carry flag is not set
if c=0
then pc ← AAA
else pc ← pc + 1
jumpz, AAA - jump if the zero flag is set
if z=1
then pc ← AAA
else pc ← pc + 1
jump nz, AAA - jump if the zero flag is not set
if z=0
then pc ← AAA
30
else pc ← pc + 1
 PicoBlaze
• The call and return instructions are
used to implement a software
function
• PicoBlaze allows nested function calls
(a function can be called within
another function)
• A stack, which is a last-in-first-out
buffer, is used to store the PC’s
values

Representative flow of a subroutine call

PicoBlaze
call AAA - unconditionally call subroutine
tos ← tos + 1
STACK[tos] ← pc
pc ← AAA
call c, AAA - call subroutine if the carry flag is set
if c = l
then tos ← tos + 1
STACK[tosl ← pc
pc ← AAA
else pc ← pc + 1
call nc, AAA - call subroutine if the carry flag is not set
if c=0
then tos ← tos+ 1
STACK[tos] ← pc
pc ← AAA
else pc ← pc + 1
 PicoBlaze
call z, AAA - call subroutine if the zero flag is set
if z = 1
then tos ← tos + 1
STACK[tos] ← pc
pc ← AAA
else pc ← pc + 1
call nz, AAA - call subroutine if the zero flag is not set
if z=0
then tos ← tos + 1
STACK[tos] ← pc
pc ← AAA
else pc ← pc + 1
return (ret) - unconditionally return
pc ← STACK[tos] + 1
tos ← tos - 1

PicoBlaze
return c (ret c) - return if the carry flag is set
if c = l
then pc ← STACK[tos] + 1
tos ← tos - 1
else pc ← pc + 1

return nc (ret nc) - return if the cany flag is not set

if c=0
then pc ← STACK[tos] + 1;
tos ← tos - 1
else pc ← pc + 1

return z (ret z) - return if the zero flag is set

return nz (ret nz) - return if the zero flag is not set

 PicoBlaze
Interrupt related instructions
• Interrupt alters program execution
• Initiated from an external request
• When the interrupt is enabled and the interrupt request is asserted, PicoBlaze
completes execution of the current instruction, saves the address of the next
instruction in the stack, preserves the flags, disables the interrupt, and loads the
PC with 3FF, which is the starting address of the interrupt service routine
• PicoBlaze has two return-from-interrupt instructions, which resume the
operation from the interrupted location
• It also has two instructions that enable and disable the interrupt request by
setting or clearing the interrupt flag i

PicoBlaze
returni disable (reti disable)
- return from interrupt service routine and keep the interrupt flag disabled
pc ← STACKC[tos]
tos ← tos - 1
i←0
c ← preserved c
z ← preserved z
returni enable (reti enable)
- return from interrupt service routine and keep the interrupt flag enabled

enable interrupt (eint) - enable interrupt request

i←1
disable interrupt (dint) - disable interrupt request
i←0
36
 PicoBlaze

37

PicoBlaze

38
PicoBlaze ASSEMBLY CODE DEVELOPMENT
PicoBlaze cannot effectively support high-level programming languages and the
code is generally developed in assembly language.
Review of code development:
• segments of frequently used data and control operations
• use of a subroutine and the derivation of overall program structure
Bit manipulation
Masking a bit
Example-
code segment to set, clear, and toggle the second LSB of the S0 register:
constant SET-MASK , 02 ; mask = 0000-0010
constant CLR-MASK , FD ; mask = 1111-1101
or S0, SET-MASK ; set 2nd LSB to 1
and S0, CLR-MASK ; clear 2nd LSB to 0 39

PicoBlaze ASSEMBLY CODE DEVELOPMENT

Example: Application of mask to the test instruction to check a single bit

test S0, 80 ; mask=1000-0000

jump nz, msb-set ; MSB is 1 , branch to msb-set
; code for MSB not set
jump done
; code for MSB set
msb-set :
...
done :
...

40
 PicoBlaze ASSEMBLY CODE DEVELOPMENT
Multiple-byte manipulation
•A microcontroller sometimes needs to handle wide, multiple-byte data,
such as a large counter
•Since the data width of PicoBlaze is 8 bits, processing this type of data
requires a mechanism to propagate information between two successive
instructions; PicoBlaze uses the carry flag for this purpose
•For the arithmetic instructions, there are two versions for addition and
subtraction, add and addcy instructions
•For the shift and rotate instructions, carry can be shifted into the MSB or
LSB of a register, and vice versa

41

PicoBlaze ASSEMBLY CODE DEVELOPMENT

Example: Assume that x and y are 24-bit data and each occupies three registers
namereg S0, x0 ; least significant byte of x
namereg sl, xl ; middle byte of x
namereg s2, x2 ; most significant byte of x
namereg s3, yo ; least significant byte of y
namereg s 4 , yl ; middle byte of y
namereg s5, y2 ; most significant byte of y
; a d d : { x2 , x1 , x0 } + { y2 , y1 , y0 }
add x0, yo ; add 1east significant bytes
addcy xl, yl ;add middle bytes with carry
addcy x2, y2 ;add most significant byte swith carry
42
 PicoBlaze ASSEMBLY CODE DEVELOPMENT
Control Structure
Examples to illustrate the if-then-else, case, and for-loop statements
if-then-else statement:
if (s0==sl) { / * then - branch statements * /
}
else { / * else - branch statements * /
}
Corresponding assembly code segment:
compare s0, s1 ; to set the zero flag
jump nz , else-branch
jump if-done ; code for then branch

else-branch : ; code for else branch

i f-done : ; code following if statement
... 43

PicoBlaze ASSEMBLY CODE DEVELOPMENT

case statement: a multi-way jump
constant value l, . . .
constant value 2, . . .
switch (S0) { constant value 3, . . .
case value l : compare S0, value l ; test value 1
/ * case value l statements* / jump nz , case-2 ; not equal to value l, jump
break ; ; code for case-1
case value 2 : jump case-done
/ * case value 2 statements * / case-2 : compare S0, value 2 ; test value 2
break ; jump nz , case-3 ; not equal to value 2, jump
case value 3 : ; code for cas- 2
/ * case value 3 statements * / jump case-done
break : case-3 : compare S0, value 3 ; test value 3
default : jump nz, default ; not equal to value 3, jump
/ * default statements * / ; code for case-3
} jump case-done
default : ; code for default case
44
case-done : ; code following case statement
 PicoBlaze ASSEMBLY CODE DEVELOPMENT
for-loop statement
Loop statement can be implemented by using a counter

for(i=MAX, i = 0 , i-1)
{
/*loop body statements*/ namereg S0, i ; loop index
} constant MAX, . . . ; loop boundary
load i, MAX ; load loop index
loop-body :
; code for loop body

sub i, 01 ; dec loop index

jump nz , loop-body ; done ?
; code following for loop
45

PicoBlaze ASSEMBLY CODE DEVELOPMENT

SUBROUTINE DEVELOPMENT
• A subroutine, such as a function in C, implements a section of a larger
program; is coded to perform a specific task and can be used repetitively
• PicoBlaze uses the call and return instructions to implement the subroutine
• call instruction saves the current content of PC and transfers the program
execution to the starting address of a subroutine; a return instruction restores
the saved PC and resumes the previous execution
• PicoBlaze only saves and restores the content of the PC during a function call
and return. We have to manage the register and data RAM use manually to
ensure that the original system state is not altered after a subroutine call

46
 PicoBlaze ASSEMBLY CODE DEVELOPMENT
Example:
Multiplication - the inputs are two 8-bit numbers in unsigned integer format and
the output is a 16-bit product.
Algorithm - simple shift-and-add method
• It iterates through 8 bits of multiplier; in each iteration, the multiplicand is
shifted left one position. If the corresponding multiplier bit is ' l ' , the shifted
multiplicand is added to the partial product.
• The multiplicand and multiplier are stored in the s3 and s4 registers. The
individual bit of multiplier is obtained by repetitively shifting s4 to the right,
which moves the LSB to the carry flag
• Instead of actually shifting the multiplicand to the left, we shift the partial
product (of 2 bytes stored in s5 and s6) to the right
47

PicoBlaze ASSEMBLY CODE DEVELOPMENT

Software integer multiplication

48
 PicoBlaze ASSEMBLY CODE DEVELOPMENT
PROGRAM DEVELOPMENT
1.Derive the pseudo code of the main program
2.Identify tasks in the main program and define them as subroutines.
If needed, continue refining the complex subroutines and divide
them into smaller routines
3.Determine the register and data RAM use
4.Derive assembly code for the subroutines
Step 3 is unique for assembly code development

49

PicoBlaze ASSEMBLY CODE DEVELOPMENT

A microcontroller based application is normally for a simple
embedded system, in which the processor monitors the I/O activities
continuously and responds accordingly. Its main program usually has
the following structure:

call initilaization-routine
forever :
call taskl-routine
call task2-rout ine
...
call taskn-rout ine
jump forever
50
 PICOBLAZE I/O INTERFACE
• Unlike a regular microcontroller, PicoBlaze has no built-in I/O peripherals
• It provides a simple generic input and output structure for an I/O interface
• I/O peripherals are customized to each application
• PicoBlaze uses the input and output instructions to transfer data between its
internal registers and I/O ports
Interface Signals:
port-id: an 8-bit signal, specifies the port address of an input or output instruction
in-port: an 8-bit signal where PicoBlaze obtains input data for an input instruction
out-port: an 8-bit signal where PicoBlaze places output data for an o/p instruction
read_strobe : a 1-bit signal, asserted in second clock cycle of an input instruction
write_strobe: a 1-bit signal, asserted in second clock cycle of an output instruction
51

PICOBLAZE I/O INTERFACE

Output instruction and timing
output instruction writes data to the output port:
output sX, (sY)
output sX , port-name

•PicoBlaze instruction takes two clock cycles Timing diagram of output s0, 02
•On execution of the instruction,
• content of S0 is placed on out-port and 02 is placed on port-id for two
clock cycles
• write-strobe signal is asserted in the second clock cycle; can be used as an
enable tick to store data in an output register 52
 PICOBLAZE I/O INTERFACE
Output interface
• It usually consists of a
decoding circuit and
necessary output buffers
• Decoding circuit decodes
the port_id and generates an
enable tick accordingly
• After the output instruction,
the data will be stored in the
designated buffer

Output decoding of four output registers

53

PICOBLAZE I/O INTERFACE

• In the second clock cycle of an output
instruction, write-strobe is asserted
and 1 bit of the 4-bit en-d signal is
asserted accordingly
• one-clock-cycle enable tick activates
the corresponding output register to
retrieve data from the out-port signal
• During the second clock cycle, the en-
d(2) signal is asserted and the data
value on out-port is stored in the
corresponding buffer at the rising
edge of the next clock 54
 PICOBLAZE I/O INTERFACE
process (write-strobe , port-id)
begin
if write-strobe= ' 0 ' then
en-d <= "0000";
else
case port-id(1 downto 0 ) is
when “00” =>
en_d <= “0001" ;
when “01” =>
HDL codes of decoder’s basic operation en_d <= "0010";
when “10”= >
en_d <= “0100” ;
when others = >
en_d <= “1000” ;
end case ;
end if ;
55
end process ;

PICOBLAZE I/O INTERFACE

Input instruction and timing
input instruction reads data from the input port
input sX, (sY)
input sX, port-name

Timing diagram of input S0, 02

• When the instruction is executed, 02 is placed on port-id

• After two clock cycles, in-port will be sampled at the rising edge of the clock
56
and its value is stored in the S0 register
 PICOBLAZE I/O INTERFACE
Input interface
• It usually consists of a multiplexing circuit, which uses port-id as the selection
signal to route the desired value to in-port.
• Sometimes, a decoding circuit similar to the one in the output interface is also
necessary to signal the completion of the data access.

For the input interface design:

Continuous Access port : data is presented continuously
Single-Access port: availability of data of a single-access port is triggered by a
single discrete event

57

PICOBLAZE I/O INTERFACE

The interface for continuous-access ports involves only a multiplexing circuit

Block diagram of four continuous-access ports

58
 PICOBLAZE I/O INTERFACE
• Interface for single-
access ports needs a
decoding circuit to
remove the retrieved data
from the buffer in the
end of an input
instruction
• The decoding circuit
decodes the port-id and
read-strobe signals and
output a “removal”
signal, which is asserted
for one clock cycle and
removes the previously
Block diagram of four single-access ports
retrieved data 59

PICOBLAZE I/O INTERFACE

HDL Implementation:

-- rnultiplexing circuit case port-id(1 downto 0 ) is

with port-id(l downto 0) select when “00” = >
data <= in-data0 when “00”, rv <= " 0001”;
in-data1 when “01”, when "01" =>
in-data2 when “10”, rv <= "0010";
in-data3 when others; when " 10 " =>
-- decoding circuit rv <= "0100";
process (reade-strobe, port-id) when others =>
begin rv <= "1000";
if read-strobe=‘0’ then end case ;
rv <= " 0000”; end if ;
else end process ; 60
 PICOBLAZE INTERRUPT INTERFACE
Interrupt:
• a mechanism that allows an external I/O peripheral to initiate the operation
• interrupts normal program execution and starts a service routine for I/O
peripheral
• interrupt is usually reserved for a time-critical peripheral operation, which
must be processed immediately
• PicoBlaze microcontroller support for simple interrupt-handling capability
• Interrupt handling is a coordinated effort between hardware and software
interrupt-handling in PicoBlaze:
• When an external peripheral needs service through interrupt, it asserts the
interrupt signal of PicoBlaze
• If interrupt is enabled, PicoBlaze completes execution of the current
instruction, activates the interrupt-ack to acknowledge the acceptance of
the interrupt request, and then implicitly executes the call 3FF instruction

PICOBLAZE
INTERRUPT INTERFACE
Assume : the interrupt signal is asserted in the
middle of the add s0, s3 instruction
PicoBlaze performs following steps
1. Completes execution of current instruction
2. Saves content of PC, clears the interrupt
flag, i, to zero, preserves the zero and carry
flags, and loads the PC with 3FF
3. Executes the jump isr instruction in the
3FF address
4. Performs the service routine
5. Executes the returni instruction, in which
the saved PC and flags are restored
6. Resumes the interrupted program and
executes the sub s5, 01 instruction
Interrupted flow
 PICOBLAZE INTERRUPT INTERFACE

Timing diagram of an interrupt event

PICOBLAZE INTERRUPT INTERFACE

Timing
• At tl: The external interrupt interface asserts the interrupt signal. PicoBlaze
continues the normal operation to complete execution of the current add
s0,s3 instruction
• At t2 : PicoBlaze recognizes the interrupt and aborts the next instruction (sub
s5,01) and implicitly executes the call 3FF instruction
• At t3: PicoBlaze asserts interrupt-ack signal. It also saves the address of sub
s5,01 instruction, preserves zero and carry flags, and clears interrupt flag to 0
• At t4: PicoBlaze loads and executes the instruction in address 3FF, jump isr ;
the external interrupt interface acknowledges interrupt-ack and deasserts
interrupt
• At t5: PicoBlaze starts the interrupt service routine
It requires up to five clock cycles from the time that the interrupt signal is
asserted to the time that the first instruction of interrupt service routine is
executed
 PICOBLAZE INTERRUPT INTERFACE
EXTERNAL INTERFACE
The nature of the interrupt request is similar to that of a single-access port.
After the request is accepted, it must be cleared so that the same request will
not be processed multiple times. A flag FF can be used for this purpose

Single interrupt request

• When the service is required, the external I/O circuit asserted the int
request signal for one clock cycle, which sets the flag FF to '1' and activates
the interrupt input of PicoBlaze.
• If the interrupt is enabled in PicoBlaze, it acknowledges acceptance of the
request by asserting the interrupt-ack signal for one clock cycle, which
clears the flag FF to '0'

PICOBLAZE INTERRUPT INTERFACE

Interrupt interface with a single request

 PICOBLAZE INTERRUPT INTERFACE
Multiple interrupt requests
• Processing a PicoBlaze system with two or more interrupt requests is more
involved
• PicoBlaze microcontroller must determine which peripheral issues the
request and clear the corresponding flag FF after the request is accepted
• This needs the coordination of the hardware interface and the interrupt
service routine
• The interrupt service routine must first input the two request signals and
check their values according to the assigned priority, and then perform the
corresponding service
• In addition, PicoBlaze also needs to clear the corresponding flag FF
• a special output decoding circuit is used to generate a clear tick, clr signal of
each flag FF is assigned to a unique port id

PICOBLAZE INTERRUPT INTERFACE

• In the interrupt service routine, an output instruction is added after

determining which interrupt request is accepted.

Interrupt interface with two requests

 PICOBLAZE INTERRUPT INTERFACE
Development of an interrupt service routine
• The interrupt service routine suspends normal program execution,
performs an independent task, and then resumes the previous execution.
• Unlike a subroutine call, an interrupt can occur any time.
• To resume execution later, the service routine must save the current state
(context) of the PicoBlaze processor
• Context switching: the service routine must save all registers used in
service routine computation and then restore them before returning to
normal execution.
• PicoBlaze is a compact 8-bit microcontroller, the hardware support for
context switching and scheduling is very limited, several dedicated registers
can be allocated to use exclusively in the interrupt service routine

PICOBLAZE INTERRUPT INTERFACE

Assignment: The block diagram of a four-request interrupt controller is shown in
the figure. Derive HDL code for the interrupt controller.
Description: The interrupt controller should contain four flag FFs and a special
priority encoding circuit. If one or more interrupt requests are activated, the
controller determines which request has the highest priority, places its 2-bit code on
the req-id port, and asserts the int signal. When PicoBlaze asserts the interrupt-ack
signal, the controller clears the corresponding flag. The int request-3 has the highest
priority and int request -0 has the lowest priority.