DEPARTMENT OF

ENGINEERING
SCIENCES 1
(AIDS, AIML, CC)
Vision of the Institute

To foster and permeate higher and quality education with value added engineering, technology programs, providing all facilities in terms of
technology and platforms for all round development with societal awareness and nurture the youth with international competencies and
exemplary level of employability even under highly competitive environment so that they are innovative, adaptable and capable of handling
problems faced by our country and world at large.

RAIT’s firm belief in a new form of engineering education that lays equal stress on academics and leadership building extracurricular skills
has been a major contribution to the success of RAIT as one of the most reputed institutions of higher learning. The challenges faced by our
country and the world in the 21st century needs a whole new range of thoughts and action leaders, which a conventional educational system
in engineering disciplines are ill equipped to produce. Our reputation in providing good engineering education with additional life skills
ensures that high grade and highly motivated students join us. Our laboratories and practical sessions reflect the latest that is being followed
in the industry. The project works and summer internships make our students adept at handling the real-life problems and be industry ready.
Our students are well placed in the industry and their performance make reputed companies visit us with renewed demands and vigour.

Mission of the Institute

The Institution is committed to mobilize the resources and equip itself with men and materials of excellence, thereby ensuring that the
Institution becomes a pivotal center of service to Industry, academia, and society with the latest technology. RAIT engages different
platforms such as technology enhancing Student Technical Societies, Cultural platforms, Sports excellence centers, Entrepreneurial
Development Centers and a Societal Interaction Cell. To develop the college to become an autonomous institution & deemed university at
the earliest, we provide facilities for advanced research and development programs on par with international standards. We also seek to
invite international and reputed national Institutions and Universities to collaborate with our institution on the issues of common interest
of teaching and learning sophistication.

RAIT’s Mission is to produce engineering and technology professionals who are innovative and inspiring thought leaders, adept at solving
problems faced by our nation and world by providing quality education.

The Institute is working closely with all stake holders like industry, academia to foster knowledge generation, acquisition, dissemination
using the best available resources to address the great challenges being faced by our country and World. RAIT is fully dedicated to provide
its students skills that make them leaders and solution providers and are industry ready when they graduate from the Institution.

Goal of the Institute

We at RAIT assure our main stakeholders 100% quality of students for the programmes we deliver. This quality assurance stems from the
teaching and learning processes we have at work at our campus. The teachers are handpicked from reputed institutions IIT/NIT/MU, etc.
and they inspire the students to be innovative in thinking and practical in approach. We have installed internal procedures to better skill
sets of instructors by sending them to training courses, workshops, seminars and conferences. We also have a full-fledged course curriculum
and deliveries planned in advance for a structured semester long programme. These tools help us to ensure same quality of teaching
independent of any individual instructor. Each classroom is equipped with internet and other digital learning resources.

The effective learning process in the campus comprises a clean and stimulating classroom environment and availability of lecture notes
and digital resources prepared by instructor from the comfort of home. In addition, a student is provided with good number of
assignments that would trigger his thinking process. The testing process involves an objective test paper that would gauge the
understanding of concepts of the students. The Q&A process also ensures that the learning process is effective. The summer internships
and project work-based training ensure learning process to include practical and industry relevant aspects. Various technical events,
seminars and conferences make the student learning complete.

2
Vision of the Department

To be a place of academic excellence by imparting quality education and carrying out research and technology in frontier areas of Electronics
And Telecommunication and to produce competent leaders to face challenges of the global village , Strive towards producing world class
engineers who will continuously innovate, upgrade telecommunication technology and provide advanced, hazard-free solutions to the
mankind Inspire, educate and empower students to ensure green and sustainable society.

Mission of the Department

3
Index
Sr. No. Name of the Experiment Page No.
1. To Study & verify basic gates and universal gates. 1
2. Design EXOR and EXNOR gates using Universal gates. 2
3. Design and Implement binary to gray code converter 3
and a gray to binary code converter.
4. Implement Half adder and Full adder circuits. 4
5. Design Boolean equation using 8:1 Multiplexer. 5
6. To understand the storage of digital data in RAM 6
used in computers with the help of implementing
Flip-flops (JK and D).
7. Design a two-bit asynchronous/synchronous 7
counter using flip-flops.
8. Design synchronous MOD N counter using IC-7490. 8

4
Experiment Plan & Course
Outcome
Course Outcomes:
CO CO Description
Students will be able to understand number representation and perform
CO1 arithmetic operations.
Students will be able to apply Boolean algebra for the implementation and
CO2 minimization of logic functions.
Students will be able to analyze, design and implement Combinational logic
CO3 circuits.
Students will be able to analyze, design and implement Sequential logic
CO4 circuits.
Students will be able to design and implement various counter using flip
CO5 flops and MSI chips.
CO6 Students will be able to understand various types of programmable devices.

Exp. Week
Experiment Name CO
No. No.
To Study & verify basic gates and
1 W1 CO1
universal gates.
Design EXOR and EXNOR gates using
2 W2 CO1
Universal gates.
Design and Implement binary to gray
3 W3 code converter and a gray to binary CO2
code converter.
Implement Half adder and Full adder
4 W4 CO3
circuits.
Design Boolean equation using 8:1
5 W5 C03
Multiplexer.
To understand the storage of digital
data in RAM used in computers with
6 W6 CO4
the help of implementing Flip-flops (JK
and D).

5
 Design a two-bit
7 W7 asynchronous/synchronous counter CO4
using flip-flops.
Design synchronous MOD N counter
8 W8 CO5
using IC-7490.

6
Study & Evaluation Scheme

Course Teaching Scheme (Hrs) Credits Assigned

Course Name
Code Theory Practical Tutorial Theory TW Tutorial Total
Digital Logic
FYL204 Design Lab -- 02 -- -- 01 -- 01

Term Work:
1. Term work assessment must be based on the overall performance of the student with
every experiment graded from time to time. The grades should be converted into
marks as per the Credit and Grading System manual and should be added and
averaged.
2. The final certification and acceptance of term work ensures satisfactory performance
of laboratory work and minimum passing marks in term work.

Practical & Oral:

1. Practical & Oral exam will be based on the entire syllabus of Mobile Communication
System.

7
DIGITAL LOGIC DESIGN LAB

8
 Experiment No.
Aim:
To Study & verify basic gates and universal gates.

What will you learn by performing this experiment?

i) Learn how to use basic gates and universal gates.
ii) Implementation of gates using basic gates NAND, NOR & EX-OR gates
iii) How to use universal gates.

Hardware Required:

Sr. Apparatus / Equipment Specification

No.
1. BASIC GATES AND 7408
OR 7432
NOT 7404
2. DERIVED GATES EXOR 7486
NOR 7402
NAND 7400
3. POWER SUPPLY 5V,1A
4. DIGITAL TRAINER KIT HITECH
5. WIRES -
Theory:
There are 5 basic gates used in performing logic operations in Digital Electronic namely
BUFFER gate, NOT gate, AND gate, OR gate, XOR gate. Each Logic Gate has A Symbol
for easy to identify, a Mathematical Expression to identify mathematic logic operation and
a Truth Table to completely describe operation of the Logic Gate.

Logic gate symbols:

9
 Figure 1.1: Logic Gate Symbols

Basic gates truth table:

AND gate

Table 1.2: AND gate truth table

Figure 1.2: AND gate symbol

OR gate

Table 1.3: OR gate truth table

Figure 1.3: OR gate symbol

Table 1.4: NOT gate truth table

10
 NOT gate

Figure 1.4: NOT gate symbol

Universal gates truth table:

NAND gate

Table 1.5: NAND gate truth table

Figure 1.5: NAND gate symbol

NOR gate
Table 1.6: NOR gate truth table

Figure 1.6: NOR gate symbol

Derived gates truth table:

EXOR gate
Table 1.7: EXOR gate truth
table

Figure 1.7: EXOR gate symbol

11
EXNOR gate
Table 1.8: EXNOR gate truth table

Figure 1.8: EXNOR gate symbol

1. Pin Diagram:

Figure 1.9: AND gate IC 7408 pin configuration

Figure 1.10: OR gate IC 7432 pin configuration

12
Figure 1.11: NOT gate IC 7404 pin configuration

Figure 1.12: NAND gate IC 7400 pin configuration

Figure 1.13: EXOR gate IC 7486 pin configuration

13
 Figure 1.14: NOR gate IC 7402 pin configuration

Conclusion & Discussion:

Truth Tables of all the gates have been verified and the implementation of
basic gates using universal gates and universal gates using basic gates has been
performed successfully. Implementation of all gates using NAND & NOR proves
their universality.
Quiz / Viva Questions:
1. What is a logic gate?
2. Which of the logical operations is represented by the + sign in Boolean algebra?
3. According to non-linear devices how clippers can be classified?
4. TTL operating range (power rating)
5. When the output of a NOR gate is high?

References:

1. William I. Fletcher, “An Engineering Approach to Digital Design”, PHI, Tenth Indian
Reprint, 2001.
2. Norman Balabanian and Bradley Carlson, “Digital Logic Design Principles”, John
Wiley & Sons, First Edition, 2011.
3. A. Anand Kumar, “Fundamentals of Digital Circuits”, PHI, Second Edition, 2012.
4. Charles H. Roth, “Fundamentals of Logic Design”, Jaico Publishing House, 1st
Edition, 2004.
5. G. K. Kharate, “Digital Electronics”, Oxford University Press, First Edition, 2010
6. R. P. Jain, “Modern Digital Electronics”, Tata McGraw Hill Education, 3rd Edition
2003.
7. Frank Vahid, “Digital Design”, John Willy and Sons, First Edition, 2011
8.

14
 Experiment No.
Aim:
Design EXOR and EXNOR gates using Universal gates.

What will you learn by performing this experiment?

• Implementation of gates using basic gates NAND, NOR & EX-OR gates
• How to use universal gates
Hardware Required:

Sr. Apparatus / Equipment Specification

No.
1. BASIC GATES AND 7408
OR 7432
NOT 7404
2. DERIVED GATES EXOR 7486
NOR 7402
NAND 7400
3. POWER SUPPLY 5V,1A
4. DIGITAL TRAINER KIT HITECH
5. WIRES -
Theory:
1. Logic Diagram:

Figure 1.15: EXOR using basic gates

15
 Figure 1.16: NAND & NOR using basic gates

NAND universality:

Figure 1.17: AND, NOT, OR using NAND

Figure 1.18: NOR, EXNOR using NAND

16
 Figure 1.19: EXOR using NAND

NOR universality:

Figure 1.20: AND, NOT, OR using NOR

Figure 1.21: NAND using NOR

17
 Figure 1.22: EXOR using NOR

Figure 1.22: EXNOR using NOR

Conclusion & Discussion:

Truth Tables of all the gates have been verified and the implementation of
basic gates using universal gates and universal gates using basic gates has been
performed successfully. Implementation of all gates using NAND & NOR proves
their universality.
Quiz / Viva Questions:
1. NAND & NOR gates are called universal gates?
2. Realize the EX – OR gates using minimum number of NAND gates.
3. Give the truth table for EX-NOR and realize using NAND gates?
4. What are the logic low and High levels of TTL IC’s and CMOS IC’s?
5. Compare TTL logic family with CMOS family?
6. Which logic family is fastest and which has low power dissipation?

References:

1. William I. Fletcher, “An Engineering Approach to Digital Design”, PHI, Tenth Indian
Reprint, 2001.
2. Norman Balabanian and Bradley Carlson, “Digital Logic Design Principles”, John
Wiley & Sons, First Edition, 2011.
3. A. Anand Kumar, “Fundamentals of Digital Circuits”, PHI, Second Edition, 2012.
4. Charles H. Roth, “Fundamentals of Logic Design”, Jaico Publishing House, 1st
Edition, 2004.
5. G. K. Kharate, “Digital Electronics”, Oxford University Press, First Edition, 2010
6. R. P. Jain, “Modern Digital Electronics”, Tata McGraw Hill Education, 3rd Edition
2003.

18
Experiment No.
Aim:
Design and Implement binary to gray code converter and a gray to binary code
converter.

What will you learn by performing this experiment?

i) To explore the applications of logic gates.
ii) To study code converter.
iii) Learn how to design and implement code converter.

Hardware Required:

Sr. Apparatus / Equipment Specification

No.
1. X-OR Gate IC 7486
2. Power Supply 5V,1A
3. Digital trainer kit HITECH
4. Wires --
Theory:
The availability of large variety of codes for the same discrete elements of information results
in the use of different codes by different systems. A conversion circuit must be inserted between
the two systems if each uses different codes for same information. Thus, code converter is a
circuit that makes the two systems compatible even though each uses different binary code.

A code converter is a circuit that makes the two systems compatible even though each
uses a different binary code. To convert from binary code to Gray code, the input lines must
supply the bit combination of elements as specified by code and the output lines generate the
corresponding bit combination of code. Each one of the four maps represents one of the four
outputs of the circuit as a function of the four input variables.

A two-level logic diagram may be obtained directly from the Boolean expressions
derived by the maps.

19
1. Pin Diagram:

Figure 2(a).1: EXOR gate IC 7486 pin configuration

2. Design:

i) Truth Table:
Table 2(a).2: Binary to gray code converter truth table

Binary Code Input Gray Code Output

B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1

20
 1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

ii) K-Map
K-Map for G3: K-Map for G2:

G3 = B3
K-Map for G1: K-Map for G0:

21
 iii) Logic Diagram:
Figure 2(a).2: Binary to gray code converter

i) Truth Table:

Table 2(b).2: Gray to Binary code converter truth table

Gray Code Binary Code

G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0

22
1 0 0 0 1 1 1 1

ii) K map:
K-Map for B3: K-Map for B2:

B3 = G3
K-Map for B1: K-Map for B0:

iii) Logic Diagram:

23
 Figure 2(b).2: Gray to Binary code converter

Conclusion & Discussion:

Binary to gray code converter is designed, implemented and verified by using EX - OR
gate. Using above code converter logic we can also implement binary to excess-3 converter.
Quiz / Viva Questions:
1. What is code converter?
2. Design binary to excess-3 code converter?
3. What are the different types of code converter?
4. What is the application of code converter?

References:

1. William I. Fletcher, “An Engineering Approach to Digital Design”, PHI, Tenth Indian
Reprint, 2001.
2. Norman Balabanian and Bradley Carlson, “Digital Logic Design Principles”, John
Wiley & Sons, First Edition, 2011.
3. A. Anand Kumar, “Fundamentals of Digital Circuits”, PHI, Second Edition, 2012.
4. Charles H. Roth, “Fundamentals of Logic Design”, Jaico Publishing House, 1st
Edition, 2004.
5. G. K. Kharate, “Digital Electronics”, Oxford University Press, First Edition, 2010
6. R. P. Jain, “Modern Digital Electronics”, Tata McGraw Hill Education, 3rd Edition
2003.
7. Frank Vahid, “Digital Design”, John Willy and Sons, First Edition, 2011

24
Experiment No.
Aim:
Implement Half adder and Full adder circuits.

What will you learn by performing this experiment?

i) To explore the applications of logic gates.
ii) Learn how to design and construct Arithmetic circuits.

Hardware Required:

Sr. Apparatus / Equipment Specification

No.
1. AND GATE IC 7408
2. X-OR GATE IC 7486
3. NOT GATE IC 7404
4. OR GATE IC 7432
5. DIGITAL TRAINER KIT HITECH
6. WIRES --

Theory:
HALF ADDER:
A combinational logic circuit that performs the addition of two data bits, A and B, is
called a half-adder. Addition will result in two output bits; one of which is the sum bit, S, and
the other is the carry bit, C. The Boolean functions describing the half-adder are:

S =A ⊕ B C = AB

FULL ADDER:
The half-adder does not take the carry bit from its previous stage into account. This
carry bit from its previous stage is called carry-in bit. A combinational logic circuit that adds
two data bits, A and B, and a carry-in bit, Cin, is called a full-adder. The Boolean functions
describing the full-adder are:

S = (A⊕B) ⊕Cin C = AB + Cin (A⊕B)

25
2. Pin Diagram:

Figure 3(a).1: AND gate IC 7408 pin configuration

Figure 3(a).2: OR gate IC 7432 pin configuration

Figure 3(a).3: EXOR gate IC 7486 pin configuration

3. Design:

26
HALF ADDER:
i) Truth Table:
Table 3(a).2: Half Adder

A B SUM CARRY
0 0 0 0
0 1 1 0
1 0 1 1
1 1 0 1

ii) K-Map:
K-Map for SUM: K-Map for CARRY:

SUM = A’B + AB’ CARRY = AB

iii) Logic Diagram:

HALF ADDER

Figure 3(a).4: Half Adder

FULL ADDER:
i) Truth Table :
Table 3(a).3: Full Adder

27
 A B C SUM CARRY
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

ii) K-Map
K-Map for SUM: K-Map for CARRY:

SUM = A’B’C + A’BC’ + ABC’ + ABC CARRY = AB + BC + AC

S = (A⊕B) ⊕Cin C = AB + Cin (A⊕B)

iii) Logic Diagram:

FULL ADDER:

Figure 3(a).5: Full Adder using two half adders

28
Observation Table:
HALF ADDER:
Table 3(a).4: Half Adder
A B SUM CARRY
0 0 0 0
0 1 1 0
1 0 1 1
1 1 0 1

FULL ADDER:

Table 3(a).5: Full Adder

A B C SUM CARRY
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Conclusion & Discussion:

Half adder circuit is designed, implemented and verified using logic gates. To overcome
disadvantages of half adder circuit full adder circuit is designed and implemented. Both
circuits are verified using addition rules.

Quiz / Viva Questions:

1. What is drawback of half adder?
2. What is the advantage of full adder?
3. Design full adder using half adder?

29
References:

1. William I. Fletcher, “An Engineering Approach to Digital Design”, PHI, Tenth Indian
Reprint, 2001.
2. Norman Balabanian and Bradley Carlson, “Digital Logic Design Principles”, John
Wiley & Sons, First Edition, 2011.
3. A. Anand Kumar, “Fundamentals of Digital Circuits”, PHI, Second Edition, 2012.
4. Charles H. Roth, “Fundamentals of Logic Design”, Jaico Publishing House, 1st
Edition, 2004.
5. G. K. Kharate, “Digital Electronics”, Oxford University Press, First Edition, 2010
6. R. P. Jain, “Modern Digital Electronics”, Tata McGraw Hill Education, 3rd Edition
2003.
7. Frank Vahid, “Digital Design”, John Willy and Sons, First Edition, 2011

30
 Experiment No.
Aim:
Design Boolean equation using 8:1 Multiplexer.
To implement the function ∑m (1, 3, 5, 7, 9, 11, 13, 14) using 8:1 Multiplexer.

What will you learn by performing this experiment?

• To verify truth table for 8:1 Multiplexer
• How to make use of data & select lines of 8:1 multiplexer to implement a function.

Hardware Required:

Sr. Apparatus / Equipment Specification

No.
1. 8:1 MULTIPLEXER IC 74151
2. INVERTER IC (NOT) 7404
3. POWER SUPPLY 5V,1A
4. DIGITAL TRAINER KIT HITECH
5. CONNECTING WIRES --

Theory:
A multiplexer is a combinational digital logic switching device that has multiple
inputs and one output. In addition to the input and output lines, the multiplexer has data
select lines through which the data passed from an input line to the output line is
determined. Based on the number of input data lines, we can determine the number of
the select data lines since it is always a power of 2. For example if we have 4 input lines
we will need 2 data select lines to control it since 22 = 4. Similarly, if we have 16 input
lines we will need 4 data select lines since 24 = 16, and so on.
Multiplexing is the generic term used to describe the operation of sending one
or more analog or digital signals over a common transmission line at different times or
speeds and as such, the device we use to do just that is called a Multiplexer. The
multiplexer, shortened to “MUX” or “MPX”, is a combinational logic circuit designed
to switch one of several input lines through to a single common output line by the
application of a control signal. Multiplexers operate like very fast acting multiple
position rotary switches connecting or controlling multiple input lines called “channels”
one at a time to the output. Normally strobe (G) input is incorporated which is generally
active low which enables the multiplexer when it is LOW. Strobe i/p helps in cascading.

Using a multiplexer to implement logical functions:

31
 Another use for the multiplexer is to implement fairly complicated logic
functions without the aid of other logic gates.
As an example, examine the following function along with its resulting minimal SOP
expression.
f = ∑m (1, 3, 5, 7, 9, 11, 13, 14)
= A'D +C'D + B'D + ABCD'
In order to implement the circuit of this function for even the minimal SOP
representation, more than eight NAND gates are required. However, a single
multiplexer can be used to implement the same expression. The key is to use the input
variables for the function as the input for each select line and set the data lines to the
value for each of the corresponding outputs.

1. Pin diagram of 8:1 Multiplexer IC74151

Figure 4(a).1: 8:1 Multiplexer IC74151 pin configuration

2. Design :
i) Design table of 8:1 Multiplexer for given Boolean function:

Table 4(a).2: Design table of 8:1 Multiplexer

Select input output
A B C Y
0 0 0 D
0 0 1 D
0 1 0 D
0 1 1 D
1 0 0 D
1 0 1 D
1 1 0 D
1 1 1 D’

32
 ii) Logic Diagram:
15 14 13 12 11(A) 12(B) 13(C)

16(VCC)

74151 (8:1 MUX)

D

1 2 3 4 5(Y) 6( 7(GND) 8(GND)

Figure 4(a).2: Logic Diagram
As per experiment we have concluded with the following output table

Table 4(a).3: Truth Table

Inputs Output
A B C D Y
0 0 0 0 0
0 0 0 1 1
0 0 1 0 0
0 0 1 1 1
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 1
1 0 0 0 0
1 0 0 1 1
1 0 1 0 0
1 0 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0

33
Conclusion & Discussion:
In this experiment we designed and implemented Boolean function using Multiplexer
and output is verified using truth table. It is concluded that any Boolean function can
be implemented using Multiplexer and one Multiplexer is required for one Boolean
function. Multiplexer is also known as the data selector.

Quiz / Viva Questions:

1.What is a Multiplexer?
2. What are the applications of Multiplexing?
3. How many data lines and select lines are available for a Multiplexer?
4. What is the function of an enable input on a multiplexer chip.

References:

1. William I. Fletcher, “An Engineering Approach to Digital Design”, PHI, Tenth Indian
Reprint, 2001.
2. Norman Balabanian and Bradley Carlson, “Digital Logic Design Principles”, John
Wiley & Sons, First Edition, 2011.
3. A. Anand Kumar, “Fundamentals of Digital Circuits”, PHI, Second Edition, 2012.
4. Charles H. Roth, “Fundamentals of Logic Design”, Jaico Publishing House, 1st
Edition, 2004.
5. G. K. Kharate, “Digital Electronics”, Oxford University Press, First Edition, 2010
6. R. P. Jain, “Modern Digital Electronics”, Tata McGraw Hill Education, 3rd Edition
2003.
7. Frank Vahid, “Digital Design”, John Willy and Sons, First Edition, 2011

34
Experiment No.
Aim:
To understand the storage of digital data in RAM used in computers with the help of
implementing Flip-flops (JK and D).

What will you learn by performing this experiment?

• To study different flip flops

• Conversion of flip flops

Hardware Required:

Sr. Apparatus / Equipment Specification

No.
1. JK FLIP FLOP 7476
2. D FLIP FLOP 7474
3. POWER SUPPLY 5V,1A
4. DIGITAL TRAINER KIT HITECH
5. WIRES --
6. EXOR GATE 7486
NOT GATE 7404

Theory:
Flip-flops are the basic building blocks of sequential circuit. The clocked FFs
change their output state depending upon inputs at certain interval of time
synchronized with the clock pulse applied to it. Different types of FFs are S-R, J-
K, D & T. Their operations are described by the respective truth tables. MSI chip
7476 incorporates two negative edge triggered Master–Slave JK flip flops. The J-K
flip flop can be converted to D flip-flop.

(i) J K FLIP FLOP

For purpose of counting, the JK flip-flop is the ideal element to use. The variable J
and K are called control I/Ps because they determine what the flip- flop does when
a positive edge arrives. When J and K are both 0s, Q retains its last value. The J-K
Flip-Flop IC is used to shift data from one point to another in a circuit in a timed
fashion using a clock/strobe pulse to control the data flow. The J-K is also used as
a binary counter. The number of bits in the counter byte is determined by the
number of J-Ks that are linked (output-to-input fashion).

35
 Figure 5.1: J-K Flip Flop

Table 5.2: Truth Table

J K Clk Q
0 0 Q(No change)
1 0 1
0 1 0
1 1 Q’(Toggles)

(ii) D FLIP-FLOP:

The D Flip Flop is the most important of the Clocked Flip-flops as it ensures that inputs
S and R are never equal to one at the same time. The D-type flip flop is constructed from
a gated SR flip-flop with an inverter added between the S and the R inputs to allow for a
single D (data) input.

Then this single data input, labelled D, is used in place of the “set” signal, and the inverter
is used to generate the complementary “reset” input thereby making a level-sensitive D-
type flip-flop from a level-sensitive RS-latch as now S = D and R = not D as shown.
D-type Flip-Flop Circuit

Figure 5.2: D Flip Flop

36
 Table 5.3: Truth Table
Clk D Q
0 O
1 1

We remember that a simple SR flip-flop requires two inputs, one to “SET” the output and
one to “RESET” the output. By connecting an inverter (NOT gate) to the SR flip-flop we
can “SET” and “RESET” the flip-flop using just one input as now the two input signals are
complements of each other. This complement avoids the ambiguity inherent in the SR latch
when both inputs are LOW, since that state is no longer possible.

Thus this single input is called the “DATA” input. If this data input is held HIGH the flip
flop would be “SET” and when it is LOW the flip flop would change and become
“RESET”. However, this would be rather pointless since the output of the flip flop would
always change on every pulse applied to this data input.

To avoid this an additional input called the “CLOCK” or “ENABLE” input is used to isolate
the data input from the flip flop’s latching circuitry after the desired data has been stored.
The effect is that D input condition is only copied to the output Q when the clock input is
active. This then forms the basis of another sequential device called a D Flip Flop.

(iii) T FLIP FLOP:

T flip-flop is known as toggle flip-flop. The T flip-flop is modification of the J-K flip-flop.
Both the JK inputs of the JK flip – flop are held at logic 1 and the clock signal continuous
to change.

Figure 5.3: T Flip Flop

Table 5.4: Truth Table

37
 Clock Pulse T Input Q(t+1)

0 x NC

1 0 NC

1 1 Toggle (Qt)'

1. Pin Diagram :
PART I:
Conversion of JK to D flip-flop

Figure 5.4: J-K Flip-Flop IC7476 Pin Configuration

NOT gate pin configuration:

Figure 5.5: NOT gate IC7404 pin configuration

PART II:

38
 Conversion of D to T flip-flop

Figure 5.6: D Flip-Flop IC7474 pin configuration

EXOR gate pin configuration:

Figure 5.7: EXOR gate IC7486 pin configuration

2. Design:
PART I:
Conversion of JK to D flip-flop

D is the external input and J and K are the actual inputs of the flip flop. D and Qp make
four combinations. J and K are expressed in terms of D and Qp. The four combination
conversion table, the K-maps for J and K in terms of D and Qp, and the logic diagram
showing the conversion from JK to D are given below.

i) Conversion Table: Table 5.5: Conversion Table

Outputs J-K Inputs

39
 D
Qp Qp +1 J K
Input
0 0 0 0 X
0 1 0 X 1
1 0 1 1 X
1 1 0 X 0

ii) K-map:

Figure 5.8: K-Map

iii) Logic Diagram:

Figure 5.9: Logic Diagram

PART II:
Conversion of D to T flip-flop
i) Conversion Table:

40
 Table 5.6: Conversion Table

ii) K-map:

Figure 5.10: K-Map

iii) Logic Diagram:

Figure 5.11: Logic Diagram

Part I:
Table 5.7: D-Flip Flop Truth Table
clk D Q
0 O
1 1

Part II:

41
 Table 5.8: T-Flip Flop Truth Table

Clock Pulse T Input Q(t+1)

0 x NC

1 0 NC

1 1 Toggle (Qt)'

Conclusion & Discussion:

We designed and implemented D-Flip flop using J-k Flip flop and T-Flip flop using D-Flip
flop and verified its output using truth table. It is observed that any flip-flop can be converted
into any other flip-flop.

Quiz / Viva Questions:

1. Differentiate between a latch and a flip flop.
2. Differentiate between combinational and sequential circuits.
3. How is a JK flip flop made to toggle?
4. Which is the basic sequential building block in which the output follows the data
input as long as the enable input is active?
5. How many stable states a flip flop has?

References:

1. William I. Fletcher, “An Engineering Approach to Digital Design”, PHI, Tenth Indian
Reprint, 2001.
2. Norman Balabanian and Bradley Carlson, “Digital Logic Design Principles”, John
Wiley & Sons, First Edition, 2011.
3. A. Anand Kumar, “Fundamentals of Digital Circuits”, PHI, Second Edition, 2012.
4. Charles H. Roth, “Fundamentals of Logic Design”, Jaico Publishing House, 1st
Edition, 2004.
5. G. K. Kharate, “Digital Electronics”, Oxford University Press, First Edition, 2010
6. R. P. Jain, “Modern Digital Electronics”, Tata McGraw Hill Education, 3rd Edition
2003.
7. Frank Vahid, “Digital Design”, John Willy and Sons, First Edition, 2011

42
Experiment No.
Aim:
Design a two-bit asynchronous/synchronous counter using flip-flops.

What will you learn by performing this experiment?

• State table for Mod 10 asynchronous counter
• Designing asynchronous Mod 10 counter using JK Flip Flop IC
• Verifying truth tables for asynchronous counter

Hardware Required:

Sr. Apparatus / Equipment Specification

No.
1. JK FLIP FLOP IC 7476 (2 ICs)
2. NAND GATE IC 7400
3. POWER SUPPLY 5V,1A
4. DIGITAL TRAINER KIT HITECH
5. CONNECTING WIRES --

Theory:
“Asynchronous counter” is a counter circuit, which created from the series of J-K flip-flops.
The clock signal will be given to the clock input of the first J-K flip-flop then the
output of the first J-K flip-flop will connect to the input of the adjacent flip-flop.
The output signal, which represents the current binary counting value, is the
output signal (Q) of all J-K flip-flops. While the output (Q) of the first J-K flip-
flop is the least significant bit (LSB) of the binary value.
The maximum number of counting value depends on the number of J-K flip-flops
in the circuit. For example, the 4 bits counter is composed of 4 J-K flip-flops.
This maximum number, which this counter can count, is 24 = 16. Hence, this
counter can count from 0 to 15.

If the output (Q) of the first J-K flip-flop is connected to the clock input of the
adjacent J-K flip-flop, this counter will be the count-up counter.
Modulus counters, or simply MOD counters, are defined based on the number of
states that the counter will sequence through before returning back to its original
value. For example, a 2-bit counter that counts from 00 to 11 in binary, that is 0 to
3 in decimal, has a modulus value of 4 ( 00 → 01 → 10 → 11 , return back to 00 )

43
 so would therefore be called a modulo-4, or mod-4, counter. Note also that it has
taken 4 clock pulses to get from 00 to 11.
In the case of modulo “m” counters, they do not count to all their possible states,
but instead count to the “m” value and then return to zero. Obviously, “m” is a
number smaller than 2n, (m < 2n), where n is number of flip flops.
As we are constructing a MOD-10 counter, we want the counter to reset back
to zero after a count of 10.The count of ten gives us the output condition of:
QD = 1, QC = 0, QB = 1, and QA = 0.
We can decode this output state of 1010 (10) to give us a signal to clear (Clr) the
counter back to zero with the help of a 2-input NAND gate (TTL 74LS00)

Figure 6(a).1: Waveform

1. Pin Diagram :

J-K Flip-flop pin configuration:

44
 Figure 6(a).2: J-K Flip-FlopIC7476 pin configuration

NAND gate pin configuration:

Figure 6(a).3: NAND gate IC7400 pin configuration

2. Design :
i) Truth Table:
Table 6(a).2: Truth Table
Clock Output Bit Pattern Decimal
Count QD QC QB QA Value
1 0 0 0 0 0

45
 2 0 0 0 1 1
3 0 0 1 0 2
4 0 0 1 1 3
5 0 1 0 0 4
6 0 1 0 1 5
7 0 1 1 0 6
8 0 1 1 1 7
9 1 0 0 0 8
10 1 0 0 1 9
11 Counter Resets its outputs back to zero

ii) Logic Diagram:

Figure 6(a).4: Logic Diagram

As per experiment we have concluded with the following output table

Table 6(a).3: State Table
Clock Output Bit Pattern Decimal
Count QD QC QB QA Value
1 0 0 0 0 0
2 0 0 0 1 1
3 0 0 1 0 2
4 0 0 1 1 3
5 0 1 0 0 4
6 0 1 0 1 5
7 0 1 1 0 6
8 0 1 1 1 7
9 1 0 0 0 8
10 1 0 0 1 9
11 Counter Resets its outputs back to zero

46
Conclusion & Discussion:
We designed and implemented mod-10 asynchronous counter using j-k Flip flop
and verified its output using truth table. It is observed that counter do not count to
all their possible states, but instead count to the 10 values and then return to zero.

Quiz / Viva Questions:

1. What is the difference between combinational logic and sequential logic?
2. What will be the terminal count of a modulus-11 binary counter?
3. What are the advantages of asynchronous counters over synchronous
counters?
4. What are the applications of asynchronous counters?
5. What is meant by propagation delay?

References:

1. William I. Fletcher, “An Engineering Approach to Digital Design”, PHI, Tenth Indian
Reprint, 2001.
2. Norman Balabanian and Bradley Carlson, “Digital Logic Design Principles”, John
Wiley & Sons, First Edition, 2011.
3. A. Anand Kumar, “Fundamentals of Digital Circuits”, PHI, Second Edition, 2012.
4. Charles H. Roth, “Fundamentals of Logic Design”, Jaico Publishing House, 1st
Edition, 2004.
5. G. K. Kharate, “Digital Electronics”, Oxford University Press, First Edition, 2010
6. R. P. Jain, “Modern Digital Electronics”, Tata McGraw Hill Education, 3rd Edition
2003.
7. Frank Vahid, “Digital Design”, John Willy and Sons, First Edition, 2011

47
Experiment No.
Aim:
Design synchronous MOD N counter using IC-7490.

What will you learn by performing this experiment?

• State table for Mod 8 synchronous counter
• Designing synchronous Mod 8 counter using JK Flip Flop IC
• Verifying truth tables for synchronous counter

Hardware Required:

Sr. Apparatus / Equipment Specification

No.
1. JK FLIP FLOP IC 7476 (2 ICs)
2. INVERTER IC (NOT) 7404
3. POWER SUPPLY 5V,1A
4. DIGITAL TRAINER KIT HITECH
5. CONNECTING WIRES -

Theory:
“Synchronous counter” was created for figure out the problem of counter
circuit, which contains a lot of bits for counting. In this case, if we use asynchronous
counter, it will consume a lot of time to complete one counting. Since the adjacent
counter need to wait the previous counter to complete the counting first, before
receiving the output signal for counting and sending the output signal to the next flip-
flop.
The synchronous counter was designed by parallel connecting the input signal
to the clock input of each flip-flop. The maximum number of counting value depends
on the number of flip-flops in the circuit, which equals to2n (where n is the number of
flip- flops in the circuit).

48
1. Pin Diagram :

J-K Flip-flop pin configuration:

Figure 6(b).1: J-K Flip-Flop IC 7476 Pin configuration

AND gate pin configuration:

Figure 6(b).2: AND gate IC 7476 Pin configuration

49
2. Design:
i) Circuit excitation Table:
Table 6(b).2: Circuit excitation Table
Q2 Q1 Q0 Q2+1 Q1+1 Q0+1 J2 K2 J1 K1 J0 K0
0 0 0 0 0 1 0 X 0 X 1 X
0 0 1 0 1 0 0 X 1 X X 1
0 1 0 0 1 1 0 X X 0 1 X
0 1 1 1 0 0 1 X X 1 X 1
1 0 0 1 0 1 X 0 0 X 1 X
1 0 1 1 1 0 X 0 1 X X 1
1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 0 0 0 X 1 X 1 X 1

ii) Boolean Expression:

J2 = Q1.Q0 K2 = Q1.Q0
J1 = Q0 K1 = Q0
J0 = 1 K0 = 1

iii) Logic Diagram:

Figure 6(b).3: Logic Diagram

50
 As per experiment we have concluded with the following output table
Table 6(b).3: State Table
Counter Q2 Q1 Q0
State
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1

Conclusion & Discussion:

We designed and implemented mod-8 synchronous counter using j-k Flip flop and verified its
output using truth table. It is observed that counter counts all their possible states and then
return to zero.

Quiz / Viva Questions:

1. What are the advantages of synchronous counters over asynchronous counters?
2. What types of flip-flops can be used to implement the memory elements of a
counter?
3. What are the applications of synchronous counters?

References:

1. William I. Fletcher, “An Engineering Approach to Digital Design”, PHI, Tenth Indian
Reprint, 2001.
2. Norman Balabanian and Bradley Carlson, “Digital Logic Design Principles”, John
Wiley & Sons, First Edition, 2011.
3. A. Anand Kumar, “Fundamentals of Digital Circuits”, PHI, Second Edition, 2012.
4. Charles H. Roth, “Fundamentals of Logic Design”, Jaico Publishing House, 1st
Edition, 2004.
5. G. K. Kharate, “Digital Electronics”, Oxford University Press, First Edition, 2010
6. R. P. Jain, “Modern Digital Electronics”, Tata McGraw Hill Education, 3rd Edition
2003.
7. Frank Vahid, “Digital Design”, John Willy and Sons, First Edition, 2011

51
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