B.M.S.

College of Engineering, Bengaluru-19

(Autonomous College under VTU)
Department of Electronics and Communication Engineering
Course Title: HDL Programming Course code: 23EC3ESHDL Third CIE
SCHEME AND SOLUTIONS

Q.1 Explain the RTL to gate-level logic synthesis flow.

------ (3M)
Fig: RTL to Gate Level logic Synthesis flow

 RTL description: The designer describes the design at a high level by using RTL
constructs.
It refers to the flow of digital signals (data) between hardware registers, and the logical
operations performed on those signals.
 Translation: The RTL description is converted by the logic synthesis tool to an
unoptimized, intermediate, internal representation.
Design constraints such as area, timing, and power are not considered in the translation process.
 Unoptimized intermediate representation: The translation process yields an
unoptimized intermediate representation of the design.
 Logic optimization: The logic is now optimized to remove redundant logic. Various
technology independent Boolean logic optimization techniques are used.
It yields an optimized internal representation of the design.
 Technology mapping and optimization: In this step, the synthesis tool takes the
internal representation and implements the representation in gates, using the cells
provided in the technology library.
 Technology library: The technology library contains library cells provided by Chip
manufacturer.
 Synthesis tool uses these cells to implement the design.
 Design constraints: Timing, Area and Power constraints are considered here.
 Optimized gate-level description: After the technology mapping is complete, an
optimized gate-level netlist described in terms of target technology components is
produced.
 If this netlist meets the required constraints, it is handed to manufacturer for final
layout.
------ (5M)

Q.2 Implement using “generate” construct an N-bit Asynchronous Down Counter

instantiating T flip-flops.

------ (3M)
Code for N-bit Asynchronous Down Counter instantiating T flip-flops.

module asynchConter(clk, Q, Qbar);

parameter N = 3; // N=3, for 3-bit counter.
input clk;
output [N-1:0] Q, Qbar;
wire [N:0] s;
assign s = {Q, clk};
/* s is the concatenation of Q and clk. We need this
concatenation to describe the clock of each T flip-flop. */
generate
genvar i;
for (i = 0; i < N; i = i + 1)
begin
T_FF TFF0 (1'b1, s[i], Q[i], Qbar[i]);
end
endgenerate
 endmodule
------ (3M)

Code for T_FF

module T_FF (
input clk,
input rst,
input t,
output reg q);
always @ (posedge clk) begin
if (!rst)
q <= 0;
else
if (t)
q <= ~q;
else
q <= q;
end
endmodule
------ (2M)

Q.3 Design a Mealy FSM to detect the sequence of “1101” with 1-bit overlapping using
Verilog HDL.

------ (3M)

------ (1M)
 module seq_detector (
input clk,
input reset,
input in,
output reg out
);
reg [2:0] present_state, next_state;

Parameter [2:0] {S0 = 3'b000, S1 = 3'b001, S2 = 3'b010,

S3 = 3'b011};

always @ (present_state or in)

begin
case (present_state)
S0: next_state = (in) ? S1 : S0;
S1: next_state = (in) ? S2 : S0;
S2: next_state = (in) ? S3 : S0;
S3: next_state = (in) ? S1 : S0;
default: next_state = S0;
endcase
end

always @ (posedge clk or posedge reset)

begin
if (reset)
present_state <= S0;
else
present_state <= next_state;
end
endmodule
------ (4M)

Q.4 Develop a Moore-type Serial Adder in Verilog, including the design of the corresponding
state diagram. Draw the necessary state diagram.

-G0 and G1 to denote the fact that the carry is 0 and that the sum is either 0 or 1.
-H0 and H1 denote that the carry is 1 and that the sum is either 0 or 1.

------ (4M)
module serial_add(a, b, reset, clk, sum, c_out);
input a, b, clk, reset;
output reg sum;
output reg c_out; /// carry out
reg [1:0] cst, nst;
parameter G0 = 2'b00, G1 = 2'b01, H = 2'b10, H1= 2'b11;
initial cst[1] = G0;
always @(cst,a,b)
begin
case (cst)
G0 : begin
sum=1’b0;
if(a&b)
nst = H0;
else if (a^b)
nst = G1;
else
nst = G0;
end
G1 : begin
sum=1’b1;
if(a&b)
nst = H0;
else if (a^b)
nst = G1;
else
nst = G0;
end
H0 : begin
sum=1’b0;
if(a&b)
nst = H1;
else if (a^b)
nst = H0;
else
nst = G1;
end
H1 : begin
sum=1’b1;
if(~a&~b)
nst = G1;
else if (a^b)
nst = H0;
else
nst = H1;
end
default: nst = G;
endcase
end // end of first always block
always@(posedge clk)
begin
 if (reset)
cst <= G0;
else
cst <= nst;
end
assign c_out = cst[1];
endmodule ------ (4M)

Q.5 (a) Analyse the below given code, write the complete Verilog code and draw the
synthesized logic circuit.

…………
…………
always @(X)
begin
if (X[0] == 1’b1)
Y = 3’d7;
else if (X[1] == 1’b1)
Y = 3’d6;
else if (X[2] == 1’b1)
Y = 3’d5;
else
Y = 3’d0;
end
…………
…………

module priority_encoder
( input [2:0] X, // 3-bit input vector
output reg [2:0] Y // 3-bit output vector
);
always @(X)
begin
if (X[0] == 1'b1)
Y = 3'd7; // Y = 111 when X[0] is 1
else if (X[1] == 1'b1)
Y = 3'd6; // Y = 110 when X[1] is 1
else if (X[2] == 1'b1)
Y = 3'd5; // Y = 101 when X[2] is 1
else
Y = 3'd0; // Y = 000 otherwise
end
endmodule
------ (2M)
 ------ (4M)

Q.5 (b) Draw the inferred logic for the code snippet given below.

module example (input ct, a, output reg out);

always @ (*)
if (ct)
out = a;
endmodule

Inputs: ct (control signal) and a (data input).

Output : out

If ct = 1, the output ‘out’ is assigned the value of a.

This design can be synthesized as a simple D-Latch

------ (2M)

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