5SFC0 Advanced CMOS design - Design a current mirror OTA

Guru Prasad Murugan

[email protected] and 2093669
I. INTRODUCTION
Analog circuit design relies heavily on the design and
analysis of current mirror operational transconductance
amplifiers (OTAs), especially for applications that demand
high gain, low power consumption, and accuracy. A current
mirror OTA achieves high input impedance, low output
impedance, and higher linearity by utilizing the concepts of
differential pair operation and current replication. The
implementation at the transistor level facilitates a thorough Fig. 2. Gain value at parameterized gain values
investigation of important design trade-offs, such as
stability, power efficiency, and matching precision. To
reduce process variability and improve the functionality of
the existing mirror structure, strategies such geometric
matching, common centroid layout, and symmetry in device
placement will be used. 45nm technology has been utilized
and components from NCSU FreePDK 45 have been used in Fig. 3. Schematic diagram
the realization of the schematic.
II. LAB DESCRIPTION
Length, width, Miller capacitance and number of fingers
were parameterized. The required gain of 60dB at low
frequency was obtained. The gain curve was obtained by
using the dB20 function. The function is used in frequency
response analysis, plotting the dB20(mag(output voltage))
over a range of frequencies allows visualization of gain/
attenuation of a circuit as a function of frequency. Fig. 4. Unity gain bandwidth obtained at 500 MHz
1.2. The gain at low frequencies should be more than 60dB;
What do you think will be better a single or two-stage
architecture?
Gain of 60dB has been obtained. A two-stage amplifier is
suited for achieving high gain, as it allows for cascading
multiple stages to amplify the signal. A two-stage amplifier
can also be designed to achieve high bandwidth by careful
selection of components and optimization of the circuit.
Fig. 1. Gain vs Frequency [AC Analysis] 1.3. The unity gain bandwidth should be at least 500MHz
Parameter Value Unity gain of 1dB has been obtained at 500MHz by
Gain 59.861 dB optimizing the W/L ratio value.
2. Synthesize the architecture and design a solution. How
Length 900 nm
can you optimize the power consumption? How do you
Number of fingers 4878
guarantee the OTA stability?
Width 1000 nm
Power consumption optimization
The design has been simulated in such a way that the  Power consumption could be optimized by scaling
unity gain bandwidth is at least 500 MHz. The figure and down transistor widths and lengths to reduce
table below shows the value of gain at 500 MHz at capacitance and power. The W/L ratio has been
parameterized value of number of fingers. Therefore, the chosen in such a way to optimize g m per unit
number of fingers is optimized to 4878. current.
Number of fingers Gain value  Efficient biasing has been implemented with a
4147 3.74239 mdB current reference to minimize quiescent current.
4976 722.509 mdB OTA stability
 Feedback technique has been appropriately used to
improve stability. The feedback network is
designed in such a way to provide sufficient phase
margin.
  Miller compensation of using a compensation
capacitor introduces a dominant pole and pushes
non-dominant poles further out. The compensation
capacitor is also used to achieve the desired phase
margin.
 Components with low parasitic capacitances have
been chosen.
5. Run transient simulations and investigate:
5.1. Transient settling for 1V input step signal. What is the
slew rate?
5.2. BONUS: Transient response for 10µV input peak-to-
peak dual-tone signal at center frequency 10MHz and Fig. 9. Spectrum
10kHz tone-spacing. Show the spectrum. Plot IMD3 vs
input frequency. How can you improve? III. CONCLUSIONS
A current mirror operational transconductance amplifier
of given design specifications has been designed,
subsequently, AC analysis, Parametric analysis, and
Transient analysis were performed to obtain the required
gain at low frequency and unity-gain bandwidth. Entire
analysis was implemented in cadence virtuoso tool.

Fig. 5. Transient characteristics of 1V step signal

∆V
Slew rate=
∆t
209.9211 mV
Slew rate=
1.06091 ns

Fig. 7. Input signal of transient response of 10µV pk-pk

signal

Fig. 8. Output signal of transient response of 10µV pk-pk

signal