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CompArch Sample Exam With Answers

The document is a sample exam for the Computer Architecture & Organization course at the Addis Ababa Institute of Technology. It consists of multiple parts, including single-word answers, brief explanations, and programming tasks related to computer architecture concepts. Topics covered include special purpose registers, instruction fetch cycles, micro operations, stack machine programming, cache memory calculations, and instruction pipelining.

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SALAS DELIL
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9 views3 pages

CompArch Sample Exam With Answers

The document is a sample exam for the Computer Architecture & Organization course at the Addis Ababa Institute of Technology. It consists of multiple parts, including single-word answers, brief explanations, and programming tasks related to computer architecture concepts. Topics covered include special purpose registers, instruction fetch cycles, micro operations, stack machine programming, cache memory calculations, and instruction pipelining.

Uploaded by

SALAS DELIL
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Addis Ababa Institute of Technology

School of Electrical and Computer Engineering


Computer Architecture & Organization
SAMPLE EXAM

Name ________________________________ ID______________

Read the Instruction Carefully and answer the following Questions.


PART I
Write a Single word answer for the following Questions. ( 2 pts each)
1. Name the special purpose register that stores the data to be written or read from memory.
Answer: _________________Memory Buffer Register ______________
2. Name the special purpose register that holds operands temporarily and results of ALU operation.
Answer: __________Accumlator__________
3. What is the technique used to look ahead in the instruction code and fetch the once to be likely
executed in the next cycles. Answer: __________Branch Prediction____________
4. Suppose that a computer has 128 Megabytes of memory. Exactly, how many 32-bit words of
memory is this? Answer: __________227/2=225_______________________

PART II
Write answers briefly for the following questions
5. (6 pts )Explain what happens during Instruction Fetch and Interrupt Cycle With simple steps.
Answer:
Instruction Fetch
PC contains address of next instruction
Address moved to MAR
Address placed on address bus
Control unit requests memory read
Result placed on data bus, copied to MBR, then to IR
Meanwhile PC incremented by 1

Interrupt Cycle

Current PC saved to allow resumption after interrupt


Contents of PC copied to MBR
Special memory location (e.g. stack pointer) loaded to MAR
MBR written to memory
PC loaded with address of interrupt handling routine

6. (2 pts.) Write the Micro operations (symbolic) for indirect cycle


Answer:
t1: MAR <- (IRaddress) - address field of IR
t2: MBR <- (memory)
PC <- (PC) +1
t3: IRaddress <- (MBRaddress)
5. (4 pts.) Write a short program for a stack machine which computes (A/B)-(C*D).
Answer:-
Push A
Push B
div
Push C
Push D
Mult
sub

PART III
Show all the Necessary steps for the Questions below.

7. (4 pts.) Write programs to compute for each of the four machines and compare one-, two-
, and three-address machines by writing programs to compute for each of the four
machines.
X = (A – B/ C) / (D* E + F)
Answer:
3-address 2-address
Comment Comment
DIV Z,B,C Z<=B/C LOAD Z,B Z<=B
SUB Z,A,Z Z<=A-Z DIV Z,C Z<=Z/C
MULT K,D,E K<=D*E LOAD X,A X<=A
ADD K,F,K Z<=F+K SUB X,Z X<=X-Z
DIV X,Z,K X<=Z/K LOAD Z,D Z<=D
MULT Z,E Z<=Z*E
ADD Z,F Z<=Z+F
DIV X,Z X<=X/Z

8. (8 pts.) Consider a 2-way set-associative cache


- Data words are 32 bits long
- Words are addressed to the byte
- The cache holds 8 Mbytes of data
- Each block holds 32 data words
- Physical addresses are 32 bits long
How many bits of tag (s-r), index (r), and offset (w) are needed to support references to this
cache?
Answer:-
We can calculate the number of bits for the offset first:
- There are 16 data words per block which implies that at least 4 bits are needed
- Because data is addressable to the 1/4 word ( Byte ), an additional 2 bit of offset is
needed
- Thus, the offset is 6 bits
A cache line contains = 32 * 32 bit/ 8 = 64 Bytes= 27 bytes.
W = 7;

To calculate the index, we need to use the information given regarding the total capacity of
the cache:
- 2 MB is equal to 223 total bytes.
- We can use this information to determine the total number of blocks in the
cache…
o 223 bytes x (1 block / 32 words) x (1 word / 32 bits) x (8 bits / 1 byte) = 2 16 blocks
- Now, there are 4 (or 212) blocks / set
o Therefore there are 216 blocks x (1 set / 21 blocks) = 215 sets
- Thus, 15 bits of index are needed
Finally, the remaining bits form the tag:
- 32– 6 – 15 = 11
- Thus, there are 11 bits of tag

To summarize: Tag: 11 bits; Index: 15 bits; Offset: 7 bits

9. (6 pts.) Assume that the following sequence of instruction is executed by the processor with a
pipeline containing stages: IF, ID, EX, M and W; and contains a single memory for read/write.
I1: Load R1,M(25)
I2: Mul R2,R3
I3: Sub R1,R2
I4: Add R2, R3
I5: Stor R2,M(45)
Using the table below, show the instruction that resides in each stage of the pipeline for each clock period.
Instructions Clock cycle number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Load R1,M(25) IF ID Ex M W
Mul R2,R3 IF ID Ex M W
Sub R1,R2 IF ID # # Ex M W
Add R2, R3 IF # # ID Ex M W
Stor R2,M(45) IF ID Ex # M W

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