COMPTE RENDU TP2

VHDL :
Les instructions du mode
Concurrent et séquentiel

REALISER PAR : MAKRI SABRINE

CLASSE : IOT-2A GROUPE 2
Partie 1 : circuits logiques combinatoires :s

1 1 1 1 1 1 0 0

0 1 1 0 0 0 0 1
Partie 2 circuits logiques séquentiels
1 1 0 1 1 0 1 2

1 1 1 1 0 00 1 3

0 1 1 0 0 1 1 4

1 0 1 1 0 1 1 5

1 0 1 1 1 1 1 6

1 1 1 0 0 0 0 7

1 1 1 1 1 1 1 8

1 1 1 1 0 1 1 9
library ieee ;
Use ieee.std_logic_1164.all;
Use ieee.numeric_std.all;
Use ieee.std_logic_unsigned.all;

Entity segt is
port(N: in std_logic_vector(3
downto 0);
S: out std_logic_vector(6
downto 0));
end segt;

Architecture Arch of segt is

Begin

with N select
S <= "1111110" when "0000",
"0110000" when "0001",
"1101101" when "0010",
"1111001" when "0011",
"0100111" when "0100",
"1011011" when "0101",
"1011111" when "0110",
"1110000" when "0111",
"1111111" when "1000",
"1110111" when "1001",
"0000000" when others ;
end Arch ;

Partie 2 circuits logiques séquentiels :

 library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all; use ieee.std_logic_unsigned.all;
entity basc is entity bbd is
port( end bbd;
d: in std_logic; architecture ARCH of bbd is
h:in std_logic; component basc
qn: out std_logic); port(
end basc; d:in std_logic;
architecture arche of basc is h:in std_logic;
begin qn:out std_logic);
process(h) end component;
begin signal x_d:std_logic:='0';
if(h'event and h='1') then signal y_h:std_logic:='0';
qn<= d; signal qn:std_logic;
end if ; begin
end process; por:basc port map(x_d,y_h,qn);
end arche; process
begin
x_d<='0';
y_h<='0';
wait for 10ns;
x_d<='1';
y_h<='0';
wait for 10ns;
x_d<='0';
y_h<='1';
wait for 10ns;
x_d<='1';
y_h<='1';
wait for 10ns;
wait;
end process;
end ARCH;
 use ieee.numeric_std.all;
library ieee; use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all; entity compt is
use ieee.numeric_std.all; end compt;
use ieee.std_logic_unsigned.all; architecture archhi of compt is
entity comp is component comp
port( port(
h:in std_logic; h:in std_logic;
s: out std_logic_vector(3 downto 0) s: out std_logic_vector(3 downto 0)
);end comp; );
architecture arch of comp is end component;
signal r: std_logic ;
signal i:integer range 0 to 15; signal q_h:std_logic:='0';
begin
s<= std_logic_vector(to_unsigned signal q_s:std_logic_vector(3 downto
(i,4)); 0):="0000";
process(h,i)
begin begin
por:comp port map(q_h,q_s);
if (h'event and h='1')then process
begin
i<=i+1; q_h<='0';
end if; wait for 10ns;
end process; q_h<='1';
end arch; wait for 10ns;
q_h<='0;
wait for 10ns;
q_h<='1';
wait for 10ns;
q_h<='0';
wait for 10ns;
q_h<='1';
wait for 10ns;
q_h<='0';
wait for 10ns;
q_h<='1';
wait for 10ns;
wait;
end process;
end archhi;
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all; use ieee.std_logic_unsigned.all;
entity comp is entity compt is
port( end compt;
h:in std_logic; architecture archhi of compt is
res:in std_logic; component comp
s: out std_logic_vector(3 downto 0) port(
);end comp; h:in std_logic;
architecture arch of comp is res: in std_logic;
signal i:integer range 0 to 15; s: out std_logic_vector(3 downto 0)
begin );
s<= std_logic_vector(to_unsigned (i,4)); end component;
process(h,i) signal q_h:std_logic:='0';
begin signal r: std_logic;
signal q_s:std_logic_vector(3 downto
if (h'event and h='1')then 0):="0000";
if(res='1')then
i<=0; begin
else por:comp port map(q_h,r,q_s);
i<=i+1; process
end if; begin
end if; q_h<='0';
end process; r<='0';
end arch; wait for 10ns;
q_h<='1';
r<='0';
wait for 10ns;
q_h<='0';
r<='1';
wait for 10ns;
q_h<='1';
r<='1';
wait for 10ns;

end process;
end archhi;
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all; use ieee.std_logic_unsigned.all;
entity comp is entity compt is
port( end compt;
res:in std_logic; architecture archhi of compt is
h:in std_logic; component comp
s: out std_logic_vector(3 downto 0) port(
);end comp; h:in std_logic;
architecture arch of comp is res: in std_logic;
signal i:integer range 0 to 15; s: out std_logic_vector(3 downto 0)
begin );
s<= std_logic_vector(to_unsigned (i,4)); end component;
process(h,i) signal r: std_logic ;
begin signal q_h:std_logic:='0';
if(res='1')then
i<=0; signal q_s:std_logic_vector(3 downto
if (h'event and h='1')then 0):="0000";
i<=i+1;
end if; begin
end if; por:comp port map(r,q_h,q_s);
end process; process
end arch; begin
q_h<='0';
r<='0';
wait for 10ns;
q_h<='1';
r<='0';
wait for 10ns;
q_h<='0';
r<='1';
wait for 10ns;
q_h<='1';
r<='1';
wait for 10ns;

end process;
end archhi;