1

A Fully Differential Wide-Band Operational Amplier

Huiyu Luo
Email: [email protected]

Jun Shi
Email: [email protected]

December 9, 2004

Gain 3-dB Bandwidth Diff. output swing HD3 Open loop phase margin Supply voltage Power dissipation
TABLE I
Fig. 1. A low-pass lter

5 1% 9.95MHz1% 1.6V < 1% > 60 1.8V minimum

D ESIGN S PECIFICATIONS

I. D ESIGN S PECIFICATIONS AND I NITIAL D ECISION A fully differential wide-band operational amplier is designed for a 1st-order RC low-pass lter. The low-pass lter and specications are shown in Fig. 1 and Table I. The output is used to drive an identical stage. Given the low load resistance (R1 = 2k), we realized that using a single-stage amplier is impossible to achieve a reasonably high gain (for example, DC gain of 594 is required to reach 1% error on the closed loop gain). Thus, a two-stage structure is mandatory. Initially, we design the rst stage to be a fully differential pairs with active load, which provides most of the required gain. The second stage is a simple common source stage which provides large output swing and additional gain. The detailed analysis is presented in the next section.

II. A NALYSIS U NDER I DEAL C ONDITIONS We model the operational amplier as a voltage-controlled voltage source with nite gain. The diagram is shown in Figure 2. The open loop voltage gain is A, output resistance Ro . We want to nd the conditions on A and Rout to satisfy the gain requirement.

A. Loaded Gain and Output Resistance Since this is a shunt-shunt feedback, it is convenient to convert the input voltage source into an input current source and compute the transimpedence Ro . We break the feedback loop in Fig. 3. First, we ignore all the capacitance to compute the DC gain. The DC transimpedence is given as Ro = The feedback factor is f = Thus the overall gain is Af b = Ro = (1 + f Ro )R1 A(R2 A(R2 RL )(R1 RL )(R1 R2 ) R2 ) + Rout + (R2 RL ) R2 R1 . (3) A(R2 RL )(R1 R2 ) . Rout + (R2 RL ) 1 . R2 (1)

(2)

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Fig. 3. diagram for gain and output resistance calculation Fig. 2. Ideal Op-Amp

Since 4.95 |Af b | 5.0, the rst term in (3) must be greater than 99%. This results in the following inequality. A 0.3564Rout + 594 (4)

Eq. 4 relates the open loop gain and output resistance of the op-amp. For example, if Rout = 10k, then A 4158.

B. Dominant Pole In order to satisfy the 3-dB bandwidth requirement, we want to compute the dominant pole of the close loop system and nd the conditions on the open loop gain A and bandwidth. This can be done by including capacitance in the previous calculation. Denote R3 = R2 RL = R2 R1 , C2 = C1 Cout . Eq. 3 becomes Af b = = A(R3 A(R3
1 sC2 )(R3 1 1 sC2 )(R3 sC1 )(R2 1 sC1 ) + (Rout + (R3 1 sC1 ) 1 sC2 )(R2 2 AR3 R2 /R1 1 sC1 )

1 R1 .

(5)

2 2 2 s2 (R3 C1 C2 Rout R2 ) + s(AR3 R2 C1 + Rout R2 R3 (C1 + C2 )) + (AR3 + Rout R2 + R3 R2 )

The dominant pole is given by p =

(6)

The second term in (6) must be greater than 99% which gives the following inequality. A 99 Rout (C1 + C2 ) 600Rout . R3 C1 R3 Af3dB 3.13 GHz (7)

Notice C1 = 1.6pF, C2 = C1 + Cout , we have the following requirement on the gain 3-dB frequency product: (8)

C. Phase Margin Two-stage amplier has two proximate dominant poles at the outputs of both stages. Proper compensation is needed to obtain a 60 phase margin. In our design, this is done by adding a capacitor C0 and a resistor R0 between the outputs of the two stages. Adding C0 splits the two low frequency poles. Inserting R0 introduces a left half plane (LHP) zero to help prevent the phase drop at low frequency. The exact value of the compensation capacitance is decided through simulations. The frequency of zero is nely tuned so that it is located near the second pole, and this gives rise to the best possible phase margin. Again, this is done through parametric simulation with Cadence.
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III. S IMPLE D IFFERENTIAL A MPLIFIER A. Design Summary The main circuitry of a simple two-stage amplier is shown in Fig. 4. The compensation circuitry consists of R0 and C0 . The gate of M2 and M3 are controlled by the bias circuitry, and the gate of M11 is connected to the output of common mode feedback circuitry. The bias currents for the rst and second stages are 0.6mA and 1.92mA respectively. The relatively high current is due to the high bandwidth requirement. This places a stringent condition on the amplier pole locations. The bias circuitry is shown in Fig. 5. A ideal current source is used. Wire vg2, vg26, and vg15 are connected to the gate of M2, M26, and M15. The common mode feedback circuit uses differential pairs, as shown in Fig. 6. The differential outputs of the amplier are connected to vg21 and vg24. Wire vg11 is routed to the gate of M11, which controls the tail current of the different pair at rst stage. The common mode voltage vcm is set to 0.9V using a ideal voltage source. Caution is needed in sizing transistors M21M24. Their overdrive voltages should be high enough such that the different pairs in common mode feedback circuitry remain on for the entire differential output range. In order to minimize the power dissipation, the bias current in common mode feedback is kept low by adjusting the transistor sizes.

Fig. 4. Main circuitry for simple differential pair

Fig. 5. Bias circuitry for simple differential pair

Fig. 6. Common mode feedback

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TABLE II
T RANSISTORS IN SIMPLE DIFFERENTIAL PAIR

Device M0,M1 M2,M3 M8,M9 M10 M11 M13 M14, M15 M16 M17 M18 M19 M21 M24 M25 M26, M27

W/L(m/m) 1.26/0.315 3.6/0.9 0.72/0.18 3.6/0.9 0.72/0.18 1/0.25 1/0.25 2/0.5 3.6/0.9 2/0.5 2/0.5 0.72/0.18 0.72/0.18 2/0.5

m 60 15 160 1 60 1 17 1 3 1 4 1 1 40

vsat (mV) 126.1 469.4 216.9 469.4 144.7 337.5 337.5 130.3 469.4 67.41 130.3 202.8 145.4 67.39

gm (mA/V) 8.969 1.739 14.1 0.1179 13.61 0.3625 6.121 0.1527 0.350 0.2076 0.588 0.082 0.2394 0.404

current (mA) 0.5992 0.5992 2.001 0.0406 1.198 0.1206 2.029 0.010 0.120 0.010 0.041 0.010 0.021 0.021

TABLE III
S IMULATION RESULT FOR TWO STRUCTURES

Open-loop gain Closed-loop gain Open-loop 3-dB BW Closed-loop 3-dB BW Diff. output swing HD3 Compensation CMFB Open-loop phase margin Power dissipation

Simple 621 4.95 2.969 MHz 9.724 MHz 1.6V 0.5% Ro = 200 Co = 580fF Vcm = 0.9 V 60.04 9.7832 mW

Cascode 1415 4.978 1.221 MHz 9.694 MHz 1.6V 0.17% Ro = 510 Co = 156fF Vcm = 0.95 V 60.03 8.9532 mW

B. Simulation The transistor sizes, DC current, and small signal parameters (gm , vsat ) are listed in Table II. The channel lengths of transistors on the second stage are minimized 0.18mbecause the load resistor dictates the gain on the second stage. The channel lengths of the transistors on the rst stage is determined by the tradeoff between gain and bandwidth (phase margin). Increasing channel length leads to higher gain but introduces more capacitance on the intermediate output. We will have more on these tradeoffs in the discussion section. The circuit was simulated and the result is reported in Table III. The output with a full 1.72V swing is shown in Fig. 7, when the input was a sinusoid at 2MHz. The 3rd harmonics distortion is obtained using the discrete Fourier transform. While all other requirements are satised, we only reach a close loop bandwidth of 9.724 MHz. We conceive that increasing the current on the second stage may lead to a better result, but we did not pursue further on the direction. Table III also includes the result of a design using telescopic cascode at the rst stage, which we will discuss in the next section.

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Fig. 7. Output Swing for simple differential pair

IV. C ASCODED D IFFERENTIAL A MPLIFIER In the previous design, we used a simple differential pair as the rst stage. Since the cascode structure can achieve higher gain, it is interesting to see if power dissipation can be improved by using this structure. We also implemented a cascode differential pair design. The main circuitry and bias circuitry are given in Fig. 8 and Fig. 9 respectively. In this high swing bias circuitry, transistor M31 is design to be in triode region, and it sets the Vds of M2 and M3. Bias vg20 needs to be appropriately chosen such that M19 and M20 work in saturation region. The corresponding transistor sizes and their operational conditions are listed in Table IV. The common mode feedback is the same as the previous one as shown in Fig. 6, so we choose not to list their transistors. The best result we got is presented in Table III. Although using a cascode at the rst stage helps enhance the gain substantially, the bandwidth becomes slight worst than our previous design. This is understandable since the dominant pole in the cascode design is located at lower frequency than the simple design.
TABLE IV
T RANSISTORS IN THE C ASCODED A MPLIFIER

Device M0,M1 M2,M3 M8,M9 M14, M15 M16 M17, M18 M19, M20 M29 M30, M33 M35 M37 M31 (triode) M32 M34

W/L(m/m) 0.72/0.18 0.72/0.18 0.72/0.18 0.72/0.18 2/0.5 0.72/0.18 0.72/0.18 1/18 0.72/0.18 0.72/0.18 4/1 0.72/0.18 16/1

m 16 40 160 40 1 20 20 1 2 2 1 4 1

vsat (mV) 148.9 186.8 216.5 204.9 130.3 250.1 126 396 250.7 118.1 424 186.7 196

gm (mA/V) 3.296 2.573 14.23 3.144 0.1527 1.818 4.036 0.1 0.1811 0.376 64.84 0.2569 0.221

current (mA) 0.303 0.303 2.02 0.5 0.010 0.303 0.303 0.028 0.030 0.027 0.027 0.03 0.028

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Fig. 8. Cascoded main circuitry

Fig. 9. Bias circuitry for the cascode

December 9, 2004

V. D ISCUSSION In this section we discuss the tradeoffs involved in adjusting the designing parameters such as the device sizes and bias current when the simple design in section III is used. The results are summarized in Table V. We use gm1 and gm2 to denote the transconductance of the rst and second stages. p1 and p2 indicate the dominant and secondary poles. Rout1 and Rout2 mean the output resistances of rst and second stages. We have: p1 1 gm2 Rout1 (Rout2 ||RL )C0 p2 gm2 Ci + CL

Gopen = gm1 Rout1 gm2 (Rout2 ||RL )

1) When the bias current on the rst stage ID1 increases, gm1 , p1 increases and Rout1 decreases. This results in PM , BW and Gclose . 2) When m0 (multiplier of transistor M0) increases, gm1 and Ci increase and p2 drops. Thus, PM , BW and Gclose . 3) Raising L0 (channel length of transistor M0) leads to larger Rout1 , Ci , and smaller p1 , p2 . Consequently, PM , BW and Gclose . 4) When the bias current on the second stage ID2 rises, gm2 and p2 increase, and p1 decreases. Hence, PM , BW , and Gclose . 5) Using a larger multiplier m8 on transistor M8 results in larger gm2 , Ci , CL . Therefore, BW , Gclose . The behavior of PM can be more complicated since gm2 and Ci cause opposite changes on phase margin. 6) When increase m8 (the channel length of M8), Rout2 , Ci , CL increase, and p2 decreases. As a result, PM , BW . Gclose changes slightly since Rout2 is in parallel with RL . Other parameters such as bias current and the sizes of transistors in CMFB circuitry has less effect on the performance of the amplier.
TABLE V
T RADEOFFS ON ADJUSTING DESIGNING PARAMETERS

Phase Margin Stage 1 ID1 m0 L0 ID2 m8 L8

Bandwidth

Gain

Stage 2

December 9, 2004